BUS LOADING METER USING DIGITAL ENVELOPE DETECTOR

Abstract: A bus loading meter for a controller area network (CAN) comprises a CAN transceiver (10) which converts an incoming CAN signal to a standard digital (TTL) signal. A counter (20) is provided for capturing the start-of-frame (SOF) and end-of-frame (EOF) of the signal by calculating the number of recessive bits present before a dominant bit (to determine the SOF) and after a dominant bit (to determine the acknowledgement slot) which is followed by seven successive recessive bits indicating the EOF. The meter further comprises a message frame converter (30) which is triggered by receipt of a start pulse from the counter (20) to start counting. Such counting is subsequently terminated on receipt of an end pulse from the counter (20) which resets the converter (30). A message envelope is formed at the output of the converter (30) which is supplied to a volt meter (40) providing a visual indication of the percentage bus loading. The converter (30) is controlled by a frequency switch (32) supplied by a crystal oscillator.

Description: BUS LOADING METER USING DIGITAL ENVELOPE DETECTOR This invention relates to bus loading meters for monitoring the loading of a data bus. It is known to make use of defined data transmission protocols for transmitting data along a data bus. For example, in the field of automotive control, it is known to utilise a Controller Area Network (CAN) using a method in which the start-of-fr-ame (SOF) is indicated by a dominant bit and the end-of-fr-ame (EOF) is indicated by seven recessive bits following an acknowledgement delimiter which is also a recessive bit. However the efficiency of such a network can be compromised by the bus loading, that is by the proportion of time for which the network is busy transmitting data. It has been shown that, for optimum efficiency, the bus loading should be maintained below 33%. As shown in Figure 1 , the latency of the network increases significantly beyond this point, with the result that there can be circumstances in which devices connected to the network may experience difficulty in transmitting signals over the network. If real time operation is to be achieved using such networks, developers of applications using CAN as a backbone need to take account of such latency. It is possible to obtain an indication of bus loading in a CAN by observing the data waveform on an oscilloscope, but this will not provide a direct indication of the percentage bus loading and is moreover an expensive option. An indication of bus loading may also be obtained directly through a calculation performed by a microprocessor, although development of appropriate systems would be costly. GB 2280574 A discloses local area network (LAN) monitoring circuitry for preventing unauthorised use of services. Such circuitry incorporates a data rate detector circuit for each user port which counts data pulses for each service in use during a preset clock period. If the count exceeds a predetermined value, the user is disconnected from that particular service. Such monitoring circuitry is not capable of providing a direct indication of the bus loading of a network such as a CAN network. SUBSTITUTE SHEET (RU.LE 25) It is an object of the invention to provide a bus loading meter which is capable of providing a direct indication of the bus loading of a CAN network at reasonable cost. The invention is defined by the accompanying claims. In order that the invention may be more fully understood, a preferred bus loading meter in accordance with the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a graph of the percentage bus loading of a CAN against latency; Figure 2 is an explanatory diagram; Figure 3 is a block diagram of the meter; Figure 4 is a timing diagram of the meter; Figure 5 is a circuit diagram of the meter; and Figure 6 is a table providing a comparison of the actual bus load and the readout from the meter. Before describing the preferred embodiment in detail, reference will first be made to the explanatory diagram of Figure 2 to illustrate the principle of operation of the meter. Figure 2 shows the form of a typical CAN message in which the start-of- frame (SOF) 2 is indicated by a dominant bit, and the end-of-frame (EOF) 4 is indicated by seven recessive bits, only the last two of which are shown. The meter detects the SOF 2 and the EOF 4, and calculates the average (mean) value of the message frame 6 in order to determine the percentage loading of the bus. Furthermore, using the mean value theorem, the average value of a square wave may be calculated from 1 [ (t2 - tl)] t3 - tl If y is set to 1 , then the formula becomes: t2 - tl mean = t3 - tl This mean value represents the percentage bus loading. Figure 3 is a block diagram of the bus loading meter which comprises a CAN transceiver 10 which converts the incoming CAN signal to a standard digital (TTL) signal, and a counter 20 for capturing the SOF and EOF of the signal by calculating the number of recessive bits present immediately before a dominant bit (to determine the SOF) and after a dominant bit (to determine the acknowledgement slot), which is followed by seven successive recessive bits indicating the EOF. The meter further comprises a message frame converter 30 which is triggered by receipt of a start pulse from the counter 20 to start counting, such counting being subsequently terminated on receipt of an end pulse from the counter 20 which resets the converter 30, forming a message envelope at the output of the converter 30 which is supplied to a voltmeter 40 providing a visual indication of the percentage bus loading. The converter 30 is controlled by a frequency switch 32 supplied with a 16 MHz (or 8 MHz) frequency signal by a crystal oscillator 34. The timing diagram of Figure 4 shows the relative timing of the signals in such a meter, the CAN signal being simplified with only a few bits being shown to indicate the SOF and EOF. The bus idle time is indicated by the "off period of the digital envelope. The circuit diagram of Figure 6 shows the various components of the meter in more detail, including the CAN transceiver 10, the 12-stage binary counter 20, the frequency switch 32, the EOF detector 35, the frame converter 30 and a power supply 36. The power supply 36 comprises a power FET Ql, a zener diode Dl, a 5v supply circuit 37, and associated capacitors Cl and C2 and resistors R5 and R6. A switch SI is provided for selection of a data rate of 125 Kbaud, 250 Kbaud or 500 Kbaud depending on the particular application. For each of these data rates the output of the counter 20 is supplied to the EOF detector 35 by a jumper Jl. Alternatively a data rate of 1 Mbaud may be selected if the output of the counter 20 is supplied to the EOF detector 35 by a jumper J2. The circuit as shown uses the 8 MHz output from the frequency switch 32, although it is also possible to make use of the 16 MHz output from the switch 32 in some applications. Considering, by way of example, the case of a 500 Kbps baud rate with 16 MHz count frequency, 1 bit contains 32 counts, so that there are 256 counts in 8 recessive bits. Since the circuit uses the leading edge of a signal to trigger the reset, 1 more count should be added, so that 257 counts are required. While no dominant bit is present, the counter 20 will keep counting (since the circuit is not reset). However, the counter 20 reaches 257, the output of the NAND gate of the detector 35 (initially at logic 1) is set to logic 0. This triggers the CLEAR of the J-K flip flop of the converter 30 and resets the output to 0, corresponding to the bus idle condition. When a dominant signal appears at the CAN_H and CAN_L pins of the transceiver 10, the RXD pin of the transceiver 10 is set to logic 0 and the resulting output signal is supplied to the J-input of the converter 30 by way of a Hex converter 11. The CLK input of counter 20 receives 8 MHz pulses from the frequency switch 32 SUBSTTTUTE SHEET (RULE 26) supplied with a frequency signal by the oscillator 34. When the dominant signal is detected, a clear signal is supplied to the CLR input of the counter 20 so as to reset the counter. The counter 20 then counts the number of pulses equivalent to the width of the 8 recessive bits until the EOF detector 35 detects a logic 1 at the pin Jl or J2 of the counter 20 causing a 0 to be applied to the CLR input of the converter 30 which in turn causes the Q output of the converter 30 to be set to logic 0. The Q output of the converter 30 will be set to logic 1 only when the J input is high, and the only condition that will cause the Q output to be set to logic 0 is when the CLR input of the converter 30 is set to 0. Thus only the EOF of a CAN signal will cause the Q output of the converter 30 to go low. Subsequently any dominant bit on the bus will trigger the Q output of the converter 30 to go high again. In this way the SOF and EOF are detected and the digital envelope is formed. Thus the average value measured at the output directly represents the percentage bus loading. For more precise and accurate reading, a digital multimeter is recommended since it has high impedance and is therefore highly precise under low voltage conditions (2 decimal places, 0.00 to 1.00 Volts). Although not shown in Figure 6, it is also possible to provide a potentiometer at the output of the circuit to enable accurate calibration. The above described circuit has been tested for accuracy, and the table of Figure 5 shows measured percentage bus loading values obtained by the bus loading meter as compared with the corresponding calculated values obtained from the time between two messages (cycle time) and the message frame time. For the purpose of the necessary measurements a single device was connected to the bus, in addition to the meter, and the device was used to permanently transmit a duplicate MAC ID check message. The message was simultaneously detected by an oscilloscope to enable the actual values to be calculated for the continually repeated message. The table indicates the high accuracy of the meter in measuring the percentage loading. The meter can be used in any CAN system or its application networks, such as DeviceNet, Smart Distributed System (SDS), CANKingdom, CANOpen or other proprietary systems. Depending on the application protocol, there is an upper boundary for the bus loading. When a network fails, it transmits no signal (0 percent) or repeatedly transmits a frame (80+%) or operates in some other condition that does not match the protocol specification. The resulting bus loading indicates that the bus has failed. It is envisaged, therefore, that such a meter may be used as an inexpensive check tool to check the bus loading of a vehicle, for example when the vehicle has failed on the road. If the bus loading is found to be different from the specified value, it can be concluded that at least one of the nodes has failed to function. The meter may also be used by a system developer to verify that there is no latency problem in the system design. The bus loading meter as described is particularly advantageous as it can be produced at low cost and so as to be made particularly compact. Furthermore an external voltage supply is optional as the supply voltage can be taken directly from the CAN system depending on the application network. The meter may be adapted to support a wide range of frequencies (up to 1 Mbps), and no programming of the device is required. Furthermore the meter is a virtual device which does not provide a load to the bus, that is it does not have any identifier and does not respond to any CAN signal. Finally it is contemplated that a variant of such a meter can be designed for use with networks other than CAN, such as, for example, Ethernet (Manchester Coding), J1850(PWM), VAN (enhanced Manchester Coding), ControlNet, Data highway, Profibus, World FIP, Fieldbus Foundation, ArcNet, LONWorks, ASI, InterBus, Hart, and any other network utilising serial protocols with SOF and EOF.

Claims: CLAIMS: 1. A bus loading meter for providing an indication of the data loading of a bus to which the meter is connected, the meter comprising start-of-frame detection means providing a first output in response to detection of the start of a frame of data transmitted on the bus, end-of-frame detection means for providing a second output in response to detection of the end of the frame of data transmitted on the bus, frame conversion means for producing a digital envelope of count signals repeated at constant frequency with the start and end of the envelope being determined by the first and second outputs of the detection means, and metering means for providing a visible output in response to the digital envelope indicative of the percentage of the total cycle time for which the bus is loaded with data. 2. A meter according to claim 1, wherein the start-of-frame detection means indicates the start of a frame on detection of a dominant bit. 3. A meter according to claim 1 or 2, wherein the end-of-frame detection means indicates the end of a frame on detection of a plurality of recessive bits following a dominant bit. 4. A meter according to claim 3, wherein said plurality of recessive bits consists of eight recessive bits. 5. A meter according to any preceding claim, wherein the frame conversion means comprises signal generating means for generating repetitive signals at constant frequency, counting means for counting said signals, and reset means for resetting the counting means to zero on receipt of the second output from the detection means. 6. A meter according to claim 5, wherein the reset means is adapted to initiate counting by the counting means on receipt of the first output from the detection means. 7. A meter according to claim 5 or 6, wherein the reset means is a flip-flop. SUBSTTTUTE SHEET (RUL£ 26) 8. A meter according to any preceding claim, wherein the metering means provides a digital readout of the percentage of the total cycle time for which the bus is loaded with data. 9. A meter according to any preceding claim, which is arranged to be connected to a controller area network (CAN). 10. A controller area network (CAN) incorporating a bus loading meter according to any preceding claim. SUBSTITUTE SHEET (RULE 25)

Inventors: MCLAUGHLIN RICHARD THOMAS, TANG KIAH HION, MCLAUGHLIN, RICHARD, THOMAS, TANG, KIAH, HION
Applicants: MCLAUGHLIN RICHARD THOMAS, TANG KIAH HION, UNIV WARWICK, MCLAUGHLIN, RICHARD, THOMAS, TANG, KIAH, HION, UNIVERSITY OF WARWICK
Application year: 1998
Main classification: H04L12
IPC codes: B60R16, H04L12