SYNCHRONOUS CLOCK GENERATOR INCLUDING DELAY-LOCKED LOOP

Abstract: A data and command latching circuit (60) includes a delay-locked loop (62) driven by a continuous reference clock signal (CCLKREF) that generates a delayed output clock signal having a delay controlled by the delay-locked loop. The latching circuit (60) also includes a variable delay circuit (64) external to the delay-locked loop (62) that is driven by a discontinuous reference clock signal (DCLKREF). Delay of the external delay circuit (64) is controlled by a control voltage output from the delay-locked loop, so that the delays of the external delay circuit are determined with reference to the continuous reference clock signal (CCLKREF). The delayed clock signals from the delay-locked loop activate control data latches (66) to latch control data (CD1-CDN) arriving at the latch circuit (60). The delayed signals from the variable delay circuit (64) activate data latches (68) to latch data (DA1-DAM) arriving at the latch circuit (60).

Description: SYNCHRONOUS CLOCK GENERATOR INCLUDING DELAY-LOCKED LOOP TECHNICAL FIELD The present invention relates to integrated circuit devices, and more particularly, to generation of clock signals in integrated circuit devices. BACKGROUND OF THE INVENTION Many high-speed integrated circuit devices, such as synchronous dynamic random access memories (SDRAM), rely upon clock signals to control the flow of commands, data, and addresses into, through, and out of the devices. Typically, operations are initiated at edges of the clock signals (i.e., transitions from high to low or low to high). To more precisely control the timing of operations within the device, each period of a clock signal is sometimes divided into subperiods so that certain operations do not begin until shortly after the clock edge. One method for controlling the timing of operations within a period of a clock signal generates phase-delayed versions of the clock signal. For example, to divide the clock period into four subperiods, phase delayed versions are produced that lag the clock signal by 90°, 180° and 270°, respectively. Edges of the phase-delayed clock signals provide signal transitions at the beginning or end of each subperiod that can be used to initiate operations. An example of such an approach is shown in Figures 1 and 2 where the timing of operations in a memory device 10 is defined by an externally provided reference control clock signal CCLKREF and an externally provided reference data clock signal DCLKREF. The reference clock signals CCLKREF, DCLKREF are generated in memory controller 11 and transmitted to the memory device 10 over a command clock bus and a data clock bus. The reference clock signals CCLKREF, DCLKREF have identical frequencies, although the reference control clock signal CCLKREF is a continuous signal and the reference data clock signal DCLKREF is a discontinuous signal, i.e., the reference data clock signal DCLKREF does not include a pulse for every clock period T, as shown in Figure 2. Although the reference clock signals CCLKREF, DCLKREF have equal frequencies, they may be phase shifted by a lag time TL upon arrival at the memory device 10 due to differences in propagation times, such as may be produced by routing differences between the command clock bus and the data clock bus. Control data CDl-CDN arrive at respective input terminals 12 substantially simultaneously with pulses of the reference control clock signal CCLKREF and are latched in respective control data latches 16. However, if the device attempts to latch the control data CDl-CDN immediately upon the edge of the reference clock signal CCLKREF, the control data may not have sufficient time to develop at the input terminal 12. For example, a voltage corresponding to a first logic state (e.g., a "0") at the input terminal 12 may not change to voltage corresponding to an opposite logic state (e.g., a "1") by the time the data are latched. To allow time for the control data CDl-CDN to develop fully at the input terminal 12, the control data are latched at a delayed time relative to the reference control clock signal CCLKREF. To provide a clock edge to trigger latching of the commands CDl-CDN at the delayed time ti, a delay circuit 18 delays the reference clock signal CCLKREF by a delay time TDI to produce a first delayed clock signal CCLKD. Edges of the first delayed clock signal CCLKD activate the control data latches to latch the control data CDl-CDN at time ti. Data DAI-DAM arrive at the data terminals 14 substantially simultaneously with the reference data clock signal DCLKREF, as shown in the fourth and fifth graphs of Figure 2. Respective data latches 20 latch the data DAI-DAM. As with the control data CDl-CDN, it is desirable that the data DAI-DAM be latched with a slight delay relative to transitions of the reference data clock DCLKREF to allow time for signal development at the data terminals 14. To provide a delayed clock edge, a delay block 22 delays the reference data clock signal DCLKREF to produce a phase-delayed data clock DCLK1 that is delayed relative to the reference data clock signal DCLKREF by the delay time TDI. For latching both control data CDl-CDN and data DAI-DAM, it is often desirable to allow some adjustment of the phase delay. For example, if the clock frequencies change, the duration of the subperiods will change correspondingly. Consequently, the delayed clocks CCLKD, DCLKD may not allow sufficient signal development time before latching the control data or data. Also, variations in transmission times of control data, data, or clock signals may cause shifts in arrival times of control data CDl-CDN or data DAI-DAM relative to the clock signals CCLKREF, DCLKREF of the memory device. One possible approach to producing a variable delay control clock CCLKD employs a delay-locked loop 38 driven by the reference command clock CCLKREF, as shown in Figure 3. The reference control clock signal CCLKREF is input to a conventional multiple output variable delay circuit 40 such as that described in Maneatis, "Low- Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE Journal of Solid-State Circuits 57(11): 1723-1732, November 1996. The delay circuit 40 is a known circuit that outputs multiple delayed signals CCLKl-CCLKN with increasing lags relative to the reference signal CCLKREF. The delays of the signals CCLKl-CCLKN are variable responsive to a control signal Nco N received at a control port 42. A feedback circuit 44 formed from a comparator 46 and an integrator 48 produces the control signal V CO N- The feedback circuit 44 receives the reference control clock signal CCLKREF at one input of the comparator 46 and receives one of the output signals CCLKN from the delay circuit 40 as a feedback signal at the other input of the comparator 46. The comparator 46 then outputs a compare signal VCOMP that is integrated by the integrator 48 to produce the control signal VCON- As is known, the control signal VCON will depend upon the relative phases of the reference control clock signal CCLKREF and the feedback signal CCLKN. If the feedback signal CCLKN leads the reference control clock signal CCLKREF, the control signal V C ON increases the delay of the delay circuit 40, thereby reducing the magnitude of the control signal V CO N until the feedback signal CCLKN is in phase with the reference signal CCLKREF. Similarly, if the feedback signal CCLK lags the reference signal CCLKREF, the control signal V CO N causes the delay circuit 40 to decrease the delay until the feedback voltage CCLKN is in phase with the reference voltage CCLKREF. A similar delay-locked loop 50 produces the delayed data clock signals DCLKl -DCLKN in response to the reference data clock signal DCLKREF. However, unlike the reference control clock signal CCLKREF, the reference data clock signal DCLKREF is discontinuous. Typically, the reference data clock signal DCLKREF arrives in bursts of clock pulses as a block of data is accessed. Between bursts, the reference data clock signal DCLKREF is relatively inactive such that the delay-locked loop 50 may lose its lock. Consequently, when bursts arrive, the delays of the delayed data clocks DCLKl - DCLKN may not be properly adjusted by the delay-locked loop 50 and the data DAI-DAM may have insufficient or excessive development time at the data bus before latching. SUMMARY OF THE INVENTION A high-speed memory device includes a clock generator that generates a plurality of clock signals in response to a reference clock signal at a reference frequency and a secondary clock signal at a secondary frequency substantially equal to the reference frequency. A first set of the clock signals is produced by a delay-locked loop in response to the reference clock signal. A delay block in the delay-locked loop receives the reference clock signal and produces a plurality of phase delayed signals at the clock frequency. One of the phase delayed signals is fed back to a comparator where the feedback signal is compared to the reference clock signal. The output of the comparator is then filtered and applied to a control input of the delay block to adjust the delay of the delay block. The delay-locked loop thus produces a plurality of output signals having fixed phases relative to the reference clock signal. In addition to the delay-locked loop, the clock generator also includes a secondary delay block having a clock input fed by the secondary clock signal. The control input of the secondary delay block receives the control signal from the comparator, such that the comparator output controls both of the delay blocks. The secondary delay block outputs a plurality of secondary delayed signals each having a respective delay relative to the secondary clock signal. By controlling the variable delays of the secondary delayed signals with the output of the delay-locked loop driven by the reference clock signal, the secondary delay signals can remain delay-locked even though the secondary clock signal is a discontinuous data clock signal. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a prior art memory system including a memory device and memory controller linked by control data and data buses. Figure 2 is a signal timing diagram showing timing of commands, data, and clock signals in the memory system of Figure 1. Figure 3 is a block diagram of a pair of delay-locked loops separately driven by control and data reference clock signals according to prior art. Figure 4 is a block diagram of a memory system according to the invention, including a memory device having a clock generator circuit where a delay-locked loop generates command clock signals in response to a reference clock signal and a variable delay block coupled to the delay-locked loop generates data clock signals in response to a reference data clock signal. Figure 5 is a block diagram of a computer system including the memory system of Figure 4. DETAILED DESCRIPTION OF THE INVENTION As shown in Figure 4, a memory system 52 includes a memory device 58 that operates under control of a memory controller 53. The memory controller 53 controls the memory device 58 through control data CDl-CDN and a reference clock signal CCLKREF, carried by a control data bus 54 and a clock bus 55, respectively. The memory controller 53 provides data DAI-DAM to the memory device 58, synchronously with a data clock signal DCLKREF over a data bus 56 and a data clock bus 57, respectively. The memory device 58 includes a latching circuit 60 that operates under control of a logic control circuit 61. The latching circuit 60 is formed from a delay-locked loop 62, a variable slave delay circuit 64, control data latches 66, and data latches 68. The control data latches 66 receive control data CDl-CDN from the control data bus 54 and the data latches 68 receive data DAI-DAM on the data bus 56. Additionally, the latching circuit 60 receives the reference control clock signal CCLKREF and the reference data clock signal DCLKREF from the respective clock buses 55, 57. As discussed above, the reference control clock signal CCLKREF is a continuous clock signal that drives the delay-locked loop 62 at a frequency fcc LK - Like the delay locked loop 38 described above with reference to Figure 3, the delay-locked loop 62 is formed from the variable delay circuit 40, comparator 46, and integrator 48. The variable delay circuit 40 is formed from a multitap variable delay line 70 of conventional construction and a selector switch 71. The delay circuit 40 provides several delayed clock signals CCLKl-CCLKN, each at the frequency fcc LK an each delayed by a respective time delay relative to the reference control clock signal CCLKREF. The selector switch 71, under control of the logic control circuit 61, couples one of the outputs of the variable delay line 70 to the control data latches form the delayed reference clock signal CCLKD. The logic controller 61 selects the switch position to select a delayed clock signal CCLKl-CCLKN that has a pulse delayed by approximately half of the data clock period relative to the control clock CCLKREF as the delayed clock signal CCLKD. The logic controller 61 is able to vary the switch position to accommodate changes in clock period that may occur as a result of operating frequency changes. As discussed above, the delayed reference clock signal CCLKD activates the control data latches 66, thereby latching control data CDl-CDN. The latched control data CDl-CDN is then made available to the logic control circuit 61. Unlike the circuit of Figure 3, the latching circuit 60 of Figure 4 does not employ a second delay-locked loop to produce the delayed data clock signal DCLKD. Instead, the reference data clock signal DCLKREF drives a slave delay circuit 64 formed from a second variable delay line 82 and a second selector switch 83. The delay of the second delay line 82 is controlled by applying the control signal V CO N from the integrator 48 to the control input 84 of the second delay line 82. The overall delay of the second delay line 82 is substantially equal to that of the variable delay line 70 of the delay-locked loop 62. However, the number of subperiods may differ between the delay lines 70, 82. The second selection switch 83 couples one of the delayed data clock signals DCLKl -DCLKN to the data latches 68 to produce the delayed data clock DCLKD, which is delayed relative to the data clock DCLKREF by the delay time TDI- The delayed data clock DCLKD activates the latches 68, thereby latching data DAI-DAM arriving at the input data bus 72. The latched data DAI-DAM is then made available by the latches 68 to a memory array 82 through read/write circuitry 84. One skilled in the art will recognize that the latching circuit 60 takes advantage of the matching clock periods T of the reference clock CCLKREF and the reference data clock DCLKREF to eliminate the delay-locked loop 50 of Figure 3. Because the delay time TDI of the delayed data clock DCLKD is controlled by the delay-locked loop 62 driven at the same frequency as the reference data clock DCLKREF, the delayed data clock DCLKD has a fixed phase relationship relative to the discontinuous reference data clock signal DCLKREF without requiring locking to the discontinuous reference data clock DCLKREF. By eliminating the delay-locked loop 50 of Figure 3 and establishing the delay time TDI with reference to the reference clock signal CCLKREF, the memory system 52 establishes the delay time T D ι with reference to a continuous signal (CCLKREF) rather than a discontinuous signal (DCLKREF). Consequently, the memory system 52 provides a continuously controlled time delay TDI while eliminating the difficulties in attempting to lock the delay-locked loop 50 to the discontinuous data clock signal DCLKREF. As noted above, the selector switches 71, 83 selectively couple the outputs of the variable delay circuits 40, 64 to the respective latches 66, 68. The positions of the selector switches 71, 83 are selected by the logic control circuit 61. Preferably, the selector switch position is programmed into the logic controller 61 when the memory device 58 is produced. However, where the memory device 58 may be used at more than one frequency or where the arrival times of data or commands may vary relative to their respective reference clocks CCLKREF, DCLKREF, the memory controller 53 may command the logic control circuit 61 to define a revised selection switch position. Thus, the use of a multi-tap variable delay line 70 in combination with the selector switches 71, 83 allows the memory device 58 to be "tuned" for varying operating conditions or frequencies. Figure 5 is a block diagram of a computer system 200 that contains the memory controller 53 and three of the memory devices 58 of Figure 4. The computer system 200 includes a processor 202 for performing computer functions such as executing software to perform desired calculations and tasks. The processor 202 also includes command, address and data buses 210 to activate the memory controller 53, thereby controlling reading from and writing to memory devices 58. One or more input devices 204, such as a keypad or a mouse, are coupled to the processor 202 and allow an operator to manually input data thereto. One or more output devices 206 are coupled to the processor 202 to display or otherwise output data generated by the processor 202. Examples of output devices include a printer and a video display unit. One or more data storage devices 208 are coupled to the processor to store data on or retrieve data from external storage media (not shown). Examples of storage devices 208 and storage media include drives that accept hard and floppy disks, tape cassettes and compact-disk read-only memories. While the invention has been described herein by way of exemplary embodiments, various modifications may be made without departing from the spirit and scope of the invention. For example, although the computer system 200 of Figure 5 contains only three memory devices 58, a larger or smaller number of memory devices 58 may be included within the computer system 200. Similarly, although the feedback portion of the delay-locked loop 62 is presented as containing only a comparator 46 and integrator 48, other circuitry may be used to control the variable delay lines 70, 82. Also, one skilled in the art will understand that other feedback elements may replace the comparator 46 and integrator 48. For example, the comparator 46 can be replaced by any know phase comparing or detecting circuit and the integrator 48 may be replaced by a conventional loop filter. Additionally, where the memory device 58 is operated such that control data and data are latched at a constant phase relative to the reference clocks CCLKREF, DCLKREF, the variable delay lines 70, 82 may have only one output. Also, although the combination of the delay-locked loop 62 and the additional variable delay block 82 are described herein as part of a latching circuit 60, a variety of other circuits may be developed incorporating this combination. Moreover, although the outputs of the variable delay lines 70, 82 are shown herein as driving the latches 66, 68, the outputs may also drive other circuitry in the memory device 58 to control timing of operations in addition to, or other than, latching. Further, although the exemplary embodiment described herein uses a delay locked loop 62 to lock to the reference clock signal CCLKREF, one skilled in the art could easily adapt the circuits described herein to employ a phase-locked loop for locking. Accordingly, the invention is not limited except as by the appended claims.

Claims: CLAIMS 1. A clock generator for generating a delayed secondary clock signal in response to a reference clock signal at a reference frequency and a secondary clock signal at a secondary frequency substantially equal to the reference frequency, comprising: a delay-locked loop, including: an reference clock terminal adapted to receive the reference clock signal; a comparator having a first input coupled to the reference clock terminal and adapted to receive the reference clock signal, and a second input receiving a delayed clock signal, the comparator being responsive to the reference clock signal and the delayed clock signal to output a compare signal on an output terminal indicative of a relationship between the reference clock signal and the delayed clock signal; and a primary variable delay block having a primary control input coupled to the comparator output terminal, a primary clock input coupled to the reference clock terminal and a first delay output coupled to the second input of the comparator, the primary variable delay block producing the delayed clock signal responsive to the reference clock signal with a first primary delay that varies responsive to the compare signal at the primary control input; a secondary clock terminal adapted to receive a secondary clock signal; and a secondary variable delay block having a secondary control input coupled to the comparator output terminal, a secondary clock input coupled to the secondary clock terminal, and a first secondary delay output, the secondary variable delay block producing a first secondary delayed signal, responsive to the secondary clock signal with a secondary delay that varies responsive to the compare signal at the secondary control input. 2. The clock generator of claim 1 wherein the primary variable delay block further includes a second delay output, the primary variable delay block having a second primary delay between the primary clock input and the second delay output that varies responsive to the compare signal at the primary control input, the second primary delay being different than the first primary delay. 3. The clock generator of claim 1 wherein the comparator includes a phase comparing circuit and an integrator. 4. The clock generator of claim 1 wherein the secondary variable delay block includes a second secondary delay output and wherein the secondary variable delay block is operative to provide a second secondary delay signal at the second secondary output, further including a selector switch having a switch output, a first input coupled to the first secondary delay output, and a second switch input coupled to the second secondary delay output. 5. A memory device adapted to receive data and commands at a reference frequency, the memory device comprising: a data input terminal; a command input terminal; a primary delay-locked loop, including: a reference clock terminal adapted to receive a reference clock signal at the reference clock frequency; a comparator having a first input terminal coupled to the reference clock terminal and adapted to receive the reference clock signal, a second input receiving a delayed clock signal, and the comparator being responsive to output a compare signal indicative of a relationship between the reference clock signal received at the first input and the delayed clock signal received at the second input terminal; and a primary variable delay block having a primary control input coupled to the comparator output, a primary clock input terminal coupled to the reference clock terminal and a first delay output coupled to the second input terminal of the comparator, the primary variable delay block producing the delayed clock signal responsive to the reference clock signal with a primary delay that varies responsive to the compare signal at the primary control input; a command latch having a clocking input coupled to a second delay output and a command input coupled to the command input terminal; a secondary clock terminal adapted to receive a secondary clock signal at a secondary clock frequency; a secondary delay block having a secondary control input terminal coupled to the comparator output, a secondary clock input coupled to the secondary clock terminal, and a secondary delay output, the secondary delay block producing a first secondary delayed signal at the secondary delay output at the secondary frequency with a secondary delay that varies responsive to the compare signal at the secondary control input; and a data latch having a data clocking input coupled to the first secondary delay output and a data input coupled to the data input terminal. 6. The memory device of claim 5 wherein the primary variable delay block further includes a second delay output that provides a second secondary delayed signal with a second primary delay between the primary clock input and the second delay output that varies responsive to the compare signal at the primary control input, the second primary delay being different than the first primary delay. 7. A latching circuit for latching data according to a discontinuous data clock signal having a clock frequency, comprising: a data clock terminal adapted to receive the data clock signal; a data terminal adapted to receive the data to be latched; a reference clock source operative to produce a reference clock signal at the frequency of the discontinuous clock signal; a delay locked loop having a reference signal input coupled to the reference clock source, a delay portion and a feedback portion, the feedback portion providing a feedback signal; a slave delay line having a clock input coupled to the data clock terminal and a control input coupled to the feedback portion, the slave delay line having a first slave output and being responsive to provide a delayed data clock signal at the first slave output in response to the data clock signal and the feedback signal; and a data latch having a data input coupled to the data terminal and a clocking input coupled to the first slave output, the data latch being responsive to latch data in response to the delayed data clock signals. 8. The latching circuit of claim 7 wherein the slave delay line includes a second slave output, further comprising a selector switch coupled between the slave delay line and the data latch, the selector switch having a first switch input coupled to the first slave output, a second switch input coupled to the second slave output, and a switch output coupled to the clocking input of the data latch. 9. A method of latching commands and data in a memory device responsive to respective command clock signals and data clock respective clock frequencies and clock phases, the method comprising the steps of: producing a delayed command clock signal in response to the command clock signal, the delayed command clock signal being delayed from the command clock signal by a command delay time; producing a delayed data clock signal in response to the data clock signal, the delayed data cock signal being delayed from the data clock signal by a data delay time; comparing a phase of the delayed command clock signal to the phase of the command clock signal; in response to the step of comparing the phases, adjusting the command delay time to produce an adjusted delayed command clock signal; in response to the step of comparing the phases, adjusting the data delay time to produce an adjusted delayed data clock signal; and latching the data in response to the adjusted delayed data clock signal. 10. The method of claim 9 wherein the step of producing a delayed data clock signal includes the step of providing d e data clock signal to a delay line and the step of adjusting the data delay time includes adjusting delay of the delay line.

Inventors: HARRISON RONNIE M, KEETH BRENT, HARRISON, RONNIE, M., KEETH, BRENT
Applicants: MICRON TECHNOLOGY INC, MICRON TECHNOLOGY, INC.
Application year: 1998
Main classification: H03L7
IPC codes: G06F1, G11C7, G11C11, H03L7