Motion vector detection apparatus

Abstract: In a motion vector detection apparatus, cascade-connected processor elements each calculates the absolute value of the difference between each of a plurality of pixels which compose a picture and a corresponding one of the same number of pixels included in a block, and also performs cumulative addition of the difference absolute values in the block. These operations are performed for each of the blocks within the predetermined search area. In said cascade-connected processor elements a difference absolute value calculation means is provided, wherein the processor elements have different bit with so as to have an improved dynamic range in the calculation.

Description: The present invention relates to an improvement of a motion vector detection apparatus which detects motion vectors used for the prediction in motion compensation prediction, which is one of the motion picture compression techniques. In transmitting and storing motion picture having a large amount of data, the motion picture compression techniques are inevitable to reduce the large amount of data. The motion picture compression techniques include a compression technique called motion compensation prediction. According to the motion compensation prediction, the level of data redundancy in motion picture is lowered in the direction of the time axis by extracting the displacement between two highly-correlated pictures, so as to compress the amount of data. The displacement between the highly-correlated pictures in the motion compensation is referred to as a motion vector, which is generally detected by a block matching method. The block matching method is briefly described with reference to Fig. 3. The block matching method is a method of evaluating the correlation between two pictures in predetermined block units. In Fig. 3, when a motion vector for a block (previous picture) 502 on Picture A 501 is detected, an evaluation value is calculated for each one of a plurality of blocks within a predetermined search area 504 on Picture B 503. As a result of the calculation, when block X 505 shown in Fig. 3 has turned out to have the best evaluation value (the highest correlation), the displacement from the position on Picture B 503 on which the previous picture block 502 is projected to block X 505 is detected as a motion vector 506. As the evaluation value indicative of the degree of correlation, a total sum is generally used which is obtained by cumulatively adding the absolute value of the difference between each of the pixels included in a block and a spatially corresponding one of the same number of pixels included in another block. As the evaluation value is smaller, the two blocks have a smaller difference, that is, higher correlation. As a conventional motion vector circuit for detecting motion vectors by the above-mentioned block matching method, there is a well-known technique disclosed in Japanese Laid-Open Patent Application No. 7-184210. Fig. 1 shows the entire structure of a motion vector detection apparatus, where one block includes 256 pixels, and each pixel has an 8-bit value. The apparatus shown in Fig. 1 includes cascade-connected processor elements (hereinafter PEs) 601 which are as many as the pixels included in one block: 256, a bus R 602 for transferring the pixel data of one block within the search area 504, a bus S 603 for transferring the pixel data of the previous picture block 502, a clock line 604 for supplying each of the PEs 601 with an operation clock, and a comparison means 605 for receiving an output of the PE at the final stage and comparing the previous value and the current value of the output. Fig. 4 show the conventional internal structure of each of the PEs 601 in the above-mentioned motion vector detection apparatus. The apparatus shown in Fig. 4 includes a difference absolute value calculator 610 for calculating the absolute value of the difference of the pixel data to be transferred via the bus R 602 and the bus S 603, an adder 611 for adding an output value of the difference absolute value calculator 610 and an output value of the PE at the previous stage together and for outputting the addition results to the PE at the following stage, a register 612 for storing the pixel data of the previous picture block to be transferred via the bus S 603, a pipeline register 613 for pipeline processing the calculations of the difference absolute value calculator 610 and the adder 611, and a pipeline register 614 for pipeline processing the calculation of the adder 611 of each of the PEs 601. The operations of the above-mentioned motion vector detection apparatus will be described as follows. The leading pixel data in the previous picture block 502 are stored in the register 612 and then transferred to the difference absolute value calculator 610 in the PE at the first stage (PE0). Also, the leading pixel data of a block (for example, block X 505) within the search area 504 are transferred to the difference absolute value calculator 610 in the PE at the first stage. The difference absolute value calculator 610 calculates the difference absolute value between the received two pixel data, and transfers the calculation results to the pipeline register 613. The adder 611 receives the difference absolute value from the register 613 and transfers it to the pipeline register 614 at the following stage, so that the difference absolute value is transferred to the PE at the next stage (PE1). Then, the second pixel data following the above-mentioned leading pixel data in the previous picture block 502 are transferred to the PE at the second stage (PE1). Also, the next pixel data in the block X 505 within the search area 504 are transferred to the PE at the second stage. In the PE at the second stage, the difference absolute value between these two pixel data is calculated and the results are stored in the pipeline register 613 in the same manner as in the PE at the first stage. Furthermore, in the PE at the second stage, the adder 611 adds the difference absolute value of the leading pixel data transferred from the PE at the first stage and the difference absolute value of the second pixel data together. The results are stored in the pipeline register 614 and then transferred to the PE at the third stage (PE2). These operations are repeated hereafter until the total sum of the difference absolute values between all the pixels in the previous picture block 502 and in block X 505 within the search area 504 is obtained in the PE at the final stage (PE255). These operations are sequentially performed for every block within the search area 504 although Fig. 3 shows only one other block Y 507. The comparison means 605 receives the total sum of the difference absolute values outputted from the PE at the final stage, compares the total sum in the previous block (for example, block X 505) and the total sum in the current block (for example, block Y507), and chooses the smaller of the two total sums. When the total sums of the difference absolute values in all the blocks within the search area 504 have been calculated and compared, the comparison means 605 obtains the smallest total sum, and outputs, as a motion vector, the displacement between the block having the smallest total sum and the previous picture block 502. However, the above-mentioned conventional motion vector detection apparatus has drawbacks of demanding huge power consumption because of a large amount of calculation processing needed and of requiring large circuit scales. These drawbacks will be detailed as follows. In Fig. 3, Picture A 501 is one of the 30 pictures displayed in one second and its size is 720 pixels×480 lines in the case of standard TV motion picture. Since the standard size of the previous picture block 502 is 16 pixels×16 lines in the motion vector detection used for the motion compensation prediction of the motion picture compression, the number of blocks included within the search area 504 amounts to 1024. Under these conditions, the number of blocks subject to the block matching amounts to 40,500 (=720×480×30÷16÷16) per second. A block matching performed for each block requires 262,144 (=1,024×16 ×16) times of calculations for the difference absolute values and the total sums. Consequently, the motion vector detection by the block matching method requires as many as 10,616,832,000 (=40,500 × 262,144) times of calculates per second for the difference absolute values and the total sums, which demands huge power consumption. In order to perform the calculations of the difference absolute values and the addition of these difference absolute values (total sum) with a high precision, it is necessary to make the difference absolute value calculator, the adder, the pipeline register, and other units in each PE have large bit widths. It is also inevitable to provide as many as 256 PEs each including these units, which leads to undesirable expansion of the circuit scales. The object of the present invention is to provide a motion vector detection apparatus which has reduced circuit scales and detects motion vectors with low power consumption. In order to achieve the object, the present invention has the features of claim 1. A motion vector detection apparatus of the present invention for detecting correlation between a picture consisting of a plurality of pixels and a plurality of blocks each consisting of the same number of pixels as the picture, the plurality of blocks being included within a predetermined search area containing a larger number of pixels than the picture is characterized by comprising: a plurality of PEs which are cascade-connected, each of the plurality of PEs calculating the difference absolute value between each of the plurality of pixels included in the picture and a corresponding one of pixels included in every one of the plurality of blocks, and performing cumulative addition of the difference absolute values for every one of the plurality of blocks sequentially, each of the plurality of PEs comprising: a difference absolute value calculation means for calculating the difference between each of the plurality pixels included in the picture and a corresponding one of pixels contained in one of the plurality of blocks, and further calculating the absolute value of the difference, so as to obtain a difference absolute value; an addition means for adding the difference absolute value obtained by the difference absolute value calculation means and an output of the PE at the previous stage together, and for transferring addition results to the PE at the next stage, and the addition means provided in the PE at the later stage of the plurality of PEs having a larger bit width. The above-mentioned motion vector detection apparatus of the present invention is also characterized in that the addition means provided in each of the plurality of PEs has the smallest bit width that does not cause an overflow. Since the addition means in each PE has a small bit width, the circuit scale can be small, which accordingly reduces the power consumption. The bit width of the addition means is set larger in a PE at a later stage. Consequently, the circuit scale can be efficiently reduced, and accordingly, the power consumption is reduced, as compared with the conventional apparatus where the bit width of the addition means at the final stage is adopted in the addition means at all the other stages. Fig. 1 shows the entire structure of the motion vector detection apparatus of the first embodiment of the present invention. Fig. 3 shows a diagram which illustrates the block matching method. Fig. 2 (a) shows the entire structure of the motion vector detection apparatus of the fifth embodiment of the present invention, and Fig. 8(b) shows a graph indicating the required number of bits in the adder in each PE. Fig. 4 shows the structure of a PE which is a component of a conventional motion vector detection apparatus. The preferred embodiment of the present invention will be described as follows with reference to the attached drawings. The present invention will be described based on Figs. 2 (a) and 2 (b). Fig. 2 (a) shows the entire structure of the motion vector detection apparatus of the present embodiment. In the structure, each block has 256 pixels, and there are cascade-connected 256 PEs 401, a bus R 402 and a bus S 403 for transferring data required for the calculation in each of the PEs 401, a clock line 404 for supplying each PE with an operation clock, and a comparison means 405 for receiving an output of the PE at the final stage. The present embodiment is characterized by the internal structure of each PE. All the addition means (the adder 611 shown in Fig. 4) in the PEs 401 have different bit widths from each other: the adder 611 in the PE at a later stage has a larger bit width. In other words, in each PE, the dynamic range of the data to be transferred from the adder 611 to the PE at the next stage is set larger in the PE at a later stage. Since the operations proceed normally unless there is an overflow, it is possible to modify the calculation precision in each PE. The dynamic range D of the adder 111 at each stage (i) when the pixel data have 8 bits can be expressed by the following equation: D = log 2 (255 (i+1) ) i = 0, 1, 2, ···, 255 Consequently, the smallest bit width of the data to be transferred to the PE in the following stage is an integer to which the value D is raised. The results are shown in Fig. 2 (b). In the present embodiment, nine different PEs which output data with a precision of 8, 9, 10, 11, 12, 13, 14, 15, and 16 bits, respectively, are realized by cascade-connecting them as shown in Fig. 2 (a). According to the above-mentioned structure, the number of bits in the adder and the pipeline register (the adder 611 and the pipeline register 614 shown in Fig. 4) can be reduced, as compared with the conventional structure. As a result, both the circuit scale and the power consumption can be reduced. In the present embodiment, as apparent from Fig. 2 (b), the circuit scales of the adder 611 and the pipeline register 614 in each PE can be about 90% of those of their equivalents in the conventional motion vector detection apparatus.

Claims: A motion vector detection apparatus for detecting correlation between a picture (502) consisting of a plurality of pixels and a plurality of blocks (505-507) each consisting of a same number of pixels as said picture (502), the plurality of blocks (505-507) being included within a predetermined search area (504) containing a larger number of pixels than said picture (502), said motion vector detection apparatus comprising: a plurality of processor elements (401) which are cascade-connected, each of said plurality of processor elements (401) calculating a difference absolute value between each of the plurality of pixels included in said picture (502) and a corresponding one of pixels included in every one of the plurality of blocks (505-507), and performing cumulative addition of the difference absolute values for every one of the plurality of blocks (505-507) sequentially, each of said plurality of processor elements (401) comprising: an difference absolute value calculation means (610) for calculating a difference between each of the plurality of pixels included in said picture (502) and a corresponding one of pixels contained in one of the plurality of blocks (505-507), and further calculating an absolute value of the difference, so as to obtain a difference absolute value, an addition means (611) for adding the difference absolute value obtained by said difference absolute value calculation means (610) and an output of a processor element (401) at a previous stage together, and for transferring addition results to a processor element (401) at a next stage, and said addition means (611) provided in a processor element (401) at a later stage of said plurality of processor elements (401) having a larger bit width. A motion vector detection apparatus according to claim 1, wherein said addition means (611) provided in each of said plurality of processor elements (401) has a smallest bit width that does not cause an overflow.

Inventors: AOKI KATSUJI, ARAKI TOSHIYUKI, AOKI, KATSUJI, ARAKI, TOSHIYUKI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1998
Main classification: G06T7
IPC codes: G06T7, H04N7