Simplified DPCC process for manufacturing FLOTOX EEPROM non-autoaligned semiconductor memory cells

Abstract: The invention relates to a simplified DPCC process for making non-self-aligned floating gate semiconductor memory cells of the FLOTOX EEPROM type as incorporated to a cell matrix having control circuitry associated therewith, wherein each cell has a selection transistor associated therewith, the process comprising at least the following steps: growing or depositing a gate dielectric layer of the selection transistor and the cell; tunnel masking to define the tunnel area with a dedicated etching step for cleaning the semiconductor surface; growing the tunnel oxide; depositing and doping the first polysilicon layer poly1. The process further comprises the following steps: poly1 masking to fully define the floating gate of the cell, the poly1 being removed from the area of the selection transistor during this step; depositing or growing the interpoly dielectric and forming tunnel oxide and interpoly dielectric; depositing or growing the interpoly dielectric and forming the overall gate dielectric of the selection transistor, which will therefore consist of the stacked interpoly dielectric and gate dielectric as previously grown or deposited; matrix masking to only remove interpoly dielectric from the circuitry; depositing and doping a second polysilicon layer poly2; masking the second later of polysilicon to define the control and selection gate; poly etching in the matrix as far down as the intermediate dielectric layer; poly etching in the circuitry the whole short-circuited poly1/poly2 stack.

Description: Field of the Invention This invention relates to a simplified DPCC (Double ShortCircuited Poly) process for making non-self-aligned semiconductor memory cells of the FLOTOX EEPROM type. In particular, the invention relates to a process as above for fabricating non-self-aligned floating gate semiconductor memory cells of the FLOTOX EEPROM type as incorporated to a cell matrix having control circuitry associated therewith, wherein a selection transistor is associated with each cell, the process comprising at least the following steps: growing or depositing a gate dielectric layer of the selection transistor and the cell; tunnel masking to define the tunnel area with a dedicated etching step for cleaning the semiconductor surface; growing the tunnel oxide; depositing and doping the first polysilicon layer poly1. Prior Art There exists a well-recognized demand, from the semiconductor integrated circuit market, for large capacity (>256 kbit) EEPROM devices. This implies increased effort on the part of the manufacturers of such circuits to provide circuit devices of an ever smaller size. A memory cell of the EEPROM type comprises a field-effect transistor having a floating gate which is coupled capacitively to a control gate terminal. This floating gate transistor is connected in series with a selection transistor. The floating gate comprises a first layer of polysilicon, referred to as the poly1, and the control gate comprises an overlying second layer of polysilicon, or poly2. Whereas in the memory cell the poly1 and poly2 layers are isolated by an intermediate dielectric (interpoly) layer 18, in the selection transistor these layers are in contact with each other. A DPCC process flow requires that the first polysilicon layer of the selection transistor associated with the memory cell be contacted, for otherwise, the selection transistor would be floating all the time. A special mask (matrix mask) is used for the purpose which allows the poly1 and poly2 layers to be short-circuited by removal of the intermediate dielectric layer from appropriate areas (every n bytes). In this way, the polyl layer of the selection transistor is forward biased through the contact with the poly2 layer. In a standard DPCC process, the control gate and select regions are defined by means of a special etching step, known as the self-aligned etch, whereby the stacked poly1/interpoly/poly2 layers are etched sequentially. For this reason, the distance of the selection transistor from the cell proper should be adequate to prevent short-circuiting of the respective gates, as may be due to polysilicon left over from the self-aligned etch. In theory, a non-self-aligned cell could be used to define the selection and control gate regions by specific etching steps, to eliminate the problem caused by poly residue. But in a DPCC process, such a solution would entail a serious loss in circuit area. A known prior art solution is disclosed in the US patent No. 5,404,037 that relates to an EEPROM cell with a drain diffused region self-aligned to the tunnel oxide region. As clearly shown in Figure 12 of this document, the interpoly ONO layer is self-aligned to the poly1 layer and the tunnel oxide layer. Moreover, a second and different gate oxide layer is deposited on the active area of the select transistor at the end of the Poly1 definition steps of the memory cell. A thermal oxide layer 41 is used as a spacer for the cell and then removed on the select transistor active area before a gate oxide deposition step. A second prior art document, the US patent No. 5,656,845, relates to an EEPROM memory cell formed with a silicon on insulator technology. The EEPROM cell disclosed in this patent includes a selection transistor 30 wherein an oxide layer 60 separates the transistor gate region 62 from the substrate channel 35. A thinner tunnel oxide layer 50 separates the floating gate region 48 of the cell from the substrate channel 38. Both oxide layers are formed by a single layer and a single deposition step as recited in the preamble of the enclosed claim 1. A third document, the EP application No. 0 422 606, relates to a Flotox type memory cell having a tunnel oxide 5 of the memory cell and a gate oxide 7 of the selection transistor obtained from a single oxide layer deposition as in the preamble of claim 1. All these prior art documents relate to self-aligned processes. In addition, a self-aligned process leaves ditches in the source line, which can result in serious malfunctioning of the memory device. The underlying technical problem of this invention is to provide a simplified DPCC process which has such features as to allow non-self-aligned semiconductor memory cells of the FLOTOX EEPROM type to be made, while keeping the cell bulk low. Summary of the Invention The concept behind this invention is one of incorporating steps of a non-self-aligned process to a DPCC process, thereby obviating the aforementioned drawbacks of self-aligned processes and the need for increased overall bulk of the cell. Based on this concept, the technical problem is solved by a process as previously indicated and defined in the appended claims The features and advantages of a process according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is an enlarged view from above illustrating schematically a portion of a semiconductor integrated circuit which includes at least one EEPROM cell formed by a DPCC process and having a selection transistor associated therewith. Figure 1A is an enlarged, vertical cross-section view, taken along line A-A', illustrating schematically the same integrated circuit portion. Figure 1B is an enlarged, vertical cross-section view, taken along line B-B', illustrating schematically the same integrated circuit portion. Figure 2 is an enlarged view from above illustrating schematically a portion of a semiconductor integrated circuit which includes at least one EEPROM cell formed in accordance with this invention and having a selection transistor associated therewith. Figure 2A is an enlarged, vertical cross-section view, taken along line A-A', illustrating schematically the same integrated circuit portion as in Figure 2. Figure 2B is an enlarged, vertical cross-section view, taken along line B-B', illustrating schematically the same integrated circuit portion as in Figure 2. Figure 3 is an enlarged view from above illustrating schematically a portion of a semiconductor integrated circuit which includes at least one EEPROM cell formed in accordance with a modification of this invention and having a selection transistor associated therewith. Figure 3A is an enlarged, vertical cross-section view, taken along line A-A', illustrating schematically the same integrated circuit portion as in Figure 3. Figure 3B is an enlarged, vertical cross-section view, taken along line B-B', illustrating schematically the same integrated circuit portion as in Figure 3. Detailed Description The process steps and structures described herein below do not reflect a complete fabricating process for integrated circuits. This invention can be practised in conjunction with such integrated circuit fabrication techniques as are commonly employed in this field, and only such common process steps will be discussed as are necessary to an understanding of the invention. Those drawing figures wherein cross-sections through portions of an integrated circuit being fabricated are shown, are not drawn to scale but rather to highlight major features of the invention. Referring to the figures of the accompanying drawings, the steps of the inventive process will now be described for forming non-self-aligned EEPROM cells 1 within a CMOS process of the DPCC type as provided for making the circuitry associated with the matrix. Referring in particular to the example of Figure 1, the structure of a conventional single EEPROM cell will be discussed first which comprises a field-effect transistor 2 having a floating gate 3 coupled capacitively to a control gate terminal 4. This floating gate transistor 2 is connected in series with a selection transistor 5. The floating gate 3, whereinto the charges are stored, is formed of a first poly1 layer, while the control gate 4 is formed of a second poly2 layer. A thin tunnel oxide layer 6, having a thickness of about 80 Ångströms is provided between the floating gate 3 and the semiconductor substrate 10. The electric charges are passed through this tunnel oxide 6 by Fowler-Nordheim effect during the step of programming the memory cell 1. A diffused area 8, formed in the substrate 10 and partway underlying the gate region, is intended for a capacitor implant effective to maintain electric continuity between the bit line selection transistor 5 and the tunnel area 6. Shown in Figure 1A is a cross-section taken through the cell and the selection transistor along a line A-A' drawn perpendicularly to the poly strips. As can be seen from this sectional view, the profile of the poly/interpoly/poly2/WSi2 stack is essentially vertical as a result of the self-aligned etch. Figure 1B is instead a cross-section taken through the cell and the selection transistor along a line B-B' drawn parallel to the poly strips. As can be appreciated from this sectional view, due to the matrix mask, the poly1 and poly2 layers of the selection transistor are short-circuited together, in this case at the area overlying the field oxide 9. The prior art memory cell considered here with reference to Figures 1, 1A and 1B is formed by a standard CMOS process of the DPCC type, wherein the following steps are carried out, starting with a substrate of the P type, as required for forming the EEPROM cells: masking for capacitor implantation and related implanting; growing or depositing the dielectric which is to form the gate dielectric for the selection transistor 5 and the cell 1; tunnel masking in order to define the tunnel area, with dedicated silicon surface cleaning etch; growing the tunnel oxide; depositing and doping the first polysilicon layer; poly1 masking to define the floating gate 3 in the perpendicular direction to the poly strips, i.e. along the direction A-A' in Figure 1A; forming the interpoly dielectric 18, either by deposition or growth thereof; matrix masking to remove the interpoly dielectric from the areas that are to be matrix and circuitry DPCC'ed; depositing the second layer of polysilicon, with relating doping, to simultaneously form the control gate 4 and the gate of the selection transistor; masking the second layer of polysilicon to define the control gate 4 and selection gate; etching the matrix and circuitry poly; masking for self-aligned etching; self-aligned matrix etching. The process is continued through further standard steps, not described herein because quite conventional. Advantageously in this invention, the standard DPCC process flow is modified to produce a non-self-aligned FLOTOX EEPROM cell. The invention principle applies equally well to two different variations, as described herein below. A first embodiment will now be described with joint reference to Figures 2, 2A and 2B. Figure 2 is a plan view of the layout of an EEPROM cell 20 according to the invention. In this case, the selection transistor 25 has for its gate dielectric the stack of the gate oxide and intermediate dielectric, and the gate only comprises the poly2 layer. From the sectional view in the direction A-A' shown in Figure 2A, it can be seen that the profile of the cell gate region is non-vertical, and exhibits a step 26 because the cell is not self-aligned. The poly2 layer of the cell 20 is definitely separated from the poly2 of the selection transistor 25 because the two gates locate at different levels (i.e. one above the other). This should avoid the risk of a short-circuit occurring due to any left-overs from the poly2 etch. The poly1 layer of the floating gate of the cell 20 locates at the same height as the poly2 of the selection transistor 25, but shorting problems can be ruled out between the two gates because the two poly's are separated by the interpoly dielectric. Shown in plan view in Figure 3 is the structure of a cell 30 formed according to a variation of this invention. Figure 3A is a cross-sectional view of the cell 30 and relating selection transistor, taken along the line A-A' perpendicularly to the poly strips. Figure 3B is a cross-sectional view of the cell 30 and relating selection transistor 35, taken along the line B-B', in a parallel direction to the poly strips. The shape of the gate of the selection transistor 35, the floating gate and the control gate of the cell 30 are identical with the previous embodiment. The gate oxide 31 of the selection transistor 35 is, however, thinner than in the previous case because it results from the superposition of the tunnel oxide and the interpoly dielectric 18. In either modified embodiments, the distance between the gate of the selection transistor and the control gate and the floating gate of the cell is less than in conventional solutions and affords savings in total area. The process flow according to the invention will now be described by drawing a parallel between the first and second embodiments, while pointing out the differences between these two process flows. In the first embodiment (Figures 2, 2A and 2B) the following steps are carried out: growing or depositing the gate dielectric of the selection transistor and the cell; tunnel masking to define the area where the tunnel oxide is to be grown; growing the tunnel oxide; depositing and doping the first layer of polysilicon; poly1 masking to fully define the floating gate of the cell; during this step, the poly1 is removed from the area of the selection transistor; the poly1 is obviously allowed to stay over the entire circuitry area; depositing or growing the interpoly dielectric 18 and forming the overall gate dielectric of the selection transistor, which will therefore consist of the stacked interpoly dielectric and gate dielectric as previously grown or deposited; matrix masking to only remove interpoly dielectric from the circuitry; depositing and doping the poly2 layer; masking the second layer of polysilicon to define the control and selection gate; poly etching in the matrix and the circuitry; this etching of the matrix poly is stopped upon meeting the intermediate dielectric layer, that is, only the poly2 is etched, whereas the whole short-circuited poly1/poly2 stack is etched in the circuitry. Advantageously, the self-aligned mask provided for in the prior art process is no longer used. Also, the self-aligned etch is no longer required, and the process can be continued in the standard fashion. As for the second embodiment (Figures 3, 3A and 3B), the inventive process comprises the following steps: growing or depositing the gate dielectric of the selection transistor and the cell; tunnel masking to define the regions where the gate dielectric is etched in the tunnel area and the channel area of the selection transistor; growing the tunnel oxide; depositing and doping the first layer of polysilicon; poly1 masking to fully define the floating gate of the cell; during this step, the poly1 is removed from the area of the selection transistor; of course, the poly1 is left over the entire circuitry area; depositing or growing the interpoly dielectric and forming the overall gate dielectric of the selection transistor, which will therefore consist of the stacked interpoly dielectric and the oxide as previously grown or deposited; matrix masking to only remove the interpoly dielectric from the circuitry; depositing and doping the poly2 layer; masking the second layer of polysilicon to define the control and selection gate; poly etching in the matrix and the circuitry; this matrix etch is stopped upon meeting the intermediate dielectric layer, that is, only the poly2 will be etched, whereas in the circuitry, the whole short-circuited poly1/poly2 stack is etched. The process flows proposed by this invention enable, through their modifications, the fabrication of EEPROM cells of the FLOTOX type, and afford the following major advantages over the state of the art: enhanced potential for scaling because of the reduced unit dimensions of the memory cell/selection transistor combination; reduced number of masks; for example, the mask for self-aligned etching in the matrix is eliminated; a simpler process, because such a complex step as the self-aligned etching step has been suppressed. These advantages outweigh any disadvantages from a possible increase in thickness of the gate dielectric of the selection transistor, with its attendant higher threshold. Thus, the invention allows non-self-aligned cells to be obtained within a DPCC process as provided for the circuitry associated with the matrix.

Claims: A short-circuited double polysilicon simplified (DPCC) process for manufacturing non-self-aligned floating gate semiconductor memory cells (20) of the FLOTOX EEPROM type that are integrated as a matrix of cells, the matrix having associated control circuitry, wherein each cell has an associated selection transistor (25), the process comprising at least the following steps: growing or depositing a gate dielectric layer of the selection transistor and the cell on a surface of a semiconductor substrate; tunnel masking to define a tunnel area with a dedicated etching step for cleaning the semiconductor surface; growing a tunnel oxide; depositing and doping a first polysilicon layer polyl characterized in that it further comprises the following steps: poly1 masking to fully define the floating gate of the cell, poly1 being removed only from the area of the selection transistor during this step; depositing or growing an interpoly dielectric layer (18) over said polyl layer and forming the overall gate dielectric of the selection transistor, which will therefore consist of the stacked interpoly dielectric and gate dielectric as previously grown or deposited; matrix masking to only remove interpoly dielectric from the control circuitry; depositing and doping a second polysilicon layer poly2; masking the second polysilicon layer poly2 to define the control gate of the memory cell (20) and the gate of the selection transistor (25); etching only the second polysilicon layer poly2 in the matrix, the etching being stopped upon meeting the intermediate dielectric layer; etching first and second polysilicon layers in the control circuitry to define a whole short- circuited poly1/poly2 stack. A simplified DPCC process for manufacturing non-self-aligned floating gate semiconductor memory cells according to claim 1, wherein the step of tunnel masking defines additionally the channel of the selection transistor such that the gate oxide layer of the selection transistor (25) comprises a tunnel oxide. A simplified DPCC process for manufacturing non-self-aligned floating gate semiconductor memory cells according to claim 1, wherein the poly2 layer of the memory cell (20) is defined at a different level from the poly2 layer of the selection transistor (25). A simplified DPCC process for manufacturing non-self-aligned floating gate semiconductor memory cells according to claim 1, wherein the polyl layer of the memory cell (20) is located at the same height of the poly2 layer of the selection transistor (25). A simplified DPCC process for manufacturing non-self-aligned floating gate semiconductor memory cells according to claim 1, wherein the profile of the memory cell (20) exhibits a step (26) between the poly2 layer and the poly1 layer.

Inventors: DALLA LIBERA GIOVANNA, VAJANA BRUNO, DALLA LIBERA, GIOVANNA, VAJANA, BRUNO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1998
Main classification: H01L27
IPC codes: H01L21