IRIS CONTROL

Abstract: In a method of generating an iris control signal (PIC, AIC), an image signal is subjected to a sample and hold operations (R1, SW, C) to obtain the iris control signal (PIC).

Description: Iris control. The invention relates to a method and circuit for iris control, and to a camera having such an iris control circuit. Cameras often have exchangeable lenses with an electrically controllable iris. There are two types of iris-controlled lenses: passively iris-controlled lenses, and actively iris-controlled lenses. A passively iris-controlled lens only comprises coils to realize the iris adaptation. All electronics is placed outside of the lens. An actively iris-controlled lens has electronics inside of the lens unit. Its iris is commonly controlled by applying a buffered sensor signal to the lens. In response, the lens controls its iris in such a manner, that the amplitude of the sensor signal has a fixed value. Back-light compensation is commonly realized by decreasing the size of the measurement window used for the exposure control. For example, the measurement window is reduced to a rectangular area or a vertical bar in the middle of the image. For lens control a same measurement window needs to be used to have the lens control correspond to the exposure control. In some prior art cameras, this is effected by applying the buffered sensor signal to the lens only during the measurement window. It is, inter alia, an object of the invention to obtain an improved iris control. To this end, a first aspect of the invention provides a method and circuit as defined in claims 1 and 4. A second aspect of the invention provides a camera as defined in claim 7. Advantageous embodiments are defined in the dependent claims. In a method of generating an iris control signal in accordance with a primary aspect of the invention, an image signal is subjected to a sample and hold operation to obtain the iris control signal. The invention is based on the recognition that most lenses have problems with control signals which are only available during a given window instead of continuously available. These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. The drawing shows an embodiment of a camera in accordance with the present invention. In the camera, a lens L has a controllable iris I. The iris is controlled by a passive iris control signal PIC or by an active iris control signal AIC. The image from the lens L is picked up by a sensor S. The image signal from the sensor S is buffered by a buffer B. The output signal of the sensor S or the buffer B is applied to image signal processing circuitry which is not shown as it is irrelevant to the present invention. In accordance with the present invention, the output signal from the buffer B is applied to an integrating sample and hold circuit comprising a resistor Rl between the buffer B and a first switch input 5, a controllable switch SW having the first switch input 5, another unconnected input 3, and a control input 9 receiving a back-light measurement window signal BL, and a capacitor C between the output 4 of the switch SW and ground. If the iris I is passively controlled, the passive iris control signal PIC could be taken from the output 4 is directly applied to the iris I. However, an emitter- follower is preferably inserted between the output 4 of the switch SW and the iris control signal input of the lens L. To this end, the circuit of Fig. 1 comprises an emitter-follower transistor Tl having a base connected to the output 4, a collector connected to a supply voltage, and an emitter connected to ground thru a resistor R2. The passive iris control signal PIC is then taken from the emitter of the transistor Tl. If the iris I is actively controlled, further elements are necessary as actively controlled irises commonly need an AC input signal AIC the peak-peak value of which corresponds to the amplitude of the DC signal PIC. So, the signal at the output of the emitter-follower Tl is chopped. A resistor R3 is connected between the emitter of the transistor Tl and the output supplying the active iris control signal AIC. The chopping action itself is carried out by a transistor T2 having a collector connected to the output supplying the active iris control signal AIC, a base receiving pulses HG at half the line frequency of the image signal thru a resistor R4, and an emitter which is connected to ground thru a diode D. Whenever the half line frequency pulse signal HG is positive, the transistor T2 connects the output supplying the iris control signal AIC to a DC level determined by the diode D. Obviously, the diode D may be absent in which case the DC level is zero. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the circuit claim enumerating several means, several of these means can be embodied by one and the same item of hardware.

Claims: CLAIMS: 1. A method of generating an iris control signal (PIC, AIC), comprising the steps of: furnishing (L, S, B) an image signal; and subjecting the image signal to a sample and hold operation (Rl, SW, C) to obtain the iris control signal (PIC). 2. A method as claimed in claim 1, wherein the iris control signal (PIC) is subjected to a DC-AC conversion (T2, R4, D) to obtain an AC iris control signal (AIC). 3. A method as claimed in claim 2, wherein the DC-AC conversion (T2, R4, D) is controlled by a signal (HG) at half the line frequency of the image signal. 4. A circuit for generating an iris control signal (PIC, AIC), comprising: means for furnishing (L, S, B) an image signal; and means for subjecting the image signal to a sample and hold operation (Rl, SW, C) to obtain the iris control signal (PIC). 5. A circuit as claimed in claim 4, further comprising means for subjecting the iris control signal (PIC) to a DC-AC conversion (T2, R4, D) to obtain an AC iris control signal (AIC). 6. A circuit as claimed in claim 4, wherein the DC-AC conversion (T2, R4, D) is controlled by a signal (HG) at half the line frequency of the image signal. 7. A camera comprising: a lens (L) having a controllable iris (I) coupled to receive an iris control signal (PIC, AIC); a sensor (S) for furnishing an image signal; and means for subjecting the image signal to a sample and hold operation (Rl , SW, C) to obtain the iris control signal (PIC). 8. A camera as claimed in claim 7, further comprising means for subjecting the iris control signal (PIC) to a DC- AC conversion (T2, R4, D) to obtain an AC iris control signal (AIC). 9. A camera as claimed in claim 8, wherein the DC-AC conversion (T2, R4, D) is controlled by a signal (HG) at half the line frequency of the image signal.

Inventors: NOOIJEN JOHANNES BERNARDUS MAR, NOOIJEN, JOHANNES, BERNARDUS, MARIA
Applicants: KONINKL PHILIPS ELECTRONICS NV, PHILIPS SVENSKA AB, KONINKLIJKE PHILIPS ELECTRONICS N.V., PHILIPS AB
Application year: 1998
Main classification: G03B7
IPC codes: G03B7, H04N5