Branch prediction in computer system

Abstract: Branch predictions are adjusted by interrupting a central processing unit (12) and observing a pending branch instruction. An interrupt is generated using a counter (40), timer (42), or software-based interrupt (36). The interrupt causes a prediction adjustment routine to execute, which in turn determines whether a pending branch instruction will branch. The actual branch behaviour of the branch instruction is compared to the predicted branch behaviour of the branch instruction, and the prediction is adjusted accordingly based on the accuracy of the prediction and previous branch behaviour. After the prediction has been adjusted (if necessary), execution returns to the program that contains the branch instruction that was evaluated.

Description: The present invention relates to the execution of computer instructions in a computer system. More specifically, the present invention relates to a method and apparatus for generating a branch prediction for a computer branch instruction by interrupting a processor and observing a pending branch instruction. Early computer systems serially executed one computer instruction at a time, and did not start executing an instruction until the previous instruction had completed. As the art of computer design progressed, computer designers began to incorporate various types of parallelism into computer systems. One type of parallelism is pipelining. Pipelining breaks down the execution of a computer instruction into various steps, and processes multiple instructions simultaneously by overlapping these steps. Another type of parallelism is superscaling. Superscaling uses multiple execution units to process separate instructions simultaneously. Parallel design techniques create problems for branch instructions. Often, when a branch instruction is executed, the condition that the branch instruction must test has not yet been determined. Early computer systems simply halted execution of the branch instruction (and subsequent instructions) until the condition was determined. However, this hurts performance. In a pipelined computer, often the pipeline must be emptied before the condition can be determined, which limits the benefits achieved by pipelining. To address this problem, computer designers started to include mechanisms that predict branch behavior. When a branch instruction is encountered, the branch behavior of the branch instruction is predicted. Later, when the condition can be evaluated, the prediction is also evaluated to determine if it is correct. If the prediction is correct, execution continues and the advantages achieved by parallel execution are preserved. If the prediction is incorrect, instructions that were provisionally executed must be purged from the pipeline and the instructions from the correct branch must he executed. However, the penalty for an incorrect branch is typically not any worse than halting execution and waiting for the condition to be determined. The performance gains achieved by branch prediction are, of course, strongly related to the accuracy of the prediction. Accordingly, many techniques have been developed to provide accurate branch predictions. One of the earliest techniques was to simply predict that a branch is always taken. Statistically, most branches are taken, so this technique proved somewhat successful. A similar technique predicts that backward branches are always taken, and forward branches are never taken. Another technique uses an address table of addresses to which branch instructions recently branched. Typically, the table consists of an associative memory having 4 to 8 entries. If an address in a branch instruction also appeared in the table, then that address is used as the predicted execution path. A more sophisticated approach was disclosed by James E. Smith in U.S. Patent No. 4,370,711. Smith disclosed a random access memory (RAM) having, for example, 16 entries, each containing a two bit count capable of assuming the values +1, 0, -1, and -2. A hash mechanism transforms the branch instruction address into a four bit address that accesses the RAM. If the value stored in an entry associated with a branch instruction is + 1 or 0, then the branch is predicted as taken. Otherwise, the prediction is that the branch is not taken. After the branch instruction is executed, if it is taken, the count memory entry is incremented up to a limit of + 1. If it is not taken, the count memory address is decremented down to a limit of-2. The prediction scheme disclosed by Smith incorporates branch history in the formulation of the branch prediction. For example, if the branch has been taken several times, it must be not taken twice in a row to change the prediction. Many computer systems use some variation of this scheme, with a table that stores a prediction and a hash function that associates a branch instruction with a prediction. Another approach is disclosed by Hanan Potash in U.S. Patent No. 4,435,756. Potash discloses encoding a branch prediction in each branch instruction based on whether it is probable that the branch condition will be evaluated as being true or false. In another embodiment, Potash discloses encoding branch history and a branch prediction in a branch instruction. In this embodiment, if the prediction proves to be incorrect two times in a row, the prediction is changed, which requires encoding a new prediction into the branch instruction and writing the branch instruction back to memory. Note that the branch instruction must also be written back to memory whenever branch history changes, even if the prediction does not change. This creates a large amount of write data, which lowers I/O throughput. For example, a branch instruction that alternates between two branch paths must be written back to memory every time it is executed. Conte T M et al: "Hardware-Based Profiling: an effective technique for profile-driven optimization" International Journal of Parallel Programming, vol. 24, no. 2, 1 April 1996, pages 187-206, XP000582805 discloses a prior art compile-run-recompile sequence with a compile-use-recompile sequence, in which a program is executed with instrumentation instructions inserted to monitor branching behavior. The program is executed, and the branching behavior is observed and collected, and is used when the program is recompiled. Conte et al propose an improvement by using branching behavior tracking registers available in many modern CPUs. As a result, the program does not need to be compiled using instrumentation instructions, and the "first" compilation of the program is much faster. Both the prior art and the technique disclosed by Conte et al require that collected information about branching behavior be used as input to a new compilation of the program. Computer systems manufactured by Hewlett-Packard Company have used two types of branch prediction; a hardware-based branch prediction scheme that uses a prediction table to store dynamically generated branch predictions close to the CPU, and a software-based branch prediction scheme that encodes static branch predictions into each branch instruction when a computer program is compiled. With software-based branch prediction, the prediction is encoded in the branch instruction based on the order of the operands in the compare function. For example, consider the following compare and branch (COMB) instructions: COMB,< R5,R3, Address, and COMB, > = R3,R5, Address. The branch prediction encoded in the first instruction is the opposite of the branch prediction encoded in the second instruction, even though the instructions are logically identical. To generate effective predictions, it is necessary to perform a "profile-based optimization" (PBO) run, wherein branching behavior is observed while an application is executing in a typical computing environment. After the PBO run is complete, the user's applications are recompiled to incorporate updated branch predictions based on branching behavior observed during the PBO run. The advantages of software-based branch prediction are that the prediction can be based on behavior observed over an extended period, not just the last branch or two. Also, software-based branch prediction requires less complex, less expensive hardware. It is much simpler to design hardware that only implements a branch prediction, compared to hardware that must also judge the accuracy of predictions and update predictions accordingly. The disadvantages of software-based branch prediction are that the prediction is static and does not adapt to changes in program data or the computing environment. Once the prediction is compiled into the branch instruction, it is not changed. Also. customers do not like to perform the PBO run, which is needed to achieve high levels of branch prediction performance. The advantages of hardware-based branch prediction are that it is completely transparent to the user of the computer system, it adapts dynamically to changes in the computing environments that may affect branching (such as changes in information stored in databases), and it tends to be very accurate when the prediction table is large or a prediction can be associated with each instruction, as disclosed by Potash. The disadvantages of hardware-based branch prediction are that it is expensive to implement, and to date, not many computers are configured to use hardware branch prediction. To increase efficiency and reduce the number of logic gates, prediction tables typically store a limited number of branch instructions and often store none or only a portion of the address of a branch instruction. This can cause the prediction scheme to be overwhelmed by aliasing, thereby causing a prediction to he generated that is not based on the actual branch instruction being executed. Aliasing can be a significant problem for programs having many frequently executed branch instructions, such as database programs. The present invention seeks to provide an improved computer system. According to an aspect of the present invention there is provided a method of adjusting a branch prediction as specified in claim 1. According to another aspect of the present invention there is provided a central processing system as specified in claim 9. The preferred embodiment can provide a method and apparatus for dynamically adjusting the branch prediction associated with a branch instruction by periodically interrupting the central processing unit of a computer and executing a prediction adjustment routine that observes a pending branch instruction. If a branch instruction is not pending, the prediction adjustment routine ends and execution of the interrupted instruction stream resumes. If a branch instruction is pending, the branch instruction is evaluated and compared with a branch prediction associated with the branch instruction. If the prediction is correct, execution of the interrupted instruction stream is resumed. If the prediction is not correct, then the prediction is evaluated to determine whether it should be changed. In one embodiment, prior branch history of the branch instruction is also used to determine whether the branch prediction should be changed. In another example, the branch prediction is toggled if incorrect. An embodiment of the present invention is described below, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a simplified block diagram of a computer system. Figure 2 is a block diagram of a portion of a CPU that is part of the computer system shown in Figure 1. Figure 3 is a flow chart of a preferred embodiment of interrupt-based prediction adjustment routine. Figure 1 is a simplified block diagram of a computer system 10. Computer system 10 includes a central processing unit (CPU) 12, level 1 (L1) cache 14, level 2 (L2) cache 16, main memory 18, permanent storage disk 20, and virtual memory storage disk 22. In many computer systems, permanent storage disk 20 and virtual memory storage disk 22 are embodied on the same physical hard drive. Figure 1 illustrates the various locations at which program code is stored before, during, and after execution. When a program is first executed, the program code is retrieved from permanent storage disk 20 and stored in main memory 18. As portions of the program code are executed, those portions are stored in L2 cache 16 and L1 cache 14. As is known in the art, L1 cache 14 is typically implemented as very fast memory that is close to CPU 12. Often it exists on the same integrated circuit as the CPU. L2 cache 16 is somewhat slower and larger. Finally main memory 18 is very large, and slower than 1.2 cache memory 16. As programs and data are stored in main memory 18, the size of the programs and data may exceed the physical size of memory 18. When this happens, memory pages from memory 18 are stored on virtual memory storage disk 22, thereby making additional memory space available in memory 18. When a program references a memory page that has been stored on disk 22, the memory page is retrieved, and if necessary, other pages are swapped out to disk 22. Figure 1 illustrates a typical computer architecture that is common in the field of computing. The preferred embodiment is described below with reference to Figure 1, but those skilled in the art will recognize that it may be implemented on a variety of other computer architectures, such as computer systems that have fewer or additional cache memories, computers with multiple CPUs, etc. Figure 2 is a block diagram of a portion of CPU 12 of Figure 1. CPU 12 includes an arithmetic logic unit (ALU) 24, a program counter (PC) 26, a status register (STR) 27, and instruction register (IR) 28, a register stack 30, last-in first-out (LIFO) stack 32, and interrupt unit 34. ALU 24 performs various mathematical operations, such as adding, subtracting, multiplying, shifting, comparing, and the like. Registers 30 store data that is used by ALU 24. PC 26 stores an address that references the memory location of the current instruction being executed, IR 28 stores the current instruction being executed, LIFO stack 32 provides temporary storage to CPU 12, and interrupt unit 34 processes interrupts. Status register 27 includes status bits that control and determine various modes of CPU 12. Interrupt unit 34 responds to interrupts, and is also capable of generating interrupts. For example, IRQ line 36 represents externally generated hardware interrupts, such as a network adaptor asserting a hardware interrupt on a bus. Break instruction 38 represents software interrupts, such as BREAK or TRAP instructions that may be placed in the program code. Timer 42 represents interrupts that are generated based on a timer value, such as a real time clock that interrupts CPU 12 at a periodic interval. Finally, instruction counter 40 represents interrupts that are generated after a certain number of instructions. The values used by instruction counter 40 and timer 42 may be altered by the operating system. When interrupt unit 34 processes an interrupt, the values stored in registers 30, PC 26, STR 27, and IR 28 are stored on LIFO stack 32. This is depicted in Figure 2 by showing each of these values. along with the label "(Int)", stored in LIFO stack 32. After these values are stored on LIFO stack 32, an interrupt service routine (ISR) associated with the particular interrupt being processed is executed. After the ISR has been processed, the values are removed from LIFO stack 32 and restored to their original locations. While the ISR is executing, it has access to the values stored on LIFO stack 32. Accordingly, the ISR can examine the instruction that was being executed when the interrupt occurred, the address at which that instruction is stored in main memory, and the contents of the registers at the time the interrupt occurred. Figures 1 and 2 show a CPU architecture that is much simpler than modern CPU architectures known in the art of computing. Modern CPUs include multiple execution units, pipelines, circuitry to support out-of-order execution, and the like. However, the architecture shown in Figures 1 and 2 is sufficient to illustrate the preferred embodiment. While the present invention will be described below with reference to Figures 1 and 2. those skilled in the art will recognise that he described embodiment may be implemented on a variety of other computer architectures. The preferred embodiment provides a method and apparatus for dynamically adjusting branch predictions. As used herein, the term "branch instruction" generally applies to branch instructions that branch based on a condition. Of course. if the branch instruction is an unconditional branch instruction that always branches to the same location, there is no need to predict whether the branch will be taken. On the other hand, many computer systems manage certain aspects of execution of unconditional branch instructions (for example, keeping the pipeline full) within a general branch prediction framework. Therefore, predicting branch behaviour of unconditional branch instructions is contemplated herein. Figure 3 is a flow chart of a preferred embodiment of interrupt-based prediction adjustment routine 44. While routine 44 may be implemented in software as an ISR, this embodiment may also be implemented partially or completely in hardware. At block 46, the routine 44 is started. With reference to Figure 2, there are several methods that may be used to generate an interrupt to start routine 44. Timer 42 may be configured to generate an interrupt at a periodic interval. Alternatively, instruction counter 40 may be configured to generate an interrupt after a certain number of instructions. Both the time interval and the instruction count can be varied on a random basis to ensure that the processor is interrupted at different locations in program code. One advantage of the instruction counter over the timer is that for some computer architectures, the instruction counter may produce a more even distribution of prediction evaluations across all branch instructions. For example, in some implementations of the PA-RISC architecture, an interrupt at a level appropriate for use with the present invention is deferred until the instruction being executed is completed, then the interrupt is serviced. Consider a load instruction that often generates a cache miss and takes a relatively large amount of time to complete. If a timer generates the interrupt, a branch instruction immediately following a load instruction will be evaluated more frequently than a branch instruction immediately following an add instruction because the total time required to execute both the branch instruction and the load instruction is dominated by the cache miss. Therefore there is an increased probability that a timer interrupt will occur during a cache miss, and the interrupt will be processed at the next instruction. The instruction counter does not suffer from this problem. While relatively frequent interrupts lead to a higher level of prediction accuracy, frequent interrupts also incur higher overhead. It has been found that an interrupt interval of approximately 0.01 seconds or an instruction count of approximately one interrupt every 15 million instructions produces relatively high prediction accuracy, while incurring minimal overhead. Another method of generating the interrupt that launches routine 44 is to replace various condition-based branch instructions with BREAK instructions. When a BREAK instruction is encountered by CPU 12, interrupt unit 34 launches routine 44, which replaces the BREAK instruction with the proper branch instruction, and evaluates the branch instruction as described below. Using this method, the branch instruction can initially be replaced by a BREAK instruction by a separate interrupt service routine, routine 44, or some other program. Finally, in another embodiment CPU 12 of Figure 2 may be configured to selectively treat branch instructions as BREAK instructions based on a status flag in status register 27. In this embodiment, whenever the status flag is set, a branch instruction generates a software interrupt that is serviced by routine 44. This embodiment may also be used in conjunction with either instruction counter 40 or timer 42 to set the status flag after a certain interval or a certain number of instructions, thereby generating a software interrupt at the first branch instruction encountered after a certain time interval or instruction count, as described above. Returning to Figure 3, after routine 44 is started at block 46, decision block 48 determines whether the instruction pending is a branch instruction. Note that block 48 is not necessary if CPU 12 is configured to generate in interrupt when a branch instruction is pending, as described above. However, when used in a computer system that is not capable of generating an interrupt based on a branch instruction, step 48 is necessary to determine whether a condition-based branch instruction has been "caught" by the interrupt. In a typical mix of computer instructions, condition-based branch instructions comprise approximately 15% of all instructions. If the pending instruction is not a condition-based branch instruction, routine 44 branches to block 50, interrupt-based prediction adjustment routine 44 is ended, and program execution resumes at the point where the original program code was interrupted However, if the pending instruction is a branch instruction, block 52 evaluates the instruction and determines whether the branch will be taken. With reference to Figure 2, this can be done be examining the values stored on LIFO stack 32 as described above. Of course, those skilled in the art will recognize how to evaluate a pending branch instruction in a particular computer system when this embodiment is adapted for use in that computer system. In another embodiment, decision block 48 first determines whether the pending instruction is a branch instruction. If it is a branch instruction, the "yes" branch is taken to block 52 as described above. If it is not a branch instruction, block 48 then executes instructions by emulating instructions until a branch instruction is reached. In comparing this method to the method described above, there are tradeoffs that must be assessed in determining which method is more efficient. As noted above, approximately 15% of instructions are branch instruction, so on average, an interrupt will catch a branch instruction once every six or seven interrupts. On the other hand, the performance of emulation is between 20 and 100 times worse than direct instruction execution, and in a typical instruction mix a branch instruction is encountered, on average, once every five or six instructions. Therefore, on average, several instructions must be emulated before a branch instruction is reached. Of course, every interrupt eventually results in the evaluation of a branch instruction. Note that the branch instruction itself does not have to be emulated because it can be executed directly after routine 44 ends. Whether an implementor decides to emulate instructions to reach a branch instruction, or interrupt until a branch instruction is "caught" will depend on several factors, such as the efficiency of routine 44, the efficiency of emulation, and the ratio of branch instructions to other instructions in the instruction mix. In certain environments it may be desirable to use both methods on the same system based on the mix of programs that are executing, and such use is contemplated. After the branch condition is evaluated at block 52, the branch prediction is evaluated at block 54. In computer systems that execute instructions in accordance with the Hewlett-Packard PA-RISC instruction set, a branch prediction is encoded in a branch instruction based on the order of the operands. Decision block 56 determines whether the branch prediction is correct by comparing the branch prediction with the actual branch that must he taken in accordance with the evaluation of the branch prediction performed at block 52. If the prediction is correct, routine 56 branches to block 58, which updates branch history, and then routine 56 ends at block 50. If the branch is incorrect, block 60 updates the branch history and updates the prediction based on branch history. Branch history is used to provide a more accurate branch prediction. However, it is not required by this embodiment. For example, the branch prediction may simply be changed when it is incorrect. All that is needed is the prediction from block 54 (which may be encoded in the branch instruction), and the evaluation of the branch condition at block 52. One simple branch history algorithm simply changes a prediction when the prediction is wrong after two successive evaluations. To illustrate how branch history can increase branch prediction, consider a program loop that loops 100 times, then does not loop. Without branch history, there is a 1 in 100 chance that the looping branch instruction will be evaluated at the last iteration of the loop, thereby changing the prediction from "branch" to "no branch" which is not a good prediction for the branch instruction. With a branch history algorithm as described immediately above, the looping branch instruction must be evaluated at the last iteration of the loop twice in a row to change the prediction. The chances of this happening are 1 in 10,000. Therefore, the accuracy of the prediction associated with the looping branch instruction is increased by branch history. Evidently, to include a branch history when modifying a prediction, the branch history must be saved. Encoding branch history in the branch instruction was disclosed by Hanan Potash in U.S. Patent No. 4,435,756. However, when branch history is stored in the branch instruction, the branch instruction must be written back to memory whenever the branch is evaluated, even when the prediction is correct. While the Hewlett-Packard PA-RISC instruction set defines a method for encoding a branch prediction in an instruction, it does not define a method for encoding branch history within a branch instruction. In one embodiment branch predictions are stored in a history table in program memory that is 32 K bits and is addressed by applying a hash function to the address of the branch instruction to determine the location in the table that represents a particular branch instruction. In hardware-based branch prediction schemes of the prior art, it is common to have history tables that are approximately 0.5 - 2.0 K in size. One of the advantages is that since it may be implemented in software, it is easy to adjust the size of the history table to achieve maximum performance. Branch history may be encoded in various ways. For example, the referenced bit in the history table may be defined to be a first value if the branch was taken and a second value if the branch was not being taken. Alternatively, the referenced bit may be defined to be a first value if the previous prediction proved to be correct and a second value if the previous prediction proved to be incorrect. The latter encoding scheme has the advantage of reducing problems associated with aliasing. Consider two branch instructions that are associated with the same entry in a branch history table due to aliasing. Since most branch predictions are correct, there is a high probability that both branch instructions will encode the table entry as "previous prediction correct". On the other hand, if the former encoding scheme is used, and one instruction has the prediction "taken" and the other has the prediction "not taken", it is much more likely that the two branch instructions will interfere with each other when accessing the branch history table. In addition, the latter scheme provides an advantage when first initializing the branch history table, since all entries of the table may be initialized to "previous prediction correct". It is also contemplated to use more sophisticated branch history algorithms. For example, a branch history table may be defined to keep a running average of branch behavior for a particular branch instruction, and update the prediction based on the running average. Those skilled in the art will recognize that a variety of algorithms may be used to keep track of branch history and adjust a branch prediction based on the branch history. Since the system may be implemented in software, it is easy for a programmer to try various algorithms to determine which works best in a particular environment. In addition, it is possible to use complex prediction algorithms that would not be practical to implement in hardware. As mentioned above, block 58 updates the history table when the prediction is correct, and block 60 updates the branch history table and updates the prediction based on the updated branch history table when the prediction is incorrect. In the vast majority of prediction/history algorithms, one would never change a prediction when the prediction proves to be correct, and it is not contemplated that one would wish to do so when implementing the present invention. However, it is contemplated also to change the prediction in block 58 if required by a particular algorithm. Block 60 updates branch history and also may change the prediction. For example, as described above, if the prediction is incorrect, but was correct the previous time the branch instruction was executed, the prediction may not be changed. Another reason why it is beneficial to use branch history to determine whether a branch prediction should be changed is because it tends to reduce the frequency of branch prediction changes. Using the Hewlett-Packard PA-RISC instruction set, each time a prediction is changed the branch instruction must be written back to memory. Therefore, it is desirable to minimize the frequency of prediction changes to the extend that overall prediction accuracy is not significantly affected. If the prediction must be updated, block 60 also updates the prediction. While the PA-RISC instruction set includes a prediction within a branch instruction, it is also contemplated to encode predictions using any other methods known in the art, such as a prediction table. When updating a prediction encoded into an instruction, the instruction op code must be updated and the instruction must be written back to memory. With reference ton Figure 1, a branch instruction may be stored in L1 cache 14, L2 cache 16, main memory 18, virtual memory storage disk 22, and permanent storage disk 20. Though a programmer may not wish to write the branch instruction back to each of these storage devices, it is certainly within the scope of the invention to do so. In an embodiment branch instructions are written back to L1 cache 14, L2 cache 16, and main memory 18, but not permanent storage disk 20 nor virtual memory storage disk 22. Writing date back to permanent storage disk 20 results in a minimal performance increases, and may create a host of problems related to managing executable code. Also, it is common for multiple users to share common program files, so it would not be possible to have each user store branch history in common files. However, it may be advantageous to store updated branch predictions back to disk 20 in certain situation. While there are fewer problems writing branch instructions back to virtual memory storage disk 22, doing so results in little performance increase and incurs significant overhead. In contrast, writing branch instructions back to L1 cache 14, L2 cache 16. and main memory 18 produces significant performance increases. Various computer systems use various techniques to manage memory. For example, it is common to associate a dirty bit with a block of memory in a cache to indicate whether that block may simply be discarded from the cache when no longer needed, or must be written back to main memory to reflect a change in the memory block. Those skilled in the art will recognize how to use these techniques to implement the invention as desired. For example, if it is desired to write altered branch instructions only to 1.1 cache 14 and L2 cache 16, but not main memory 18, then the dirty bit of a block containing an altered branch instruction may be left clear on L2 cache 16 to indicate that the block may be discarded and need not be written back to main memory 18. Alternatively, if the dirty bit is set, the block (and the altered branch instruction with the updated prediction) must be written back to main memory 18 before the memory block containing the branch instruction is displaced, thus preserving the updated branch prediction, but consuming additional computing resources. It may also be desirable to treat various types of code differently. For example, it may be desirable to adjust branch predictions for kernel code, but not user code. Likewise, a programmer may wish to turn off branch prediction while debugging a program to prevent branch instructions from changing during program execution. Those skilled in the art will recognize situations wherein it is desirable to use or not use the system and will be able to provide programmers and computer users appropriate interfaces for doing so. After block 60 updates the branch history and possibly updates the branch prediction, routine 44 branches to block 50 and the routine terminates. As will be apparent from the above, the described embodiments can provide the following features: a system and apparatus for dynamically adjusting branch predictions by interrupting a CPU and examining a pending branch instruction; the advantages of software and hardware techniques; they can be implemented using software, as it can also be implemented in hardware or microcode. When implemented in software, they are easy to configure. Such parameters as interrupt interval and history table size may be easily adjusted and the performance changes observed to allow the system to be tuned for optimal performance. Typically, this is not possible with prior-art hardware-based branch prediction; they may be implemented on systems designed to interpret a static software-encoded branch prediction, thereby providing such systems with dynamic branch prediction; they can provide larger history and prediction memories than prior art branch prediction schemes, since these memories may be defined as software data structures; while they can dynamically adjust predictions over time. they can do so at a much lower frequency than prior art prediction schemes. In the prior art, branch prediction tended to be at one extreme or another. Prior art software-based branch prediction generated predictions once, and then locked them into the coding of the instructions where the prediction was not altered doing execution. On the other hand, prior art hardware-based branch prediction evaluated a branch instruction every time that branch instruction was executed. A significant amount of hardware is required to perform this function without degrading performance. In addition, if the prediction tends to be stable (and most predictions are), little is gained by evaluating the prediction every time the branch instruction is executed, and if the prediction alternates often, then continually changing the prediction does not offer a significant performance increase either; they can strike a balance between never updating a prediction and updating a prediction every time a branch instruction is executed. In one of the embodiments discussed, the CPU is only interrupted once every 15 million instructions. Since the branch prediction of a branch instruction is evaluated so infrequently, it is possible to spend additional time updating the prediction without incurring a significant amount of overhead; relatively infrequent evaluation can also be an asset when implemented in hardware. Such as implementation could be much simpler than prior art hardware branch prediction techniques because evaluating and updating the prediction may take significantly longer without affecting overall system performance. Since less hardware is dedicated to branch prediction, more hardware is available to speed up other functions of the CPU; they can provide a significant performance improvement over prior-art branch prediction schemes. Simulations have shown a 4% to 8% improvement over prior hardware predictions schemes and a 10% to 15% improvement over prior software prediction schemes. The disclosures in United States patent application no. 08/840,080, from which this application claims priority, and in the abstract accompanying this application are incorporated herein by reference.

Claims: A method of adjusting a branch prediction associated with a branch instruction contained in a segment of program code while said program code is being executed by a central processing unit, the method comprising recurringly interrupting execution of said program code when execution of said branch instruction by the central processing unit is pending; executing a prediction adjustment routine (46) that updates said branch prediction; and resuming execution of said program code. A method as in claim 1, wherein interrupting execution of the program code when execution of the branch instruction by the central processing unit is pending comprises initialising a timer to a time interval or an instruction counter to an instruction count; waiting for the time interval to expire or counting instructions as they are executed; and interrupting execution of the program code when the time interval has expired or when the number of executed instructions equals the instruction count. A method as in claim 2, including the step of waiting for the branch instruction after the time interval has expired or after the instruction count has been reached. A method as in claim 2 or 3, wherein the timer is initialised to a random time interval or the instruction counter is initialised to a random instruction count. A method as in any preceding claim, wherein interrupting execution of the program code when execution of the branch instruction by the central processing unit is pending comprises: a) executing a break instruction that interrupts execution of the program code; and replacing the break instruction with the branch instruction, or b) setting a flag that causes the branch instruction to generate an interrupt; and interrupting execution of the program code when the first break instruction after setting the flag is encountered. A method as in any preceding claim, wherein executing a prediction adjustment routine that updates the branch prediction comprises evaluating a branch condition of the branch instruction to determine whether the branch instruction will branch; evaluating a branch prediction associated with the branch instruction; determining whether the branch prediction is correct or incorrect; and a) toggling the branch prediction if the branch prediction is incorrect, or b) saving whether the branch prediction is correct or incorrect as branch history; updating the branch prediction based on both the branch history and the results of the step of determining whether the branch prediction is correct or incorrect. A method as in claim 6, wherein sub-step b) comprises toggling the branch prediction if the prediction is incorrect when evaluated twice in a row. A method as in claim 1, wherein executing a prediction adjustment routine that updates the branch prediction includes examining a pending instruction to determine whether the pending instruction is the branch instruction; and a) resuming execution of the program code if the pending instruction is not the branch instruction, or b) emulating execution of instructions from the program code if the pending instruction is not the branch instruction, until the branch instruction is reached. A central processing unit designed to execute computer instructions and including an interrupt unit (34) operable to launch a branch prediction adjustment routine in response to an interrupt which evaluates a pending branch instruction and updates a branch prediction associated with the pending branch instruction based on whether the branch prediction is correct in accordance with the method of any preceding claim. A central processing unit as in claim 9, wherein the interrupt unit (34) includes a timer (42) operable to measure a time interval and to generate the interrupt when the time interval has expired and/or an instruction counter (40) that can be initialised to an instruction count and operable to generate the interrupt after a number instructions that have been executed equals the instructions count. A central processing unit as in claim 9 or 10, comprising: a status flag (27) operable to cause the interrupt unit to generate the interrupt when the branch instruction is pending.

Inventors: LARSON DOUGLAS V, LARSON, DOUGLAS V.
Applicants: HEWLETT PACKARD CO, HEWLETT-PACKARD COMPANY
Application year: 1998
Main classification: G06F9
IPC codes: G06F9, G06F11