Pulse width modulation circuit

Abstract: In a pulse width modulation (PWM) control circuit, a free run counter counts a clock signal to count a time value, and generates an overflow signal when the counted time value is equal to a predetermined value. A transfer control circuit allows a set time value to be transferred from a master compare register to a slave compare register and inhibits the transfer of the set time value in response to the overflow signal. A comparing circuit compares the counted time value in the free run counter and the set time value transferred in to the slave compare register and generates a coincident signal when the counted time value is coincident with the set time value. An output circuit generates a PWM signal in response to the overflow signal and the coincident signal.

Description: Background of the present invention 1. Field of the present invention The present invention relates to a pulse width modulation (PWM) control and, more particularly, to PWM control which is used in a meter control. 2. Description of the Related Art In each of meters on the dashboard of an automobile, a value pointed by a needle of the meter changes in accordance with change in vehicle speed, rotational speed of an engine, or the like. The Pulse Width Modulation (PWM) control is typically used to change the position of the needle of each meter in accordance with the change in vehicle speed, rotational speed of an engine, or the like. Fig. 1 shows a block diagram illustrating the structure of a conventional meter control circuit, as in Japanese Laid Open Patent Application (JP-A-Heisei 3-228102), for example. Referring to Fig. 1, a set value is written from a bus 210 into a master compare register 203 in response to generation of a write request signal. When a transfer control signal 209s from a transfer control circuit 204 is in a transfer permission state, the set value is transferred from the master compare register 203 to the slave compare register 202 in synchronism with the overflow signal 206s of the free run counter 201. A coincidence signal 207s is generated when a count value of a free run counter 201 and a set value on a slave compare register 202 coincide. Also, the overflow signal 206s is generated when the free run counter 201 overflows. A PWM output signal 208s is formed from the coincidence signal 207s and the overflow signal 206s. However, when the overflow signal 206s is generated during the writing operation of the set value into the master compare register 203 through the bus 210, there is a possibility that the set value is transferred to the slave compare register 202 through the master compare register 203 during the writing operation. For this reason, the transfer control circuit 204 is provided to control the transfer of the set value from the master compare register 203 to the slave compare register 202. Thus, an erroneous operation can be prevented even in the case where the overflow signal 206s is generated during the rewriting operation on the master compare register 203, as mentioned above. To prevent the erroneous operation in the above circuit structure, the following transfer control is performed. That is, when the transfer control signal 209s is in a transfer permission state, the transfer control circuit 204 permits the set value to be transferred from the master compare register 203 to the slave compare register 202 in synchronism with the overflow signal 206s from the free run counter 201, as shown by an arrow A. On the other hand, the transfer control circuit 204 inhibits the set value from being transferred from the bus 210 to the master compare register 203, as shown by an arrow B. When the transfer control signal 209s is in a transfer inhibition state, the transfer control circuit 204 inhibits the set value from being transferred from the master compare register 203 to the slave compare register 202, even if the overflow signal 206s is generated from the free run counter 201. On the other hand, the transfer control circuit 204 permits the set value to be written into the master compare register 203 through the bus 210, as shown by the arrow B. Fig. 2 shows a control flow in the conventional circuit after the write request signal is generated. In the conventional circuit, when a write request signal is generated in a step S32, the transfer control circuit 204 is set in the transfer inhibition state in a software manner in a step S34. Then, the set value is written a CPU (not shown) to the master compare register 203 through the bus 210 in a step S36. Subsequently, the transfer control circuit is set in the transfer permission state in a software manner in a step S38. The above steps are repeated until the overflow signal is generated. When the overflow signal 206s is generated from the free run counter 201, the transfer of the set value from the master compare register 203 to the slave compare register 202 is executed in synchronism with the overflow signal in a step S40. Fig. 3 shows a relation between the overflow signals 206s of the free run counter 201 and the write request signals to the master compare register 203. As shown in Fig. 3, the many write request signals are generated between an overflow signal 206s and the next overflow signal 206s from the free run counter 201. In this case, The CPU sets the transfer control circuit 204 into the transfer inhibition state each time the write request signal is generated. Then, the CPU writes a set value into the master compare register 203. Thereafter, the CPU sets the transfer control circuit 204 to the transfer permission state. This processing is repeated each time the write request signal is generated for a time period between the overflow signal 206s and the next overflow signal 206s. As a consequence, however, only the set value written into the master compare register 203 just before the generation of the overflow signal 206s is transferred to the slave compare register 202. Thereby, the latest set value is reflected in the PWM output signal 208s. That is, the set values other than the value written into the master compare register 203 just before the generation of the overflow signal 206s are not used. Since the transfer of the set value shown by the arrow A is controlled by the transfer control circuit 204, the set value is not transferred from the master compare register 203 to the slave compare register 202 even when the overflow signal 206s is generated during the writing operation of the value into the master compare register 203. Therefore, it can be that the value of the slave compare register 203 is not updated. In this manner, the PWM output signal cannot be not changed in spite that although the values to be indicated by the meters such as vehicle speed, rotational speed of the engine, etc. are changed. As described above, there are the following problems in the conventional circuit. As a first problem, the CPU performs vain processing. In the conventional circuit, the set value is written to the master compare register through the bus by the number of times of generation of the write request for the time period from a overflow signal and the next overflow signal from the free run counter. However, even if the value is written many times from the bus to the master compare register, only the latest value which has been finally written among them is eventually transferred as a valid value to the slave compare register. Therefore, any values overwritten on the master compare register other than the latest value are not reflected to the PWM output. As a result, the CPU performs the vain processing. As a second problem, the transfer control circuit 204 controls the transfer of the set value from the master compare register to the slave compare register. Therefore, it can be that the set value on the slave compare register is not updated in dependence on a timing. In other words, when the overflow signal is generated from the free run counter during the writing operation of the set value into the master compare register, the transfer of the set value from the master compare register to the slave compare register is not permitted, since the value is being written into the master compare register. Therefore, the set value is not transferred from the master compare register to the slave compare register. Thus, the set value on the slave compare register is not updated and the PWM output signal does not change. Summary of the Invention The present invention is accomplished to solve the above problems. Therefore, an object of the present invention is to provide a pulse width modulation control circuit. In order to achieve an aspect of the present invention, a pulse width modulation (PWM) control circuit includes a free run counter for counting a clock signal to count a value, and for generating an overflow signal when the counted value is equal to a predetermined value, a slave compare register for storing a set value, a master compare register for storing the set value, a transfer control circuit for allowing the set value to be transferred from the master compare register to the slave compare register and for inhibiting the transfer of the set value in response to the overflow signal, a comparing circuit for comparing the counted value in the free run counter and the set value transferred into the slave compare register and for generating a coincident signal when the counted value is coincident with the set value, and an output circuit for generating a PWM signal in response to the overflow signal and the coincident signal. The transfer control circuit may include a transfer control flag which is reset in response to the overflow signal, and may generate a transfer inhibition signal when the transfer control flag is reset. In this case, the transfer of the set value from the master compare register to the slave compare register is inhibited in response to the transfer inhibition signal. Also, the master compare register may receive the set value in response to a write request signal when the transfer inhibition signal is generated. Also, the transfer control circuit may set the transfer control flag in response to the write request signal to generate a transfer permission signal such that the set value is transferred from the master compare register to the slave compare register. In this case, write of the set value into the master compare register is inhibited in response to the transfer permission signal. The PWM control circuit may further include a writing section for referring to the transfer control flag to detect whether the transfer control flag is set or reset, and generating the write request signal to write the set value in the master compare register when the transfer control flag is reset. In order to achieve another aspect of the present invention, a method of reliably generating a pulse width modulation (PWM) signal in a PWM control circuit, includes the steps of: counting a clock signal to count a value, and generating an overflow signal such that a transfer inhibition mode is set, when the counted value is equal to a predetermined value; transferring a set value from a master compare register to a slave compare register in a transfer permission mode, the transfer is inhibited in the transfer inhibition mode; and comparing the counted value and the set value transferred into the slave compare register and generating a PWM output signal in the transfer inhibition mode when the counted value is coincident with the set value. The generation of an overflow signal includes resetting a transfer control flag in response to the overflow signal, such that the transfer inhibition mode is set. The set value is desirably written into the master compare register in the transfer inhibition mode. In this case, the transfer permission mode is set in response to the writing of the set value into the master compare register. Also, the transfer control flag is set. In order to still another aspect of the present invention, a pulse width modulation (PWM) control circuit includes a transfer control flag, a master compare register and a slave compare register, a writing section for referring to the transfer control flag to detect whether the transfer control flag is set or reset, for writing a set value in the master compare register when the transfer control flag is reset, wherein the set value is transferred from the master compare register to the slave compare register when the transfer control flag is set, a free run counter for counting a clock signal to count a value, and for generating an overflow signal to reset the transfer control flag, when the counted value is equal to a predetermined value, and a PWM signal output circuit for comparing the counted value in the free run counter and the set value transferred into the slave compare register and for generating a PWM output signal in response to the overflow signal when the counted value is coincident with the set value. In order to achieve yet still another aspect of the present invention, a method of outputting a pulse width modulation (PWM) signal corresponding to a set value in a PWM control circuit, comprising the steps of: counting a pulse signal to generate a counted value; generating an overflow signal when the counted value is equal to a predetermined value; writing a set value in a master compare register in a transfer inhibition mode; transferring the set value from said master compare register to a slave compare register in a transfer permission mode; resetting the transfer permission mode to the transfer inhibition mode in response to the overflow signal; comparing said counted value and the set value transferred into the slave compare register to generate a coincident signal when the counted value is coincident with the set value; and outputting a PWM signal in response to the overflow signal and the coincident signal. The writing step includes generating a write request signal. In this case, the transfer inhibition mode is reset to the transfer permission mode in response to the write request signal. The resetting of the transfer permission mode includes setting a transfer control flag in response to the overflow signal, and the resetting of the transfer inhibition mode includes resetting the transfer control flag in response to the write request signal. In this manner, only the set value corresponding to a first one of the plurality of write request signals is allowed to be written in the master compare register. Brief Description of the Drawings Fig. 1 is a block diagram illustrating the structure of a conventional PWM control circuit; Fig. 2 is a control flow chart illustrating the operation of the conventional PWM control circuit shown in Fig. 1; Fig. 3 is a diagram illustrating the relation of overflow signals and write request signals in the conventional PWM control circuit shown in Fig. 1 ; Fig. 4 is a block diagram illustrating the structure of a PWM control circuit according to an embodiment of the present invention; Fig. 5 is a control flow chart illustrating the operation of the PWM control circuit according to the embodiment of the present invention; Fig. 6 is a diagram illustrating the relation of overflow signals and write request signals in the PWM control circuit according to the embodiment of the present invention; and Fig. 7 is a diagram illustrating the relation of transfer of the set value from the master compare register to the slave compare register and the write requests in the PWM control circuit according to the embodiment of the present invention. Description of the Preferred Embodiments The pulse width modulation (PWM) control circuit of the present invention will be described below in detail with reference to the accompanying drawings. Fig. 4 shows a block diagram illustrating the structure of a pulse width modulation (PWM) control circuit according to an embodiment of the present invention. Referring to Fig. 4, the PWM control circuit is composed of a free run counter 101, a slave compare register 102, a master compare register 102, a transfer control circuit 104 with a transfer control flag 104-1, an output circuit 105, a comparing circuit 106, a CPU 124 and a clock signal generating circuit 122. As seen from Fig. 4, the PWM control circuit in the embodiment differs from the conventional PWM control circuit shown in Fig. 1 with respect to a point that the overflow signal 106s is connected from the free run counter 101 to a transfer control circuit 104. The CPU 124 controls the whole operation of the PWM control circuit. The CPU 124 refers to the transfer control flag 104-1 of the transfer control circuit 104. When the transfer control flag 104-1 is reset to a transfer inhibition state or mode, the CPU generates a write request signal and writes a set value into a master compare register 203 through the bus 110 in response to the write request signal. The transfer control flag 104-1 of the transfer control circuit 104 is reset to a transfer permission state or mode in response to the write request signal to output a transfer permission signal. On the other hand, when the transfer control flag 104-1 is set in the transfer permission state, the CPU cannot generate the write request signal. As a result, the set value is never written into the master compare register 103 in the transfer permission mode. When the transfer control flag 104-1 is set in the transfer permission state, the transfer control circuit 104 outputs a transfer permission signal 109s. The set value is transferred from the master compare register 203 to the slave compare register 202 in synchronism with the overflow signal 206s of the free run counter 201 in response to the transfer permission signal 109s. The free run counter 101 counts the clock signal from the clock signal generating circuit 122 to generate a counted value, and generates the overflow signal 106s when the counted value is equal to a predetermined value which is set by the CPU 124. The comparing circuit 106 compares generates a coincidence signal 207s when the counted value by the free run counter 101 is coincident with the set value transferred to the slave compare register 202. The output circuit 105 generates a PWM output signal 208s from the coincidence signal 207s and the overflow signal 206s. Also, the transfer control flag 104-1 of the transfer control circuit 104 is reset to the transfer inhibition state in response to the overflow signal 206s to output the transfer inhibition signal 109s. To prevent the erroneous operation in the above circuit structure, the following transfer control is performed. That is, when the transfer control signal 209s is in a transfer permission state, the transfer control circuit 204 permits the set value to be transferred from the master compare register 203 to the slave compare register 202 in synchronism with the overflow signal 206s from the free run counter 201, as shown by an arrow A. On the contrary, in the transfer permission state, the CPU does not generates the write request signal. Therefore, the set value is not written into the master compare register 203, as shown by an arrow B. On the other hand, when the transfer control signal 209s is in a transfer inhibition state, the transfer control circuit 204 inhibits the set value from being transferred from the master compare register 203 to the slave compare register 202, even if the overflow signal 206s is generated from the free run counter 201. On the contrary, the transfer control circuit 204 permits the CPU to generate the write reques signal and to write the set value into the master compare register 203 through the bus 210, as shown by the arrow B. In this manner, in this embodiment, the transfer control signal 109s of the transfer control circuit 104 is reset (transfer is inhibited) by the overflow signal 106s in a hardware manner and only the setting operation (transfer is permitted) is executed in a software manner. Fig. 5 shows a control flow for explaining the operation of the PWM control circuit of the present invention. The CPU 124 refers to the transfer control flag 104-1 of the transfer control circuit 104. When the transfer control flag 104-1 is reset to a transfer inhibition state or mode, the CPU 124 generates a write request signal in a step S12 and writes a set value into a master compare register 203 through the bus 110 in response to the write request signal in a step S14. The transfer control flag 104-1 of the transfer control circuit 104 is set in a transfer permission state in response to the write request signal in step S16 to output a transfer permission signal. The set value is transferred from the master compare register 103 to the slave compare register 102 in the transfer permission state in response to the transfer permission signal in a step S18. Thereafter, the overflow signal is generated from the free run counter 101 and then the PWM signal is outputted from the output circuit 105 as described above. The transfer control flag 104-1 of the transfer control circuit 104 is reset to the transfer inhibition state in a step S20 to output the transfer inhibition signal 109s. As described above, the transfer control flag 104-1 is reset in a hardware manner, Therefore, in a software manner, it is sufficient to execute only a control to set the transfer control circuit 104 into the transfer permission state after the set value has been written to the master compare register 103. Fig. 6 shows a relation between write request signals and the writing operations to the master compare register 103 through the bus 110. When only the transfer permission is controlled in the software manner in accordance with the control flow of Fig. 5, only the write request signal just after the overflow signal 106s is validated. On the contrary, the subsequent write request signals before generation of the overflow signal are invalidated. At the same time, the transfer control flag is always checked by the CPU. Only when it is confirmed that the transfer control signal 109s is set in the transfer inhibition state, the writing operation of the set value to the master compare register 103 is carried out. Thus, the writing operation of the set value from the bus 110 to the master compare register 103 is carried out only once for a period of time between the overflow signal 106s and the next overflow signal 106s. Subsequent, the set value is transferred from the master compare register 103 to the slave compare register 102. Fig. 7 shows a change quantity of a target such as vehicle speed, rotational speed of a engine, and the like in the PWM control and the set values which are transferred from the master compare register 103 to the slave compare register 102. In Fig. 7, an alternate long and short dash line indicates the change quantity in the conventional circuit. The dash line indicates a target change quantity. The solid line indicates the change quantity in the PWM control circuit of the present invention. In the conventional circuit shown in Fig. 1, whenever the write request signal is generated, the set value is written from the bus 210 to the master compare register 203. As a result, the last set value between the overflow signal 206s and the next overflow signal 206s is transferred from the master compare register 203 to the slave compare register 202. On the other hand, according to the circuit of the present invention, after the overflow signal 106s is generated, only the first write request is validated and the first set value is written to the master compare register 103 through the bus 110. Then, the set value is transferred from the master compare register 103 to the slave compare register 102 in response to the next overflow signal 106s. The subsequent write request signals are invalidated. As seen from Fig. 7, in the present invention, the PWM control can be accomplished more precisely than in the conventional circuit. Even if a timing when the set value is transferred from the master compare register to the slave compare register is fluctuated, it is possible to accomplish the PWM control with higher precision. By using the PWM control circuit of the present invention, a control can be performed to validate only the first write request signal after the generation of the overflow signal from the free run counter. Also, the set value is written from the bus to the master compare register in response to only the first write request signal after the generation of the overflow signal. After that, even if the write request signals are generated for a period of time until the generation of the next overflow signal, they are invalidated and the writing of the set value from the bus to the master compare register is not executed. Thus, even if the write request signals are generated for a period of time between the overflow signal and the next overflow signal, the writing operation of the set value from the bus to the master compare register is executed only once. Then, the set value is transferred to the slave compare register. Thus, the master compare register is not overwritten and the vain overwriting operation of the CPU is prevented. Since only the first write request signal after the overflow signal from the free run counter is validated and the set value is written from the bus to the master compare register, there is an enough time until the generation of the next overflow signal. Therefore, the generation of the overflow signal during the writing operation of the set value from the bus to the master compare register can be avoided. Thus, inconvenience can be prevented in which the set value is not transferred from the master compare register to the slave compare register.

Claims: A pulse width modulation (PWM) control circuit comprising: a free run counter (101) for counting a clock signal to count a time value, and for generating an overflow signal when said counted time value is equal to a predetermined value; a slave compare register (102) for storing a set time value; a master compare register (103) for storing said set time value; a transfer control circuit (104) for allowing said set time value to be transferred from said master compare register to said slave compare register and for inhibiting the transfer of said set time value in response to said overflow signal; a comparing circuit (106) for comparing said counted time value in said free run counter and said set time value transferred into said slave compare register and for generating a coincident signal when said counted time value is coincident with said set time value; and an output circuit (105) for generating a PWM signal in response to said overflow signal and said coincident signal. A PWM control circuit according to claim 1, wherein said transfer control circuit includes a transfer control flag (104-1) which is reset in response to said overflow signal, and generates a transfer inhibition signal when said transfer control flag is reset, and wherein the transfer of said set time value from said master compare register to said slave compare register is inhibited in response to said transfer inhibition signal. A PWM control circuit according to claim 2, wherein said master compare register receives said set time value in response to a write request signal when said transfer inhibition signal is generated. A PWM control circuit according to claim 3, wherein said transfer control circuit sets said transfer control flag in response to said write request signal to generate a transfer permission signal such that said set time value is transferred from said master compare register to said slave compare register. A PWM control circuit according to claim 4, wherein write of said set time value into said master compare register is inhibited in response to said transfer permission signal. A PWM control circuit according to claim 5, further comprising writing means for referring to said transfer control flag to detect whether said transfer control flag is set or reset, and generating said write request signal to write said set time value in said master compare register when said transfer control flag is reset. A method of reliably generating a pulse width modulation (PWM) signal in a PWM control circuit, comprising the steps of: counting a clock signal to count a time value, and generating an overflow signal such that a transfer inhibition mode is set, when said counted time value is equal to a predetermined value; transferring a set time value from a master compare register to a slave compare register in a transfer permission mode, the transfer is inhibited in said transfer inhibition mode; and comparing said counted time value and said set time value transferred into said slave compare register and generating a PWM output signal in said transfer inhibition mode when said counted time value is coincident with said set time value. A method according to claim 7, wherein said step of generating an overflow signal includes resetting a transfer control flag in response to said overflow signal, such that said transfer inhibition mode is set. A method according to claim 7 or 8, further comprising the step of writing said set time value into said master compare register in said transfer inhibition mode. A method according to claim 9, further comprising the step of setting said transfer permission mode in response to the writing of said set time value into said master compare register. A method according to claim 10, further comprising the step of setting said transfer permission mode includes setting a transfer control flag.

Inventors: YOSHINO MASAKI, YOSHINO, MASAKI, Yoshino, Masaki, c/o NEC IC Microcomp. Syst. Ltd.
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1998
Main classification: H03K7
IPC codes: G05B9, G05B11, H02M7, G06F1, H04Q9, G06F13, H02P27, H03K3, H03K7, G01R5