Circuit with hot-electron protection and method

Abstract: An I/O circuit (100) whose output receives a voltage V PAD which is temporarily higher than a critical voltage V DS MAX > V DS 1 across drain and source of a conducting first N-FET (110, N1) acting as a pull-down device. The first N-FET is protected against hot-electron induced degradation by a serially coupled second N-FET (113, N3). A variable drain-source voltage V DS 3 is added to V DS 1 . A comparator (150) compares the received voltage V PAD to a supply voltage V CC and pulls a gate (G) of the second N-FET (N3) to V PAD or to V CC . The conductivity of the second N-FET (N3) is thereby changed so that V PAD is distributed among V DS 1 and V DS 2 . The comparator (150) conveniently comprises two P-FETs (P1, P2, 160, 170).

Description: Field of the Invention This invention relates to electronic devices, and especially to input-output circuits and to a method for operating input-output circuits. Background of the invention Advances in very large scale integration (VLSI) fabrication techniques for integrated circuits (IC) are often based on reduced transistor dimensions (e.g., channel length) without a proportional scaling of the reference voltages. The reduction of critical transistor dimensions results in a significant increase of the electrical fields in the transistors. When for example, a N-channel field effect transistor (N-FET) is conductive in the deep saturation region, then its gate oxide can be damaged by high electrical fields. The results are, for example, longer delay times and a lower long-term reliability of the IC. Consequences known in the art under the terms 'hot-carrier induced degradation' and 'hot electron effects' are described in Leblebici, Y.: "Design Considerations for CMOS Digital Circuits with Improved Hot-Carrier Reliability", IEEE J. of Solid State Circuits, vol. 31, No. 7, p. 1014-1024 (1996). FIGS. 1-2 explain details of the problem which is reduced or solved by the present invention. FIG. 1 is a simplified circuit diagram of a prior art electronic system 11 having first circuit 10 and second circuit 20. Electronic system 11 represents an I/O (input/output) connection. Circuits 10 and 20 are coupled by signal line 15 and reference line 19. Signal line 15 is also referred to as "PAD". Circuit 10 receives a low supply voltage V CC 1 (e.g., V CC 1 =3.3 volts) at supply line 91; and circuit 20 receives a higher supply voltage V CC 2 (e.g., V CC 2 =5.5 volts) at supply line 92, so that: V CC 1 < V CC 2 . V PAD is the potential between lines 15 and 19 and can be: 0 < V PAD < V CC 2 . Circuit 10 comprises N-FETs N2 and N1 serially coupled with drain (D) and source (S) electrodes between signal line 15 and reference line 19. A gate (G) of N-FET 1 is coupled to input terminal 90; and a gate (G) of N-FET N2 is coupled to supply line 91 at V CC 1 . Voltages across D and S of N-FET N1 and N-FET N2 are V DS 1 and V DS 2 , respectively. N-FETs N1 and N2 are voltage sensitive components, whose V DS 1 and V DS 2 should not exceed a critical voltage ("break voltage") V DS MAX : V DS 1,2 ≤ V DS MAX when either of N-FETs N1 or N2 is conductive. When N-FETs N1 and N2 are not conductive, then V DS 1,2 can exceed V DS MAX . It is inconvenient, when V DS MAX is lower than V CC 2 : V DS MAX < V CC 2 In circuit 20, switch 25 is coupled between supply line 92 and signal line 15. The operation of switch 25 is not communicated to circuit 10. Circuit 20 can temporarily pull V PAD (signal line 15) to the higher supply voltage V CC 2 so that N-FETs N1 and N2 could be damaged. FIG. 2 is a simplified voltage-time diagram illustrating the operation of system 11 of FIG. 1 by way of example. FIG. 2 refers to a pull-down operation when N-FETs N1 and N2 pull line 15 to line 19. A pull-up operation in the opposite direction is not considered. Traces 31-32 for V PAD and traces 41-43 for V DS1 are coordinated by a vertical voltage-axis "V" (0 volts to V CC 2 =5.5 volts) and a horizontal time-axis "t" (in nano seconds ns). Line 51 between traces 31 and 41 and lines 52-53 between traces 32 and 43 show: V DS 2 = V PAD - V DS 1 It is assumed that V DS MAX is about 3.6 volts. In a time interval between t=0 and t=t 1 , (e.g., at t 1 =2ns), V PAD is at its maximum value V CC 2 = 5.5 volts (trace 31, equation 2). N-FETs N1 and N2 are not conducting. N-FET N2 adds its V DS 2 (line 51) to V DS 1 of N-FET N1 (trace 41), thus fulfilling condition (3). At time t 1 , N-FET N1 is made conductive by, e.g., an input signal at its gate G (input terminal 90), and V DS 1 goes quickly to substantially zero (at 0.5 volts, trace 42) so that N-FET N1 is not damaged. In the interval after t 1 , V DS 1 stays at zero (trace 43). However, V PAD decreases slowly (trace 32), so that between t 1 , and t 2 , V DS 2 (line 52) exceeds temporarily V DS MAX . V DS 2 across N-FET N2 reaches its allowable value V DS 2 = V DS MAX only at t 2 (equation 3, line 53). One method for preventing V DS MAX from being temporarily exceeded utilizes a control circuit that switches the gate of N-FET N2 (signal G2) alternatively between a voltage VCCL (corresponding to V CC 1 in FIG. 1) and VCCH (corresponding to V CC 2 ). With a temporarily increased conductivity of N-FET N2, voltage V DS 2 falls faster so that the time interval t 1 and t 2 can be reduced. However, such a solution is not always applicable, because circuit 10 would require two supply voltages (V CC 1 and V CC 2 ). This is especially difficult to implement when circuit 10 and circuit 20 separated by a significant distance. There is a need to design an I/O connection which mitigates or avoids these and other disadvantages and limitations of the prior art. Brief Description of the Drawings FIG. 1 is a simplified circuit diagram of an prior art electronic system having a first circuit and a second circuit; FIG. 2 is a simplified voltage-time diagram illustrating the operation of the system of FIG. 1 by way of example; FIG. 3 is a simplified circuit diagram of a circuit illustrating a preferred embodiment of the present invention; and FIG. 4 is a simplified voltage-time diagram illustrating a method of the present invention to operate the circuit of FIG. 3. Detailed Description of a Preferred Embodiment FIG. 3 is a simplified circuit diagram of circuit 100 illustrating a preferred embodiment of the present invention. Input-output (I/O) circuit 100 (hereinafter circuit 100) comprises pull-down device 101 with transistors 110, 120 and 130, (hereinafter N1, N2, and N3, respectively), node 115 (also: "PAD" or "line"), optional pull-up device 116, comparator 150 (also: "switch network") with transistors 160, 170 and 180 (hereinafter P1, P2 and P3, respectively). Optionally provided transistors N2 and P3 are convenient but not essential for the present invention. Circuit 100 has reference line 119 with reference potential V R1 (or "GND" of e.g., 0 volts) and reference line 191 with a reference potential V R2 (or "V CC " of e.g., 2.5 volts). Lines 119 and 191 are also referred to as "terminals". Similar to prior art circuit 10 of FIG. 1, circuit 100 is coupled to a further circuit, such as e.g., circuit 20' (cf. FIG. 1) by node 115 and either one or both of lines 119 or 191. Optionally, circuit 100 receives input signal 195 via input terminal 190 and provides output signal 117 at node 115. N1, N2, and N3 are preferably N-channel field effect transistors each having a gate (G), a drain (D) and a source (S). The term "transistor" is intended to include any device having at least two main electrodes and a control electrode which is controlled by a signal applied to the control electrode. Transistors, such as N1, N2, N3, P1, P2, and P3 can be e.g., FETs having drain (D), source (S) as main electrodes and gates (G) as control electrode. Transistors can also be bipolar transistors with collectors (C) and emitters (E) as main electrodes and bases (B) as control electrodes, or other devices. Transistors N1, N2, and N3 are, preferably, field effect transistors (FETs) of the N-channel type (N-FETs) and transistors P1, P2 and P3 of comparator 150 are, preferably, field effect transistors (FETs) of the P-channel type (P-FETs), symbolized by a circle at the gate. This is convenient for explanation, but not essential. A person of skill in the art will apply apparatus and method of the present invention for other configurations, such as complementary configurations with N-FETs in comparator 150 and P-FETs in pull-down device 101. Although the preferred embodiment has been implemented in CMOS-technology, a person of skill in the art is able, based on the description herein, to use the present invention with other technologies, with for example, all transistors of equal conductivity types. The transistors and the other mentioned elements of circuit 100 are coupled, preferably, as follows: Pull-up device 116 which is not essential for the invention, is illustrated as coupled with dashed lines between line 191 and node 115. Preferably, pull-up device 116 receives input signal 195 from input terminal 190. Pull-down device 101 is coupled between node 115 and line 119 with transistors N3, N2, and N1 serially coupled together. The order in which transistors N3, N2, and N1 are arranged is convenient, but not essential for the invention. In detail, the drain (D) as main electrode of N3 is coupled to node 115, the source (S) as the other main electrode of N3 is coupled to the drain (D) of N2. The source (S) of N2 is coupled to the drain (D) of N1. The source (S) of N1 is coupled to line 119. The gate (G) as control electrode of N1 is coupled to input terminal 190 and receives input signal 195. The gate (G) of transistor N2 is coupled to line 191 receiving predetermined potential V CC . The gate (G) of transistor N3 is coupled to output node 155 of comparator 150 and receives either the potential of node 115 (V PAD ) or the potential of line 191 (V CC ). In comparator 150, transistors P2 and P1 are serially coupled between line 191 and node 115. The drain (D) of P2 is coupled to the drain (D) of P1 at output node 155. The source (S) of P1 is coupled to node 115. The gate (G) of P2 is coupled to node 115 and the gate (G) of P1 is coupled to line 191. The gates (G) of P1 and P2 form comparator inputs 151 and 152, respectively. Optional transistor P3 has its source (S) coupled to line 191 and its drain (D) and gate (G) coupled together to output node 155. P3 prevents node 155 from drifting when V PAD = V CC . Comparator 150 can be implemented in various ways, provided that it measures the potential difference between line 191 and line 115 and provides a control signal to transistor N3 so as to vary the S-D impedance of transistor N3 to act as a potential divider redistributing the voltage V PAD across pull-down device 101 so that none of transistors N1, N2, or N3 is exposed to a voltage V DS > V DS MAX . A person of skill in the art is able to couple bulks (or wells) of transistors N1, N2, N3, P1, P2, and P3 to lines 191, 119 or to other points, but such further details are not illustrated for simplicity. It is convenient to couple bulks of P1 and P2 (in FIG. 3, arrows pointing to the gate circles) to output node 155, since, as further explanation will show, node 155 has either the potential of V PAD or of V CC , whichever is higher. For explanation, voltages and their function are introduced. Voltages across D and S of transistors N1, N2, and N3 are V DS 1 , V DS 2 , and V DS 3 , respectively, which should not exceed the above mentioned allowable voltage V DS MAX : V DS 1,2,3 ≤ V DS MAX N-FETs N1, N2 and N3 are voltage sensitive components. As discussed in connection with FIGS. 1-2 in the background section, the further circuit imposes a potential V PAD between node 115 and line 119 (GND potential). V PAD is the sum of V DS 1,2,3 : V PAD = V DS 1 + V DS 2 + V DS 3 V PAD can be temporarily higher than the maximum allowable voltage V DS MAX (cf. equation 3) across transistors N1, N2, and N3. Voltages between gate (G) and (S) of N-channel transistors N1, N2, and N3 are referred to as V GS N1 , V GS N2 , V GS N3 , respectively (in general V GS N ). These transistors are assumed to be conductive ("ON") thus able to carry a current between D and S when V GS N is equal or higher a threshold voltage V th N (of e.g., 0.2 volts), or otherwise non-conductive ("OFF"): V GS N ≥ V th N (conductive, "ON") V GS N < V th N (non-conductive, "OFF") Comparator 150 has an output voltage V GN3 defined between the gate (G) of N3 and line 119 (GND). Voltages between G and S of P-channel transistors P1 and P2 are referred to as V GS P1 and V GS P2 , respectively, (in general V GS P ) and control P1 and P2 according to: V GS P ≤ V th P (conductive, "ON") V GS P > V th P (non-conductive, "OFF") with a threshold voltage V th P of e.g., minus 0.2 volts. Having, preferably, comparator 150 configured as in FIG. 3, the gate-source voltages of P1 and P2 and their influence on circuit behavior are for example: (a) V GS P1 = V CC - V PAD making P1 conductive for V PAD ≥ V CC + | V th P | and providing V GN3 ≈ V PAD (b) V GS P2 = V PAD - V CC making P2 conductive for V CC ≥ V PAD + | V th P | and providing V GN3 ≈ V CC The threshold voltage is given within | | symbols for absolute value. In case of V CC ≈ V PAD , that is when |V PAD - V CC | < |Vth|, transistor P3 provides V GN3 ≈ V CC . For convenience of further explanation, |V th P | having a small magnitude compared to e.g., V CC and V PAD can be neglected in the following. Comparator 150 ("switch network") protects transistors N1, N2, and N3 by comparing voltages V CC at reference line 191 and V PAD at node 115 (PAD) and switches the control input (e.g., the gate) of transistor N3 alternatively to reference line 191 (at V CC ) and node 115 (V PAD ). The voltage V DS 3 across transistor N3 thereby alternates so that the voltages V DS 1 across transistor N1, V DS 2 across transistor N2 and V DS 3 across transistor N3 are always smaller than the maximum allowable voltage V DS MAX . A method of the present invention to protect transistors against "hot-electrons" is better understood in reference to an example in a voltage-time representation which was obtained by simulation. FIG. 4 is a simplified voltage-time diagram illustrating a method of the present invention to operate circuit 100 of FIG. 3. FIG. 4 was obtained by SPICE-investigation of circuit 100. SPICE is a simulator well known in the art, but a person of skill in the art could used other simulators and obtain similar results. The diagram of FIG. 4 has vertical a voltage-axis "V" (0 volts to 5.5 volts) and a horizontal time-axis "t" (in nano seconds). Circuit 100 receives V CC =3.3 volts at line 191 and receives V PAD = 5.5 volts at node 115. It is assumed that V PAD is determined by whatever additional circuitry (e.g., circuit 20') is coupled to line 115. In the example of FIG. 4, traces 210-212 illustrate the output voltage V GN3 of comparator 150 applied to the gate (G) of transistor N3; traces 220-222 illustrate V PAD across transistors N1, N2 and N3; traces 230-232 illustrate the sum voltage V DS 1 +V DS 2 across N1 and N2; and traces 240-242 illustrate the voltage V DS 1 across transistor N1. The voltage V DS 2 across N2 can be seen as the distance between traces 230-232 (V DS 1 +V DS 2 ) and traces 240-242 (V DS 1 ). The voltage V DS 3 across N3 can be seen as the distance between traces 220-222 (V PAD ) and traces 230-232 (V DS 1 +V DS 2 ). A critical voltage of V DS MAX = 3.6 volts is not exceed by any V DS at any time. At time t < t 1 , V DS 1 , 2 , 3 < V DS MAX of serially coupled transistors N1, N2, and N3 are added to V PAD (equations 6 and 7). With, for example, input signal 195 having a potential V GS N1 smaller than V th N (equation 9), N1 is non-conductive. N2 and N2 are also non-conductive due to source voltages floating in reference to line 119. Voltages V DS 1 (trace 240) V DS 1 +V DS 2 (trace 230) and V PAD (220) are stable. According to equations (11) to (13), P1 is conductive with V PAD =5.5 volts > V CC =3.3 volts, so that V GN3 ≈ V PAD (traces 210 and 220). At time point t 1 , input signal 195 switches N1 into the conductive state and V DS 1 goes (trace 241) to zero (e.g., 0 volts) at line 119. With the drain (D) of N1 and the source (S) of N2 having decreasing potential and the gate (G) of N2 at VCC, N2 also becomes conductive (equation 9) and V DS 1 +V DS 2 also goes to zero (trace 231). In other words, the distance between traces 231/241 is smaller than between traces 230/240. With its source (S) being pulled down by N1 and N2, the increasing value at V GS 3 makes transistor N3 conductive. With all transistors N1, N2, and N3 being conductive, V PAD goes to zero (trace 221). The initially high voltage V PAD (at time t=t 1 ) across conductive transistors N1, N2, N3 is distributed into smaller fractions (under trace 241, between traces 231/241, and between traces 221/231), each being smaller than V DS MAX , so that not only transistor N1, but also transistors N2 and N3 are protected against stress. With V PAD going below V CC , conductive transistor P2 of comparator 150 provides V GN3 ≈ V CC (equations 15-17). The transition interval t 1 to t 2 is finished at time t=t 2 when V PAD and all other across-the-transistor voltages V DS 1,2,3 reach substantially zero (traces 222, 232, 242). V GN3 stays at about V CC (trace 212). It is important to mention, that during the transition time interval (t 1 , t 2 ), V DS 3 across transistor N3 is reduced (between traces 221 and 231). This is due to the increasing conductivity of N3. For understanding, the reader can imagine that the gate (G) of N3 is connected to line 191 at V CC . N3 would not have sufficient conductivity when pull-down device 101 is switched on, so that an unwanted delay would be the result. According to the present invention, the conductivity of N3 is substantially always at the highest possible value. This is accomplished by keeping its gate (G) at the highest possible potential (V PAD or V CC ). In general terms, the method of the present invention can be described as method for protecting a N-channel field effect transistor (e.g., N-FET N3) with a variable drain-source voltage V DS 3 against a voltage V PAD which appears at a node (e.g., node 115) and which is at times V PAD ≥ V DS MAX . N-FET N3 is serially coupled to N-FET N1 and adds thereby a variable drain-source voltage V DS 3 to V DS 1 . The method of the present invention is applicable when pull-down device 101 (with e.g., N1) pulls node 115 to reference line 119 similar to the pull-down operation described in connection with FIG. 2. The pull-up operation when pull-up device 116 pulls node 115 to line 119 is not considered here, since N1 is not conductive in that case. The method comprises the following steps: (i) Comparing V PAD to a voltage V CC ≤ V DS MAX . Preferably, this step is performed by a comparator, such as comparator 150, but other implementations are also possible. In the preferred embodiment, V PAD and V CC are supplied to gates (G) of P-FETs P1 and P2, respectively, which are alternatively conductive and non-conductive. (ii) Changing the conductivity of N-FET N3 so that V PAD is distributed among V DS 1 and V DS 3 and V DS 1 is smaller than V DS MAX . Preferably, the conductivity of N-FET N3 is changed by coupling a gate (G) of N-FET N3 (a) to V PAD (if V PAD ≥ V CC ) by P1 obtaining high conductivity or (b) to V CC (if V CC ≥ V PAD ) by P2 obtaining high conductivity. The present invention allows one to design I/O-connections which can be used as interface between circuits having different supply voltages (e.g., of V CC 1 = 3.3 volts and V CC 2 =5 volts). The voltage sensitive transistor therein are protected without the need of a second supply voltage (as e.g., V CC 2 in prior art circuit 11). Circuit 100 as part of an I/O connection can accommodate signal voltages (e.g., V PAD ) which it does not produce internally (e.g., 5 volts). This makes it easy for so called plug-and-play applications. The comparator, as e.g., comparator 150 with two P-FETs can be implemented with smaller dimensions than pull-down device 101. The additional circuitry (e.g., P1, P2, N2, N3) used to protect a voltage sensitive transistor (e.g., N1) is small in chip area compared to the sensitive transistor itself. Moreover, due to enhanced protection, the sensitive transistor can be implemented with less chip area. The invention has been described in detail, by way of example only, with reference to a preferred embodiment thereof. In the description, numerous specific details have been set forth such as examples of voltages and particular transistor configurations, etc., in order to provide a thorough understanding of the present invention. It will be evident, however, to those skilled in the art that such specific details are not necessarily required in order to practice the invention. In other instances, well known structures and circuits not relating to the invention have been omitted or simplified in order to avoid unnecessarily obscuring the invention. The present invention provides cost saving protection circuitry which allows I/O connections which accommodate high signal voltages. Compared to the prior art, an additional serial pull-down transistor and two transistors in a logic, consuming preferably, only a small chip area, provide effective protection against the above-mentioned hot-electron effects. The circuit of the present invention needs only a single supply voltage which is, preferably, a low supply voltage. The logic controls the additional transistor and ensures an additional voltage across the additional transistor needed for protection. While the invention has been described in terms of particular structures, steps, devices and materials, those of skill in the art will understand based on the description herein that it is not limited merely to such examples and that the full scope of the invention is properly determined by the claims that follow.

Claims: A circuit (100) having a first reference terminal (119) at a voltage V RI (GND), a second reference terminal (191) at a voltage V R2 (V CC ), a node (115) for coupling said circuit (100) to a further circuit (20) which can apply a further voltage V PAD to said node, comparator (150) having inputs coupled to said second reference terminal and to said node and having an output (155), and a first transistor (110) having main electrodes (D, S) and a control electrode (G), said first transistor having its control electrode receiving an input signal (195), said circuit (100) being characterized by a second transistor (113) having main electrodes (D, S) and a control electrode (G), said second transistor (113) having its control electrode coupled to said output (155) of said comparator, said first and second transistors being serially coupled by their main electrodes between said node (115) and said first reference terminal V RI (GND) so as to support potentials V DS 1 and V DS 3 , across the main electrodes of the first and second transistor respectively, and wherein said comparator compares V PAD and V R2 (V CC ) and switches the control input of said second transistor to either V PAD or V R2 dependent upon whether the voltage V PAD or V R2 has the greater magnitude such that V DS 3 is less than a predetermined voltage (V DS MAX ) when V PAD > V R2 . The circuit of claim 1 characterized by a third transistor (112) having main electrodes and a control electrode, said third transistor being serially coupled with its main electrodes to said first transistor and said second transistor, said third transistor having its control electrode coupled to said second reference terminal. The circuit of claim 1 wherein said first transistor (110), and said second transistor (113, N3), and said third transistor (112) are N-channel field effect transistors (N-FETs), each having a drain (D) and a source (S) as main electrodes and having a gate (G) as control electrode. The circuit of claim 1 wherein said comparator (150) has a fourth transistor (170) and a fifth transistor (160), each having main electrodes and a control electrode, said fourth and fifth transistors being serially coupled with said main electrodes between said second reference terminal and said node and having said control electrodes as said inputs. The circuit of claim 1 wherein said comparator (150) has a first P-channel field effect transistor (160, P-FET) and a second P-FET (170), said first and second P-FETs being serially coupled with their sources to said node and to said second reference terminal, respectively, drains of said first and second P-FETs being coupled together and forming said output (155) of said comparator, a gate of said first P-FET being coupled to the source of said second P-FET and a gate of said second P-FET being coupled to the source of said first P-FET, said first and second P-FETs pulling said control input of said second transistor (113) alternatively to said node (115) or to said second reference terminal (191), whichever has higher potential. A method for protecting a second transistor (113) in a circuit (100) having a first reference terminal (119) at a voltage V R1 (GND), a second reference terminal (191) at a voltage V R2 (V CC ) and a node (115) for coupling said circuit to a further circuit (20) that can apply a further voltage V PAD to said node, wherein the second transistor (113) and a first transistor (110) each have main electrodes and a control electrode with the first and second transistor being serially coupled by their main electrodes between said first reference terminal (119) and said node (115) so as to support potential V DS 3 and V DS 1 respectively, and wherein the first transistor (110) has its control electrode receiving an input signal (195), the method comprising comparing V PAD and V R2 and switching the control input of said second transistor (113) to either V PAD or V R2 dependent upon whether the voltage V PAD or V R2 has the greater magnitude such that V DS 3 is less than a predetermined voltage (V DS MAX ) when V PAD >V R2 .

Inventors: AFEK YACHIN, SHOR JOSEPH, YOSEFIN MARK, AFEK, YACHIN, SHOR, JOSEPH, YOSEFIN, MARK
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1998
Main classification: H02H9
IPC codes: H03K17, H03K19, H03F1