SLAVE DSP REBOOTS STALLED MASTER CPU

Abstract: A digital home entertainment system comprises one or more slave processors, e.g, DSPs, for processing specific tasks, and a master processor, e.g., a CPU, for control of the system. The slave processor is capable of rebooting the master processor if the master processor has stalled. This slave-controlled rebooting avoids manual cold rebooting of the system and is particularly advantageous in open-architecture multimedia systems with asynchronously cooperating components.

Description: SLAVE DSP REBOOTS STALLED MASTER CPU The invention relates to an information processing system, in particular to a consumer electronics home entertainment system, with a slave processor for processing a task, and a master processor for control of the system, as defined in the precharacterizing part of claim 1. A typical multi-processor system with a hierarchical organization comprises one or more slave processors, each processing a specific task, and a master processor driving one or more slave processors and controlling the system. For example, the system is a multimedia consumer apparatus or a digital entertainment system, wherein the master is a CPU and the slaves are DSPs. One of the slaves processes audio data, another slave processes video data. Suppose that, in the multi-processor system, the master encounters an event that causes the master to stop working. For example, the master has lost its stack, or its memory is completely filled. The result is that the entire system stops functioning and has to be rebooted, typically by hand. The power has to be turned off before the system can start afresh (i.e. , cold reboot). Accordingly, the complete state of the system may be lost. Fortunately, typical consumer apparatus of the type described, which are commercially available now or in the near future, are well protected against such disasters, since all processes active on the system have been well tried out by the OEM during the system's development. An object of the invention is therefore to provide an asynchronously multiprocessor system that limits the rather disastrous consequences of a stalled master or a "hung" system. It is another object to render a cold reboot power sequence unnecessary, which is of particular interest to apparatus meant for the consumer market. If anything goes wrong with the master, the consumer him/herself is the sole external agent available to jumpstart the system. Most consumers are not, and should not need to be, particularly knowledgeable about the nuances of system architectures beyond where to put the power plug and how to operate the remote. It is clear that having to do a cold reboot now and again is not only particularly unattractive, but a major drawback. Consumer apparatus have been becoming increasingly more sophisticated. Modular configurations and open architectures are believed to form the paradigm for such apparatus. The inventors have realized, however, that failure of the master may occur more frequently in such an architecture, typically when its components are cooperating asynchronously. The reason for this is the following. An open architecture system can be modified and extended at will. Future functionalities, presently unknown, or customized functionalities, will be added to the existing system as an after-market add-on. Proper functioning under each and every circumstance cannot be guaranteed anymore, simply because many of all possible processes could not have been contemplated in advance by the manufacturer, let alone tried out in the development phase. To this end, the invention provides an information processing system with a slave processor for processing a task, and a master processor for control of the system. The slave processor is operative to reboot the master processor if the master processor has stalled. The slave detects that the master has stalled by monitoring the master's heart beat. The automatic reboot performed by the slave allows the temporarily inactivated master to start working again without intervention of the user. Preferably, periodic state savings are performed allowing the system to pick up at the last known valid checkpoint. Since almost all of the stalls occur as a consequence of mutually interfering events in the asynchronous system, restarting the master at the last known valid checkpoint solves the problem in most of the cases. The system according to the invention is particularly useful in a consumer apparatus, wherein the DSP of the slave is capable of rebooting the master's CPU without the user's interfering. These and other aspects of the invention will be explained in further detail by way of example and with reference to the accompanying drawing. FigJ is a block diagram of a system according to the invention. FigJ is a block diagram of a multiprocessor system 100 according to the invention. System 100 has a master processor 102 and one or more slave processors 104 and 106. Master 102 drives the entire system 100. Slave 104 and 106 each process a respective one of specific tasks under control of master 102. The system is, for example, a multimedia system with an open architecture, wherein master 102 is a CPU and slaves 104 and 106 are DSPs (Digital signal processors). Slaves 104 and 106 may communicate with each other. Master 102 has program memory 108. Slave 104 has program memory 110, and slave 106 has program memory 112. Master 102 sends a data stream 118 to slave 104 wherein periodically a special command occurs, the sole purpose of which is to notify slave 104 of the fact that master 102 is still running. The special command is commonly referred to as "heart beat" . Typically, a heart beat is sent one every second. Slave 104 has a fail safe timer 114. Upon receipt of a heart beat, slave 104 resets its timer 114. Timer 114 expires after, say, 2 seconds, which is substantially longer than the time period between two successive heart beats. When master 102 stalls, slave 104 does not receive the heart beat anymore, and timer 114 expires. This confirms that master 102 has become inert. Slave 104 then resets master 102. In a first embodiment, the reset brings master 102 back to the very beginning of the program(s) it was supposed to execute, and master 102 starts anew from ground zero. In a second embodiment, master 102 is coupled to a checkpoint memory 116, typically a magnetic disk. Prior to the failure, master 102 has been updating checkpoint memory 116 every N heart beats with the system state. For example, every 10 heart beats the content of the registers (not shown) of master 102, including the I/O registers, control registers, and the content of memory 108 are stored in memory 116. Memory 116 thus stores periodically a snapshot of the system, i.e. , all information that unambiguously defines the state of system 100 that is necessary to restore the state of the system. Now, when slave 104 notes that master 102 has stalled, slave 104 sends a reset to master 102. When master 102 starts to reboot it sends a response to slave 104 indicating it rebooted. This response enables slave 104 to issue a command to master 102 to fetch the last valid state recorded in memory 116, to reload the registers and memory 108 with this valid state, and start executing the program code from there on. Slave 104 can notify the user, for example, via a short message on the system's display (not shown), that a problem occurred, has been solved, and that system operation has been resumed.

Claims: CLAIMS: 1. An information processing system with a slave processor for processing a task, and a master processor for control of the system, wherein the slave processor is operative to reboot the master processor if the master processor has stalled. 2. The system of claim 1, wherein: - the master processor periodically sends a heart beat to the slave processor; - the slave processor has a timer with a maximum timing interval substantially longer than a time period between two successive heart beats; - the slave processor resets the timer upon receipt of the heart beat; and - the slave processor starts rebooting the master upon expiry of the maximum timing interval. 3. The system of claim 2, wherein: - the system comprises a checkpoint memory for periodically saving a valid current state of the system; - upon detection of the master processor having stalled, the slave processor issues a command to the master processor to re-establish the last valid state of the system as saved in the checkpoint memory.

Inventors: FOSTER PAUL DAVIS, PANCOAST STEVEN TAYLOR, FOSTER, PAUL, DAVIS, PANCOAST, STEVEN, TAYLOR
Applicants: KONINKL PHILIPS ELECTRONICS NV, PHILIPS SVENSKA AB, KONINKLIJKE PHILIPS ELECTRONICS N.V., PHILIPS AB
Application year: 1998
Main classification: G06F1
IPC codes: G06F1, G06F15