INSTRUCTION ALIGNMENT UNIT EMPLOYING DUAL INSTRUCTION QUEUES FOR HIGH FREQUENCY INSTRUCTION DISPATCH

Abstract: A microprocessor includes an instruction alignment unit for locating instructions and conveying the located instrutions to a set of decode units. The instruction alignment unit includes dual instruction queues. The first instruction queue receives instruction blocks fetched from the instruction cache. The instruction alignment unit uses instruction identification information provided by the instruction cache to select instructions from the first instruction queue for conveyance to the second instruction queue. Additionally, the instruction alignment unit applies a predetermined selection criteria to the instructions within the second intruction queue in order to select instructions for dispatch to the decode units. Selection logic for the first instruction queue need not consider the type of instruction, etc., in selecting instructions for conveyance to the second instruction queue. Selection logic for the second instruction queue considers instruction type, etc., in determining which instructions to dispatch.

Description: TITLE: INSTRUCTION ALIGNMENT UNIT EMPLOYING DUAL INSTRUCTION QUEUES FOR HIGH FREQUENCY INSTRUCTION DISPATCH BACKGROUND OF THE INVENTION 1 Field ol the Invention This mvention relates to the field ol microprocessors and more particularly to instruction alignment mechanisms w itlun microprocessors 2 Descnption ot the Related Art Superscalar microprocessors achiev e hiirh performance b \ executing multiple instructions per clock cv cle and b . choosing the shortest possible clock cvcle consistent with the design As used herein the term clock e \ cle' refers to an inters al ot time accorded to . anous staees ol an instruction processine pipel c w itlun the microprocessor Storage dev ices (e a registers and arra \ s) capture their v alues according to the clock ev cle 1 or example a storage dev ice mav capture a value according to a πsine or tailing edge of a clock signal defimne the clock c . cle The storage deuce then stores the \ alue until the subsequent rising or tailing edge ot the clock signal respecti \ eh The term instruction processing pipeline is used herein to refer to the logic circuits emplo \ ed to process instructions in a pipelined tashion Although the pipeline ma\ be div ided into anv number ot stages at wlueh portions ol instruction processing are performed mstruction processing generaliv comprises tetchmg the instruction decoding the instruction executing the instruction and stormg the execution results in the destination identified b . the instruction Microprocessor designers often design their products in accordance ith the \86 microprocessor architecture in order to take advantage ot its w idespread acceptance in the computer ndustrv Because the \86 microprocessor architecture is perv asive mam computer programs aie written in accordance w ith the aichitecture X86 compatible microprocessors execute these computer programs thereb . becoming moie attracli \ e to computer s\ stem designers who desire \86-eapable computer s\ stems Such computer s\ stems arc oiten well received itlun the industry due to the w ide range ol av ailable computer programs The x86 micropiocessor specifies a \ aπable length mstruction set (I e an instruction set in which \ anous instructions employ dilfenng numbers ot bvtes to specif, that instruction) For example the 80386 and later v ersions ot x86 microprocessors emplo \ between 1 and 15 bvtes to specih a particular instruction Instructions hav e an opcode which mav be 1 -2 bvtes and additional b \ tes mav be added to specif \ addressing modes operands and additional details regarding the mstruction to be executed Untortunateh ha\ mg variable bvte lenelh instructions creates numerous problems tor dispatchmg multiple instructions per clock evele Because the instructions have diilering numbers ot bvtes an instruction mav begin at an\ memorv address Converseh fixed length instructions t \ picallv begin at a known location For example a 4 bvte fixed length mstruction set has instructions which begin at 4 bvte boundaries within memorv (l e the two least significant bits are zeros tor the memon addresses at which instructions begm) In order to locate multiple v anable bvte length instructions during a clock c\ cle instruction bvtes fetched by the microprocessor mav be senallv scanned to determine instruction boundanes and therebv locate instructions winch mav be concurrently dispatched Serial scanning involves a large amount ot logic and tvpicallv a large number ot cascaded logic lev els For high frequency (1 e short clock cvcle tune) microprocessois large numbers ot cascaded logic levels mav be deletenous to the performance ol the microprocessor Some microprocessor designs employ predecodmg to identify the beginning and end ot instructions as the instructions are stored into an instruction cache within the microprocessor Ev en with predecodmg locating and dispatching multiple instructions per clock cv cle is a complex and often clock-cvcle-hmiting operation Multiple lev els of multiplexing are employ ed and significant bussing between the multiplexors and the mstruction bvtes being dispatched is needed to allow arbitrarv selection ol bv tes from the instruction bvtes being examined lor dispatch The first mstruction to be dispatched mav be located anv where withm the mstmetion bv tes The second mstruction to be dispatched is then located at the end ot the first mstruction etc SUMMARY OF THE INVENTION riie problems outlined above are in large part solved bv a microprocessor in accordance with the present invention The microprocessor desenbed herein includes an mstruction alignment unit lor locating instructions and convev me the located instructions to a set ot decode units The mstruction alignment unit includes dual instruction queues The first mstruction queue receiv es mstruction blocks letehed from the instruction cache The mstruction alignment unit uses instruction identification information provided bv the instruction cache to select instructions trom the first instruction queue tor com ev ancc to the second instruction queue Additionally the instruction alignment unit applies a predetermined selection cπteπa to the instructions the second instruction queue in order to select instructions for dispatch to the decode units Advantaeeouslv the location ol vanable bvte length instructions w itlun the instruction block is separated Irom the application ot the predetermined selection cnlcπa Selection loaic for the first instruction queue mav not consider the ty pe of instruction etc m seleetine instructions lor conv eyance to the second instruction queue Instead the selection logic may locus on quickly locatinε the first instructions (in program older) v\ itlun the queued instruction blocks Selection logic tor the second instruction queue may then consider instruction type etc in deteπnrnmc which instructions to dispatch Therelore the dual bv te queue mstruction alignment unit may support a lugh frequency implementation In addition since the second instruction queue is refilled upon dispatch ol instructions bv the first instruction queue a relativ elv large number ot instructions may be available tor dispatch from the second by te queue in anv given clock cycle In other words the bandwidth ol instructions dispatched trom the instruction alignment unit mav be high I heretore a In eh bandwidth high trequencv instruction ahenment unit mav be leahzed bv employing the dual mstruction queue implementation described herein Broadlv speaking the present invention contemplates an instruction alignment unit comprising a first instruction queue a second instruction queue and a first control unit Coupled to receiv e a plurality ot mstruction blocks the first instruction queue is configured to store the plurality ol mstruction blocks The second instruction queue is coupled to receive a plurality ot instruction identifiers corresponding to a plurality ol instructions trom the first instruction queue The second instruction queue is configured to store the plurality ot mstruction identifiers Coupled to the first mstruction queue and the second mstruction queue, the first control unit is configured to select the plurality ol instructions trom the plurality ot mstruction blocks Additionally, the first control unit is configured to select a number ol the plurality ot mstructions based upon a number ot instructions stored in the second instruction queue The present mvention further contemplates a method for aligning instructions from an instruction cache to a plurality ot decode umts m a superscalar microprocessoi A plurality ot instruction blocks is received from the mstruction cache mto a first instruction queue A plurality ol instructions are selected trom the plurality ot instruction blocks The plurality ot mstructions are stored into a second instruction queue One or more instructions trom the second instruction queue are selected lor dispatch to the plurality ot decode units Moreover, the present invention contemplates a superscalar microprocessor comprising an instruction cache, an instruction alignment unit, and a lurality ot decode umts The mstruction cache is configured to store instructions and is further configured to provide a plurality ot instruction blocks in response to instruction letchmg Coupled to the instruction cache to receive the plurality ol instruction blocks the mstruction alignment umt is configured to store the plurality ol instruction blocks mto a first instruction queue Additionally, the instruction alignment unit is configured to select a plurality ol instructions irom instruction blocks stored in the first mstruction queue and to store the plurality ot instructions in a second instruction queue Still further, the instruction alignment unit is contigured to select one or more instructions from the instructions stored in the second instruction queue tor dispatch based upon a predefined selection cnteria Coupled to receive the one or more mstructions lrom the mstruction alignment unit, each one ol the plurality ol decode umts is configured to receive a different one ot the one or more instructions and to decode the received mstruction BRIEF DESCRIPTION OF THE DRAWINGS Other ob|ects and advantages ol the invention vull become apparent upon readme the tollowing detailed descnption and upon reference to the accompanying draw gs m vvliieh Fig 1 is a block diagram ot one embodiment ot a superscalar microprocessor Fig 2 is a block diagram ot one embodiment ol a pair ot decode units shown m Fig 1 Fig 3 is a block diagram ot one embodiment of an mstruction cache and an instruction alignment unit shown in Fig 1 Fig 4 is a more detailed block diagram illustrating one embodiment of the mstruction alignment umt shown m Fig 3 Fig 5 is a diagram illustrating mstruction identification information corresponding to one instruction within an mstruction block accordmg to one embodiment ol the instruction alignment umt Fig 6 is a diagram illustrating mstruction identification information which is shared among the instructions yy ithin an mstruction block accordmg to one embodiment ol the instruction alignment unit Tig 7 is a diagram illustrating mstruction identification information stored in an mstruction position within a second bvte queue accordmg to one embodiment ol the instruction alignment unit Fig 8 is a block diagram of one embodiment ol a computer sv stem including the microprocessor shown While the invention is susceptible to various modifications and alternative forms specific embodiments thereof are shown bv ay of example m the draw ings and w ill herein be descnbed in detail It should be understood that the drawmgs and detailed descnption thereto are not intended to limit the rnv ention to the particular torm disclosed but on the contrary the mtention is to cov er all modifications equivalents and alternatives talline within the spint and scope ot the present inv ention as defined bv the appended clauns DETAILED DESCRIPTION OF THE INVENTION Turning now to Fig 1 a block diagram ol one embodiment ot a microprocessor 10 is shown Microprocessor 10 includes a pretetch/predecode umt 12 a branch prediction umt 14 an mstruction cache 16 an instruction alienment unit 18 a plurahtv ol decode units 20A-20C a plurality ol reserv ation stations 22A-22C a plurality ot functional units 24A-24C a load/store umt 26 a data cache 28 a register tile 30 a teorder buff er 32 and an MROM umt 14 Elements retened to herein with a particular reference number lollowed bv a letter v\ ill be collectiv ely reterred to bv the reference number alone Tor example decode umts 20A-20C w ill be collectively referred to as decode umts 20 Prefetch/predeeode unit 12 is coupled to receiv e instructions trom a mam memorv subsvstem (not sho n) and is further coupled to instruction cache 16 and branch prediction umt 14 Similarly branch prediction umt 14 is coupled to mstruction cache 16 Still further branch prediction unit 14 is coupled to decode umts 20 and functional units 24 Instruction cache 16 is further coupled to MROM unit 34 and instruction alignment unit 18 Instruction alienment unit 18 is m turn coupled to decode umts 20 Each decode umt 20A-20C is coupled to load/store umt 26 and to respectiv e reservation stations 22A-22C Reservation stations 22A-22C arc further coupled to respective functional units 24A-24C Additionally decode units 20 and reserv ation stations 22 are coupled to register file 30 and reorder butter 32 Functional umts 24 are coupled to load/store unit 26 register file 30 and reorder buffer 32 as well Data cache 28 is coupled to load/store umt 26 and to the main memorv subsvstem Finally MROM unit 34 is coupled to decode umts 20 Generally speaking instruction alignment unit 18 is confieured to receive mstruction blocks trom instruction cache 16 and to align instructions from the mstruction blocks to decode units 20 Instruction alienment umt 18 employ s a first bvte queue lor stonng the mstruction blocks Instruction alignment unit 18 selects instructions from the bvte queue and stores them into a second bvte queue Based upon predetermined selection cπtena mstruction alignment umt 18 selects one or more instructions trom the second bv te queue lor co ev ance to decode units 20 Advantageouslv the relatively large number ot instructions available in the instruction blocks is reduced to a smaller number of mstructions via the first stage ot selection from the first bvte queue into the second bvte queue Because the second bvte queue stores a smaller number of instructions the selection cnteπa tor selecting instructions lor dispatch to the decode umts 20 mav be applied ev en m a high frequency 5 implementation Additionally the selection cπtena mav be more complex thereby allow ing more instructions to be selected tor concurrent dispatch than selection cπtena applied to a larger number ot mstructions Multiple instructions mav thereby be identified tor dispatch An mstruction block as used herein eompπses a fixed number ot bvles ithm which up to a maximum number of instructions per block are identified A particular mstruction block may include fewer instructions than 0 the maximum number ot mstructions per block ithm its fixed number ot bvles Alternatively a given fixed number of bvtes within mstruction cache 16 mav include more instructions than the maximum number of instructions per block In the latter case tvv o or more instruction blocks are formed trom the giv en fixed number ot bv tes Each mstruction block includes the fixed number ot bvles but identities different instructions within the fixed number ot bv tes as compπsine the mstruction block The fixed number ol by tes are aliened to a boundary "> of the fixed number ol bv tes In one embodiment mstruction blocks comprise eight bvles aligned on an eicht bvte boundary and the maximum number ot instructions per block is three The maximum number ot instructions per block is selected because the average length ol an x86 instruction is three bvles Therefore each eieht bvtes ol instruction code includes 2 2/3 mstructions on average It is noted that the maximum number of instructions per block mav be varied in various embodiments as a matter ot design choice 0 Instruction cache 16 is a high speed cache memorv provided to store mstructions Instructions are tetched trom mstruction cache 16 and dispatched to decode units 20 In one embodiment mstruction cache 16 is configured to store up to 32 kiloby tes ot instructions in a 4 way set associativ e structure having 32 bvte lines (a bvte comprises 8 binary bits) Instruction cache 16 may additionally employ a ay prediction scheme order to speed access tunes to the mstruction cache Instead ot accessme tags identify me each line ol instructions and s comparmg the taes to the letch address to select a w y instruction cache 16 predicts the y\ av that is accessed hi lliis manner the way is selected pπoi to accessing the mstruction storage The access time ot mstruction cache 16 may be similar to a direct -mapped cache A. tag compaπson is performed and it the ay prediction is incorrect the correct instructions are tetched and the lneonect instructions arc discarded It is noted that instruction cache 16 mav be implemented as a tullv associativ e set associative or direct mapped confieuration 0 Instructions are tetched from mam memory and stored into mstruction cache 16 bv pretetch/predecode unit 12 Instructions mav be prefetched prior to the request thereot trom mstruction cache 16 in accordance with a prefetch scheme A v ariety of preletch schemes mav be employ ed bv pretetcli/predecode unit 12 As pretetch/predecode unit 12 translers instructions trom main memorv to instruction cache 16 pretetch/predecode umt 12 generates three predecode bits lor each bv te of the mstructions a start bit an end bit and a functional bit 5 The predecode bits lorm tags mdicative of the boundaries ot each instruction The predecode tags may also convey additional information such as whether a given instruction can be decoded directly by decode units 20 or whether the mstruction is executed bv invoking a microcode procedure controlled bv MROM unit 34 as will be descnbed in greater detail below Still further pretetch/predecode unit 12 mav be configured to detect branch instructions and to store branch prediction information corresponding to the branch instnictions into branch prediction unit 14 One encoding ol the predecode tags lor an embodiment ot microprocessor 10 emplovme a vanable bvte length instruction set will next be descnbed A vanable bvte length mstruction set is an instruction set m which different instructions mav occupy diffenng numbers ot bvtes An exemplary variable bv te length mstruction set employed bv one embodiment of microprocessor 10 is the x86 mstruction set In the exemplary encoding it a given bv te is the first bvte of an instruction the start bit tor that bvte is set II the bvte is the last bvte ol an mstruction the end bit tor that bvte is set Instructions which mav be directly decoded by decode umts 20 are relened to as fast path mstructions The remaining \86 instructions are referred to as MROM mstructions accordmg to one embodiment For fast path instructions the functional bit is set tor each prefix bvte included in the mstruction and cleared tor other bvles Alternatively tor MROM mstructions the functional bit is cleared for each prefix bvte and set tor other bvles The type of mstruction may be determined bv exami nε the lunctional bit corresponding to the end bvte If that functional bit is clear the instruction is a last path instruction Conversely it that lunctional bit is set the instruction is an MROM instniction Fhe opcode of an instniction may thereby be located withm an instruction winch may be directly decoded by decode units 20 as the bvte associated with the first clear functional bit in the instruction Tor example a fast path mstruction including two prefix bvles a Mod R/M bvte and an immediate by te v\ ould hay e start end and functional bits as follows Start bits 10000 End bits 00001 Functional bits 1 1000 According to one particular embodiment early identify mg that an mstruction includes a scale-index-base (SIB) bv tc is advantaεeous tor MROM umt 34 Tor such an embodunent it an mstruction includes at least tvso bvles alter the opcode bvte the lunctional bit for the Mod R/M bvte indicates the piesence ol an SIB bv te Lt the lunctional bit for the Mod R M byte is set then an SIB bvte is present Alternativ ely if the lunctional bit lor the Mod R/M bvte is clear then an SIB bv te is not present MROM mstructions are mstructions which are determined to be too complex tor decode by a smgle decode unit 20A-20C and tor execution bv a smgle functional unit 24A-24C MROM mstructions mav be an example of microcode mstructions Generally microcode mstructions are mstructions which are separated by a microcode umt (e g MROM unit 34) mto two or more mstructions each of which mav be decode by a single decode umt 20A-20C and executed by a corresponding functional unit 24A-24C MROM instructions are executed bv mv okmg MROM umt 34 More specifically when an MROM instruction is encountered MROM umt 34 parses and issues the instruction into a subset ot defined last path instructions to effectuate the desired operation MROM unit 34 dispatches the subset of fast path instructions to decode units 20 A listing ot exemplary \86 instructions categonzed as fast path mstructions will be provided further below Microprocessor 10 employ s branch prediction in order to speculatively fetch instructions subsequent to conditional branch mstructions Branch prediction unit 14 is included to perform branch prediction operations In one embodiment , to two branch target addresses are stored with respect to each 16 bv te portion ol each cache lme in mstruction cache 16 Prefetch/predecode unit 12 determines initial branch targets yvhen a particular line is predecoded Subsequent updates to the branch targets correspondme to a cache lme mav occur due to the execution ol instructions within the cache lme Instruction cache 16 provides an indication ot the mstruction address bemg tetched so that branch prediction unit 14 mav determine which branch tarεet addresses to select tor lormrng a branch prediction Decode umts 20 and functional umts 24 provide update information to branch prediction unit 14 Because branch prediction umt 14 stores tw o tarεets per 16 bvte portion ot the cache line some branch mstructions within the line mav not be stored in branch piediction unit 14 Decode units 20 detect branch mstructions yyhich w ere not predicted bv branch prediction unit 14 Functional units 24 execute the branch instructions and determine it the predicted branch direction is mconect The branch direction mav be ' taken in yyhich subsequent instructions arc tetched trom the target address ot the branch instruction Conversely the branch direction mav be not taken in which subsequent mstructions are fetched lrom memorv locations consecutive to the branch instruction When a mispredicted branch instruction is detected instructions subsequent to the mispredicted branch are discarded lrom the vaπous umts ol microprocessor 10 V v netv ot suitable branch prediction algonthms may be employed bv branch prediction unit 14 Instructions tetched lrom mstruction cache 16 are conveyed to mstruction alienment umt 18 As instructions are tetched lrom mstruction cache 16 the corresponding predecode data is scanned to provide information to mstruction alignment unit 18 (and to MROM umt 34) regarding the instructions bemg tetched Instruction alignment unit 18 utilizes the scanning data to align an mstruction to each ot decode units 20 In one einbodunent instruction alignment unit 18 ahens instructions lrom tliree sets ot eight instruction bvles to decode umts 20 Decode umt 20A receives an mstruction which is pnor to instructions eoncwrentlv receiv ed bv decode umts 20B and 20C (in program order) Similarly decode umt 20B receives an mstruction which is pnor to the instniction concurrently received by decode umt 20C in program order Decode umts 20 are confiεured to decode instructions receiv ed trom mstruction alignment umt 18 Reeister operand information is detected and routed to register file. 30 and reoider butler 32 Additionally if the instructions require one or more memorv operations to be pertoπned decode umts 20 dispatch the memory operations to load/store unit 26 Each mstruction is decoded into a set ot control v alues tor lunctional units 24 and these control values are dispatched to reserv ation stations 22 along with opeiand address information and displacement or immediate data w Inch may be included w ith the instruction Microprocessor 10 supports out ot older execution and thus employ s reorder butter 32 to keep track ot the oπgmal program sequence lor register read and write operations to implement register renaming to allow tor speculativ e mstruction execution and branch misprediction recov erv and to facilitate precise exceptions A temporary storage location withm reorder butter 32 is reserved upon decode of an instruction that involves the update ol a register to thereby store speculativ e register states It a branch prediction is incorrect the results ol speculatively -executed instructions along the mispredicted path can be invalidated m the butter before they are wntten to reeister file 30 Similarly it a particular mstruction causes an exception mstructions subsequent to the particular instruction mav be discarded In this manner exceptions are precise (I e instructions subsequent to the particular mstruction causing the exception are not completed pnor to the exception) It is noted that a particular instruction is speculatively executed it it is executed prior to instructions which precede the particular instruction in program order Preceding instructions may be a branch instruction or an exception-eausmg instruction m which case the speculative results mav be discarded bv reorder butter 32 The instruction control values and immediate or displacement data provided at the outputs ot decode umts 20 are routed directly to respective reservation stations 22 In one embodiment each reservation station 22 is capable of holdmg instniction information (1 e mstruction control values as well as operand values operand tags and/or immediate data) lor up to three pendmg mstructions a aiting issue to the corresponding functional umt It is noted that for the embodiment ot Fig 1 each reservation station 22 is associated with a dedicated functional unit 24 Accordm lv tliree dedicated issue positions are formed bv reserv ation stations 22 and lunctional units 24 In other words issue position 0 is formed bv reservation station 22 A and functional umt 24 A Instructions aligned and dispatched to reservation station 22 A are executed bv functional umt 24A Similarly issue position 1 is formed bv reservation station 22B and lunctional unit 24B and issue position 2 is formed by reserv ation station 22C and functional umt 24C Upon decode ol a particular mstruction it a required operand is a reeister location register address mtonnation is routed to reorder butter 32 and reeister file 30 simultaneously Those ot skill in the art ill appreciate that the x86 register tile includes eicht 32 bit real registers (1 e tvpicallv reiened to as EAX EBX ECX EDX EBP ESI EDI and ESP) In embodiments of microprocessor 10 which employ the \86 microprocessor architecture register file 30 compπses storage locations tor each ot the 32 bit real registers Additional storage locations mav be included withm register file 30 tor αse bv MROM unit 34 Reorder buffer 32 contams temporary storage locations tor results winch change the contents ot these registers to thereby allow out ot order execution A temporary storage location ol reorder buffer 32 is reserv ed tor each mstruction which upon decode is determined to modify the contents ot one ot the real registers Therefore at v anous points durmε execution ot a particular program reorder butter 32 may have one or more locations w hich contain the speculatively executed contents ol a given reeister If following decode ol a civen mstruction it is deteπmned that reorder butler 32 has a previous location or locations assicned to a register used as an operand in the given instruction the leorder butter 32 forwards to the corresponding ieserv tion station either 1 ) the v alue in the most recently assiened location or 2) a tae tor the most recently assigned location it the value has not vet been produced bv the functional umt that ill ev entually execute the prev ious instruction II reorder butter 32 has a location reserv ed lor a given register the operand value ( oi reorder butlei tag) is prov ided liom reorder butter 32 rather than lrom register file 30 II there is no location reserved lor a required register m reorder butter 32 the v alue is taken directly trom register file 30 If the operand conesponds to a memory location the operand v alue is provided to the reservation station through load/store umt 26 In one particular embodiment reorder buffer 32 is contigured to store and manipulate concurrently decoded mstructions as a umt Tins configuration will be referred to herein as hne-onented Bv manipulating several instructions together the hardware employed yyithin reorder butter 32 mav be simplified For example a lme-onented reorder butter included in the present embodiment allocates storage sufficient tor instruction information pertaining to three instructions (one trom each decode umt 20) whenever one or more instructions arc dispatched bv decode units 20 Bv contrast a variable amount ot storage is allocated in conventional reorder buffers dependent upon the number ot instructions actually dispatched A comparatively larger number ot logic gates may be required to allocate the variable amount of storage When each ol the concurrently decoded instructions has executed the mstruction results are stored mto register file 30 simultaneously The storage is then tree tor allocation to another set of concurrently decoded instructions Additionally the amount ot control logic circuitry employed per instruction is reduced because the control logic is amortized over several concunentlv decoded mstructions A reorder butter tag identify mg a particular instruction mav be div ided mto t o fields a lme tag and an offset tag The lme tag identifies the set ot concurrently decoded instructions including the particular instruction and the offset tag identifies which instruction within the set conesponds to the particular instruction It is noted that stormg mstruction results into register file 30 and Ireemg the corresponding storage is referred to as retiring the mstructions It is further noted that anv reorder buf er configuration mav be employed in various embodiments ot microprocessor 10 As noted earlier reservation stations 22 store instructions until the mstructions are executed bv the eonespondrnε functional umt 24 An mstruction is selected lor execution it (I) the operands ot the instruction have been provided and (n) the operands hav e not vet been prov ided for mstructions which are w itlun the same reservation station 22A-22C and which are pnor to the instruction in program order It is noted that w hen an instruction is executed bv one ot the functional umts 24 the result ot that instruction is passed directly to any reservation stations 22 that are yvaiting lor that result at the same tune the result is passed to update reorder butler 32 (this technique is commonly retened to as result forwarding ) An instruction may be selected tor execution and passed to a lunctional unit 24A-24C during the clock cv cle that the associated result is forwarded Reservation stations 22 route the forwarded result to the functional unit 24 in tins case In one embodiment each ol the lunctional units 24 is configured to perform mteeer anthmetic operations ot addition and subtraction as well as shifts rotates logical operations and branch operations The operations are performed in response to the control v alues decoded lor a particular instruction bv decode units 20 It is noted that a fioatmg point unit (not shown) may also be employed to accommodate floating point operations The floating point umt may be operated as a coprocessor receiv ing instructions lrom MROM unit 34 and subsequently eommunicatinε with reorder butter 32 to complete the instructions Additionally functional umts 24 mav be eonfigured to perform address generation tor load and store memory operations pcrtoπned by load/store unit 26 Each ot the lunctional units 24 also prov ides mloπnation regardmg the execution ot conditional branch instructions to the branch prediction umt 14 It a branch prediction was lnconect branch prediction umt 14 flushes mstructions subsequent to the mispredicted branch that hav e entered the instruction processing pipeline and causes fetch ol the required instructions lrom instruction cache 16 or main memorv It is noted that in such situations results of mstructions m the oπgmal program sequence which occur after the mispredicted branch instruction are discarded including those which were speculativ ely executed and temporaπly stored in load/store umt 26 and reorder butter 32 Results produced bv functional umts 24 are sent to reorder butter 32 if a register value is being updated and to load/store umt 26 if the contents ol a memory location are changed II the result is to be stored in a register reorder butter 32 stores the result in the location reserved tor the value ol the register when the instruction vy as decoded A plurality of result buses 38 are included tor tony arding ol results trom functional umts 24 and load/store unit 26 Result buses 38 convey the result generated as well as the reorder butter tag identify mg the instruction bemg executed Load/store unit 26 provides an interface between functional umts 24 and data cache 28 In one embodiment load/store umt 26 is configured with a load/store butter having eight storage locations for data and address information lor pending loads or stores Decode umts 20 arbitrate lor access to the load/store umt 26 When the butter is full a decode umt must wait until load/store umt 26 has room tor the pending load or store request information Load/store umt 26 also performs dependency checking lor load memory operations aeamst pending store memorv operations to ensure that data coherency is maintained A memorv operation is a transfer ol data between microprocessor 10 and the mam memory subsystem Memory operations mav be the result ol an instruction which utilizes an operand stored in memorv or mav be the result ot a load/store mstruction which causes the data transfer but no other operation Additionally load/store unit 26 mav mclude a special register storage tor special registers such as the segment registers and other registers related to the address translation mechamsm defined bv the x86 microprocessor architecture In one embodiment load/store umt 26 is configured to perform load memory operations speculatively Store memory operations are perforated m program order but mav be speculativ ely stored into the predicted yvav It the predicted ay is incorrect the data pnor to the store memory operation is subsequently restored to the predicted way and the store memory operation is performed to the conect w ay In another embodiment stores mav be executed speculatively as vv ell Speculatively executed stores are placed mto a store butler along with a copv ol the cache lme pnor to the update If the speculativ elv executed store is later discarded due to branch misprediction or exception the cache line mav be restored to the v alue stored in the buff er It is noted that load/store u t 26 mav be configured to perform any amount ot speculative execution including no speculative execution Data cache 28 is a high speed cache memorv prov ided to temporarily stoic data bemg transferred between load/store unit 26 and the mam memory subsy stem In one embodiment data cache 28 has a capacity ot stormg up to sixteen kilobytes ot data in an eight way set associativ e structure Similar to instruction cache 16 data cache 28 mav employ a way prediction mechamsm It is understood that data cache 28 mav be implemented in a vanetv ot specific memorv conlieurations mcludinε a set associative configuration In one particular mbodiment ol microprocessor 10 employing the \8o microprocessor architecture instruction cache 16 and data cache 28 are lmeailv addressed The lmear address is formed lrom the offset specified bv the instruction and the base address specified bv the seεment portion ol the \86 address translation mechamsm Lmear addresses mav optionally be translated to phy sical addresses tor accessing a mam memory The lmear to physical translation is specified bv the pagmg portion ot the x86 address translation mechamsm It is noted that a lmear addressed cache stores linear address tags A set ol physical tags (not shown) mav be employed lor mapping the linear addresses to physical addresses and for detectmg translation aliases Additionally the physical tag block mav perform lmear to physical address translation Fuming now to Fig 2 a block diagram ot one embodiment of decode umts 20B and 20C is show n Each decode umt 20 receives an instruction lrom instruction alignment unit 18 Additionally MROM unit 34 is coupled to each decode unit 20 for dispatchine last path mstructions corresponding to a particular MROM mstruction Decode umt 20B compnses earlv decode unit 40B multiplexor 42B and opcode decode unit 44B Similarly decode umt 20C mcludes earlv decode unit 40C multiplexor 42C and opcode decode umt 44C Certain instructions in the x86 instruction set are both fairlv complicated and frequently used In one embodiment ot microprocessor 10 such instructions include more complex operations than the hardware included within a particular functional unit 24A-24C is configured to perform Such instructions are classified as a special type of MROM instruction relerred to as a 'double dispatch mstruction These instructions are dispatched to a pa r ol opcode decode umts 44 It is noted that opcode decode units 44 are coupled to respectiv e reservation stations 22 Each ot opcode decode units 44A-44C forms an issue position with the corresponding reservation station 22A-22C and functional umt 24A-24C Instructions arc passed lrom an opcode decode unit 44 to the corresponding reservation station 22 and further to the correspond nc functional umt 24 Multiplexor 42B is mcluded tor selecting between the instructions provided bv MROM unit 34 and bv earlv decode unit 40B During times in which MROM unit 34 is dispatclung instructions multiplexor 42B selects instructions provided bv MROM unit 34 At other tunes multiplexor 42B selects mstructions prov ided bv earlv decode unit 40B Snnilarlv multiplexor 42C selects bet een mstructions provided bv MROM unit 34 early decode umt 40B and earlv decode unit 40C The mstruction lrom MROM unit 34 is selected dunng tunes in winch MROM umt 34 is dispatch e mstructions Dunne tunes in w hich the earlv decode unit w ithm decode umt 20A (not shown) detects a double dispatch instruction the instniction lrom early decode umt 40B is selected bv multiplexor 42C Otherw ise the mstruction lrom early decode unit 40C is selected Selecting the mstruction lrom earlv decode umt 40B mto opcode decode unit 44C allows a fast path mstruction decoded bv decode unit 20B to be dispatched concurrently w lth a double dispatch instruction decoded bv decode umt 20A According to one embodiment employ mg the \86 instruction set early decode units 40 perform the tolloyying operations (l) merge the prefix bytes ot the instruction into an encoded prefix bvte (n) decode unconditional branch instructions (w Inch mav mclude the unconditional )ump the CALL and the RETURN) which were not detected duπnc branch prediction (nι)deeode source and destination flags (IV ) decode the source and destination opeiands which are reeister operands and geneiate operand size information and (v ) determine the displacement and/or inunediate size so that displacement and umnediate data mav be routed to the opcode decode unit Opcode decode units 44 are configured to decode the opcode ot the mstruction producmg control v alues tor functional unit 24 Displacement and immediate data are routed yy ith the control values to reserv ation stations 22 Since earlv decode units 40 detect operands the outputs ot multiplexors 42 are routed to register file 30 and reorder butter 32 Operand values or tags mav thereby be routed to reserv ation stations 22 Additionally memory operands are detected bv earlv decode umts 40 Therefore the outputs ol multiplexors 42 are routed to load/store umt 26 Memorv operations corresponding to instructions hav mg memorv operands are stored bv load/store umt 26 Turmne now to Fig 3 a block diagram ol one embodiment of instruction cache 16 and instruction alignment unit 18 is shown Instruction cache 16 mcludes an mstruction cache storage and control block 50 and an instruction scanning umt 52 Instruction alignment unit 18 includes a first bvte queue 54 and a second bvte queue 56 Instruction cache storage and control block 50 includes storage lor instruction cache lines and related control circuitry for fetching instructions from the storage for selectmg cache lines to discard when a cache miss is detected etc Instruction cache storage and control block 50 receives fetch addresses trom branch prediction umt 14 (sho n in Fig 1) in order to tetch instructions lor execution by microprocessor 10 Instruction bv tes tetched from mstruction cache storage and control block 50 are conveyed to instruction scannmg unit 52 upon an instructions bus 60 Instruction bvles are com eyed upon mstructions bus 60 as well as corresponding predecode data (e g start end and lunctional bits) In one embodiment sixteen bvtes stored in contiguous memorv locations are conveyed upon mstructions bus 60 along w ith the conespondmg predecode data The sixteen bvtes torm either the upper or lower halt ot the 32 bvte cache lme employed bv mstruction cache 16 accoidmg to the present einbodunent The upper halt ot the cache lme is the half stored in memorv addresses hav mg larger numerical y alues while the lower halt is stored m memory addresses having smaller numerical v alues Additionally instruction scanning umt 52 receiv es information reearding the bytes w ithm the sixteen bvtes wluch are to be conveyed as mstructions to instruction alignment unit 18 Instruction by tes at the beemmne ot the sixteen bvles mav be ignored if the bvtes are tetched as the target ot a branch instruction and the target address identifies a bv te other than the first bvte ot the sixteen bvtes Additionally it a branch instruction is itlun the sixteen bv tes and branch prediction umt 14 predicts the branch taken then bvtes subsequent to the branch mstruction w ithm the sixteen bytes are ignored Instruction scanning umt 52 scans the predecode data associated with the bv tes which are to be conv eved as mstructions to instruction alignment unit 18 Instruction scannmg unit 52 div ides the sixteen bvtes conv ey ed bv instruction cache storage and control block 50 mto two portions comprising eight contieuous bvtes each One portion toπns the lower hall ot the sixteen bv tes (ι e the bvtes stored at smaller numerical addresses than the bvles lorming the upper hall ol the sixteen bvles) I he other portion loπns the upper halt ot the sixteen bv tes I herelore an eight bvte portion tonns one ot tour quarters ot the 32 bvte cache lme employed by mstruction cache storage and control block 50 accordmg to the present embodunent As used herein bvtes are contieuous it they are stored in contiguous memory locations in the main memorv subsvstem It is noted that particular sizes ot v anous components are used herein tor claπtv ot the description Anv size may be used lor each component w ithin the spirit and scope ot the appended claims Instruction scanning umt 52 scans the predecode data ol each portion of the mstruction bytes independently and in parallel These portions scanned bv scanning umt 52 comprise the fixed number ot bv tes defined to be an mstruction block Instruction scanning umt 52 therefore scans the predecode data to identify up to the maximum number ol instructions per block The instruction bvtes and mstruction identification information εenerated bv instruction scanning umt 52 are conveved to first bvte queue 54 upon an instructions bus 62 and an mstruction data bus 64 respectively As shown in Fig 3, mstructions bus 62 includes an mstructions - block A bus 62 A and an instructions - block B bus 62B Instructions - block A bus 62A conveys the instruction bvles conesponding to the first instruction block bemg scanned bv instruction scanning umt 52 (m program order) Similarly instructions - block B bus 62B conveys the instruction bvtes conesponding to the second mstruction block bemg scanned by instruction scanning umt 52 Instruction identification information conesponding to the instruction bvtes conveved upon instructions - block A bus 62A is conveved upon mstruction data - block A bus 64A Similarly instruction identification information conesponding to the mstruction bv tes convey ed upon instructions - block B bus 62B is conveved upon mstruction data - block B bus 64B Instruction data - block A bus 64A and instruction data - block B bus 64B comprise mstruction data bus 64 as shown in Fig 3 Each eieht bvte portion and the conesponding instruction identification information forms an instruction block First byte queue 54 receives the instruction blocks conv ev ed and stores them into one ol multiple subqueues included therein In the embodiment sho n first bvte queue 54 includes three subqueues a first subqueue 66A a second subqueue 66B and a third subqueue 66C First subqueue 66A stores the instruction block y hich is foremost among the mstruction blocks stored m first by te queue 54 in program order Second subqueue 66B stores the mstruction block wluch is second m proeram order and third subqueue stores the instruction block which is third in program order It a particular eieht bv te portion as scanned bv mstruction scannmg unit 52 includes more than the maximum number ol instructions per block then the particular eight bv te portion is retamed bv instruction scanning umt 52 Dunng the follow mg clock cy cle the particular eight by te portion is scanned aεain The predecode data corresponding to the previously identified instructions included withm the prev iously dispatched instruction block is invalidated such that mstruction scannmg unit 52 detects the additional mstnictions If the other eight bvie portion concmrentlv receiv ed with the particular eight bvte portion is subsequent to the particular eight byte portion m program order then the other eight byte portion is reseanned as well Tirst bv te queue 54 discards the instruction block received trom the other eieht byte portion in order to retam program order among the mstruction blocks stored m the by te queue A contiol unit 70 withm first bvte queue 54 conveys a bvte queue status upon bv te queue status bus 68 to instniction scanning umt 52 Bvte queue status bus 68 includes a sienal conespondinε to each subqueue 66 The signal is asserted if the subqueue 66 is stoπnε an mstruction block and dcasserted it the subqueue 66 is not storing an instruction block In this manner mstruction scannmg unit 52 mav determine how manv instniction blocks arc accepted bv first bvte queue 54 dunng a clock cvcle It t v mstruction blocks are conv ey ed durrnc a clock cy cle and onlv one mstruction block is accepted mstruction scannmg unit 52 rctams the reacted instruction block and rescans the instruction block in the subsequent clock cvcle As noted above an instruction block may contain up to a maximum number ot instructions (e g tliree in the present embodiment) Additionally eight contiguous bvtes are convey ed tor each mstruction block Howevei due to the v aπable bvte length ot the x86 mstnictions an instruction mav begin withm one set ol eight contiguous bvtes and end in another set of eight contiguous bvles Such an mstruction is referred to as an ov erflow instruction II an overflow mstruction is detected it is identified as the last of the maximum number ot instructions Instead of bemg mdicated as a v alid mstruction withm the mstruction block the overflow instruction is identified as an overflow Instruction identification information is generated but the instruction is handled somewhat differently as will be explamed m more detail below In one einbodunent the mstruction identification information lor each mstruction includes (1) start and end pointers identifying the bvtes at which the identified mstruction begms and ends within the instruction block (n) a valid mask including a bit tor each ot the bv tes withm the mstruction block (in) a bit indicativ e ot whether the mstruction is MROM or fast path (IV) an instruction valid bit indicating that the mstruction is valid and (v) an overflow bit for the last instruction indicating whether or not it is an overflow The valid mask includes a bmarv one bit conesponding to each bvte mcluded within the particular instruction (1 e the bits between the start pointer and end pointer inclusive are set) Zero bits are included tor the other bvtes Additional information conveved with the instruction identification information includes the taken/not taken prediction it the mstruction is a branch mstruction bits indicating which ot the quarters ol the 32 bvte cache lme the eight bvtes conespond to the functional bits trom the predecode data conespondmg to the eight bvtes and a segment limit identity mg the segment limit ithm the eight bvtes tor exception handling The additional information is provided bv mstruction cache storage and control block 50 except for the branch prediction which is provided bv branch prediction unit 14 Control umt 70 examines the instruction identification mtoπnation stored in the subqueues 66 to select mstnictions trom first by te queue 54 Control umt 70 selects a number ot mstructions for convey ance to second bvie queue 56 dependme upon the numbei ot instructions currently stored in the second bvte queue and the number of instruction blocks containing those instructions Generally control unit 70 selects as manv instructions as possible tor conveyance to second bvte queue 56 based upon the av ailable storage withm second bvte queue 56 tor instruction blocks and mstructions In other ords control unit 70 selects a number ot mstructions which either fill instruction position storages 74 or the conespondmε mstruction blocks which are not alreadv stored in instniction bvles storages 72 fill mstruction bv tes storages 72 Second bvte queue 56 includes a plurality ol instruction bytes storages 72A-72C a plurality ot instruction position storages 74A-74C and a control unit 76 Each mstruction bvtes storage 72 is configure to store the mstruction bv tes compnsmg an instniction block Theretore in the embodiment shov\ n second bvte queue 56 may concunentlv store instructions y hich aie drayv n trom up to tliree different mstruction blocks Each instruction position storaec is configured to store an mstruction identifier conespondme to one mstruction Generally speaking an mstruction identifier is information which locates a particular mstruction withm instruction bvles storages 72A-72C The mformation can be used to select the mstruction by tes which comprise the mstruction trom mstruction bytes storage 72A-72C Therefore m the embodiment shown second bvte queue 56 mav concurrently store mstruction identifiers tor up to three instructions w itlun the instruction bvtes stored m instruction bvles storages 72 Control umt 76 is configured to select mstructions lrom second bv te queue 56 toi conv eyance to decode umts 20 The instruction represented withm each instruction position storage 74 is dispatched to a corresponding decode umt 20 subject to a selection cπtena employed bv control umt 76 Generally the mstruction represented within mstruction position storage 74A mav be dispatched to decode umt 20A dunng a clock cv cle (assuming no pipeline stalls lrom decode units 20 or subsequent pipeline stages) It control unit 76 determines that the instruction represented ithm instruction position storage 74B mav be concurrentlv dispatched w ith the instruction represented withm instruction position storage 74A then the mstruction mav be dispatched to decode umt 20B Similarly it control unit 76 determines that the instruction represented withm instruction position storage 74C may be concurrentlv dispatched with the instructions represented within instruction position storages 74A-74B. then the instruction mav be dispatched to decode umt 20C Upon dispatchmg one or more instructions, control unit 76 causes the information within mstruction position storages 74A-74C to be shifted mto adjacent instruction position storages 74A-74B. thereby allowing tor additional mstructions to be conveved trom first bvte queue 54 into second byte queue 56 while maintaining the identified mstructions m program order According to one embodiment, the selection cnteπa employed by control unit 76 is as follows (l) instructions are dispatched in program order, (ii) up to three tast path mstructions can be concurrentlv dispatched. (πι)an MROM instruction can be dispatched it a synchronization signal trom MROM unit 34 is asserted indicating that MROM unit 34 is ready to dispatch an MROM instruction. (IV ) an MROM instruction being dispatched to decode umt 20A mav concunentlv be dispatched with a tast path mstruction to decode position 20B and vice-versa (reterred to as "packing -- see further discussion belov ) (v) at most one MROM instruction is dispatched concunentlv (vi) an MROM instruction is not dispatched to decode unit 20C (a corollary to cntenon (iv)) (vn)at most one predicted taken branch is concurrently dispatched, and (vin)ιnstructιons lrom at most two cache lines are concurrentlv dispatched (each cache line is represented bv an address m reorder buffer 32. and reorder buffer 32 employ's two locations tor stormg addresses tor each set ot concunentlv dispatched instructions in the present embodunent) As mentioned above, an MROM mstruction and a tast path instniction can be "packed" together (l e concurrentlv dispatched) Some MROM instructions are parsed mto two last path mstructions. thereby leav ing a decode umt 20 available tor the concurrent dispatch ot a tast path instruction II MROM umt 34 indicates that the MROM mstruction to be dispatched is a tvso instruction MROM mstruction. then control unit 76 selects both the MROM mstruction and the adμcent last path mstruction tor dispatch Othervyise. the MROM mstruction is dispatched dunng a different clock cvcle than the adjacent last path mstruction If no tast path instruction is adjacent to the MROM instruction, the MROM mstruction is dispatched separate lrom other mstructions regardless ot whether or not the MROM instruction parses mto t o instructions or more than two instructions Bv using first bvte queue 54 and second bvte queue 56. the location ot vanable byte length instructions within the instniction blocks is separated from the dispatch of instructions to decode units 20A These two operations are logically separate trom each other and are generally senal m nature Therefore, first bv te queue 54 performs instruction location Instruction identifiers locatmg the instructions are placed into mstruction position storages 74 Bv first locatmg a small number ot mstructions which are eligible for dispatch and conveying these instructions to second bvte queue 56. first bvte queue 54 provides a smaller pool ot mstructions to which second byte queue 56 may apply the dispatch selection cnteπa Since a relatively small number ol instructions are examined, the selection cnteπa mav be applied using a relatively small number ot cascaded levels ol logic A high frequency implementation ol mstruction alignment mav therebv be realized While the small pool ol mstructions stored bv second bvte queue 56 allows a high frequency implementation the larger pool of mstructions mamtained bv first bvte queue 54 allows tor more mstructions to be fetched trom mstruction cache 16 dunng a giv en clock cvcle than it second bvte queue 56 were employed alone Ihus first bvte queue 54 may increase the averaεe number ot mstructions dispatched dur ne a giv en clock cv cle by rapidly providmg mstructions mto second bvte queue 56 yvhen mstructions are dispatched Advantageously instruction alignment unit 18 mav prov ide both a high bandwidth (l e mstructions dispatched per clock cvcle) and high frequency alignment of mstructions to decode umts 20 It is noted that it mav be advantageous to phv sicallv locate control units 70 and 76 near each other to facilitate high speed communications therebetween In addition it mav be advantageous to duplicate control logic between control umts 70 and 76 to lessen the communication signals employed between the control umts It is noted that MROM mstructions are identified bv mstruction scanning unit 52 as well Instruction scanning umt 52 routes the MROM instructions to MROM unit 34 Howev er the MROM instructions may flow through instruction alignment unit 1 as well In this manner instruction alienment unit 18 may detect the MROM mstruction and co ev it to decode units 20 MROM umt 34 mav then insert the conespondme instructions between earlv decode units 40 and opcode decode units 44 when the MROM mstruction amv es in earlv decode umts 40 as descnbed above w ith respect to Tie 2 Control umt 70 upon detectmg that all instructions within a erven mstruction block hav e been conv eved to second bv te queue 56 shifts the contents ot each subqueue 66B-66C into an adjacent subqueue 66A-66B In tins manner the instruction block which has been exhausted ot instructions is discarded and other instruction blocks are mamtained in program order Additionally the instruction identification inlormation ithin a subqueue 66 is slutted such that the first field within the subqueue 66 stores the first instruction (in program order) remaining ithm the subqueue Howev er o ertlow instructions rcmam in the last field within the subqueue Control umt 70 turther allocates subqueues 66 tor stonne instruction blocks provided by instruction scanning unit 52 Fumine next to Tig 4 a more detailed block diaεiam of one embodiment ot first bvte queue 54 and second bvte queue 56 is shown Lach ot subqueues 66 lrom first bv te queue 54 are illustrated as havine v anous fields including a first mstruction field (10) a second mstruction tield (I I ) and third mstruction field (12) and a shared field (SFI) Each ot the first instruction field the second instniction field and the third mstruction field are configured to store instruction identification infoπnation conesponding to one mstruction withm the mstruction block stored in that subqueue The inlormation stored in the instruction fields and the shared fields accordme to one embodiment ot the subqueues is shown below A second bvte queue status bus 80 is coupled between control umt 76 and control umt 70 Additionally control umt 76 is coupled to a sy nc line 82 and a two instructions lme 84 trom MROM unit 34 A plurality ol mstruction multiplexors 86A-86C are coupled between subqueues 66A-66C and mstruction position storages 74A-74C A plurality of mstruction bvtes multiplexors 88A-88B are coupled between subqueues 66A-66C and instruction bvtes storages 72B-72C Additionally a plurality of output multiplexors 90A-90C are coupled between mstruction by tes storages 72A-72C and decode units 20 Control umt 70 is coupled to provide multiplexor selection controls to instruction multiplexors 86 Control umt 70 generates the multiplexor selection controls bv seanninε the mstruction v alid bits conesponding to the mstruction fields within subqueues 66 and the mtormation conveved upon second bv te queue status bus 80 Second bvte queue status bus 80 indicates which ot instruction position storages 74 and which ot mstruction bvtes storages 72 are empty upon dispatclung instructions dunng a particular clock cy cle F or example second by te queue status bus 80 mav comprise a sienal conesponding to each mstruction position storage 74A-74C indicative when asserted that the conespondme mstruction position storage 74 is stonng an instruction subsequent to 5 dispatch ol mstructions dunng the cunent clock cvcle Additionally second bv te queue status bus 80 mav be include a signal conespondmg to each instruction bvte storage 72A-72C mdicativ e vy hen asserted that the conesponding mstruction bvtes storage 72 is stonng a block ol instruction bvtes subsequent to instruction dispatch durmg the cunent clock cv cle Control umt 70 selects as manv instructions as possible from subqueues 66 to fill mstruction position 10 storages 74 Control umt 70 also considers av ailability ol instruction bvles storages 72 in selectmg mstructions Generally control unit 70 selects a number ot mstructions tor mstruction position storages 74 which either fills instruction position storages 74 or fills instruction bvles storages 72 Control umt 70 considers the validity ot instructions w ithin subqueues 66A-66C in selecting instructions tor instruction position storages 74 Adv antageously the tvpe ot instniction (MROM or tast path) and other instniction properties stored in subqueues 1 5 66A-66C (such as whether or not an mstruction is a predicted taken branch instruction etc ) need not be considered bv control unit 70 m selecting instructions to fill instruction position storages 74 The logic tor pert oπning the selection may be simplified thereby allow me tor a high lrequencv implementation As shown in Fig 4 mstruction multiplexor 86A is coupled to receive instruction information lrom the 10 instruction field ol each subqueue 66A-66C Since mstruction position storage 74A stores the mstruction yyhich is 0 first in program order among instructions in mstruction position storages 74A-74C and since subqueues 66A are shitted such that the first mstruction in program order is the instruction in field 10 instruction multiplexor 86A is connected to select trom only the first instruction field ol each subqueue 66A-66C Smnlarlv mstruction multiplexor 86B is coupled to select instruction inlormation lrom either mstruction fields 10 and I I Instruction multiplexor 86B is coupled to select instruction information trom anv field yy itlun subqueues 66 2^ Instruction bvles storaccs 72 aie coupled to receiv e blocks ot mstructions tiom subqueues 66 via instruction bvtes multiplexors 88 Contiol unit 76 is coupled to prov ide selection controls lor multiplexors 88 as shown m Fig 4 but control unit 70 may prov ide selection controls as well Instruction by tes storage 72 are maintamed such that instruction bvles storage 72 A stores a block ot instruction bytes conesponding to instructions which are prior to instructions conespondmg to blocks ot instniction bvtes in instruction bvtes storages 72B and 30 72C Similarly instruction bvtes storage 72B stores a block ol instruction bvles conesponding to instructions wluch are prior to instructions conespondmg to the block ol instruction by tes in instruction bvtes storage 72C T herefore if instruction bvles storaee 72 A receives a block ol instruction bvtes trom subqueues 66 the block ot instruction bvles is drawn trom subqueue 66 A Blocks ol mstruction bv tes in subqueues 66B and 66C are subsequent to the block ol mstruction bvtes m subqueue 66A Additionally mstruction bvtes storage 72A may 35 receive a block ot mstruction bvtes slutted m lrom instruction bvtes storage 72B Smnlarlv mstruction bvtes storage 72 A mav receiv e a block ol instruction bvtes trom subqueue 66A or subqueue 66B while mstruction bvtes storage 72C mav receiv e a block ot instruction bvles lrom anv subqueue 66 For example it mstruction bv tes storages 72A-72C are empty durmg a clock cvcle instruction bvles storage 72 A may receive a block ol instruction bvtes trom subqueue 66A mstruction bv tes storage 72B may receive a block ol mstruction bvtes lrom subqueues 66B and mstruction bv tes storage 72C mav receiv e a block ot instruction bvles trom subqueue 66C On the other hand if mstruction bytes storage 72 A is storing a block ot instruction bvtes durmg a clock cv cle instruction bvtes storage 72B mav receive a block of instruction bvtes trom subqueue 66A and mstruction bv tes storage 72C mav receive a block ot mstruction bv tes trom subqueue 66B Generally a block ol mstruction bv tes mav be selected tor storage into mstruction bv tes stoiages 72 v la instruction bvtes multiplexors 88 and a particular block ol instruction bvtes may be v ahdated it an instruction within the particular block ol instruction bvtes is convey ed into mstruction position storages 74 Instruction identifiers stored in instniction position storages 74A-74C are directly convey ed to conespondmg decode units 20A-20C Control unit 76 siεnals which instructions hav e been selected tor dispatch via a dispatch bus 92 coupled to decode units 20 It a decode unit 20A-20C receives an indication that the conespondmε mstruction is being dispatched the decode unit 20 operates upon the received mstruction information and conesponding instruction bvles selected v la multiplexors 90 It is noted that in the case ol overflow instructions instruction bv tes trom more than one ot instruction bvtes storaees 72 may be selected bv a given output multiplexor 90A-90C Control unit 76 teceiv es sy nehronization signals trom MROM umt 34 in oider to dispatch MROM mstnictions The sync signal upon sync line 82 indicates when asserted that MROM umt 34 is prepared to dispatch an MROM mstruction Control unit 76 does not select an MROM instruction tor dispatch unless the svnc signal is asserted Control unit 76 asserts a similar sv nc signal to MROM umt 34 to mdicate that the MROM instruction has been selected Additionally a two mstruction line 84 carnes an indication when asserted that the next MROM mstruction to be dispatched translates mto two tast path mstructions Control unit 76 uses the two instruction indication io determine it a tast path instruction can be concurrently dispatched w ith the MROM instruction It is noted that although multiplexors 86 88 and 90 as shown in Tig 4 arc individual multiplexors the selection represented bv each multiplexor mav actually be performed bv multiple multiplexors ananged in cascade or in parallel Turning novy to Tie 5 a diagram is shown depietinε exemplary mloπnation stored in a held 1 10 ot subqueues 66A-66C accordme to one embodiment Tor example field 1 10 mav be field 10 I I or 12 lor the first second or third instniction w lth an mstruction block Each field stores equivalent mtormation regardmε different instructions Tield 1 10 stores a valid indication 1 12 a start pointer 1 14 an end pointer 1 16 a v alid mask 1 18 an MROM/tast path indication 120 and a branch prediction indication 122 Valid indication 1 12 identifies the validity or inv alidity of the rema der ol the information stored in field 1 10 If the valid indication mdicates validity then instruction identification mtormation is stored m field 1 10 If the v alid indication indicates invalidity then mstruction identification information is not stored within field 11 (l e field 1 10 is empty ) In one embodiment valid indication 1 12 comprises a bit lndicativ e w hen set that instruction identification information is stored ithm field 110 When clear the bit indicates that instruction identification mtormation is not stored withm field 110 Start pointer 1 14 and end pomter 116 locate the bvte positions withm the mstruction block at v\ hιch the instruction identified m field 110 begms and ends respectively Tor embodiments m y hich an mstruction block includes 8 bv tes start pomter 1 14 and end pointer 1 16 each comprise three bit values indicating the numeπcal position betw een zero and sev en of the respective start or end point Valid mask 118 is a mask ot zeros and ones Each bit in the mask conesponds to one of the bvtes within the instruction block Bits m the mask corresponding to bvtes not mcluded within the instruction identified bv field 110 are set to zero Com erselv bits in the mask conespondmg to bytes included withm the mstruction are set to one For example if the mstruction identified by field 110 beg s at the third bv te withm the mstruction block and ends at the filth bv te w ithm the mstruction block the start pomter is 010 the end pomter is 100 and the mask is 0011 1000 (all expressed m binary iormat) The start pointer end pomter and mask are used to generate selection controls tor selecting bvtes withm the instruction block when the instruction is selected tor issue MROM/tast path indication 120 indicates the MROM or tast path nature ol the instruction identified bv field 110 In one embodiment indication 120 comprises a bit indicativ e when set that the mstruction is an MROM mstruction When clear the bit indicates that the mstruction is a last past instruction Finally branch prediction indication 122 comprises a bit indicativ e when set that the instruction is a branch mstruction which is predicted taken When clear the bit indicates that the mstruction is either not a branch instruction or is a branch instruction predicted not taken Turning now to Tie t. a diagram is shoyvn depicting exemplary inlormation stored m a shared Held 130 of a subqueue 66A-66C Information stored in shared field 130 is shared information v alid tor the entire instruction block accordmg to one embodiment An address bits field 132 a lunctional bits field 134 a seεment limit field 136 an overflow indication 138 and an instruction bvles field 140 are mcluded Address bits field 132 stores a pair ol address bits wluch identify the quarter ot the cache lme trom yyhich the instruction block was letched Functional bits field 134 stores the origmal functional bits trom the predecode data associated with the instruction bvles within the instruction block Segment limit field 136 is used to detect instructions beme dispatched from outside the code segment As w ill be appreciated by those skilled in the ail the x86 microprocessor architecture div ides the memorv space into segments One ot these seements is the code segment trom which instructions are tetched The segment has a defined limit yyhich may be ol arbitrarv si/c It instruction execution proceeds outside ot the code segment a segment limit v iolation exception is sienalled Microprocessor 10 mav handle segment lunit violations as follows it an entire set ot instructions fetched trom instruction cache 16 dunnε a clock cvcle lies outside the code segment the mstnictions are not conveved to mstruction alignment unit 18 Instead the segment limit v lolation is signalled to reorder buffer 32 and to the control logic w ithin mstruction cache 16 The control logic generates a signal to MROM unit 34 causing MROM umt 34 to begm dispatching the exception serv ice routine conespondmg to the segment lunit v lolation If mstructions prior to the segment limit v lolation retire successfully (as opposed to bemg discarded due to branch misprediction or other exception) then the exception mav be taken at that time However the limit mav be arbitrarv and theretore mav tall withm the set of instructions tetched from mstruction cache 16 Segment limit field 136 is mcluded tor handling this case It the limit is crossed within the instruction block then segment limit field 136 indicates wluch bvte position represents the segment limit In one embodiment segment limit field 136 comprises tour bits to mdicate a lunit at one ot the sixteen bv tes withm the instruction cache lme II an mstruction bevond the limit unposed bv segment limit field 136 is dispatched an exception is signalled to reorder buffer 32 Overflow indication 138 indicates that one of the instructions within the instruction block overflows mto the subsequent instruction block Information reeardmg the ov ertlovvmg mstruction is stored m field 12 ot the conespondmg subqueue 66A-66C In one embodiment overflow indication 138 comprises a bit indicativ e yyhen set that an mstruction withm the mstruction block overflows When clear the bit mdicates that no instruction within the instruction block ov erflows It ov erflow indication 138 is set then the valid indication withm field 12 is clear Alternatively overflow indication 138 is clear if the valid indication withm field 12 is set In this manner field 12 is indicated either to store an overflow mstruction or a v alid instruction ending w lthin the instruction block but not both Additionally field 12 is indicated to be not storing an mstruction it both ov erflovv mdication 138 and the v alid mdication tor position 12 are clear Instruction bvles field 140 stores the actual instruction bvles included withm the mstruction block In one einbodunent instruction bvtes field 140 is eight bvles wide Turning next to Fig 7 an exemplary mstruction identifier 150 stored bv one embodiment of mstruction position storages 74 is shown Other embodiments mav employ different instruction identifiers than the embodiment shown in Fig 7 As shoyyn in Fie 7 instruction identifier 150 includes v alid indication 1 12 start pointer 1 14 end pomter 1 16 v alid mask 1 18 MROM/last path mdication 120 and branch prediction 122 lrom the instruction field ot the subqueue 66A-66C which stored the instruction when the mstruction s convey ed mto the instruction position storage 74 Additionally mstruction identifier 150 includes a start block field 152 and an end block field 154 Start block field 152 identifies w luch of instniction bvles storages 72 stores the start bv te ot the mstruction Smnlarlv end block field 154 identifies which ot mstruction bvtes storaεes 72 stores the end bvte ot the instruction For non-ov erflow instructions start block field 152 and end block field 154 store the same v alue Using start block field 152 end block field 154 start pointer 1 14 and end pointer 1 16 control unit 76 mav torm select controls tor output multiplexors 90 ruming now to Fig 8 a computer sy stem 200 includinε microprocessor 10 is shown Computer sv stem 200 lurther mcludes a bus bridge 202 a mam memory 204 and a plurality ot input/output (I/O) dev ices 206 A- 206N Plurality ot I/O dev ices 206A-206N v ill be collectiv ely ietened to as I/O dev ices 206 Microprocessor 10 bus bridge 202 and mam memory 204 arc coupled to a sy stem bus 208 I/O devices 206 are coupled to an I/O bus 210 tor communication w ith bus bridge 202 Bus bridge 202 is provided to assist m communications bet een I/O dev ices 206 and dev ices coupled to sy stem bus 208 I/O devices 206 typically require longer bus clock cy cles than microprocessor 10 and other devices coupled to system bus 208 Therefore bus bridge 202 provides a buffer between system bus 208 and input/output bus 210 Additionally bus bndge 202 translates transactions lrom one bus protocol to another In one embodiment input/output bus 210 is an Enhanced Industry Standard Architecture (EISA) bus and bus bndge 202 translates lrom the sy stem bus protocol to the EISA bus protocol In another embodiment input/output bus 210 is a Penpheral Component Interconnect (PCI) bus and bus bπdεe 202 translates trom the sy stem bus protocol to the PCI bus protocol It is noted that many v aπations ot sv stem bus protocols exist Microprocessor 10 mav employ any suitable sy stem bus protocol I/O dev ices 206 provide an interlace between computer sy stem 200 and other dev ices external to the computer sv stem Exemplary I O devices mclude a modem a senal or parallel port a sound card etc I/O dev ices 206 mav also be retened to as peripheral devices Mam memorv 204 stores data and mstructions lor use by microprocessor 10. In one embodiment, main memory' 204 includes at least one Dynamic Random Access Memory (DRAM) and a DRAM memory controller. It is noted that although computer system 200 as shown in Fig. 8 includes one bus bridge 202. other embodiments of computer system 200 may include multiple bus bridges 202 for translating to multiple dissimilar or similar I/O bus protocols. Still further, a cache memory for enhancing the performance of computer system 200 by storing instructions and data referenced by microprocessor 10 in a faster memory' storage may be included. The cache memory may be inserted between microprocessor 10 and system bus 208. or may reside on system bus 208 in a "lookaside" configuration. It is still further noted that the functions of bus bridge 202, main memory 204. and the cache memory may be integrated into a chipset which interfaces to microprocessor 10. It is still further noted that the present discussion may refer to the assertion of various signals. As used herein, a signal is "asserted" if it conveys a value indicative of a particular condition. Conversely , a signal is "deasserted" if it conveys a value indicative of a lack of a particular condition. A signal may be defined to be asserted yvhen it conveys a logical zero value or. conversely, when it conveys a logical one value. Additionally, various values have been described as being discarded in the above discussion. A value may be discarded in a number of manners, but generally involves modifying the value such that it is ignored by logic circuitry' vvliich receives the value. For example, if the value comprises a bit. the logic state of the value may be inverted to discard the value. If the value is an n-bit value, one of the n-bit encodings may indicate that the value is invalid. Setting the value to the invalid encoding causes the value to be discarded. Additionally, an n-bit value may include a valid bit indicative, yvhen set. that the n-bit value is valid. Resetting the valid bit may comprise discarding the value. Other methods of discarding a value may be used as well. Table 1 below indicates fast path, double dispatch, and MROM instructions for one einbodunent of microprocessor 10 employing the x86 instruction set: Table 1 : x86 Fast Path, Double Dispatch, and MROM Instructions X86 Instruction Instruction Cateεorv AAA MROM AAD MROM AAM MROM AAS MROM ADC- fast path ADD fast path AND fast path ARPL MROM BOUND MROM BSF fast path BSR fast path BSWAP MROM BT fast path BTC fast path BTR fast path BTS fast path CALL fast path/double dispatch CBW fast path CWDE fast path CLC fast path CLD fast path CLI MROM CLTS MROM CMC fast path CMP fast path CMPS MROM CMPSB MROM CMPSW MROM CMPSD MROM CMPXCHG MROM CMPXCHG8B MROM CPUID MROM CWD MROM CWQ MROM DDA MROM DAS MROM DEC fast path DIV MROM ENTER MROM HLT MROM IDIV MROM IMUL double dispatch IN MROM INC fast path INS MROM INSB MROM INSW MROM INSD MROM INT MROM INTO MROM INVD MROM INVLPG MROM IRET MROM IRETD MROM Jec fast path JCXZ double dispatch JECXZ double dispatch JMP fast path LAHF fast path LAR MROM LDS MROM LES MROM LFS MROM LGS MROM LSS MROM LEA fast path LEAVE double dispatch LGDT MROM LIDT MROM LLDT MROM LMSW MROM LODS MROM LODSB MROM LODSW MROM LODSD MROM LOOP double dispatch LOOPcond MROM LSL MROM LTR MROM MOV fast path MOVCC fast path MOV.CR MROM MOV.DR MROM MOVS MROM MOVSB MROM MOVSW MROM MOVSD MROM MOVSX fast path MOVZX fast path MUL double dispatch NEG fast path NOP fast path NOT fast path OR fast path OUT MROM OUTS MROM OUTSB MROM OUTSW MROM OUTSD MROM POP double dispatch POPΛ MROM POPAD MROM POPF MROM POPFD MROM PUSH fast path/double dispatch PUSHA MROM PUSHAD MROM PUSHF fast path PUSHFD fast path RCL MROM RCR MROM ROL fast path ROR fast path RDMSR MROM REP MROM REPE MROM REPZ MROM REPNE MROM REPNZ MROM RET double dispatch RSM MROM SAHF ast path SAL ast path SAR ast path SHL ast path SHR ast path SBB ast path SCAS double dispatch SCASB MROM SCASW MROM SCASD MROM SETcc fast path SGDT MROM SIDT MROM SHLD MROM SHRD MROM SLDT MROM SMSW MROM STC fast path STD last path STI MROM STOS MROM STOSB MROM STOSW MROM STOSD MROM STR MROM SUB fast path TEST tast path VERR MROM VERW MROM WBINVD MROM WRMSR MROM XADD MROM XCHG MROM XLAT last path XLATB tast path XOR tast path Note Instructions including an SIB bvte are also considered double dispatch instructions In accordance with the abov e disclosure a microprocessor has been shown yyhich employ s a dual bv te queue lor high speed instruction alignment ot v aπable bvie length instructions to a plurality ot decode umts The dual bvte queue approach mav allow a high frequency implementation ot the microprocessor despite the complexity ot locating and dispatclung vanable bvie length instructions Numerous vanations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated It is mtended that the tollowmg claims be interpreted to embrace all such v anations and modifications

Claims: WHAT IS CLAIMED IS: 1 An mstruction alignment umt compnsmg a first instruction queue coupled to receive a plurality ol instruction blocks wherem said first instruction queue is contigured to store said plurality ot mstruction blocks a second mstruction queue coupled to receive a plurality ot mstruction identifiers conespondmg to a plurality ol instructions trom said first instruction queue wherein said second instruction queue is configured to store said plurality ol mstruction identifiers, and a first control unit coupled to said first mstruction queue and said second mstruction queue herem said first control umt is configured to select said plurality ol mstructions lrom said plurality of instruction blocks and wherem said first control unit is configured to select a number ot said plurality of instructions based upon a number ot instructions stored in said second instruction queue 2 The instruction alienment unit as recited in claim 1 further compnsmg a second control unit coupled to said first instruction queue and said second instruction queue yy herein said second control unit is configured to select one or more ol said plurality ot instructions tor dispatch 3 The instruction alignment unit as recited in claim 2 yy herein said second mstruction queue compnses a plurality ol instruction position storages w herem each ot said instniction position storages is configured to store a different one ot said plurality ot mstruction identifiers conespondmε to said plurality ot mstructions 4 The instruction alignment unit as recited in claim 3 w herem said second control unit is configured to mamtaui said plurality ol instructions withm said plurality ol mstruction position storages in program order whereby a first one ol said plurality ot mstruction position storages stores a first one ot said plurality of instruction identifiers conesponding to a first mstruction which is pnor to a second instruction in program order and said second instruction conesponds to a second one ot said plurality ot mstruction identifiers stored m a second one ot said plurality ol mstruction position storages 5 The instruction alignment unit as recited in claim 4 v herem if said first instruction is selected for dispatch and said second instruction is not selected lor dispatch said second control unit is configured to shift said second one ol said plurality ol mstruction identifiers trom said second one ot said plurality ol instruction position storages to said first one ot said plurality ol mstruction position storages 6 The instruction alignment unit as recited in claim 5 yv herein said second mstruction queue further comprises a plurality of instruction bvtes storages wherem said plurality ot mstruction bv tes storages is configured to store instruction bytes which mclude said plurality ot instructions 7 The instruction alignment unit as recited in claim 6 wherem said first control unit is further configured to select said number of said plurality ol mstructions based upon a number ol instruction bvtes stored withm said plurality ot instruction bvles storages 8 The instruction alienment unit as recited in claim 6 wherem each one ot said plurality ol mstruction position storages is contigured to store a start block value which identifies winch one ot said plurality ol instruction bvte positions is storing a start bvte ot said different one ol said plurality ot mstructions 9 The instruction alienment unit as recited in claim 8 wherem each one ol said plurality ot mstruction position storaees is contieured to store an end block value which identifies wluch one ot said plurality ot instruction bvte positions is storing an end bvie ol said different one ol said plurality ol mstructions 10 The instruction alignment unit as recited m claim 1 w herem said first instruction queue comprises a plurality ol subqueues wherein each one ot said plurality ol subqueues is configured to stoie a different one ot said plurality ot mstruction blocks 1 1 The instruction alienment unit as recited in claim 10 wherein said first control umt is configured to manage said plurality ot instruction blocks withm said plurality ot subqueues such that a first one ot said plurality ot subqueues stores a first one ot said plurality ot instruction blocks which is pnor to a second one ot said plurality ot instruction blocks stored in a second one ot said plurality ol subqueues m program order 12 I he instruction alignment unit as recited in claim 1 1 vy herein ll said first one ot said plurality ot instruction blocks is exliausted and said second one ol said plurality ot instruction blocks is not exhausted said first control umt is configured to shift said second one ot said plurality ol instruction blocks mto said first one ot said plurality ol subqueues 13 A method tor aliening mstructions trom an mstruction cache to a plurality ot decode units in a superscalar microprocessor compnsmg receiv mg a plurality of instruction blocks lrom said instruction cache into a first mstruction queue selecting a plurality ot mstructions trom said plurality of instruction blocks storing said plurality ot instructions into a second instruction queue and selecting one or more mstructions trom said second instruction queue tor dispatch to said plurality ol decode umts 14 The method as recited in claim 13 w herem said first instruction queue comprises a plurality of subqueues yy herein each one of said plurality ot subqueues is configured to store a different one ol said plurality ot mstruction blocks 15 The method as recited in claim 13 w herem said second mstruction queue compnses a plurality ol instruction position storages wherem each one ol said plurality ot instruction position storages is configured to identify a different once ol said plurality ol instructions 16 The method as recited in claun 15 wherem said second mstruction queue further comprises a plurality ol instruction bvles storages yyherem said plurality ol mstruction bvtes storages is configured to store a plurality ot instruction bv tes including said plurality ot mstnictions 17 The method as recited in claim 13 w herem said selecting one or more instructions is based upon a predefined set ol cnteπa 18 The method as recited in claun 17 w herem said predefined set of cπtena includes a criterion that at most one predicted taken branch mstruction is mcluded within said one or more mstructions 19 The method as recited in claun 17 wherein said predefined set ot cπtena includes a cnteπon that at most one microcode mstruction is mcluded withm said one or more mstructions 20 The method as recited in claim 17 w herem said predefined set ot cπtena includes a cπteπon that at most one non-microcode instruction is included w ithin said one or more mstructions it a microcode mstruction is also included w ithin said one or more instructions 21 A superscalar microprocessor compnsmg an instruction cache configured to store instructions wherein said instruction cache is further configured to prov tdc a plurality of mstruction blocks in response to mstruction letchmg an mstruction alignment unit coupled to said instruction cache to receive said plurality ot instruction blocks wherem said mstruction alignment umt is configured to store said plurality ol instruction blocks mto a first instruction queue and wherem said mstruction alignment umt is configured to select a plurality of instructions from instruction blocks stored in said first instruction queue and wherem said mstruction alignment umt is configured to store said pluralit y ot instructions in a second instruction queue and wherem said mstruction alignment unit is contigured to select one or more instructions from said plurality of instructions stored in said second instruction queue for dispatch based upon a predefined selection criteria: and a plurality of decode units coupled to receive said one or more instructions from said instruction alignment unit, wherein each one of said plurality of decode units is configured to receive a different one of said one or more instructions and to decode said different one of said one or more instructions.

Inventors: NARAYAN RAMMOHAN, VENKATESWARA RAO M, NARAYAN, RAMMOHAN, VENKATESWARA, RAO, M.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1998
Main classification: G06F9
IPC codes: G06F9