Viterbi decoding apparatus and viterbi decoding method

Abstract: In a Viterbi decoder, a trace-back operation is carried out using three dual-port RAMs of the number of bits = 8 and the number of words = 4 are provided in a path memory circuit. Path selection information is sequentially written into the three RAMs every clock in accordance with the control of a control circuit. On the other hand, the path selection information is read out every clock from the RAMs in accordance with the control of the control circuit and is inputted as read path selection information or the like to a tracing circuit. The tracing circuit executes the tracing operation as many as three times on the basis of the read path selection information and trace starting state information which is formed by the control circuit. On the basis of a tracing result, the decoding data and a trace starting state in the subsequent clock are obtained. Thus, high speed operation is performed with a circuit having a small size.

Description: BACKGROUND OF THE INVENTION Field of the Invention The invention relates to a Viterbi decoding apparatus and a Viterbi decoding method which is used in a maximum likelihood decoding method of a convolution code that is used in, for example, a satellite broadcasting or the like. Description of the Related Art As a method of decoding a convolution code, a Viterbi decoding method has been known. The Viterbi decoding method is a maximum likelihood decoding method for the convolution code, and by selecting a series that is the closest to a received code series (hereinafter, such a series is referred to as a maximum likelihood path) among a code series which can be formed from an encoder on the transmission side, an error correction is performed. That is, a transition diagram (hereinafter, referred to as a trellis) which is formed on the basis of an encoding method by the encoder on the transmission side is used as a prerequisite and, for example, a path whose Hamming distance from the received code series is the shortest is selected as a maximum likelihood path from transitions which can occur on the transition diagram. A Viterbi decoding apparatus for performing a Viterbi decoding method comprises: a branch metric calculating circuit for calculating a branch metric, namely, a Hamming distance between a path which reaches each state on the trellis and the received code series in accordance with a clock; an ACS circuit for calculating state metrics on the basis of the branch metric, comparing values of the state metrics, and selecting a maximum likelihood path; a normalizing circuit for normalizing the values of the state metrics; a state metric storing circuit for storing the values of the state metrics; and a path memory circuit for forming decoding data in accordance with a selection result by the ACS. As a path memory circuit, there are two kinds of circuits: namely, a circuit for performing a register transition method for transferring the path selection contents by using a register train; and a circuit for performing a method of storing the path selection contents by using RAMs, tracing the stored contents, and decoding. Those two kinds of methods will now be described hereinbelow. In the register transition method which is generally used in a Viterbi decoding apparatus, memory cells each comprising a selector and a register are arranged on the trellis in the path memory circuit and the contents in the register are transferred on the basis of the path selection information that is outputted from the ACS circuit. An example of a construction of the memory cell is shown in Fig. 1. An example of an arrangement of memory cells in the case where a restriction length = 3 is shown in Fig. 2 (in Fig. 2, the memory cell is shown as MS). With such a construction, information corresponding to a survival path from each state is preserved in the register of each memory cell. The registers of the number of stages corresponding to a cut length are arranged in the memory cell. Among outputs at the final stages, the output of the maximum likelihood state is selected, thereby selecting the information for the maximum likelihood path and outputting decoding data. Although such a register transition method has an advantage such that the high speed operation can be performed, there is a drawback such that a circuit scale is extremely large as the cut length becomes long. Particularly, since an application such that the cut length exceeds 100 also has appeared in recent years, the enlargement of the circuit scale becomes a serious problem. In recent years, therefore, the method of decoding by storing path information by using the RAMS (Random Access Memories) as many as the cut length and tracing the stored information has actively been studied. Such a method is called a trace-back method hereinbelow. According to the trace-back method, a path memory circuit whose circuit scale is fairly smaller than that of the register transition method can be constructed. However, in the conventional apparatus for performing the trace-back method, the path memory circuit still has a large circuit scale. In the article "An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders" by E. Paaske, S. Pedersen and J. SparsØ, Integration, The VLSI Journal, Vol. 12 No. 1, pages 79-91, NL, north-holland Publishing Company, Amsterdam, 01 November 1991, a trace back algorithm is described in point 2.2. During each period of L clock cycles, decisions from the ACS module are written in one of the RAM blocks, an opening trace back is performed in one of the RAM blocks, and a final trace back is performed in one of the RAM blocks. In point 2.3 of the article, a combined register exchange and block trace back algorithm is introduced. The register exchange algorithm is used for generating small blocks (segments) of length 1 of the surviving paths, and then a trace back is performed based on blocks of length 1 instead of bits in a RAM. The trace back resulting from this procedure provides 1 bits in each step compared to one bit for the TBA. In the US Patent 4,905,317 to Suzuki et al., a path memory control method for Viterbi decoders is described. According to this invention, if a plurality of steps are required in a trace back to a final stage on the surviving path, a plurality of decoded data equal in number to the number of the decode steps involved are delivered as an output, not only one decoded data. For this purpose, the path memory is divided into a number N+ of intervals, and N+ back tracers are provided so as to independently trace back the corresponding divided intervals. Another possible solution is to handle the state transition information over a range of a plurality of times and to make a jump-back over a plurality of stages by one memory access. In the European Patent Application EP 0 798 867 A2, a Viterbi decoder for generating maximum likelihood decoded data as a result of analysing survivor sequences information stored in a memory unit by carrying out traceback is provided. In order to improve the decoding speed, an interleave operation with respect to two RAMs is carried out. The first memory is for memorising half of the survivor sequences information in accordance with a first clock, and the second memory is for memorising half of the survivor sequences information in accordance with a second clock, whereby the second clock has a phase inverse of that of said first clock. In the article "Architectural tradeoffs for survivor sequence memory management in Viterbi decoders" by G. Feygin and P. G. Gulak, IEEE Transactions On Communications, Vol. 41, No. 3, pages 425-429, March 1993, four alternative traceback algorithms are described. In section C of this article, the so-called one-pointer algorithm is described. Instead of utilizing k read pointers to perform the required k reads for every column write operation, a single read pointer is used, but the read operations are accelerated so that every time the write counter advances by one column, k column reads occur. Fig. 3 shows an implementation of the one-pointer algorithm using four single-port memory banks. It is an object of the invention to provide a Viterbi decoding apparatus and a Viterbi decoding method in which a circuit scale is small and a high sped operation can be performed. SUMMARY OF THE INVENTION The invention of Claim 1 is a Viterbi decoding apparatus which has a path memory for storing selection information of a path in each transition state of a convolution code by using a rewritable memory and traces the information held in the path memory by an amount corresponding to a cut length, thereby performing a Viterbi decoding, wherein a plurality of rewritable memories and memory control means for controlling accesses to the plurality of rewritable memories are comprised, and tracing operations as many as a plurality of times for a period of time of one clock and decoding are performed. The invention of claim 7 is a Viterbi decoding method of storing selection information of a path in each transition state of a convolution code and tracing the stored information by an amount corresponding to a cut length, thereby performing a Viterbi decoding, comprising a tracing step of performing tracing operations as many as a plurality of times for a period of time of one clock with using a plurality of rewritable memories provided in a path memory. According to the invention as mentioned above, by performing the decoding by executing the tracing operation as many as a plurality of times for the period of time of one clock, the total number of words in the RAM can be reduced. When the path selection information is written, it is sequentially written into a plurality of rewritable memories. Upon tracing, by sequentially reading out the information from the plurality of memories and performing the tracing operation as many as the plurality of times, the tracing operation as many as the plurality of times can be performed while setting the number of times of access to each memory of each clock to one time. Further, among the outputs of the plurality of memories, the information of the state having a possibility such that it is traced is preliminarily selected on the basis of the trace starting state and the tracing operation is executed with regard to the selected information of the state. Thus, even if the tracing operation as many as the plurality of times is executed, an increase in delay can be minimized. The above, and other, objects, features and advantage of the present invention will become readily apparent from the following detailed description thereof which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram for explaining a memory cell of a path memory in a register transition method; Fig. 2 is a s schematic diagram for explaining an arrangement of the memory cells in the path memory in the register transition method; Fig. 3 is a block diagram for explaining a whole construction of an embodiment of the invention; Fig. 4 is a schematic diagram for explaining a transition diagram in the case where a restriction length = 4; Fig. 5 is a schematic diagram for explaining a principle of tracing in a trace-back method; Fig. 6 is a schematic diagram for explaining a method of tracing in the trace-back method; Figs. 7A to 7D are schematic diagrams for explaining a role of each RAM in a general trace-back method which has conventionally been used; Fig. 8 is a schematic diagram for explaining the memory operation in the general trace-back method which has conventionally been used; Fig. 9 is a block diagram for explaining a path memory circuit in an embodiment of the invention; Fig. 10 is a schematic diagram for explaining the memory operation in the embodiment of the invention; Figs. 11A to 11F are schematic diagrams for more specifically explaining the memory operation in the embodiment of the invention; Figs. 12A to 12G are schematic diagrams for more specifically explaining the memory operation in the embodiment of the invention; Fig. 13 is a schematic diagram for explaining states having a possibility such that they are traced; Fig. 14 is a block diagram for explaining a tracing circuit in the embodiment of the invention; Fig. 15 is a block diagram for explaining a path memory circuit in another embodiment of the invention; Fig. 16 is a schematic diagram for explaining the memory operation in the other embodiment of the invention; Figs. 17A to 17F are schematic diagrams for more specifically explaining the memory operation in the other embodiment of the invention; and Figs. 18A to 18G are schematic diagrams for more specifically explaining the memory operation in the other embodiment of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the invention will now be described hereinbelow with reference to the drawings. First, a whole construction of the first embodiment of the invention will now be described with reference to Fig. 3. The first embodiment of the invention comprises: a branch metric calculating circuit 701; an ACS circuit 702; a normalizing circuit 703; a state metric storing circuit 704; and a path memory circuit 705. When data received through a transmission path is inputted from the transmission side, a maximum likelihood path is selected from a code series which can be formed from an encoder on the transmission side and decoding data is formed on the basis of selection contents. That is, for example, a transition diagram (hereinafter, referred to as a trellis) as shown in Fig. 4 which is formed on the basis of an encoding method by the encoder on the transmission side is used as a prerequisite and, for example, a path whose Hamming distance from the received code series is the shortest is selected as a maximum likelihood path from the transitions which can occur on the transition diagram. When a reception data signal s701 is inputted, the branch metric calculating circuit 701 calculates a branch metric of the reception data and outputs a calculation result as a branch metric signal s702. On the basis of the branch metric signal s702 and a state metric signal s705 which is inputted from the state metric storing circuit 704, the ACS circuit 702 adds the branch metric and the state metric to each of two paths which join a certain state, compares their addition values, selects the addition value having a higher likelihood on the basis of a comparison result, and sets it as a new state metric. The contents of such a selection are outputted as path selection information s706. The number of the state having the minimum state metric is outputted as a maximum likelihood state signal s707. The newly obtained state metric is outputted as a new state metric signal s703. A selecting method of the path will now be described with respect to a case where a restriction length = 4 as an example. The trellis of Fig. 2 shows an example of a trellis in the case where it has eight states 000, 001, 010, 011, 100, 101, 110, and 111 and a restriction length = 4. An arrow indicates a path which can occur every time slot. A path corresponding to the decoding data '0' is shown by a broken line. A path corresponding to the decoding data '1' is shown by a solid line. Two paths which join exist in all of the states every time slot. Therefore, for each of the two paths which join a certain state, the Hamming distance (branch metric) between the reception signal and the path and an accumulation sum (state metric) of the branch metrics so far are added and compared. A path having a higher likelihood is selected on the basis of a comparison result. The normalizing circuit 703 normalizes by using a method whereby the minimum state metric is subtracted from the new state metric signal s703 which is outputted from the ACS circuit 702 or the like, thereby setting to a value within a preset range and outputting it as a normalization state metric signal s704. The state metric storing circuit 704 stores the normalization state metric signal s704 which is outputted from the normalizing circuit 703 and returns it as a state metric signal s705 to the ACS circuit 702. The path memory circuit 705 executes the decoding operation by the trace-back method and is constructed so as to reduce an area of the RAMs as compared with the general path memory for performing the trace-back method as mentioned above. Prior to describing the path memory circuit 705, to make it easy to understand, the tracing operation in the general trace-back method will now be described with respect to a case where a restriction length = 4 as an example. In Fig. 5, a case of tracing from state 01 will be considered. States having a possibility of transition to state 001 are state 000 and state 100. '0' has been stored in the path memory when the path on the state 000 side had been selected. '1' (namely, the most significant bit of the pre-state) has been stored in the path memory when the path on the state 100 side had been selected. Even in case of transferring from any state, the input is 1 and it is expressed by the least significant bit of state 001. By the above description, it is sufficient to execute the tracing operation as follows. That is, as shown in Fig. 6, the least significant bit of a trace starting state to start the tracing is used as a decoding bit. The number of the next tracing state to trace subsequently to the trace starting state is formed by newly adding the bit in the path memory as a most significant bit for a range from the most significant bit to the second lowest bit of the trace starting state. By such an operation, the selected path can be traced from the state having the minimum state metric. To make the Viterbi decoding apparatus operative at a high speed, the access to the RAM can be performed only once every clock. The operation of the path memory circuit to perform the decoding by the access of once for each RAM will now be described with respect to a case of using four single-port memories as an example. In the following description, a restriction length of a code = 4 and a cut length = 6. In this case, as four single-port memories, memories each having the bits of the number as many as the number of states (eight bits in this case) and the words of the number as much as the cut length (in this case, six words) are used. The path selection information as many as the number of states is inputted from the ACS circuit to the path memory every clock. In the four RAMs, the following four roles of (1) to (4) are sequentially switched every clock (six clocks here) as much as the cut length (refer to Figs. 7A and 7D). (1) The path selection information is sequentially written. (2) The tracing is sequentially performed on the basis of the written path selection information. The decoding is not performed. (3) No access (4) The tracing is sequentially performed from a tracing result in (2) and a decoding bit is outputted. The operation of each RAM based on such a switching operation is shown in Fig. 8. By the memory operation as mentioned above, a Viterbi decoding apparatus which can perform a high speed decoding even by using RAMs can be constructed. According to such a general trace-back method, the circuit scale can be fairly reduced as compared with that in case of performing the register transition method. However, since four RAMs having the words of the number as many as the cut length are necessary, the total number of words of the RAMs is equal to (the cut length) x 4 and the large circuit scale is still needed. Therefore, the embodiment of the invention intends to further reduce the circuit scale of the path memory circuit. Referring to Fig. 9, the path memory circuit 705 in the embodiment of the invention will now be described. The path memory circuit 705 is a path memory circuit which has three dual-port RAMs of 1-write and 1-read of the number of bits = 8 and the number of words = 4 and executes the tracing operation as many as three times for a period of time of one clock in case of performing the decoding of the cut length = 6 for the code of the restriction length = 4. Path selection information s102 which is inputted from the ACS circuit is sequentially stored into the RAMs every clock in accordance with the order of RAM 12 - RAM 11 - RAM 10 - RAM 12 - RAM 11 ••• on the basis of a write control signal s103 which is generated from a control circuit 101. In response to a read control signal s104 which is generated by the control circuit 101, the path selection information is read out from all of the RAMs 10, 11, and 12 every clock and read path selection information s105, s106, and s107 is inputted to a tracing circuit 102. Timings for the memory operation based on the control circuit 101 are shown in Fig. 10. The tracing circuit 102 executes the tracing operation as many as three times in accordance with the read path selection information s105, s106, and s107 which is outputted from the RAMs 10, 11, and 12 and trace starting state information s108 which is formed by the control circuit 101. A result is inputted as a trace result signal s109 to the control circuit s101. While initializing the trace starting state every cut length/2 clocks on the basis of the trace result signal s109 and a maximum likelihood state signal s101, the control circuit s101 obtains the trace starting state of the next clock. Such a memory operation will now be more specifically explained with reference to Figs. 11A to 11F and Figs. 12A to 12G. Figs. 11A to 11F and Figs. 12A to 12G show the writing/reading operations for the RAMs 10, 11, and 12 at continuous times. As mentioned above, those three RAMs are dual-port RAMs of the number of bits = 8 and the number of words = 4. Because of a limitation of a drawing space, states of times 1 to 6 are shown in Figs. 11A to 11F and states of times 7 to 13 are shown in Figs. 12A to 12G. It is now assumed that all of the addresses in each memory are sequentially allocated to 0, 1, 2, and 3 from the left. The path selection information is sequentially written into each RAM until times 1, 2, 3, ..., and 9 and three addresses are written with respect to each RAM at time 9. The operation at time 10 and subsequent times is shown in Fig. 10. In the head clock in Fig. 10 corresponding to time 10, storage contents (three path selection information 9, 8, 7) are read out from address 3 in each RAM and the tracing is performed. At the same time, the subsequent path selection information 10 is written into address 0 in the RAM 12. In Figs. 11A to 11F and Figs. 12A to 12G, 't' added to a reading arrow denotes that the tracing is executed and 'd' indicates that the tracing is performed and the decoding is executed. In the second clock in Fig. 10 corresponding to time 11, the storage contents (three path selection information 6, 5, 4) are read out from addresses 2 in the RAMs and the tracing is executed. At the same time, the subsequent path selection information 11 is written into address 0 in the RAM 11. Further, In the third clock in Fig. 10 corresponding to time 12, the storage contents (path selection information 3, 2, 1) are read out from addresses 1 in the RAMs and the tracing is executed. After that, the decoding operations corresponding to the path selection information 1 to 9 are executed. At the same time, the subsequent path selection information 12 is written into address 0 in the RAM 12. In the fourth clock in Fig. 10 corresponding to time 13, the storage contents (three path selection information 10, 11, 12) are read out from addresses 0 in the RAMs and the tracing and the initialization of the trace starting state are executed. At the same time, the subsequent path selection information 13 is written into address 1 in the RAM 12. As mentioned above, the decoding and the initialization of the trace starting state in the clock subsequent to it are executed once every three clocks. The subsequent path selection information as much as one address is inputted at any clock. On the other hand, the trace starting state information s108 is also inputted to an output buffer 103. In the output buffer 103, lower three bits of the trace starting state information s108 after the tracing was performed by an amount corresponding to the cut length or more are stored as decoding bits and are rearranged in accordance with the inherent order of the time series. After that, they are outputted as a decoding bit signal s110. By the construction as mentioned above, as for the access to each RAM, while keeping the access to once every clock, the total number of words in the RAM in the path memory circuit can be set to (the cut length) x 2. Thus, the circuit scale of the Viterbi decoding apparatus can be reduced. The tracing circuit 102 will now be described. Since the tracing is executed in accordance with the order of the RAM 10 - RAM 11 - RAM 12, the path selection information of which state is selected from the path selection information s105 is determined by the trace starting state information s108. The numbers of candidates of the states to be selected from the path selection information s106 and s107 can be suppressed to 2 and 4 by the trace starting state information s108, respectively (refer to Fig. 13). The tracing circuit 102 is constructed by using this nature. Fig. 14 shows a construction of the tracing circuit 102. The path selection information s105, s106, and s107 which is inputted from the RAMs 10, 11, and 12 is inputted to selecting circuits 401, 402, and 403, respectively. On the other hand, the trace starting state information s107 is also inputted to the selecting circuits 401, 402, and 403. The selecting circuit 401 selects the path selection information of the state to be traced from the path selection information s104 in accordance with the trace starting state information s107 and outputs as trace result information s401. The selecting circuit 402 selects the path selection information of two states having a possibility such that it is traced from the path selection information s105 in accordance with the trace starting state information s107 and outputs as pre-trace information s402. The pre-trace information s402 is inputted to the selecting circuit 404. The trace result information s401 is further inputted to the selecting circuit 404. The selecting circuit 404 selects the path selection information of the state to be traced in accordance with the trace result information s401 and outputs as trace result information s403. The selecting circuit 403 selects the path selection information of four states having a possibility such that it is traced from the path selection information s106 in accordance with the trace starting state information s107 and outputs as pre-trace information s404. The pre-trace information s404 is inputted to the selecting circuit 405. The trace result information s401 and s403 is further inputted to the selecting circuit 405. The selecting circuit 405 selects the path selection information of the state to be traced in accordance with the trace result information s401 and s403 and outputs as trace result information s405. Finally, the trace result information s401, s403, and s405 is outputted as a trace result signal s109 in a lump with respect to three bits. With the construction of the tracing circuit 102 as mentioned above, in the embodiment of the invention, even if the tracing operation as many as a plurality of times is executed, a delay corresponding to two stages of selectors merely occurs as compared with the case of performing the tracing as many as one time. The decoding operating speed can be hardly deteriorated. The embodiment of the invention mentioned above uses a path memory circuit which has three dual-port RAMs of 1-write and 1-read and executes the tracing as many as three times for a period of time of one clock. On the other hand, another embodiment of the invention using a path memory circuit having a different construction is also possible. Fig. 15 shows a construction of the path memory circuit in another embodiment of the invention. The path memory circuit is a circuit which has four single-port RAMs (an RAM 50, an RAM 51, an RAM 52, an RAM 53) of the number of bits = 8 and the number of words = 3 and executes the tracing as many as three times for a period of time of one clock in case of performing the decoding of the cut length = 6 for a code of the restriction length = 4. Path selection information s502 which is inputted from the ACS circuit is sequentially stored into the RAMs every clock in accordance with the order of RAM 53 - RAM 52 - RAM 51 - RAN 50 RAN 53 - • • • in response to a write control signal s503. As for the RAMs 50, 51, 52, and 53, the path selection information is read out from the three RAMs every clock in response to a read control signal s504 and path selection information s505, s506, s507, and s508 is outputted. The path selection information s505, s506, s507, and s508 is inputted to a tracing circuit 502. The write control signal s503 and read control signal s504 are formed by a control circuit 501 and inputted to the RAMs 50, 51, 52, and 53, respectively. Timings of the memory operation based on the control circuit 501 are shown in Fig. 16. In the tracing circuit 502, the tracing as many as three times is executed in accordance with the path selection information s505, s506, s507, and s508 which is outputted from the RAMs 50, 51, 52, and 53 and trace starting state information s509 which is formed by the control circuit 501 and its result is inputted as a trace result signal s510 to the control circuit 501. The tracing circuit 502 can be constructed by combining, for example, the selecting circuits as used in the tracing circuit 102 in the embodiment of the invention shown in Fig. 14. In the control circuit 501, the trace starting state of the next clock is obtained while initializing the trace starting state every (cut length)/2 on the basis of the trace result signal s510 and a maximum likelihood state signal s501. Such a memory operation will now be specifically explained with reference to Figs. 17A to 17F and Figs. 18A to 18G. Figs. 17A to 17F and Figs. 18A to 18G show the writing/reading operations for the RAMs 50, 51, 52, and 53 at continuous times. As mentioned above, those four RAMs are single-port RAMs of the number of bits = 8 and the number of words = 3. For the purpose of saving of a drawing space, the states at time 1 to time 6 are shown in Figs. 17A to 17F and the states at time 7 to time 13 are shown in Figs. 18A to 18G. It is now assumed that all of the addresses in each memory are allocated to 0, 1, and 2 in accordance with the order from the left. The path selection information is sequentially written into each RAM until times 1, 2, 3, ..., and 9. At time 9, information is written into two addresses with respect to each RAM. The operation after time 10 subsequent to the above state is shown in Fig. 16. In the head clock in Fig. 16 corresponding to time 10, the storage contents (path selection information 9, 8, 7) are read out from addresses 2 in the three RAMs (namely, RAM 50, RAM 51, RAM 52) and the tracing is performed. At the same time, the subsequent path selection information 10 is written into address 0 in one RAM (namely, RAM 53). 't' added to a reading arrow denotes that the tracing is executed and 'd' indicates that the tracing is performed and the decoding is executed. In the second clock in Fig. 16 corresponding to time 11, the storage contents (path selection information 6, 5, 4) are read out from addresses 2 in the three RAMs (namely, RAM 50, RAM 51, RAM 53) and the tracing is executed. At the same time, the subsequent path selection information 11 is written into address 0 in one RAM (namely, RAM 51). The reading operation in this instance is executed with respect to addresses 1 with regard to the two RAMs (RAM 50, RAM 51) and is performed with regard to address 2 as for the other one RAM (RAM 53). Further, in the third clock in Fig. 16 corresponding to time 12, the storage contents (path selection information 3, 2, 1) are read out from addresses 2 in the three RAMs (namely, RAM 50, RAM 52, RAM 53) and the tracing is executed. After that, the decoding operations corresponding to the path selection information 1 to 9 are executed. At the same time, the subsequent path selection information 12 is written into address 0 in the other one RAM (namely, RAM 51). The reading operation in this instance is executed with respect to addresses 1 with regard to the two RAMs (RAM 52, RAM 53) and is performed with regard to address 0 as for the other one RAM (RAM 51). In the fourth clock in Fig. 16 corresponding to time 13, the storage contents (path selection information 10, 11, 12) are read out from addresses 0 in the three RAMs (namely, RAM 51, RAM 52, RAM 53) and the tracing and the initialization of the trace starting state are executed. At the same time, the subsequent path selection information 13 is written into address 0 in the other one RAM (namely, RAM 50). The decoding and the initialization of the trace starting state in the clock subsequent to the decoding are executed once every three clocks as mentioned above. At any one of the clocks, the subsequent path selection information as much as one address is inputted. On the other hand, the trace starting state information s509 is also inputted to an output buffer 503. The output buffer 503 stores lower three bits of the trace starting state information s507 after the tracing over the cut length was performed as decoding bits and rearranges them in accordance with the inherent time series and, after that, outputs as a decoding bit signal s511. As mentioned above, even in the other embodiment of the invention, as for the accesses to each RAM, the total number of words in the RAM of the path memory can be set to (the cut length) x 2 while setting the number of accesses to one time with respect to each clock. According to the path memory circuit in the other embodiment of the invention, since only the single-port memories are used, the circuit scale can be further reduced as compared with the embodiment of the invention described above with reference to Fig. 9 or the like. Further, in the tracing circuit 502, by preliminarily restricting the number of candidates of the states in a manner similar to the tracing circuit 102 in the path memory circuit 705 in the embodiment of the invention, the increase in the delay can be minimized. Although the embodiment of the invention and the other embodiment of the invention mentioned above have been described with respect to the case where the restriction length = 4 and the cut length = 6, the restriction length and the cut length are not limited to those values but can be set to arbitrary values. Although the embodiment and the like of the invention have been shown with respect to the case of performing the tracing operation as many as three times every clock as an example, for instance, various modifications such that the tracing operation as many as four times is executed every clock by a construction having four dual-port RAMs, the tracing operation as many as four times is executed every clock by a construction having five single-port RAMs, and the like are possible. As mentioned above, according to the invention, since the tracing operation as many as a plurality of times is executed for a period of time of one clock and the decoding is executed, the total number of words of the RAM in the path memory circuit can be reduced. Therefore, it is possible to contribute to the reduction of the circuit scale of the apparatus. Since the number of times of access to each RAM at every clock is equal to once and the increase in delay is minimized by the foregoing construction of the tracing circuit, the high speed decoding operation can be performed. Therefore, according to the invention, the Viterbi decoding apparatus in which a circuit scale is small and the high speed operation can be performed can be provided.

Claims: A Viterbi decoding apparatus for decoding a reception data signal (s701), comprising an add-compare-select circuit (702) for calculating state metrics, comparing values of the state metrics, and selecting a maximum likelihood path, a path memory circuit (705) comprising a predetermined number of RAMs (RAM10, RAM11, RAM12, RAM 50, RAM 51, RAM 52, RAM 53) for storing path selection information (s102, s502) and for executing the decoding operation by the trace-back method, whereby the path selection information (s102, s502) in the path memory circuit (705) is traced by an amount determined by a truncation length, and whereby the tracing operation is executed several times for a period of time of one clock, characterized in that said path memory circuit (705) stores said path selection information (s102, s502) sequentially into a different one of said RAMs (RAM10, RAM11, RAM12, RAM 50, RAM 51, RAM 52, RAM 53) every clock in accordance with a rotational order of said RAMs. An apparatus according to claim 1, wherein said RAMs (RAM10, RAM11, RAM12, RAM 50, RAM 51, RAM 52, RAM 53) are controlled in a way that path selection information (s102, s502) is sequentially read out from said RAMs at the time of tracing. An apparatus according to any of the preceding claims, wherein when the path selection information (s102, s502) is sequentially read out from said predetermined number of RAMs (RAM10, RAM11, RAM12, RAM 50, RAM 51, RAM 52, RAM 53) and the tracing operations are performed, the number of candidates of the states to be selected from the path selection information (s102, s502) is reduced in accordance with a trace starting state information. An apparatus according to any of the preceding claims, wherein said path memory has a predetermined number of dual-port RAMs (RAM10, RAM11, RAM12) of one-write and one-read, and the tracing operations as many as the times of the number that is equal to the number of said dual-port RAMs are executed for the period of time of one clock. An apparatus according to any of claims 1 to 3, wherein said path memory has a predetermined number of single-port RAMs (RAM 50, RAM 51, RAM 52, RAM 53), and the tracing operations as many as the times of the number that is smaller than the number of said single-port RAMs by one are executed for the period of time of one clock. An apparatus according to any of the preceding claims, wherein the number of times of access to each RAM at every clock is equal to once. A Viterbi decoding method of calculating state metrics, comparing values of the state metrics, selecting a maximum likelihood path, whereby path selection information (s102, s502) is stored in a path memory circuit (705) comprising a predetermined number of RAMs (RAM10, RAM11, RAM12, RAM 50, RAM 51, RAM 52, RAM 53), executing the decoding operation by the trace-back method, and performing tracing operations in order to trace back the path selection information (s102, s502) by an amount determined by a truncation length, whereby the tracing operation is executed several times for a period of time of one clock. characterized by storing said path selection information (s102, s502) sequentially into a different one of said RAMs (RAM10, RAM11, RAM12, RAM 50. RAM 51, RAM 52, RAM 53) every clock in accordance with a rotational order of said RAMs. A method according to claim 7, wherein in said tracing step, a reading operation is sequentially performed from said RAMs (RAM10, RAM11, RAM12, RAM 50, RAM 51, RAM 52, RAM 53). A method according to claim 7 or claim 8, further characterized by reducing the number of candidates of the states to be selected from the path selection information (s102, s502) in accordance with a trace starting state information when the path selection information (s102, s502) is sequentially read out from said predetermined number of RAMs (RAM10, RAM11, RAM12, RAM 50, RAM 51, RAM 52, RAM 53) and the tracing operations are performed. A method according to any of claims 7 to 9, where in said tracing step, the tracing operations as many as the times of the number that is equal to the number of dual-port RAMs (RAM10, RAM11, RAM12) of one-write and one-read are executed for the period of time of one clock. A method according to any of claims 7 to 9, where in said tracing step, the tracing operations as many as the times of the number that is smaller than the number of single-port RAMs (RAM 50, RAM 51, RAM 52, RAM 53) by one are executed for the period of time of one clock. A method according to any of claims 7 to 11, wherein the number of times of access to each RAM at every clock is equal to once.

Inventors: HATTORI MASAYUKI, MIYAUCHI TOSHIYUKI, HATTORI, MASAYUKI, MIYAUCHI, TOSHIYUKI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1998
Main classification: H03M13
IPC codes: G06F11, H03M13