Image sensor with photosensor chips and output circuit on a single mounting substrate

Abstract: There is provided a method of driving an image sensor which can remove FPN resulting from inter-chip variations without requiring any dark correction. A semiconductor photosensor chip has a plurality of sensor modules mounted on a mounting substrate, and a semiconductor device in which at least an N signal input buffer circuit for receiving N signals, an S signal input buffer circuit for receiving S signals, a differential circuit for calculating any difference between the outputs from the N and S signal input buffer circuits, and a voltage clamping circuit for clamping the output from the differential circuit are formed on a single semiconductor substrate, and the voltage clamping circuit clamps the reset state of S and N signal common output line.

Description: The present invention relates to an image sensor (for example, a linear contact image sensor) for reading images in e.g. a facsimile, image scanner, digital copying machine, or X-ray imaging apparatus, and, more particularly, one capable of removing fixed pattern noise (FPN) arising from inter-chip differences. In recent years, in the field of linear photo-electric conversion devices, an equal-magnification (magnification = 1) contact image sensor in which a plurality of semiconductor photosensors are mounted has been extensively developed in addition to CCDs using reducing optics. Fig. 1A is a partial block diagram showing the arrangement of a conventional contact image sensor having an amplifier element, which is disclosed in Journal of Television Society Vol. 47, No. 9 (1993), pp. 1180 (Reference 1). In this contact image sensor, a plurality of amplifier type semiconductor photosensor chips having amplifier elements in units of pixels are mounted. Especially, Fig. 1A shows the arrangement of a single sensor chip. The output from one sensor module is externally output via an analog switch 37. Fig. 1B shows a state wherein a plurality of sensor chips are connected. In order to enable the output of a specific chip, the analog switch 37 of that chip is energized. As shown in Fig. 1A, one sensor chip comprises a plurality of sensor elements (phototransistors 9), an output line 3 (4) which commonly receive the outputs from these transistors 9, differential amplifier 33, clamping circuit 204, and buffer amplifier 36, the above-mentioned analog switch 37, and the like. In the image sensor, since fixed pattern noise (FPN) resulting from variations of the amplifier elements used for a plurality of pixels is produced, FPN produced in the chip is removed by calculating the difference between a light signal (S signal) and noise signal (N signal) in a dark state (to be referred to as an "S-N method" hereinafter for the sake of simplicity) in the prior art shown in Fig. 1A. FPN removal using the S-N method in the image sensor shown in Fig. 1A will be described below with reference to Figs. 1A and 2 (timing chart). In Fig. 1A, the bipolar transistor 9 constructs a sensor portion of an photo-electric conversion element. Each transistor 9 is connected to a MOS transistor 27 (28), MOS transistor 31 (32), capacitances C TS 1 and C TN 2, and MOS transistor 25 (26), and the MOS transistors 25 and 26 of the respective bits are connected to the common output lines 3 and 4. Reference symbols C HS and C HN denote capacitances for the output lines 3 and 4. The output lines 3 and 4 are connected to the differential amplifier 33 via voltage-follower amplifiers 13 and 14. Upon irradiation of light onto the sensor 9 of the photo-electric conversion element, a light signal (i.e., a charge) corresponding to its light amount hν (h is a Planck constant, and ν is the frequency of the light) is accumulated on the PN junction of the emitter-follower transistor 9. Upon completion of accumulation, the transistor 9 is set in a floating state (by turning off  ERS ), and  TS is turned on to transfer the charge accumulated on the PN junction to the light signal holding capacitance C TS 1. Subsequently, a reset pulse  ERS is turned on to reset the sensor (transistor 9). At this time, the charge transferred to the capacitance C TS 1 contains noise components. After that,  TN is turned on to transfer a noise (N) signal of the sensor to the noise signal holding capacitance C TN 2. Again, a reset pulse  BRS is turned on to enable a MOS transistor 29, and the reset pulse  ERS is turned on to enable a MOS transistor 30. Since the MOS transistors 29 and 30 are ON, the sensor transistor 9 is reset and then starts the next accumulation. Some components of the charges accumulated on the C TS 1 and C TN 2 are respectively shifted to the output line capacitances C HS and C HN during the next accumulation. This operation is called "capacitive division" for the sake of simplicity since the original charges accumulated on C TS 1 and C TN 2 are divided as a result of movement of the charges between the two capacitances. The "capacitive division" is activated by the MOS transistors 25 and 26 when a control timing signal  N is ON. The "capacitive division" will be explained below. In order to reset holding capacitances C HS 7 and C HN 8, MOS transistors 5 and 6 are turned on by a signal  HC . After these capacitances are reset, the MOS transistors 25 and 26 are turned on by the timing signal  N output from a shift register (not shown). When the MOS transistors 25 and 26 are ON, data in the light signal holding capacitance C TS 1 and noise signal holding capacitance C TN 2 (some components of charges) are respectively transferred to the capacitances C HS 7 and C HN 8 connected to the common output lines 3 and 4. Consequently, the potential that appears on the output line 3 (4) is determined by the ratio between the capacitances C HS 7 and C TS 1 (the ratio between C HN 8 and C TN 2). The potential on the output line 3 (4) is amplified by the differential amplifier 33 via an amplifier 13 (14). Although not shown in Fig. 1A, as described above, one sensor chip has sensor elements 9 for a plurality of bits. In order to read out the sensor output of the next bit, the capacitances C HS 7 and C HN 8 are reset by turning on the MOS transistors 5 and 6, and a drive signal  N for that bit is then supplied to read out data accumulated on the capacitances C TS and C TN to the common capacitances C HS 7 and C HN 8. By repeating such shift operation, the charges accumulated on the sensors (transistors 9) of the respective bits are read out to the capacitances C HS 7 and C HN 8. Voltages induced on the capacitances C HS 7 and C HN 8 are input to the differential amplifier 33 via the voltage-follower amplifiers 13 and 14. Fixed pattern noise FPN in the sensor IC mainly arises from variations of h FE or the like of the bipolar transistors 9 of the respective pixels (bits). Such variations are reflected in the charges accumulated on the holding capacitances C TS and C TN . FPN removal using the S-N method removes noise resulting from h FE variations of the bipolar transistors 9 in units of pixels by detecting any level differences between the signal lines by the differential amplifier 33 upon reading out the charges accumulated on the holding capacitances C TS and C TN onto the common signal lines 3 and 4. The S-N method using the differential amplifier 33 is effective for removing FPN produced in the sensor chip. However, in case of the equal-magnification contact image sensor in which a plurality of photosensors are mounted, since a plurality of linear line sensor chips are cascade-connected, as shown in Fig. 1B, as it is of contact type, the differential amplifiers 33 and buffer amplifiers 36 are arranged in units of chips. Among the differential amplifiers 33 (or buffer amplifiers 36) of the different chips, the DC components of the output voltages vary due to variations of offset potentials. Such variations of the DC offset voltages among chips will be referred to as "FPN resulting from inter-chip differences (inter-chip FPN)" in contrast to "FPN produced in the chip (intra-chip FPN)" in this specification. The above-mentioned S-N method is not effective for inter-chip FPN. In the image sensor shown in Fig. 1A, the clamping circuit 204 copes with inter-chip FPN resulting from the differential amplifier 33. That is, the clamping circuit 204 is constructed by a capacitance 34 for cutting DC components from the output from the amplifier 33, and a MOS transistor 35 for fixing to earth level the potential between this capacitance 34 and the input portion of the amplifier 36, that shifts to the minus side. With this arrangement, the clamping circuit 204 can prevent inter-chip FPN attributed to the differential amplifier 33. However, the present inventors found that it is difficult to remove inter-chip FPN arising from the offsets of the output buffer amplifier 36 even by the prior art technique shown in Fig. 1A. Especially, when the initial stage of the output buffer amplifier 36 adopts a MOS top arrangement (in which the MOS transistor is located on the input side), since threshold value unbalance of that MOS influences the offsets, offset variations of, e.g., around 10 mV are produced among the output buffer amplifiers 36 of different chips. Even after a plurality of sensor chips are mounted, as shown in Fig. 1B, FPN of around 10 mV is produced. Hence, when a high-gradation image is to be obtained using the conventional image sensor, dark correction is required in units of chips to assure its dynamic range, and the cost required for system design and manufacture increases. In the prior art, each sensor chip includes a large-scale analog circuit such as a sensor, holding capacitances, and the like, and 10 to 20 chips are mounted. For this reason, the chip area for the analog circuit portion increases, and it is hard to reduce cost. Furthermore, each sensor chip includes both a digital circuit such as MOS transistors for light signal read and reset, and the aforementioned analog circuit, and the sensor output is readily influenced by noise produced by the digital circuit. The present invention is intended to provide a high-performance image sensor which can remove FPN arising from inter-chip variations and which does not require any dark correction. The present invention also is intended to provide an inexpensive image sensor which can obviate the need for any dark correction means, and can avoid an increase in cost resulting from an increase in chip area, which is inevitable in the prior art. The present invention also is intended to provide an image sensor, which can simultaneously remove intra-chip FPN and inter-chip FPN. An image sensor in accordance with the present invention is defined in claim 1 of the claims attached. The features recited in the preamble of this claim correspond to features of the image sensor described in reference 1 and previously identified herein with reference to Figures 1A and 1B, and 2. It is acknowledged that an image sensor is known, from the disclosure of European Patent Application EP-A-0488674, having a plurality of semiconductor photosensor chips mounted on a mounting substrate, each semiconductor photosensor chip having a signal holding capacitor for holding a signal comprising light signal and noise signal components, outputting switches and a line for outputting each signal held in the holding capacitor, and readout circuitry for outputting each signal on this line. The signals from each chip are output via a semiconductor device having a common input buffer and a voltage charging circuit following the common input buffer. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is the equivalent circuit diagram of a conventional image sensor; Fig. 1B is a diagram for explaining connections among individual sensor chips in the conventional image sensor shown in Fig. 1A; Fig. 2 is a timing chart for explaining the operation of the conventional image sensor shown in Fig. 1A; Fig. 3 is a schematic view showing an image sensor assembly according to the first embodiment of the present invention; Fig. 4A is the equivalent circuit diagram of an image sensor of the first embodiment; Fig. 4B is a diagram for explaining connections of principal part of the image sensor of the first embodiment; Fig. 5 is a timing chart showing one operation example of the image sensor of the first embodiment; Fig. 6 is a timing chart showing another operation example of the image sensor of the first embodiment; Fig. 7 is the equivalent circuit diagram of an image sensor according to the second embodiment of the present invention; Fig. 8 is a timing chart showing one operation example of the image sensor of the second embodiment; Fig. 9 is the equivalent circuit diagram of an image sensor according to the third embodiment of the present invention; and Fig. 10 is a timing chart showing one operation example of the image sensor of the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The arrangement, operation, and drive method of an image sensor according to the preferred embodiments of the present invention will be explained hereinafter with reference to the accompanying drawings. <First Embodiment> Fig. 3 shows the arrangement of an assembly 300 of a contact image sensor according to the first embodiment. In Fig. 3, the assembly 300 has a plurality of sensor chips 100, 100', 100",..., 100 n , a pair of common output lines 101 and 102 from these sensor chips, and one amplifier chip 200. In principle, each of the sensor chips 100,... has two output terminals, which are respectively connected to the common output lines 101 and 102. The two input terminals of the amplifier chip 200 are respectively connected to the common output lines 101 and 102. The amplifier chip 200 has a single output terminal V OUT . The output from this terminal V OUT is that of the assembly 300. Note that parts such as capacitances, resistors, and the like (not shown) are also mounted on the assembly 300 shown in Fig. 3. In Fig. 3, the sensor chips 100, 100', and 100", and the amplifier chip 200 are mounted on a single mounting substrate 300, Since the sensor chips 100,... are mounted on a single mounting substrate together with the amplifier chip 200, the size of the assembly 300 can be reduced, and external noise that may be produced in the outputs of the sensor chips 100,... can be reduced, thus stabilizing the output. Note that the amplifier chip 200 which is encapsulated in a ceramic package may be mounted on the mounting substrate 300 by soldering, or it may be mounted on the mounting substrate 300 by dye-bonding. When it is mounted by dye-bonding, common chucks can be used for the sensor and amplifier chips if the short side length of each sensor chip is set to be substantially equal to that of the amplifier chip, thus reducing the number of steps in a mounting process. Fig. 4A shows the equivalent circuit of each sensor chip (100, 100', 100",...) and that of the amplifier chip 200 according to the first embodiment. In Fig. 4A, the sensor chip according to the first embodiment has a plurality of photo-electric converters 10, 10', 10",..., noise signal holders 2, 2', 2",... for reading out noise signals (to be abbreviated as "N signals" hereinafter) from these photo-electric converters and holding the N signals, S signal holders 1, 1', 1",... for reading out light signals (to be referred to as "S signals" hereinafter) from the photo-electric converters and holding the S signals, an N signal output line 4 for commonly outputting N signals, an S signal output line 3 for commonly outputting S signals, reset circuits 5 and 6 for resetting the N and S signal output lines 4 and 3, and a read-out circuit for reading out signals held by the N signal holders 2, 2', 2",... and those held by the S signal holders 1, 1', 1",... by capacitance or capacitive division between capacitances C HN 8 and C HS 7 of the N and S signal output lines 4 and 3. The capacitance division will be explained later. Note that the photo-electric converter 10, 10', 10",... preferably use bipolar elements such as, e.g., BASIS, or amplifiers each consisting of a photo-diode and MOS transistor. The signal holder preferably comprises a capacitor, as shown in Fig. 4A, and the reset circuit preferably comprises a transistor circuit. Each of the photo-electric converters 10, 10', 10",... is connected to a pair of MOS transistors 27 and 28. An array of MOS transistors 27 commonly receive a control signal  TS . An array of MOS transistors 28 commonly receive a control signal  TN . When a transfer pulse  TS is turned on, S signals are stored in the S signal holders (capacitances) C TS 1, 1', 1",...; when a transfer pulse  TN is turned on, N signals are stored in the N signal holders (capacitances) C TN 2, 2', 2",.... That is, when the transfer pulses  TS and  TN are turned on, the S and N signals detected by the photo-electric converters 10, 10', 10",... are respectively stored in the holders C TS 1, 1', 1",..., and the holders C TN 2, 2', 2" ,.... In order to supply the outputs from the photo-electric converters 10, 10', 10",... onto the common output lines 3 and 4, the common output lines 3 and 4 must be reset before that. The MOS transistors 5 and 6 are turned on to reset the S and N signal output lines 3 and 4. Upon being reset in this way, the lines 3 and 4 are ready to transfer data to the capacitances C HS 7 and C HN 8. The MOS transistors 25 and 26 are then enabled using a shift pulse  1 of a shift register SR to output data (charges) in the capacitances C TS and C TN in turn onto the common output lines 3 and 4 by capacitance division. Some components of the charges accumulated on C TS and C TN are respectively transferred to the capacitances C HS 7 and C HN 8. As a result, the charge accumulated on C TS is divided into C TS 1 and C HS 7, and the charge accumulated on C TN is divided into C TN 2 and C HN 8. When the charge is divided into two capacitances, the potential between these two capacitances will be referred to as the capacitively divided output in this specification. The capacitively divided outputs are impedance-converted by amplifiers 11 and 12, and are then output onto the S and N signal lines 101 and 102 on the mounting substrate via analog switches 14 and 15. In Fig. 4A, each of the amplifiers 11 and 12 uses a source-follower circuit including two transistors, but may use, e.g., a normal voltage-follower circuit. Data detected by the sensor element 10 is output onto the S and N signal lines 101 and 102 in response to a shift pulse  1 , as described above. Next, data detected by the sensor element 10' is similarly output onto the S and N signal lines 101 and 102 in response to a shift pulse  2 . Furthermore, data detected by the sensor elements 10" is output onto the S and N signal lines 101 and 102 in response to a shift pulse  3 . The sensor module (100, 100', 100",...) as a semiconductor photosensor is connected to the S and N signal lines 101 and 102 and one amplifier chip 200 mounted on a single mounting substrate via terminals 99 mounted on the same mounting substrate by wire bonding. That is, S and N signals from the sensor modules (100, 100', 100",...) are input to the amplifier chip 200. The amplifier chip 200 shared by the plurality of sensor modules (100, 100', 100",...) has a buffer amplifier 201 for receiving an N signal, a buffer amplifier 202 for receiving an S signal, a differential amplifier 203 for calculating the difference between the outputs from the amplifiers 201 and 202, a voltage clamping circuit 204 connected to the output side of the differential amplifier 203, and an output buffer amplifier 205, as shown in Fig. 4A. Note that the voltage clamping circuit 204 comprises a clamping capacitance 206, and a MOS switch 207, and has a function of clamping the input signal toward a clamping reset voltage V CD . The characteristic features of the first embodiment shown in Fig. 4A are as follows: I: The clamping circuit 204 for removing inter-chip FPN is mounted outside the plurality of sensor chips 100,... but inside the amplifier chip 200 as a circuit common to these sensor chips. For this reason, clamping circuits (204 in Fig. 1A) in units of sensor chips, which are required in the conventional image sensor (Fig. 1A), can be omitted. II: In order to effectively remove inter-chip FPN, the generation timing of a signal  CHR for controlling the reset timing of the output lines 3 and 4 and the generation timing of a signal  CD for controlling the clamping circuit 204 are appropriately set. Two examples of the generation timings of  CHR and  CD will be explained later. III: Since the differential amplifier 203 for differentially amplifying the outputs from the pair of common output lines 3 and 4 is mounted inside the amplifier chip 200, the number of differential amplifiers which are required in units of chips in the prior art (Fig. 1A) can be reduced to one, and the number of circuit elements can be greatly decreased. IV: As a combined effect of the features I to III, the timings set in II can remove not only "inter-chip FPN" but also "intra-chip FPN" at the same time. According to the arrangement shown in Fig. 4A, since the buffer amplifier 36 can be omitted from each sensor chip, generation of inter-chip FPN can be reduced as compared to Fig. 1A. However, since the source-follower amplifiers 11 and 12 are required in place of the buffer amplifier 36, "inter-chip FPN" due to inter-chip variations of the source-follower amplifier 11 (or 12) remains unsolved. The drive control method for the image sensor of the first embodiment, especially, the drive control method for removing inter-chip FPN will be explained below with reference to Fig. 5. Fig. 5 shows signals  TN and  TS for determining the charge transfer timings of the converter 10, shift pulses  1 ,  2 , and  3 from the shift register SR, a reset pulse  CHR for resetting the common signal lines 3 and 4, and a reset pulse  CD for resetting the clamping circuit 204 in the amplifier chip 200. Fig. 4B shows principal elements of the image sensor (Fig. 4A) of the first embodiment. Referring to Fig. 4B, the reset circuit which receives  CHR and the clamping circuit 204 which receives  CD are present between the capacitances C HS 7, 7', 7",... (capacitances C HN 8, 8', 8",...) on the common output lines 3, 3', 3" (and output lines 4, 4', 4"), and the output V OUT of the amplifier chip 200. The MOS transistors 5 and 6 must be reset by  CHR at each shift timing ( 1 ,  2 ,  3 ,...) before each of the pulses  1 ,  2 ,  3 ,... is input, so as to cancel variations (intra-chip FPN) of each sensor converter 10 in a single chip. DC offset variations resulting from the source-follower amplifiers 11 and 12 can be removed by driving the clamping circuit 204 in Fig. 4B. More specifically, referring to Fig. 4A, a clamping pulse  CD which changes LOW → "H" → LOW is input to the gate of the MOS transistor 207. During the LOW period of  CD , the differential amplifier 203 outputs an output signal which reflects DC offset variations caused by the source-follower amplifiers 11 and 12. This voltage is input to the DC cutoff capacitor (clamping capacitance) 206. When  CD changes from LOW to HIGH, the source side of the MOS transistor 207 is clamped to a potential V CD . Then, the potential difference across the two terminals of the DC cutoff capacitor 206 reflect DC offset variations caused by the source-follower amplifiers 11 and 12. In this state, when  CD changes from HIGH to LOW, since the MOS transistor 207 is turned off, the charge accumulated on the capacitor 206 is held at a charge value for canceling inter-chip FPN. When a shift pulse  N is applied from the shift register SR to the MOS transistors 25 and 26 at that time, an output signal from which not only "intra-chip FPN" but also "inter-chip FPN" are canceled appears at the output of the voltage-follower amplifier 205. That is, it is important for the timings in Fig. 5: V: to output the clamping pulse  CD before each shift pulse  N (one of  1 ,  2 ,  3 ,...); and VI: to reset the MOS transistors 5 and 6 before the clamping pulse  CD is output. In the control timing example shown in Fig. 5, the reset pulse  CHR goes HIGH and then LOW before the clamping pulse  CD goes HIGH. The operation of the circuit shown in Fig. 4A will be described in more detail below with the aid of Fig. 5. After signals  TN and  TS are input, S signals have already been read out to the capacitances C TS 1, 1', 1",..., and N signals to the holding capacitances C TN 2, 2', 2",.... Read-out signals (shift pulses)  1 ,  2 ,  3 ,... are output in turn from the shift register SR, and sensor detection signals are read out onto the signal lines 3 and 4 by capacitance division between the capacitances C TS and C HS , and between C TN and C HN , as described above. In Fig. 4A, the MOS transistor 207 in the clamping circuit 204 is controlled by the control signal  CD . According to the timings shown in Fig. 5,  CD is enabled after  CHR is enabled. Hence, during the period from when  CHR is enabled until  CD is enabled, the capacitances C HS 7 and C HN 8 are reset to desired voltages by  CHR immediately before the signals on the signal lines 3 and 4 are read out after  CHR . In addition, the state after the capacitances C HS 7 and C HS 8 have been reset is clamped by  CD , and is used as a reference state. Hence, the outputs after capacitance division contain Vth variations of the source-follower amplifiers 11 and 12 in units of chips. However, since these outputs are obtained after Vth variations are corrected by the above-mentioned operations, inter-chip FPN that has conventionally posed a problem can be removed without any dark correction. <Modification of Control Timings> The control timings of the clamping circuit 204 of the first embodiment are not limited to those shown in Fig. 5. Fig. 6 shows another timing example that can be applied to the image sensor (Fig. 4A) of the first embodiment. In the example shown in Fig. 6, the reset pulse  CHR is held at HIGH, and then goes LOW after the clamping pulse  CD goes LOW and before the shift pulse  N is turned on. According to the timing example shown in Fig. 6, since the reset state of the capacitances C HS 7 and C HN 8 by the reset pulse  CHR is clamped by the clamping pulse  CD , the same effect as in the timing example shown in Fig. 5 can be obtained. According to the first embodiment, since the need for a differential amplifier in each sensor chip can be obviated as compared to the image sensor shown in Fig. 1A, the output portion of each sensor chip can be simplified, and the chip area of the analog portion in each sensor chip can be minimized. In addition, since the analog portion for all the sensor chips can be integrated using the common signal lines 101 and 102, the chip area of each module can be minimized, thus attaining a cost reduction. <Modification of First Embodiment> In the image sensor assembly 300 of the first embodiment, when the power supply for the sensor chips 100, 100', 100",... and that for the amplifier chip 200 are independently set, a broad dynamic range of the output can be maintained even when the sensor power supply voltage is decreased. In the first embodiment, a contact image sensor using a plurality of line sensor chips has been exemplified. However, the present invention is not limited to such specific sensor, but may be effective for a two-dimensional area sensor including a large number of sensor chips. Especially, when area chips in small regions have different photo-electric conversion sensitivities, FPN variations become more conspicuous than a 1-line contact sensor and, hence, it is very effective to apply the present invention. As another modification, when an amplification function is added to the amplifier chip 200, the amplification function may be added to, e.g., the differential amplifier 203 or a gain amplifier may be inserted on the output side of the differential amplifier 203. In the arrangement shown in Fig. 4A, the sensor chip 100 and amplifier chip 200 use a common power supply. Alternatively, when the power supplies for the sensor chip 100 and amplifier chip 200 are isolated on the mounting substrate, the sensor chip and amplifier chip may use different power supply voltages, or independent GND terminals may be used on the mounting substrate to reduce noise in analog output. <Second Embodiment> Fig. 7 is a circuit diagram of an image sensor according to the second embodiment of the present invention. In the second embodiment, photo-electric converters in each of the sensor chips 100, 100', 100",... of the first embodiment are respectively constructed by photo-diodes 20, 20', 20",..., reset switches 21, 21', 21",..., NMOS source-follower transistors 22, 22', 22",..., transfer switches 23, 23', 23",.... As other building elements of the second embodiment, each sensor chip has N signal holders 2, 2', 2",..., S signal holders 1, 1', 1",..., an N signal output line 4, an S signal output line 3, and reset switches 5 and 6, as in the first embodiment (Fig. 4A). The characteristic feature of the second embodiment lies in that the level of a final output V OUT of a sensor assembly 300 can be adjusted by adding a gain amplifier 208 to an amplifier chip 200'. However, when the gain amplifier 208 is added, the output V OUT of the assembly 300 suffers an individual difference due to individual offset variations in the gain amplifier 208. Such individual difference will be referred to as an "inter-assembly FPN" hereinafter for the sake of simplicity. In the image sensor of the second embodiment, a clamping circuit 209 is added to remove this "inter-assembly FPN". The arrangement of the image sensor of the second embodiment will be described in more detail below. The capacitively divided outputs that appear on the N and S signal output lines 4 and 3 are impedance-converted by source-follower amplifiers 11 and 12 each including two transistors, and are then output onto S and N signal lines 101 and 102 via analog switches 14 and 15. S and N signals on the S and N signal lines 101 and 102 are input to the amplifier chip 200' mounted on the same chip as the sensor chips. The amplifier chip 200' of the second embodiment comprises an N signal input buffer amplifier 201, S signal input buffer amplifier 202, differential amplifier 203, voltage clamping circuit 204, gain amplifier 208 (gain = A), voltage clamping circuit 209, and output buffer amplifier 205. A clamping control signal to the voltage clamping circuit 204 is  CD as in the first embodiment, and a clamping signal for controlling the voltage clamping circuit 209 is  CL . Fig. 8 is a timing chart of control signals in the second embodiment. The clamping signal  CD to the clamping circuit 204 must be generated at the charge transfer timing ( 1 ,  2 , and  3 in Fig. 8) of each bit as in the first embodiment, since it aims at removing FPN for each bit. On the other hand, as the clamping circuit 209 removes offset FPN produced in each assembly, the clamping signal  CL for the clamping circuit 209 need only be generated once for a start signal SP (equivalent to a signal SP in Fig. 2) which is generated once for the assembly 300 at the beginning of image reading, as shown in Fig. 8. In the second embodiment, the voltage clamping circuit 209 reduces offset variations ("inter-assembly FPN") for each module including the sensor chips 100, 100', 100",..., and the amplifier chip 200', and a nearly uniform reference level of the module (i.e., the assembly) can be maintained. Since variations of the module (i.e., the assembly) can be reduced, variations in units of products can be reduced, and the manufacture of high-quality products can be achieved. In the second embodiment, the power supplies and GND terminals for the sensor chips 100, 100', 100",..., and amplifier chip 200' are isolated from each other on the mounting substrate, and the power supply voltages for the sensor chip and amplifier chip are respectively 3.3 V and 5.0 V. The operation of the second embodiment will be described below with reference to the timing chart in Fig. 8. Fig. 8 shows the drive timing relationship among read-out signals  1 ,  2 , and  3 from a shift register SR, a reset pulse  CHR of the common signal lines 3 and 4, and reset pulses  CD and  CL in the amplifier chip 200'. After signals are read out to the S signal holding capacitances (holders) C TS 1, 1', 1",..., and N signal holding capacitances (holders) C TN 2, 2', 2",..., read-out signals  1 ,  2 ,  3 ,... are output in turn from the shift register SR, and signals detected by the photosensors are read out by capacitance division between C TS and C HS , and between C TN and C HN . Immediately before these signals are read out, capacitances C HS 7 and C HN 8 are reset to desired voltages by turning on the MOS transistors (switches) 5 and 6 in response to the reset pulse  CHR . After C HS 7 and C HN 8 are reset, the clamping circuits 204 and 209 enabled by the clamping signals  CD and  CL generate reference signals. Hence, the outputs after capacitance division contain variations caused by a threshold voltage Vth of the source-follower amplifiers 11 and 12 in units of chips. However, since the outputs are obtained after Vth variations are corrected by the above-mentioned operations of the reset pulses and the like, inter-chip FPN that has posed a problem in the prior art can be removed. That is, in the second embodiment as well, the problem of "inter-chip FPN" can be solved. In this way, the second embodiment can remove all of "intra-chip FPN", "inter-chip FPN", and "inter-assembly FPN". More specifically, the inter-chip difference is around 10 mV in the conventional module, but is 3 mV or less in the second embodiment. Note that  CD for controlling the clamping timing of the clamping circuit 204 is generated at the first bit in the second embodiment, but may be generated in synchronism with the generation timings of other bits. <Third Embodiment> Fig. 9 is a circuit diagram showing the third embodiment of the present invention. In this embodiment, N and S signals are read out time-serially (i.e., by time division), and the output state of N signals is clamped and is used as a reference signal. In the third embodiment, the arrangement of each of the sensor chips 100, 100', 100",... is substantially the same as that in the second embodiment, i.e., comprises photo-diodes 20, 20', 20",..., reset switches 21, 21', 21",..., NMOS source-follower transistors 22, 22', 22",..., transfer switches 23, 23', 23",..., N signal holders 2, 2', 2",..., and S signal holders 1, 1', 1",..., except that N and S signals are time-serially (time-divisionally) read out onto a single common output line 55. That is, the single common output line 55 is sequentially reset by a reset MOS transistor 56. Since time-division driving is done, the number of source-follower amplifiers 11 including two transistors for amplifying N and S signals can be reduced to one as compared to the second embodiment. An amplifier chip 200' of the third embodiment comprises an input buffer amplifier 201, voltage clamping circuit 204, gain amplifier 208, voltage clamping circuit 209, and output buffer amplifier 205 as in the second embodiment. That is, the reason why the voltage clamping circuit 209 is added in the third embodiment is to remove "inter-assembly FPN" as in the second embodiment. Fig. 10 shows the operation of the third embodiment, i.e., the drive timing relationship among read-out signals  1S ,  1N ,  2S ,  2N ,  3S , and  3N from a shift register SR, a reset pulse  CHR of the common signal line 55, and reset pulses  CD and  CL in the amplifier chip 200'. After signals are read out to the S signal holding capacitances (holders) C TS 1, 1', 1",..., and N signal holding capacitances (holders) C TN 2, 2', 2",..., the common output line is reset by  CHR , and an N signal for the first bit is read out by capacitance division onto the common output line 55 in response to  1N . The read-out state of the N signal is clamped in response to  CD , and is used as a reference signal for the first bit. Subsequently, the common output line 55 is reset by  CHR , and an S signal for the first bit is read out by capacitance division onto the common output line 55 in response to  1S . The difference between the S signal for the first bit and a voltage clamped to the N signal is input to the gain amplifier 208 via the signal input buffer amplifier 201, and variations in units of pixels can be removed by this clamping function. In addition, variations of the sensor chips 100, 100', 100",... can be removed. Likewise, signals for the second and third bits are read out, and after all the bit pixel signals of the sensor chip are read out, a switch 14 of that sensor chip output is turned off and a signal for the first bit of the next sensor chip is read out. In the arrangement of the third embodiment, inter-chip FPN is 2.9 mV or less; the FPN removal effect can be improved. Note that  CD for controlling the clamping timing of the clamping circuit 204 is generated at the first bit in the third embodiment, but may be generated in synchronism with the generation timings of other bits. According to the present invention, a method of driving a high-performance contact image sensor which can remove inter-chip FPN without requiring any dark correction can be provided. More specifically, since the output is clamped using as a reference signal the level obtained upon resetting the common output lines after signals are output from each sensor module to the amplifier chip, a reference potential can be obtained in the final state of photo-electric conversion, thus reliably removing FPN. Of course, since the dynamic range can be maximized, the need for dark level correction means can be obviated. Also, since the state immediately after the common output lines are reset is used as a reference potential for the clamping circuit, the clamping circuit can clamp at a reliable level in correspondence with a stable reset level, thus removing FPN for each chip. Furthermore, since variations in units of output lines in the capacitively divided outputs from each photo-electric conversion chip can be corrected in units of chips, FPN can be removed as a whole. As described above, since the level obtained upon resetting the common output lines after signals are output from each sensor module to the amplifier chip is clamped as a reference signal, a reference potential can be obtained in the final state of photo-electric conversion, thus reliably removing FPN. Of course, since the dynamic range can be maximized, the need for dark level correction can be obviated. Also, since the state immediately after the common output lines are reset is used as a reference potential for the clamping circuit, the clamping circuit can clamp at a reliable level in correspondence with a stable reset level, thus removing FPN for each chip. As described above, the module chips 100 and amplifier chips 200 are mounted on a single mounting substrate and are thus integrated into a single module. The earth wiring for the semiconductor photosensor chips and the earth wiring for the semiconductor (amplifier) device can be isolated from each other on the common single mounting substrate. As many apparently widely different embodiments of the present invention can be made without departing from the scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.

Claims: An image sensor including a sensor module having a plurality of semiconductor photosensor chips (100,100',...) mounted on a mounting substrate (300), wherein each semiconductor photosensor chip has on a semiconductor substrate: signal holding means (1,2) for holding first signals (S) including light signals and noise signals, and second signals (N) including noise signals read out from a plurality of photo-electric conversion elements (10,10'...;20,20',...); output means (3,4,7,8,25,26;55) for outputting the first signals and the second signals in said signal holding means; reset means (5,6;56) for resetting said output means; and read-out means (11-14,99;11,14,99) for outputting the signals from said output means; said image sensor being characterised by : a semiconductor device (200;200') including on a semiconductor substrate: common buffer means (201,202;201) for receiving the first signals and the second signals from each semiconductor photosensor chip and outputting first and second signals; common differential means (203;204) for calculating a difference between each of said first and second signals output from said buffer means; and common voltage clamping means (204) for clamping an output from said differential means, wherein said semiconductor photosensor chips (100,100',...) and said semiconductor device (200;200') are mounted on a single mounting substrate (300). An image sensor according to claim 1, wherein it is arranged that the power supply voltage that is applied to said semiconductor device (200;200') is higher than the power supply voltage that is applied to said semiconductor photosensor chips (100,100',...). An image sensor according to claim 1, wherein earth wiring for said semiconductor device and earth wiring for said semiconductor photosensor chips (100,100',...) are isolated from each other on said mounting substrate (300). An image sensor according to any one of claims 1 to 3, wherein said output means (55) includes a common output line (55) for sequentially outputting the first signals (S) and the second signals (N) from said signal holding means (1,2). An image sensor according to any one of claims 1 to 3, wherein said output means (3,4,7,8,25,26) includes a light signal common output line (3) for outputting the first signals (S) from said signal holding means (1), and a noise signal common output line (4) for outputting the second signals (N) from said signal holding means (2). An image sensor according to any preceding claim, wherein said common differential means comprises a differential amplifier (203). An image sensor according to any preceding claim, wherein said differential means (204) includes a second clamping means (204) for clamping the second signals (N). An image sensor according to any preceding claim, wherein said semiconductor device (200') includes a gain amplifier (208) for amplifying an output from said voltage clamping means (204), output buffer means (205) for outputting an output from said gain amplifier to outside of said semiconductor device, and third voltage clamping means (209) arranged between said gain amplifier and said output buffer means.

Inventors: KOZUKA HIRAKU, KOZUKA, HIRAKU, Kozuka, Hiraku, c/o Canon K.K.
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1998
Main classification: H04N5
IPC codes: H04N5