METHOD FOR SWITCHING DATA BETWEEN BITSTREAMS TRANSFERRED IN CIRCUIT SWITCHED CHANNELS

Abstract: The present invention refers to a method, an apparatus and a switch for switching data transferred in circuit switched channels between at least three unidirectional multi-channel time division multiplexed bitstreams that are accessed at respective ports of a switch. According to the invention, data is transferred between said ports in circuit switched channels of a switch internal unidirectional multi-channel time division multiplexed bitstream that is accessed by said ports.

Description: METHOD FOR SWITCHING DATA BETWEEN BITSTREAMS TRANSFERRED IN CIRCUIT SWITCHED CHANNELS Technical Field of Invention The present invention refers to a method, an apparatus, and a switch for switching data transferred in circuit switched channels between at least three unidirec- 5 tional multi-channel time division multiplexed bitstreams that are accessed at respective ports of a switch. Technical Background and Prior Art Today, new types of circuit-switched communication 10 networks are being developed for the transfer of information using synchronous or isochronous, time division multiplexed bitstreams, wherein a bitstream is divided into cycles, each cycle in turn being divided into time slots . 15 An example of such a network is a DTM (Dynamic synchronous Transfer Mode) network, which for example is described in "The DTM Gigabit Network", Christer Bohm et al., Journal of High Speed Networks, 3(2), 109-126, 1994. The basic topology of a network of this kind is pre- 20 ferably a bus with two unidirectional, multi-access optical fibers connecting a number of network nodes. Note, however, that the topology may just as well be realized by any other kind of structure, e.g. a ring structure or a hub structure. 25 The bandwidth of each wavelength on the bus, i.e. each bitstream on each fiber, is divided into fixed rate cycles that in turn are divided into fixed size time slots. The number of slots in a cycle thus depends on the network's bit-rate. The time slots are divided into two 30 groups, control slots and data slots. Control slots are used for transferring of signaling messages between said nodes for the network's internal operation. The data slots are used for the transfer of data between said users connected to the different nodes. 35 Each node is arranged to dynamically allocate time slots for its respective end users to use when sending or receiving information to or from other nodes . As a result, different end users have write access to different data slots. In this manner, multi-rate circuit switched channels may be established on a bitstream, each being defined by a respective set of one or more time slot positions within each frame of the bitstream. In such a network, so called switches are used to switch data between channels on different bitstreams. In the above mentioned article "The DTM Gigabit Network by Christer Bohm et al . , a switch in a DTM network is described, wherein data is transferred between ports of the switch using a switch internal slotted parallel ring bus that provides one slot for each pair of adjacent ports on the bus. An advantage with using this solution for transferring data between ports of the switch is that a slotted ring bus of the kind described is simple to design and operate. However, a problem with this prior art is that over-dimension of the internal ring bus capacity in relation to the bandwidth of the external bitstreams are necessary in order to prevent congestion, especially causing a problem at high throughput. Another problem is that control of the internal bus resources is very limited, increasing the risk of temporary congestion or data loss due to inability to adapt to traffic on external bitstreams. Objects of the invention An object of the invention is therefore to provide a switch that provides increased control of switching capacity as well as increased possibilities of switching data in space and time, such as efficient space multicasting of multi-rate channels. Another object of the invention is to provide a simple and fast mechanism for switching between multiple incoming and outgoing bitstreams. Summary of the Invention The above mentioned objects are achieved by a method and an apparatus as defined in the accompanying claims . According to the invention, data transferred in cir- cuit switched channels is switched between at least three unidirectional multi-channel time division multiplexed bitstreams that are accessed at respective ports of a switch using circuit switched channels of a switch internal unidirectional multi-channel time division multi- plexed bitstream that is accessed by said ports. The invention is thus based upon the idea of transferring data between the ports of the switch using an internal bitstream providing similar features as the bitstreams used for transferring data between the nodes of the surrounding network. As channels for data transfer through the switch may be established, modified, and terminated using the invention in a similar way as channels are established modified and terminated within the network, control of switching resources is advantage- ously increased as compared to prior art. Hence, according to an embodiment of the invention, the allocation of channels on said switch internal bitstream is dynamically adjusted based upon changes in allocation of channels on said two or more bitstream. The allocation of channels on the internal bitstream could for example also be adjusted based upon the demand for switching capacity of individual channels . The invention thus provides the very advantageous possibility of changing the switching capacity of the different switch paths through the switch, i.e. the switching bandwidth allocated to the different ports of the switch, dynamically as the demand for switching capacity changes. By creating such a correspondence and similarity between the "outside" (with respect to the switch) network and the "inside" transferring of data, a quicker and more compatible performance of the switch will be obtained. Preferably, the frame, or cycle, rate of the internal bitstream is synchronized to the frame rate of the network, or to a multiple of the frame rate of the network, thus providing compatibility with the outside network and facilitating the transfer of circuit switched channels through the switch. With regards to the synchronization of the operation of the switch in relation to the internal bitstream, the different input/output ports may have different degree of freedom in relation to the internal bitstream. According to one alternative, each port will operate in relation to the internal bitstream like a node in a DTM-like network, i.e. will derive bit clock, detect the start of frame and provide time slot count from the internal bitstream by itself. According to another alternative, the bit clock of the internal bitstream is distributed to the different ports of the switch by a central control unit (for example like the one designated 150 in the figures to be described below) , whereas the detection of start of frame, the counting of slots and other features in relation to the internal bitstream are still handled at each port. According to yet another alternative, both bit clock rate and time slot count (and thus the start of frame) are distributed centrally, e.g. by said control unit. In the latter case, the time slot count may be individual for each port, i.e. at a point in time when the time slot count at a second port is one (1) the time slot count at a first port will be two (2) , or may be common for all ports, i.e. at a point in time when the time slot count at a second port is one (1) the time slot count at a first port will also be one (1) . (In the latter case, a specific time slot count will correspond to different time slots position of the actual frame at different ports.) Consequently, the time slot mapping tables at the switch ports have to be controlled accordingly at channel set-up. If using an internal bitstream lacking terminating ends, i.e. a bitstream forming a closed loop within the node, a problem will arise if the number of time slots of a frame (for example a frame comprising 4000 time slots) is larger than the number of time slots corresponding to the amount of time required for a time slot to travel once through the loop (for example a loop travel time corresponding to only 3000 time slots) . In such a situation, at at least one location on the loop a port or a similar unit will find itself transmitting slot number 3000 out of a frame of 4000 time slots while already receiving the initially transmitted slot number one (1) . There are two preferable solutions to this problem. One solution is to provide for buffering of 1000 time slots at said unit (i.e. the time slots 1-1000 will be buffered by said unit as it transmits time slots 3001- 4000, and so on) . This is a simple procedure, which unfortunately provides an undesired delay through the switch. Also, a frame buffer may be used to map the time slot to any available slot (if there are any) . According to another solution, when establishing a channel on a segment of the bitstream carrying medium comprising said unit, one time slot of the frame is allocated on one side of said unit and another time slot of the frame is allocated on the other side of said unit. If, according to the situation discussed above, a channel is established to comprise slot number 1 on the receiving side of said unit and slot number 3001 on the transmitting side of said unit, the time slot data of time slot number 1 may simply be transferred by said unit directly from the received slot one (1) to the transmitted slot 3001 without any need for intermediate buffering. Of course, if this solution is used without the reuse of said time slot positions for channels on other segments, two time slots instead of just one will be used within each frame for the transfer of only one piece of time slot data, which may be undesired. This solution is hence preferably used in connection with a time slot reuse scheme as discussed further below. Since at least three ports have access to the same internal bitstream, the property of optional space multicasting is inherently provided. As is understood, different output ports of the switch may be controlled to read time slot data from different time slots of the internal bitstream, or from the same time slots of the internal bitstream, or a combination thereof, thus providing switching freedom. Whether or not a received time slot will be multicasted, broadcasted, or transferred point- to-point between different output ports will depend on slot mapping instructions controlling the ports of the switch. Also, switching in the time domain as well as the space domain is easily achieved by control of the slot mapping instructions of the ports. As is understood, space multicasting according to the invention, i.e. the switching of time slot data from at least one input port to at least two output ports, may involve the selection of different single output ports for different input time slots, the selection of more than one output port for an input time slot as well as the selection of all output ports for said input time slot (broadcasting) . Preferably, means are provided for controlling, at each input port, for each time slot of a cycle of the corresponding bitstream at the input port, whether or not the time slot data thereof is to be written into said internal bitstream, and, if so, which time slot of the internal bitstream that said time slot data is to be written into. Similarly, means are provided for controlling, at each output port, for each time slot of said internal bitstream, whether of not the time slot data thereof is to be written into the respective output bitstream, and, if so, which time slot of the respective output bitstream that said time slot data is to be written into. As is understood, there is no limit as to the number of input and output ports connected to said internal bit- stream. Also, each output port may act as an input port as well, and each input port may act as an output port as well, thus providing bi-directional functionality at each port . In an alternative embodiment, the switch comprises more than one internal bitstream, for example a set of two or more parallel bitstreams, wherein the ports of the switch may be connected to all, some or just one of said bitstreams . Also, in yet another embodiment, time slot alloca- tion on said internal bitstream is divided into segments, a specific time slot then being used for communication between a first set of ports on a first portion of a bitstream carrying medium and for communication between another set of ports on another portion of said bitstream carrying medium, thus providing better utilization of the bitstream bandwidth. According to an embodiment, a time slot position in each cycle of said at least one bitstream, containing data to be transferred to/from said internal bitstream, is unambiguously associated with a respective time slot position in each cycle of said shared bitstream, said data hence being transferred thereto/therefrom. In such an embodiment, there will be a unique slot-to-slot mapping for said time slot, which will require a minimum of decision-making once the mapping has been established. According to another embodiment, to optionally be used when a channel is defined by a set of time slot positions in each cycle of said at least one bitstream and a corresponding channel is defined by a corresponding set of time slot positions in each cycle of said internal bitstream, data from any time slot position of said set of time slot positions of said at least one bitstream is mapped to/from any time slot position of said set of time slot positions of said internal bitstream while maintaining the relative order of data among said set of time slots as received from/transmitted to said at least one bitstream. The use of this kind of channel based association of time slots of different bitstreams instead of a strict slot-to-slot association has the advantage of reducing the timing requirements between the incoming and the outgoing links/bitstreams , since it is not decided in advance which specific time slot that is to be mapped to which specific outgoing time slot. Instead the resolution is performed in connection with the output port by means of the identification of the channel. This gives the advantage that there is no need for any strict timing requirements between the bitstream at the input port and the bitstream at the output port, but the phase of one of the bitstreams may be arbitrary shifted in relation to the phase of the other bitstream. Preferably, the next available time slot is selected, the advantage here lying in the fact that there is no need to wait for a certain slot in the second bitstream, instead data is directly mapped to the first time slot available to the channel that has not yet been filled with switched data. Also, the writing of said data from time slots of said first set of time slots into time slots of said second set of time slots is preferably done in maintained mutual order. This is of course required by many applications, and when used in such a context, the switch must be able to meet this requirement. As is understood, the term internal bitstream does not necessarily mean that the internal bitstream or the corresponding bitstream carrying medium must reside physically inside a switch circuit or the like, but may be arranged peripheral to the circuit, however still being used for the transfer of data between different ports of the switch. The invention is especially advantageous in a DTM network. However, the invention is not restricted to, for example, DTM networks but can be used in any synchronous network wherein data is transferred in circuit switched channels on unidirectional, multi-channel time division multiplexed bitstreams. The present application corresponds to one three Swedish patent applications, SE 9704738-5, SE 9704739-3, and SE 9704740-1, which were filed on the same day and which refer to related inventive ideas, the descriptions thereof being incorporated by reference. The above mentioned and other features and aspects of the invention will be more fully understood from the following description of exemplifying embodiments thereof as well as from the accompanying claims. Brief Description of the Drawings Exemplifying embodiments of the invention will be described below with reference to the accompanying drawings, wherein: Fig. 1 schematically shows the structure of a time multiplexed bitstream; Fig. 2 schematically shows a switch according to an embodiment of the invention; Fig. 3 schematically shows an input port of the switch shown in Fig. 2; Fig. 4 schematically shows an output port of the switch shown in Fig . 2 ; and Figs. 5a, 5b, and 5c schematically show three further embodiments of a switch according to the invention. Detailed Description of Preferred Embodiments The structure of a unidirectional, multichannel time multiplexed bitstream of a circuit switched DTM network wherein a switch according to the invention is preferably incorporated will now be described with reference to Fig. 1. As shown in Fig. 1, the bitstream is divided into fixed rate, for example 125 μs, cycles, also referred to as frames. Each cycle is in turn divided into fixed size, for example 64 bits, time slots. The number of time slots within a frame depends on the network's bit rate. Of course, the number of time slots 1-6 shown in the cycle of the bitstream in Fig. 1 is merely illustrative. The time slots are divided into two groups, control slots C and data slots D. Control slots C are used for control signaling between nodes of the network. The data slots D are used for the transfer of payload data between said nodes . In addition to said control slots and data slots, each cycle comprises one or more synchronization slots S used to synchronize the operation of each node in relation to each cycle. Also, to make sure that the number of slots in one cycle will not overlap a following cycle, a guard band G is added after the last slot at the end of each cycle. As indicated in Fig. 2, the bitstream cycle is repeated continuously. Each node connected to the bitstream has access to at least one control slot and to a dynamic number of data slots . Each node uses its control slot to communicate with other nodes within the network, and data channels are established by a node allocating a certain amount of its data slots, forming a set of one or more time slot positions within each cycle, to the respective channel. The number of data slots allocated to each node and to each channel depends upon the transfer capacity requested for channels handled by the respective node. If a channel requires a large transfer capacity, the node will allocate more data slots for that purpose. On the other hand, if only a small transfer capacity i required within a certain channel, the node may limit the number of data slots allocated thereto. The allocation of time slots and data slots to different nodes may by dynamically adjusted as the network load changes . In Fig. 2, a switch 100 according to an embodiment of the invention is shown. The switch 100 comprises two ports 110 and 120, having at least read access to bitstreams 112 and 122 propagating on optical fibers 111 and 121, respectively. The switch also comprises two ports 130 and 140 having at least write access to output bitstreams 132 and 142 propagating on optical fibers 131 and 141, respectively. In order to switch data from any one of bitstreams 112 and 122 to one or both of bitstreams 132 and 142, ports 110 and 120 will establish circuit switched channels on an internal shared unidirectional bitstream 162 transferred on, e.g., a parallel TDM bus 161 within the switch 100. The internal bitstream 162 is accessed by all four ports and thus provides multi access. In similar to the switch external bitstreams, the internal bitstream 162 is also divided into cycles which in turn are divided into time slots. Assume for example that it is decided during channel setup that the first time slot in each cycle of bitstream 112 is to be used for transmitting information to time slot position seven in each cycle of bitstream 132 as well as to time slot position nine in each cycle of bitstream 142. A channel comprising one time slot in each cycle of the internal bitstream (assuming that the internal bitstream have the same frame rate as the external bitstreams), for example time slot number ten, will then be allocated for this purpose. Accordingly, port 110 will transfer data from the first time slot in each cycle of bitstream 112 to the tenth time slot in each cycle of the internal bitstream 162. Correspondingly, port 130 will read data from time slot position ten in each cycle of the internal bitstream 162 and transmit said data into the seventh time slot of bitstream 132. Likewise, port 140 will read data from time slot number ten in each cycle of the internal bitstream 162, and transmit said data into the ninth time slot of bitstream 142. Management of channels and allocation/ deallocation of time slot of the internal bitstream is controlled by a controller 170. The controller communicates with the ports, for providing slot mapping instructions thereto, using private communication links (as indicated by dashed lines in Fig. 2) or using control slots on the internal bitstream 162. Also, in the exemplified embodiment, the controller 170 communicates with other nodes of the network via the internal bitstream 162. (However, in an alternative embodiment, the ports themselves may be arranged to negotiate channel and time slot allocation using control slots of the bitstream 162. ) In Fig. 2, the frame or cycle rate of the internal bitstream 162 is controlled by a frame synchronization unit 190 which is arranged to synchronize the frame rate of the internal bitstream 162 to the frame rate of the network, in this case using the bitstream 112 as a reference. Also, multiples of the network frame rate may be used for the internal bitstream. As is understood, in an alternative embodiment, one of the medium access units may provide the frame synchronization feature, as described with reference to Figs. 5a, 5b, and 5c. In the embodiment of Fig. 2, with exemption for control or data slots to be used by the controller 170, the switch node will not handle control slots any differently than data slot. As far as the switch is concerned, both control slots and data slots provide data to be switched in accordance with switching instructions provided by the controller 170. An input port of the switch 100, more specifically the port 110 connected to the bitstream 112 in Fig. 2, will now be described in detail with reference to Fig. 3, the input port connected to the bitstream 122 having a similar configuration. Fig. 3 shows the part of the switch 100 connected to the optical fiber 111 that transfers bitstream 112. The port 110, which provide read access to time slots of bitstream 112, includes a medium access unit 115, a bit clock (not shown), a slot counter 116 and a frame clock (not shown) . The bit clock is synchronized to the bit-rate of bitstream 112 and is used as input to the slot counter 116. The slot counter 116 counts the time slot positions transferred by the fiber 111 and is cyclically restarted by the frame clock at the start of each new cycle. At channel set-up, the controller 170 stores information in a slot mapping table 117. Each time slot position in a cycle of bitstream 112 has a corresponding entry in said table 117, and each entry that represents a time slot carrying data to be switched by the switch is provided with information for identifying the time slot position on said internal bitstream 162 to which the time slot data is to be transferred. The count of the slot counter 116 is used to address an entry in the slot mapping table 117. When, for example, the access unit 115 reads time slot position 3 from each cycle of bitstream 112, the slot counter 116 will address the third entry of the slot mapping table 117. At this entry, position information, in this case designating position number 10, has been stored by means of the controller 170 during channel setup. Upon addressing this third entry, osition number ten will be outputted and used to control that the data read from time slot three of bitstream 112 is written into time slot ten of the internal bitstream 162. Upon addressing the next entry, i.e. corresponding to time slot number four on the bitstream 112, no time slot is specified in the slot mapping table 117 and, hence, data from time slot number four of bitstream 112 will not be transmitted to the internal bitstream 162. The output port 130 of the switch 100 will now be described in detail with reference to Fig. 4, the port connected to the bitstream 142 having a similar configuration. At channel set-up, the controller 170 stores information in a slot mapping table 137. Each time slot position in a cycle of the internal bitstream 162 has a corresponding entry in said table 137, and each entry that represents a time slot position carrying data to be switched to bitstream 132 is provided with information in the table 137 for identifying the time slot position on said bitstream 132 to which the respective data is to be transferred. The count of a first slot counter 136, keeping track or the time slot positions passing on the internal bitstream 162, is used to address an entry in the slot mapping table 137. When, for example, time slot position 10 is read from each cycle of the internal bitstream 162, the first slot counter 136 will address the tenth entry of the slot mapping table 137. At this entry, position information, in this case position number 22, has been stored by means of the controller 170 during channel set-up. Upon addressing the tenth entry, position number twenty-two will be outputted and used to control that data read from time slot position ten of the internal bitstream 162 is written for output into time slot position twenty-two of an output frame buffer 138. Upon addressing, for example, the fourteenth entry, i.e. corresponding to time slot fourteen of bitstream 162, no time slot position is specified in the slot mapping table 137 and, hence, data from time slot position fourteen of the internal bitstream 162 will not be written into the frame buffer 138. The port 130 further includes a medium access unit 135, a bit clock (not shown), a second slot counter (not shown) and a frame clock (not shown) . The bit clock is synchronized to the bit-rate of bitstream 132 and is used as input to the second slot counter. The second slot counter counts the number of slots transferred by the fiber 131 and is cyclically restarted by the frame clock at the start of each new cycle. The count of the second slot counter is used to address entries in the frame buffer 138. Data stored in said frame buffer at a specific entry is transferred to the access unit 135, which then writes the data into a time slot having a position in a cycle of the bitstream 132 corresponding to the entry of the frame buffer 138. Further aspects of the invention will now be exemplified with reference to switch embodiments shown in Figs. 5a, 5b, and 5c,. In Fig. 5a, time slots of an internal bitstream of a switch 10, according to an embodiment of the invention, are allocated to different ports over different segments of the bitstream carrying medium. For example, as schematically indicated by the dashed line in Fig. 5a, a time slot of the internal shared bitstream, lets say time slot number four in each cycle thereof, is allocated for transfer of time slot data from port 11 to optional one or more of ports 15, 16, and 17 on one segment (to the left of the dashed line) , but is allocated for transfer of time slot data from port 18 to optional one or more of ports 12, 13, and 14 on another segment (to the right of the dashed line) of the bitstream carrying medium, thus providing better utilization of the bitstream bandwidth. In Fig. 5b, a switch 20 is, according to an embodiment of the invention provided, with two internal shared bitstreams are provided in the switch 20. All eight ports 21-28 of the switch 20 have access to both bitstreams and the bitstreams are propagating in opposite directions, as indicated by the arrows in Fig. 5b. Consequently, when transferring data from one port, for example port 27, to another port, for example port 25, of the switch 20, time slots may for example be allocated on the bitstream that has the shortest propagation distance between the two ports, thereby providing both quicker switching and efficient segmented allocation of a time slot. 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Claims: CLAIMS 1. A method for switching data transferred in circuit switched channels between at least three unidirectional multi-channel time division multiplexed bitstreams that are accessed at respective ports of a switch, said method comprising the steps of: transferring said data between said ports in circuit switched channels of a switch internal unidirectional multi-channel time division multiplexed bitstream that is accessed by said ports. 2. A method as claimed in claim 1, wherein each one of said at least three bitstreams as well as said switch internal bitstream is divided into cycles, which in turn are divided into time slots. 3. A method as claimed in claim 1 or 2 , comprising dynamically adjusting the allocation of channels on said switch internal bitstream based upon changes in allocation of channels on said two or more bitstreams. 4. A method as claimed in claim 1, 2, or 3 , comprising the step of switching data from a channel on a first bitstream of said at least three bitstreams to a channel on a second bitstream of said at least three bitstreams as well as a channel on a third bitstream of said at least three bitstreams using a channel on said switch internal bitstream. 5. A method as claimed in any one of the preceding claims, comprising the step of synchronizing the frame rate of said internal bitstream to the frame rate of one or more of said at least three bitstreams. 6. A method as claimed in any one of the preceding claims, wherein said data is transferred between said ports in circuit switched channels of two or more switch internal unidirectional multi-channel time division multiplexed bitstream that are accessed by said ports . 7. A method as claimed in claim 6, comprising the step of transferring data received as a time slot of serial data on a bitstream of said at least three bitstreams as a time slot of at least partly parallel data using said two or more switch internal bitstream. 8. An apparatus for switching data transferred in circuit switched channels between at least three unidirectional multi-channel time division multiplexed bitstreams that are accessed at respective ports of said apparatus, comprising: a shared medium for transferring said data between said ports in circuit switched channels of an internal unidirectional multi-channel time division multiplexed bitstream that is carried on said medium and that is accessed by said ports. 9. An apparatus as claimed in claim 8, wherein each one of said at least three bitstreams as well as said switch internal bitstream is divided into cycles, which in turn are divided into time slots. 10. An apparatus as claimed in claim 8 or 9 , comprising control means for controlling allocation of channels on said internal bitstream. 11. An apparatus as claimed in claim 10, wherein said control means are arranged to dynamically adjust the allocation of channels on said switch internal bitstream based upon changes in the allocation of channels on said at least three bitstreams. 12. An apparatus as claimed in any one of claims 8- 11, wherein a channel on said internal bitstream is used for switching data from a channel on a first bitstream of said at least three bitstreams to a channel on a second bitstream of said at least three bitstreams as well as a channel on a third bitstream of said at least three bitstreams . 13. An apparatus as claimed in any one of claims 8- 12, comprising means for synchronizing the frame rate of said internal bitstream to the frame rate of one or more of said at least three bitstreams. 14. An apparatus as claimed in any one of claims 8- 13, comprising mapping means for controlling, for each time slot position of a cycle of at least one bitstream of said at least three bitstreams, whether or not data transferred therein is to be written into said internal bitstream, and, if so, which time slot position of the internal bitstream that said data is to be written into. 15. An apparatus as claimed in claim 14, wherein said mapping means are arranged to unambiguously associate a specific time slot position in each cycle of said at least one bitstream, containing data to be transferred to said internal bitstream, with a respective time slot position in each cycle of said shared bitstream, said data hence being transferred thereto. 16. An apparatus as claimed in claim 14, wherein a channel is defined by a set of time slot positions in each cycle of said at least one bitstream and a corresponding channel is defined by a corresponding set of time slot positions in each cycle of said internal bit- stream, and wherein said mapping means are arranged to map data from any time slot position of said set of time slot positions of said at least one bitstream to any time slot position of said set of time slot positions of said internal bitstream while maintaining the relative order of data among said set of time slots as received from said at least one bitstream. 17. An apparatus as claimed in any one of claims 8- 16, comprising mapping means provided in relation to at least one bitstream of said at least three bitstreams for controlling, for each time slot of a cycle of said inter- nal bitstream, whether or not data transferred therein is to be written into said at least one bitstream and, if so, which time slot position of said at least one bitstream that said data is to be written into. 18. An apparatus as claimed in claim 17, wherein said mapping means are arranged to unambiguously associate a specific time slot position in each cycle of said internal bitstream, containing data to be transferred to said at least one bitstream, with a respective time slot position in each cycle of said at least one bitstream, said data hence being transferred thereto. 19. An apparatus as claimed in claim 17 , wherein a channel is defined by a set of time slot positions in each cycle of said internal bitstream and a corresponding channel is defined by a corresponding set of time slot positions in each cycle of said at least one bitstream, and wherein said mapping means are arranged to map data from any time slot position of said set of time slot positions of said internal bitstream to any time slot position of said set of time slot positions of said at least one bitstream while maintaining the relative order of data among said set of time slots as received from said internal bitstream. 20. An apparatus as claimed in any one of claims 8- 19, wherein said shared medium provides for transferring of data between said ports in circuit switched channels of two or more internal unidirectional multi-channel time division multiplexed bitstream that are carried on said medium and that are accessed by said ports. 21. An apparatus as claimed in claim 20, wherein data received as a time slot of serial data on a bitstream of said two or more bitstreams is transferred as a time slot of at least partly parallel data using said two or more switch internal bitstream. 22. An apparatus as claimed in any one of claims 1- 21, wherein said channels are multi-rate channels. 23. A switch for switching data between at least three multi-channel unidirectional bitstreams of a circuit switched time division multiplexing network, wherein: each one of said bitstreams is divided into cycles and each one of said cycles is divided into time slots; circuit switched channels between nodes of the network is established, modified and terminated by dynamic allocation of time slots on said bitstreams; time slot data from said bitstreams is transferred between input and output ports of said switch using an internal unidirectional multi-channel time division multiplexed bitstream, which is divided into cycles which in turn are divided into time slots; circuit switched channels between two or more ports of the switch node is established, modified and terminated by dynamic allocation of time slots on said internal bitstream.

Inventors: BOHM CHRISTER, DANIELSSON MAGNUS, GAUFFIN LARS, LINDGREN PER, BOHM, CHRISTER, DANIELSSON, MAGNUS, GAUFFIN, LARS, LINDGREN, PER
Applicants: BOHM CHRISTER, DANIELSSON MAGNUS, GAUFFIN LARS, LINDGREN PER, NET INSIGHT AB, BOHM, CHRISTER, DANIELSSON, MAGNUS, GAUFFIN, LARS, LINDGREN, PER
Application year: 1998
Main classification: H04L12
IPC codes: H04Q11