SELF-TEST FOR INTEGRATED MEMORIES

Abstract: The invention relates to an integrated circuit comprising a read/write memory and a test circuit for testing said memory. The test circuit includes a test controller for successively writing, on series of memory locations, a test data word and reading out a response data word, said test data word in a first phase corresponding to a data background and in a second phase to an inverse of said data background. The test circuit further includes test logic for bit-wise checking whether the contents of the response data word is correct. The invention is characterized in that the test logic intrinsically comprises patterns of the data background and of the inverse of the data background, and said test logic is embodied so as to simultaneously use both patterns to check the response data word.

Description: Self-test for integrated memories. The invention relates to an integrated circuit comprising: (1) a read/write memory having a plurality of memory locations for N-bit wide data words which are each accessible by means of unique memory addresses; (2) a test circuit for testing said memory, which test circuit includes a test controller for successively writing, on series of memory locations, a test data word and reading out a response data word, said test data word in a first phase corresponding to a data background and, in a second phase, to an inverse of said data background, and test logic for bit-wise checking whether the contents of the response data word is correct. The invention further relates to a method of testing a read/write memory for N-bit wide data words by means of a test circuit which is fixedly coupled to the memory, which method comprises the following steps: (1) writing an N-bit wide data background on a memory location; (2) reading out a response data word at said memory location; (3) bit-wise checking whether the contents of the response data word is correct; (4) repeating steps (1) through (3) for an inverse of the data background. Such an integrated circuit (IC) and such a method are disclosed in United States patent specification US 5,568,437. The IC described therein comprises a memory which can be subjected to a test in accordance with the Built-in Self-Test (BIST) principle. This means that a test circuit is integrated on the IC which can independently test the memory. In the associated testing method, the test circuit writes a series of test data words (consisting of one or more so-called data backgrounds and the inverses thereof) in the memory, whereafter response data words are read out and compared with the written test data words. Correspondence between the response data words and the test data words confirms the proper functioning of the memory. The data backgrounds must be such that a large number of frequently occurring defects are detected. To this end, the known IC comprises a test circuit of unlimited flexibility as regards the data backgrounds to be used. However, a problem with such an approach is that the test logic takes up a relatively large surface area. It is an object of the invention to provide, inter alia, an IC of the type mentioned in the opening paragraph, in which the test logic potentially takes up a smaller part of the surface area of the IC. To achieve this, an IC in accordance with the invention is characterized in that the test logic intrinsically comprises patterns of the data background and of the inverse of the data background, and in that the test logic is embodied so as to simultaneously employ both patterns to check the response data word. This means that a test circuit in accordance with the invention is optimized for one data background and the inverse thereof. It has been found that one suitably selected data background (and the inverse thereof) is sufficient to detect the most frequent defects. As a result, supplying the written test data word to the test logic can be omitted. This has two consequences as regards the size of the test logic in terms of IC-surface. In the first place, the relatively large XOR gates, as used in the known IC for bit-wise comparing the response data word to the written test data word, are superfluous and they are replaced by more efficient logic in which the patterns of the data background and the inverse of the data background are integrated. In the second place, the data bus between the test controller and the test logic, as used in the known IC to pass on the expected response data word to the test logic, is superfluous. As a result, a substantial reduction of the necessary surface area is achieved without a substantial reduction of the error-covering ratio. A method in accordance with the invention is characterized in that step (3) includes: carrying out a logical function on the response data word, said function being predetermined by patterns of the data background and of the inverse of said data background, and both patterns being used simultaneously. Consequently, unlike the method described in said United States patent specification, there is no bit- wise comparison between the response data word and the written test data word. In a method in accordance with the invention, the data background and the inverse thereof are incorporated in the logical function which is carried out on the response data word. An embodiment of the IC in accordance with the invention is characterized in that the test logic is provided with a bus comprising N data lines for receiving the response data word, a first and a second circuit being connected in parallel to the bus to check whether the contents of the response data word match the data background and the inverse of the data background, respectively. The first circuit comprises an OR gate and the second circuit comprises an AND gate, each gate being provided with at least N inputs. Each data line which conveys a first value if the response data word corresponds to the data background, is coupled via an inverter to a corresponding input of the OR gate and to a corresponding input of the AND gate, while each of the other data lines is directly coupled to a corresponding input of the OR gate and to a corresponding input of the AND gate. As regards the IC-surface, these gates can be implemented much more advantageously than the test logic of the known IC. In this respect, it is noted that it may be advantageous to compose the AND and OR gates of a number of gates and/or different logic, for example by means of NAND and NOR gates. With respect to the invention, however, only two important conditions are to be met, namely that the first circuit as such should be capable of carrying out an AND function, and that the second circuit as such should be capable of carrying out an OR function, the results being passed on inverted or unin verted. A more advanced variant of the last-mentioned embodiment is characterized in that the AND gate and the OR gate both comprise an input connected to the test controller, for receiving a signal originating from the test controller, which signal respectively has a second value or the first value if, as anticipated, the response data word corresponds, respectively, to the data background or the inverse of the data background. This has the advantage that if a response data word corresponds to the inverse of what was expected, this can be distinguished from the case in which the response data word corresponds to what is expected. This enables a higher error covering ratio to be achieved. An embodiment of the IC in accordance with the invention is characterized in that adjoining bits of the data background have complementary values. This data background has the advantage that, in addition to the so-called stuck-at faults, also specific coupling faults within a memory location and between adjoining memory locations are activated. A more advanced variant of the preceding embodiment is characterized in that the test controller comprises a shift register for storing the data background. This has the advantage that, for this special data background, the inverse of the test data word can be efficiently obtained, in terms of IC-surface and in terms of time, from the test data word, and conversely, by shifting the data word stored in the shift register by one bit. Further attractive embodiments of the IC and of the method in accordance with the invention are described in the dependent claims. For a description of relevant technique, reference is further made to united States patent specification US 5,325,367 (PHN 12.624). These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. In the drawings: Fig. 1 schematically shows the IC in accordance with the prior art, Fig. 2 schematically shows the relevant part of a first embodiment of an IC in accordance with the invention, Fig. 3 schematically shows the relevant part of a second embodiment of an IC in accordance with the invention. Fig. 1 schematically shows the IC in accordance with the prior art. The IC 100 comprises a read/write memory 102 and a test circuit 104 for testing the memory. The memory 102 is connected to possible other components of the IC via a connection 112 which is responsible for the communication necessary for the operation of the IC as a whole. For the purpose of testing, the memory 102 and the test circuit 104 are connected to one another via a connection 114. To put the test circuit 104 into operation, to read the test results and for other external communication, the test circuit 104 comprises a connection 116. This communication may be implemented in various ways, for example on the basis of scan-chains, TAP (test access port) or otherwise. The invention relates to the test circuit 104. Fig. 2 schematically shows the relevant part of a first embodiment of an IC in accordance with the invention. The elements of the IC which are not relevant to the invention have been omitted. In this embodiment, as well as in subsequent embodiments, the above-mentioned terms, i.e. first and second value, correspond, respectively, to logical 0 and logical 1. A read/ write memory 202 is embodied so as to store 4-bit wide data words. To this end, the memory 202 comprises a number of memory locations (typically several hundred to many millions) which are all accessible by means of respective unique addresses. To detect defects in the memory 202, a BIST test circuit is integrated on the IC. This test circuit comprises a test controller 204 and test logic 206. The test controller 204 is capable of generating addresses (a), data (d) and a write-enable (WE) signal for writing test data words on series of memory locations. These test data words correspond to 1010 (data background) and 0101 (inverted data background). Said test controller 204 is also capable of generating addresses and a read-enable (RE) signal for reading response data words on series of memory locations. These response data words become available at an output of the memory 202. In Fig. 2, this is indicated by q(0)-q(3), which represent the 4 independent bits of a response data word. Said output is connected to the test logic 206 via a first bus 224 for passing on response data words. The data lines of a second bus 222 of the test logic 206 are connected to corresponding data lines of the first bus 224. An inverter 232 is provided for every second data line. The test logic 206 is embodied so as to check whether the contents of the response data word is correct. In this embodiment, this is achieved by means of an OR gate 242, an AND gate 244 and a XOR gate 246. To pass on a result of this check, the test logic 206 is connected to the test controller 204. In other embodiments, the inverters may be incorporated in the OR gate 242 and the AND gate 244 by alternately using PMOS transistors and NMOS transistors. Other optimizations are also possible. In general, it can be said that Fig. 2 gives a functional description of the test logic 206 in this embodiment. Possibly, the individual components of the test logic 206 are no longer recognizable in the eventual realization on the IC. These components themselves are not relevant to the invention. The only essential feature is that the patterns of the data background and the inverse of the data background are already incorporated in the test logic 206 in accordance with the invention, so that they do not have to be presented separately to the test logic 206. The operation of this embodiment during a test mode is explained by means of a number of steps: (1) the test controller 204 presents an address, the data background and a WE signal to the memory 202, the timing requirements imposed by said memory being met, and hence writes a test data word in the memory; (2) the test controller 204 presents an address and an RE signal to the memory 202, the timing requirements imposed by said memory being met, and hence reads a response data word from the memory; (3) the test logic 206 checks bit- wise whether the contents of the response data word is correct. Subsequently, said steps are repeated for the inverse of the data background. These steps may be embedded in an extensive test algorithm, which is referred to in the literature as march test. Various march tests are known from the literature. However, only step (3) is relevant to the invention. In connection with the embodiment shown in Fig. 2, the step characteristic of the invention, i.e. in which it is checked bit-wise whether the contents of the response data word is correct, can be explained as follows. If the data lines of the bus 222 only convey a 0, this is detected ( e. a deviant output signal is generated) by the OR gate 242. If the data lines of the bus 222 only convey a 1, this is detected (i.e. a deviant output signal is generated) by the AND gate 244. In other embodiments, the same result can alternatively be achieved by replacing one or both gates by NOR and/or NAND gates. In this embodiment, there is a discrepancy between, on the one hand, the response data word and, on the other hand, the data-background or the inverse thereof if exactly one of both gates conveys a 1 as the output signal. This situation is detected by the XOR gate 246, so that in the case of an error, the output of the XOR gate 246 conveys a 1. After the detection of a deviant response data word, the test controller can store the corresponding address to make it available for diagnosis after the completion of the test. In another, less elaborate method, the test is interrupted as soon as a deviant response data word is detected, and only an error signal is made available. The above-mentioned United States patent specification deals, in particular, with these aspects. Fig. 3 schematically shows the relevant part of a second embodiment of an IC in accordance with the invention. A property of the test circuit shown in Fig. 2 is that response data words corresponding to the data background or to the inverse of the data background are always approved. In theory, however, it is possible that the response data word corresponds to the data background while its inverse was expected, or conversely. To detect these cases, the test circuit of the second embodiment comprises an additional connection 310 between the test controller 304 and the test logic 306 for stating which one of these two possible data words is expected. This signal has the value 1 if the response data word is expected to correspond to the data background, and the value 0 if the response data word is expected to correspond to the inverse of the data background. In this test circuit, both the OR gate 342 and the AND gate 344 have an additional input to which this signal is applied. As a result of this additional input, there are only ones and zeros, respectively, at the inputs of the OR gate 342 and the AND gate 344 if, as expected, the response data word corresponds, respectively, to the data background and the inverse of the data background. An advantage of the use of one data background and the inverse thereof is that also the test controller can be optimized for this purpose. In this connection, for the special data background 0101 use can be made of the property that this data background and the inverse thereof can be derived from each other by shifting by one bit. A shift register 320 utilizes this property of the data background. The use of this principle leads to a further simplification of the test circuit and hence to a further reduction of the IC-surface, as test circuits suited for a number of data backgrounds must use relatively complex logic to derive and present these data backgrounds and the inverses thereof. If the IC comprises a number of memories, the test circuit can be readily adapted so that it is capable of testing more than one memory. In practice this boils down to rendering the memories to be tested selectable for the test circuit and adapting the test circuit so that it can deal with possible differences in the address ranges of the memories.

Claims: CLAIMS: 1. An integrated circuit comprising: (1) a read/ write memory having a plurality of memory locations for N-bit wide data words which are each accessible by means of unique memory addresses; (2) a test circuit for testing said memory, which test circuit includes a test controller for successively writing, on series of memory locations, a test data word and reading out a response data word, said test data word in a first phase corresponding to a data background and, in a second phase, to an inverse of said data background, and test logic for bit-wise checking whether the contents of the response data word is correct, characterized in that the test logic intrinsically comprises patterns of the data background and of the inverse of the data background, and in that the test logic is embodied so as to simultaneously employ both patterns to check the response data word. 2. An integrated circuit as claimed in claim 1, wherein the test logic is provided with a bus comprising N data lines for receiving the response data word, characterized in that a first and a second circuit are connected in parallel to the bus to check whether the contents of the response data word is correct, said contents being the data background and the inverse of the data background. 3. An integrated circuit as claimed in claim 2, characterized in that the first circuit comprises an OR gate and the second circuit comprises an AND gate, which gates are each provided with at least N inputs, and each data line, which conveys a first value if the response data word corresponds to the data background, is coupled via an inverter to a corresponding input of the OR gate and to a corresponding input of the AND gate, and each of the other data lines is directly coupled to a corresponding input of the OR gate and to a corresponding input of the AND gate. 4. An integrated circuit as claimed in claim 3, characterized in that outputs of the OR gate and of the AND gate are connected to inputs of a XOR gate. 5. An integrated circuit as claimed in claim 3, characterized in that the AND gate and the OR gate both comprise an input connected to the test controller for receiving a signal originating from the test controller, which signal has a second value, or the first value if, as anticipated, the response data word corresponds to the data background or the inverse of the data background. 6. An integrated circuit as claimed in claim 1, characterized in that adjoining bits of the data background have complementary values. 7. An integrated circuit as claimed in claim 6, characterized in that the test controller comprises a shift register for storing the data background. 8. A method of testing a read/ write memory for N-bit wide data words by means of a test circuit which is fixedly coupled to the memory, which method comprises the following steps: (1) writing an N-bit wide data background at a memory location; (2) reading out a response data word at said memory location; (3) bit- wise checking whether the contents of the response data word is correct; (4) repeating the steps (1) through (3) for an inverse of the data background; characterized in that step (3) includes: carrying out a logical function on the response data word, said function being predetermined by patterns of the data background and of the inverse of said data background, and both patterns being used simultaneously. 9. A method as claimed in claim 8, characterized in that adjoining bits of the data background have complementary values. 10. A method as claimed in claim 9, characterized in that, in step (4), the inverse of the data background is obtained from the data background by shifting the latter by one bit.

Inventors: LOUSBERG GUILLAUME ELISABETH A, VERSTRAELEN MARTINUS JOHANNES, LOUSBERG, GUILLAUME, ELISABETH, ANDREAS, VERSTRAELEN, MARTINUS, JOHANNES, WILHELMINA
Applicants: KONINKL PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 1998
Main classification: G11C29
IPC codes: G11C29