DIGITAL CORRELATED DOUBLE SAMPLE CAMERA

Abstract: A digital electronic camera, method and circuit for converting an analog image-bearing signal from an electronic imaging device. The image-bearing signal provides both a pixel-reference signal and a pixel-image signal for each one of a plurality of pixels of the imaging device. The circuit includes a voltage clamp that adjusts a level of the image-bearing signal based on a black reference level to produce a clamped image-bearing signal. An analog-to-digital converter (ADC) is coupled to digitize the clamped image-bearing signal and operated to produce a first digital value representative of the pixel-reference signal for a pixel, and operated to produce a second digital value representative of the pixel-image signal. Then, a first digital subtractor generates a first digital difference signal based on the first and second digital values to reduce pixel-to-pixel noise and/or drift. The circuit optionally includes a feedback circuit that adjusts the black-reference level based on a comparison between the digital reference value and a digital black-reference value selected to be near or at one end of a range of values accommodated by the ADC. The circuit further optionally includes a clock-adjustment circuit that adjusts an image-voltage-signal sampling clock and/or a reference-voltage-signal sampling clock to sample the respective signal at substantially an end of a valid sampling interval. The circuit further optionally includes an accumulator/averager which is operated to accumulate and average one or more digital values of non-imaging pixels to produce a third digital value, and a second digital subtractor is operated to generate a second digital difference signal based on the first on the first digital difference signal and the third digital value, to reduce row-to-row noise and/or drift. A dovetail camera mounting system is also disclosed.

Description: DIGITAL CORRELATED DOUBLE SAMPLE CAMERA Field of the Invention This invention relates to the field of electronic cameras, and in particular to analog and digital electronic circuitry to improve cameras using charge- coupled devices (CCDs) in digital-output machine-vision applications. Background ofthe Invention In a machine-vision camera, an electronic image sensor captures the picture. This image sensor often includes a charge-coupled device (CCD) that includes an array of pixels and electronic circuitry used to serially transfer the signals from the pixel array to external circuitry. The array of pixels is typically organized in rows and columns of pixels. All the rows and columns of one image are collectively called one frame. Typically, after the array is exposed to light, each row is shifted vertically into a horizontal shift register from which the image signal is serially shifted out, one pixel at a time. This vertical shifting of rows into the horizontal shift register, and horizontal shifting of pixels from the horizontal shift register is repeated until all pixels of one frame are serially output. The shifting operations are typically performed on the electron charges using charge-transfer operations. Each pixel stores an electron charge that is proportional to the amount of light that has fallen on the pixel during a period in which an aperture, usually located near a lens in a lens housing, is open. Many CCD image sensors have certain pixel positions made as non-imaging pixels to be used as a dark reference level. The CCD circuitry moves the pixel charges from the array, converts the charges to voltage levels, and serially outputs analog voltage levels representing the image of each pixel. However, the shifting operations, as well as other factors, add electronic signal noise to the pixel signal. Many CCD image sensors also have circuitry, or certain pixel positions made as non-imaging pixels (often having opaque coverings), to be used to provide a dark reference level. Analog correlated-double-sampling ("CDS") techniques are sometimes used to reduce the amount of noise in an analog video signal from a CCD device. For example, some circuits use analog sample-and-hold circuits to capture both the dark-reference voltage for a pixel, and the image voltage for that pixel, and then use a differential amplifier to generate an output signal representing the difference between the two voltages. If a source of noise affected both voltages equally, the difference function should remove that noise. In one embodiment, three sample-and-hold (S/H) circuits are used: one S/H is clocked at a reference time to capture the dark-reference voltage, a second S/H is clocked at an image time to capture the image voltage, and a third S/H is clocked at the image time to capture the output ofthe first S/H (i.e., the dark-reference voltage). The outputs ofthe second and third S/H circuits are fed to the differential amplifier and analog-subtracted. A series of analog difference values typical of pixel image information with reduced electrical noise is thus obtained. U.S. Patent Number 5,086,344 describes a digital implementation of a correlated-double-sampling technique to produce an image signal with reduced electrical noise. That implementation uses three digital registers and a single clock source (i.e., a plurality of clock edges as needed are all referenced from a single source clock, wherein the clock edges may be delayed and/or divided from that clock source) to sample a reference level and an image level from the CCD image sensor. The analog voltage signal from the CCD image sensor is converted into a series of digital values by an Analog-to-Digital Converter (ADC). The digitized signal is shifted and stored in three digital registers, in a manner similar to the three S/H circuits described above. Two ofthe digital registers are digitally subtracted. A series of digital difference values typical of pixel image information with reduced electrical noise is thus obtained. Summary of the Invention It is an object ofthe present invention to provide an improved digital circuit that provides correlated double sampling of a charge-coupled device (CCD) image sensor used in a machine-vision camera. In one embodiment, this circuit uses two digital registers and a clock generator to perform the correlated double sampling on a digitized signal. A feedback loop from the digitized signal adjusts a varying DC component of an analog signal from the CCD image sensor, so that the signal into an analog-to-digital converter (ADC) stays within the defined range ofthe ADC, and the dynamic range ofthe ADC is optimized. In one embodiment, the analog voltage signal from the CCD image sensor is provided by output circuitry in the CCD image sensor that converts image-bearing charges from the photosensitive pixels in the CCD image sensor into a serial analog voltage signal that time multiplexes both reference signals and image signals. This analog voltage signal is serially clocked from the CCD image sensor one pixel at a time. Each pixel time period includes two intervals: a first interval, corresponding to a "dark" or reference voltage, and a second interval corresponding to the image voltage for the image-bearing signal. A feedback loop compares the digitized value of each pixel's dark-reference voltage to a predefined pixel value. If the value ofthe dark-reference voltage of a pixel is above or below the predefined pixel value, the feedback loop adjusts the DC component ofthe analog voltage signal for the next pixel time frame. This adjustment helps to keep the digitized value ofthe image-bearing signal within the range ofthe ADC. In one embodiment, a circuit is provided for converting an analog image-bearing signal from an electronic imaging device. The image-bearing signal provides both an pixel-reference signal and a pixel-image signal for each one of a plurality of pixels ofthe imaging device. The circuit includes a voltage clamp that adjusts a level ofthe image-bearing signal based on a black reference level to produce a clamped image-bearing signal. An analog-to-digital converter (ADC) is coupled to digitize the clamped image-bearing signal and operated to produce a first digital value representative ofthe pixel-reference signal for a pixel, and operated to produce a second digital value representative ofthe pixel- image signal. Then, a first digital subtractor having an input coupled to receive the first and second digital values, generates a first digital difference signal based on the first and second digital values. This first digital-difference signal is the image signal adjusted to reduce the pixel-to-pixel noise or drift. In one such embodiment, the above circuit further includes a feedback circuit that adjusts the black-reference level based on a comparison between the digital reference value and a digital black-reference value, the digital black- reference value selected to be near or at one end of a range of values accommodated by the ADC. In another such embodiment, the above circuit further includes a clock- adjustment circuit that adjusts an image-voltage-signal sampling clock to sample the image-voltage signal at substantially an end of a valid image-sampling interval, a clock-adjustment circuit that adjusts a reference-voltage-signal sampling clock to sample the reference-voltage signal at substantially an end of a valid reference-sampling interval, or both. In another such embodiment, the above circuit further includes a first digital register having an input connected to the ADC to receive and temporarily store the first digital value, and a second digital register having an input connected to the ADC to receive and temporarily store the second digital value, wherein the first digital subtractor has an input connected to the first register and second registers. In another such embodiment, the above circuit further includes an accumulator/averager coupled to an output ofthe first digital subtractor and operated to accumulate and average one or more digital values representative of non-imaging pixels to produce a third digital value representative ofthe accumulated and averages digital values, and a second digital subtractor having an input coupled to receive the first digital difference signal and the third digital value, the second digital subtractor generating a second digital difference signal based on the first digital difference signal and the third digital value. In yet another such embodiment, an entire digital electronic camera system including some or all ofthe above features is described. In one such embodiment, the output circuit ofthe camera provides a serial digital signal representative of an image captured by the digital electronic camera. Another aspect ofthe present invention is a camera mounting system including a camera body having one or more dovetail slots, and a dovetail mounting block operable to maintain a predetermined mounting force to a corresponding one ofthe dovetail slots on the camera body. In one such embodiment, the camera body includes two non-coplanar surfaces, and wherein each one of said two surfaces includes a dovetail slot. In another such embodiment, two non-coplanar surfaces are at substantially 90 degrees to one another. In another such embodiment, the camera body includes an aluminum extrusion anodized with an electrically insulating layer. In another such embodiment, the camera body includes an aluminum extrusion having one or more cooling vanes. Another aspect ofthe present invention is a method for adjusting timing for converting an analog image-bearing signal from an electronic imaging device, wherein the image-bearing signal providing a pixel-reference signal and a pixel-image signal for each one of a plurality of pixels ofthe imaging device. The method includes the steps of: (a) measuring either the pixel-reference signal or the pixel-image signal for a pixel using a timing pulse; (b) changing a delay ofthe timing pulse; (c) measuring either the pixel-reference signal or the pixel-image signal for a subsequent pixel using the timing pulse; (d) based on a change amount ofthe measured signal, conditionally branching back to step (b); (e) backing off the change to the delay ofthe timing pulse; (f) saving the delay ofthe timing pulse; and (g) operating the electronic imaging device using the saved delay to control the timing pulse. In one such embodiment, the method steps (a) through (d) are performed on a plurality of imaging pixels within a row of pixels ofthe imaging device. In another such embodiment, the method steps (a) through (d) are performed on a plurality of non-imaging pixels ofthe imaging device. Brief Description of the Drawings FIG. 1 shows a block diagram of a machine- vision video camera 100 of one embodiment ofthe present invention. FIG. 2 A shows a detailed block diagram ofthe electronics of machine- vision camera 100 of one embodiment ofthe present invention. FIG. 2B shows a detailed block diagram of clock generator circuit 180 of one embodiment. FIG. 2C shows a detailed block diagram ofthe electronics of machine- vision camera 100 of another embodiment ofthe present invention. FIG. 3 A shows one embodiment of analog-signal-conditioning circuit 130 and feedback circuit 170. FIG. 3B shows details of another embodiment of analog-signal- conditioning circuit 130. FIG. 3C shows details of yet another embodiment of analog-signal- conditioning circuit 130. FIG. 3D shows details of one embodiment of adder/subtractor 238. FIG. 3E shows a stylized voltage-versus-time graph representation of signal 119. FIG. 4A is a stylized timing diagram showing the relationship of clocks 203, 204, 202, clock-enable 209, and V out 119 (as represented by idealized signals 410 and 420). FIG. 4B is a stylized timing diagram showing the relationship of sampling clock 205 and signal V out 119 (as represented by idealized signal 440). FIG. 4C is a flow chart showing one method for adjusting sampling clock 205 relative to signal V out 119. FIG. 5 A is an isometric view of one embodiment of a mechanical housing 500 for machine- vision camera 100. FIGs. 5B, 5C, 5D, 5E, 5F, and 5G are views of other embodiments of dovetail slots 512 and mechanical housings 500 for machine- vision camera 100. FIG. 6 is a back view of one embodiment of a machine- vision camera. FIG. 7 is a drawing of one embodiment ofthe mounting scheme for the electronics' printed circuit boards inside of a machine- vision camera. FIG. 8 A is a drawing ofthe mounting mechanism of one embodiment of a machine- vision camera. FIGs. 8B, 8C, 8D, 8E are drawings ofthe mounting mechanism of another embodiment of a machine- vision camera. FIGs. 8F, 8G, 8H1, 8H2, 8HA, 8HB, 811, 812, and 813 are drawings of the mounting mechanism of yet another embodiment of a machine-vision camera. FIGs. 8J1, 8J2, 8J3, 8J4, 8KA, 8KB, 8K1, 8K2, and 8K3 are drawings of the mounting mechanism of still another embodiment of a machine-vision camera. FIG. 9 is a drawing of a system 900 that uses machine- vision camera 100 in an automated manufacturing situation. FIG. 10 shows a multiple-dovetail unit 8100, dovetail-slot guiderail 890, and a dovetail slot 512 formed onto strobe 940. Description of Preferred Embodiments In the following detailed description ofthe preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope ofthe present invention. Figure 1 shows a block diagram ofthe major functional components of machine-vision camera 100 of one embodiment ofthe present invention. These functional components include, in one embodiment, dedicated circuits, such as Application Specific Integrated Circuits (ASICs), one or more microprocessors and support hardware for microprocessors, such as Random Access Memory (RAM) or Read Only Memory (ROM), or a combination of dedicated circuits and microprocessors. One objective ofthe present invention is to reduce the amount of analog circuitry and to replace analog functions and signals with digital functions and signals. In the embodiment shown, an image to be sensed and digitized by machine-vision camera 100 is captured by a conventional lens 101 & aperture 103 (both mounted within housing 102) and focused onto CCD sensor 110. CCD sensor 110 converts varying light levels ofthe image into varying electric charges in each of a plurality of pixel locations, often arranged as an array of rows and columns. Circuitry inside CCD sensor 110 converts the electric charges ofthe pixel locations into a series of analog voltage levels which are fed into analog-signal-conditioning (ASC) circuit 120. The process of converting pixel charges often involves shifting every row of charges to an adjacent row (a "vertical shift") wherein the last row is shifted into a "horizontal shift register." The contents ofthe horizontal shift register (i.e., one row of pixel charges) is then serially shifted out (a "horizontal shift") to a circuit that converts the electric charges to a series of analog voltages representing the image of that row of pixels. Both the vertical shift and the horizontal shift tend to introduce noise and/or error into the image signal. In order to assist in removing the noise, typical CCD circuits often provide a reference voltage associated with each pixel. In some past designs, the reference voltage for a pixel is stored in a sample-and-hold circuit, and this reference voltage and the image voltage for that pixel are fed to a differential amplifier to generate a difference voltage representing the true image for that pixel. If a source of noise or error affects both the reference and image voltages, generating this difference will remove the effect ofthe noise from the image signal. Some CCD circuits also provide one or more "black pixels" at the beginning and/or end of each row and/or column. In some embodiments, these black pixels have opaque coverings but are otherwise identical in signal characteristics as imaging pixels, and thus the signal from those pixels is representative ofthe signals of other pixels were those pixels to receive a black image (i.e., a pixel having no light). The output of analog-signal-conditioning circuit 120 is fed into digitizing & digital-signal-conditioning circuit 130. Feedback output 135 of digitizing & digital-signal-conditioning circuit 130 is used to control feedback circuit 170. Feedback circuit 170 controls analog-signal-conditioning circuit 120 (using signal 171) in order to reduce the effects of amplifier drift for any amplifiers within the feedback circuit loop, and so that the analog signal 129 fed into digitizing & digital-signal-conditioning circuit 130 is maintained within a range of voltages with which digitizing & digital-signal-conditioning circuit 130 can best function. Image output 139 of digitizing & digital-signal-conditioning circuit 130 feeds into packetizer, serializer, & transmitter block 140. Packetizer, serializer, & transmitter block 140 outputs the serial digital image 149 from machine- vision camera 100, as well as other information necessary for the operation of machine- vision camera 100 onto user interface 190. Receiver, deserializer, & depacketizer block 150 receives data into camera 100, such as operational commands, frame timing signals, and aperture control from user interface 190. Block 150 deserializes the information and passes the information onto command processing circuit 160. Command processing circuit 160 controls the aperture speed and timing, and clock circuitry 180. The control output of clock circuitry 180 provides clocks for the output timing of CCD sensor 110, timing for digitizing & digital-signal-conditioning 130, and output timing for output onto user interface 190 by block 140. In one embodiment, user interface 190 is a high-speed digital video serial link (DSL) passing both commands and data, and its function and the support circuitry of command processing circuit 160, block 140, and block 150 are as more fully described in commonly assigned and copending application 08/410,119 titled HIGH-SPEED DIGITAL VIDEO SERIAL LINK. Figure 2 A shows a more detailed block diagram of one embodiment of machine-vision camera 100 ofthe present invention. Image sensor 110 includes an array 112 of CCD pixels and output circuitry 114. In one embodiment, image sensor 110 includes a full-frame 640-by-480 pixel CCD image sensor, Model KAI-0310 (available from Eastman Kodak Company - Microelectronics Division, Rochester, New York 14650-2010). In another embodiment, image sensor 110 includes a full-frame 1024-by-1024 CCD image sensor, Model KAI 1001 series CCD sensor (also available from Eastman Kodak Company - Microelectronics Division, Rochester, New York 14650-2010). Output circuitry 114, controlled by clocking signals 181, serially outputs an analog image-bearing signal, V out 119, to analog-signal-conditioning circuit 120. In one embodiment, V ouτ 119 is supplied as a 300 millivolt image-bearing signal on top of, for example, an 8-volt DC component. In the embodiment shown, V out 119 is applied through DC-blocking capacitor 122 (which removes the DC component just mentioned) to the input of amplifier 124, which is also coupled to "clamp" or integrator/offset-level adjustor 126 (which provides a replacement adjustable "DC" or "offset-level" component for the signal from the CCD 110 that can be varied, as described below). The output of amplifier 124 is applied to the input of analog-to-digital converter (ADC) 132. In one embodiment, amplifier 124 is omitted, and the clamped signal is coupled directly to ADC 132. ADC 132 is clocked at a suitable sampling rate to convert the clamped analog signal V out 129 to a digitized image-bearing signal, each sample having "n" bits, where "n" is the number of output bits of ADC 132. In one embodiment, a 10-bit ADC, Model HI5766 (available from Harris Semiconductor, P.O. Box 883, Melbourne, Florida 32902) is used for ADC 132. In another embodiment, a 12-bit ADC is used, giving greater resolution to the digitized signal. The output of ADC 132 is fed to the inputs of both digital image register 136 and digital pixel-reference-level register 134. In the embodiment shown, ADC 132, image register 136 and reference register 134 are clocked by clock 205 to generate digital values, one each for both the reference voltage and the image voltage associated with each pixel. Pixel-reference-level register 134 is latched under control of clock 205 qualified by clock-enable 207, and image register 136 is latched under control of clock 205 qualified by clock-enable 209. (In another embodiment, signals 207 and 209 are clocks rather than clock- enables, and thus registers 134 and 136 do not require clock 205.) In one embodiment, clock-enable 207 is the logical inversion of clock-enable 209, causing pixel-reference-level register 134 to be clock-enabled on the opposite transition of clock-enable 209 that image register 136 is clock-enabled. For example, in one embodiment, at the rising edge of a clock cycle, the signal present on the input of image register 136 or pixel-reference-level register 134 is latched into the respective register (See Figure 4A, Clock-enable 209). Clock- enable 209 has a frequency equivalent to the pixel processing rate ofthe circuit. Clock generator 180 includes circuitry that generates clocks, including clocks 171 and 205, and clock-enables 207 and 209. In one embodiment, clock generator 180 includes phase-locked loop circuitry to generate control clocks for output circuitry 114 (clocks 171) and ADC 132 (clock 205) which are synchronized to one another and are automatically varied in edge timing (and/or frequency) as outside stimuli, e.g., ambient temperature, affects the timing ofthe output signal 119 ofthe CCD image sensor. In another embodiment (See Figure 2B), a tapped delay line 281 coupled to multiplexors (for example, multiplexors 283 and 284 in a suitable programmed field-programmable gate array (FPGA) 282, programmable array logic (PAL) or application-specific integrated circuit (ASIC) chip are used to implement suitable multiplexors) are used for varying the frequency and/or edge positions of clocks and clock-enables from clock generator 180. As shown in Figure 2B, oscillator 280 drives FPGA 282, which in turn drives tapped delay line 281, and receives the N tapped, delay signals from delay line 281. In one embodiment, tapped delay line 281 provides ten taps at one nanosecond (ns) intervals, i.e., each delayed one nanosecond more than the one before. Multiplexor (mux) 283 and mux 284 each select one (either the same or different ones) ofthe delayed signals under the control of clock control logic 286, thus allowing selection at an output such as 287 of a clock that is delayed by the same amount on both its rising and falling edges. In addition, both the rising-edge delay and the falling edge delay can be separately specified at output 288, where latch 285 is set by the output of mux 283 and reset by the output of mux 284. In addition, divider 289 provides the ability to divide the frequency ofthe clock from oscillator 280 as required for various clock requirements. Subtractor 138 (see Figure 2 A) receives at its input terminals the output signals from image register 136 and pixel-reference-level register 134, and generates a digital difference signal 139 representative ofthe digital difference between these values. The resultant digital difference signal 139 is the digitally correlated double sample value ofthe image pixel that is used to reduce electrical noise and/or drift errors. Digital difference signal 139 provides one digital value for each pixel. Clamp logic 170 includes electronic circuitry that compares the digital value of pixel-reference-level register 134 to a predefined value, and generates a control signal to adjust the offset level of signal 119 (sometimes referred herein as "to clamp" signal 119, although not identical in function to other "clamp" circuits). In one embodiment, if the reference value contained in pixel- reference-level register 134 is greater than the predefined value, integrator/offset- level adjustor 126 decreases the DC component of clamped signal 129 using an output signal from clamp logic 170. If the value in pixel-reference-level register 134 is less than the predefined value, integrator/offset-level adjustor 126 increases the DC component of clamped signal 129 using an output signal from clamp logic 170. FIG. 2C shows a detailed block diagram ofthe electronics of machine- vision camera 100 of another embodiment ofthe present invention. In this embodiment, otherwise identical to that of Figure 2 A, the output 133 of ADC 132 directly feed adder/subtractor 238 (one embodiment implements adder/subtractor 238 as a staged or pipelined unit, wherein lower-order bits are e.g., added earlier than higher-order bits, latched earlier in reference and image register (RIR) 234, and thus available earlier for subsequent operations, thus increasing throughput ofthe subsystem). During the reference part ofthe cycle, the line reference number 242 is added to the reference part ofthe pixel (the same line-reference number is added to each pixel's reference value for an entire line). The resultant adjusted-reference value is latched into RIR 234 by clock 205 and fed back to mux 241. Then, during the image part ofthe cycle, the adjusted-reference value is subtracted from the image part ofthe pixel, the result again is latched into RIR 234 by clock 205 and fed to image register 136, where it is latched by clock 205 as clock enabled by 209. In both Figures 2A and 2C, measurement and logic 278 sample various portions ofthe image and/or reference signals, and drive control 279 which is used to control the edge positions of various clocks and enable signals from clock generator 180. Referring to Figure 4 A, signal 410 is representative of an idealized analog signal (ideally corresponding to V out 119 from output circuit 114 of Figure 2) showing dark level at point 410 D , and (during cycle n) a reference level at point 410 R and an image level at point 410, for a pixel(n) ofthe analog signal 410. Dark level 410 D is the result of reading out a pixel that is a black (or non-imaging) pixel (explained above). The difference between reference level 410 R and image level 410, represents the image from the first imaging pixel (pixel "n") of a row. In this idealized signal 410, the reference level for each pixel is the same (no noise or drift), and thus the image signal is easily extracted. Signal 420 shows an output signal (in which a drift signal 430 has been added to the reference level and image level of each pixel of signal 410), in which the reference level at point 421 (and the associated image level for that pixel) is varying in a positive direction in cycle n+1, and in a negative direction at point 425 (and the associated image level for that pixel) in cycle n+3. At point 421 the positive increase in the reference level causes the feedback loop to decrease the DC component of clamped V out 129 resulting in the adjusted reference level at point 423 seen in cycle n+2. At point 425 the negative change in the reference level causes the feedback loop to increase the DC component of clamped signal V out 129 resulting in the reference level at point 427 seen in cycle n+4. This feedback causes ADC 132 to have a more consistent reference level signal applied to the input to ADC 132 better enabling ADC 132 to output digital values within the range of ADC 232. For example, drift could cause the voltages ofthe reference levels and the corresponding image levels to both shift by approximately the same amount. The digital subtractor 138 described above will remove the shift, but because the shift occurs before the ADC 132, its dynamic range cannot be fully utilized. For example, using a 10-bit ADC, there are 1024 possible values representative ofthe input analog signal 129. If the analog output from a CCD image sensor has a maximum difference from dark to light of 1.023 volts, each increment on the digitized signal can correspond to 1 millivolt. For example, a black level might be represented by the number 1000 (approximately 1 volt), and a white level might be represented by the number zero (approximately 0 volts). Setting the reference level to be equivalent to dark, and setting the predefined value to, for example, a digital value of 1000, the ADC will correctly digitize the maximum difference from reference level to light by keeping the analog signal at such a level that the reference level is shifted to try to maintain a digitized value of 1000. Without this feedback loop, if the reference level would drift in value to less than a digitized value of 1000 and the image level drift by the same amount (for example, the reference level goes to a voltage corresponding to a digitized value of 800), the ADC would not output the correct value for the condition of maximum difference between the reference level and the image level since the ADC cannot output negative values. Thus the dynamic range of the system would then be limited to 800 values. By providing the feedback loop and controlling integrator/offset-level adjustor 126, drift in the reference levels and image levels is compensated for. Further, drift in amplifier 124 and ADC 132 can also be compensated for. In one embodiment, the digital logic shown in Figure 2 functions as follows (refer also to Figure 4A): Clocks 202, 203, and 204 represent those clocks 171 presented to CCD 110 by clock generator 180 in one embodiment of the present invention. Timing for a pixel on voltage signal V out 119, includes two intervals of time: a first interval (active during the positive portion of clock 204), has a reference level voltage signal, corresponding to an external voltage level provided to output circuit 114 and present after dissipation ofthe electron charge ofthe previously presented pixel, present at V out 119; and a second interval (active during the positive portion of clock 203), has an image-bearing voltage signal, corresponding to the amount of light the pixel was exposed to, present on the output port of output circuitry 114. Clock 202 is the signal to output circuitry 114 to dissipate the electron charge. Clocks 203 & 204 are at the same frequency, and the period of this frequency corresponds to the timing needed to shift the analog voltage signal for one pixel from output circuitry 114. In one embodiment, clock 204 is the logical inversion (i.e., opposite in polarity) of clock 203. At some point after the rising edge of clock 203 exceeds a least positive up level for output circuitry 114, output circuitry 114 begins to output the image level to image-bearing voltage level V out 119. For non-imaging pixels, the level outputted is the dark level (see point 410 D in Figure 4A), and for imaging pixels, the level outputted is the image level shown in point 410, in Figure 4A. The value of image level at point 119D is dependent upon how much light the particular pixel has been exposed to, e.g. the brighter the light the further from the dark level the image level will be. The reference level is shown at point 410 R in Figure 4 A. In one embodiment ofthe present invention, at the negative-going transition of clock 209, see Figure 4A clock 209, the digitized value ofthe reference level is latched in the pixel- reference-level register 134 by clock 207 (see Figure 2), and at the following positive-going transition of clock 209, see Figure 4A clock 209, the digitized value ofthe image-bearing signal is latched into image register 136 by clock 209. (In another embodiment ofthe present invention, clock 205 drives ADC 132, image register (IR) 136, and reference register (RR) 134, and clock-enables 207 and 209 are used to clock-enable the register circuits 134 and 136 respectively.) The value contained in image register 136 is subtracted by subtractor 138 from the value contained in pixel-reference-level register 134. The resultant value is thus a more accurate representation ofthe signal voltage reasonably free from noise and/or drift generated, for example, in the vertical and horizontal shifting operations, in the output circuit 114, in the amplifier 124, and in the ADC 132. Figure 3 A shows one embodiment of feedback circuit 170 and analog- signal-conditioning circuit 130. Using, for example, a 10-bit ADC for ADC 132 and a predefined pixel-value of 992 for comparison to the pixel-reference-level, the 5 most-significant output bits of reference register are applied to the input of NAND 374. If any ofthe 5 most-significant bits are at a digital logic zero level, the value contained in pixel-reference-level register 134 is less than 992; and the output of NAND 374 drives high, increasing the bias voltage on capacitor 327 through rail-to-rail driver 372 and resistor 328. If all ofthe 5 most-significant bits contained in reference register are at a digital logic one level, the value contained in pixel-reference-level register 134 is equal to or greater than a value of 992; and the output of NAND 374 is driven low, decreasing the voltage on capacitor 327. Thus the DC bias voltage of V out 129 is being constantly increased or decreased to a value that results in the reference level corresponding to a digitized value of 992. Since ADC 132 will not output correct values for voltages corresponding to digitized values less than zero, the dynamic range of the system is approximately 992 digital values (out of 1024). This provides an acceptable buffer of about 31 digital values below the top ofthe range of ADC 132 (i.e., the maximum digital value of 1023). In one embodiment, the time constant of integrator/offset-level adjustor 126 and clamp logic 170 is kept relatively slow, such that a maximum change to the clamp voltage corresponds to a one-bit change each pixel. That is, if a 6-unit voltage change (corresponding to 6 times the 1-bit voltage, for example 6 millivolts) is needed to maintain the reference level at the predetermined value, it will take 6 pixel time periods to effect this change. In one embodiment of analog-signal-conditioning circuit 130, labeled 130B shown in Figure 3B, the values of one or more non-imaging pixels present at the start of each row of pixels are sampled, corrected by subtractor 138, added together and then divided by the number of non-imaging pixels at the start of each row, typically 4 or 8, in row accumulator/averager 192 to get an average dark level value 242 (see Figure 2C) which is later subtracted in subtractor 194 from each imaging pixel's image level value for that line or row, thus eliminating row-to-row noise from the vertical analog shifter. CCD 110 provides a CCD signal, a series of analog voltage levels that are conditioned by analog-signal-conditioning (ASC) circuit 120, and sampled by ADC 132 at twice the pixel frequency (i.e., once during the reference portion ofthe pixel cycle, and then once during the image portion ofthe pixel cycle). In Figure 3B, the digitized reference samples are latched in reference register 134, the digitized image samples are latched in reference register 136, and a subtraction is performed by subtractor 138 (in one embodiment, the reference value is inverted, i.e., the one's complement is taken, and added to the image value, thus yielding a value that is one less than the true grey-scale image value which would be obtained by two's complement arithmetic; in one such embodiment, a one is later added to all image pixel values). In one such embodiment, one or more rows ofthe non-imaging pixels in each frame (or, in another embodiment, all pixels of one or more frames are averaged on order to get a number used to achieve frame-to-frame brightness control) are added together in accumulator/averager 196, then divided by the number of imaging pixels in those rows (e.g., either 4 or 8 pixels are added, and the result is right shifted 2 or three bits, respectively) to get an average frame- noise or brightness for the frame; this number is compared to a desired average frame-noise or brightness number, and the difference is used to generate a correction signal that is later subtracted by subtractor 198 from each pixel image value for the entire frame, thus reducing frame-to-frame drift or noise, or controlling brightness. Signal 137 thus represents the raw digitized value ofthe clamped voltage 129, signal 139A represents this value after subtracting the pixel reference value 135 (i.e., for one pixel), signal 139B represents this value after subtracting the row reference value 193 (i.e., the reference for one row is subtracted from each pixel in that row), and signal 139C represents this value after subtracting the frame reference value 135 (i.e., the reference for one frame is subtracted from each pixel in that frame). In various embodiments, either signal 139 A, 139B or 139C is used as the signal 139 output from block 130. The details of one embodiment of adder/subtractor 238 of Figures 3C and 2C is shown in Figure 3D. A stylized representation of signal 119 is shown in the voltage- versus-time graph of Figure 3E that shows the reference portion of the pixel cycle and the image portion ofthe pixel cycle. It is desirable to sample the signal for the reference value as late in the reference portion ofthe pixel cycle as possible without going past the knee ofthe curve, and similarly it is desirable to sample the signal for the image value as late in the image portion of the pixel cycle as possible without going past the knee ofthe curve, in order to allow the most time for each signal to settle to their respective true values. In one embodiment of Figures 3B and 3C, a calibration operation is performed at the factory and/or periodically during operation of camera 100 to adjust the appropriate sampling clock edges and camera-driving clock edges from clock generator 180, which is controlled by periodically adjusting the edges to determine their optimal positions. This provides compensation for drift, component aging, and/or temperature effects that might affect CCD 110, ASC 120, ADC 132, and clock generator 180 itself, as well as other components of camera 100. Figure 3C shows an another embodiment of digital-signal-conditioning circuit 130, labeled 130C. This embodiment performs functions similar to those described above for Figure 3B, but in a manner similar to Figure 2C. The reference value from ADC 132 is inverted (ones complement) by invertor 338 and added to the line reference 242 during the reference portion ofthe pixel cycle (see Figure 3E) and the adjusted-reference result is latched in reference/image register 234 (an accumulator). The output of register 234 is coupled to mux 341 through invertor 339, and added to the inverted image value from ADC 132 during the image portion ofthe pixel cycle (see Figure 3E) and the adjusted-image result is latched in reference/image register 234. The adjusted-image result is then latched into image register 136, and digital pixel values output ofthe adjusted-image result are output on bus 139C. At the start of each line, the line reference 242 is set to a predetermined value during the measurement of a certain number of "black-reference pixels", and the adjusted-reference results are then latched into reference register 134, and digital pixel values output ofthe adjusted-reference result are output on bus 135. As described above for Figure 3B, the values of one or more non-imaging pixels present at the start of each row of pixels are sampled, corrected by subtractor 238 relative to the predetermined value, added together and then divided by the number of non-imaging pixels at the start of each row, typically 4 or 8, in row accumulator/averager 343 to get an average row dark level value 345, that is used for line reference 242 (see Figure 2C) which is later subtracted in subtractor 238 from each imaging pixel's image level value (i.e., by adding the line reference to the inverted CCD reference value that is then inverted and added to the inverted CCD image value) for that line or row, thus eliminating row-to-row noise from the vertical analog shifter. In one such embodiment, an average frame black value (e.g., a frame- noise value or brightness-offset value) is accumulated in accumulator/averager 344 (i.e., a value that applies to every row, as described above for Figure 3B), to get an average frame dark level value 346, that is added to each row value 345 in adder 342 and used for line reference 242. Referring again to Figure 4A, signal 410 is representative of an idealized analog signal in which (during cycle n) the voltage of signal 410 settles rapidly to a reference level at point 410 R which is maintained (at a constant voltage) for a relatively long time and which also later settles rapidly to image level at point 410, for a pixel(n) ofthe analog signal 410. For actual image sensor circuits 110, the actual signal 119 looks more like signal 440 as shown in Figure 4B. The dissipation intervals shown represent artifacts ofthe signal that ends the image phase ofthe previous pixels. Starting at the time point that ends the dissipation interval of pixel n-1 (T dis . eπd(n _ 1) ), V ouτ 440 transitions to the reference voltage level for the n th pixel V ref , n) . This transition is not instantaneous, but is limited by, among other factors, the equivalent RC constant ofthe circuitry of and attached to imaging device 110. In order to obtain the most accurate representation of reference level V ref(n) , it is advantageous to sample V ouτ 440 as close as possible to the ending time ofthe reference interval, and preferably, at or immediately before T ref . end(n) . This allows the most time for the signal V ouτ 440 to settle to its correct reference value for this pixel. Likewise, in order to obtain the most accurate representation of image level V ιmg(n) for pixel n, it is advantageous to sample V ouτ 440 as close as possible to the ending time ofthe image interval, and preferably, at or immediately before T img . end(n) . This allows the most time for the signal V ouτ 440 to settle to its correct image value for this pixel. In one embodiment, a single row of imaging pixels at the starting (or ending) edge of a frame is used, not for imaging, but instead to calibrate the timing of sampling clock 205 (which is used to trigger the sample-and-hold and/or conversion functions of ADC 132, both for sampling the V ref(n) and V img(n) for each given pixel). In one such embodiment, this operation is performed periodically in an operating camera (for example, once per frame, once per second, or once per minute), in order to compensate for timing drift caused by, e.g., temperature changes. In one such embodiment, the timing to adjust the pulse edge (P ref ) that captures V ref(n) is calibrated separately from the timing to adjust the reference pulse edge (P ref of signal 202) that captures V jmg(n) . Figure 4C is a flow chart showing one method for adjusting the reference pulse P ref and the image pulse P img of sampling clock 205 relative to signal V out 119. In one embodiment (see the flow chart of Figure 4C starting at block 450), the timing of reference pulse edge (P ref ) is made to occur later and later (relative to some fixed repeating pixel timing edge, such as clock 202) for successive pixels (at block 452) until it is determined at block 456 (e.g., by watching for a sudden drop in the measured V ref for subsequent pixels) that the pulse is occurring after T ref . end(n) . The delay timing is then "backed off by a predetermined amount (in block 458) to ensure that subsequent reference timing pulses P ref of clock 202 (i.e., pulses used in operation of camera 100 until the next calibration operation) are as close as desired to the correct timing. For example, at block 450, the V ref for a pixel n is measured; at block 452, the delay of P ref for a subsequent pixel n+1 is increased slightly, and at block 454, the V ref for the subsequent pixel n+1 is measured; at block 456 the V ref(n+1) is compared to V ref(n) and if it has changed significantly, control drops to block 458 where the delay is shortened by an empirically determined (or predetermined) amount to ensure operability ofthe system, and at block 460, this delay is saved for later use; and if at block 456 the measured V ref had not changed significantly, control is passed back in the loop to block 452 and the process is iterated until the "correct" timing edge is determined. In a similar manner as adjusting the P ref delay, the timing of image pulse edge (P ιmg ) is made to occur later and later (relative to a fixed repeating pixel timing edge, such as clock 202) for successive pixels until it is determined (e.g., by watching for a sudden rise in the measured V ιmg for subsequent pixels) that the pulse is occurring after T ιmg . end(n) . The delay timing is then "backed off by a predetermined amount to ensure that subsequent reference timing pulses P ιmg of clock 202 (i.e., pulses used in operation of camera 100 until the next calibration operation) are as close as desired to the correct timing. For example, at block 470, the V ιmg for a pixel n is measured; at block 472, the delay of P ιmg for a subsequent pixel n+1 is increased slightly, and at block 474, the V ιmg for the subsequent pixel n+1 is measured; at block 476 the V ιmg(n+1) is compared to V ιmg(n) and if it has changed significantly, control drops to block 478 where the delay is shortened by an empirically determined (or predetermined) amount to ensure operability ofthe system, and at block 480, this delay is saved for later use; and if at block 476 the measured V ref had not changed significantly, control is passed back in the loop to block 472 and the process is iterated until the "correct" timing edge is determined. At block 482, the camera 100 is operated using the saved values for delays for P ref and P ιmg . After operating for some amount of time at block 482 (short enough to ensure that a significant amount of timing drift has not occurred), control passes back to block 450 to repeat the calibration operation. In another embodiment, the delay of P ref and/or P ιmg are initially selected to be too long, and the measurement-test-and-change-delay loop is used to iteratively shorten the delay until the proper timing is determined. In one such embodiment, DC initialization to the knee ofthe reference portion ofthe CCD signal is more difficult, since the adjustment can move the DC offset the wrong direction, thus setting the wrong portion ofthe CCD signal to the back reference value (e.g., to 1000). Generally, it is easier to start with the delay of P ref too short, and then lengthen that delay until the knee ofthe curve is reached. In other embodiments, the above-described calibration operation is performed during the manufacturing operation in the factory, and the timing is then locked in for later field operation. In still other embodiments, the above- described calibration operation is performed during non-imaging-pixel times at the beginning or end of each row, or the beginning or end of each frame. In yet other embodiments, the above-described calibration operation is performed for an entire frame every so often, e.g., once per minute or once per hour. In once such embodiment, the aperture 103 is left open long enough to overexpose most or all pixels ofthe frame to a "white" level in order to get sharper timing edges for the calibration operation. In still other embodiments, only a single calibration operation is used (i.e., calibrating either P ref or P jmg , and using that timing delay calibration to set the delays for both P ref and P img ) and the appropriate adjustment to the flow chart of Figure 4C is made. In one embodiment (see Figure 2B), the clock-control logic 286 controls edges of clocks by measuring the knee at the end of reference portion curve (Figure 3E) and the knee at the end of image portion curve (Figure 3E) by moving the edge (e.g., using successive taps of delay line 281) ofthe reference- sampling clock to ADC 132 until the reference knee is found, and by moving the edge ofthe image-sampling clock to ADC 132 until the image knee is found, both of these tests done, in one embodiment, during scan rows not used for imaging (i.e., either black rows if CCD 110 provides these, or edge-of-image lines that are not used by the machine vision system 900 (see Figure 9) if not). Once the knees are found, the respective clock edges are backed off to a suitable operating point. Note that clock 205 provides both the image-sampling clock (e.g., the even sampling edges) and the reference-sampling clock (e.g., the odd sampling edges) on the same signal, and that these are separately adjustable in this embodiment of clock generator 180. The mechanical package of one embodiment ofthe present invention is shown in Figures 5 A, 5B, 5C, 5D, 5E, 5F, 5G, 6, 7, and 8A-8K3. Figure 5 A is an isometric view of camera 500 showing a four-sided camera body 502 with a substantially square cross-section, front lens-mounting plate 503, and lens assembly 102. Figure 5B shows a detailed cross-section view of one embodiment of camera body 502 showing dovetail slots 512, and cooling fins 510. In the embodiment shown, dovetail slots 512 each include inward-angled faces 520 and 522, flat bottom face 524, and slightly elevated bottom-edge faces 526. The slightly elevated bottom-edge faces 526 help to keep dovetail insert 810 from adhering or sticking to flat bottom face 524. Figure 5C shows a detailed cross-section taken at one end of camera body 502 showing dovetail slots 512, cooling fins 510, screw-holding grooves 550, end recess 580, and card-mounting slots 712. Figures 5F and 5G show cross-sections at the edge and center, respectively, of end plate 503, showing edge groove 581 that mated with recess 580, and screw holes 551 for the screws that mate with screw grooves 550. Figure 5D shows a detailed lengthwise cross- section of camera body 502 showing end recesses 580 and card-mounting slots 712. In the embodiment shown, camera body 502 includes small cooling vanes or fins 510 (used to increase the surface area of housing 502 and thus better cool the electronic circuitry inside the camera body 502, e.g., that circuitry shown in Figures 1, 2A, 2B, 2C, 3 A, 3B and/or 3C) and dovetail slots 512. Dovetail slots 512 are used for attaching the camera 500 to the camera mounting apparatus of dovetail insert 810, (i.e., 810A, 810B, 810C or 810D) as shown in Figures 8A- 8K. In the embodiment shown, dovetail slots 512 are made on each ofthe four sides, to enable camera 500 to be mounted on any one of four different orientations that are at substantially 90 degrees from each other. This enables the camera user to rotate the camera to have images taken with the long dimension ofthe image on the horizontal, i.e., landscape orientation, or with the long dimension ofthe image on the vertical, i.e., portrait orientation. In other embodiments, camera body 502 is built with more than four sides each having a dovetail slot 512, e.g., approximately hexagonal or octagonal in cross-section, enabling camera 500 to be mounted in a multitude of orientations; e.g., for a hexagonal body, the orientations can be at 60-degrees to each other, and for an octagonal body, the orientations can be 45-degrees to each other. For example, Figure 5E is an isometric view of camera 500 showing a six-sided camera body 502 with a substantially hexagonal cross-section, front lens-mounting plate 503, and lens assembly 102. In one embodiment, camera body 502 is fabricated in extruded aluminum. In one such embodiment, an extrusion is fabricated as a suitable length, e.g., approximately twelve feet (approximately 3.65 meters) long, and then suitable-length pieces are cut to make individual camera bodies, e.g., 3.85 inches (approximately 9.8 cm) long. In one embodiment, the cross-section of camera housing 502 shown in Figure 5B has an outside dimension of approximately 1.75 inches by 1.75 inches (approximately 4.5 cm by 4.5 cm). In one such embodiment, aluminum body 502, as well as end plates 503 and 602 are anodized with an electrically insulating hardcoat layer on at least all external surfaces, in order to provide electrical insulation to the camera body. In one embodiment, this hardcoat layer is equivalent to the anodized aluminum hardcoat provided by Hardcoat Inc. of St. Louis Park, MN. Figure 6 is a back view isometric schematic of a four-sided camera 500 showing camera back plate 602 and cable connector 604. Cable connector 604 is where the cable for user interface 190 is plugged into. The configuration of cable connector 604 is shown for illustrative purposes. Other embodiments of camera 500 may include any suitable type and size of cable connector 604. Figure 7 shows one embodiment ofthe mounting scheme for the printed circuit boards containing the electronics for camera 500. Mother board 702 includes CCD sensor 110, and inter-card connections between daughter board's 706, 708, & 710. In the embodiment shown, extruded aluminum camera body 502 includes slots 712 to secure daughter boards 706, 708, & 710. In other embodiments ofthe present invention, the number of slots 712 can be increased or decreased depending upon the quantity of electronics included in camera 100. CCD sensor 110 is fastened on mother board 702 is such a position as to align CCD sensor 110 to the focal plane of lens 101. Daughter board 706 includes cable connector 604 seen in Figure 6. Cable connector 604 can be fastened to daughter board 706 in a variety of techniques known to those skilled in the art, e.g. soldered and/or riveted. Daughter boards 706, 708, & 710 may be connected to mother board 702 in a variety of techniques known to those skilled in the art, e.g. printed circuit board-to-printed circuit board connectors. Figure 8 A shows one embodiment (i.e., 810A) of camera-mounting apparatus of a split-block dovetail insert 810 (810 refers generally to dovetail inserts such as the exemplary embodiments 810A, 81 OB, 810C, or 810D described below) for camera 500. Dovetail block 809 is made with a pre-loaded force holding dovetails halves 812 & 814 apart. Tightening of screw 816 causes dovetail halves 812 & 814 to come together in order to be placed and fit within slot 512. When the dovetail slot 512 on camera 500 is mounted on dovetail insert 810 and screw 816 is released, surfaces 813 & 815 mate with corresponding surfaces 520 & 522 in slot 512 applying the predetermined force. Since loosening screw 816 allows the predetermined force to be applied, excess force that might damage the camera housing cannot be applied by turning screw 816 too far in either direction. Screw 816 is tightened to allow mounting or removing camera 500, keeping surfaces 813 & 815 away from surfaces 520 & 522. Screw 816 is loosened to secure camera 500 to dovetail insert 810. This results in a known force keeping camera 500 secured to dovetail insert 810, thus alleviating problems of a loosely mounted camera because of too little mounting force, or damaged mounting surfaces from too much mounting force. Figure 8B shows an alternative embodiment ofthe camera- mounting apparatus having a two-part-block dovetail insert 810B1 for camera 500, including block halves 820 and 830. Block half 820 is shown having a rectangular tongue that slides into a rectangular groove (not shown) in block 830, keeping the block halves 820 and 830 in the proper (parallel) relationship to one another. Springs 822 that fit into suitable recesses between block halves 820 and 830 provide the predetermined amount of force to the dovetail as screw 816 is released. Figures 8C, 8D, and 8E shows another alternative embodiment of the camera-mounting apparatus having a two-part-block dovetail insert 810B2 for camera 500, including block halves 840 and 850. Block half 840 is shown having two rods 824 slide into holes in block 850, keeping the block halves 840 and 850 in the proper (parallel) relationship to one another. Springs 822 that fit around the rods 824 and into suitable recesses between block halves 840 and 850 provide the predetermined amount of force to the dovetail as screw 816 is released. Figure 8C shows a top view ofthe assembly of rods 824 and springs 822 to block half 840. Figure 8D shows a side view ofthe assembly of block half 840 to block half 850. Figure 8E shows a top view ofthe assembly of block half 840 to block half 850. In another embodiment, dovetail insert 810 is rigidly attached to camera body 502, and the dovetail slot 512, rather than being part of camera housing 502 is instead made in the external camera-mounting apparatus, in a manner complementary to that described above. FIGs. 8F, 8G, 8H1, 8H2, 8HA, 8HB, 811, 812, and 813 are drawings of the dovetail insert 810C (and of its pieces) of yet another embodiment of a machine-vision camera. In this embodiment, a movable center piece 864 is urged left and downwards (See Figure 8G) by springs 822 (once screw 816 is released) to a predetermined force as determined by the springs. Outer bars 862 and 863 are bolted to two fixed center pieces 861 by four screws 865. Fixed center pieces 861 have angled lips 869 that project into the opposite side of slot 512 in camera 100 as the angled lip 868 of movable center piece 864. FIGs. 8J1, 8J2, 8J3, 8J4, 8KA, 8KB, 8K1, 8K2, and 8K3 are drawings of the dovetail insert 810D (and of its pieces) of still another embodiment of a machine- vision camera. Outer piece 871 is a single-piece replacing pieces 861, 862, 863, and screws 865 of Figure 8F. Movable center piece 874 replaces movable center piece 864. FIG. 9 is a drawing of a system 900 that uses machine- vision camera 100 in an automated manufacturing situation. Control processor 910 uses a DSL communications link 911 to DSL HUB 920, which in turn uses DSL links to control and/or receive information from robot 934, photodetector trigger 942, machine-vision camera 100, conveyor-belt motor 932 that drives conveyor 930, strobe light 940, and reject mechanism 936. Control processor 910 is typically a high-performance image processor and robotics controller that senses and controls much or all ofthe manufacturing process, and takes advantage ofthe improved correlated double sampling of camera 100. In one embodiment (see Figure 10), two dovetail inserts 810 are manufactured back-to-back (e.g., the two are screwed together, or the unit is made as a whole with two or more dovetails) to form a single multiple-dovetail unit 8100. In one such embodiment, one dovetail faces on one direction (e.g., up) and the other faces in another direction (e.g., either down ~ 180 degrees from the first— or to the side ~ 90 degrees from the first, or at any other suitable direction from the first, and having a longitudinal axis at any suitable angle from that ofthe first). A dovetail-slot guiderail 890 of any suitable length is provided (e.g., a 3 meter length of camera body stock 502 as shown in cross section in Figure 5B, or even a flat bar having a single dovetail slot 512). Multiple-dovetail unit 8100 is used to interconnect camera 100 to dovetail-slot guiderail 890, one dovetail to the camera, and one dovetail to the rail. Similarly, another embodiment incorporates a dovetail slot 512 onto strobe 940, in order that a multiple-dovetail unit 8100 may be used to mount the strobe 940 to the camera 100. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope ofthe invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims: What is claimed is: 1. An apparatus for converting an analog image-bearing signal from an electronic imaging device, the image-bearing signal providing an pixel-reference signal and a pixel-image signal for each one of a plurality of pixels ofthe imaging device, the apparatus comprising: a signal clamp that adjusts a level ofthe image-bearing signal based on a black reference level to produce a clamped image-bearing signal; an analog-to-digital converter coupled to digitize the clamped image-bearing signal and operated to produce a first digital value representative ofthe pixel-reference signal for a pixel, and operated to produce a second digital value representative ofthe pixel-image signal; and a first digital subtractor having an input coupled to receive values based on the first and second digital values, the first digital subtractor generating a first digital difference signal based on the first and second digital values. 2. The apparatus as recited in claim 1, further comprising: a first digital register, wherein an input ofthe first digital register is coupled to receive an output from the first digital subtractor, and an output ofthe first digital register is coupled to provide an input to the first digital subtractor. 3. The apparatus as recited in claim 1 or 2, wherein the first digital subtractor generates a intermediate difference value between an offset and the first digital value, and then generates the first difference value between the intermediate difference value and the second digital value. 4. The apparatus as recited in claim 1 or 2 or 3, further comprising: a feedback circuit that adjusts the black-reference level based on a comparison between the digital reference value and a digital black-reference value, the digital black-reference value selected to be near or at one end of a range of values accommodated by the analog-to-digital converter. 5. The apparatus according to claim 1 or 2 or 3 or 4, further comprising: a clock-adjustment circuit that adjusts an image-voltage-signal sampling clock to sample the image- voltage signal at substantially an end of a valid image-sampling interval. 6. The apparatus according to claim 1 or 2 or 3 or 4 or 5, further comprising: a clock-adjustment circuit that adjusts a reference-voltage-signal sampling clock to sample the reference-voltage signal at substantially an end of a valid reference-sampling interval. 7. The apparatus according to claim 1 or 2 or 3 or 4 or 5 or 6, further comprising: a first digital register having an input connected to the analog-to- digital convertor to receive and temporarily store the first digital value; and a second digital register having an input connected to the analog-to- digital convertor to receive and temporarily store the second digital value; wherein the first digital subtractor has an input connected to the first register and second registers. 8. The apparatus according to claim 1 or 2 or 3 or 4 or 5 or 6 or 7, further comprising: an accumulator/averager coupled to an output ofthe first digital subtractor and operated to accumulate and average one or more digital values representative of non-imaging pixels to produce a third digital value representative ofthe accumulated and averages digital values; and a second digital subtractor having an input coupled to receive the first digital difference signal and the third digital value, the second digital subtractor generating a second digital difference signal based on the first digital difference signal and the third digital value. 9. The apparatus according to claim 1 or 2 or 3 or 4 or 5 or 6 or 7 or 8, further comprising: a camera housing; an electronic imaging device contained within the camera housing, wherein the imaging device produces the image-bearing signal based on an optical image, and producing an output coupled to the signal clamp; and an output circuit that drives a digital signal based on the digital pixel- difference value. 10. The apparatus according to claim 9, wherein the output circuit provides a serial digital signal representative of an image captured by the digital electronic camera. 11. The apparatus according to claim 9 or 10, wherein the camera housing has one or more dovetail slots, and a dovetail mounting block operable to maintain a predetermined mounting force to a corresponding one ofthe dovetail slots on the camera housing. 12. The apparatus according to claim 9 or 10 or 11, wherein the camera housing includes two non-coplanar surfaces, and wherein each one of said two surfaces includes a dovetail slot. 13. The apparatus according to claim 12, wherein two ofthe non-coplanar surfaces are at substantially 90 degrees to one another. 14. The apparatus according to claim 9 or 10 or 11 or 12 or 13, wherein the camera housing includes an aluminum extrusion anodized with an electrically insulating layer. 15. The apparatus according to claim 9 or 10 or 11 or 12 or 13 or 14, wherein the camera housing includes an aluminum extrusion having a plurality of cooling fins. 16. A method for converting an analog image-bearing signal from an electronic imaging device, the image-bearing signal providing an pixel-reference signal and a pixel-image signal for each one of a plurality of pixels ofthe imaging device, the apparatus comprising: adjusting an analog level ofthe image-bearing signal based on a black reference level to produce a clamped image-bearing signal; digitizing the clamped image-bearing signal to produce a first digital value representative ofthe pixel-reference signal for a pixel; digitizing the clamped image-bearing signal to produce a second digital value representative ofthe pixel-image signal for the pixel; and generating a first digital difference signal based on the first and second digital values. 17. The method of claim 16, further comprising: storing an output from a first digital subtractor, and the stored output ofthe first digital register coupled to an input to the first digital subtractor. 18. The method of claim 16 or 17, further comprising: generating a intermediate difference value between an offset and the first digital value, and wherein generating the first difference value provides a difference between the intermediate difference value and the second digital value. 19. The method of claim 16 or 17 or 18, further comprising: adjusting the black-reference level based on a digital comparison between the digital reference value and a digital black-reference value, the digital black-reference value selected to be near or at one end of a range of values accommodated by an analog-to-digital convertor. 20. The method of claim 16 or 17 or 18 or 19, further comprising: adjusting an image- voltage-signal sampling clock to sample the image-voltage signal at substantially an end of a valid image-sampling interval. 21. The method of claim 16 or 17 or 18 or 19 or 20, further comprising: adjusting a reference- voltage-signal sampling clock to sample the reference-voltage signal at substantially an end of a valid reference-sampling interval. 22. The method of claim 16 or 17 or 18 or 19 or 20 or 21, further comprising: temporarily storing a first saved value based on the first digital value; and digitally subtracting to generate a difference between the first saved value and the second digital value. 23. The method of claim 16 or 17 or 18 or 19 or 20 or 21 or 22, further comprising: accumulating and averaging one or more digital values representative of non-imaging pixels to produce a third digital value representative ofthe accumulated and averages digital values; and generating a second digital difference signal based on the first digital difference signal and the third digital value. 24. The method as recited in claim 16 or 17 or 18 or 19 or 20 or 21 or 22 or 23, further comprising: providing a camera housing; mounting an electronic imaging device within the camera housing, wherein the imaging device produces the image-bearing signal based on an optical image, and producing an output coupled to the signal clamp; and driving a digital output signal based on the digital pixel-difference value. 25. The method as recited in claim 24, wherein the digital output signal is a serial digital signal representative of an image captured by the digital electronic camera. 26. The method as recited in claim 24 or 25, wherein the camera housing has one or more dovetail slots, and the method further comprises: clamping one ofthe dovetail slots on the camera housing to a corresponding dovetail mounting block using a predetermined mounting force that cannot be exceeded. 27. The method as recited in claim 24 or 25 or 26, wherein the camera housing includes two non-coplanar surfaces, and wherein each one of said two surfaces includes a dovetail slot. 28. The method as recited in claim 27, wherein two ofthe non-coplanar surfaces are at substantially 90 degrees to one another. 29. The method as recited in claim 24 or 25 or 26 or 27 or 28, wherein the camera housing includes an aluminum extrusion anodized with an electrically insulating layer. 30. The method as recited in claim 24 or 25 or 26 or 27 or 28 or 29, wherein the camera housing includes an aluminum extrusion having a plurality of cooling fins. 31. A method for adjusting timing for converting an analog image-bearing signal from an electronic imaging device, the image-bearing signal providing a pixel-reference signal and a pixel-image signal for each one of a plurality of pixels ofthe imaging device, the method comprising the steps of: (a) measuring either the pixel-reference signal or the pixel-image signal for a pixel using a timing pulse; (b) changing a delay ofthe timing pulse; (c) measuring either the pixel-reference signal or the pixel-image signal for a subsequent pixel using the timing pulse; ( based on a change amount ofthe measured signal, conditionally branching back to step (b); (e) adjusting the change to the delay ofthe timing pulse to produce an adjusted delay; (f) saving the adjusted delay ofthe timing pulse; and (g) operating the electronic imaging device using the saved adjusted delay to control the timing pulse. 32. The method according to claim 31 , wherein steps (a) through (d) are performed on a plurality of imaging pixels within a row of pixels ofthe imaging device. 33. The method according to claim 31 , wherein steps (a) through (d) are performed on a plurality of non-imaging pixels ofthe imaging device. 34. A camera mounting system comprising: a camera housing having one or more dovetail slots, and a dovetail mounting block operable to maintain a predetermined mounting force to a corresponding one ofthe dovetail slots on the camera housing. 35. The camera mounting apparatus of claim 34, wherein the camera housing includes two non-coplanar surfaces, and wherein each one of said two surfaces includes a dovetail slot. 36. The camera mounting apparatus of claim 34 or 35, wherein two ofthe non-coplanar surfaces are at substantially 90 degrees to one another. 37. The camera mounting apparatus of claim 34 or 35 or 36, wherein the camera housing includes an aluminum extrusion anodized with an electrically insulating layer. 38. The camera mounting apparatus of claim 34 or 35 or 36 or 37, wherein the camera housing includes an aluminum extrusion having a plurality of cooling fins.

Inventors: LIEBERT SCOTT S, TONKIN STEVEN W, LIEBERT, SCOTT, S., TONKIN, STEVEN, W.
Applicants: PPT VISION INC, PPT VISION, INC.
Application year: 1998
Main classification: H04N5
IPC codes: H04N5