SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD FOR SEMICONDUCTOR COMPONENT

Abstract: A semiconductor comprising a buried conducting layer (108), such as a buried collector, comprises a trench, the walls of which are covered with a layer (109') of a material in which dopant ions diffuse faster than in monocrystalline silicon. A contact area is doped in close proximity to the trench wall (109'). The dopants will diffuse through the layer (109') and form a low resistance connection to the buried layer (108). The layer (109') may comprise polysilicon or porous silicon, or a silicide. If the material used in the layer (109') is not in itself conducting, the size of the component may be significantly reduced.

Description: Semiconductor Component and Manufacturing Method for Semiconductor Component Technical Field The present invention relates to semiconductor components and in particular to a method of achieving a low resistance in semiconductor components comprising a buried conducting layer, and to such a semiconductor component. Background Silicon on Insulator (SOI) materials offer a number advantages when making semiconductors, for example latchup immunity, galvanic insulation between components and reduced parasitic capacitance. The SOI material most frequently used today comprises a thin silicon layer, for example between 500 A .and 30μm thick, on top of an insulating layer, such as silicon dioxide. The active components are located in the silicon layer and are isolated from each other by means of trenches that are etched down to the buried oxide and normally filled with oxide .and polycrystalline silicon (polysilicon). Often, a buried conducting layer is used, which is then located adjacent to the buried oxide. Such a conducting layer may be, for example, a collector in a bipolar component, or, in a field effect component, a drain. For simplicity, in the discussion below, the term collector, or buried collector, is used. Also the term collector resistance is used to describe the resist.ance from a contact at the surface to the buried conducting layer. Depending on the component type, the component also comprises other doped areas, such as a base and an emitter in a bipolar component, a gate and a source in a field effect component, and an anode or a cathode in a diode. To minimize costs, the area of the components should be minimized. Also the component's performance must be good like d e collector resistance that should be low. The use of trenches enables the collector resistance to be minimized, if the trench wall is doped. This doped area surrounds the component and extends down to the buried collector. An alternative way of minimizing the collector resistance is to make a deep diffusion from the surface near the collector contact down to the buried collector. The dopants in the buried collector then at the same time diffuse upwards. This diffusion must be compensated for by using a thicker silicon layer. This adds an extra masking step to the manufacturing process, and it becomes more difficult to obtain insulation by means of trenches. To minimize the area of the component, the trench wall may be kept without doping. An area of an opposite doping type, can then be placed relatively close to the trench, to form, for example, a base, an anode or a cathode. This results, however, in a degraded component performance in terms of an increased collector resistance. As a result of this, especially power transistors must be made very big. Summary of the Invention It is .an object of the present invention to obtain a semiconductor component, with a buried collector, having a low collector resistance. It is another object of the invention to obtain a comparatively small semiconductor component. These objects are achieved according to d e invention by a method of achieving a low resistance connection to a buried conducting layer in or below a device layer constituting part of a semiconductor component, said method comprising the following steps: - etching at least one trench in the device layer, delimiting the area of an active component; - applying a trench wall layer of a material in which a dopant diffuses faster than in the substance in which the buried layer is located, on the walls of the trench; If an area on the surface of said active component in direct connection with the trench wall layer is doped, the dopant of this area will diffuse dirough said trench wall layer, and a short way into the device layer to form a contact to the buried layer. The trench wall layer may comprise polysilicon or porous silicon, or a metal silicide. If polysilicon or porous silicon is used, the trench wall will only be conducting in the vicinity of the doped contact area. All other parts of the trench wall may therefore be placed arbitr-arily near any other doped areas of the component, and even adjoining them. Suicides are in themselves conductors; using a silicide will therefore result in an improved contact. On the other hand, the silicide cannot be used as near die base area of the component as polysilicon or porous silicon. The size of the component will therefore not be reduced compared to prior art components if silicide is used. The invention offers the following advantages: The semiconductor component with a low collector resistance may be achieved without any additional masking steps. The yield and die reliability of the component can be increased, making use of a near by getter centre. Getter centres are areas that will capture metallic impurities that can otherwise degrade d e performance of the component. The upper silicon layer can be made thinner man when conventional techniques, with a deep diffusion from me top surface down to d e buried collector .are used. The component can be made smaller m.an with conventional techniques, such as doping of die trench walls. If the trench according to die invention is formed at an early stage, it will function as a getter centre, gettering metallic impurities. Brief Description of the Drawings Figure 1 is a cross-sectional view of a prior art bipolar transistor made in an SOI material; Figure 2 shows the component of Figure 1, seen from above; Figures 3 A -3F are cross-sectional views of parts of a semiconductor in d e manufacturing process according to one embodiment of d e invention. Figure 4 is a cross-sectional view of a part of the resulting component from the process outlined in Figures 3 A-3F. Figure 5 is the bipolar transistor of Figure 4, seen from above. Detailed Description of Embodiments Figure 1 is a cross-sectional view of a prior art transistor made in an SOI material. On a substrate layer 1, lies an insulating layer 3, for example, of silicon dioxide. On the insulating layer there is a silicon layer 5 comprising the active components 7a, 7b, separated by trenches 9 providing lateral insulation between the components. Here, only one of die active components 7a will be considered. A buried collector 11 is located in die silicon layer 5, adjacent to the insulating layer 3. An emitter 13 is located at me surface of the active component 7a, surrounded by a base 15, in die way common in the art. A collector contact 17 is located at die surface of d e active component 7a, close to the trench wall. An area 19 of the trench wall has been doped, to provide a low-resistance connection from die collector contact 17 to the buried collector 11. The trench 9 is normally formed according to the following: The trench is etched in a conventional way down to d e buried oxide. The trench wall is dien doped in a conventional way, for example, with doping impurities from a gas source in a furnace or by high angle implantation. An oxide layer 21 is then grown or deposited in the trench, which is then filled with polysilicon. Because d e trench wall 19 has been doped all die way around d e component 7a, die distance between die base 15 and die french wall 19 must be kept large to prevent die formation of a too strong electric field near the base, which might lead to an avalanche breakdown. Figure 2 shows the component 7a of Figure 1 seen from above, where the same reference numerals have been used to signify the same components as in Figure 1. The component 7a is surrounded by die trench 9. The trench wall is doped to serve as a connector between the collector contact 17 and the buried collector (not shown). As can be seen, the base 15 and die trench wall 19 must be kept apart by substantially die same distance in all directions, as shown by the aπows 23. Figures 3 A to 3F show important steps of the manufacturing process relevant to the production of die low collector resistance connection according to die invention, diat is, to produce die component shown in Figure 4: Figure 3 A shows a semiconductor component comprising a substrate layer 101, an insulating layer 103 and a silicon layer 105 in which a trench has been formed using conventional masking and etching techniques. The component comprises an active component 107 witii a buried conducting layer 108. Before this stage, the surface of die component may be covered with an oxide and/or nitride layer (not shown). Figure 3B shows the same semiconductor component with a layer 109 deposited over die surface of die component, including d e walls and bottom of the trench. The layer 109 comprises a material in which dopant ions diffuse significantly faster than in monocrystalline silicon, such as polysilicon, porous silicon or a silicide. In the case of layer 109 being a silicide, a metal is first applied over die component, including die walls and bottom of the trench. During a subsequent heat treatment, silicide is formed at die silicon-metal interface in the trench, die remaining metal is removed, by selectively etching the metal and not die silicide. Figure 3C shows die same semiconductor component after the layer 109 has been etched back from die top of the component and from d e bottom of the trench, leaving a layer 109' of die material covering d e trench walls. The layer 109 does not have to be removed from the bottom of the trench, but usually is, for practical reasons when anisotropic reactive ion etching is used. Figure 3D shows die same semiconductor component after a layer 111 of oxide has been grown or deposited over d e whole surface of the component. Instead of an oxide, silicon nitride or another insulating material may be deposited. In Figure 3E, the trench of die component has been filled witi a suitable material, such as polysilicon, and an emitter 113 and a base 115 have been formed, by mask- ing and doping steps, in d e way common in the art. In Figure 3F, collector contact 117 has been formed, by masking and doping, in die way common in the art. The collector contact 117 is in contact with a part of die layer 109' covering die trench wall (This part 109a is shown in Figure 5). The component is tiien subjected to an annealing process in a way well known in the art. The annealing process is carried out until the dopant reaches die buried collector. The dopant should, however, not be allowed to diffuse so far as to increase d e risk for an avalanche breakdown with doped regions. The annealing times an temperatures depend, among otiier tilings, on die deptii of die trench. Typical values are 1-10 hours at temperatures of approximately 800-1250C As the diffusion velocity of the dopants in polysilicon, porous silicon and silicide is much higher man in monocrystalline silicon, dopants from me collector contact 117 will diffuse drrough the layer 109a (see Figure 5) down to die buried collector 108, also diffusing slightly into die adjacent silicon of d e active component, and forming a low-resistance connection from the collector contact to d e buried collector 108. Suicides are in memselves conductors. Therefore, d e use of a silicide will reduce die collector resistance even more man die use of polysilicon or porous silicon. On die otiier hand, die distance between die trench wall and d e base will have to be increased if d e trench wall comprises a conductor. If polysilicon or porous silicon is used, d e trench wall will be conducting only in d e vicinity of the collector contact, so tiiat this is the only part of the trench that have to be far away from die base, as shown in Figure 5. Figure 4 is a cross-sectional view of part of die component shown in Figure 3F, to illustrate die diffusion of dopant ions from die collector contact 117 down to die buried collector 108. As can be seen, d e dopant diffuses from the collector contact 117 dirough the layer 109' down to the buried collector 108 and also a short distance into die silicon of die active component 107. The layer 109' and d e area of the active component 107 into which the dopant diffuses, togetiier form a low- resistance connection from the collector contact 117 to die collector 108. The trench formation procedure may be earned out at any point in d e manufacturing process of die semiconductor, i.e. before or after die formation of die active components. If the trench according to the invention is formed at an early stage, before any components are formed, it will also function as a getter centre, to capture any metallic impurities tiiat may be introduced in d e processing. Even if made at a later stage, die trench according to die invention may still serve to reduce leakage currents but will not be able to getter impurities, or to heal damages such as emitter shorts, to the same degree as if it is present while die active components are being formed. Figure 5 shows die active component of Figure 3F, seen from above, assuming mat die material used in d e layer 109' is not in itself conducting. In this case, only a portion 109a of die layer 109' and a region of die active component in the vicinity of this portion 109a is conducting, because of die diffusion of dopants from die contact 117. As can be seen, the base 115 may be located very near the trench walls 109' on all sides except the side 109a, at which the collector contact 117 is located. If desired, die trench wall may be placed at a distance of less tiian lμm from the base, or even adjoining d e base 115. This makes the component significantly smaller man d e prior art component shown in Figure 2. As mentioned in die introduction, die invention is not only applicable to tr.ansistors comprising a buried collector, but is equally applicable to other semiconductors comprising a buried conducting layer, such as diodes, thyristors, MOS or DMOS transistors or IGBTs, when a low resistance contact to the buried conducting layer is desired.

Claims: CLAI MS 1. A method of achieving a low resistance connection to a buried conducting layer (108) in or below a device layer (105) constituting part of a semiconductor compo- nent, said method comprising die following steps: - etching at least one trench in die device layer (105), delimiting die area of an active component (107); - applying a layer (109') of a material in which a dopant diffuses faster tiian in the substance in which the buried layer is located, on die walls of the trench; - doping an area of said active component (107) in direct contact with the layer (109'), to form a contact (117); armealing the component until die dopant has diffused down to the buried conductor (108). 2. A method according to claim 1, wherein the component is .annealed until die dopant has diffused down to die buried conductor (108) but is still far enough from the otiier doped region or regions (115) to avoid causing a decrease in die breakdown voltage. 3. A metiiod according to claim 1 or 2, characterized by die steps of: - depositing or growing a layer (111') of oxide and/or silicon nitride on die layer (109') in the trench. 4. A method according to any one of the preceding claims, characterized in that die portion (109a) of die trench wall adjacent to die contact (117) is located farther away from die doped region or regions (115) tiian the rest of the trench wail. 5. A method according to claim 4, characterized in that the portion (109a) of die trench wall adjacent to die contact (117) is located at least twice as far away from the doped region or regions ( 115) as die rest of die trench wall. 6. A method according to claim 4, characterized it tiiat the part of the trench wall not adjacent to the contact (117) is located at a distance smaller tiian l.um from the doped region or regions (115). 7. A method according to any one of die preceding claims, characterized by using polysilicon or porous silicon in the layer (109'). 8. A method according to any one of die preceding claims, characterized by using a silicide in the layer (109'). 9. A method according to any one of the preceding claims, characterized in that die device layer (105) comprises monocrystalline silicon. 10. A method according to claim 10, characterized in diat the device layer (105) is located on an insulating layer (103). 11. A method according to ∑my one of die preceding claims, characterized in that the buried conductor (108) comprises silicide. 12. A semiconductor component comprising a device iayer (105) in which at least one active component (107) is located and laterally dehrnited by a trench and having a buried conducting layer (108), there being a layer (109') on the wall of said trench of a material in which a dopant diffuses faster than in die substance of die device layer in which die buried layer is located, said component being characterized m tiiat at least one portion of said layer (109') is doped whereas at least one portion of said layer is substantially undoped. 13. A semiconductor component according to claim 12, characterized in - mat there is a contact (117) to the buried conducting layer on die surface of the active component (107), in direct contact with a doped part of die layer (109'). 14. A semiconductor component according to claim 12 or 13, characterized in - mat die dopant of the contact (117) has diffused through d e layer (109') to the buried conductor (108), so tihat a low resistance connection from die contact (117) to die buried conductor (108) has been formed. 15. A semiconductor component comprising a device layer (105) in which at least one active component (7a) is located, said component (7a) being laterally delimited by a trench and having at least one doped area (115) and a buried conductor (108), characterized in - tiiat there is a layer (109') on die wall of said trench of a material in which a dopant dLiffuses faster tiian in the substance in which the buried collector (108) is lo- cared; - that diere is contact (117) on the surface of the active component, in direct contact with a portion of the layer (109'); - tiiat said portion of die layer (109') comprises die same dopants as die collector contact (117), foirning a low resistance connection from die collector contact (117) to d e buried collector (108), whereas at least one otiier part of the layer (109') is substantially without dopants. 16. A semiconductor component comprising a device layer (105) in which at least one active component (7a) is located, said component (7a) being laterally delimited by a trench and having a base (115), an emitter (113) and a buried collector (108), characterized in - that there is a layer (109') of a material in which a dopant diffuses faster than in the substance in which the buried collector (108) is located, on the wall of said trench; - tiiat mere is collector contact (117) on die surface of the active component in direct contact with the layer (109'); - that at least one portion of the layer (109') comprises the same dopants as the collector contact (117), forming a low resistance connection from the collector contact (117) to the buried collector (108), whereas at least one other part of the layer (109') is substantially undoped. 17. A semiconductor component according to any one of the claims 12-16, characterized in that die layer (109') comprises polycrystalline silicon or porous silicon. 18. A semiconductor component according to any one of die claims 12-16, characterized in tihat tiie layer (109') comprises a silicide. 19. A semiconductor component according to any one of he claims 12-18, charac- terized in that the device layer (105) comprising me active component (107) is a silicon layer located on a substrate (101) with an insulating layer (103) therebetween. 20. A semiconductor component according to any one of the claims 12-19, charac- terized in that die portion (109a) of the trench wall adjacent to die contact (117) is farther away from the doped region or regions (115) dian die rest of ti e trench wall. 21. A semiconductor component according to claim 20, characterized in at the portion (109a) of e trench wall adjacent to die contact (117) is at least twice as far away from die doped region or regions (115) tiian tihe rest of the trench wall. 22. A semiconductor component according to claim 20, characterized it at die part of the trench wall not adjacent to d e contact (117) is located at a distance smaller tiian lμm from the doped region or regions (115). 23. A semiconductor component according to any one of die claims 12-22, characterized in tiiat the layer (109') comprises polysiHcon or porous silicon. 24. A method according to any one of die claims 12-23, characterized in that the layer (109') comprises a silicide.

Inventors: SJOEDIN HAAKAN, SOEDERBAERG ANDERS, SJOEDIN, HAAKAN, SOEDERBAERG, ANDERS
Applicants: ERICSSON TELEFON AB L M, TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
Application year: 1998
Main classification: H01L29
IPC codes: H01L21, H01L27, H01L29