DRIVING DEVICE FOR THREE-PHASE BRUSHLESS MOTOR

Abstract: A driving device for a three-phase brushless motor offers stable rotation characteristics even in case of polarity inversion resulting from braking applied, noise appearing, or other factors arising during rotation of the motor. The driving device has a comparator circuit for comparing the back electromotive forces appearing in the motor individually with the common-terminal voltage to output square-wave signals, a synthesizing circuit for producing drive signals, a circuit for producing from the square-wave signals a speed signal and then shifting the phase thereof to produce a phase signal, and a current supply circuit for supplying drive currents to the motor in accordance with the drive signals and the phase signal. The driving device further has a selector circuit for feeding a select signal back to the gate circuits provided in the stage subsequent to the comparator to perform masking.

Description: Technical field The present invention relates to a driving device for a three-phase brushless motor used to rotate a head in, for example, a portable MD (MiniDisk) apparatus or a VCR (videocassette recorder). Background art In a conventional driving device for a three-phase brushless motor, the back electromotive forces V U , V V , and V W appearing in the coils of the motor are individually compared with the common-terminal voltage V N of the coils by a comparator to obtain three-phase square-wave signals P U , P V , and P W , which are then directly synthesized together to produce a speed signal (hereafter referred to as an "FG (frequency generator) signal") and drive signals D UU , D UL , D VU , D VL , D WU , and D WL . The FG signal is then subjected to 30-degree phase shifting performed by a phase shifting circuit so as to be converted into a phase signal FGP. In accordance with this phase signal FGP and the above-mentioned drive signals D UU , D UL , D VU , D VL , D WU , and D WL , drive currents are supplied from a current supply circuit such as a power transistor circuit to the three-phase brushless motor. However, in this conventional driving device, as long as the motor is rotating stably, the square-wave signals P U , P V , and P W exhibit stable waveforms as shown in Fig. 6; however, as shown in Fig. 7, when irregular variations occur in the back electromotive forces V U , V V , and V W as a result of polarity inversion caused by braking applied as in the period T, or by noise appearing as indicated by reference numerals 40 and 41, or by other factors, the square-wave signals P U , P V , and P W exhibit irregular variations accordingly. Thus, the FG signal and the drive signals D UU , D UL , D VU , D VL , D WU , and D WL , which are produced from the square-wave signals P U , P V , and P W , are also affected such that the FG signal is no longer usable if left intact and that the drive signals D UU , D UL , D VU , D VL , D WU , and D WL , cause unstable rotation of the motor, making it impossible to obtain stable rotation characteristics. Note that, in Figs. 6 and 7, only the drive signals D UU and D UL are shown, and the other drive signals D VU , D VL , D WU , and D WL are omitted. EP 0 429 412 A discloses a method for controlling a multi phase brushless motor without position sensors for a rotor. The control is carried out by detecting signals being representative of the difference voltage between ends of the phase windings and the star-centre, by selecting the signal relating to a non excited phase winding, by detecting the crossing by the selected signal of a reference voltage, and by generating a logic commutation signal upon the crossing. Furthermore, these signals are masked for a sufficiently long time before restarting the circle. US 5,017,845 A discloses a brushless motor and an operating method thereof. The slope of the back electromotic force is sampled and a zero or a predetermined slope condition is searched. A masking circuit is included to prevent an unwanted commutation. JP 08-251978 A teaches that when a masking means masks a signal obtained from the counter electromotive forces, noise can be eliminated therefrom at the time of conduction. However, the masking means masks only for a predetermined period immediately after a level-change-point. In JP 08-033382 A voltage waveforms u, v, w and output signals from a mask-signal generator are input to a counter-electromotive-force detector. By this arrangement, since only the signal of counter-electromotive force according to the rotation of the motor can be detected, the driving current which drives the driving calls can be changed over smoothly. The masking is not designed for preventing noise from disrupting control of motor coils. In JP 08-182379 A masking signals are produced to mask signals generated only when an output current is cut off. Disclosure of the invention An object of the present invention is to provide a driving device for a three-phase brushless motor that offers stable rotation characteristics by preventing an FG signal and drive signals from being affected by polarity inversion resulting from braking applied, noise appearing, or other factors arising during rotation of the motor. This and other objects of the present invention are achieved by a three-phase brushless motor device according to claim 1. The dependent claims treat further developments of the present invention. Brief description of drawings Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of the gate circuits and the selector circuit employed therein, Fig. 3 is a waveform diagram of the signals observed at various points therein, Fig. 4 is a diagram showing the configuration of the comparator circuit employed in the device shown in Fig. 1, and Fig. 5 is a circuit diagram showing a part of the power transistor circuit employed in the device shown in Fig. 1. Fig. 6 is a waveform diagram of the signals observed at various points in a conventional driving device, and Fig. 7 is a waveform diagram illustrating how signals are affected by braking and noise therein. Best mode for carrying out the invention Hereinafter, an embodiment of the present invention will be described with reference to Figs. 1 to 5. Fig. 1 is a block diagram showing the configuration of this embodiment. A driving device 11 drives a three-phase brushless motor 10 by supplying it with drive currents I OU , I OV , and I OW . The driving device is formed, for example, as an IC (integrated circuit). The motor 10 is provided with coils 10A, 10B, and 10C for the U, V, and W phases, respectively. These Coils 10A, 10B, and 10C are arranged at such intervals that their phases differ by 120 degrees from one another. The back electromotive forces V U , V V , and V W appearing in the coils 10A, 10B, and 10C, respectively, are, together with the common-terminal voltage V N , fed to the driving device 11 so as to be individually subjected to comparison performed by comparators in a comparator circuit 1. The comparator circuit 1 outputs, as the results of comparison, square-wave signals P U , P V , and P W . As shown in Fig. 4, the comparator circuit 1 is composed of three comparators 1a, 1b, and 1c. The square-wave signals P U , P V , and P W are then subjected to passage control performed by gate circuits 2, 3, and 4, and are thereby output as inverted signals M U , M V , and M W . Next, in a drive waveform synthesizing circuit 5, the signals M U , M V , and M W are synthesized together to produce drive signals D UU , D UL , D VU , D VL , D WU , and D WL . For example, the signal D UU is so synthesized as to rise at a rising edge of the signal M U and fall at a rising edge of the signal M V . The other signals D UL , D VU , D VL , D WU , and D WL are synthesized in a similar manner from the signals M U , M V , and M W . The signals D UU , D VU , and D WU differ in phase by 120 degrees from one another. Similarly, the signals D UL , D VL , and D WL differ in phase by 120 degrees from one another. In an FG circuit 7, the exclusive-OR value of the signals M U , M V , and M W is calculated by means of an exclusive-OR gate, and then the NOT value of the thus calculated value is calculated to produce an FG signal (described later). Then, in a phase shifting circuit 8, the FG signal is subjected to 30-degree phase shifting so as to be formed into a phase signal FGP. The phase shifting circuit 8 is composed of, for example, a delay circuit. In a power transistor circuit 6, power transistors are turned on and off in accordance with the drive signals D UU , D UL , D VU , D VL , D WU , and D WL and the phase signal FGP, and thereby drive currents I OU , I OV , and I OW having a regular cycle are produced. The drive currents I OU , I OV , and I OW are supplied to the motor coils 10A, 10B, and 10C, respectively. The power transistor circuit 6 serves as a current supply circuit. For example, to produce the drive signal I OU , a pnp-type transistor Q1 and an npn-type transistor Q2 are connected together as shown in Fig. 5 so that, when the signal D UU is at a high level, the transistor Q1 is turned on to cause a current to flow from the direct-current supplied voltage Vcc through the transistor Q1 to the coil 10A and, when D UL is at a high level, the transistor Q2 is turned on to cause a current to flow from the coil 10A to ground. Note however that, in the power transistor circuit 6, the phase signal FGP is used as a timing signal for switching the drive signal I OU , and therefore the drive signal I OU shows a 30-degree phase difference relative to the level shifts in the drive signals D UU and D UL . The drive currents I OV and I OW are output in a similar manner. The thus obtained drive currents I OU , I OV , and I OW differ in phase by 120 degrees from one another. In a selector circuit 9, as will be described later, the drive signals D UU , D UL , D VU , D VL , D WU , and D WL are switched in accordance with whether the FGP signal is at a high level or at a low level to produce select signals FBU1, FBU2, FBV1, FBV2, FBW1, and FBW2. The select signals FBU1, FBU2, FBV1, FBV2, FBW1, and FBW2 are fed back to the gate circuits 2, 3, and 4, where they are used to control passage of the square-wave signals P U , P V , and P W . The gate circuits 2, 3, and 4 and the selector circuit 9 together constitute what will hereafter be referred to as the masking circuit. The comparator circuit 1, the gate circuits 2, 3, and 4, the drive waveform synthesizing circuit 5, the FG circuit 7, the phase shifting circuit 8, and the selector circuit 9 together constitute a passage control means. The detailed configuration of the masking circuit is shown in Fig. 2. The phase signal FGP fed to the selector circuit 9 is subjected to level inversion by a NOT gate (inverter) 9M. The drive signal D UL and the signal output from the NOT gate 9M are fed to a NAND gate 9A. The drive signal D WU and the phase signal FGP are fed to a NAND gate 9B. The drive signal D VL and the signal output from the NOT gate 9M are fed to a NAND gate 9C. The drive signals D UU and the phase signal FGP are fed to a NAND gate 9D. The drive signal D WL and the signal output from the NOT gate 9M are fed to a NAND gate 9E. The drive signal D VU and the phase signal FGP are fed to a NAND gate 9F. An AND gate 9G calculates the AND value of the signals output from the NAND gates 9A and 9F, and thereby outputs the signal FBV2. An AND gate 9H calculates the AND value of the signals output from the NAND gates 9A and 9B, and thereby outputs the signal FBU1. An AND gate 9I calculates the AND value of the signals output from the NAND gates 9B and 9C, and thereby outputs the signal FBW2. An AND gate 9J calculates the AND value of the signals output from the NAND gates 9C and 9D, and thereby outputs the signal FBV1. An AND gate 9K calculates the AND value of the signals output from the NAND gates 9D and 9E, and thereby outputs the signal FBU2. An AND gate 9L calculates the AND value of the signals output from the NAND gates 9E and 9F, and thereby outputs the signal FBW1. In the gate circuit 2, a NOT gate 2A inverts the level of the square-wave signal P U . Then, a NAND gate 2B calculates the NAND value of the signal output from the NOT gate 2A and the signal FBU1 fed from the selector circuit 9. Then, a NAND gate 2C calculates the NAND value of the signal output from the NAND gate 2B and the signal FBU2. Thus, the gate circuit 2 outputs the signal M U . In the gate circuit 3, a NOT gate 3A inverts the level of the square-wave signal P V . Then, a NAND gate 3B calculates the NAND value of the signal output from the NOT gate 3A and the select signal FBV1. Then, a NAND gate 3C calculates the NAND value of the signal output from the NAND gate 3B and the signal FBV2. Thus, the gate circuit 3 outputs the signal M V . In the gate circuit 4, a NOT gate 4A inverts the level of the square-wave signal P W . Then, a NAND gate 4B calculates the NAND value of the signal output from the NOT gate 4A and the select signal FBW1. Then, a NAND gate 4C calculates the NAND value of the signal output from the NAND gate 4B and the signal FBW2. Thus, the gate circuit 4 outputs the signal M W . Now, how driving of the motor 10 (see Fig. 1) is achieved will be described with reference to Fig. 3, which shows the waveforms of the signals observed at various points in the driving device when the motor 10 rotates. In the motor coils 10A, 10B, and 10C, the back electromotive forces V U , V V , and V W are induced to appear repeatedly with a regular cycle by the drive currents I OU , I OV , and I OW . Here, the back electromotive forces V U , V V , and V W differ in phase by 120 degrees from one another. On the other hand, the common-terminal voltage V N varies with one third of the cycle of the back electromotive forces V U , V V , and V W as long as the motor 10 is rotating normally. As described previously, in the comparator circuit 1, the back electromotive forces V U , V V , and V W are individually compared with the common-terminal voltage V N to obtain three-phase square-wave signals P U , P V , and P W . If inversion occurs in the waveforms of the back electromotive forces V U , V V , and V W as a result of phase inversion as caused by braking as indicated by reference numerals 21 and 22, irregular variations occur in the square-wave signals P U , P V , and P W as indicated by reference numerals 23 and 24. If these square-wave signals P U , P V , and P W are fed directly to the drive waveform synthesizing circuit 5 as in the conventional driving device described earlier, it is impossible to drive the motor 10 normally. By contrast, in this embodiment, where the gate circuits 2, 3, and 4 are inserted in the stage subsequent to the comparator circuit 1 to perform masking on the square-wave signals P U , P V , and P W and thereby form them into the signals M U , M V , and M W , it is possible to drive the motor 10 normally. Here, when the phase signal FGP is at a high level, the selector circuit 9 (see Fig. 2) feeds D WU as the signal FBU1 to the NAND gate 2B, and feeds D UU as the signal FBU2 to the NAND gate 2C. By contrast, when the phase signal FGP is at a low level, the selector circuit 9 feeds D UL to the NAND gate 2B, and feeds D WL to the NAND gate 2C. The signals FBU1 and FBU2 have the following relationship. When the signal FBU1 is at a low level, the signal FBU2 is at a high level. When the signal FBU2 is at a low level, the signal FBU1 is at a high level. The signals FBU1 and FBU2 are never at a low level simultaneously. Thus, when the signal FBU1 is at a low level, the signal M U is invariably at a low level irrespective of the level of the square-wave signal P U . By contrast, when the signal FBU2 is at a low level, the signal M U is invariably at a high level irrespective of the level of the square-wave signal P U . That is, a variation in the square-wave signal P U is passed along to the signal M U only when the signals FBU1 and FBU2 are both at a high level; otherwise, any variation in the square-wave signal P U , as caused by noise or the like, is masked by the gate circuit 2, and thus is not passed along to the signal M U . The periods in which a variation in the square-wave signal P U is passed along through the gate circuit 2 to the signal M U are, for example, as indicated by hatching 30 and 31. These periods each last for one sixth of the cycle of the signal M U , and are repeated so as to include a level-shift point of the signal P U each. On the other hand, in the periods between those periods, the signal M U is kept at the level at which it is set after a level-shift point of the signal P U . Similarly, the gate circuit 3 controls passage of the square-wave signal P V in accordance with the signals FBV1 and FBV2 output from the selector circuit 9 in such a way that a variation in the square-wave signal P V is passed along to the signal M V only when the signals FBV1 and FBV2 are both at a high level. Moreover, the gate circuit 4 controls passage of the square-wave signal P W in accordance with the signals FBW1 and FBW2 output from the selector circuit 9 in such a way that a variation in the square-wave signal P W is passed along to the signal M W only when the signals FBW1 and FBW2 are both at a high level. The periods in which a variation in the square-wave signals P V and P W is passed along through the gate circuits 3 and 4 to the signal M V and M W , respectively, are also indicated by hatching in Fig. 3. In this way, for each of the signals M U , M V , and M W , the periods indicated by hatching occur with one third of the cycle of the back electromotive forces in such a way as not to overlap among the signals M U , M V , and M W . Now, for example, suppose that, at the moment when the drive signal D UL causes a transistor provided within the power transistor circuit 6 (see Fig. 1) to be turned from an on state to an off state, pulse-like noise 25 appears in the back electromotive force V V , and accordingly noise 26 appears in the signal P V . Even in this case, no noise appears in the signal M V because it has been subjected to masking as described above. Therefore, the noise 25 does not affect generation of the FG signal or the drive signals D UU , D UL , D VU , D VL , D WU , and D WL , and thus does not cause unstable rotation of the motor 10 (see Fig. 1). The power transistors provided within the power transistor circuit 6 operate in accordance with the phase signal FGP and thus with a 30-degree phase difference from the drive signals D UU , D UL , D VU , D VL , D WU , and D WL , and accordingly the back electromotive forces V U , V V , and V W are induced with a 30-degree phase difference from the drive signals D UU , D UL , D VU , D VL , D WU , and D WL . Similarly, noise appears also at the moment when other transistors than those mentioned just above are turned from an on state to an off state; however, masking prevents also such noise from being passed along to the signals M U , M V , and M W . Moreover, even if noise as indicated by reference numeral 27 appears in the back electromotive force V W as a result of randomly occurring external disturbance, the noise is passed along to the signal P W , but is not passed along to the signal M W except in the periods in which the signals FBW1 and FBW2 are both at a high level (i.e. the periods indicated by hatching in the figure). Thus, it is also possible to prevent external disturbance from affecting the drive signals D UU , D UL , D VU , D VL , D WU , and D WL . Note that the periods indicated by hatching in Fig. 3 include time points at which the values of the voltages of the back electromotive forces V U , V V , and V W cross the value of the common-terminal voltage V N . By detecting such time points, the rotor position of the motor 10 is recognized to produce the FG signal and the drive signals D UU , D UL , D VU , D VL , D WU , and D WL . Therefore, in these periods, variations in the individual three-phase square-wave signals P U , P V , and P W need to be passed along to the signals M U , M V , and M W , and thus no masking is performed. In these periods indicated by hatching, the square-wave signals P U , P V , and P W turn from a high level to a low level or from a low level to a high level. As described above, in this embodiment, the masking circuits 2 to 4 and 9 mask disturbances in waveforms caused by noise or the like, so that the signals M U , M V; and M W , which have been subjected to masking, are fed to the drive waveform synthesizing circuit 5 and the FG circuit 7. This makes it possible to obtain stable waveforms in the FG signal and the drive signals D UU , D UL , D VU , D VL , D WU , and D WL without using an external sensor, and thereby achieve stable rotation of the motor 10. The power transistor circuit 6 may be provided separately from the IC 11. This makes it possible to drive a larger-sized motor 10. The driving device of this embodiment can be used also to achieve stable rotation with a motor that is so configured as to obtain an FG signal by the use of an external sensor such as a hole sensor. Industrial applicability As described heretofore, according to the present invention, masking is performed by a selector circuit and gate circuits, and therefore it is possible to prevent braking or noise from making the rotation of a motor unstable, and thereby enhance rotation characteristics. Moreover, a stable FG signal can be produced without using an external sensor, and therefore it is possible to reduce mount surface area, and thereby reduce costs. Thus, a driving device according to the present invention can be suitably used as a driving device for a three-phase brushless motor for use in a VCR or portable MD apparatus.

Claims: A three-phase brushless motor driving device (11) for supplying a three-phase brushless motor (10) with three-phase drive currents (I OU, I OV , I OW ) that differ in phase by 120 degrees from one another, wherein passage control means is provided that compares back electromotive forces (V U , V V , V W ) appearing in three coils (10A, 10B, 10C) provided one for each phase (U, V, W) in the three-phase brushless motor (10) individually with a common-terminal voltage (V N ) of the three coils (10A, 10B, 10C) and includes a selector circuit (9) and gate circuits (2, 3, 4), the selector circuit (9), based on drive signals (D UU , D UL , D VU , D VL , D WU , D WL ) for turning on and off the three-phase drive currents (I OU , I OV , I OW ) and a phase signal (FGP) produced from a speed signal (FG) by performing phase shift, generates, for each of the three phases (U, V, W), two select signals (FB U1 , FB U2 , FB V1 , FB V2 , FB W1 , FB W2 ) both of which are kept at a high level simultaneously during a predetermined period including a zero-cross point of each back electromotive force (Vu, Vv, Vw) on both rising and trailing edges thereof and any one of which is kept at a high level while another is kept at a low level outside the predetermined period that corresponds to a half cycle of the phase signal (FGP), the gate circuits (2, 3, 4) mask the comparison outputs individually in such a way that each of the comparison outputs is, in the predetermined period including a level-shift point thereof, permitted to pass through the gate circuit (2, 3,4) intact when the gate circuit (2,3, 4) receives two select signals (FB U1 , FB U2 , FB V1 , FB V2 , FB W1 , FB W2 ) that are high from the selector circuit (9) and is, in a period between one such predetermined period and a next such predetermined period, kept at a level at which it is set after the level-shift point when the gate circuit (2, 3, 4) receives two select signals (FB U1 , FB U2 , FB V1 , FB V2 , FB W1 , FB W2 ) of which one is at a high level and another is at a low level from the selector circuit (9), and wherein the drive currents (I OU , I OV , I OW ) are produced by current supply means (6) in accordance with signals resulting from passage control. The three-phase brushless motor driving device (11) as claimed in claim 1, further comprising: a drive waveform synthesizing circuit (5) for synthesizing together each of the comparison outputs fed from the gate circuits (2, 3, 4) to produce the drive signals (D UU , D UL , D VU , D VL, D WU , D WL ); an FG circuit (7) for producing the speed signal (FG) from each of the comparison outputs fed from the gate circuits (2, 3, 4); and a phase shifting circuit (8) for producing from the speed signal (FG) the phase signal (FGP) having a phase shifted by 30 degrees relative to the speed signal (FG), wherein the selector circuit (9) feeds the select signals (FB U1 , FB U2 , FB V1 , FB V2 , FB W1 , FB W2 ) back to the gate circuits (2, 3, 4) in accordance with the drive signals signals (D UU , D UL , D VU , D VL , D WU , D WL ) and the phase signal (FGP), and wherein the current supply means (6) supplies the drive currents (I OU , I OV , I OW ) to the three-phase brushless motor (10) in accordance with the drive signals signals (D UU , D UL , D VU , D VL , D WU , D WL ) and the phase signal (FGP). The three-phase brushless motor driving device (11) as claimed in claim 2, wherein the comparison outputs fed from the gate circuits (2, 3, 4) turn from a high level to a low level or from a low level to a high level individually in the predetermined level. The three-phase brushless motor driving device (11) as claimed in claim 2 or 3, wherein the driving device is formed as an integrated circuit.

Inventors: HASHIMURA TOMOHIDE, HASHIMURA, TOMOHIDE, HASHIMURA, Tomohide, Rohm Co., Ltd.
Applicants: ROHM CO LTD, ROHM CO., LTD.
Application year: 1998
Main classification: H02P6
IPC codes: H02P6