METHOD AND APPARATUS FOR INSERTING/EXTRACTING SETS OF SIGNALS INTO/FROM A SIGNAL STREAM

Abstract: A method and apparatus in an optical network unit for identifying signals for a set of communication devices in a signal stream having signals for a number of different sets of communication devices. Each optical network unit ONU (335) includes a common control unit CCU (350) which uses a content addressable memory CAM for identifying sets of signals that need to be extracted from the signal stream and transmitted to a first set (392, 394, 396, 398) of communication devices; and identifying time periods for inserting sets of signals from a first set of communication devices into a signal stream.

Description: METHOD AND APPARATUS FOR INSERTING/EXTRACTING SETS OF SIGNALS INTO/FROM A SIGNAL STREAM RESERVATION OF COPYRIGHT A portion of the disclosure of this patent document contains material to which a claim of copyright protection is made. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it 5 appears in the Patent and Trademark Office patent file or records, but reserves all other rights whatsoever. BACKGROUND OF THE INVENTION To date, several telecommunication systems have been proposed for carrying signals for different types of communication applications in the same signal stream. 10 Some of these systems integrate signals for narrowband applications (e.g., telephony signals) with signals for broadband applications (e.g., video and data signals) in the signal streams that they transmit. For systems that transmit integrated signal streams in a cell based format, the signal stream can contain a mixture of cells having asynchronous application signals (i.e., signals for asynchronous communication 15 applications) and cells having isochronous application signals (i.e., signals for isochronous applications). Integrated telecommunication systems, that carry different types of signals for different types of applications, have to properly multiplex and demultiplex the different signals in the signal stream. For instance, some integrated 20 broadband/narrowband systems have to separate the isochronous application signals (e.g., such as telephony signals) from the asynchronous application signals (e.g., video and data signals). A simple prior art method for extracting isochronous telephony signals reads all of the bytes in a received frame into a memory and subsequently determines the isochronous bytes. Figures 1 and 2 set forth one implementation of this prior art technique. As shown in Figure 1, the prior art includes a memory 105 which sequentially stores every byte of a received frame in contiguous byte-wide memory locations. This prior art implementation also includes a table of pointers 110 with a pointer for each memory location. Each pointer for a memory location that stores telephony bytes points to a specific twisted pair 210 of a specific telephone-interface-unit (TIU) card 205, as set forth in Figure 2. Hence, once the memory completely stores all bytes of a received frame, the isochronous telephony bytes in the memory are routed to the appropriate telephone lines by traversing the table of pointers. This prior art technique is inefficient and memory-intensive. For instance, a 155 Mb/s SDH-like data stream having ATM and TDM cells could have 2,340 DS0 bytes. Storing this many data bytes in the memory to extract a relatively few TDM bytes is highly inefficient and memory-intensive. Consequently, there is a need in the art for method and apparatus that efficiently demultiplex signals for different applications from a signal stream. There is also a need for method and apparatus that efficiently multiplex signals for different applications into a signal stream. More generally, there is a need for method and apparatus that identify signals for a set of communication devices in a signal stream which has signals for a number of different sets of communication devices. SUMMARY OF THE INVENTION The invention provides method and apparatus for identifying signals for a set of communication devices in a signal stream having signals for a number of different sets of communication devices. Some embodiments of the invention are methods and devices for extracting signals for a first set of communication devices from a signal stream having signals for a number of different sets of communication devices. Other embodiments of the invention are methods and devices for inserting into a signal stream signals from a first set of communication devices. Yet other embodiments of the invention are time division multiplexing and demultiplexing methods and apparatuses that use a content addressable memory to identify sets of signals for a particular set of communication devices. In addition, some embodiment of the invention are used in fiber optic telecommunication networks. These embodiments include an optical network unit that receives an integrated signal stream having signals for different types of applications. The optical network unit includes a content addressable memory that stores locations in the received signal stream of signals for a first type of communication application. BRIEF DESCRIPTION OF THE DRAWINGS The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are explained by reference to the following figures. Figure 1 presents a memory device and a table of pointers used in one prior art time division demultiplexing technique. Figure 2 presents four TIU cards used in conjunction with the memory device and table of pointers of Figure 1. Figure 3 presents a fiber-to-the-curb network in which the invention can be implemented. Figure 4 presents one example of a SDH-like frame used in some embodiments of the invention. Figure 5 presents one example of a telephony cell used in some embodiments of the invention. Figure 6 presents a common control unit for use in the network of Figure 3. Figure 7 presents one embodiment of the invention. Figure 8 presents one example of a content addressable memory used in some embodiments of the invention. Figure 9 presents one example of a memory interface unit used in some embodiments of the invention. Figure 10 illustrates one manner for forwarding extracted telephony data and control bytes to four TIUs in the network of Figure 3. Figure 11 presents another embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION The invention provides method and apparatus for identifying signals for a set of communication devices in a signal stream which has signals for a number of different sets of communication devices. In a communication system, a communication device is a device that transmits and/or receives signals through the communication system. Examples of such communication devices include computers (such as network computers, personal computers, workstations, servers, etc.), television set-top boxes, premises interface device, and telephones. One or more communication devices form each set of communication devices. A set of communication devices can include similar communication devices (e.g., a set of telephony communication devices can use similar telephony equipment). A set of communication devices can be defined by a number of communication devices that utilize a similar communication medium (e.g., utilize twisted pairs or co-axial cables) to connect to the communication system. In addition, a set of communication devices can be defined by a number of communication devices that utilize similar communication-medium terminating devices (e.g., utilize similar line cards, adapter cards, modems, etc.). In the following description, numerous details are set forth for purpose of explanation. However, one of ordinary skill in the art would realize that the invention may be practiced without the use of these specific details. In other instances, well- known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail. Several embodiments of the invention are implemented in fiber-to-the-curb (FTTC) networks. One example of such a network is presented in Figure 3. As set forth in this figure, the FTTC network 300 connects one or more communication devices at one or more network subscriber site 305 to one or more communication networks, such as a public switched telecommunications network (PSTN) 310, an asynchronous transfer mode (ATM) network 315, or other communication networks. Each network subscriber site 305 can be residential or commercial subscriber sites. The FTTC network 300 transmits signal streams between the subscriber sites and the PSTN 310, the ATM network 315, or other networks (e.g., individual, private, or non-switched public networks). The signal streams contain signals transmitted to, or received from, a number of sets of communication devices. For one embodiment of the invention, the FTTC network transmits signals to and from telephony communication devices (i.e., telephony application signals) and signals to and from non-telephony communication devices (i.e., non-telephony application signals). For alternative embodiments of the invention, signals for different types of communication devices can be transmitted through the communications network. The FTTC network 300 includes a host digital terminal (HDT) 320, element management system (EMS) 325, a number of fiber optic cables 330, and a number of optical network units (ONUs) 335. As shown in Figure 3, the HDT couples to the PSTN, the ATM network, and/or other networks. For one embodiment of the invention, the PSTN-HDT interface 340 follows the specification adopted by one of the standards bodies, such as the Bellcore specification TR-TSY-000008, TR-NWT- 000057 or TR-NWT-000303. The physical interface to the PSTN can be twisted pairs carrying DS1 signals, or fiber optic cables carrying OC-3 optical signals. The ATM network-HDT interface 345 can be realized using an optical interface (such as OC-3, OC-12c, etc.). For one embodiment of the invention, the HDT 320 has two optical broadcast ports, which can only receive signals carrying ATM cells, and one optical interactive port which can receive and transmit signals. The HDT receives downstream signals from the PSTN, the ATM network, or other networks, and routes these signals downstream to the network subscriber sites. It also receives upstream signals from the network subscriber sites, and routes these signals upstream to the PSTN, the ATM network, or other networks. On the downstream side of the network, the HDT serves a multiplexor which (1) controls access of the received downstream signals (i.e., the signals it receives from the PSTN, ATM, or other networks) to the transmission media, and (2) transmits the received signals to the appropriate ONUs 335 via the appropriate fiber optic cables 330. Conversely, on the upstream side of the network, the HDT serves as a demultiplexer which (1) parses the received upstream signals (i.e., the signals received from the ONUs) into signal streams for the PSTN, ATM, or other networks, and (2) supplies these signal streams to the appropriate network. The HDT also re-formats the downstream and upstream signals, before forwarding them to their destinations. As further described below, the HDT performs the following formatting operations: combining isochronous and asynchronous signals into frames, parsing integrated frames into individual signal streams, adjusting signal rates, and converting of electrical signals to and from optical signals. One of ordinary skill in the art would realize that, in alternative embodiments of the invention, the HDT does not perform all of these formatting operations, or performs additional operations. In the FTTC network set forth in Figure 3, the HDT combines (i.e., maps) the received downstream signals into frames containing a mixture of cells having asynchronous application signals (such as data and video signals) and cells having isochronous application signals (such as telephony signals). The HDT transmits these frames to the ONUs at a prespecified rate (e.g., once every 125 μs). The HDT also parses the received upstream frames into individual bytes supplied to the PSTN, ATM, or other networks. Figure 4 presents one example of frames transmitted across the fiber optic cables 330. Each frame shown in this figure is a SDH-like frame which includes overhead and payload envelopes. The payload envelope includes 41 cells of asynchronous and isochronous information. Each cell has 57 bytes. Figure 5 presents one example of an isochronous, telephony cell. As shown in this figure, each cell includes three reserved bytes (R), and six groups of DSO bytes. Figure 5 presents each group as eight DSO data bytes following one signaling byte (S). - The signaling byte contains the status and control signals (e.g., on/off hook, ring, etc.) for the eight DSO bytes. Alternatively, each group can include nine clear DSOs bytes containing a mix of information and control signals. The HDT also adjusts the signal rate of the data it receives. For instance, for some embodiments of the invention, the HDT 320 converts the signals it receives from the PSTN 310 at a DSl-rate to signals at a DSO-rate; it then transmits these signals to the ONUs in the SDH-like frames. On the upstream side, the HDT performs the inverse signal rate transformation operation. The HDT also converts the electrical representation of the digital signals into an optical representation, and visa versa. As shown in Figure 3, the HDT couples to the EMS 325. The EMS is used to provision services and equipment on the FTTC network (e.g., allocate twisted pairs off the TIUs), in the central office where the HDT 320 is located, in the field, or in the residences. The EMS is software based and can run on a personal computer in which case it will support one HDT and the associated access network equipment connected to it. Alternatively, it can run on a workstation in which case it will support multiple HDTs and access networks. The fiber optic cables 330 communicatively couple the HDT to a number of ONUs 335 located in a number of serviced areas. Some embodiments of the invention use bi-directional, single-mode fiber lines and a dual wavelength transmission scheme to communicate between the ONUs and the HDT. In addition, some embodiments of the invention use sixty four optical fiber cables to connect the HDT to sixty four ONUs. As shown in Figure 3, each ONU includes a common control unit (CCU) 350, four telephone interface units (TIU) 355, and eight broadband interface units (BIU) 360. The CCU controls the operation of the ONU. In particular, the CCU performs similar formatting operations as those performed by the HDT. For instance, the CCU (1) parses the received downstream signals (i.e., the frames it receives from the HDT) into telephony application signal streams and non- telephony application signal streams, and (2) supplies the telephony application signal streams to the appropriate TIU 355. The CCU also combines the signal streams that it receives from the TIUs 355 and BIUs 360 into SDH-like frames (such as the frames discussed above with respect to Figure 4), which it then transmits to the HDT via fiber optic cable 330. Different embodiments of the invention can be employed in the CCU, in order to allow the CCU to perform the above-described parsing (i.e., demultiplexing) and combining (i.e., multiplexing) operations. Two such embodiments will be described below by reference to Figures 7 and 11. Figure 6 presents one example of the CCU 350. As shown in this figure, the CCU includes a bi-directional (BIDI) optical converter 605, a framer 610, a TIU interface (TIUI) 615, a BIU interface (BIUI) 620, and a microprocessor 625. On the downstream side, the optical converter 605 converts optical signals, that it receives via a fiber optic cable 330, into a serial, electrical signal stream. The framer 610 then receives this bit-wide electrical signal stream and converts it into a byte- wide signal stream. On the upstream side, the optical converter receives bit-wide, electrical signals from the framer, and converts these electrical signals into optical signals for transmission via the fiber optic cable 330. The framer also scans the incoming signal stream in order to determine the frame boundary information used to determine the location of payload and overhead bytes. Once the framer determines the frame boundary, it generates a frame synch signal which indicates the start of each frame. As described below, this frame synch signal is used by a number of the circuits of the CCU. The framer communicatively couples to the TIUI 615, in order to transmit and receive signals from the TIUI. Some embodiments of the invention are implemented in the TIUI, in order to allow the TIUI to parse the telephony application signals from the downstream signal stream, and to combine the telephony application signals into the upstream signal stream. Two such embodiments will be described below by reference to Figures 7 and 11. The framer also transmits signals to and receives signals from the BIUI. The BIUI performs administrative functions (e.g., parity check and overhead addition functions). On the downstream side, the BIUI forwards the signals it receives from the framer to the BIUs 360. Each individual BIU then extracts the portion of the received signals that are addressed to it; the BIU forwards the extracted signals to a network subscriber site 305. On the upstream side, the BIUI 620 acts as an arbitrator for the BIUs. In this capacity, the BIUI allocates different portions of each frame's payload to different BIU's. The microprocessor 625 of the CCU 350 is used to program various components of the CCU. For instance, as further described below, the microprocessor is used to program various components of the TIUI. Through this programming, the TIUI can store the location of telephony bytes in the received or transmitted signal stream. As shown in Figure 3, each ONU 335 includes four TIUs 355 coupled to the TIUI 615 through a backplane interconnect. Each TIU 355 connects to six twisted pairs 365, which thereby allow each ONU to service up to twenty four network subscriber sites. For alternative embodiments of the invention, the FTTC network 300 utilizes ONUs that have different number of TIUs and/or different number of twisted pairs for each TIU. When a TIU receives a signal stream from the CCU, it converts the signal stream into a signal stream for a narrowband service (such as plain old telephony signals (POTS), coin, ISDN, etc.). For instance, the TIU can generate analog POTS which it transmits to network subscriber site 305 via a twisted pair 365. At the network subscriber site 305, a network interface device (NID) 370 serves as an interface and demarcation point between the twisted pair 365 and subscriber-site twisted pair 375 coupled to telephone 380. The NID provides high-voltage protection. In addition, through the NID 370 and twisted pairs 365 and 375, each TIU 355 receives analog signals from the network subscriber site. It then converts these analog signals into digital signals which it supplies to the CCU. Each ONU 335 also includes eight BIUs 360 coupled to the CCU 350 through the backplane interconnect. Each BIU 360 connects to two co-axial cables. Alternative number of BIUs and/or co-axial cables could also be used in the ONU. As described above, each BIU communicatively couples to the BIUI 620 of the CCU 350. Through this coupling, the BIU receives signals from the CCU. The BIU includes a filter which decodes a portion of the overhead bytes of each received cell to determine if the received cell is addressed to its BIU. If so, the filter also determines the addressed co-axial cable of the BIU. The filter then reformats the received cell and stores it in a FIFO queue. As the contents of the FIFO are read out, the BIU modulates the read-out signals onto an RF carrier and transmits the data via the addressed co-axial cable to a splitter 385 at the network subscriber site 305. Subscriber-site coaxial cables 390 couple the splitter to a number of communication devices at the network subscriber site. These communication devices include a television (TV) 392 with a television set-top 394, computer with a network interface card (NIC) 396, and a premises interface device (PID) 398 connected to a telephone. Each of these devices parses and decodes the received reformatted cells in order to obtain video, data, and voice signals. In particular, each communication device requires an interface sub-system which provides for the conversion of the signal from the format on the subscriber-site coaxial cable to the service interface required by the device. The PID 398 extracts the voice signals carried on the subscriber-site coaxial cable 390 and generates a telephone signal compatible with the telephone. Similarly, the television set-top 394 converts digital video signals to analog signals compatible with the TV 392. The NIC card generates a computer compatible signal. Through the subscriber-site coaxial cables 390, the splitter 385, and the coaxial cable 367, the BIU also receives broadband signals for upstream transmission through the FTTC network 300. The BIU demodulates the signals that it receives and combines the resulting components of the broadband signals into a unified broadband signal stream, which it relays to the BIUI 620. One of ordinary skill in the art would understand that the invention can be implemented in other FTTC networks. For instance, some embodiments of the invention can be implemented in the networks disclosed in United States Application No. , entitled "Unified Access Platform," filed on August 4, 1997, concurrently with the present application, having Thomas R. Eames as the inventor, and having the express mail label number EH385539499US. The disclosure of this application is incorporated in the present application by reference. Alternatively, one of ordinary skill in the art would understand that the invention can be implemented in alternative networks. One embodiment of the invention that is implemented in the FTTC network 300 extracts signals for a set of telephony communication devices from an integrated telephony/non-telephony signal stream transmitted through the FTTC network. This embodiment stores position identifying indicia (e.g., pointers) that identify the locations of telephony application signals in a received signal stream, which as mentioned above, is organized in a SDH-like frame. It then generates position identifying indicia as it receives a transmitted frame, and simultaneously compares this indicia to more than one of the stored indicia. When the generated indicia matches a stored indicia, the process extracts the telephony signal corresponding to the generated indicia from the received signal stream. This process then generates appropriate routing signals based on the matched stored location, in order to route the extracted set of signals to its set of communication devices. Figure 7 sets forth one such embodiment. This apparatus is implemented in the CCU's TIUI 615, and serves as the interface to the TIUs of the ONU 335. This interface constantly receives the SDH-like frames in byte-wide increments at the SDH- like 19.44 MHz. The interface includes a byte counter 705, a content addressable memory 710, a memory interface unit 715, swing data random access memories 720, a control random access memory (RAM) 725, a downstream TIU interface 730, a table of pointers 735, a pointer RAM control 740, a bit counter (not shown), a microprocessor interface unit 745, and a downstream synchronizing unit (not shown). The counter 705 and content addressable memory (CAM) 710 in conjunction act to identify the telephony application signals in the downstream SDH-like frames forwarded to the memory interface unit 715. Specifically, the counter receives frame synchronizing signal (generated by the framer 610) to maintain its alignment to each frame. The counter also receives a synchronizing signal from the downstream synchronizer (not shown). This synchronizing signal maintains the counters in the SDH-domain and the counters in the telephony-domain in synch, so that the interface units 715 and 730 in these domains do not simultaneously access the memories 720 and 725. The counter also receives the 19.44 MHz SDH-byte clock to generate three count values that are synchronous with the signals received in byte-wide sets at this frequency. In other words, the counter is a byte counter which generates sets of count values. Each set of count values serves as a pointer that specifies the location of a byte within a frame received by the memory interface unit 715. Each pointer is input to the CAM to determine if the received byte corresponding to the pointer is a telephony application byte. As mentioned above by reference to Figures 4 and 5, some embodiments of the invention are designed to multiplex and demultiplex SDH-like frames with a payload of 41 cells of telephony application signals (e.g., TDM signals) and non- telephony applications signals (e.g., ATM signals). Each telephony cell is composed of 6 groups of 9 bytes. The 9 bytes are arranged as one signaling byte followed by 8 DSO bytes. Given this cell structure, the counter generates (1) a cell count value, RxCellCnt, that specifies the cell count of the currently received byte, (2) a group count value, RxGrpCnt, that specifies the group count of the currently received byte, and (3) a DSO byte count, RxDSOCnt, that specifies the byte count of the currently received byte. In this manner, the three count values serve as pointers that uniquely identify every byte within each of the 41 potential TDM cells. The behavior of these three counts is shown below. CellCnt: n-1 | n GroupCnt: 5 | 7 | 0 | 1 | 2 DSOCount: 4|5|6|7|θ|l|8|θ|l|2|3 |5|6|7|8|θ|l|2|3 |5|6|7|8|θ|l|2|3|4|5|6| 7 I CellCnt: n I n+1 GrpCnt: | 7 | 3 | 4 | 5 I 7 | — 0- DSOCount : |2|8|θ|l|2|3 |5|6|7|8|θ|l|2|3 |5|6|7|8|θ|l|2|3|4|5|6|7|θ|l|8|θ| The DSO number 8 within each group is used as the super-frame, multiplexed signaling byte. Also, within each cell there are three reserved bytes corresponding to group 7 with a DSO count of 0, 1 or 2. As shown in Figure 7, the CAM 710 receives the generated count values (RxCellCnt, RxGrpCnt, and RxDSOCnt) and receives a signal (RxCellType) indicating the type of the received cell. A CAM is a memory device with the ability to compare any set of signals (e.g., a data word) presented to it with all of the CAM contents at once, and report the location in the CAM whose contents match the presented set of signals. In the prior art, CAMs have been used in bridges and routers to compare extracted MAC addresses with stored MAC addresses, in order to determine if received packets are addressed to LANs connected to the bridges or routers. Figure 8 presents one example of the CAM 710 that can be used in some embodiments of the invention. As shown in this figure, the CAM includes control circuitry 805, a first memory 810, a second memory 815, downstream comparators 820, and decoder 825. Although this figure presents two memories, one of ordinary skill in the art would appreciate that this presentation is simply a pictorial representation of the CAM in order to facilitate its description, and that these two memories could be part of a single memory array. Through microprocessor interface unit 745 and the control circuitry 805, the first and second memories couple to the microprocessor 625 to receive respectively data signals (i.e., position identifying indicia) and control signals (e.g., block size indicia) for storing. Specifically, through this coupling, the first memory 810 receives and stores up to thirty two position identifying indicia that identify the position of thirty two telephony-application bytes in each SDH-like frame. In some embodiments of the invention, the first memory stores thirty position identifying indicia, where each position identifying indicia is a pointer that specifies the location of a telephony-application byte within each frame received by memory interface unit. When the frames have a structure as shown in Figure 4, and the telephony cells have structures as shown in Figure 5, each stored pointer can have thirteen bits. Of these bits, six bits identify the cell value, three bits identify the group value, and four bits identify the byte value. In the second memory 815, the microprocessor stores control bits that determine the size of the blocks of signals extracted from the signal stream. In some embodiments of the invention, the second memory stores thirty two sets of control bits, so that there is one set of control bits for each pointer in the first memory. Each set of control bits includes two bits. When a received byte has its location in the received frame match one of the stored pointers in the first memory, the memory interface unit decodes the two control bits corresponding to the matched pointer in order to determine whether it needs to extract one to three bytes following the received byte in the received signal stream in addition to extracting the received byte. As mentioned above, the CAM also includes thirty-two comparators 820. Each comparator compares a particular thirteen-bit pointer stored in the first memory with the thirteen-bit output of the byte counter 705. For instance, the comparator for the nth row in the first memory array receives the bits stored in row n (Rn) from columns 0 to 12 (CO and C12), and compares these bits to the generated thirteen count bits RxCellCnt, RxGrpCnt, and RxDSOCnt. Each comparator includes thirteen X-NOR gates, with each X-NOR gate receiving one bit of the stored pointer and one bit of the generated count value. Each comparator also has an AND gate (not shown) which receives the outputs of the thirteen X-NOR gates of the comparator. The output of each AND gate then represents the output of the comparator. Hence, the thirty two comparators 820 have thirty two output lines. When a received byte's location matches a stored pointer, the pointer's comparator indicates a hit (i.e., a match) by pulling its output line high. One of ordinary skill in the art would understand that alternative CAM structures are used in alternative embodiments of the invention. As further described below, the memory interface unit 715 receives the thirty two bit output of the comparators 820. This interface unit includes a priority encoder which receives this thirty two bit output to generate a five bit output to represent the address of the row storing the matched pointer in the first memory. The row address for the matched pointer is the same as the row address for its corresponding pair of control signals in the second memory. Hence, the five bit address is supplied to the decoder 825 of the second memory. This decoder then latches and outputs the two control bits stored at the row identified by the received address signal. The memory interface unit then receives these two bits, which, as described later, direct the interface unit to extract up to three bytes that follow the received byte. The CAM also receives the CellType signal (such as RxCellType or TxCellType). This signal indicates whether the cell that is currently being received in the received frame is a telephony cell or a non-telephony cell. To generate this signal, the CCU includes a memory (not shown) with forty one registers for the forty one cells in the frame payload. Each register stores a CellType flag that indicates whether its corresponding cell is a telephony cell. By using the cell count address generated by the counter 705, the CCU sequentially reads the forty one registers to generate the CellType signal. When the cell is not a telephony cell, the value of the CellType signal powers down the comparators 820. As mentioned above, the memory interface unit 715 of Figure 7. This interface unit receives the downstream signal stream. It also receives the generated count values RxGrpCnt and RxDSOCnt, and the RxCellType, in order to synchronously operate with the CAM. It couples to the CAM 710 to receive its thirty- two bit output. Based on this output, it generates the five bit address of the matched pointer in the CAM. The interface unit then uses this address to retrieve the two control bits corresponding to the matched pointer from the CAM. Based on the two control bits, as well as the thirty two output bits of the CAM, the interface unit extracts one to four telephony bytes from the received signal stream, and generates address and control signals to store the extracted telephony bytes in data and control RAMs 725 and 730. Figure 9 presents one example of the memory interface unit 715. This embodiment includes a priority encoder 905, an OR gate 910, and a downstream (DS) state machine 915. Priority encoder 905 receives the thirty two bit output of the CAM. As the CAM does not store identical pointers, only one of the thirty two output lines should be active when a telephony signal is received. If the CAM reports multiple hits on its thirty two output lines (i.e., if more than one line is active), it is determined that the CAM was improperly programmed, and an error condition is reported through an interrupt structure or a status flag. When one of the thirty two output lines 755 are active, the priority encoder generates a five bit address based on the values of the active line. This address is sent back to the CAM in order to retrieve two control bits which are stored in the second memory at the generated row address. These two bit are then supplied to the DS state machine. The state machine also receives an enable signal 920, as well as the five-bit output of the encoder. The enable signal is the output of the OR gate 910, which receives as its input the thirty two output lines of the CAM. When one of these lines is active, the OR gate output is also active. This active signal causes the DS state machine to extract from the downstream signal stream the byte that it is receiving at that time. By decoding the two control bits, the DS state machine then determines whether it needs to extract up to three other bytes that follow the initial, extracted byte. Based on the value of the generated five bit address and the two control bits, the state machine 915 generates address and control signals to store the extracted bytes in the data and control RAMs 720 and 725. For some embodiments of the invention, the relationship between the pointers stored in the CAM and the storage locations in RAMs 720 and 725 (for storing extracted bytes whose locations in the signal stream matched the stored pointers) is hard coded. This hard coded relationship allows the downstream state machine to simply use the five bit row address 925 of the matched pointers to generate the address signals for the locations in the RAMs 720 and 725 for storing the extracted bytes. In some embodiments of the invention, the memory interface unit is designed by using a hardware design language. For such embodiments, one possible design of the memory interface unit is set forth in Appendix A. This design uses the Verilog hardware design language. Numerous manufacturers of logic synthesizers (such as Synopsys, Viewlogic, Synplicity, ACEO, Cascade Design Automation, Exemplar, and Altera) can transform the logic in this code to gates, and thereby obtain the gate level implementation for the memory interface unit. The memory interface unit extracts either telephony data signals or telephony control signals from the frame. The two signal types are treated differently in the way they are stored. The control signals are written to control RAM 725, whereas the data signals are written to data RAM 720. In some embodiments of the invention, the control RAM is a 128x8, dual port RAM, while the data RAM is formed by two 32x32, dual port RAMs that act as a "swing" buffer ("ping-pong" buffer). RAMs 720 and 725 are where the telephony data and control signals cross from the 19 MHz, SDH-like time domain into the 4 MHz, telephony domain (e.g., POTS domain). Two RAMs are used to form the "swing" buffer for the telephony data signals. The "swing" buffer has two memory areas so the 19 MHz domain can write the data for one frame, while the 4 MHz domain can read the data for the previous frame. The memory interface unit 715 determines which of the "swing" RAMs to store the telephony data signals in the current frame, based on a frame count generated by a frame counter (not shown). The control signals do not require more than one RAM to cross the 19 MHz - 4 MHz boundary. This is because the frequency of the control signals is slow enough that both the 19 MHz and the 4 MHz domains can access the RAM before the next signaling byte will appear in the SDH frame. Also, a slight degree of imprecision can be tolerated with respect to the control signals, as such imprecision will hardly be noticed by the users. The 4 MHz side is given priority over the 19 MHz side in the accessing of this control signal RAM. Once the ONU has completely received a frame, the counter 705 and the CAM 710 have checked the location of each received byte, and the memory interface unit 715 has extracted and stored all the telephony data and control signals of the frame in the data and control RAMs, the pointer RAM control 740, the table of pointers 735, and the DS TIU interface 730 direct the telephony signals in RAMs 720 and 725 to the appropriate TIUs. In other words, the pointer RAM control 740, the table of pointers 735, and the DS TIU interface 730 act as a cross connect structure that determines which data and control is forwarded to which TIU. As shown in Figure 7, the DS TIU interface 730 couples to four TIUs A, B, C, and D. This interface also couples to the pointer control 740 to receive addresses of locations in the data and control RAMs that it needs to read. The pointer control retrieves these addresses from the pointer table 735. The pointer table couples to the microprocessor 625 through the pointer control 740 and the microprocessor interface unit 745, in order to receive and store address signals from the microprocessor during a program mode. The pointer control 740 serves as an arbitor which controls access to the table 735. The pointer control receives the 4.096 MHz clock signal, the frame synch signal, and the DS synch signal. A bit counter (not shown) of this pointer control receives the 4 MHz clock signal to generate a nine-bit count at this frequency. The control unit receives the frame synch signal (generated by the framer 610) to maintain its alignment to each frame. The control unit 740 receives the DS synch signal from the downstream synchronizer (not shown), in order to synchronize its counter with the SDH-domain counters so that the interface units 715 and 730 do not simultaneously access the memories 720 and 725. The top six bits of the nine-bit count produced by the pointer control's counter serves as a byte counter that counts sixty four bytes for each received frame. These sixty four count values define sixty four time slots during which the pointer control 740 (1) causes the pointer table 735 to generate 256 addresses in the RAMs 720 and 725, and (2) supplies these 256 addresses to the DS TIU interface 730. In particular, during each of the sixty four time slots, the pointer RAM control directs the table 735 to output in a particular sequence the contents of four of its nine- bit wide storage locations. Each nine-bit wide storage location of the table 735 includes seven bits for defining a row address, one bit for selecting the control RAM, and one bit for selecting the data RAM. In turn, during each of the sixty four time slots, the TIU interface 730 reads the RAMs at each of the four addresses output by the table. The TIU interface then forwards the four sets of retrieved signals to the four TIUs A, B, C, and D. Figure 10 illustrates this read out operation pictorially for one embodiment of the invention which stores 120 telephony data bytes in each data RAM 720, and stores 120 telephony control bytes in the control RAM 725. During the first two time slots and the last two time slots, the DS TIU interface reads out overhead bytes (e.g., parity bytes). During the remaining sixty time slots, four sets of thirty telephony data bytes (D), and four sets of thirty telephony control bytes (C) are respectively read out of the data RAMs 720 and the control RAM 725. Each TIU 355 receives one set of telephony data bytes and one set of telephony control bytes. For the operation illustrated in Figure 10, the pointer RAM control 740 alternatively reads out telephony data bytes and telephony control bytes for each TIU. Data and control signal fetching are done for each of the TIU in a particular order. During each of the middle sixty time slots, the DS TIU interface 730 retrieves four telephony bytes, The first three bytes for three TIUs are stored in intermediate registers. When the fourth byte is fetched, all four bytes are written to shift registers. These bytes are then shifted out to the TIUs one bit at a time based on the value of the pointer control's bit counter. While the bytes in the shift registers are being shifted out, the next four telephony bytes are fetched. In some embodiments of the invention, the DS TIU interface 730 and the pointer control 740 are designed and manufactured by using a hardware design language. For such embodiments, one possible design for the DS TIU interface unit is set forth in Appendix B, while one possible design for the pointer control 740 is set forth in Appendix C. These designs use the Verilog hardware design language. Numerous manufacturers of logic synthesizers (such as Synopsys, Viewlogic, Synplicity, ACEO, Cascade Design Automation, Exemplar, and Altera) can transform the logic in this code to gates, and thereby obtain the gate level implementation for the DS TIU interface. Another embodiment of the invention that is implemented in the FTTC network 300 multiplexes telephony application signals and non-telephony application signals to form an integrated telephony/non-telephony signal stream for transmission to the HDT 320 through the FTTC network. This embodiment stores position identifying indicia (e.g., pointers) that identify the appropriate location of the telephony signals in a signal stream, which as mentioned above is organized in a SDH- like frame. It then generates position identifying indicia as it receives signals for transmission, and compares the indicia to the stored indicia. When generated indicia matches stored indicia, it inserts the telephony signal corresponding to the generated indicia in the signal stream. Figure 11 sets forth one such embodiment of the invention. This embodiment multiplexes telephony signals and non-telephony signals to form an integrated telephony /non-telephony signal stream for transmission to the HDT 320 through the FTTC network. The interface apparatus 1100 constantly receives four telephony data streams (e.g., four DSO streams) from four TIUs A, B, C, and D. It multiplexes these streams with another signal stream to form a byte-wide stream supplied to the framer. Like the apparatus 700 of Figure 7, the apparatus 1 100 of Figure 11 can be implemented in the CCU's TIUI, which serves as the interface between the TIUs and the fiber optic cables. Also, like apparatus 700, this apparatus has a byte counter 1105, a CAM 1100, a memory interface unit 1115, two dual port data RAMs 1120, a dual port control RAM 1 125 , an upstream (US) TIU interface 1130, a table 1135, a pointer control 1140, and a microprocessor interface unit 1145. However, it also includes a delay FIFO 1150, an early counter 1155, and a set of eight OR gates 1160. The operation of the apparatus 1100 is similar to the operation of the apparatus 700, except that it is in the reverse order and it has a built in delay. For instance, like the pointer control 740, the table 735, and the DS TIU interface 730, the pointer control 1140, the table 1135, and the US TIU interface 1130 act as a cross connect structure. However, unlike these structures of apparatus 700, the pointer control 1140, the table 1135, and the US TIU interface 1130 forward the signals coming from the TIUs to the RAMs 1120 and 1125. As shown in Figure 11, the US TIU interface 1130 couples to TIUs A, B, C, and D to receive telephony data and control bytes. This interface also couples to the table 1135 via the control unit 1140 to receive addresses of locations in the data and control RAMs 1120 and 1125, in which it can store the received telephony bytes. The table 1135 couples to the microprocessor 625 through the control unit 1140 and the microprocessor interface unit 1145, in order to receive and store address signals from the microprocessor during a program mode. The table 1135 is controlled by the pointer control 1140, which includes a bit counter (not shown). This control unit receives the 4.096 MHz clock signal, the frame synch signal, and the US synch signal. The control unit's bit counter receives the 4.096 MHz clock signal to generate a nine-bit count at this frequency. The control unit receives the frame synch signal (generated by the framer 610) to maintain its alignment to each frame. The control unit 1140 receives the US synch signal from the downstream synchronizer (not shown), in order to synchronize its counter with the SDH-domain counters so that the interface units 1115 and 1130 do not simultaneously access the memories 1120 and 1125. The top six bits of the nine-bit count produced by the pointer control's counter serves as a counter that counts sixty four time slots for each transmitted frame. During these sixty four time slots the pointer control 1140 (1) causes the pointer table 1135 to output 256 addresses in the RAMs 1120 and 1125, and (2) supplies these addresses to the US TIU interface 1130. The US TIU interface then uses these 256 addresses to store 256 bytes from the TIUs 355 in the RAM 1120 and 1125. More particularly, during each of the sixty four time slots, the US TIU 1130 receives and stores up to four telephony bytes from the four TIUs A, B, C, and D. Also, during each time slot, the pointer RAM control 1140 directs the table 1135 to output four of its nine-bit wide storage locations. Each nine-bit wide storage location in the table 1135 includes seven bits for defining a row address, one bit for selecting the control RAM, and one bit for selecting the data RAM. The US TIU interface then uses the nine-bit outputs of the table to store its four telephony bytes in the RAMs 1120 and 1125. As mentioned above, in some embodiments of the invention, the pointer RAM control 740 is designed and manufactured by using a hardware design language; one example of such a design is set forth in Appendix C. Also, in some embodiments of the invention, the US TIU interface 1130 is designed and manufactured by using a hardware design language. For such embodiments, one possible design of the US TIU interface is set forth in Appendix D. This design uses the Verilog hardware design language. Numerous manufacturers of logic synthesizers (such as Synopsys, Viewlogic, Synplicity, ACEO, Cascade Design Automation, Exemplar, and Altera) can transform the logic in this code to gates, and thereby obtain the gate level implementation for the US TIU interface. The memory interface unit 1115 also accesses the data and control RAMs 1120 and 1125. However, unlike the US TIU interface 1130 which couples to the 4.096 MHz ports of these RAMs, the memory interface unit 1115 couples to the 19.44 MHz ports of these RAMs. As shown in Figure 11, the memory interface unit also couples to the CAM 1110, the early counter 1155, the counter 1105, and the delay FIFO 1150, in order to read the telephony bytes from the RAMs and timely output these bytes in a signal stream for transmission. Specifically, the early counter 1 155 cause memory interface unit to read out the telephony signals from the RAMs and to store them in the delay FIFO 1150. The count values generated by the early counter are a predetermined number of bytes (e.g., twenty four) ahead of the count values generated by the counter 1105. The early counter 1155 generates count values which identify the locations (or time slots or time periods) in the frame for transmission. These count values are supplied to the CAM 1110. One example of this CAM is depicted in Figure 8, which was discussed above. The CAM 1110 can store up to thirty two pointer in a first memory, where each pointer specifies the location of a telephony-application byte within each frame for transmission. The CAM also stores two control bits for each pointer in a second memory. Once the CAM receives a count value from the early counter, it simultaneously compares the count value with all of its pointers. If the generated count value matches one of the CAM's stored pointers, the CAM outputs a hit signal on the output line for its matched pointer. The memory interface unit 1115 receives the thirty two output lines of the CAM. When the CAM outputs a hit signal, the memory interface unit (like the memory interface unit 715 of apparatus 700) uses a priority encoder to encode the signal on the thirty two output lines into a five bit output. This five bit output represents the address of the row storing the matched pointer. This output is feedback to the CAM in order to read out the pair of control signals corresponding to the matched pointer. The memory interface unit then receives these two bits. For some embodiments of the invention, the relationship between the pointers stored in the CAM 710 and the storage locations in RAMs 1120 and 1125 is hard coded. This hard coded relationship allows the memory interface unit to use the matched pointer's row address plus the retrieved two control bits to extract one to four bytes from the RAMs 1120 and 1125. In some embodiments of the invention, the memory interface unit 1115 is designed and manufactured by using a hardware design language. For such embodiments, one possible design of the memory interface unit is set forth in Appendix E. This design uses the Verilog hardware design language. Numerous manufacturers of logic synthesizers (such as Synopsys, Viewlogic, Synplicity, ACEO, Cascade Design Automation, Exemplar, and Altera) can transform the logic in this code to gates, and thereby obtain the gate level implementation for the memory interface unit 1115. The memory interface unit stores the extracted telephony data bytes in the delay FIFO 1150, while it stores some of the extracted telephony control bytes in a circular buffer. As mentioned above, the early counter is a predetermined number of bytes (e.g., twenty four) ahead of the byte counter 1105. Hence, the early counter causes the memory interface unit to extract each telephony byte from the RAMs a number of cycles before it needs to output the byte. The memory interface unit uses the delay FIFO 1150 to store the extracted telephony data bytes. The delay FIFO stores thirty two sets of nine bits. The memory interface unit can store a telephony data byte in eight bits of each set. The ninth bit indicates whether the set contains telephony data bytes. Each time the early counter generates a count value, the memory interface unit (1) reads out the set of bits that was input first, and (2) can store a telephony data byte in the FIFO. Also, each time the early counter generates a new count value, the contents in each nine bit register in the FIFO are advanced one stage. The early counters and the delay FIFO allow the memory interface unit to perform a "look ahead" function, in order to identify the telephony data bytes that will surface in a few clock cycles. By identifying the telephony data bytes slightly ahead of time, the memory interface unit can combine in proper order the telephony control bytes and the telephony data bytes, as depicted in Figure 5. In other words, this early hit detection will allow the data and control bytes to be fetched and merged into the SDH frame at the proper time. The memory interface unit stores the extracted telephony control bytes in a circular buffer. For some embodiments of the invention, a three byte circular buffer is used by the memory interface unit. In these embodiments, this unit uses a frame count generated by the frame counter (not shown) to selectively store in the circular buffer one of the eight possible telephony control bytes that are to be placed in front of the sets of eight telephony data bytes in nine-byte groups of the transmitted cells. The memory interface unit reads out the contents of the delay RAM and the circular buffer under the control of the early counter 1155 or the counter 1105. The memory interface supplies each retrieved byte to input of OR gates 1160. The OR gates receive the output of the memory interface unit or another signal stream, but not both simultaneously. These gates then output the signals they receive onto line 1165, which couples to the framer 610. As apparent from the discussion above, the invention is advantageous because it provides method and apparatus that efficiently demultiplexes signals for different communication applications (such as telephony applications and non- telephony applications) from a signal stream. The invention also provides method and apparatus that efficiently multiplexes signals for different applications into a signal stream. As described above, some embodiments of the invention efficiently perform the demultiplexing operation by using a CAM to quickly verify whether a set of signals are for a particular type of communication application. If so, these embodiments extract these sets of signals from the signal stream. This demultiplexing operation obviates the need for storing all the received sets of signals, prior to determining which sets of signals need to be routed to the particular communication applications. Some embodiments of the invention also efficiently perform the multiplexing operation by using a CAM to quickly identify appropriate locations in a signal stream. While the invention has been described with reference to numerous specific details, one of ordinary skill in the art would recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Thus, one of ordinary skill in the art would understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims. APPENDIX A Appendix A page 1 for (i = 31; i = 0; i = i -1) begin mmmnmmmimiiiimiiiiimmmimmiiimmimiiiiiimmiii if (RxPcmHitlil) mimiii mi nun II ιι II II iiiimnmmnmm linn inn 5 begin , llll PCM RAM address and data control ., Hit = I'M; miiiiimiii iiiiiiimiiiiiiiiimii iiiiiimimimiiimiiimiiiiiiimiii if (ErrMulHitFlg) ErrMulHit = I'M; iiiiimiimi iimmiiimmmiiiimiimmmiiiimmimmiimiiim . > ErrMulHitFlg = I'M; HitAdd = i; i/i/i/im mi imiii/miiiii/i mi /iiiiiimmmmmminiin/imimm end II Delayed (lit signal used as byte 0 write enable, counter start signal end // and RAM storage enable end III/ llll 1/1/ II II ii ii/ii/mii/imiiniiimii fill fill II ϊtisign ErrOvrLp = Busy S Hit; always a (posedge Clk19 or negedge iRESET_) begin always 3 (posedge Clk19 or negedge iRESET_) if < ! IRESET ) begin begin if (I iRESET ) UeOOnPDIn <= 1'bO; begin dtRxSOH <- 1'bO; CAMErr <= 1'bO; dRxD <= 8'h00; end end else else begin begin CAMErr <= ErrMulHit | ErrOvrLp; UeOOnPDIn <= Hit S -Busy; end dtRxSOH <= tRxSOH; end dRxD <= RxD; end ll l III II ' lll I III! II II III II III II llll II II II llll II end II Hit address latch Latches address on CAH hit IIII ii iiiiiiiiiiiiiiiiiiiniiimiminiiiiiiiiiiiiiiiiii ii i minium mimmimmmmmmimmimimmmmiiiiiiiiiiiimiiiiiiiiiiii II Byte counter and control always a {posedge C 19 or negedge iRESET ) IIII ii ii IIII IIII mini/ inn ii mmiiiimimiiimiiiiiniiiiii begin if OlRESET assign BlkCntrO = (BlkCntr == 2'bOO); begin assign BlkSzO = (BlkSz == 2'b00); StHitAdd <= 5'bQOOOO; end always S (posedge Clk19 or negedge iRESET_) else if (Hit t -Busy) begin begin if (MRESET_) StHitAdd <= HitAdd; BlkCntr <= 2'bOO; end else end BlkCntr <= nBlkCntr; end II RAM address latch always a (UeODnPDln or StBlkSz or BlkSzO or dtRxSOH or BlkCntrO or BlkCntr) inn it iiiiiiiiiiπniiiiiiii nun iimiiimiminiiiiiiiiiiii III III ii begin if (UeODnPDln S -BlkSzO) always 3 (posedge Clk19 or negedge iRESET_) nBlkCntr = 2'b01; I begin else if (IdtRxSOH) i f < ! iRESET ) if ((BlkCntr >= StBlkSz) || BlkCntrO) begin nBlkCntr = 2'bOO; DnPUAdd <= 6'bOOOOOO; else StBlkSz <- 2'b00; nBlkCntr = BlkCntr ♦ I'M; end else else if (UeODnPOIn) nBlkCntr = BlkCntr; begin end DnPUAdd <= <RxSFCnt[0) .StHitAdd); StBlkSz <= BlkSz; assign Busy = nBlkCntr < ~ 2'b00; end end always 3 (posedge Clk!9 or negedge iRESET_) begin iimiimmmmimmiiimmmiimmiiiiimmiiiiiiiiiiimmiiiiii if ( l l RESET II Block size multiplexer to retrive the stored block size of the hit CAM begi n // location DnPUe <= 1 'bO; IIII ii mum ii miiiiimiii minium IIII ii ii IIII ii ii ii IIII ii IIII ii i UelDnPOln <= 1 'bO; UeΣOnPDtn <= 1'bO; assign BlkSz ■= {StB SzHStHi tAdd] , StBlkSzO [StHitAddJ ); Ue3DnPDIn <- 1 'bO; 39 APPENDIX assign RirvByte = 8'dO; begin pUpRdyDs! lnt4M <= UpRcq4M; minimum end / Clock inversion for down-stream signalling and PCM RAMs llll IIIII assign UpRdyusTInt4M = dAny S UpReqiM 8 -pUpRdy0sTInt4H; assign DsClk4b = -Ctk4; assign UpUr = UpRdyDsTInt4M 8 -iUPRNU; mmmmmmimmmmmiimmiimmmmmmimmiimiiiiii assign MsgCmdUr = UpUr 8 dMsgCmd; II Processor address decodes miimiiimiiiimiiiimi IIII ii mniimiiimiiiiiiiiiiiiiiiiimm always 3 (posedge Clk4 or negedge RESEI4M_) begin •ssign dAny = UpReq4M 8 ( iUPA [10:6l == 5'bOOO 00); if (!RESET4M_) assign dBitOffSet = dAny 8 ( iUPA[5:1] == 5'b00 000) begin assign dPCMSigOffB = dAny 8 ( iUPA [5 : 1] == 5'b00~001 ) MsgCmd <= 8'h00; assign dPCMAISByte = dAny 8 (iUPA[5:1] == 5'b00~010) end assign dSigAISByte = dAny 8 ( iUPA[5: 1l == 5'b00~011 ) else if (MsgCmdUr) issign dAutoAIS = dAny 8 ( iUPA[5: U == 5'b00~100) be in ssign dUpAIS = dAny 8 ( iUPA[5: 1] == 5'b00~101) MsgCmd <= iUPD [7:0] ; assign dMsgXmtEn = dAny 8 ( iUPA[5: 1l == 5'b01~000) end assign dMsgPend = dAny 8 (iuPA[5:1l -- 5'bo O01) end assign dMsgCmd = dAny 8 ( iUPA[5: 1l == 5'b01~010) assign dMsgAdd = dAny 8 (iUPA[5: 1l == S'b01~011) always a (posedge Clk4 or negedge RESET4M_) assign dMsgUrD = dAny 8 ( iUPA [5: 1] — 5'b01~100) begin i f ( ! RESET4M_) m iiiiimm ii m/i/ii mi i ι/ι/ιιm/m//ιιιιιιιι//ιι//ιιιι/ιι/ιιιιι begin II Offset bit-count capture MsgAdd <= 16'h0000; miiiiimii IIII i ii ill IIII minium minium ii miiimiiiiimi I ii mm end el se i f (UpUr 8 dMsgAdd) always S (posedge Clk4 or negedge RESET4H ) begin begin MsgAdd <= iUPD; if (IRESEI4M end be in end BitOffSet <= 9'dO; end assign MsgHAdd = MsgAdd[15:8] ; else if (UsOffSetRef) assign MsgLAdd = MsgAdd[7:0] ; t.-gin BitOffSet <= BitCnt; always a (posedge Clk4 or negedge RESET4M_) end begin end i f ( 1 RESET4M begin always a (posedge Clk4 or negedge RESET4M_) MsgUrD <= 8'hOO; begin end if (IRESET4M ) else if (UpUr 8 dMsgUrD) begin begin BitOffSetS <= 9'dO; MsgUrD <- iUPD [7:0] ; BitOffSetChg <= 1'bO; end end end else begin always a (posedge Clk4 or negedge RESET4M_) BitOffSetS <= BitOffSet; begin BitOffSetChg <= BitOffSetS \ - BitOffSet; if (IRESET4M_) end begin end MsgXmtEn <= 4'hO; end imiiiiiii/i mi i/nm i ii ii mimi/mii/iiiimiiimm/ii/mimiiiii/m else if (UpUr 8 dMsgXmtEn) II Porcessor interface control Logic, storage regs, and read mux begin IIIII ilium IIIII IIIII III IIIII iiiiiiiiiimi IIIII ii III ii ii ii ii ii ii i MsgXmtEn <= iUPD l3:0] ; end always 3 (posedge Clk4 or negedge RESET4M_) end begin if (IRESET4M ) always a (posedge Clk4 or negedge RESET4M_) begin begin pUpRdyDsTlnt4M <= 1'bO; if URESET4M_) end begin PCMSigOffB <» B'h02; <</'dU,-ltOtfSct} 8 (16(dUltUttSct))), end else if (UpUr 8 dPCMSlgOffB) iimiii IIII im ii IIII mmmuiiimm/uuui/iiiiuuuuim begin ' II Master bit counter, reference frame pulse and frame count register PCMSigOffB <= IUPD17-0]; mm imuiiun u mini minium mini in IIIII mi end t end always a (posedge Ctk4 or negedge RESET4M_) begin always a (posedge Clk4 or negedge RESET4M_) if (IRESEI4M ) begin begin if CRESET4M ) BltCnt <= 9'hOO; begi DnFrmRef <- 1'bO, PCMAISByte <= 8'h7f; end end else lelse if (UpUr 8 dPCMAlSByte) begin begin BltCnt <= nBltCnt; PCMAISByte <- lUPD[7.0), OnFrmRef <= (BltCnt == 9'bl 1101 0000), end end end end always a (posedge Clk4 or negedge RESET4M_) always 3 (BltCnt or DnCntrRst) begin begin if CRESET4M ) if (DnCntrRst) begin nBltCnt = 9'h00; SigAISByte <= 8'h02; else end nBltCnt = BltCnt * I'M; else if (UpUr 8 dSigAISβyte) end begin SigAISByte <= ιUPD [7:0] ; always 3 (posedge Clk4 or negedge RESET4M_) end begin end If (IRESET4M ) FrmCnt <= 5'bOOOOO; always 3 (posedge Clk4 or negedge RESET4H_) else if (DnCntrRst | (BltCnt == 9'd511)) begin FrmCnt <= DnFrmCnt; if (1RESET4H_) end begin AutoAIS <= 1'bO; always 3 (posedge Clk4 or negedge RESET4M_) end begin else if (UpUr & dAutoAIS) If (IRESEI4M ) begin DnMsgFC <= 2'bOO; AutoAIS <= lUPD lO] ; else if (BltCnt == cUsMsgFCRef) end DnMsgFC <- FrmCnt [1:0]; end end always a (posedge Clk4 or negedge RESET4H_) mmiiii ii it limit i mini i mm mmimimmimiiimum begi II Address and read enable for pointer and PCM RAMs if PRESET4H_) begin UpAIS <= 4'dO; assign FSSel = nBιtCnt[8:3] == 6'dl; end else if (UpUr 8 dupAIS) always 3 (posedge Clk4 or negedge RESET4M_) begin begin UpAIS <= lUPD[3:0); if (I ESET4M end oTFS <= I'M; end else oTFS <= (FSSel) ' assign UpRODsTInt = ((8'hOO,MsgCmd) 8 <16{dMsgCmd))) {(FrmCnt ==5'b00000) » ( MsgAdd 8 (16{dMsgAdd)}) cSFS[7-nBltCnt[2:0]] cFS[7-nBltCnt[2:0]]) : U8'h00,HsgUrD) 8 (16CdMsgUrD)}) I'M; ({12'd0,MsgXmtEn) 8 C16{dMsgXmtEn))) end ({15'dO,MsgPend) 8 {16CdMsgPend)>) (C8'h00,PCMSigOffB) 8 C16CdPCMSιg0ffB))) ((8'h00,PCMAISByte) 8 <16CdPCMAISByte))) II Address and read enable for pointer and PCM RAMs ((8'hOO,SigAISByte) 8 (16{dSιgAISByte») ii mm IIII minium ii mi IIIII urn 11 mi mi mi mm nun III i m u n <(15'd0,AutoAIS) t (16{dAutoA!S))) U12'd0,UpAIS) 8 (16{dUpAIS))) assign PtrRAddOS = (Bi tCnt [1 :0] ,Bi tCnt [8:4]); U Holding registers for PCM and signalling assign pPtr.1Ren0S = Bι tCnt [3:0] == 4'b0110 | // 8ι tCnt [3:0] == 4'b1000 I // PCM holding reg for interface C is not needed because the PCM buffer BιtCnt [3:0] — 4'b1011 | // read occurs just as the shift byte is needed thus no holding reg is Bl tCnt [3:0] == 4'M 101; // required III III llll II always a (posedge Clk4 or negedge RESET4M ) if (I ESET4M ) always 3 (posedge Clk4 or negedge RESEΪ4M_) PtrRRenDS <- 1 'bO, begin else if (IRESET4M PtrRRenDS <= pPtrRRenDS; begin PCHHldRegA <= 8'h00; assign DnPRAdd = {FrmCnt [0] ,DnPRAddLwr[6:2] ); SigHldRegA <= 8'h00; end assign DnPRen = Bl tCnt [3:0] -- 4'M000 I else if (LdTDDA) Bl tCπt [3:0] == 4'M010 begin Bl tCnt [3:0] == 4'b1101 | PCMHldRegA <= DnPDOutB, Bι tCnt I3:0] == 4'b1111; SigHldRegA <= DnSigOutB, end .ssign DnSl gRAdd = DnPRAddLwr, end assign DnSlgRen = DnPRen, always 3 (posedge Clk4 or negedge RESET4M_) begin minimum minium IIII mm mmiiiiiimmiimiiiimiiiiiumiu if PRESET4M ) II Stored'info from pointer RAM begin mil/mm ii / mi immimiiiiimiiummiimimuutiiimmii i PCMHldRegB <= 8'h00; SigHldRegB <= 8'h00; always 3 (posedge Clk4 or negedge RESET4M_) end begin etse if (LdlDDB) if (IRESET4M ) begin begin PCMHldRegB <= DnPDOutB; DnPRAddLwr <= 7'h00; SigHldRegB <= DnSigOutB; SigEn <= 1'bO; end PCMEn <= 1'bO; end end else if (PtrRRenDS) always 3 (posedge Ctk4 or negedge RESET4M_) begin begin DnPRAddLwr <- PtrRDOutDUS[8:2] ; if PRESET4M SigEn <= PtrRDOutDUSMl; begin PCMEn <= PtrRDOutDUSIO]; SigHldRegC <= 8'hOO, • end end end else if (LdlDDC) begin SigHldRegC <= DnSigOutB; II Data read muxes for PCM and signalling RAMs end end assign DnPDOutB = (-PCMEn) ' PCMSigOffB : ( always 3 (posedge Clk4 or negedge RESET4M_) (DnPDOut [31:24] 8 {8{DnPRAddlwr [1:0] == 2'b00))) I be in (DnPDOut[23:16] 8 {8<DnPRAddLwrf1:0] == 2'b01)}) | If CRESET4M_) (DnPDOut [15:8] 8 <8<DnPRAddLwrt1:0] == 2'M0))) | begin (DnPDOut[7:0] 8 (8{DnPRAddLwr[1:01 == 2'b11») PCMHldRegD <= 8'hOO; ); SigHldRεgD <= 8'hOO, end assign DnSigOutB - (-SigEn) ' PCMSigOffB : DnSigDOut; else if (LdlDDD) begin PCMHldRegD <= DnPDOutB; II Load enables for holding registers SigHldRegD <= DnSigOutB; II end end assign LdTDDA = BltCnt[3:0] == 4'b1101; assign LdTDDB = BιtCnt[3:0] == 4'b1010; //im milt ιιιtιtιιuι//ιι/m/iii///ιι///ι//ι/ιιι//ιι///u/ιιιu/ι//ιuιιιuιι assign LdlDDC = BιtCnt[3:0] == 4'b1111; II Parity generation and storage aassssiiggnn LLddTTDDDDOO == BBιιttCCnntttt33::00]] ==== 44''bb11000000;- in mi m mm n mum mi mm iiuimiiii ii mil III llll IIIII II I II III II II llll assign LdPrty = RsrvBSet 8 LdShftRegs; HsgEnO <- MsgXmtEn(3] ; always 3 (posedge Clk4 or negedge RESET4H_) end begin if (I ESET4M assign MsgHldLd = MsgPend S MsgHldUrDClr, begin ' PrtyByteA <= 8'hOO; assign MsgHldC dClr = LdShftRegs 8 HsgBCmdSel; PrtyByteB <- 8'hOO; assign HsgHldHAddClr = LdShftRegs 8 MsgBHAddSel; PrtyByteC <= 8'hOO; assign MsgHldLAddClr = LdShftRegs 8 MsgBLAddSel; PrtyByteO <= 8'hOO; assign HsgHldUrDClr = LdShftRegs 8 MsgBUrDSel; PrtyAccA <= 8'hOO; PrtyAccB <= 8'hOO; always 3 (posedge Clk4 or negedge RESEI4M_) PrtyAccC <= 8'hOO; if CRESET4M PrtyAccD <= 8'hOO; begin end MsgHldCmd <= 8'hOO; else if (LdPrty) end begin else if (MsgHldLd) PrtyByteA <= PrtyAccA; begin PrtyByteB <= PrtyAccB; MsgHldCmd <- MsgCmd; PrtyByteC <= PrtyAccC; end PrtyByteO <= PrtyAccD; else if (MsgHldCmdClr) PrtyAccA <= -ShftOByteA; begin PrtyAccB <= -ShftOByteB; MsgHldCmd <■= 8'h00; PrtyAccC <= -ShftOByteC; end PrtyAccD <= -ShftOByteD; end always 3 (posedge Clk4 or negedge RESEI4M_) else if (LdShftRegs) If (IRESET4M ) begin begin PrtyAccA PrtyAccA ShftOByteA; MsgHldHAdd <= 8'hOO, PrtyAccB PrtyAccB ShftOByteB; end PrtyAccC PrtyAccC ShftOByteC; else if (MsgHldLd) PrtyAccD PrtyAccD ShftOByteD; begi end MsgHldHAdd <= MsgHAdd; end else if (HsgHldHAddClr) I II II 111 II IIIII begin II Message cpu holding reg, output holding reg, and control logic MsgHldHAdd <= 8'hOO, till II UIIUII II llll II III III II Ulll end always 3 (posedge Clk4 or negedge RESET4M_) always 3 (posedge Clk4 or negedge RESET4M_) If (IRESEI4M ) if (I ESET4M_) begin begin MsgHldLAdd <= 8'h00; MsgPend <= 1'bO; end end else if (MsgHldLd) else if (MsgCmdUr) begin begin MsgHldLAdd <= MsglAdd; MsgPend <= I'M, end end else if (MsgHldLAddClr) else if (MsgHldLd) begin begin MsgHldLAdd <= 8'hOO; HsgPend <= 1'bO; end end always 3 (posedge Clk4 or negedge RESET4M_) always 3 (posedge Clk4 or negedge RESET4M ) if CRESET4H ) If (IRESET4H_) begin begin HsgHldUrD <= 8'hOO; HsgEnA <= 1'bO; end MsgEnB <= 1'bO; else if (MsgHldLd) IsgEnC <= 1'bO; begir HsgEnO <= 1'bO; HsgHldUrD <= MsgUrD; end end else if (MsgHldUrDClr) else if (MsgHldUrDClr) begin begin HsgEnA <= MsgXmtEn[01; HsgHldUrD <= 8'hOO; HsgEnβ <= MsgXmtEnM); end HsgEnC <= HsgXmtEn[21; mmumimmimuuiiiiuimiiiiuu assign HsgBHλddSctD ■= HsgEnD 8 HsgBHAddSel, II Alarms assign HsgBLAddSelD = HsgEnD 8 HsgBLAddSel, iimiiiiiiiiiiiiiiimiiimiiiiiiiiiimiiiiimimimimiiiuimuiiiiiu assign HsgBUrDSelD - HsgEnD 8 MsgBUrDSel, assign AISA = AutoAIS 8 RXAISL4M UpAISlO] , assign A1SB = AutoAIS 8 RxAISL4H UpAIS [11 ; assign ShftOByteA - (RsrvByte 8 {8<RsrvBSel}}) assign AISC = AutoAIS 8 RxλISL4M UpAIS [21 ; (PrtyByteA 8 {8(PrtyBSel))) assign AISD = AutoAIS 8 RXAISL4M UpAIS [31 ; (PCMHldRegA 8 (8(PCMBSelNrmA)}) (PCMAISByte 8 <8{PCMBSelAlSA})) assign Al rmByteA = (UsPrtyErr lO] ,AISA,Crι tPwrAlm4H,5'b00O0O), (SigHldRegA 8 (8{SιgBSelNrmA))) assign Alr ByteB = {UsPrtyErrlll , AISB, CπtPwrAlm4M,5'bO0O00); (SigAISByte 8 (8{SιgBSelAISA)}) assign AlrmByteC = {UsPrtyErr [2] ,AISC,Crι tPwrAlrrήH,5'bOOOOO); (MsgHldCmd 8 (8(HsgBCn>dSelA)}) assign AlrmByteD = {UsPrtyErr [3] ,AlSD,CrttPurAlm4H,5'bO00OO); (HsgHldHAdd 8 {8(HsgBHAddSelA))> (HsgHldLAdd 8 (8{HsgBLAddSelA))) iiimiii III III mmumium mil miiiiimiiiiiiiiiiiuum III ii III (HsgHldUrD 8 (8{MsgBUrDSelA))) II Output byte select signals and byte muxes (AlrmByteA 8 (8{AlrmβSel))), // // Interface C is different than the others see holding reg comment above assign ShftOByteB = (RsrvByte 8 (8{RsrvBSel))) ' um /// IIIII IIII im III m immmiiimiuii/i/iiumm i/im //////in (PrtyByteB 8 {8{PrtyBSel))) (PCMHldRegB 8 {8{PCMBSelNrιrβ))) assign RsrvBSel BitCntIB 3] == 6'd1, (PCMAISByte 8 {S(PCMBSelAISB))) assign PrtyBSel BltCnt [83) == 6'd2; (SigHldRegB 8 <8{SlgBSelNrmB}}) assign MsgBSel BltCnt [83] == 6'd63, (SigAISByte 8 (8{SιgBSelAISB))) assign AlrmBSel BltCnt [8 3] == 6'dO; (MsgHldCmd 8 {8(MsgBCmdSelB))) (MsgHldHAdd 8 (8{MsgBHAddSelB))) assign PCMSigBSel -RsrvBSel 8 -PrtyBSel 8 ■ MsgBSel 8 -AlrmBSel; (MsgHldLAdd 8 (8{MsgBLAddSelB»> assign PCMBSel PCMSigBSel 8 BιtCnt[3]; (HsgHldUrD 8 (8{MsgBUrDSelB))) assign SlgBSel PCHSigBSel 8 -BltCnt[3]; (AlrmByteB 8 (8{AlrmBSel))), assign HsgBCmdSel = HsgBSel 8 FrmCntH.O] == 2'b00 assign ShftOByteC = (RsrvByte 8 {8(RsrvBSel))) assign HsgBHAddSel ■ ■ HsgBSel 8 FrmCnttl.O] == 2'b01 (PrtyByteC 8 <8(Prty8Set})) assign HsgBLAddSel = HsgBSel 8 FrmCnt [1:0] == 2'MO, (DnPDOutB 8 {8(PCMBSelNrmC))> assign MsgBUrDSel = HsgBSel 8 FrmCnt[1:0] == 2'b11 (PCMAISByte 8 (BCPCMBSelAlSC))) (SigHldRegC 8 {8{SιgBSelNrmC}}) assign PCMBSelNr A = PCMBSel 8 -AISA, (SigAISByte 8 CβCSigBSelAISC)}) assign PCMBSelAISA : PCMBSel 8 AISA, (HεgHldCmd 8 {8{HsgBCmdSelC)}) assign SigBSelNrmA ■ ■ SigBSel 8 -AISA, (HsgHldHAdd 8 (8(HsgBHAddSelC}» assign SigBSelAISA : SigBSel 8 AISA; (HsgHldLAdd 8 {8{HsgBLAddSelC}}) assign MsgBCmdSelA • HsgEnA 8 HsgBCmdSel; (HsgHldUrD 8 {8(HsgBUrOSelC))) assign HsgBHAddSelA ■ MsgEnA 8 HsgBHAddSel; (AlrmByteC 8 (8(AlrmBSel))), assign MsgBLAddSelA ■ ■ MsgEnA 8 HsgBLAddSel; assign MsgBUrDSelA MsgEnA 8 MsgBUrDSel; assign ShftOByteD = (RsrvByte 8 (B(RsrvBSel))) (PrtyByteO 8 (8{PrtyBSel))) assign PCMBSelNrmB PCMBSel 8 -AISB, (PCMHldRegD {8{PCMBSelNrrrO))) assign PCMBSelAlSB PCMBSel 8 AISB, (PCMAISByte (BCPCMBSelAISD))) ssign SigBSelNrmB SigBSel 8 -AISB, (SigHldRegD {8(SlgBSelNrmD))) ssign SigBSelAlSB SigBSel 8 AISB; (SigAISByte (8{SιgBSelAISD))) assign HsgBCmdSelB MsgEnB 8 HsgBCmdSel; (MsgHldCmd (8{HsgBCmdSelD))) assign HsgBHAddSelB HsgEnB 8 HsgBHAddSel; (MsgHldHAdd {8{HsgBHAddSelO))) assign HsgBLAddSelB HsgEnB 8 HsgBLAddSel; (HsgHldLAdd {8(HsgBLAddSelD))) asstgn HsgBUrDSelB MsgEnB 8 MsgBUrDSel; (HsgHldUrD {8{MsgBUrOSelD))> (AlrmByteD (8{Al πrfiSel)}); assign PCMBSelNrmC PCMBSel 8 -AISC, assign PCMBSelAISC PCMBSel 8 AISC, ilium mill mil IIIII ii IIII ii mi iiiiuiiiiiiiiiiimiiiiiiuuu assign SigBSelNrmC SigBSel 8 -AISC, It Byte load signal for output shift registers assign SlgBSetAlSC SigBSel 8 AISC; llll llll II llll llll IIIII III IIIII I II II II assign HsgBCmdSelC MsgEnC 8 HsgBCmdSel; assign HsgBHAddSelC MsgEnC 8 HsgBHAddSel; assign LdShftRegs = BιtCnt[20] -- 3'b111, assign MsgSLAddSelC HsgEnC 8 HsgBLAddSel; assign Ms BUrDSelC HsgEnC 8 MsgBUrDSel; II Output shift registers assign PCMBSelNr D ' PCMBSel 8 -AISD, ii mm i IIII m IIII mmmiiiim IIII ii miiiuiiiuuiliiiiuummmuu assign PCHBSelAISO ■ ■ PCMBSel 8 AISD, •ssign SigBSelHrrrO ■ ■ SigBSel 8 -AISD; always 3 (posedge Clk4 or negedge RESET4H_) assign SigBSelAISD SigBSel 8 AISD; begin assign HsgBCmdSelD HsgEnO 8 HsgBCmdSel ; If ( IRESET4M_) begin TDBAReg <= 8'hOO; assign oTDDD = T0DDReg[7] ; end else if (LdShftRegs) begin endmodule // tdstint TDDAReg <= ShftOByteA; end • else begin TDDAReg <= {TDDARegt6:01 ,1'bO); end end ■ assign oTDDA = TDDAReg[7]; always 3 (posedge Clk4 or negedge RESET4H_) begin if (IRESET4H ) b in TDDBReg <= 8'h00; end else if (LdShftRegs) begin TDDBReg <= ShftOByteB; end else begin TDDBReg <= UDDBReg[6:0] , 1'bO); end assign oTDDB = TDDBReg[7]; always 3 (posedge Clk4 or negedge RESET4H_) I begin if (I ESET4H begin TDDCReg <= 8'h00; end else if (LdShftRegs) be in TDDCReg <= ShftOByteC; end else begin end assign oTDDC = TDDCReg[71; always 3 (posedge Clk4 or negedge RESET4H_) begin if (IRESET4H ) begin TDDDReg <= B'hOO; end else if (LdShftRegs) begin TDDDReg <= ShftOByteD; end else begin // input [3:01 UsPrtyErr; // // tdstfnt.v : Down-stream telephony interface input UsOffSetRef; // // input [31:0] DnPDOut; //Down-stream PCM RAM Dβta-Out U- input [7:0] DnSi DOut; //Down-stream Signalling RAH Data-Out II input [8:0] PtrRDOutDUS; // + input UpReq4M; // t t input [10:1] iUPA; // II Functional desription: input iUPRNU; // // input [15:0] iUPD; // // // output DsClk4b; // // synthesis constraints output [1:0] DnMsgFC; // // output [5:0] DnPRAdd; //Down-stream PCH RAM Read Address-In // sc ClkList = CC 4) output DnPRen; //Down-stream PCH RAH Read Enable // sc create clock C 4 -period 220 -waveform {0 110) output DnFrmRef; //Down-stream frame reference pulse // sc set clock skew -uncertainty 3 ClkList output [6:0] DnSigRAdd; //Down stream Signalling RAH Read Address-In // sc set fix hold ClkList output DnSi Ren; //Down stream Signalling RAH Read Enable // sc set atse path -from (RESET4M_) output [6:0] PtrRAddDS; // '/ sc set_dont_touch_network ClkList output PtrRRenDS; // / ι;c set dont touch network RESET4H output oTCLK; //Telephony clock // sc set oad 32 * load_of(m5c/CHDF00/D) DsClk4b output oTFS; //Telephony frame sync " // sc set_input_delay 1 (DnFrmCnt) output oIDDA; //Serial output data for telephony interface A output OlDDC; //Serial output data for telephony interface B ' module tdstint output oIDDB; //Serial output data for telephony interface C ( output oTDDD; //Serial output data for telephony interface D RESET4H , output UpRdyDsTlnt4H; // C 4, output [15:0] UpRDDsTlnt; // DsClk4b, output BitOffSetChg; // DnCntrRst, DnFr Ref, // toca I declarations DnFrmCnt, RxAISL4M, reg [B:0] BltCnt; // CritPwrAlm4H, reg [8:0] nBitCπt; // UsPrtyErr, reg [4:0] FrmCnt; // UsOffSetRef, reg oTFS; // DnPDOut, reg DnFrmRef; // DnPRAdd, reg [7:0] PCMHldRegA; // DnPRen, reg [7:0] PCMHldRegB; // DnSigDOut, reg [7:0] PCMHldRegD; // DnSigRAdd, reg 16:01 DnPRAddLwr; // DnSigRen, reg SigEn; // PtrRAddDS, reg PCMEn; // PtrRDOutDUS, reg PtrRRenDS; // PtrRRenDS, reg [7:0] SigHldRegA; // DnMsgFC, reg [7:0] SigHldRegB; // oTCLK, reg [7:0] SigHldRegC; // oTFS, reg [7:01 SigHldRegD; // OTDDA, reg 17:0] TDDAReg; // oTDDB, reg [7:0] TDDBReg; // olDDC, reg [7:0] IDDCReg; // otDDD, reg [7:01 TDDDReg; // UpReq4M, reg [7:0] PrtyByteA; // UpRdyDsTlnt4H, reg [7:0] PrtyByteB; // iUPA, reg [7:0] PrtyByteC; // iUPRNU, reg [7:0] PrtyByteO; // iUPD, reg [7:0] PrtyAccA; // UpRDDsTlnt, reg [7:01 PrtyAccB; // BitOffSetChg reg [7:01 PrtyAccC; // ); reg [7:0] PrtyAccD; // reg pUpRdyDsTInt4H, // input RESET4H_; reg 17:0] HsgCmd; // input Clk4; reg 115:0] HsgAdd; // input DnCntrRst; // reg [7:01 MsgUrD; // input [4:0] DnFrmCnt; // reg [3:01 MsgXmtEn; // input RXAISL4H; // reg [7:0] PCHSigOffB; // input CritPwrAtm4H; // reg [7:0] PCHAISByte; // reg [7:0] SigAISByte; // Msgshnααϊeiu; reg AutoAIS; // HsgBLAddSelD; // reg [3:0] UpAIS; // wi re HsgBUrDSelD; // reg HsgPend; // wi re PCMBSelNrmA; // reg HsgEnA; // PCMBSelNrmB; // reg HsgEnB; // PCMBSelNrmC; // reg HsgEnC; // PCMBSelNrmD; // ■ reg HsgEnD; // PCMBSelAISA; // reg 17.0] HsgHldCmd; // PCMBSetAISB; // reg [7:0] HsgHldHAdd; // PCMBSelAISC; // reg [7:0] HsgHldLAdd; // PCMBSelAlSD; // reg [7:0] HsgHldUrD; // SigBSelNrmA; // reg [1:0] DrflsgFC; // SigBSelNrmB; // reg [8:0] BitOffSet; // SigBSelNr C; // reg [8:0] BitOffSetS; // // reg BltOffSetChg; // SigBSelAISA; // SigBSelAISB; // wire dMsgCmd, // SigBSelAISC; // wire dMsgAdd; // SigBSelAISD; // ire dMsgUrD; // DnSigRen; // wire dHsgXmtEn; // wi re FSSel; // wire dMsgPend; // RsrvBSel, // wire dPCMStgOffB; // PrtyBSel; // wire dPCMAISByte; // AlrmBSel; // wire dSigAISByte; // PCMSigBSel; // wire dAutoAlS; // PCMBSel; // wire dUpAIS; // SigBSel; // wire dBltoffSet; // LdShftRegs; // wire dAny, // [5:0] DnPRAdd; // wire UpRdyOsTlnt4H; // [6:0] DnSigRAdd; // wire UpUr; // [7:0] DnSigOutB; // wire MsgCmdUr; // wi re [7:0] ShftOByteA; // wire [7:0] HsgHAdd; // [7:0] ShftOByteB; // wtre [7:0] HsgLAdd; // 17:0] ShftOByteC; // wire [15:0] UpRDDsTlnt; // [7:0] ShftOByteD; // wire HsgHldLd; // 17:0] RsrvByte; // wire HsgHldCmdClr; // pPtrRRenDS; // wire HsgHldHAddClr; // [6:0] PtrRAddDS; // wire HsgHldLAddClr; // DnCntrRst; // wire HsgHldUrDClr; // DnPRen; // wire AISA; // 17:0] DnPDOutB; // wire AISB; // wi re LdTDDA; // wire AISC; // wi re LdTODB; // wire AISD; // wi re LdlDDC; // wire [7:0] AlrmByteA; // wi re LdTDDD; // ire [7:0] AlrmByteB; // wi re oTCLK; // irfe [7:0] AlrmByteC; // wi re olDDA; // wtre [7:0] AlrmByteD; // wi re olDDB; // wtre MsgBSel; // wi re OlDDC; // wire MsgBCmdSel; // wi re oIDDD; // wire HsgBHAddSel ; // wi re LdPrty; // wire HsgBLAddSel; // wire 0sClk4b; // wire HsgBUrOSel; // wire HsgBCitdSelA; // uiii/mimmmmiimium/m/iimm/uuumiuuiiumium/uui wire HsgBHAddSelA; // It Constants wire MsgBLAddSelA; // wire HsgBUrDSelA; // wire HsgBC dSelB; // parameter cSFS = 8'hcc wire HsgBHAddSelB; // cFS = B'hea, wire HsgBLAddSelB; // cUsMsgFCRef = 9'd24; wire HsgBUrDSelB; // wire MsgBC dSelC; // ii inn /nun nimuuii mum mi umimiuiiiummimmiiuiiiiim wire HsgBHAddSelC; // II Mtsc assigns wire HsgBLAddSelC; // I llll llll III II II llll llll II wire HsgβUrDSelC; // wire HsgBCmdSelD; // assign oTCLK = Clk4; APPENDIX C // II local declarations // tpt, -mctl.v ■ : Pointer RAM control // ( reg dUpReq4H; // // reg UpPtrRmReqLt; // // reg DataEπ; // - x - // wire PtrRmHi t ; // • // Funct ional ι desription: wi re UpPtrRmReqSt; // '// wi re UpPtrRmReq; // // wi re UpRdyPtrRmCt UM;// // wi re PtrRAckUS; // // synthesis constraints wire PtrRCeb; // // wi re PtrRURb; // // sc ClkList = <Ctk4) wi re 16:0] PtrRAdd; // // sc create ^ clock Clk4 -per iod 220 -waveform (0 110) wire [8:0] PtrRDOutDUS; // // sc set clock skew -uncertainty 3 ClkList wi re [15:0] UpRDPtrRmCtl ; // // sc set f ix hold ClkList wi re Ctrl Hi t; // // sc set_falsej>ath -from CRESEI4M ) wi re CtrlRdy; // // sc set_dont_touch_network ClkL ist wi re UpPtrRmRdy; // // sc set dont touch network RESEI4H wire Ctrlur; // // sc set oad 32 * load of (m5c/CMOF00/D) PtrClk4b wi re PtrC 4b; // module tptrrmctl ( II Clock inversion for pointer RAH RESET4M , ii urn Clk4, PtrCtk4b, assign PtrClk4b = -Clk4; PtrRAddDS, PtrRRenDS, PtrRAddUS, II Address decode PtrRReqUS, PtrRAckUS, PtrRAdd, assign PtrRmHi t = UpReq4H 8 lUPA [10:8] " 3'b001 ; PtrRDOut, assign CtrlHit = UpReq4H 8 l ' UPA[10:1] == 10'b000_1000_000; PtrRDOutDUS PtrRCeb, PtrRURb, II Cpu request for pointer RAM signal UpRe"4H, UpRdyPtrRmCtUM, iUPA, always a (posedge Ct k4 or negedge RESET4M_) iUPRNU, i f ( I ESET4M ) iUPD, dUpReq4M <= 1 'bO; UpRDPtrRmCtl else ); dUpReq4M <s UpReq4M; input RESET4H ; II assign UpPtrRmReqSt = -dUpReq4H 8 PtrRmHi t; input Clk4; II assign CtrlRdy = -dUpReq4H 8 CtrlHit; output PtrClk4b; II input [6:0] PtrRAddDS; II always 3 (posedge Clk4 or negedge RESET4H_) input PtrRRenDS; II if ( IRESET4M ) input [6:0] PtrRAddUS; II UpPtrRmReqLt <= 1 'bO; input PtrRReqUS; II else i f (UpPtrRmRdy) output PtrRAckUS; II UpPtrRmReqLt <- 1 'bO; output [6:0] PtrRAdd; II else i f (UpPtrRmReqSt) input [8:0] PtrRDOut; II UpPtrRmReqLt <- I 'M; output [8:0] PtrRDOutDUS; II output PtrRCeb; II assign UpPtrRmReq = UpPtrRnΛeqSt | UpPtrRmReqLt; output PtrRURb; II input UpReq4H; II muuimii mi i ii mi mimummmimmiimiium minium output UpRdyPtrRmCtUM :ll It Arbitration between Cpu and Up-stream input [10:1] iUPA; II // Up-stream has priority over the Cpu input iUPRNU; II input [15:0] iUPD; II output [15:0] UpRDPtrRmCtl ; II assign UpPtrRmRdy = -PtrRRenDS 8 -PtrRReqUS 8 UpPtrRmReq; assign UpRdyPtrR CtUH = UpPtrRmRdy | CtrlRdy; assign "trRAckUS = -PtrRRenDS 8 PtrRReqUS; uumiuimui lui'Uiimummiiiiiiiuummmuui mi ii mi III II Pointer RAH Add mux and control signals assign PtrRAdd : (PtrRAddDS 8 f CPtrRRenDS)}) (PtrRAddUS 8 {7{PtrRAckUS))) | (ιUPA[7:1l 8 {7(UpPtrRmRdy))); assign PtrRCeb = -(PtrRRenDS | PtrRAckUS | UpPtrRmRdy); assign PtrRURb = -iUPRNU 8 UpPtrRmRdy; IIIII ii IIIII II Pointer RAH data disable function HI IIII IIII mi imiimimiimiiiimmimmi IIII IIII ii ii IIII i assign PtrRDOutDUS (PtrRDOut i WDataEn))); // in ii ii ii ii IIII 11 ii mum mi mimumumi mum m u , II Control register in ii ii ii ii mi IIII iiiiiiu IIII mmiuimmiiiiiimmuuiuuii assign Ctrlur = -iUPRNU 8 CtrlRdy; always 3 (posedge Clk4 or negedge RESET4M_) if (IRESET4M_) DataEn <= 1'bO; else if (CtrlUr) DataEn <= ιUPD[0J; mum IIIII II Cpu read data mux uuuuuimm ii IIIII miiiiiuumiiiuuuiuiuuuuui IIII mi IIII IIII i assign UpRDPtrRmCtl = ({7'dO, trRDOut) 8 {16{PtrRmHit») | ({15'dO,DataEn) 8 <16{CtrlHit))); end odule // tptrrmctl APPENDIX D // input [1 :0] DnMsgFC; II // Up-stream telephony interface input Bi tOffSetChg; II // input 18:0) PtrRDOutDUS; II // input PtrRAckUS; II < // input i lUDA; //Seri al input data for telephony interface A H- input i lUDC; //Seri al input data for telephony interface B Jl input UUDB; //Seri ial input data for tele hony Interface C II Functional desription: input i lUDD; //Seri al input data for telephony interface D 'II input UpReq4M; II II input [10: 1] iUPA; II II input iUPRNU; II II synthesis constraints input [15:0] iUPD; II u II sc ClkList = <Clk4 Usclk4b) output // II sc create_clock Clk4 -period 220 -waveform {0 110) output [7:0] //Up- stream PCH RAM Data-in II sc set_clock_skew -uncertainty 3 ClkList output [7:0] //Up- stream PCH RAH Urite Address- In II sc set fix hold ClkList output //Up- stream PCH RAH Urite Enable II sc set falsejiath -from (RESET4M_) output //Up- stream frame reference pulse II sc set~dont_touch_network ClkList * output UsOffSetRef; // . 1 sc set dont touch network RESET4H output 17:01 UsSigDIn; //Up-stream Signalling RAH Data-in it sc set load 32 * Toad of(m5c/CM0F00/D) UsClk4b output 16:0] UsSigUAdd; //Up- stream Signalling RAH Urite Address-In II sc set_input_delay 1 (UsFrmCnt) output UsSigUen; //Up- stream Signalling RAH Urite Enable output 16:0] PtrRAddUS; // module tustint output PtrRReqUS; // ( output [3:0] UsPrtyErr; // RESET4M_, output UsSigRdBlk4H; // Clk4, output UpRdyUsTlnt4H; // UsClk4b, output [15:0] UpRDUslInt; // UsCntrRst, output UplntUsTInt; // UsFrmRef, UsFrmCnt, // local declarat ions DnMsgFC, BitOffSetChg, reg [8:01 nβi tCnt; // UsOffSetRef, reg [8:0] Bi tCnt; // UsPDIπ, reg [2:0] FrmCnt; // UsPUAdd, reg UsFrmRef; // UsPUen, reg IUDA; // UsSigDIn, reg IUDB; // UsSigUAdd, reg IUDC; // UsSigUen, reg TUDD; // PtrRAddUS, reg [7:01 lUDAReg; // PtrRDOutDUS, reg 17:0] lUDBReg; // PtrRReqUS, reg 17:0] lUDCReg; // PtrRAckUS, reg 17:0] TUDDReg; // UsSigRdBlk4M, reg [7:01 PCHHldRegA; // iTUDA, reg [7:0] PCHHIdRegB; // iTUDB, reg [7:0] PCHHIdRegC; // MtUDC, reg [7:0] PCHHIdRegD; // i IUDD, reg [7:0] SigHldRegB; // UsPrtyErr, reg [7:0] SigHldRegC; // UpReq4H, reg [7:0] SigHldRegD; // UpRdyUsTln M, reg [7:0] PrtyHldRegA; // iUPA, reg [7:0] PrtyHldRegB; // iUPRNU, reg [7:0] PrtyHldRegC; // iUPD, reg [7:0] PrtyHldRegD; // UpRDUslInt, reg [6:0] UsPUAddLwr; // UplntUsTInt reg [1 :0] IntAdd; // ); reg [1 :0] PtrRAddLwr; // reg PtrRReqUSa; // reg PtrRReqUSb; // reg UsiigRdBlk4M; // reg SigEn; // input RESET4M ; reg PCMEn; // input Clk4; reg UsUen; // input UsCntrRst; // reg 17:0] PrtyβyteA; // input [2:0] UsFrmCnt; / reg 17:0] PrtyByteB; // [7:0] PrtyByteC // [7:0] PrtyByteO // // [7:0] PrtyAccA; [7:0] PrtyAccB; // [7:0] PrtyAccC; // [7:0] PrtyAccD; // pUpRdyUsTlnt4H; // // [1.0] HsglntNu ; // // [3:0] ActivityS; // // [9:0] LatAl O; // // [15:0] LatAlml; // // [9:0] IntAlmO; // // [15:0] IntAlml; // // [9:0] IntHskO; // // [15:01 IntMskl; // // [1:03 MsgFr Cnt; // // UsOffSetRef; // // [10:0] Actlmr; // // [10:0] nActTmr; // // GotEdgeA, // // // < GotEdgeB, // GotEdgeC; // // GotEdgeD; // // ActlvityA; // // ActlvltyB; // // Activi tyC; // // ActtvltyO; // // LdPrtyErr; // // [7:0] PCHAISByte; // // [7:0] SigAISByte; // // [3:0] UpAIS; // // [3:01 UsPrtyErr; // // // l- [1:0] MsglntNumS; // [7:0] MsgHldCmd; // // [7:0] HsgHldHAdd; // // [7:0] HsgHldLAdd; // // [7:0] HsgC d, // // [7:01 HsgHAdd, // // [7:0] MsgLAdd, // // [7:0] HsgRdD; // // wire dMsgCmd; // // // wire dMsgAdd; // wire dMsgRdD; // // wire dMsglntNu ; // // wire dActlvtty; // // wire dLatAl O; // // rfire dLatAl l; // // wire dlntAlmO; // // wire dlntAl l; // // wire dlntMskO; // // wire dlntHεkl; // // wire dAny; // // wire UpRdyUsTlnt4H; // // wire UpUr; // // wire [3:0] Activity; // // wire [3:0] RiseAct; // // wire [3:0] FallAct; // // wire LatAlmOUr; // // wire LatAlmlUr; // // wire IntAlmOUr; // // wire IntAlmlUr; // // wire UplntUsTInt; // // wire LastBtt; // wire ActTick; // // II Constants wire EdgeA; wire EdgeB; // else i f (UpUr 8 dSigAISByte) parameter cOffSetRef - 9'd485; begin SigAISByte <= iUPD [7:0] ; in i ii 1111 ii i in 11 ii 111111 ri 11111 III 11 III 11111 n 'im 'luiimiiu/iiiiiuu end ■ It Clock inversion for up-stream signalling and PCH RAHs end ι in 1111 m in i m i III III 11 m m i m i u u i ii u I m ii n i ii n i in 1111 III 11 III 111 always 3 (posedge Clk4 or negedge RESET4H_) assign UsClk4b = -C 4; begin i f ( J RESET4M ) III 11/111 II III// II III IIIII II I llll II III! III II llll llimillll I III llll I begin t Processor address decodes UpAIS <= 4'hf ; III llll II II II IIIII II 11/11 III II II II IIIII end else if (UpUr 8 dUpAIS) assign dAny = UpReq4M 8 (iUPA[10; 6] == 5' b000_01 ); begin assign dActivity = dAny 8 ( iUPA[5 1] = 5'b00 000); UpAIS <= lUPD [3:0] ; assign dLatAlmO = dAny 8 ( iUPA[5 1] = 5'b00 " 001) end assign dLatAlml = dAny 8 ( iUPA[5 11 = 5'b00 " 010) end assign dlntAlmO = dAny 8 ( iUPA[5 11 = 5'bOO " 011 ) a ssign dlntλlml dAny 8 ( iUPA[5 1] = 5'bOO ' 100) always 3 (posedge Clk4 or negedge RESET4H ) -ssign dlntHskO dAny 8 ( iUPA[5 1] = 5'bθθ " 101 ) begin assign dlntMskl dAny 8 ( iUPA [5 11 = 5'bOO " 110) i f ( IRESET4M ) assign dMsglntNum dAny 8 ( iUPA [5 1] = 5'bθf 000) begin ' , assign dMsgCmd dAny 8 ( iUPA[5 1] = = 5'b0l " 001 ) HsglntNum <= 2'bOO; assign dMsgAdd dAny 8 ( iUPA[5 1] = = 5'b0l " 010) end assign dMsgRdO dAny 8 ( iUPA[5 11 = = 5'bθf 011 ) else i f (UpUr 8 dMsglntNum) assign dPCMAISByte dAny 8 ( l ' UPA[5 11 = = 5'bθf 100) begin assign dSigAISByte dAny 8 ( iUPA[5 11 = = 5'bθf 101) HsglntNum <- iUPD[1 :0] ; assign dUpAIS dAny 8 ( iUPA[5 11 = = 5'b0l " 110) end end minimi II II Porcessor interface control logic, storage regs, and read mux assign L tAlmOUr = UpUr 8 dLatAlmO always a (posedge Clk4 or negedge RESET4H ) always 3 (posedge Clk4 or negedge RESET4H_) begin begin if ( 1RESET4H ) if (IRESET4M ) begin begin LatAlmO <= 10'dO; pUpRdyUsTInt4M <= 1 'bO; end end else else begin begin LatAl OlO] <= LatAlmOlO] ? -(-BitOffSetChgS LatAlmOUr 8 iUPD IO] ) : BitOffSetC pUpRdyUsT In M <= UpReq4H; LatAlmOM] <= LatAlmOfl] ? -(-RcvMsgTick I LatAlmOUr 8 iUPD tl] ) : RcvMsgTi end LatAlmO[2] <= LatAlm0[2] ? -(-UsMiscAlmlA I LatAlmOUr 8 iUPD [2J ) : UsHiscAl end LatAlmO[3] <= LatAlmO[3] ? -(-UsHiscAlmlB 8 LatAlmOUr 8 iUPD [3] ) : UsHiscAl LatAlmOL4] <= LatAlmOK] ? -{-UsHiscAlmlC 8 LatAlmOUr 8 iUPD[4J ) : UsHiscAl ssign UpRdyUsTInt4H = dAny 8 UpReq4H 8 -pUpRdyUsTInt4H; LatAlm0[5] <= LatAlm0[5] 7 -(-UsMiscAlmlO 8 LatAlmOUr 8 iUPD [5] > : UsHiscAl assign UpUr = UpRdyUsTInt4H 8 -iUPRNU; LatAlm0[6] <- LatAlmOlO] ? ~(-UsHiscAlm2A 8 LatAlmOUr 8 iUPD lόJ ) : UsHiscAl LatAlm0[7] <= LatAlmO[7] ? -(-UsHiscAlm2B t LatAlmOUr 8 iUPD [71 ) : UsHiscAl always 3 (posedge Clk4 or negedge RESET4H_) LatAlmO [8] <- LatAlπO[8] ? -(-UsHiscAlm2C 8 LatAlmOUr 8 iUPD[81 ) : UsHiscAl begin LatAlmO[9] <= LatAlmO[9] ? -(-UsHiscAlm2D 8 LatAlmOUr 8 iUPD [9] ) : UsHiscAl if (I ESET4H ) end begin end PCHAISByte <= 8'h7f; end assign Activity - {ActivityD,ActivityC,ActιvityB,ActivityA); else if (UpUr 8 dPCMAISByte) begin always 3 (posedge Clk4 or negedge RESET4H_) PCMAISByte <= ι ' UPD[7:0]; begin end if (!RESET4H_) end begin ActivityS <= 4'hO; always 3 (posedge Clk4 or negedge RESET4M_) end begin else if (!RESET4H_) begin begin ActivityS <= Activity; SigAISByte <= 8'h02; end end end IntAlmltU <= IntAlmlllJ 1 -(IntAlmlUr H lU UUJJ . Kt.eM.uui, assign RiseAct = Activity 8 -ActivityS; IntAlmUΣ] <- IntAlm1[2) 7 -(IntAlmlUr 8 IUPDI21) : OsPrtyAlmA; assign FallAct = -Activity 8 ActivityS; IntAlm1[3] <= lntAlm1[3] 7 -(IntAlmlUr 8 ιUPD[3]) i PrtyErrlO); lntAlm1[4] <= IntAlm1[4) ? -(IntAlmlUr 8 1UPD[4J) : Fal cttH; assign LatAlmlUr = UpUr 8 dLatAlml; IntAlm1[5] <= IntAlm1[5] ■ > -(IntAlmlUr 8 1UPD[5]) : RiseActd]; IntAlm1[6] <= lntAlm1[6] ■ > -(IntAlmlUr 8 IUPD16]) : DsPrtyAtmS; always 3 (posedge Ctk4 or negedge RESET4H_) lntAlm1[7] <= lntAlm1[7] ' -(IntAlmlUr 8 IUPD17]) : PrtyErrll], 1 5 begin IntAlmUβ] <= IntAlmllβ] ' -(IntAlmlUr 8 IUPD18]) : FatlActl2], if CRESET4H_) IntAlm1[9] <= lntAlm1[9] ■ > -(IntAlmlUr 8 IUPD19]) : RlseAct[2]; begin IntAlmUIO] <= IntAl lHO] ' -(IntAlmlUr 8 lUPDtIO]) : DsPrtyAlmC; LatAlml <- 16'dO, IntAlmUH] <= IntAlmltU] ? -(IntAlmlUr 8 lUPDtH]) : PrtyErr[2]; end IntAlm1[12] <= IntAlml C12] ' -(IntAlmlUr 8 1UPDI12]) : FallAct!3); else lntAlm1!13] <= lntAlm1[13] ? -(IntAlmlUr 8 |UPD[I3]) : RιseAct!3]; begin IntAlm1!14] <= IntAlm1!14] ' -(IntAlmlUr 8 lUPDIH]) : DsPrtyAlmD; L-tAlm1[0] <- LatAl HO] ? -(-Fal lAct [0] 8 LatAlmlUr 8 lUPOlOJ) FallAct! lntAlm1I15] <= lntAlm1[15] ' -(IntAlmlUr 8 iUPD[15]) : PrtyErr!3]; LatAlml [1] <- LatAlml [1] ? -(-RiseAct [0] 8 LatAlmlUr 8 lUPDMl) RiseAct] end LatAlml [2] <= LatAlml [2] ? -(-DsPrtyAlmA 8 LatAlmlUr 8 IUPD12J) : DsPrtyAl end LatAlm1[3] <= LatAlml [3] ? -(-PrtyErr[0] 8 LatAlmlUr 8 ιUPD[31) : PrtyErrl LatAlml [4] <- LatAlml [4] ? -(-FallAct [1] 8 LatAlmlUr 8 lUP0[41) : FallActl always 3 (posedge C 4 or negedge RESET4H_) LatAlml [5] <= LatAlml [5] ? -(-RiseAct [1] 8 LatAlmlUr 8 ιUPD[5]) : RiseAct! begin LatAlml [6] <= LatAlml [6] 1 -(-OsPrtyAlmB 8 LatAlmlUr 8 ιUPD[61) : DsPrtyAl If (IRESET4M ) LatAlml 17] <= LatAlml [7] ' -(-PrtyErr [1] 8 LatAlmlUr 8 ιUPD[7]) : PrtyErrl begin LatAlm1[8] <= LatAlml [8] ? -{-FallAct 12] 8 LatAlmlUr 8 1UPD18]) : FallAct! IπtMskO <= 10'dO, LatAlm1[9] <- LatAlml [9] 1 -(-RiseAct [2] 8 LatAlmlUr 8 IUPDI9]) • RtεeActl end LatAlm1l10] <= LatAlmKlO] ? -(-DsPrtyAlmC 8 LatAlmlUr 8 1UPDI10J) DsPrtyA else if (UpUr 8 dlntHskO) LatAlm1[11] <= LatAlml [11] ? -(-PrtyErr [2] 8 LatAlmlUr 8 lUPDlHI) : PrtyErr begin LatAlm1[12] <= LatAlmUU] ? -(-FallAct [3] 8 LatAlmlUr 8 IUPDM2]) : FallAct IntMskO <= tUPD[9:0]; LatAlml [13] <- LatAlml [13] ? -(-RiseAct [3] 8 LatAlmlUr 8 1UPDM31) : RiseAct end LatAlmUU] <= LatAlml [14] ? ~( -DsPrtyA IrrO 8 LatAlmlUr 8 ιUPD[14]) : DsPrtyA end LatAlml [15] <= LatAlm1[15] ? -(-PrtyErr[3] 8 LatAlmlUr 8 tUPD[15J) : PrtyErr end always 3 (posedge Clk4 or negedge RESET4M_) end begin if (IRESET4H_) assign IntAlmOUr = UpUr 8 dlntAlmO; begin IntMsM <- 16'd0; always 3 (posedge Clk4 or negedge RESET4H_) end begin else if (UpUr 8 dlntMskl) If (IRESET4M begin begin IntMskl <= |UPD[15 0], IntAl O <= 10'dO, end end end else begin assign UpRDUslInt = ( {8 'hOO, MsgCmd) 8 {16CdHsgCmd») IntAtmOlO] <= IntAlmOlO] 7 -(IntAlmOUr t lUPDIOl) : BitOffSetChg; ({MsgHAdd.HsgLAdd) 8 {16{*sgAdd))> IntAlmOH] <= lπtAlmOll) ? -(IntAlmOUr 8 IUPDI1]) : RcvMsgTick; (<8'h00,HsgR )) 8 (16{dMsgRdD))) IntAlmO[2] <= lntAlmO[2] ? -(IntAlmOUr 8 iUPD[2]) : UsMiscAlmlA; {{14'd0, HsglntNum) 8 {16{dMsgIntNu ))) IntAlmO[3] <= lntAlmO[3] 1 -(IntAlmOUr 8 iUPD[3]> : UsHiscAtmlB; ({8'hOO, PCMAISByte) 8 {16CdPCHAISByte)» lntAlmO[4] <= lntAlmO[4] ? -(IntAlmOUr 8 1UPD[4]) : UsHtscAlmlC, ({8'h00, SigAISByte) 8 {16{dSιgAIS8yte))) lntAlmO[5] <- lntAlmO[5] ? -(IntAlmOUr 8 IUPDI5]) : UsHiscAl ID, ((12'dO, UpAIS) 8 {16(dUpAIS))> lntAlmO[6] <= lntλlιtϋ[6] 7 -(IntAlmOUr 8 1UPD16]) : UsMiscAlmZA, U12'd0, Activity) 8 (16{dAct ivlty))) 1 IntAlmO[7] <= Intλtm0[7] ? -(IntAlmOUr 8 ιUPD[7]) : UsHιscλ[m28, ({6'dO, atAlmO) 8 (16{dLatAlm0») lntAtmO[8] <= IntAlmOIβ] ? -(IntAlmOUr 8 1UPD18J) : UsHιscAlm2C; (LatAlml 8 (16{dLatAlm1))) IntAlmO[9] <= IntAlmO[9] ? -(IntAlmOUr 8 iUPD[9]) : UsHιscAlm2D; ({6'dO, IntAlmO) 8 {16{dIntAlmO})) end (IntAlml 8 {16{dIntAlro1))> end ({6'dO, IntMskO) 8 {16CdlntHskO)}) assign IntAlmlUr = UpUr 8 dlntAl l, (IntMskl 8 (16{dlntHsk1))); always 3 (posedge Clk4 or negedge RESET4H_) assign UpIntUsl I nt = (| (IntAlmO 8 IntMskO)) | (| (IntAlml 8 IntMskl)), begin if (IRESET4H ////// ituuiit IIIII IIII ii IIII ii muumimimumumimumiuuiiiiii begi 11 Master bit counter, reference frame pulse and frame count register IntAlml <= 16'dO, m IIII iiiiiiiuuumuuiiimmuuiiiiiiiiiiiiiiimimiiiimu end else always 3 (posedge Clk4 or negedge RESET4M_) begin begin IntAlml [0] <- IntAlml [0] ' -(IntAlmlUr t lUPDIO]) : FallAct [0], if (IRESET4M | begin TUDC <= iTUDC; BitCnt <= 9'h00; TUDD <= iTUDD; UsFrmRef <= VbO; end end , end else ; be in always 3 (posedge Ctk4 or negedge RESET4M ) i ; BitCnt <= nBitCnt; begi ' ■ ' UsFrmRef <= (BitCnt == 9'b1110l OOOO); if (!RESET4M_) 1 5 end begi end TUDAReg <= 8'hOO; end always 3 (BitCnt or UsCntrRst) else begin begin if (UsCntrRst) TUDAReg <= (TUDAReg[6:0] ,TUDA); nBitCnt = 9'h00; end else end nβitCnt = BitCnt + 1'bl; end always 3 (posedge Clk4 or negedge RESET4M_) begin jssgn LastBit = (BitCnt == 9'd511); if (.RESET4M begin always 3 (posedge Clk4 or negedge RESETM_) TUDBReg <= 8'h00; I begin end if (IRESEHM ) else FrmCnt <= 3'b000; begin else if (UsCntrRst | LastBit) TUDBReg <= <TUDBReg[6:0] ,TUDB); FrmCnt <= UsFrmCnt; end end end always 3 (posedge Ctk4 or negedge RESET4M_) always 3 (posedge Clk4 or negedge RESET4H_) begin begin if (!RESET4M_) if (!RESET4M_) MsgFrmCnt <= 2'bOO; begin else if (LastBit) TUDCReg <- B'hOO; HsgFrmCnt <= DnMsgFC; end end else begin II 111 I till I IIIII 111 II III III III III TUDCReg <= (TUDCReg[6:01.TUDO; II Reference pulse used by down-stream module to capture bit offset for TIUA end //////////////////////////////////////////////////////////////////////////////// end always 3 (posedge C 4 or negedge RESET4M_) always 3 (posedge Clk4 or negedge RESET4H_) begin begin if ORESET4M_) if (!RESEKM_) UsOffSetRef <= VbO; begin else TUDDReg <= S'hOO; UsOffSetRef <= BitCnt == cOffSetRef; end end else begin //////////////////////////////////////////////////////////////////////////////// TUDDReg <= <TUDDReg[6:0] ,TUDD); // Input shift registers with data clocked in on the falling edge of the 4MHz end //////////////////////////////////////////////////////////////////////////////// end always 3 (posedge Clk4 or negedge RESET4H_) II I III II I III II 11 II It iiiiiuuuumiuuiuiiiiiutuiuiti begin II Activity detectors -- at least one edge must occur every four frames if (1RESET4M ) //////////////////////////////////////////////////////////////////////////////// begin TUDA <= 1'bO; always 3 (posedge Clk4 or negedge RESET4M_) T.JDB <- VbO; begin TUOC <= 1'bO; if (.RESEKM TUDD <= 1'bO; begin end ActTmr <= 11 'd0; else end begin else TUDA <= iTUDA; begin TUOB <= iTUOB; ActTmr <= nActT r; end assign LdHld = BιtCnt[2.0] == 3'b111; assign LdRsrv = LdHld t BιtCnt[8-3] == 6'd63; always 3 (ActTmr) assign LdPrty = LdHld S BitCnt[B:3] == 6'dO; begin assign MsgSlot = BitCnt [8:3] == 6'd61; , nActTmr = ActTmr + 1'bl; assign LdAlr = LdHld 8 Bι tCnt [8.3] " 6'd62; end assi n LdPCMSig = -LdRsrv 8 -LdPrty 8 -LdMsg 8 -LdAlr ; assign LdPCM = LdHld 8 LdPCHSt g 8 Bι tCnt [3] ; assign Actlick = -nActTmrMO] - ActTmrHO]; assign LdSig = LdHld 8 LdPCMStg 8 -BltCnt l3] ; assign EdgeA - TUDARegll] 1= TUDAReg[0], • miiimiuiimiiiiimmiuiiiuuiiiiiiiiiuuiiiiiiimmmimiiimiii assign EdgeB = TUDBReg[1] != TUDBReg[0]; II Holding registers for PCM and signalling assign EdgeC = tUDCRegM] 1= TUDCReg10], • // assign EdgeD = TUDDReg[1] 1= TUDDReg[01; // Sig holding reg for interface A is not needed because the Stg buffer // write occurs just as the shift byte arrives thus no holding reg is always 3 (posedge Clk4 or negedge RESET4H ) // required. if (1RESET4M ) III I II III I II mum I 111 GotEdgeA <= 1'bO, 'else if (EdgeA) always 3 (posedge Clk4 or negedge RESET4M_) CotEdgeA <- 1'b1, begin else if (ActTtck) If CRESET4M ) GotEdgeA <= 1'bO; begin PCMHldRegA <= 8'h00; always 3 (posedge Clk4 or negedge RESET4H_) PCHHIdRegB <= 8'hOO; If PRESET4M PCHHldRegC <= 8'hOO; GotEdgeB <= 1'bO; PCMHldRegD <= B'hOO; else if (EdgeB) end GotEdgeB <- 1'b1, else if (LdPCM) else if (ActTick) begin GotEdgeB <= 1'bO; PCHHldRegA <= TUDAReg; PCHHIdRegB <= TUDBReg; always 3 (posedge Clk4 or negedge RESET4M_) PCHHldRegC <= TUDCReg; if (IRESET4M ) PCHHldRegD <= TUDDReg; N GotEdgeC <= I'M; end else if (EdgeC) end GotEdgeC <= 1'bl; else if (ActTick) always 3 (posedge Clk4 or negedge RESET4H_) GotEdgeC <= 1'bO; begin If (IRESET4M ) always 3 (posedge Clk4 or negedge RESET4M ) begin if (IRESET4H ) SigHldRegB <= 8'hOO; GotEdgeD <= 1'bO; SigHldRegC <= B'hOO; else if (EdgeD) SigHldRegD <= 8'hOO; GotEdgeD <= 1'bl; end else if (ActTtck) else if (LdSig) GotEdgeD <= 1'bO; begin SigHldRegB <= TUDBReg; always 3 (posedge Clk4 or negedge RESET4H ) SigHldRegC <= TUDCReg; if (IRESET4H ) SigHldRegD <= TUDDReg; begin end ActivityA <= 1'bO; end Activltyβ <= 1'bO; ActtvltyC <= 1'bO; always 3 (posedge Clk4 or negedge RESET4M_) ActtvltyO <= 1'bO; begin end If (IRESET4H ) else if (ActTtck) begin begin PrtyHldRegA <= 8'hOO, ActivityA <= GotEdgeA; PrtyHldRegB <= 8'hOO; ActtvityB <= GotEdgeB; PrtyHldRegC <= 8'hOO; ActivttyC <= GotEdgeC; PrtyHldRegD <= 8'h00; ActtvttyD <= GotEdgeD; end end else if (LdPrty) begin /// tlllltlllttlttllttllll II llll PrtyHldRegA <= TUDAReg; II Load signals for holding registers PrtyHldRegB <- TUDBReg; IIIII II II II II II IIIII PrtyHldRegC « TUDCReg; PrtyHldRegD <= TUDDReg; begin end UsPrtyErr PrtyErr; end end m ' i IIIII IIII IIII ii III i ii imiiimmiiiiiiuiiuuiuiiiiiiuiimu IIII immmiiuimmimmu ii III IIIII muiiiiimiuiiuiuiimmi ( ' Parity generation and storage II Hessage control and storage i iiiiuuuuuiuuuummmmmuimmimumiumummu IIIII assign LdPrtyAcc = LdRsrv 8 LdHld; assign RcvMsgTick = LdPrty 8 MsgFrmCnt == 2'bOO; always 3 (posedge Clk4 or negedge RESEI4H_) assign ErlyLdMsg = MsgSlot 8 BitCnt [2:01 == 3'b110; begin if (IRESET4H ) assign LdMsglntNun = ErlyLdMsg 8 MsgFrmCnt [1:0] == 2'b00; begin PrtyByteA <= 8'hOO; always 3 (posedge Clk4 or negedge RESET4M_) PrtyByteB <= 8'hOO; if (IRESET4M ) PrtyByteC <= 8'hOO; begin PrtyByteO <= 8'h00; MsglntNumS <= 2'bOO; PrtyAccA <= B'hOO; end PrtyAccB <= 8'hOO; else if (LdMsglntNuπ) PrtyAccC <= 8'hOO; begin PrtyAccD <= 8'hOO; MsglntNumS <= MsglπtHum; end end else if (LdPrtyAcc) begin assign MsgByte = (TUDAReg 8 {8CMsgIntNumS == 2'b00))) I PrtyByteA <= PrtyAccA; (TUDBReg 8 (8(HsglntNumS == 2'b01))) PrtyByteB <= PrtyAccB; (TUDCReg 8 {βCHsglntNu S == 2'blO)}) PrtyByteC <= PrtyAccC; (TUDDReg 8 {8{HsglntNu S == 2*b11»>; PrtyByteD <= PrtyAccD; PrtyAccA <= -TUDAReg; assign LdHsg = HsgSlot 8 LdHld; PrtyAccB <= -TUDBReg; PrtyAccC -TUDCReg; assign LdMsgCmd = LdMsg 8 MsgFrmCnt 2'b00; PrtyAccD -TUDDReg; assign LdMsgHAdd = LdHsg 8 HsgFrmCnt == 2'b01 end assign LdMsgLAdd = LdHsg 8 HsgFrmCnt " 2'b10 else if (LdHld) assign LdMsgRdO * LdHsg t HsgFrmCnt == 2'bll begin PrtyAccA <= PrtyAccA * TUDAReg; always 3 (posedge Clk4 or negedge RESET4H ) PrtyAccB <= PrtyAccB " TUDBReg; if (IRESET4M PrtyAccC <= PrtyAccC " TUDCReg; begin PrtyAccD <= PrtyAccD " TUDDReg; MsgHldCmd <= 8'hOO; end HsgHldHAdd <= 8'hOO; end HsgHldLAdd <- 8'h00; end always 3 ,:posedge Clk4 or negedge RESET4H_) else if (!RESET4H_) begin begin HsgHldCmd <- (LdMsgCmd) ? MsgByte : MsgHldCmd; LdPrtyErr <= I'M; HsgHldHAdd <= (LdMsgHAdd) ? MsgByte : HsgHldHAdd; end HsgHldLAdd <= (LdMsgLAdd) ? MsgByte : HsgHldLAdd; else end be in LdPrtyErr <= LdPrty; always 3 (posedge Clk4 or negedge RESET4M_) end if (1RESET4M begin assign PrtyErrA = LdPrtyErr 8 PrtyByteA != PrtyHldRegA; HsgCmd <= 8'h00; assign PrtyErrB = LdPrtyErr I PrtyByteB 1= PrtyHldRegB; HsgHAdd <= 8'hOO; assign PrtyErrC = LdPrtyErr 8 PrtyByteC I- PrtyHldRegC; HsgLAdd <= 8'hOO; assign PrtyErrD = LdPrtyErr 8 PrtyByteD != PrtyHldRegD; HsgRdD <= 8'h00; end assign PrtyErr = (PrtyErrD, PrtyErrC, PrtyErrB, PrtyErrA); else if (LdMsgRdD) begin always 3 (posedge Cl 4 or negedge RESET4H_) MsgCmd <= MsgHldCmd; if (!RESET4H_> HsgHAdd <- HsgHldHAdd; begin HsgLAdd <= HsgHldLAdd; UsPrtyErr <= 4'hO; HsgRdD <= MsgByte; end end else if (LdPrtyErr) /////// II II II II IIIII 11 III IIIII III II II III PtrRReqUSa II Down-stream parity alarm end assign OsPrtyAlmA - LdAlr 8 TUDAReg17]; •Ssign DsPrtyAlmB = LdAlrm 8 TUDBReg[7]; //// III II assign DsPrtyAlmC = LdAlrm 8 TUDCRe [7]; II Generate pointer RAH signals using synchronous delays 'assign DsPrtyAlrrC = LdAlrm 8 TUDDReg[7]; // Also generate read blocking signal for other side of signalling RAH llll II II llll 11 II 11 II II II I III III I III II I II II II II llll II II II assign UsHiscAlmlA LdAlrm 8 TUDAReg [6] ; assign UsHiscAlmlβ LdAlrm 8 TUDBReg[6]; always 3 (posedge Clk4 or negedge RESET4H_) assign UsHiscAlmIC LdAlrm 8 TUDCReg[61; if CRESET4M ) assign UsHiscAlmID LdAlrm 8 TUDDReg [61; begin PtrRReqUSb <= I'M; assign UsHtscAlm2A LdAlrm 8 TUDAReg[51; UsSlgRdBlk4H <- 1'b0, assign UsHtscAlm2B LdAlrm 8 TUDBRegtϊ]; end assign UsHιscAlm2C LdAlrm 8 TUDCRe [5J, ■ else assign UsHιscAlm20 LdAlrm 8 TUDDReg[5]; begin PtrRReqUSb <= -PtrRAckUS 8 PtrRReqUSa; mmiimin ii mill immimmuiuuiumuummuu UsSlgRdBlk4M <= PtrRReqUSa; It Decode of bi t counter to get mtsc control addresses and signals end assign PtrRAddUS = ( " PtrRAddLwr,Bl tCnt 18 4] ), always 3 (BitCnt) begin assign PtrRReqUS = PtrRReqUSa | PtrRReqUSb; if (BitCnt [8:4] == 5'd31 | BltCnt[8:4] == 5'dO) begin iimiiiiiiiimmiiiiiiiiiiiimiuiiiimiimiimiiiimiiiiiiiiiiiiiimu PtrRAddLwr = 2'bOO; II Stored info from pointer RAM PtrRReqUSa = VbO; nimi III IIIIIU llll 11 llll end else always 3 (posedge Clk4 or negedge RESET4M ) case (BltCnt[3:01) begin 4'b0101 : begin If (IRESET4H ) PtrRAddLwr = 2'bOO; begin PtrRReqUSa = I'M; UsPUAddLwr <= 7'h00; end SigEn <- 1'bO; 4'b0l10 : begin PCHEn <= 1'bO; PtrRAddLwr = 2'b00; end PtrRReqUSa = 1'bO; else if (PtrRAckUS) end begin 4'b0111 : begin UsPUAddLwr <- PtrRD0utDUS(8:2]; PtrRAddLwr = 2'b01; SigEn <- PtrRDOutDUSdl; PtrRReqUSa = I'M; PCMEn <= PtrRDOutDUS [0] ; end end 4'b1000 . begin end PtrRAddLwr - 2'b01; PtrRReqUSa = 1'bO; end II Generate PCH and signalling RAH signals using synchronous delays 4'b1010 . . begin llll II II II II II II II II llll II PtrRAddLwr = 2'b10; PtrRReqUSa = 1'bl; assign UsPUAdd = {FrmCnt [0] ,UsPUAddLwr}; end 4'b1011 : : begin PtrRAddLwr = 2'b10; always 3 (posedge Clk4 or negedge RESET4H ) PtrRReqUSa = 1'bO; if (IRESET4H end begin 4'b1100 : : begin IntAdd <= 2'M0; PtrRAddLwr = 2'b11; UsUen <= 1'bO; PtrRReqUSa = 1'bl; end end else 4'b110l : : begin begin PtrRAddLwr - 2'bl1; IntAdd <= PtrRAddLwr; PtrRReqUSa = I'M; UsUen <= UsSιgRdBlk4M; end end default : : begin PtrRAddLwr = 2'b00; assign UsSigUAdd = UsPUAddLwr; APPENDIX E AddSt <= nAddSt; if (lιRESET_) dETxSOH <= ETxSOH; begin end dEIxGrpCnt <- 3'M00; end , dETxDSOCnt <= 4'M000; ValldGrp <= I'M; iimuiimi IIII mumimuimuiumuummuiuuimiuuiiiii end ll Byte counter and control else * in im uummmii IIIII ii ii III i ii ii i IIIII 11 ii i begin dEIxGrpCnt <- ETxGrpCnt; assign BlkCntrO = (BlkCntr « 2'bOO), dETxDSOCnt <= El DSOCnt; assign BlkSzO = (BlkSz == 2'MO); VβlldGrp <- pValidGrp, end always 3 (posedge C 19 or negedge ιRESET_) end begin If PlRESET assign SigHtt - -dETxSOH 8 ValldGrp 8 ({1'M.ETxSFCnt) == dETxDSOCnt) 8 BlkCntr <- 2'MO; (nUsPRen); else BlkCntr <- nBlkCntr; atways 3 (posedge Clk19 or negedge ιRESET_) end if (i iRESET ) SigUAdd <= 2'bOO, always 3 (AddSt or StBlkSz or BlkSzO or dETxSOH or BlkCntrO or BlkCntr) else if (StgHit) begin begin if (AddSt 8 -BlkSzO) if (dEIxGrpCnt == 3'dO dEIxGrpCnt == 3'd3) SigUAdd <= 2'MO, nBlkCntr = 2'M1; if (dEIxGrpCnt == 3'd1 dEIxGrpCnt == 3'd4) SigUAdd <= 2'M1 else if (IdETxSOH) if (dEIxGrpCnt == 3'd2 dEIxGrpCnt == 3'd5) SigUAdd « 2'MO if ((BlkCntr >= StBlkSz) || BlkCntrO) end nBlkCntr = 2'MO; else always 3 (posedge Clk19 or negedge ιRESET_) nBlkCntr = BlkCntr ♦ I'M; if ClRESET ) else begin nBlkCntr = BlkCntr, UsSigRAdd <= 7'hOO, end end else if (SigHtt) assign Busy = nBlkCntr ' = 2'bOO; begin UsSigRAdd = {{(AddSt) • > StHitAdd : StPRAdd[4:0]),8lkCntr>; IIIIIU IIIII llll IIIII llll end II PCH RAH read address and read enable llll III III llll llll llll II III III III I III always 3 (posedge Clk19 or negedge iRESET ) if (lιRESET_) always 3 (posedge Clk19 or negedge ιRESET_) SigFlg <= I'M; begin else if (SigFlg 8 UsSigRen) if (HRESET_) SigFlg <= I'M; begin else if (-SigFlg 8 SigHit) UsPRAddLwr <= 2'MO; SigFlg <- I'M; nUsPRen <= I'M; UsPRen <= I'M; assign UsSigRen = SigFlg 8 -UsSigRdBlk, 1 end else assign UeSigRegO - UsSigRen 8 SigUAdd == 2'b00 begin assign UeSigRegl = UsSigRen 8 SigUAdd == 2'b01 UsPRAddLwr <= BlkCntr; assign UeSιgReg2 = UsSigRen 8 SigUAdd == 2'b10; nUsPReπ <= nAddSt | -ETxSOH 8 -{nBlkCntr == 2'MO); UsPRen <= nUsPRen; assign SigFlgRAllClr = -(ETdmCell0ly[0] | DlyRen); end end always 3 (posedge Clk19 or negedge iRESET ) if (llRESET ) assign UsPRAdd = (StPRAdd,UsPRAddLwr); SigFlgRO <= I'M; else if (SigFlgRO 8 (SigFlgROClr I SigFlgRAllClr)) SigFlgRO <= I'M; else if (-SigFlgRO 8 UeSigRegO) II Signalling RAH address and data control SigFlgRO <- I'M; llll III llll always 3 (posedge Clk19 or negedge ιRESET_) assign pValidGrp = tETxCellType 8 (ETxGrpCnt 1= 3'b111); if (hRESET_) SigFlgRi <= I'M; always 3 (posedge Clk19 or negedge |RESET_) else if (SigFlgRi 8 (SigFlgRKlr I SigFlgRAllClr)) begin SigFlgRi <■= I'M; else if (-SigFlgRi 8 UeSigRegl) SigFlgRi <= I'M; assign nTxSigDSel = tTxCellType 8 -tTxSOH 8 (TxDSOCnt == 4'b1000); always 3 (posedge Ctk19 or negedge iRESET ) assign SigRegOHit = TxGrpCπt == 3'dO IxGrpCnt == 3'd3; I' if (! iRESET ) assign SigReglHit = TxGrpCnt == 3'd1 TxGrpCnt == 3'dA, [\ SigFlgRi <= 1'bO; assign SigReg2Hit = TxGrpCnt == 3'd2 IxGrpCnt == 3'd5, :, else if (SigFlgR28 (SigFlgR2Clr | SigFlgRAllClr)) ■ ' : SigFlgR2 <= I'M; assign SigFlgROClr - TxSigDSel 8 SigRegOHit; ) else if (-SigFlgR28 UeSigReg2) assign SigFlgRKlr - TxSigDSel 8 SigReglHit; SigFlgR2 <= 1'bl; assign SigFlgR2Clr - TxSigDSel 8 SigReg2Hιt; always 3 (posedge Clk19 or negedge iRESET ) assign TxSigD = (SigRegO 8 {8((SigRegOHit 8 SigFlgRO)})) ;- if (I iRESET ) (SigRegl 8 (8USigReg1Hit 8 SigFlgRi))}) SigRegO <= 8'h00; (SigReg28 <8((SigReg2Hit 8 SigFlgR2)))); else if (UeSigRegO) SigRegO <- UsSigDOut; assign nTxDVId = DlyDOutIB] SigFlgRO 8 SigFlgROClr always 3 (posedge Clk19 or negedge iRESET ) SigFlgRi 8 SigFlgRlClr if (!iRESET_) SigFlgR2 i SigFlgR2Clr; SigRegl <= 8'hOO; else if (UeSigRegl) always 3 (posedge Clk19 or negedge iRESET ) SigRegl <= UsSigDOut; if CiRESET_) begin "always 3 (posedge C 19 or negedge iRESET ) TxDEn <= I'M; if (HRESET_) end SigReg2 <= 8'h00; else if (-OlyUen 8 dDlyUen) else if (UeSigReg2) begin SigReg2 <= UsSigDOut; TxDEn <= 1'bl; end II Delay RAH write and read address and control signals and final TxD data assign TxSigDSelα = TxSigDSel 8 -OlyDOut [8] ; // rπuxtng and retiming II II II II II II II I always 3 (posedge Clk19 or negedge iRESET ) if (!iRESET_) begin always 3 (posedge Clk19 or negedge iRESET ) TxDVld <= I'M; if (HRESET ) TxD <= 8'h00; begin end DlyDln = 9'dO; else end begin else TxDVld <= (DlyRen 8 TxDEn) ? nTxDVId : M; begin TxD <= (DlyRen 8 TxDEn) ? ((TxSigDSelO) ? TxSigD: DlyOOut[7:0) ) : 8'h00; DlyDln <= (UsPRen, ((UsPRen) ? UsPDOut : 8'hOO)); end end uiiiumi i imiiiim IIII ii lumimmmmmmuiuuiiiu Iways 3 (posedge Clk19 or negedge iRESET ) II Generation of early frame sync signal if (!iRESET_) II III III II II II llll II II II III 11 IIHUlll begin E'.dmCellDly <= 2'MO; always 3 (posedge Clk19 or negedge iRESET_) DlyUen <= 1'M; begin dOlyUen <= I'M; if (lιRESET_) DlyUAdd <= 5'MOOOO; begin DlyRAdd <- S'MOOOO; ETxFS <= 1'bO; Dl Ren <= I'M; end TxSigDSel <= 1'M; else end begin else ETxFS <= TxCellCnt == TxFSCellNum 8 begin TxGrpCnt == TxFSGrpNum 8 ETdmCellDly « {EIdmCellDly[0] .tETxCellType); TxDSOCnt == TxFSDSONum; DlyUen <= ETdmCellDlyM); end dDlyUen <= DlyUen; end DlyUAdd <= DlyUAdd ♦ 1'M; DlyRAdd <= DlyUAdd ♦ DlyOffset; endmodule // tusrmictl DlyRen <= tTxCellType; TxSigDSel <= nTxSigDSel; end // //up-stream IDM cell // tusrmictl .v : Up-stream RAH output control input [3:0] EIxDSOCnt; //Early DSO number within the current // //up-stream POTS group II input [5:0] TxCellCnt; //Up-stream SPE cell number • I' I input [2:0] TxGrpCnt; //POTS group number within the current U //up-stream TDM cell l input [3:0] TxDSOCnt; //DSO number within the current i f lι Functional desription: //up-stream POTS group i7 input [31 :0] TxPcmHit; //up-stream hit signals from CAH II input [31 :0] StBlkSzO; //Bit 0 of all stored CAM block size counts II input [31 :0] StBlkSzl; //Bit 1 of all stored CAH block size counts II synthesis constraints input UsSigRdBlk, // H input [7:0] UsPDOut; //Up-stream PCH RAM data-out 11 ClkList = CClk19) input [8:01 DlyDOut; //Delay RAM data-out 11 create_clock Clk19 -period 40 -waveform (020) input [7:0] UsSigDOut; //Up-stream signalling RAM data-out II set clόck skew -uncertainty 3 ClkList II set ix iold ClkList output UsClk19b; // II set~falsejιath -from {iRESET_) output [7:0] TxD; //Up-stream SONET frame data set_dont_touch_network ClkList output TxDVld; //Up-stream SONET valid frame data signal set~dont_touch~network UsClk19b output [7:01 UsPRAdd; //Up-stream PCM RAM address-In set oad 32 * Toad_of(m5c/CHDF00/D) UsClk19b output [4:0] DlyRAdd; //Delay RAH read address output [4:0] DlyUAdd; //Delay RAM urite address module tusrmictl output DlyRen; //Delay RAM read enable output DlyUen; //Delay RAM write enable iRESE!_, output [8:0] DlyDln; //Delay RAM data-in Clk19, output UsPRen; //Up-stream PCM RAM read enable UsClk19b, output [6:0] UsSigRAdd; //Up-stream Signalling RAH read address TxD, output UsSigRen; //Up-stream Signalling RAN read enable IxD ld, output ETxFS; //Early transmitt frame sync output tETxCellType, tTxCellType, // local declarations ET SOH, ETxSFCnt, integer ETxGrpCnt, EIxDSOCnt, reg Hi t; // tlxSOH, reg [4:0] Hi tAdd; // TxCellCnt, reg AddSt; // IxGrpCnt, reg dETxSOH; // TxDSOCnt, reg nUsPRen; // TxPcmHit, reg UsPRen; // StBlkSzO, reg Val idGrp; // StBlkSzl, r eg SigF lg; // UsPDOut, reg DlyUen; // UsPRAdd, reg DlyRen; // UsPRen, reg TxSigDSel ; // UsSigDOut, reg EIxFS; // UsSigRAdd, reg [4:0] StHi tAdd; // UsSigRen, reg 15:0] StPRAdd; DlyDOut, // reg [1 :0] StBlkSz; // DlyUAdd, reg 11 :01 BlkCntr; // DlyUen, reg 11 :0] nBlkCntr; // DlyDln, reg 11 :0) UsPRAddLwr; // DlyRAdd, reg [2:0] dEIxGrpCnt; // DlyRen, reg [3:0] dETxDSOCnt; // UsSigRdBlk, reg [1 :0] SigUAdd; // ETxFS reg [6:0] UsSigRAdd; // ); reg [7:01 SigRegO; // reg [7:0] SigRegl; // input iRESET ; reg [7:0] SigReg2; // input C 19;~ reg [8:0] DlyDln; // input tETxCellType; //Early transmit cell type reg [1 :0] EldmCet lDty; // input tTxCellType; //Transmit cell type reg [4:0] DlyUAdd; // input tlxSOH; //Up-stream SONET overhead enable reg [4:0] DlyRAdd; // input ETxSOH; //Early up-stream SONET overhead enable reg [7:01 TxD; // input 12:0] ETxSFCnt; //Early up-stream super frame count reg TxDVld; // input [2:0] ETxGrpCnt; //Early POTS group number within the current reg SigFlgRO; // reg SigFlgRi; // reg SigFlgR2; // end reg TxDEn; // reg dDlyUen; ( // ilium 'mm mi mi II Hit address latch Latches address on CAH hit Mire nAddSt; // II II II II IIIII II llll II • Hire BlkCntrO; // iύire BlkSzO; // always 3 (posedge Clk19 or negedge iRESET ) • Iiire Busy; // begin w ' ire pValidGrp; // if (!iRESET_) wire SigHit; // begin wire UsSigRen; // StHitAdd <= 5'MO0O0; wire UeSigRegO; // end wire UeSigRegl; // else if (Hit 8 -Busy) 'iiire UeSigReg2; // begin wirii nTxSigDSel; // StHitAdd <= HitAdd; wire SigRegOHit; // end wire SigReglHit; // end 'ire Si Reg2Hit; // ire [1 :0] BlkSz; // wire [7:0] UsPRAdd; // II RAM address latch 'wire [7:0] TxSigD; // IIIII I II II II I ;wire SigFlgRAllClr; // 'wire SigFlgROClr; // always 3 (posedge Clk19 or negedge iRESET ) Wire SigFlgRKlr; // begin wire SigFlgR2Clr; // i f ( ! lRESET_) wire UsClk19b; // begin wire nTxOVld; // StPRAdd <= 6'MOOOOO; wire TxSigDSelO; // StBlkSz <= 2'MO; end 11 IIIII II else if (AddSt) II Parameters begin llll I III IIIII llll StPRAdd <- {ETxSFCnt[0],StHitAdd); StBlkSz <= BlkSz; parameter DlyOffset = 5'd8, end TxFSCellNum = 6'd40, end TxFSGrpNum = 3'd3, TxFSDSONum = 4'dl; llll II II II II II III II Block size multiplexer to retrive the stored block (lie of the hit CAM // location II I llll I II IIIII II II II II I II llll II llll II II II III III llll III llll I llll Conmon stuff III II II IIII IIII i mmmiiiiiiimiiiiimiiiiiiiiiiiiiiiiiiiii assign BlkSz = {StBlkSzl [StHitAdd] ,StBlkSzO[StHitλdd]}; II II II llll II llll II II II I IIIII II ,1 Clock inversion for up-stream signalling and PCH RAHs llll PCH RAH address and data control II II llll llll II II II II llll II llll uuuuiuiuuiiiuuiimmumimu imumuuuumiumuuu assign UsClk19b = -Clk19; mmuumuiuumiumimuummmummmiumumuu I II II II II IIIII II Delayed Hit signal used as a strobe to store the CAH hit address, as a start II Priority encoder with error signal for more than one CAH location hit // signal for the BlkCntr, and as a RAH read enable for the first DSO. I II llll II II llll II II always 3 ( TxPcmHit ) assign nAddSt = Hit 8 -Busy; begin Hit = I'M; always 3 (posedge Clk19 or negedge iRESET ) HitAdd = 5'M0O0O; begin for (i = 31; i >= 0; i = i -1) if (!iRESET_) begin begin if (TxPcmHit [i]) AddSt <= I'M; begin dETxSOH « I'M; Hit = 1'bl; end HitAdd = i; else end begin

Claims: CLAIMS I claim: 1. In a communication system that transmits a signal stream having signals for a number of sets of communication devices, a method of extracting signals for a first set of communication devices from the signal stream, the method comprising the steps of: (a) storing locations, in the signal stream, of sets of signals, said sets of signals including at least one set of signals for the first set of communication devices; (b) simultaneously comparing locations of received sets of signals in a received signal stream to a number of the stored locations; (c) when a location of a first set of signals matches the stored location of the set of signals for the first set of communication devices, extracting the first set of signals from the signal stream. 2. The method of claim 1 further comprising the steps of: (a) generating routing signals; (b) routing said extracted first set of signals to the first set of communication devices based on the routing signals. 3. The method of claim 2, (a) wherein the generating step includes the step of generating memory address and control signals; (b) wherein the routing step includes the step of using the generated memory signals to store the extracted first set of signals in a memory. 4. The method of claim 4 wherein the routing step further includes the step of reading said memory to extract the first set of signals, and forwarding the read¬ out first set of signals to the first set of communication devices. 5. In a communication system that transmits a signal stream having signals for different communication applications, a method of extracting signals for a first type of communication application from a received signal stream, the method comprising the steps of: (a) storing position identifying signals identifying the location of sets of signals for the first type of application in the received signal stream; (b) generating a position identifying signal for each received set of signals in the received signal stream; (c) simultaneously comparing the generated position identifying signal for each received set of signals with a number of the stored position identifying signals; (d) when one of the generated position identifying signals matches one of the stored position identifying signals, extracting from the signal stream the set of signals corresponding to the generated position identifying signal. 6. In a communication system that transmits a signal stream having signals for a number of sets of communication devices, a method of inserting signals for a first set of communication devices into the signal stream, the method comprising the steps of: (a) for each set of signals for transmission from the first set of communication devices, storing a pointer that identifies the location of the sets of signals in the signal stream; (b) generating pointers identifying locations of sets of signals in the signal stream; (c) simultaneously comparing each generated pointer with a number of the stored pointers; (d) when a generated pointer matches a stored pointer, inserting into the signal stream a set of signals corresponding to the matched stored pointer. 7. In a communication system that transmits a signal stream having signals for a number of sets of communication devices, a method of inserting signals for a first set of communication devices into the signal stream, the method comprising the steps of: (a) for each set of signals for transmission from the first set of communication devices, storing a pointer that identifies the time period for transmitting the set of signals; (b) while transmitting the signal stream, generating pointers to identify time periods for transmitting sets of signals; (c) simultaneously comparing each generated pointer with a number of the stored pointers; (d) when a generated pointer matches a stored pointer, inserting into the signal stream the set of signals, from the first set of communication devices, corresponding to the matched stored pointer. 8. A time division demultiplexing method, said method comprising the step of using a content addressable memory to identify sets of signals that need to be extracted from a signal stream. 9. A time division multiplexing method, said method comprising the step of using a content addressable memory to identify time periods for inserting sets of signals into a signal stream 10. In a fiber optic telecommunication network, an optical network unit receiving a signal stream having signals for a telephony application and signals for a non-telephony application, said optical network unit having a content addressable memory, said memory storing locations of signals for the telephony application in the received signal stream. 11. In a communication system that transmits a signal stream having signals for a number of sets of communication devices, an apparatus for extracting signals for a first set of communication devices from the signal stream, the apparatus comprising: (a) a memory storing position identifying signals identifying the locations, in the signal stream, of sets of signals for the first set of communication devices; (b) a comparator coupled to the memory, wherein, for each received set of signals, the comparator receives a position identifying signal identifying the location of the received set of signals, the comparator simultaneously comparing each received position identifying signal with a number of the stored position identifying signals, wherein, when a position identifying signal of a first set of signals matches a stored position identifying signal, the comparator generates a signal indicating that the first set of signals have to be extracted from the signal stream. 12. In a communication system that transmits a signal stream having signals for a number of sets of communication devices, an apparatus for inserting signals from a first set of communication devices into the signal stream, the apparatus comprising: (a) a memory storing position identifying signals identifying the locations, in the signal stream, for sets of signals from the first set of communication devices; (b) a comparator coupled to the memory, wherein, while transmitting the signal stream, the comparator receives position identifying signals identifying the locations of the set of signals in the signal stream, the comparator simultaneously comparing each received position identifying signal with a number of the stored position identifying signals, wherein, when a position identifying signal matches a stored position identifying signal of a first set of signals, the comparator generates a signal indicating that the first set of signals have to be inserted into the signal stream. 13. A time division demultiplexer comprising a content addressable memory to identify sets of signals that need to be extracted from a signal stream. 14. A time division multiplexor comprising a content addressable memory to identify time periods for inserting sets of signals into a signal stream.

Inventors: GOODY STEVEN H, GOODY, STEVEN, H.
Applicants: NEXT LEVEL COMM, NEXT LEVEL COMMUNICATIONS
Application year: 1998
Main classification: H04L12
IPC codes: H04J3, H04L12, H04Q11