ETCHING METHODS FOR ANISOTROPIC PLATINUM PROFILE

Abstract: A method of etching a platinum electrode layer disposed on a substrate to produce a semiconductor device including a plurality of electrodes separated by a distance equal to or less than about 0.3 mu m and having a platinum profile equal to or greater than about 85 DEG . The method comprises heating the substrate to a temperature greater than about 150 DEG C, and etching the platinum electrode layer by employing a high density inductively coupled plasma of an etchant gas comprising chlorine, argon and optionally a gas selected from the group consisting of BC13, HBr, and mixtures thereof. A semiconductor device having a substrate and a plurality of platinum electrodes supported by the substrate. The platinum electrodes have a dimension (e.g., a width) which includes a value equal to or less than about 0.3 mu m and a platinum profile equal to or greater than about 85 DEG .

Description: ETCHING METHODS FOR ANISOTROPIC PLATINUM PROFILE BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to plasma etching of platinum. More specifically, this invention provides a method for plasma etching of platinum for producing semiconductor integrated circuits containing platinum electrodes. 2. Description of the Prior .Art The implementation of digital information storage and retrieval is a common application of modem digital electronics. Memory size and access time serve as a measure of progress in computer technology. Quite often storage capacitors are employed as memory array elements. As the state of the art has advanced, small-feature-size high density dynamic random access memory (DRAM) devices require storage capacitors of larger capacitance having high dielectric constant materials. The high dielectric constant materials or ferroelectric materials are made primarily of sintered metal oxide and contain a substantial amount of very reactive oxygen. In the formation of capacitors with such ferroelectric materials or films, the electrodes must be composed of materials with least reactivity to prevent oxidation of the electrodes which would decrease the capacitance of storage capacitors. Therefore, precious metals, such as platinum (Pt), palladium (Pd), etc., are preferred metals used in the manufacture of capacitors for high density DRAM. Among the possible precious metals for capacitor electrodes, platinum .has emerged as an attractive candidate because it is inert to oxidation and is known to have a leakage current ( < 10" 9 amps/cm 2 ) lower than other electrodes such as Ru0 2 and Pd. Platinum also is a good conductor. In the prior art, platinum etching has been conducted by means of isotropic etching, such as wet etching with aqua regia, or by anisotropic etching, -such as ion milling with Ar gas or by other means. Because of the nature of isotropic etching, using wet etching with aqua regia causes deteriorated processing accuracy. The grade of p.recision in isotropic etching is not high enough for fine pattern processing. Therefore, it is difficult to perform submicron patterning of platinum electrodes due to its isotropic property. Furthermore, a problem with ion milling (i.e. anisotropic etching) occurs because the etching speed on platinum, which is to foim the electrode, is too slow for mass production. In order to increase processing accuracy in etching platinum, research and development has been quite active, particularly in the area of etching platinum by means of a dry etching process where etchant gases (e.g., Cl 2 , HBr, O 2 , etc.) .are used. The following prior art is representative of the state of art with respect to etching platinum with a plasma of etching gases. U.S. Patent No. 5,492,855 to Matsumoto et al. discloses a semiconductor device manufacturing method, wherein an insulation layer, a bottom electrode Pt layer, a dielectric film and a top electrode Pt layer are provided on top of a substrate having already-completed circuit elements and wiring, and then, a capacitor is formed by selectively dry etching the bottom electrode Pt layer after selectively dry etching the top electrode Pt layer and the dielectric film. The manufacturing method uses a gas containing an S component as etching gas for Pt etching, or an etching gas containing S component as an additive gas; and also it implants S into the Pt layer before the Pt dry etching process by means of ion implantation to compose a S and Pt compound, and then d.ry etches the Pt compound thus composed. U.S. Patent No. 5,527,729 to Matsumoto et al. discloses process steps to form on a substrate in which circuit elements and wirings, etc., are already shaped, an insulation layer, a first metal layer, a dielectric film and a second metal layer. A top electrode and a capacitance film are formed by dry etching the second metal layer and the dielectric film. A bottom electrode is formed by dry etching the first metal layer. The etching gas for dry etching the second metal layer is a mixed gas containing hydrogen halide (e.g. HBr) and oxygen, having a ratio of oxygen against the total of hydrogen halide and oxygen set at about 10%-35% . The etching gas is also taught as a gas containing hydrocarbon, such as chloroform. Matsumoto et al. employs a silicon oxide layer as the insulation layer on the substrate, and a platinum layer or palladium layer as the first and second metal layers. Dry etching of the second metal layer and dielectric film is conducted in a low pressure region not higher than about 5 Pa, where the etching speed is high. Matsumoto et al. further teaches that where a mixed gas of hydrogen halide and oxygen is used as the etching gas, the etching speed on the silicon oxide layer can be made sufficiently low relative to that on the second metal layer made of a platinum layer or a palladium layer; in this way, the excessive etching of the silicon oxide layer underlying the first metal layer is avoided, and damage to the circuit elements and wiring, etc. underneath the silicon oxide layer can be prevented. Furthermore according to Matsumoto et al, the ratio of etching speed of the platinum and dielectric material to the resist can be increased by lowering the etching speed on the resist. Therefore, etching of the platinum and dielectric material may be conducted by using a mask of normal lay-thickness resist (generally speaking, about 1.2 μm to about 2.0 μm thick), instead of using a conventional thick-layer resist (about 3 μm and thicker). Chou et al. in an article entitled "Platinum Metal Etching in a Microwave Oxygen Plasma", J. Appl. Phys. 68 (5), 1 September 1990, pages 2415-2423, discloses a study to understand the etching of metals in both plasma and chemical systems. The study found that the etching of platinum foils in an oxygen plasma generated in a flow-type microwave system and that very rapid etching (~6.A/s) took place even at low power inputs (200 W). The principal plasma parameters, including oxygen atom concentration, ion concentration, and electron temperature, were measured by Chou et al. as a function of distance below the microwave coupler. These were correlated to the rate of foil etching, which decreased with increasing distance from the coupler. On the basis of these coirelations Chou et al. formulated a simple mechanistic model. The study by Chou et al. further found that the etching of platinum in an oxygen plasma jet results from the concomitant action of oxygen atoms and high energy electrons. Nishikawa et al. in an article entitled "Platinum Etching .and Plasma Characteristics in RF Magnetron and Electron Cyclotron Resonance Plasmas", Jpn. J. Appl. Phys., Vol. 34 (1995), pages 767-770, discloses a study wherein the properties of platinum etching were investigated using both rf magnetron and electron cyclotron resonance (ECR) plasmas, together with measurement of the plasma parameters (neutral concentration, plasma density, etc.). Nishikawa et al. performed experiments in Cl 2 plasmas over a pressure ranging from 0.4 to 50 mToiτ. In rf magnetron plasmas, the etch rate of Pt was constant at the substrate temperature of from 20 to 160 ' C. The etch rate and the plasma electron density increased with gas pressure decreasing from 50 to 5 mTorr. In ECR plasmas for rf power of 300 W, Nishikawa et al. found that the etch rate of Pt was almost constant ( - 100 nm min) with gas pressure decreasing from 5 to 0.4 mTorr, while the plasma electron density gradually increased with decreasing gas pressure. The study by NisMkawa et al. discusses these experimental results with respect to the relationship between the etch yield and the ratio of neutral Cl 2 flux and ion flux incident on the substrate. Yokoyama et al. in an article entitled "High-Temperature Etching of PZT/Pt/TiN Structure by High-Density ECR Plasma", Jpn. J. Appl. Phys., Vol. 34 (1995), pages 767- 770, discloses a study wherein micron patterning technologies for the PZT/Pt/TiN/Ti structure with a spin on glass (SOG) mask are demonstrated using a high-density electron cyclotron reson^ce (ECR) plasma and a high substrate temperature above 300'C. A 30%- Cl 2 /Ar gas was used to etch a lead zirconate titanate (PZT) film. No deposits remained, which resulted in an etched profile of more than 80 * . A 40%-O 2 /C1 2 gas was used to etch a Pt film. The etching was completely stopped at the Ti layer. 30-nm-thick deposits remained on the sidewall. They were removed by Yokoyama et al. after dipping in hydrochloric acid. The etched profile of a Pt film was more than 80 ' . The Ti/TiN/Ti layer was etched with pure Cl 2 gas. The size shift from the SOG mask was less man 0.1 μm. Yokoyama et al. did not detect any interdiffusion between SOG and PZT by transmission electron microscopy and energy dispersive x-ray spectroscopy (TEM-EDX) analysis. Yoo et al. in an article entitled "Control of Etch Slope During Etching of Pt in Ar/Cl 2 /O 2 Plasmas", Jpn. J. Appl. Phys. , Vol. 35 (1996), pages 2501-2504, teaches etching of Pt patterns of the 0.25 μm design rule at 20 ' C using a magnetically enhanced reactive ion etcher (MERIE). Yoo et al. found that a major problem of etching with a MERIE was the redeposition of the etch products onto the pattern sidewall, making it difficult to reduce the pattern size. In both cases separately using a photoresist mask and an oxide mask, the redeposits of the etch products onto the sidewall were reduced by the addition of Cl 2 to Ax, although the etched slope was lowered to 45 ' . The redeposits were removed by an HC1 cleaning process. Kotec i in an article entitled "High-K Dielectric Materials for Capacitors" , Semiconductor International, November 1996, pages 109-116, the potential advantages of incorporating high-dielectric materials into a storage capacitor of a dynamic random access memory (DRAM) are described and the requirements of the high dielectric layer are reviewed as they relate to use in a simple stack capacitor structure suitable for the gigabit generation. Kotecki teaches that when considering the use of high-dielectric materials in a stack capacitor structure, the following issues need to be addressed: electrode patterning, high-dielectric material/barrier interaction, electrode/high-dielectric material interaction, surface roughness (e.g. hilocking, etc.), step coverage, high-dielectric material uniformity (e.g. thickness, composition, grain size/orientation, etc.), and barrier (e.g. O 2 and Si diffusion, conductivity, contact resistance and interactions, etc.). Various materials and combinations of materials were studied by Kotecki for use with perovslcite dielectrics including the noble metals (i.e. Pt, Ir, Pd) and conductive metal oxides (i.e. IrO 2 and RUO 2 ). The work function of these materials, their ability to be patterned by dry etching, the stability of the surface with regards to surface roughening .and their suitability in a semiconductor fabricator are listed by Kotecki in the following Table I: TABLE I Comparison of the .Properties of Various Electrode Materials Suitable for Use with Perovskite Dielectrics .Material Work Dry Surface Deposition Selection Function Etch Stability Method Pt 5.6-5.7 difficult potential problem sputtering Ru 4.7 easy/dangerous potential problem sputtering Ru0 2 /Ru easy/dangerous good .reactive sputtering Ir 5.0-5.8 difficult good sputtering IrOj/Ir difficult good reactive sputtering Pd 5J-5.6 difficult 7 sputtering Kotecki further teaches in the article entitled "High-K Dielectric Materials for DRAM Capacitors" that one of the major problems which needs to be overcome with respect to the manufacturing of D.RAM chips using capacitors is the problem of electrode patterning. There are minimal volatile species produced during the dry etching of the noble metal electrodes such as Pt, Ru, Pd and Ir. Since the etch mechanism is primarily by physical sputtering, even during a RIE process, fences are typically formed on the sides of the photoresist. To eliminate the problem of fencing, it is possible to etch the fence layer and erode the sides of the photoresist during the etch process which leads to "clean" metal structures but with sloping sidewall angles and a loss of control over critical feature sizes. As the dimension of the feature shrinks to 0J8 μm or below, only limited tapering of the sidewall angle can be tolerated. Kotecki presents in the following Table II some of the high- dielectric materials which have been considered for use in a DRAM capacitor, the various methods which can be used to foim the films, and the range of reported permittivites: TABLE H A Comparison of Various .High-Dielectric Materials and Method for Formation and Dielectric Constants Material Deposition Methods e τ (thin films) SrTiO, MOCVD, ECR-CVD, sol-gel, sputtering, PLD 90-240 (Ba, Sr)Ti0 3 MOCVD, ECR-CVD, sol-gel, sputtering, PLD 160-600 PLT MOCVD, sol-gel, sputtering, PLD 400-900 PZT and PLZT MOCVD, sol-gel, sputtering, PLD > 1000 Milkove et al. reported in a paper entitled "New Insight into the Reactive Ion Etching of Fence-Free Patterned Platinum Structures" at the 43rd Symposium of AVS, October 1996, Philadelphia, PA, that an investigation was undertaken to charactei±re the time progression of the Pt etch process during the reactive ion etching (RIE) of fence-free patterned structures. The experiment by Milkove et al. consisted of coprocessing two oxidized Si wafers possessing identical 2500 A thick Pt film layers, but different photoresist (PR) mask thicknesses. Etching was suspended at 20, 40, 60 and 80% of the full etch process in order to cleave off small pieces of wafer for analysis by a scanning electron microscopy (SEM). Using Cl 2 -based RIE conditions known to produce fence-free etching for 2500 A thick film layers, Milkove et al. discovered that a severe fence actually coats the PR mask during the first 20% of the etch process. As the etch continues the fence structure evolves, achieving a maximum height and width followed by progressive recession until disappearing completely prior to process endpoint. The data from Milkove et al. shows that the final profile of an etched Pt structure possess a functional dependence on the initial thickness and slope of the PR mask, as well as on the initial thickness of the Pt layer. Milkove et al. further reported in the paper entitled "New Insight Into The Reactive Ion Etching of Fence-free Patterned Platinum Structures" that the observed behavior of the transient fence provides the strongest evidence to date supporting the existence of a chemically assisted physical sputtering component associated with the RIE of Pt films in halogen-based plasmas. Keil et al. teaches in an article entitled "The Etching of Platinum Electrodes for PZT Based Ferroelectric Devices", Electrochemical Society Proceedings, Vol. 96-12 (1996), pages 515-520, that the technical difficulties of fabricating capacitors employing platinum Pt etching is most often dominated by sputtering processes. While oxygen and/or various gaseous chlorides or fluorides are used to chemically enhance the etch process, the products of both etch mechanisms are usually of low volatility and tend to redeposit on the wafer. After etching, large wall-like structures extend up from the edges of the Pt region. These wall-like structures are frequently referred to as "veils" or "fences" or "rabbit ears" and can reach lengths which are more than double the thickness of the Pt film to which they are attached. The existence of such structures makes useful deposition of the PZT layer impossible. Keil et al. further teaches that even when one is able to attenuate redeposition to the point where only small "nub" like features are present, the high electric fields which will form at such "nubs" enhances the likelihood for dielectric breakdown. .Although process conditions can be found which result in either low redeposition or even no redeposition, they most often also give an unacceptably tapered platinum profile angle. Keil et al. observed that redeposition becomes more severe as process conditions are pushed toward those which give increasingly vertical sidewalls. While a post etch wet clean in a solvent bath is frequently used, the heavy redeposition which attends the pursuit of vertical sidewalls regularly renders this approach minimally effective. The foregoing prior art illustrates that generally a clean vertical dense area profile and CD (critical dimension) control of the etch profiles are critical factors for successful plasma etching of 1-Gbit (and beyond) DRAM ferroelectric devices possessing platinum electrodes. Redeposition and profile control are found to be strongly interlinked. Optimization of both profile angle and redeposition requires a tradeoff between the two. Where as vigorous post etch cleaning (e.g. wet cleaning with acid, mechanical polishing, etc.) can relieve some of the need to achieve a deposition free plasma etch, such post etch cleaning does not possess the accuracy that is desired as the platinum electrode itself is typically eroded and/or deteriorated by currently known post etch cleaning methods. Therefore, what is needed and what has been invented is a method for etching a platinum electrode layer to produce a high density integrated circuit semiconductor device having platinum electrodes with a high degree (i.e., > 85°) of platinum profile anisotropy. What is fUarther needed and what has been invented is a semiconductor device including a plurality of platinum electrodes having a platinum profile equal to or greater than about 85° and separated by a distance equal to or less than about 0.3 μm with each electrode having a critical dimension (e.g., a width) equal to or less than about 0.3 μm. SUMM.ARY OF THE INVENTION The present invention accomplishes its desired objects by broadly providing a method of etching a platinum layer disposed on a substrate comprising the steps of: a) providing a substrate supporting a platinum layer; b) heating the substrate of step (a) to a temperature greater than about 150°C; and c) etching the platinum layer including employing a high density plasma of an etchant gas comprising a halogen containing gas (e.g., a halogen such as chlorine) and a noble gas (e.g. , argon) to produce the substrate supporting at least one etched platinum layer. The platinum layer is preferably a platinum electrode layer. The high density plasma of an etchant gas is a plasma of an etchant gas having an ion density greater than about 10 9 /cm\ preferably greater than about 10 π /cm 3 . The etchant gas may also include a gas selected from the group consisting of BC1 3 , HBr, and mixtures thereof. The platinum layer of step (a) above may additionally comprise a mask layer disposed on a selected part of the platinum layer to selectively protect the platinum layer during the etching step (c) above. The platinum layer of step (a) may also additionally comprise a protective layer disposed on the selected part of the platinum layer between the mask layer and the platinum layer. The mask layer may be removed during or after the etching step (c). Similarly, the protective layer may be removed during or after the etching step (c). The platinum layer is part of or is contained in a platinum wafer, and the method of etching a platinum layer additionally comprises disposing the platinum wafer including the platinum layer of step (a) in a high density plasma chamber having a coil inductor and a wafer pedestal; and performing the etching step (c) in the high density plasma chamber under the following process conditions: Process Parameters Etchant Gas Flow 50 to 500 seem Halogen Gas (e.g., Cl 2 ) 20% to 95% by vol. Noble Gas (e.g., Ax) 5% to 80% by vol. Pressure, mTorr 0J to 300 milliToiT RF Power (watts) of Coil Inductor 100 to 5000 watts RF Power (watts) of Wafer Pedestal 50 to 3000 watts Temperature (° C) of Platinum Wafer 150° to 500° C Platinum Etch Rate (-A/min) 200 to 6000 A/min RF Frequency of Coil Inductor 100 K to 300 M . Hz RF Frequency of Wafer Pedestal 100 K to 300 .MHz The etched platinum layer includes a platinum profile equal to or greater than about 85°, more preferably equal to or greater than about 87°, most preferably equal to or greater than about 88.5°. The etchant gas for the process conditions immediately above may alternatively comprise from about 10% to about 90% by vol. of a halogen (e.g., Cl 2 ), from about 5% to about 80% by vol. of a noble gas (e.g., argon), and from about 4% to about 25% by vol. HBr and/or BC1 3 . The present invention also accomplishes its desired objects by broadly providing a method for producing a capacitance structure including a platinum electrode comprising the steps of: a) providing a substrate supporting a platinum electrode layer and at least one mask layer disposed on a selected part of said platinum electrode layer; b) heating the substrate of step (a) to a temperature greater than about 150°C; and c) etching the platinum electrode layer including employing a plasma of an etchant gas comprising a halogen (e.g., chlorine) and a noble gas (e.g., argon) to produce a capacitance structure having at least one platinum electrode. The at least one mask layer is removed during or after the etching step (c) immediately above. The platinum electrode layer of step (a) immediately above may additionally comprise a protective layer disposed on the selected part of platinum electrode layer between the mask layer and the platinum electrode layer. The etched platinum electrode layer produced by the etching step (c) immediately above includes a platinum profile equal to or greater than about 85°, more preferably equal to or greater than about 87°, most preferably equal to or greater than about 88.5°. The etchant gas of the plasma of step (c) more specifically includes a halogen (e.g., chlorine), a noble gas (e.g., argon), and a gas selected from the group consisting of HBr, BC1 3 and mixtures thereof. The platinum electrode layer is part of or is contained in a platinum electrode wafer, and the method for producing a capacitance structure including a platinum electrode layer additionally comprises disposing, prior to the etching step (c), the platinum electrode wafer in a high density plasma chamber having a coil inductor and a wafer pedestal; and performing the etching step (c) in the high density plasma chamber under the following previously indicated process conditions: Process Parameters Etchant Gas Flow 50 to 500 seem Halogen Gas (e.g., Cl 2 ) about 10% to about 90% by vol. Noble Gas (e.g., Ax) about 5% to about 80% by vol. HBr and/or BC1 3 about 4% to about 25% by vol. Pressure, mTorr 0J to 300 milliToιτ RF Power (watts) of Coil Inductor 100 to 5000 watts RF Power (watts) of Wafer Pedestal 50 to 3000 watts Temperature (° C) of Platinum Electrode Wafer about 150° to about 500° C Platinum Etch Rate (.A/min) 200 to 6000 aA/min RF Frequency of Coil Inductor 100 K to 300 MHz RF Frequency of Wafer Pedestal 100 K to 300 MHz The produced platinum electrodes are separated by a distance or space having a dimension equal to or less than about 0.3 μm. Each of the platinum electrodes include a dimension having a value equal to or less than about 0.6 μm, preferably equal to or less than about 0.3 μm. More preferably, each of the platinum electrodes have a width equal to or less than about 0.3 μm, a length equal to or less than about 0.6 μm, and a height equal to or less than about 0.6 μm. The plasma of the etchant gas comprises a high density inductively coupled plasma. The etchant gas preferably comprises a noble gas selected from the group consisting of helium, neon, argon, .krypton, xenon, radon, and mixtures thereof. More preferably, the noble gas is selected from the group consisting of helium, neon, argon, and mixtures thereof. Most preferably, the noble gas is argon. As was previously indicated, the etclmt gas of the high density inductively coupled plasma most preferably comprises, or preferably consists of or consists essentially of, chlorine, .argon, and BC1 3 and/or HBr. The present invention further accomplishes its desired objects by broadly providing a method of manufacturing a semiconductor device comprising the steps of: a) forming a patterned resist layer, a mask layer and a platinum electrode layer on a substrate having circuit elements formed thereon; b) etching a portion of the mask layer including employing a plasma of an etchant gas to break through and to remove the portion of the mask layer from the platinum electrode layer to produce the substrate supporting the patterned resist layer, a residual mask layer, and the platinum electrode layer; c) removing the resist layer of step (b) to produce the substrate supporting the residual mask layer and the platinum electrode layer; d) heating the substrate of step (c) to a temperature greater than about 150° C; and e) etching the platinum electrode layer of step (d) including employing a high density plasma of an etchant gas comprising a halogen gas (e.g., chlorine) and a noble gas (e.g., argon) to produce a semiconductor device having at least one platinum electrode. The present invention also further accomplishes its desired objects by broadly providing a method of etching a platinum electrode layer disposed on a substrate comprising the steps of: a) providing a substrate supporting a platinum electrode layer, a protective layer on the platinum electrode layer, and a mask layer on the protective layer, and a patterned resist layer on the mask layer; b) etching a portion of the mask layer including employing a plasma of an etchant gas to break through and to remove the portion of the mask layer from the protective layer to expose part of the protective layer and to produce the substrate supporting the platinum electrode layer, the protective layer on the platinum electrode layer, a residual mask layer on the platinum electrode layer, and the patterned resist layer on the residual mask layer; c) removing the patterned resist layer from the residual mask layer of step (b) to produce the substrate supporting the platinum electrode layer, the protective layer on the platinum electrode layer, and the residual mask layer on the protective layer; d) heating the substrate of step (c) to a temperature greater than about 150° C; e) etching the exposed part of the protective layer to expose part of the platinum electrode layer and to produce the substrate supporting the platinum electrode layer, a residual protective layer on the platinum electrode layer, and the residual mask layer on the residual protective layer; and f) etching the exposed part of the platinum electrode layer of step (e) including employing a high density plasma of an etchant gas comprising a halogen gas (e.g., chlorine) and a noble gas (e.g., argon) to produce the substrate supporting an etched platinum electrode layer having the residual protective layer on the etched platinum electrode layer, and the residual mask layer on the residual protective layer. The patterned resist layer is removed from the residual mask layer before heating the substrate to a temperature greater than about 150° C because such high temperatures would destroy the resist layer. The residual mask layer may be removed from the platinum electrode layer either before or after heating of the substrate to a temperature greater than about 150° C, and during or after the platinum etching step. The platinum electrode layer is part of or is contained in a platinum electrode wafer. The purpose of the protective layer is to ensure the adhesion between the mask layer and the platinum layer and also to maintain the platinum profile of the platinum electrode layer, especially during the platinum etching process of the present invention. Preferably, the residual protective layers are removed from the etched platinum electrodes after the platinum etching step. As previously indicated, etching of the platinum electrode layer to produce the platinum electrodes of the present invention is performed in a high density plasma chamber. The platinum etching step employs a high density plasma of an etchant gas preferably consisting of, or consisting essentially of, a halogen gas (e.g., chlorine), a noble gas (i.e., argon) and HBr and/ or BC1 3 . The high density plasma chamber possesses a separate control for ion flux and a separate control for ion energy. As previously indicated, the ion density of the high density plasma in the high density plasma chamber is greater than about 10 9 /cm 3 . The high density plasma chamber for the method of manufacturing a semiconductor device and for the method of etching a platinum electrode layer disposed on a substrate includes a coil inductor and a wafer pedestal; and the platinum etching step in both of the methods is performed in the high density plasma chamber under the following previously mentioned process conditions: Process Parameters Etchant Gas Flow 50 to 500 seem Halogen Gas (e.g., Cl 2 ) about 10% to about 90% by vol. Noble Gas (e.g., argon) about 5% to about 80% by vol. HBr and/or BC1 3 about 4% to about 25% by vol. Pressure, mTorr 0J to 300 milliTorr RF Power (watts) of Coil Inductor 100 to 5000 watts RF Power (watts) of Wafer Pedestal 50 to 3000 watts Temperature (° C) of Platinum Electrode Wafer about 150° to about 500° C Platinum Etch Rate (.A/min) 200 to 6000 .A/min RF Frequency of Coil Inductor 100 K to 300 MHz RF Frequency of Wafer Pedestal 100 K to 300 MHz The present invention yet also further accomplishes its desired objects by broadly providing a semiconductor device, more specifically a capacitance structure, comprising a substrate, and at least two platinum electrodes supported by the substrate. The platinum electrodes have a platinum profile equal to or greater than about 85°, preferably equal to or greater than about 87°, more preferably equal to or greater than about 88.5°. The platinum electrodes are separated by a distance or space having a dimension equal to or less than about 0.3 μm. Each of the platinum electrodes include a dimension having a value equal to or less than about 0.6 μm, preferably equal to or less than about 0.3 μm. More preferably, each of the platinum electrodes have a width equal to or less than about 0.3 μm, a length equal to or less than about 0.6 μm, and a height equal to or less than about 0.6 μm. It is therefore an object of the present invention to provide a method for etching a platinum layer disposed on a substrate. It is another object of the present invention to provide a method of manufacturing a semiconductor device. It is also another object of the present invention to provide a method of manufacturing a capacitance structure. It is yet another object of the present invention to provide a capacitance structure. It is also yet another object of the present invention to provide a semiconductor device. These, together with the various ancillary objects and features which will become apparent to those skilled in the an as the following description proceeds, are attained by these novel methods, and semiconductor devices, a preferred embodiment thereof shown with reference to the accompanying drawings, by way of example only, wherein: BWEF DESCRIPΗON OF THE DRAWINGS Fig. 1 is a side elevational view of a semiconductor wafer having a semiconductor substrate, a barrier layer disposed on the semiconductor substrate, a platinum electrode layer disposed on the barrier layer, a mask layer disposed on the platinum electrode layer, and a patterned resist disposed on the insulation layer; Fig. 2 is a side elevational view of the semiconductor wafer of Fig. 1 additionally including a protective layer disposed on the platinum electrode layer between the m.ask layer and the platinum electrode layer; Fig. 3 is a vertical sectional view of a prior art plasma processing apparatus including a plasma etching reactor with an electromagnetic unit for enhancing a plasma; Fig. 4 is a diagram of a flux produced by a magnetic field and illustrated as rotating around a center axis; Fig. 5 is a side elevational view of the semiconductor wafer of Fig. 1 after etching and removing a portion of the mask layer from the surface of the platinum electrode layer to expose the platinum electrode layer; Fig. 6 is a side elevational view of the semiconductor wafer of Fig. 2 after etching and removing a portion of the mask layer from the surface of the protective layer to expose the protective layer; Fig. 7 is a side elevational view of the semiconductor wafer of Fig. 5 after the patterned resist layer has been removed from a portion of the mask layer with the removed patterned resist layer being represented as broken lines; Fig. 8 is a side elevational view of the semiconductor wafer of Fig. 6 after etching and removing a portion of the protective layer off of the surface of the platinum layer, and after removing the patterned resist layer from a portion of the mask layer with the removed patterned resist layer being represented as broken lines; Fig. 9 is a side elevational view of the semiconductor wafer of Fig. 7 after the platinum electrode layer has been etched to produce an etched platinum electrode layer; Fig. 10 is a side elevational view of the semiconductor wafer of Fig. 8 after the platinum electrode layer has been etched to produce an etched platinum electrode layer; Fig. 11 is a side elevational view of the semiconductor wafer of Fig. 7 after the platinum electrode layer has been etched to produce an etched platinum electrode layer with a residual mask layer on top thereof; Fig. 12 is a side elevational view of the semiconductor wafer of Fig. 8 after the platinum electrode layer has been etched to produce an etched platinum electrode layer with a residual mask layer on top of the residual protective layer; Fig. 13 is a side elevational view of the semiconductor wafer of Fig. 11 with the residual mask layer removed from the surface of the etched platinum electrode layer; Fig. 14 is a side elevational view of the semiconductor wafer of Fig. 12 with the residual mask layer and the residual protective layer removed from the surface of the etched platinum electrode layer; Fig. 15 is a side elevational view of semiconductor wafer of Fig. 11 after the residual mask layer has been removed from the surface of the etched platinum electrode layer and with the barrier layer having been etched; Fig. 16 is a side elevational view of semiconductor wafer of Fig. 12 after the residual mask layer and the residual protective layer have been removed from the surface of the etched platinum electrode layer and with the barrier layer having been etched; Fig. 17 is a simplified cut-away view of an inductively coupled RF plasma reactor which may be employed in etching the platinum electrode layer to produce a semiconductor device; Fig. 18 is a simplified cut-away view of another inductively coupled .RF plasma reactor which may be employed in etching the platinum electrode layer to produce a semiconductor device; Fig. 19 is a picture showing an elevational view of a test semiconductor wafer for Example I after the platinum electrode layer was etched in accordance with the process conditions listed in Example I; Fig. 20 is a picture showing an elevational view of the test semiconductor wafer of Fig. 19 after the oxide mask was removed; Fig. 21 is a drawing representing the elevational view in the picture of Fig. 19 with the respective parts identified by a reference numeral; Fig. 22 is a drawing representing the elevational view in the picture of Fig. 20 with the respective parts identified by a reference numeral; Fig. 23 is a picture showing an elevational view of a test semiconductor wafer for Example II after the platinum electrode layer was etched in accordance with the process conditions listed in Example II; and Fig. 24 is a drawing representing the elevational view on the picture of Fig. 23 with the respective parts identified by a reference numeral. DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION Refeiring in detail now to the drawings wherein similar parts of the present invention are identified by like reference numerals, there is seen in Fig. 1 a wafer, generally illustrated as 10, having a semiconductor substrate, generally illustrated as 12. The semiconductor substrate 12 includes regions of circuit elements which do not appear in the drawings, but are well .known to those skilled in the .art. A barrier layer 14 is disposed over the semiconductor substrate 12 and a platinum layer, generally illustrated as 15, is disposed over the barrier layer 14. The platinum layer 15 is preferably a platinum electrode layer 16 as shown in Fig. 1. Because the platinum electrode layer 16 is a preferred platinum layer 15, the remaining description of the present invention will use only the term "platinum electrode layer 16" in describing the present invention. However, it is to be understood that wherever "platinum electrode layer 16" is stated hereinafter, it is to also have the equivalence of "platinum layer 15" for purposes of the present invention. Because the platinum electrode layer 16 easily diffuses or reacts with certain elements (e.g. a poly-Si plug) within the semiconductor substrate 12, the barrier layer 14 is required between the platinum electrode layer 16 and the semiconductor substrate 12. The barrier layer 14 also functions as an adhesive for coupling the semiconductor substrate 12 to the platinum electrode layer 16. A mask 18 is disposed over the platinum electrode layer 16 and a patterned resist (i.e. a photoresist), generally illustrated as 20, is selectively positioned on the mask layer 18 as best shown in Fig. 1. As best shown in Fig. 1, the patterned resist 20 includes a plurality of resist members 20a, 20b, 20c, and 20d. In another preferred embodiment of the invention as shown in Fig. 2, a protective layer 22 is disposed between the platinum electrode layer 16 and the mask layer 18. The barrier layer 14 may be any suitable barrier layer which is capable of dually functioning as an adhesive and a diffusion barrier to the platinum electrode layer 16. The barrier layer 14 may be of any suitable thickness. Preferably, the barrier layer 14 comprises titanium and/or a titanium alloy, such as TiN, and possesses a thickness ranging from about 50 Angstroms to about 600 Angstroms, more preferably from about 200 Angstroms to about 400 Angstroms, most preferably about 300 .Angstroms. The barrier layer 14 is preferably disposed on the semiconductor substrate 12 by the RF magnetron sputtering method. The platinum electrode layer 16 is used as the electrode material because it is inert to oxidation which tends to occur in the subsequent high temperature processes of depositing the high dielectric constant ferroelectric materials. The platinum electrode layer 16 is also used as the electrode material because platinum is a good electric conductor. The thickness of the platinum electrode layer 16 would depend upon the end use of the semiconductor or capacitance device which is to contain the platinum electrode layer 16. Typically, the thickness of the platinum electrode layer 16 ranges from about 500 Angstroms to about 4000 .Angstroms, more preferably from about 1000 Angstroms to about 3000 Angstroms, most preferably about 2000 .Angstroms. The platinum electrode is preferably disposed on the barrier layer 14 by the RF magnetron sputtering method. The mask layer 18 may be any suitable insulation or metallic material that is capable of being etched in accordance with the procedure described hereinafter such that all traces of the mask layer 18 are essentially removed from the surface platinum electrode layer 16 except that portion (identified as "18a," "18b," "18c," and "18d" below) of the mask layer 18 remaining under the patterned resist 20. The mask layer 18 may also be of any suitable thickness. Preferably, the mask layer 18 comprises silicon dioxide (SiO 2 ) and/or silicon nitride (Si 3 N 4 ) or any other suitable dielectric material. A preferred thickness for the mask layer 18 ranges from about 1000.Angstroms to about 9000.Angstroms, more preferably from about 3000 Angstroms to about 7000 .Angstroms, most preferably about 5000 .Angstroms. The mask layer 18 is preferably disposed on the platinum electrode layer 16 by chemical vapor deposition. The patterned resist 20 (i.e. the photoresist 20, including resist members 20a, 20b, 20c .and 20d) may be any suitable layer of material(s) that is capable of protecting any underlying material (e.g. the mask layer 18) from being etched duiing the etching process of the present invention. Suitable materials for the patterned resist 20 include resist systems consisting of novolac resin and a photoactive dissolution inhibitor (all based on Suss's discovery). Other suitable materials for the resist 20 are listed in an article from the July 1996 edition of Solid State Technology entitled "Deep-UV Resists: Evolution and Status" by Hiroshi Ito. The patterned resist 20 may have any suitable thickness; preferably, the thickness of the patterned resist 20 ranges from about 0.3 μm to about 1.40 μm, more preferably from about 0.5 μm to about 1.2 μm, most preferably about 0.8 μm. The patterned resist 20 is preferably disposed on the mask layer 18 by the spin coating method. The protective layer 22 in the embodiment of the invention depicted in Fig. 2 is for protecting the corners (identified as "16g" below) of an etched platinum electrode layer (generally identified as "16e" below) during the overetching process of the present invention. -Another purpose of the protection layer 27 is for providing good adhesion to the mask layer 18 and the platinum electrode layer 16. The protective layer 22 may comprise any suitable materials or chemicals, such as titanium and/or titanium nitride etc., and may be conveniently disposed on the surface of the platinum electrode layer 16, such as by the RF magnetron sputtering method. The thickness of the protective layer 22 may be any suitable thickness, preferably ranging from about 50 .Angstroms to about 1000 Angstroms, more preferably ranging from about 100 Angstroms to about 600 Angstroms, most preferably about 300 Angstroms. In order to form or produce a semiconductor or capacitance device from the multilayered structure of Fig. 1 or Fig. 2, the multilayered structure is initially placed in a suitable plasma processing apparatus to break through .and remove or etch away from the surface of platinum electrode layer 16 the mask layer 18, except those mask layers 18a, 18b, 18c and 18d that are respectively below the resist members 20a, 20b, 20c and 20d, as best shown in Fig. 5, or as best shown in Fig. 6 if the embodiment of the invention depicted in Fig. 2 is being employed. A suitable prior art plasma processing apparatus is shown in Fig. 3 and described in U.S. Patent No. 5,188,704 to Babie et al, fully incorporated herein by reference thereto as if repeated verbatim immediately hereinafter. The plasma process apparatus of Fig. 3 comprises a plasma reactor, generally illustrated as 30 and including walls, generally illustrated as 31 for forming and housing a reactor chamber 32 wherein a plasma 33 of neutral (n) particles, positive (+) particles, and negative (-) particles are found. Walls 31 include cylindrical wall 54 and cover 56. Plasma processing gases are introduced via inlets 34 into reactor chamber 32. Plasma etching gases are introduced into chamber 32 through inlets 34-34. A water cooled cathode 36 is connected to an RF power supply 38 at 13.56 MHz. An anode 39 is connected to the walls 31 which are grounded by line 40. Helium gas is supplied through passageway 50 through cathode 36 to the space beneath wafer 10 which is supported peripherally by lip seal 52 so that the helium gas cools the wafer 10. The wafer 10 is supported by a wafer support 46 that includes a plurality of clamps (not shown) which hold down the upper surface of wafer 10 at its periphery, as is well known to those skilled in the art. A pair of helmholtz configured electromagnetic coils 42 and 43 provide north and south poles within the chamber 32 and are disposed at opposite ends of the lateral cylindrical wall 54 and the walls 31. The electromagnetic coils 42 and 43 provide a transverse magnetic field with the north and south poles at the left and right providing a horizontal magnetic field axis parallel to the surface of the wafer 10. The transverse magnetic field is applied to slow the vertical velocity of the electrons which are accelerated radially by the magnetic field as they move towards the wafer 10. Accordingly, the quantity of electrons in the plasma 33 is increased by means of the transverse magnetic field .and the plasma 33 is enhanced as is well known to these skilled in the art. The electromagnetic coils 42 and 43 which provide the magnetic field are independently controlled to produce a field intensity orientation which is unifoim. The field can be stepped angularly around the wafer 10 by rotating the energization of the electromagnetic coils 42 and 43, sequentially. The transverse magnetic field provided by the electromagnetic coils 42 and 43 is directed parallel to the surface of the wafer 10 being treated by the plasma 33, and the cathode 36 of the plasma reactor 30 increases ionization efficiently of the electrons in the plasma 33. This provides the ability to decrease the potential drop across the sheath of the cathode 36 and to increase the ion current flux present on the surface of the wafer 10, thereby permitting higher rates of etching without requiring higher ion energies to achieve the result otherwise. The preferred magnetic source employed to achieve magnetically enhanced reactive ion etcher (MERIE) used in practicing the present invention is a variable rotational field provided by the electromagnetic coils 42 and 43 arranged in a Helmholtz configuration. The electromagnetic coils 42 and 43 are driven by 3-phase AC cuirents. The magnetic field with Flux B is parallel to the wafer 10, and perpendicular to the electrical field as shown in Fig. 4. Referring to Fig. 4, the vector of the magnetic field H which produces flux B is rotating around the center axis of the electrical field by varying the phases of current flowing through the electromagnetic coils 42 and 43 at a typical rotational frequency of 0.01 to 1 Hz, particularly at 0.5 Hz. The strength of the magnetic flux B typically varies from 0 Gauss to about 150 Gauss and is determined by the quantities of the currents supplied to the electromagnetic coils 42 and 43. While Fig. 3 illustrates one plasma processing apparatus that is suitable for removing the mask layer 18 (except mask layers 18a, 18b, 18c and 18d), it is to be understood that other plasma etchers may be employed, such as electron cyclotron resonance (ECR), helicon resonance or inductively coupled plasma (ICP), triode etchers, etc. The plasma 33 may employ any suitable etchant gas to break through (i.e. to clean and etch away) the mask layer 18 except those mask layers 18a, 18b, 18c and 18d that are respectively below the resist members 20a, 20b, 20c and 20d, as best shown Figs. 5 and 6. For example, if the mask layer 18 contains silicon oxide, suitable etchant gas(es) may be selected from the group consisting of fluorine-containing gases (e.g. CHF 3 , SF 6 , C 2 F 6 , NF 3 , etc.), bromine-containing gases (e.g. HBr, etc.), chlorine-containing gases (e.g. CHClj, etc.), rare or noble gases (e.g. argon, etc.), and mixtures thereof. Preferably, the etchant does not include an oxidant, such as oxygen, since the puipose of this step is to remove the mask layer 18 (except those mask layers 18a, 18b, 18c and 18d which are respectively protected by resist members 20a, 20b, 20c and 20d) and not to remove the patterned resist 20. More preferably, the etchant gas comprises from about 20% by volume to about 40% by volume CHF 3 and from about 60% by volume to about 80% by volume argon. The preferred reactor conditions for a suitable plasma processing apparatus (such as the plasma processing apparatus of Fig. 3) in removing the mask layer 18 (except mask layers 18a, 18b, 18c and 18d) are as follows: Pressure 10-150 mTorr RF Power 500-1500 watts Rotational Magnetic Field 25-70 Gauss Temperature of Wafer 25-100 ' C Mask L . ayer 18 Etch Rate 2000-10,000 .Angstroms/min The selectivity of mask layer 18 to patterned resist 20 is better than 3:1, depending on the materials employed for the mask layer 18 and the patterned resist 20. More generally, the process parameters for removing the mask layer 18 in a suitable plasma process apparatus (such as the plasma processing apparatus of Fig. 3) fall into ranges as listed in the following Table III and based on flow rates of the gases CHF 3 and Ar also listed in the following Table III: TABLE HI Process Broad Preferred Gas Flow, seem CHF, 10 to 50 (20 to 40% by vol.) 20 to 40 Ai 50 to 90 (60 to 80% by vol.) 60 to 80 Pressure, mT 10 to 250 10 to 150 13.56 MHz RF Power (Watts) 500 to 2500 500 to 1500 Temperature (°C) of Wafer 10 to 120 25 to 100 Magnetic Field Gauss 10 to 120 25 to 70 For the embodiment of the invention depicted in Fig. 2 wherein the protective layer 22 is disposed on the platinum electrode layer 16 between the mask layer 18 and the platinum electrode layer 16, the protective layer 22 has to be removed or etched after removal of the mask layer 18 in order to expose the platinum electrode layer 16. The protective layer 22 may be etched and removed by any suitable manner and/or with any suitable plasma processing apparatus (such as with the plasma processing apparatus of Fig. 3) including the plasma 33 employing a suitable etchant gas to break through and etch away the protective layer 22 except those protective layers 22a, 22b, 22c and 22d (see Figs. 6 and 8) immediately below mask layers 18a, 18b, 18c and 18d, respectively. For example, if TiN is used as the protective layer 22, suitable etchant gas(es) may be selected from the group consisting of Cl 2 , HBr, BC1 3 , noble gases (e.g., Ax), and mixtures thereof. Preferably and in one embodiment of the present invention, the etchant gas for breaking through and etching away the protective layer 22, except protective layers 22a, 22b, 22c and 22d, comprises from about 20% by volume to about 60% by volume Cl 2 , from about 20% by volume to about 60% by volume HBr and/or BC1 3 , and from about 10% by volume to about 30% by volume of a noble gas which is preferably Ar. Suitable reactor conditions for a suitable plasma processing apparatus (such as the plasma processing apparatus of Fig. 3) to remove the protective layer 22 (except protective layers 22a, 22b, 22c and 22d) may be the s-arne as those previously stated reactor conditions for the removal of the mask layer 18 (except mask layers 18a, 18b, 18c and 18d). It is to be understood that other plasma etchers may be employed to remove the protective layer 20, such as ECR, ICP, Helicon Resonance, etc. As will be further explained below, the protective layers 22a, 22b, 22c and 22d are for protecting the corners (identified as "16g" below) of an etched platinum electrode layer (generally identified as "16e" below) during the etching process of the present invention. It is believed that the protective layers 22a, 22b, 22c and 22d not only protect the corners of an etched platinum electrode layer duiing the etching process, but also assist in maintaining an existing platinum profile and/or improves a platinum profile. In another embodiment of the present invention, the protective layer 22 (except protective layers 22a, 22b, 22c and 22d) may be etched and removed by the high temperatures and etchant gases employed in the platinum-etching process of the present invention. More specifically and as will be further explained below, because the platinum electrode layer 16 is preferably etched under the following process conditions in a high density plasma chamber containing a high density inductively coupled plasma: Process Parameters Etchant Gas flow 50 to 500 seem Halogen Gas (e.g., Cl 2 ) 20% to 95% by vol. Noble Gas (e.g., Ar) 5% to 80% by vol. Pressure, mTorr 0J to 300 milliTorr RF Power (watts) of Coil Inductor 100 to 5000 watts RF Power (watts) of Wafer Pedestal 50 to 3000 watts Temperature (°C) of Platinum Electrode Wafer about 150 to about 500°C Platinum Etch Rate (A/min), 200 to 6000 .A/min RF Frequency of Coil Inductor 100 K to 300 MHz RF Frequency of Wafer Pedestal 100 K to 300 MHz the protective layer 22 may be etched and removed under the same foregoing conditions. Thus, the same apparatus and process conditions may be employed to etch and remove selective parts of the protective layer 22, as well as to etch the platinum electrode layer 16. In another preferred embodiment of the present invention and as will be also further explained below, the protective layer 22 and the platinum electrode layer 16 may be removed and etched respectively in a high density plasma chamber containing a high density inductively coupled plasma under the following process conditions: Process Parameters Etchant Gas flow 50 to 500 seem Halogen Gas (e.g., Cl 2 ) 10% to 90% by vol. Noble Gas (e.g., Ar) 5% to 80% by vol. HBr and/or BC1 3 45% to 25% by vol. Pressure, mTorr 0J to 300 milliToiT RF Power (watts) of Coil Inductor 100 to 5000 watts RF Power (watts) of Wafer Pedestal 50 to 3000 watts Temperature (°C) of Platinum Electrode Wafer about 150 to 500°C Platinum Etch Rate (A/min) 200 to 6000 A/min RF Frequency of Coil Inductor 100 K to 300 MHz RF Frequency of Wafer Pedestal 100 K to 300 MHz After selective parts of the mask layer 18 have been etched away from the surface of the platinum electrode layer 16 to expose the latter and such that the only remnants of the mask layer 18 are the mask layers 18a, 18b, 18c and 18d situated immediately below the resist members 20a, 20b, 20c, and 20d, respectively, the resist members 20a, 20b, 20c and 20d are to be removed. The resist members 20a, 20b, 20c and 20d may be removed at any suitable time, preferably before the etching of the platinum electrode layer 16 and before the heating of the semiconductor substrate 12 to a temperature greater than about 150° C. The same would hold true with respect to the embodiment of the invention illustrated in Figs. 2, 6 and 8 in that after selective parts of the protective layer 22 have been etched away from the surface of the platinum electrode layer 16 to expose the latter and such that the only renmants of the protective layer 22 are the protective layers 22a, 22b, 22c and 22d situated respectively immediately below the πrnsk layers 18a, 18b, 18c and 18d, the resist members 20a, 20b, 20c and 20d are to be removed. However, with respect to this embodiment of the present invention, the resist members 20a, 20b, 20c and 20d may be removed before the etching away of selective parts of the protective layer 22. .Alternatively, the resist members 20a, 20b, 20c and 20d may be removed after (or simultaneously during) the removal of selective parts of the protective layer 22 and before the heating of the semiconductor substrate 12 to a temperature greater man about 150° C for purposes of etching the platinum electrode layer 16. Typically, at least a portion of the resist members 20a, 20b, 20c and 20d would be removed while selective parts of the protective layer 22 are being etched away to expose the platinum electrode layer 16 that is not superimposed by the protective layers 22a, 22b, 22c and 22d. The resist members 20a, 20b, 20c and 20d may be removed in any suitable manner such as by using oxygen plasma ashing which is well known to those skilled in the art. The resist members 20a, 20b, 20c and 20d may be respectively stripped from the mask layers 18a, 18b, 18c and 18d with any suitable plasma processing apparatus, such as the plasma processing apparatus shown in Fig. 3 and employing a plasma containing an etchant gas comprising oxygen. The resist members 20a, 20b, 20c and 20d have been respectively removed from the mask layers 18a, 18b, 18c and 18d in an advanced strip passivation (ASP) chamber of a plasma processing apparatus sold under the trade mark metal etch MJCP Centura to Applied Materials, Inc. 3050 Bowers Avenue, Santa Clara, CA 95054-3299. In stripping the resist members 20a, 20b, 20c and 20d from the mask layers 18a, 18b, 18c and 18d, respectively, the ASP chamber may employ microwave downstream O 2 /N 2 plasma with the following recipe: 120 seconds, 250°C, 1400W, 3000cc O 2 , 300cc N 2 and 2Torr. After the platinum electrode layer 16 has been exposed as represented in Figs. 7 and 8, it is etched to develop a submicron pattern with a platinum profile. As will be further stated below, before the platinum electrode layer 16 is etched, the semiconductor substrate 12 supporting the platinum electrode layer 16 is heated to a temperature greater than about 150° C, preferably greater than about 150° C up to about 500° C, more preferably from about 200° C to about 400° C, most preferably from about 250° C to about 350° C. The semiconductor substrate 12 is heated by the pedestal which supports the wafer 10 during the platinum etching process. The platinum electrode layer 16 may be etched in any suitable plasma processing apparatus, such as in the reactive ion etch (RIE) plasma processing apparatus sold under the trademark AME8100 Etch™, or under the trademark Precision Etch 5000™, or under the trademark Precision Etch 8300™, all trademarks owned by Applied Materials Inc., 3050 Bowers Avenue, Santa Clara, CA 95054-3299. Another suitable plasma processing apparatus for etching the platinum electrode layer 16 is that plasma processing apparatus sold under the trademark Metal Etch DPS Centura™ also owned by Applied Materials, Inc. It is also to be understood that other plasma etchers may be employed, such as ECR, ICP, Helicon Resonance, etc. A suitable plasma processing apparatus for etching the platinum electrode layer 16 employs a plasma of an etchant gas, which is capable of producing good platinum profiles (e.g. platinum profiles equal to or greater than about 85 degrees, preferably equal to or greater than about 87 degrees, more preferably equal to or greater than about 88.5 degrees). The etchant gas broadly comprises a halogen containing gas, such as a halogen gas (e.g., fluorine, chlorine, bromine, iodine, and astatine) and a noble gas such as helium, neon, argon, .krypton, xenon, and radon. Preferably, the etchant gas comprises or consists of or consists essentially of a halogen (preferably chlorine) and a noble gas selected from the group consisting of helium, neon, and argon. The noble gas is preferably argon. The etchant gas more specifically comprises preferably from about 20% by volume to about 95% by volume of the halogen gas (i.e., chloiϊne) and from about 5% by volume to about 80% by volume of the noble gas (i.e., argon); more preferably from about 40% by volume to about 80% by volume of the halogen gas (i.e., chlorine) and from about 20% by volume to about 60% by volume of the noble gas (i.e., argon); most preferably from about 55% by volume to about 65% by volume of the halogen gas (i.e., chlorine) .and from about 35% by volume to about 45% by volume of the noble gas (i.e., argon). In another preferred embodiment of the invention, the etcliant gas comprises, preferably consists of or consists essentially of, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group consisting of HBr, BC1 3 and mixtures thereof. The etchant gas more specifically comprises, or consists of or consists essentially of, from about 10% by volume to about 90% by volume of the halogen gas (i.e., chlorine) and from about 5% by volume to about 80% by volume of the noble gas (i.e., argon) and from about 4% by volume to about 25% by volume of HBr and/or BC1 3 ; preferably from about 40% by volume to about 70% by volume of the halogen gas (i.e., chlorine) and from about 25% by volume to about 55% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 20% by volume of HBr and/or BC1 3 ; and more preferably from about 50% by volume to about 60% by volume of the halogen gas (i.e., chlorine) .and from about 35% by volume to about 45% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 15% by volume of HBr .and/or BC1 3 . The etchant gas flow rate .ranges from about 50 seem to about 500 seem. HBr and/or BC1 3 are for removal of platinum residue during etching of the platinum electrode layer 16. Plasmas containing argon are .known to have a high energetic ion concentration and are often used for physical sputtering. The sputtering effect due to the ions is a function of the accelerating potential which exist between the plasma and the sample. The reactor conditions for a suitable plasma processing apparatus, such as the plasma processing apparatus of Fig. 3, in etching the platinum electrode layer 16 are as follows: Pressure 0J -300 mTorr RF Power 100-5000 watts Rotational Magnetic Field 20-100 Gauss Temperature of Wafer about 150-about 500 * C Platinum Layer 16 Etch Rate 200-6000 Angstroms/min The selectivity of platinum electrode layer 16 to mask 18 is better than 2:1, depending on the materials employed for the mask layer 18. More generally, the process parameters for etching the platinum electrode 16 in a suitable plasma processing apparatus, such as the plasma processing apparatus of Fig. 3, fall into ranges as listed in the following Table IV and based on the flow rate of etchant gas as also listed in Table IV below: TABLE IV Process Broad Preferred Optimum Gas Flow, seem Etchant Gas 50 to 500 75 to 250 100 to 200 Pressure, mT 20 to 2000 30 to 300 50 to 150 13.56 MHz RF Power (Watts) 50 to 3000 500 to 2000 700 to 1200 Temperature (°C) of Wafer 150 to 500 200 to 400 250 to 350 Magnetic Field Gauss 0 to 140 20 to 100 60 to 80 As previously indicated, a more preferred etchant gas for etching the platinum electrode layer 16 is a mixture of chloiine and argon, or a mixture of chlorine, argon and HBr and/or BC1 3 . If the etchant gas is a mixture of chlorine and argon (i.e., from about 20% by volume to about 95% by volume chloiine and from about 5% by volume to about 80% by volume argon), or a mixture of chloiine, argon and HBr and/or BC1 3 (i.e., from about 10% by volume to about 90% by volume chlorine and from about 5% by volume to about 80% by volume argon and from about 4% by volume to about 25% by volume HBr and/or BC1 3 ), and if the semiconductor substrate 12 is heated to a temperature greater than about 150 °C, preferably to a temperature ranging from about 150°C to about 500°C, the plasma processing apparams for etching the platinum electrode layer 16 etches the platinum electrode layer 16 in a high density plasma of the etchant gas at a high platinum etch rate (i.e. an etch rate higher than 1000 A/min) and produces an etched platinum electrode layer, generally illustrated as 16e (as best shown in Figs. 9 and 10). The etched platinum electrode layer 16e includes etched platinum electrode layers 16a, 16b, 16c and 16d having corners 16g and sidewalls 16s and an excellent platinum profile; that is, a platinum profile where the angle o of the sidewalls 16s (as also best shown in Figs. 9 .and 10) with respect to a horizontal plane is equal to or greater than about 85 degrees, preferably equal to or greater than about 87°, and more preferably equal to or greater than about 88.5°. The platinum electrodes are separated by a distance or space having a dimension equal to or less than about 0.3 μm. Each of the platinum electrodes include a dimension having a value equal to or less than about 0.6 μm, preferably equal to or less than about 0.3 μm. More preferably, each of the platinum electrodes have a width equal to or less than about 0.6 μm, and a height equal to or less than about 0.6 μm. It has also been discovered that the etched platinum electrode layer 16e (i.e., etched platinum electrode layers 16a, 16b, 16c and 16d) has essentially no wall-like structures extending up from the edges of the platinum region. These wall-like structures are frequently referred to as "veils" or "fences" or "rabbit ears." Therefore, the method of the present invention produces etched platinum electrode layers 16a, 16b, 16c and 16d which are essentially veil-less. Because the produced etched platinum electrode layers 16a, 16b, 16c and 16d are essentially veil-less and have no "fences" or "rabbit ears," they are ideally suited for receiving a dielectric BST or PZT layer and functioning as electrodes in a semiconductor device (i.e., a capacitance structure). The high density plasma of the present invention may be defined as a plasma of the etchant gas of the present invention having an ion density greater than about 10 9 /cm 3 , preferably greater than about 10 π /cm 3 . The source of the high density plasma may be any suitable high density source, such as electron cyclotron resonance (ECR), helicon resonance or inductively coupled plasma (ICP)-type sources. All three are in use on production equipment today. The main difference is that ECR and helicon sources employ .an external magnetic field to shape and contain the plasma, while ICP sources do not. The high density plasma for the present invention is more preferably produced or provided by inductively coupling a plasma in a decoupled plasma source etch chamber, such as that sold under the trademark DPS™ owned by Applied Materials, Inc. which decouples or separates the ion flux to the wafer 10 and the ion acceleration energy. The design of the etch chamber provides fully independent control of ion density of an enlarged process window. This is accomplished by producing plasma via an inductive source. While a cathode within the etch chamber is still biased with rf electric fields to determine the ion acceleration energy, a second rf source (i.e. an inductive source) determines the ion flux. This second rf source is not capacitive (i.e. it does not use electric fields like the cathode) since a large sheath voltage would be produced, interfering with the cathode bias and effectively coupling the ion energy and ion flux. The inductive plasma source couples rf power through a dielectric window rather than an electrode. The power is coupled via rf magnetic fields (not electric fields) from rf current in a coil. These rf magnetic fields penetrate into the plasma and induce rf electric fields (therefore the term "inductive source") which ionize and sustain the plasma. The induced electric fields do not produce large sheath voltages like a capacitive electrode and therefore the inductive source predominantly influences ion flux. The cathode bias power plays little part in determining ion flux since most of the rf power (typically an order of magnitude less than the source power) is used in accelerating ions. The combination of an inductive plasma source and a capacitive wafer bias allows independent control of the ion flux .and ion energy reaching the wafer 10 in the etch chamber, such as the DPS™ brand etch chamber. DPS™ brand etch chambers for producing the high density plasma of the present invention for etching the platinum electrode layer 16 to produce the etched platinum electrode layers 16a, 16b, 16c and 16d may be any of the DPS™ brand etch chambers of the inductively coupled plasma reactor disclosed in co-pending U.S. Patent application Serial No. 08/389,889 filed February 15, 1995, entitled "RF PLASMA REACTOR WITH HYBRID CONDUCTOR AND MULTI-RADIUS DOME CEILING" and assigned to the present assignee and fully incorporated herein by reference thereto as if repeated verbatim immediately hereinafter. Referring now to Figs. 17 and 18 for two (2) embodiments of an inductively coupled plasma reactor from co-pending application Serial No. 08/389,889 there is seen an inductively coupled RF plasma reactor generally illustrated as 90, having a reactor chamber, generally illustrated as 92, wherein a high density plasma 94 of neutral (n) particles, positive (+) particles, and negative (-) particles are found. The reactor clumber 92 has a grounded conductive cylindrical sidewall 60 and a dielectric ceiling 62. The inductively coupled RF plasma reactor 90 further comprises a wafer pedestal 64 for supporting the (semiconductor) wafer 10 in the center of the chamber 92, a cylindrical inductor coil 68 surrounding an upper portion of the chamber 92 beginning near the plane of the top of the wafer 10 or wafer pedestal 64 and extending upwardly therefrom toward the top of the chamber 92, an etching gas source 72 and gas inlet 74 for furnisliing an etching gas into the interior of the chamber 92, and a pump 76 for controlling the pressure in the chamber 92. The coil inductor 68 is energi^d by a plasma source power supply or RF generator 78 through a conventional active RF match network 80, the top winding of the coil inductor 68 being "hot" and the bottom winding being grounded. The wafer pedestal 64 includes an interior conductive portion 82 connected to the bias RF power supply or generator 84 and an exterior grounded conductor 86 (insulated from the interior conductive portion 82). Thus, the plasma source power applied to the coil inductor 68 by the RF generator 78 and the DC bias RF power applied to the wafer pedestal 64 by generator 84 are separately controlled RF supplies. Separating the bias and source power supplies facilitates independent control of ion density and ion energy, in accordance with well-known techniques. To produce high density plasma 94 as an inductively coupled pl∑tsma, the coil inductor 68 is adjacent to the chamber 92 and is connected to the RF source power supply or the RF generator 78. The coil inductor 68 provides the RF power which ignites .and sustains the high ion density of the high density plasma 94. The geometry of the coil inductor 68 can in large part determine spatial distribution of the plasma ion density of the high density plasma 94 within the reactor chamber 92. Uniformity of the plasma density spatial distribution of the high density plasma 94 across the wafer 10 is improved (relative to conical or hemispherical ceilings) by shaping the ceiling 62 in a multi-radius dome and individually determining or adjusting each one of the multiple radii of the ceiling 62. The multiple-radius dome shape in the particular embodiment of Fig. 17 somewhat flattens the curvature of the ceiling 62 around the center portion of the ceiling 62, the peripheral portion of the ceiling 62 having a steeper curvature. As illustrated in Fig. 18 the coil inductor 68 may be coupled to the RF power source 78, 80 in a mhror coil configuration that is known to those skilled in the art. In the mirror coil configuration of Fig. 18, the RF source 78, 80 is connected to the center winding of the coil inductor 68 while the top and bottom ends of the coil inductor 68 are both grounded. The mirror coil configuration has the advantage of reducing the maximum potential on the coil inductor 68. It has been discovered that by employing a high density plasma, such as the high density plasma 94 illustrated in Figs. 17 and 18, for etching the platinum electrode layer 16, and by heating the semiconductor substrate 12 to a temperature greater than about 150°C before conducting the etching operation under process parameters wliich are stated below, a semiconductor device is produced with platinum electrodes having a platinum profile with an angular value which is equal to or greater than about 85 degrees, more preferably equal to or greater than about 87 degrees, most preferably equal to or greater than about 88.5 degrees. The platinum electrodes are essentially veil-less; that is, they have no "fences" or "rabbit ears. " The platinum electrodes are preferably separated by a distance or space having a dimension equal to or less than about 0.3 μm. Each of the platinum electrodes include a dimension having a value equal to or less than about 0.6 μm, preferably equal to or less than about 0.3 μm. More preferably, each of the platinum electrodes have a width equal to or less than about 0.3 μm, a length equal to or less than about 0.6 μm, and a height equal to or less than about 0.6 μm. The preferred reactor conditions for a suitable inductively coupled RF plasma reactor, such as the inductively coupled RF pl∑isma reactor 90 in Figs. 17 and 18, in etching the platinum electrode layer 16 are as follows: Pressure 0.1 to 300 mTorr RF Power to Coil Inductor 100 to 5000 watts RF Power to Wafer Pedestal 50 to 3000 watts RF Frequency in Coil Inductor 100K to 300 MHz RF Frequency in Wafer Pedestal 100K to 300 MHz Temperature of Wafer 150 to 500° C Platinum Etch Rate 200 to 6000 Angstrom min More generally, the process parameters for etching the platinum electrode layer 16 in a suitable inductively coupled plasma reaαor, such as the induαively coupled plasma reaαor 90 in Figs. 17 and 18, fall into ranges as listed on the basis of flow rates of the gases, including the halogen gas(es) (i.e., Clj) and the noble gas(es) (i.e., argon), as listed in Table V below. TABLE V Process Broad Preferred Optimum Gas Flow, seem Cl 2 30 to 400 50 to 250 60 to 150 Ar 20 to 300 30 to 200 40 to 100 Pressure, mT 0.1 to 300 10 to 100 10 to 40 RF Power of Coil Induαor (Watts) 100 to 5000 650 to 2000 900 to 1500 RF Power of Wafer Pedestal (Watts) 50 to 3000 100 to 1000 150 to 400 Temperature of Wafer (°C) about 150 to about 200 to 400 250 to 350 500 Platinum Etch Rate (A/min) 200 to 6000 500 to 3000 1000 to 2000 RF Frequency of Coil Induαor 100 K to 300 MHz 400 K to 20 2 to 13.5 MHz MHz RF Frequency of Wafer Pedestal 100 K to 300 MHz 400 K to 20 400 K to 13.5 MHz MHz More generally further, and when the etchant gases are a mixture of the halogen gas(es) (i.e., chlorine), the noble gas(es) (i.e., argon), and HBr and/or BC1 3 , the process parameters for etching the platinum eleαrode layer 16 in a suitable induαively coupled plasma reaαor, such as the induαively coupled plasma reaαor 90 in Figs. 17 and 18, fall into the ranges as listed on the basis of flow rates of the gases, including the halogen gas(es) (i.e., Cl j ) and the noble gas(es) (i.e., Ar) and HBr and/or BC1 3 , as listed in Table VI below: TABLE VI .Process Broad PrefeiTed Optimum Gas now. seem cι 2 30 to 400 50 to 250 60 to 150 Ar 20 to 300 30 to 200 40 to 100 HBr and/or BC1 3 5 to 70 5 to 40 5 to 20 Pressure, mT 0.1 to 300 10 to 100 10 to 40 RF Power of Coil Induαor (Watts) 100 to 5000 650 to 2000 750 to 1000 RF Power of Wafer Pedestal (Watts) 50 to 3000 100 to 1000 150 to 400 Temperature of about 150 to about Wafer (°C) 500 200 to 400 250 to 350 Platinum Etch Rate (A/min) 200 to 6000 500 to 3000 1000 to 2000 RF Frequency of Coil Induαor 100 K to 300 MH. z 400 K to 20 2 to 13.5 MHz MHz KF Frequency of Wafer Pedestal 100 K to 300 MHz 400 K to 20 400 K to 13.5 MHz MHz Therefore, the foregoing process conditions are preferably based on flow rates of etchant gas(es) having a flow rate value ranging from about 5 to about 500 seem. As was previously mentioned, the etchant gas comprises or consists of or consists essentially of a halogen (preferably chlorine) and a noble gas selected from the group consisting of helium, neon, and argon. The noble gas is preferably argon. As was also previously mentioned, the etchant gas more specifically comprises or consists of or consists essentially of from about 20% by volume to about 95% by volume of the halogen gas (i.e., chloiine) and from about 5% by volume to about 80% by volume of the noble gas (i.e., argon); preferably from about 40% by volume to about 80% by volume of the halogen gas (i.e., chloiine) and from about 20% by volume to about 60% by volume of the noble gas (i.e., argon); more preferably from about 55% by volume to about 65% by volume of the halogen gas (i.e., chlorine) and from about 35% by volume to about 45% by volume of the noble gas (i.e., argon). In another preferred embodiment of the invention and as was previously mentioned, the etchant gas comprises, preferably consists of or consists essentially of, the halogen (i.e., chloiine), the noble gas (i.e., argon), and a gas selected from the group consists of HBr, BC1 3 and mixtures thereof. The etchant gas more specifically comprises, or consists of or consists essentially of from about 10% by volume to about 90% by volume of the halogen gas (i.e., chlorine) and from about 5% by volume to about 80% by volume of the noble gas (i.e., argon) and from about 4% by volume to about 25% by volume of Br and/or BC1 3 ; preferably from about 40% by volume to about 70% by volume of the halogen gas (i.e., chlorine) and from about 25% by volume to about 55% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 20% by volume of HBr and/or BC1 3 ; and more preferably from about 50% by volume to about 60% by volume of the halogen gas (i.e., chlorine) and from about 35% by volume to about 45% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 15% by volume of HBr and/or BC1 3 . Thus, the foregoing process conditions stated in Tables V and VI may be based on such etchant gas constituency and on such percent (%) by volume value(s). For the embodiment of the invention illustrated in Figs. 2, 6, 8 and 10, the protective layers 22a, 22b, 22c and 22d protect the corners 16g of the etched platinum electrode layers 16a, 16b, 16c and 16d during the etching process. Typically and as best shown in Figs. 11 and 12, some of the mask layers 18a, 18b, 18c and 18d would be etched during the platinum etching process, leaving residual mask layers 18r on top of etched platinum electrode layers 16a, 16b, 16c and 16d, or on top of the protective layers 22a, 22b, 22c and 22d. The protective layers 22a, 22b, 22c and 22, respectively, insure that the comers 16g of the etched platinum electrode layers 16a, 16b, 16c and 16d are protected during platinum etching, especially in the event that the platinum etching process removes essentially all of the mask layers 18a, 18b, 18c and 18d. Maintaining the corners 16g of the etched platinum electrode layers 16a, 16b, 16c and 16d protects the quality of the platinum profile formed during etching of the platinum electrode layer 16 to produce the etched platinum electrode layers 16a, 16b, 16c and 16d. After the platinum electrode layer 16 has been etched to produce the platinum electrode layers 16a, 16b, 16c and 16d, the residual mask layers 18r (if not completely removed during the platinum etching process) typically remain on top of the veil-less etched platinum electrode layers 16a, 16b, 16c and 16d, or on top of the protective layers 22a, 22b, 22c and 22d which are respectively supported by the essentially veil-less etched platinum electrode layers 16a, 16b, 16c and 16d, all as best shown in Figs. 11 and 12. The residual mask layers 18r are to be removed by any suitable means and/or in .any suitable manner, such is by CHF 3 /.Ar plasma. Likewise for the embodiment of the invention depicted in Fig. 12, the protective layers 22a, 22b, 22c and 22d are to be removed after removal of the residual mask layers 18r from the protective layers 22a, 22b, 22c and 22d. The protective layers 22a, 22b, 22c and 22d may be removed by any suitable means and/or in any suitable manner. For example, when the protective layers 22a, 22b, 22c and 22d comprise TiN removal is by Ar/Cl 2 plasma in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following apparatus and process conditions as listed in Table VII below. TABLE Vπ Process Broad Preferred Optimum Gas Flow, seem Cl 2 20 to 150 30 to 120 40 to 100 Ar 20 to 100 30 to 80 40 to 60 Pressure, mT 0.5 to 40 4 to 30 7 to 14 .RF Power of Coil Induαor (Watts) 500 to 3000 500 to 2000 800 to 1200 RF Power of Wafer Pedestal (Watts) 50 to 500 50 to 300 50 to 150 Temperature of Wafer 20 to 500 20 to 150 80 to 130 TiN Etch Rate (A/min) 500 to 5000 1000 to 3500 1500 to 2500 RF Frequency of Coil Induαor 100 K to 300 MHz 400 K to 20 2 to 13.5 MHz MHz RF Frequency of Wafer Induαor 100 K to 300 MHz 400 K to 20 400 K to 13.5 MHz MHz After removal of residual mask layers 18r, or the residual mask layers 18r and the protective layers 22a, 22b, 22c and 22d for the embodiment of the invention illustrated in Fig. 12, the veil-less etched platinum electrode layered structure of Fig. 13 or Fig. 14 remains. It should be noted, as best shown in Figs. 15 and 16, respectively, that the barrier layer 14 could be etched simultaneously during or after removal of the residual mask layers 18r (see Fig. 15), or etched simultaneously during or after removal of the residual mask layers 18r and the protective layers 22a, 22b, 22c and 22d (see Fig. 16). It is to be understood that the patterned resist 20 (i.e., resist members 20a, 20b, 20c and 20d) for the embodiment of the invention depicted in Fig. 1, or the patterned resist 20 (i.e., resist numbers 20a, 20b, 20c and 20d) and/or the mask layers 18a, 18b, 18c and 18d for the embodiment of the invention depicted in Fig. 2, may be removed at any suitable time, preferably before the etching of the platinum electrode layer 16. Similarly, the protective layers 22a, 22b, 22c and 22d and/or mask layers 18a, 18b, 18c and 18d for the embodiment of the invention depiαed in Fig. 2, may also be removed at any suitable time, such as during the platinum etching process or after the platinum etching process. The invention will be illustrated by the following set forth example which is being given to set forth the presently known best mode and by way of illustration only and not by way of any limitation. All parameters such as concentrations, mixing proportions, temperatures, pressure, rates, compounds, etc., submitted in this example are not to be construed to unduly limit the scope of the invention. Example 1 A test semiconduαor wafer was formulated with the following film stack: 0.8 μm patterned PR (photoresist)/500θA Oxide/IOOA Ti/IOOOA Pt/30θA TiN The feature size of the patterned PR test semiconduαor wafer was 0.3 μm block and 0.25 μm spacing. The oxide mask (i.e. the mask layer) was opened in the oxide etch chamber of a plasma processing apparatus sold under the trademark Oxide Etch MxP Centura™, owned by Applied Materials Inc., 3050 Bowers Avenue, Santa Clara, CA 95054-3299. The etchant gas for opening the ojude mask comprised about 68% by volume Ar and about 32% by volume CHF 3 . The reaαor and process conditions were as follows: Reaαor Conditions Pressure 60 mTorr RF Power 850 watts Rotational Magnetic Field 40 Gauss Temperature of Test Wafer 100 °C Oxide Mask Etch Rate 3000 A/min Process Conditions Based on the Flow Rate of Ar and CHF. CHF 3 50 seem Ar 100 seem Pressure, mTorr 60 mTorr RF Power Density 850 watts Temperature fC) of Test Wafer 100 ° C Oxide Mask Etch Rate (A/min) 3000 A/min Magnetic Field (Gauss) 40 Gauss The photoresist was stripped from the oxide mask in an ASP chamber of the Metal Etch MxP Centura™ brand plasma processing apparatus under the following recipe using microwave downstream O z /N 2 plasma: 120 seconds, 250° C, 1400 W, 3000 seem 0 2 , 300 seem N 2 , and 2 Torr. The Ti proteαive layer was etched with Ar, Cl 2 and BC1 3 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reaαor and process conditions: Reaαor Conditions Pressure 12 mTorr RF Power to Coil Induαor 900 watts RF Power to Wafer Pedestal 100 watts Temperature of Test Wafer 110 * C Ti Etch Rate 2000 .A min Process Conditions Based on the Flow Rate of Ar and C and BCK Ar 40 seem Cl 2 30 seem BC1 3 30 seem Pressure 12 mTorr RF Power to Coil Induαor 900 watts RF Power to Wafer Pedestal 100 watts Temperature of Test Wafer 110 * C Ti Etch Rate 2000 A/min The platinum layer of the test semiconduαor wafer was then etched with Ar and Cl 2 as the etchant gas and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reaαor and process conditions: Reaαor Conditions Pressure 12 mTorr RF Power to Coil Induαor 900 watts RF Power to Wafer Pedestal 150 watts Temperature of Test Wafer 260 * C Platinum Etch Rate 1500 A/min Process Conditions Based on the Flow Rate of Ar and C1-, Ar 40 seem Cl 2 60 seem Pressure, mTorr 12 mTorr RF Power to Coil Induαor 900 watts RF Power to Wafer Pedestal 150 watts Temperature (°C) of Test Wafer 260 * C Pt Etch Rate (A/min) 1500 A/min Seleαivity of Pt/Oxide Mask 1:1 The resulting etched platinum layer of the test semiconduαor wafer is shown in Fig. 19 wherein a platinum profile of about 87 degrees is shown. The oxide mask was then removed in a 6:1 HF solution to produce the veil-less test semiconduαor wafer shown in Fig. 20. The remaining Ti proteαive layer could be removed by any suitable means and/or in any suitable manner, such as by etching with Ar, BC1 3 and Cl 2 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reaαor and process conditions: Reaαor Conditions Pressure 12 mTorr RF Power to Coil Induαor 900 watts RF Power to Wafer Pedestal 100 watts Temperature of Test Wafer 110° C Ti Etch Rate 2000 A/min Process Conditions Based on the Flow Rate of Ar and Cl 7 Ar 40 seem Cl 2 30 seem BC1 3 30 seem Pressure 12 mTorr RF Power to Coil Induαor 900 watts RF Power to Wafer Pedestal 100 watts Temperature of Test Wafer 110° C Ti Etch Rate 2000 A/min Example II A test semiconduαor wafer was formulated with the following film stack: 0.8 μm patterned PR (photoresist)/500θA 0»de/60θA TiN/200θA Pt/30θA TiN The feature size of the patterned PR test semiconduαor wafer was 0.25 μm block and 0.2 μm spacing. The oxide mask (i.e. the mask layer) was opened in the oxide etch chamber of a plasma processing apparatus sold under the trademark Oxide Etch MxP Centura™, owned by Applied Materials Inc., 3050 Bowers Avenue, Santa Clara, CA 95054-3299. The etchant gas for opening the oxide mask comprised about 68% by volume Ar and about 32% by volume GHF 3 . The reaαor and process conditions were as follows: Reaαor Conditions Pressure 60 mTorr RF Power 850 watts Rotational Magnetic Field 40 Gauss Temperature of Test Wafer 100 * C Oxide Mask Etch Rate 3000 A/min Process Conditions Based on the Flow Rate of Ar and CHF CHF 3 50 seem Ar 100 seem Pressure, mTorr 60 mTorr RF Power Density 850 watts Temperature (°C) of Test Wafer 100 * C Oxide Mask Etch Rate (A/min) 3000 A/min Magnetic Field (Gauss) 40 Gauss The photoresist was stripped from the oxide mask in an ASP chamber of the Metal Etch MxP Centura™ brand plasma processing apparatus under the following recipe using microwave downstream 0 2 /N 2 plasma: 120 seconds, 250° C, 1400 W, 3000 seem 0 2 , 300 seem N 2 , and 2 Torr. The TiN proteαive layer was etched with Ar, Cl 2 and BC1 3 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reaαor and process conditions: Reaαor Conditions Pressure 12 mTorr RF Power to Coil Induαor 900 watts RF Power to Wafer Pedestal 100 watts Temperature of Test Wafer 110 * C TiN Etch Rate 2000 A/min Process Conditions Based on the Flow Rate of Ar and CU and BCl. Ar 40 seem Cl 2 30 seem BC1 3 30 seem Pressure 12 mTorr RF Power to Coil Induαor 900 watts RF Power to Wafer Pedestal 100 watts Temperature of Test Wafer 110 * C TiN Etch Rate 2000 A/min The platinum layer of the test semiconduαor wafer was then etched with Ar and Cl 2 and BCL, as the etchant gas and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reaαor and process conditions: Reaαor Conditions Pressure 12 mTorr RF Power to Coil Induαor 900 watts RF Power to Wafer Pedestal 150 watts Temperature of Test Wafer 260 * C Platinum Etch Rate 1500 A/min Process Conditions Based on the Flow Rate of Ar and Cl, and BCl, Ar 40 seem Cl 2 60 seem BC1 3 10 seem Pressure, mTorr 12 mTorr RF Power to Coil Induαor 900 watts RF Power to Wafer Pedestal 150 watts Temperature (°C) of Test Wafer 260 ° C Pt Etch Rate (A/min) 1500 A/min Seleαivity of Pt/ Oxide Mask 1:1 The resulting etched platinum layer of the test semiconduαor wafer is shown in Fig. 23 wherein a platinum profile of about 87 degrees is shown. The oxide mask could have been removed in a 6:1 F solution to produce a veil- less test semiconduαor wafer similar to the one shown in Fig. 20. The remaining TiN proteαive layer could have been removed by any suitable means and/or in any suitable manner, such as by etching with Ar, BC1 3 and Cl 2 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reaαor and process conditions: Reaαor Conditions Pressure 12 mTorr RF Power to Coil Induαor 900 watts RF Power to Wafer Pedestal 100 watts Temperature of Test Wafer 110° C TiN Etch Rate 2000 A/min Process Conditions Based on the Flow Rate of Ar and Cl> and BCh Ar 40 seem Cl 2 30 seem BC1 3 30 seem Pressure 12 mTorr RF Power to Coil Induαor 900 watts RF Power to Wafer Pedestal 100 watts Temperature of Test Wafer 110° C TiN Etch Rate 2000 A/min Conclusion Thus, by the praαice of the present invention there is provided a method for etching of the platinum eleαrode layer 16. The etched platinum eleαrode layer 16 includes a plurality of etched platinum eleαrode layers 16a, 16b, 16c and 16d having a platinum profile where the angle α of the sidewalls 16s with respeα to a horizontal plane is equal to or greater than about 85 degrees. The platinum eleαrode layers 16a, 16b, 16c and 16d are separated by a distance or space having a dimension equal to or less than about 0.3 μm. Each of the platinum eleαrode layers 16a, 16b, 16c and 16d include a dimension having a value equal to or less than about 0.6 μm, preferably equal to or less than about 0.3 μm. More preferably, each of the platinum eleαrode layers 16a, 16b, 16c and 16d has a width equal to or less than about 0.3 μm, a length equal to or less than about 0.6 μm, and a height equal to or less than about 0.6 μm. Because the produced etched platinum eleαrode layers 16a, 16b, 16c and 16d are essentially a "veil-less" with no "fences" or "rabbit ears," they are ideally suited for receiving a dieleαric (e.g., a BST layer) in producing a semiconduαor device. The etchant gas in Example I consisted of about 40% by vol. Ar and about 60% by vol. Cl 2 , and produced an etched platinum layer with a platinum profile of about 87 degrees. In Example II, the etchant gas consisted of 54.5% by vol. (about 55% by vol.) Cl 2 , 36.4% by vol. (about 36% by vol.) Ar, and 9.1% by vol. (about 9% by vol.) BC1 3 , and the resulting etched platinum layer had a platinum profile of about 87 degrees. Thus, while the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosure, and it will be appreciated that in some instances some features of the invention will be employed without a corresponding use of other features without departing from the scope and spirit of the invention as set forth. Therefore, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular embodiments) disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments and equivalents falling within the scope of the appended claims.

Claims: WHAT IS CLAIMED IS: 1. A method of etching a platinum layer disposed on a substrate comprising the steps of: a) providing a substrate supporting a platinum layer; b) heating said substrate of step (a) to a temperature greater than about 150°C; and c) etching said platinum layer including employing a high density plasma of an etchant gas comprising a halogen containing gas and a noble gas to produce said substrate supporting at least one etched platinum layer. 2. The method of Claim 1 wherein said etchant gas additionally comprises BC1 3 . 3. The method of Claim 1 wherein said etchant gas additionally comprises HBr. 4. The method of Claim 1 wherein said etched platinum layer includes a platinum profile equal to or greater than about 85°. 5. The method of Claim 1 wherein said halogen containing gas consists essentially of chlorine and said noble gas consists essentially of argon. 6. The method of Claim 5 wherein said etchant gas consists essentially of chlorine, argon and BC1 3 . 7. The method of Claim 1 wherein said platinum layer of step (a) additionally comprises a mask layer disposed on a seleαed part of said platinum layer to seleαively proteα said platinum layer during said etching step (c). 8. The method of Claim 4 wherein said platinum layer of step (a) additionally comprises a mask layer disposed on a seleαed part of said platinum layer to seleαively proteα said platinum layer during said etching step (c). 9. The method of Claim 5 wherein said platinum layer of step (a) additionally comprises a mask layer disposed on a seleαed part of said platinum layer to seleαively proteα said platinum layer during said etching step (c). 10. The method of Claim 7 wherein said platinum layer of step (a) additionally comprises a proteαive layer disposed on said seleαed part of said platinum layer between said mask layer and said platinum layer. 11. The method of Claim 8 wherein said platinum layer of step (a) additionally comprises a proteαive layer disposed on said seleαed part of said platinum layer between said mask layer and said platinum layer. 12. The method of Claim 9 wherein said platinum layer of step (a) additionally comprises a proteαive layer disposed on said seleαed part of said platinum layer between said mask layer and said platinum layer. 13. The method of Claim 7 additionally comprising removing said mask layer after said etching step (c). 14. The method of Claim 8 additionally comprising removing said mask layer during said etching step (c). 15. The method of Claim 9 additionally comprising removing said mask layer after said etching step (c). 16. The method of Claim 10 additionally comprising removing said mask layer during said etching step (c). 17. The method of Claim 16 additionally comprising removing said proteαive layer after removing said mask layer. 18. The method of Claim 1 wherein said high density plasma includes a high density induαively coupled plasma. 19. The. method of Claim 18 additionally comprising disposing said substrate including said platinum layer of step (a) in a high density plasma chamber including a coil inductor and a wafer pedestal; and performing said etching step (c) in said high density plasma chamber under the following process conditions: Process Parameters Etchant Gas flow 50 to 500 seem Pressure, mTorr 0J to 300 milUTorr RF Power (watts) of Coil Induαor 100 to 5000 watts RF Power (watts) of Wafer Pedestal 50 to 3000 watts Platinum Etch Rate (A/min) 200 to 6000 A/min RF Frequency of Coil Inductor 100 K to 300 MHz RF Frequency of Wafer Pedestal 100 K to 300 MHz 20. The method of Claim 5 wherein said high density plasma includes a high density inductively coupled plasma. 21. The method of Claim 20 additionally comprising disposing said substrate including said platinum layer of step (a) in a high density plasma chamber including a coil inductor and a wafer pedestal; and performing said etching step (c) in said high density plasma chamber under the following process conditions: Process Parameters Cl, 20% to 95% by vol. Ar 5% to 80% by vol. Pressure, mTorr 0J to 300 milliTorr RF Power (watts) of Coil Induαor 100 to 5000 watts RF Power (watts) of Wafer Pedestal 50 to 3000 watts Platinum Etch Rate (A/min) 200 to 6000 A/min RF Frequency of Coil Induαor 100 K to 300 .MHz RF Frequency of Wafer Pedestal 100 K to 300 MHz 22. The method of Claim 1 wherein said etched platinum layer includes a dimension having a value equal to or less than about 0.3 μm. 23. The method of Claim 4 wherein said etched platinum layer includes a dimension having a value equal to or less than about 0.3 μm. 24. The method of Claim 1 wherein said substrate supports at least two etched platinum layers separated by a distance equal to or less than about 0.3 μm. 25. The method of Claim 24 wherein said etched platinum layers have a platinum profile equal to or greater than about 85°. 26. The method of Claim 25 wherein said etched platinum layers each include a dimension having a value equal to or less than about 0.3 μm. 27. A method for producing a capacitance strutture including a platinum eleαrode comprising the steps of: a) providing a substrate supporting a platinum eleαrode layer and at least one mask layer disposed on a seleαed part of said platinum eleαrode layer; b) heating said substrate of step (a) to a temperature greater than about 150°C; and c) etching said platinum eleαrode layer including employing a plasma of an etchant gas comprising chlorine and a noble gas to produce a capacitance struαure having at least one platinum eleαrode. 28. A capacitance struαure produced in accordance with the method of Claim 27. 29. The method of Claim 27 wherein said capacitance struαure of step (c) includes said substrate supporting an etched platinum eleαrode layer with at least one mask layer disposed on a seleαed part of said etched platinum eleαrode layer. 30. The method of Claim 29 additionally comprising removing said at least one mask layer after said etching step (c). 31. The method of Claim 29 additionally comprising removing said at least one mask layer during said etching step (c). 32. The method of Claim 29 wherein said platinum eleαrode layer of step (a) additionally comprises a proteαive layer disposed on said seleαed part of said platinum elettrode layer between said mask layer and said platinum eleαrode layer. 33. The method of Claim 27 wherein said plasma of an etchant gas comprises a high density induαively coupled plasma. 34. The method of Claim 33 wherein said etchant gas of said high density induαively coupled plasma additionally comprises BCl 3 . 35. The method of Claim 33 wherein said noble gas is seleαed from the group consisting of helium, neon, argon, and mixtures thereof. 36. The method of Claim 33 wherein said noble gas of said etchant gas of said high density induαively coupled plasma is seleαed from the group consisting of helium, neon, argon, krypton, xenon, radon, and mixtures thereof. 37. The method of Claim 33 wherein said etchant gas of said high density induαively coupled plasma consists essentially of chlorine, argon and BC1 3 . 38. The method of Claim 33 additionally comprismg disposing said substrate including said platinum eleαrode layer of step (a) in a high density plasma chamber including a coil induαor and a wafer pedestal; and performing said etching step (c) in said high density plasma chamber under the following process conditions: Process Parameters Etchant Gas flow 50 to 500 seem Pressure, Mtorr 0.1 to 300 milliTorr RF Power (watts) of Coil Induαor 100 to 5000 watts RF Power (watts) of Wafer Pedestal 50 to 3000 watts Platinum Etch Rate (A/min) 200 to 6000 A/min RF Frequency of Coil Induαor 100 K to 300 Mhz RF Frequency of Wafer Pedestal 100 K to 300 Mhz 39. The method of Claim 27 wherein said plasma of an etchant gas comprises a high density induαively coupled plasma, and said etchant gas comprises chlorine and argon. 40. The method of Claim 39 additionally comprising disposing said substrate including said platinum eleαrode layer of step (a) in a high density plasma chamber including a coil induαor and a wafer pedestal; and performing said etching step (c) in said high density plasma chamber under the following process conditions: Process Parameters Cl 2 20% to 95% by vol. Ar 5% to 80% by vol. Pressure, Mtorr 0.1 to 300 milliTorr RF Power (watts) of Coil Induαor 100 to 5000 watts RF Power (watts) of Wafer Pedestal 50 to 3000 watts Platinum Etch Rate (A/min) 200 to 6000 -A/min KF Frequency of Coil Induαor 100 K to 300 Mhz RF Frequency of Wafer Pedestal 100 K to 300 MHz 41. The method of Claim 27 wherein said platinum eleαrode includes a dimension having a value equal to or less than about 0.3 μm. 42. The method of Claim 27 wherein said platinum eleαrode includes a platinum profile equal to or greater than about 85°. 43. The method of Claim 42 wherein said platinum eleαrode includes a dimension having a value equal to or less than about 0.3 μm. 44. The method of Claim 27 wherein said substrate supports at least two platinum eleαrodes separated by a distance equal to or less than about 0.3 μm. 45. The method of Claim 44 wherein said platinum eleαrodes include a platinum profile equal to or greater than about 85°. 46. The method of Claim 45 wherein said platinum eleαrodes include a dimension having a value equal to or less than about 0.3 μm. 47. A method of manufaαuring a semiconduαor device comprising the steps of: a) forming a patterned resist layer, a mask layer and a platinum eleαrode layer on a substrate having circuit elements formed thereon; b) etching a portion of said mask layer including employing a plasma of an etchant gas to break through and to remove said portion of said mask layer from said platinum eleαrode layer to produce said substrate supporting said patterned resist layer, a residual mask layer, and said platinum eleαrode layer; c) removing said patterned resist layer of step (b) to produce said substrate supporting said residual mask layer and said platinum eleαrode layer; d) heating said substrate of step (c) to a temperature greater than about 150°C; and e) etching said platinum eleαrode layer of step (d) including employing a high density plasma of an etchant gas comprising chlorine and argon to produce a semiconduαor device having at least one platinum eleαrode. 48. The method of Claim 47 additionally comprising removing said residual mask layer after said etching step (e). 49. The method of Claim 47 additionally comprising removing said residual mask layer during said etching step (e). 50. The method of Claim 47 wherein said forming step (a) additionally comprises disposing a proteαive layer on said platinum eleαrode layer between said mask layer and said platinum eleαrode layer. 51. The method of Claim 47 wherein said etchant gas of said high density plasma of step (e) consists essentially of chlorine, argon and a gas seleαed from the group consisting of BC1 3 , HBr and mixtures thereof. 52. The method of Claim 47 additionally comprising disposing said substrate including said platinum eleαrode layer of step (d) in a high density plasma chamber including a coil induαor and a wafer pedestal; and performing said etching step (e) in said high density plasma chamber under the following process conditions: Process Parameters Cl 2 20% to 95% by vol. Ar 5% to 80% by vol. Pressure, mTorr 0J to 300 milliTorr RF Power (watts) of Coil Induαor 100 to 5000 watts RF Power (watts) of Wafer Pedestal 50 to 3000 watts Platinum Etch Rate (A/min) 200 to 6000 .A min RF Frequency of Coil Induαor 100 K to 300 MHz RF Frequency of Wafer Pedestal 100 K to 300 MHz 53. The method of Claim 47 wherein said platinum eleαrode includes a dimension having a value equal to or less than about 0.3 μm. 54. The method of Claim 47 wherein said platinum eleαrode includes a platinum profile equal to or greater than about 85°. 55. The method of Claim 54 wherein said platinum eleαrode includes a dimension having a value equal to or less than about 0.3 μm. 56. The method of Claim 47 wherein said substrate supports at least two platinum eleαrodes separated by a distance equal to or less than about 0.3 μm. 57. The method of Claim 56 wherein said platinum eleαrodes include a platinum profile equal to or greater than about 85°. 58. The method of Claim 57 wherein said platinum eleαrodes include a dimension having a value equal to or less than about 0.3 μm. 59. A method of etching a platinum eleαrode layer disposed on a substrate comprising the steps of: a) providing a substrate supporting a platinum eleαrode layer, a proteαive layer on said platinum eleαrode layer, a mask layer on said proteαive layer, and a patterned resist layer on said mask layer; b) etching a portion of said mask layer including employing a plasma of an etchant gas to break through and to remove said portion of said mask layer from said platinum eleαrode layer to expose part of said proteαive layer and to produce said substrate supporting said platinum eleαrode layer, said proteαive layer on said platinum eleαrode layer, a residual mask layer on said proteαive layer, and said patterned resist layer on said residual mask layer; c) removing said patterned resist layer from said residual mask layer of step (b) to produce said substrate supporting said platinum eleαrode layer, said proteαive layer on said platinum eleαrode layer, and said residual mask layer on said proteαive layer; d) heating said substrate of step (c) to a temperature greater than about 150°C; e) etching said exposed part of said proteαive layer to expose part of said platinum eleαrode layer and to produce said substrate supporting said platinum elettrode layer, a residual proteαive layer on said platinum eleαrode layer, and said residual mask layer on said residual proteαive layer; and f) etching said exposed part of said platinum eleαrode layer of step (e) including employing a high density plasma of an etchant gas comprising chlorine and argon to produce said substrate supporting an etched platinum eleαrode layer having said residual proteαive layer on said etched platinum eleαrode layer, and said residual mask layer on said residual proteαive layer. 60. The method of Claim 59 wherein said etched platinum eleαrode layer includes a platinum profile equal to or greater than about 85°. 61. The method of Claim 59 wherein said etched platinum eleαrode layer includes a dimension having a value equal to or less than about 0.3 μm. 62. The method of Claim 60 wherein said etched platinum eleαrode layer includes a dimension having a value equal to or less than about 0.3 μm. 63. The method of Claim 59 wherein said substrate supports at least two etched platinum eleαrode layers separated by a distance equal to or less than about 0.3 μm. 64. The method of Claim 63 wherein said etched platinum eleαrode layers have a platinum profile equal to or greater than about 85°. 65. The method of Claim 64 wherein said etched platmum eleαrode layers each include a dimension having a value equal to or less than about 0.3 μm. 66. The method of Claim 65 wherein said dimension is a width. 67. The method of Claim 59 wherein said etched platinum eleαrode layer is essentially veil-less. 68. A method of etching a platinum eleαrode layer disposed on a substrate comprising the steps of: a) providing a substrate supporting a platinum eleαrode layer, a proteαive layer on said platinum eleαrode layer, a mask layer on said proteαive layer, and a patterned resist layer on said mask layer; b) etching a portion of said mask layer including employing a plasma of an etchant gas to break through and to remove said portion of said mask layer from said platinum eleαrode layer to expose part of said proteαive layer and to produce said substrate supporting said platinum eleαrode layer, said proteαive layer on said platinum elettrode layer, a residual mask layer on said proteαive layer, and said patterned resist layer on said residual mask layer; c) etching said exposed part of said proteαive layer to expose part of said platinum eleαrode layer and to produce said substrate supporting said platinum eleαrode layer, a residual proteαive layer on said platinum eleαrode layer, said residual mask layer on said residual proteαive layer, and said patterned resist layer on said residual mask layer; d) removing said patterned resist layer from said residual mask layer of step (c) to produce said substrate supporting said platinum eleαrode layer, said residual proteαive layer on said platinum eleαrode layer, and said residual mask layer on said residual proteαive layer; e) heating said substrate of step (d) to a temperature greater than about 150°C ; and f) etching said exposed part of said platinum eleαrode layer of step (d) including employing a high density plasma of an etchant gas comprising chlorine and a noble gas to produce said substrate supporting an etched platinum eleαrode layer having said residual proteαive layer on said etched platinum eleαrode layer, and said residual mask layer on said residual proteαive layer. 69. The method of Claim 68 wherein said etched platinum elettrode layer includes a platinum profile equal to or greater than about 85°. 70. The method of Claim 68 wherein said etched platinum eleαrode layer includes a dimension having a value equal to or less than about 0.3 μm. 71. The method of Claim 69 wherein said etched platinum elettrode layer includes a dimension having a value equal to or less than about 0.3 μm. 72. The method of Claim 68 wherein said substrate supports at least two etched platinum eleαrode layers separated by a distance equal to or less than about 0.3 μm. 73. The method of Claim 72 wherein said etched platinum eleαrode layers have a platinum profile equal to or greater than about 85°. 74. The method of Claim 73 wherein said etched platinum elettrode layers each include a dimension having a value equal to or less than about 0.3 μm. 75. The method of Claim 74 wherein said dimension is a width. 76. The method of Claim 68 wherein said noble gas is argon. 77. The method of Claim 68 wherein said etchant gas additionally comprises a gas seleαed from the group consisting of BC1 3 and HBr and mixtures thereof. 78. The method of Claim 69 wherein said etchant gas additionally comprises a gas seletted from the group consisting of BC1 3 and HBr and rr xtures thereof. 79. The method of Claim 77 wherein said noble gas is argon. 80. The method of Claim 68 wherein said etched platinum elettrode layer is essentially veil-less. 81. A capacitance structure comprising a substrate, and at least two platinum eleαrodes supported by said substrate, said platinum eleαrodes being separated by a distance equal to or less than about 0.3 μm and including a platinum profile equal to or greater than about 85°. 82. The capacitance structure of Claim 81 wherein said platinum elettrodes have a width with a value equal to or less than about 0.3 μm. 83. The capacitance structure of Claim 81 wherein said platinum eleαrodes have a dimension with a value equal to or less than about 0.3 μm. 84. The capacitance strutture of Claim 81 wherein said platinum eleαrodes have a length with a value equal to or less than about 0.6 μm. 85. The capacitance struαure of Claim 81 wherein said platinum elettrodes have a dimension with a value equal to or less than about 0.6 μm. 86. The capacitance stincture of Claim 83 wherein said platinum electrodes have a length with a value equal to or less than about 0.6 μm. 87. A semiconduαor device comprising a substrate, and a plurality of platinum elettrodes supported by said substrate, said platinum elettrodes having a platinum profile equal to or greater than about 85°. 88. The semiconductor device of Claim 87 wherein said platinum elettrodes have a dimension with a value equal to or less than about 0.3 μm. 89. The semiconductor device of Claim 87 wherein said platinum eleαrodes have a dimension with a value equal to or less than about 0.6 μm. 90. The semiconductor device of Claim 88 wherein said dimension is a width. 91. An etchant gas for etching platinum consisting essentially of from about 55% by volume to about 65% by volume Cl 2 and from about 35% by volume to about 45% by volume argon. 92. The method of Claim 1 wherein said etchant gas comprises from about 55% by volume to about 65% by volume Cl 2 and from about 35% by volume to about 45% by volume argon. 93. The method of Claim 51 wherein said etchant gas consists essentially of from about 50% by volume to about 60% by volume Cl 2 ; from about 35% by volume to about 45% by volume argon; and from about 5% by volume to about 15% by volume 94. The method of Claim 78 wherein said etchant gas consists essentially of from about 50% by volume to about 60% by volume Cl 2 ; from about 35% by volume to about 45% by volume argon; and from about 5% by volume to about 15% by volume BC1 3 and/or H . Br.

Inventors: HWANG JENG H, HWANG, JENG, H.
Applicants: APPLIED MATERIALS INC, APPLIED MATERIALS, INC.
Application year: 1998
Main classification: H01L21
IPC codes: C23F4, H01L21, H01L27