Fabrication method of a vertical cavity surface emitting semiconductor laser

Abstract: The present invention relates to a vertical cavity surface emitting laser with an accurately defined and controlled aperture (134) which directs the current path within the laser. Specifically, the oxide regions (106) surrounding the aperture are formed by a pre-oxidation layer disordering process which controls the regions within which oxidation can occur. The present invention allows for the manufacture of highly compact lasers with reproducible optical and electrical characteristics.

Description: This invention relates to vertical cavity surface emitting laser structures formed by a selective oxidation process. Solid state semiconductor lasers are important devices in optoelectronic communication systems and high-speed printing systems. Although edge emitting lasers are currently used in the vast majority of such applications, recently, there has been an increased interest in vertical cavity surface emitting lasers ("VCSELs") therefor. One reason for the interest in VCSELs is that edge emitting lasers produce a beam with a large angular divergence, making efficient collection of the emitted beam more difficult. Furthermore, edge emitting lasers cannot be tested until the wafer is cleaved into individual devices, the edges of which form the mirror facets of each device. On the other hand, the beam of a VCSEL has a small and circular angular divergence, and the VCSEL is a stacked structure that incorporates the mirrors monolithically into its layer design. Therefore, it allows for on-wafer testing and for monolithic fabrication of one-dimensional or two-dimensional laser arrays. A known technique to fabricate a VCSEL's laser emitting aperture is by a lateral oxidation process. In this process, the stack of epitaxial layers comprising the laser device includes an AlGaAs layer with a high aluminum content disposed either above or below the active layer. Then, a patterned etching is performed, forming a mesa structure and exposing the edges of the stacked layers. To form the lasing aperture or the emissive region, the structure is exposed to an oxidizing environment which will cause only the high aluminum content AlGaAs layer to be oxidized laterally inwardly from its free edges towards the center of the mesa structure. Other layers in the structure remain essentially unoxidized since their aluminum content is lower. Thus, the oxidized portions of the high aluminum content layer become electrically non-conductive and the remaining unoxidized portions, which remain conductive, form the laser aperture, which directs the current path through the VCSEL structure. A VCSEL formed by such a technique is discussed in "Selectively Oxidized Vertical Cavity Surface Emitting Lasers With 50% Power Conversion Efficiency," Electronics Letters, vol. 31, pp.208-209 (1995). One disadvantage of this approach is that the oxidation process results in poor control over the shape of the aperture. The process produces apertures with uneven and jagged boundaries because the rate of oxidation through different portions of the high aluminum content AlGaAs layer depends upon the direction of the oxidation fronts relative to the crystal orientation. Another disadvantage of this approach is the difficulty in controlling the amount of oxidation in order to accurately define the aperture. A typical mesa for a VCSEL structure is on the order of 50 to 100 microns (µm) across and the desired device aperture is generally on the order of one to tens of microns. Therefore, several tens of microns of lateral oxidation would typically be required in order to fabricate the device. Since the size of the resulting aperture is small relative to the extent of the lateral oxidation regions, the devices formed will have severe variations in their performance characteristics, aperture sizes, and aperture shapes. This lateral oxidation approach is also sensitive to composition nonuniformity and fluctuation in processing temperatures. These shortcomings decrease the reproducibility of device performance and result in, manufacturability and yield problems. WO-A-97/22991 discloses a conductive element with a lateral oxidation barrier for the control of lateral oxidation processes in semiconductor devices such as lasers, vertical cavity surface emitting lasers (VCSEL's) and light emitting diodes. The oxidation barrier is formed through the modification of one or more layers of the conductive element which initially were receptive to oxidation. This modification of the oxidizing layer is achieved by interdiffusing the oxidizing layer with a non-oxidizing layer thereby rendering it resistive to oxidation. The interdiffused region of the oxidizing layer is substantially electrically conductive, while the non-interdiffused region thereof is electrically resistive. This interdiffusion of the oxidizing layer and the non-oxidizing layer can be brought about impurity induced layer disordering (IILD). Accordingly, there is a need for developing VCSEL structures with well-defined and well-controlled apertures. These structures should also allow for the formation of high density and high uniformity laser arrays. The invention is defined in claim 1. Various embodiments are defined in the dependent claims. The present invention provides an approach to building a vertical cavity surface emitting laser comprising a plurality of active region layers including an active layer and an adjacent group of disorderable layers having a well defined intermixed conductive portion bounded by an outlying nonconductive, oxidized portion, wherein the aperture which controls the current flowing through the active layer is defined by the intermixed portion. The advantages of the present invention will become apparent to those skilled in the art from the following detailed description of the invention, its preferred embodiments, the accompanying drawings, and the appended claims. FIG. 1 illustrates a cross-sectional view of a stacked semiconductor structure that is used to form a VCSEL with a method in accordance with one form of the present invention. FIG. 2 illustrates the stacked semiconductor structure shown in FIG. 1 after deposition of a silicon nitride cap and completion of an IILD process. FIG. 3 illustrates the stacked semiconductor structure shown in FIG. 2 after deposition of a silicon dioxide cap and completion of a mesa etching process. FIG. 4 illustrates a VCSEL structure formed with a method in accordance with the present invention. FIG. 5 illustrates a view taken substantially in the direction of line 5-5 of FIG. 4, showing a non-oxidized aperture region and a surrounding oxidation region. FIG. 6 illustrates schematic representations of three anisotropic apertures. FIG. 7 illustrates a cross-sectional view of a stacked semiconductor structure that is used to form a VCSEL with a method in accordance with an alternative form of the present invention. FIG. 8 illustrates the stacked semiconductor structure shown in FIG. 7 after deposition of silicon nitride caps and completion of an IILD process. FIG. 9 illustrates the stacked semiconductor structure shown in FIG. 7 after deposition of a silicon dioxide cap and completion of a mesa etching process. FIG. 10 illustrates a VCSEL structure formed with a method in accordance with the alternative form of the present invention. Turning now to the drawings, there is illustrated in FIG. 1 a stacked semiconductor structure which is used to form a VCSEL in accordance with the present invention. The stacked structure includes a number of semiconductor layers formed by an epitaxial process such as metal-organic chemical vapor deposition ("MOCVD"), liquid phase epitaxy ("LPE"), molecular beam epitaxy ("MBE"), or other known crystal growth processes. As shown in FIG. 1, the stacked semiconductor structure is generally in the form of a P-I-N diode as represented by the notation overlying the structure. It includes a highly doped n-type GaAs substrate 100, whose doping is typically on the order of 5 x 10 18 cm -3 , on which is deposited an n-type superlattice structure, collectively identified as the monolithic region 102, forming a lower distributed Bragg reflector ("DBR"). This lower DBR provides the necessary internal reflection, as required in a VCSEL structure. If desired, a buffer layer (not shown) of about 0.5 µm may be inserted between the substrate 100 and the superlattice structure 102. The superlattice structure 102 typically comprises multiple pairs of Al x Ga 1-x As and Al y Ga 1-y As layers (not shown). The Al y Ga 1-y As layers in the superlattice typically have a low aluminum content, on the order of 10%, so as to achieve a desired refractive index, but should have sufficient aluminum so as to be non-absorptive at the lasing wavelength. The Al x Ga 1-x As layers have an aluminum content of about 95% to differentiate them from the AlAs layer in the disordering layers (as will be described). After the growth of a number of layer pairs, typically about 20 to 40, a final Al 0.95 Ga 0.05 As layer is deposited before growing further layers. The total thickness of each layer pair is designed to be equal to one half of the optical wavelength and the thickness of the final Al 0.95 Ga 0.05 As layer is designed to be a quarter of the optical wavelength, at the desired wavelength of laser operation, which is typically in the range of 670 to 980 nanometers. In this embodiment, since light is designed to be outcoupled through the top surface of the VCSEL structure, the reflectivity of the lower DBR 102 should be as close to 100% as possible, in order to achieve high internal reflection. It is well known that the reflectivity of the lower DBR 102 is generally a function of the difference in the refractive indices between its Al x Ga 1-x As and Al y Ga 1-y As layers, and is also a function of the number of layer pairs in the structure. Thus, the greater the difference in the refractive indices, the fewer number of pairs are required. Deposited over the lower DBR structure 102 is a group of three n-type disorderable layers which are provided to be preferentially and locally intermixed by the impurity induced layer disordering ("IILD") process. This group comprises first an AlGaAs layer 104 of approximately 20 nanometers, second, an AlAs layer 106 of about 15 nanometers, and lastly, another AlGaAs layer 108 of about 20 nanometers. Layers 104 and 108 have an aluminum content of approximately 40%, whereas layer 106 has an aluminum content of approximately 100%. These layers are silicon doped, wherein the silicon doping of the AlGaAs layers, 104 and 108, is on the order of 1 - 5 x 10 18 cm -3 while the silicon doping of the AlAs layer 106 is on the order of 5 x 10 18 cm -3 . The silicon acts as the disordering agent which enables intermixing by the IILD process. The n-type disordering layers may also be associated with the lower, n-type, DBR structure by being incorporated therein. Above these disorderable layers is deposited a group of three intrinsic, undoped, active region layers in which the desired optical gain can be attained. The active region layers include a first AlGaAs cladding layer 110 having an aluminum content of about 40% and a thickness of approximately 65 nanometers, a GaAs active layer 112 which comprises one to two quantum wells, each with a thickness of five to ten nanometers, and a second AlGaAs cladding layer 114 having an aluminum content of about 40% and a thickness of approximately 100 nanometers. Although the quantum wells are preferably formed of GaAs, In x Ga 1-x As or Al x Ga 1-x As may also be used, depending upon the desired output wavelength. Of course, other multiple quantum well structures ("MQW") also may be used to form the active layer 112. The total thickness of layers 104, 106, 108, 110, 112 and 114, collectively identified as the optical cavity layers, is typically equal to the intended wavelength of laser operation divided by the average refractive index of these layers. Above the upper AlGaAs cladding layer 114 is deposited a p-type superlattice structure, collectively identified as the monolithic region 116, which forms an upper DBR mirror 116. The upper DBR mirror 116 is structurally similar to the lower DBR mirror 102 except for the polarity of its dopants. Additionally, the mirror layer closest to the active region generally has a high aluminum content. In this embodiment, the reflectivity of the upper DBR 116 is typically 98% to 99% because light will be outcoupled through the upper surface of the VCSEL. Typically, 15 to 25 pairs of alternating Al 0.95 Ga 0.05 As and Al 0.10 Ga 0.90 As layers are used to form this upper DBR mirror 116. Finally, a p + -GaAs layer 118 is deposited for the formation of p-type contacts. After all the semiconductor layers shown in FIG. 1 have been deposited, a silicon nitride layer is deposited on the surface of the semiconductor structure and is photolithographically formed into the capping mask 120, as shown in FIG. 2. The capping mask 120 overlies the location where the aperture is to be formed and defines its configuration, as will be described below. The n-type disordering agent, created by the silicon dopants in the disorderable layers 104, 106 and 108 generates Group III vacancies in these layers. During the IILD process, the semiconductor structure is placed in a furnace and elevated into the range of about 800 to 900°C for several (about ten) hours to allow intermixing of the Group III elements, gallium and aluminum, to occur under the silicon nitride cap 120. In the regions outside of the nitride cap 120 arsenic outdiffuses causing Group V vacancies to increase. But since the number of Group V vacancies (V v ) times the number of Group III vacancies (V III ) must remain constant (V v x V III = k), as the Group V vacancies increase due to arsenic outdiffusion, the number of Group III vacancies decrease thus reducing the capability of these regions to intermix. Intermixing will be confined to the region 122 under the cap 120. During the intermixing process in the region 122, the aluminum composition decreases and the gallium composition increases in the layer 106, which originally had a high aluminum content, while conversely the aluminum composition increases and the gallium composition decreases in the layers 104 and 108 which originally had a low aluminum content. Thus, after a typical IILD process, the region 122 has an average aluminum content of less than about 95%. Minimal intermixing of Group III elements occurs in the regions outside of the silicon nitride cap 120. After the layer disordering process has been completed, a silicon dioxide layer 124 is deposited on the surface of the semiconductor structure. Layer 124 is masked and an etching process is performed to form mesa 126, as shown in FIG. 3. This exposes the edges of the AlAs layer 106 for the next step, oxidation. The oxidation environment is water vapor at a temperature of 400 to 500°C. Since there exists a difference between the aluminum mole fractions in intermixed region 122 and the outboard non-intermixed regions of the AlAs layer 106, there will be a disparity in the oxidation rates of these two regions because the oxidation rate of AlGaAs varies exponentially with the aluminum mole fraction. For example, the oxidation rate of AlAs is about 1.5 µm per minute at 450°C while it is about 0.05 µm per minute for AlGaAs with about 95 percent aluminum and about 0.01µm per minute for AlGaAs with about 80 percent aluminum. Due to this significant difference in the oxidation rates, oxidation slows down substantially when it reaches the interface between the intermixed and non-intermixed regions. The oxidized regions are identified in FIG. 4 at 128. After the oxidation process has been completed, the silicon nitride cap 120 and the silicon dioxide masking layer 124 are removed. Finally, upper p-type contacts 130 of titanium/gold, and a lower n-type contact 132 of germanium/gold are formed on the semiconductor structure. As can be seen in FIG. 5 the aperture 134 defined by the intermixed region 122 is smoothly circular in shape. It has been found that such a structure offers both electrical and optical confinement in a VCSEL because the surrounding oxide 128 is electrically insulating and has an adequately low refractive index of approximately 1.6. The formation of the oxide region 128 is controlled photolithographically, thus affording a high degree of accuracy and flexibility in the size and shape of the optical aperture. As shown in FIG. 6, anisotropic apertures 136, 138 and 140 of virtually any other shape can be formed. Utilizing the present invention, not only does the aperture of a VCSEL tend to be smooth, it can be formed in any arbitrary shape or size. In contrast, a typical oxidation process without a layer disordering step generally produces jagged and uneven boundaries because the oxidation rates of alloys depend upon their crystal orientation. In FIGS. 7 to 10 there is illustrated an alternative embodiment which uses three p-type disorderable layers in lieu of the n-type disorderable layers of the previous embodiment. A typical p-type dopant is magnesium. As can be seen in FIG. 7, the stacked semiconductor structure is in the form of a P-I-N diode as represented by the notation overlying the structure. The structure is very similar to that shown in and described relative to FIG. 1, with the exception that the p-type doping of the disorderable layers requires a reversal in the positioning of the disorderable layers and the active region layers. The stacked structure comprises a highly doped n-type GaAs substrate 142, an n-type superlattice structure, collectively identified as the monolithic region 144, forming a lower distributed Bragg reflector ("DBR"), a group of three intrinsic, undoped, active region layers 146, 148 and 150, a group of three p-type disorderable layers 152, 154 and 156, a p-type superlattice structure, collectively identified as the monolithic region 158, which forms an upper DBR mirror 158, and a p + -GaAs layer 160 deposited for the formation of p-type contacts thereon. As in the above described embodiment, the disorderable layers are associated with the DBR mirror of the same dopant type. The active region layers include a first AlGaAs cladding layer 146 having an aluminum content of about 40% and a thickness of approximately 110 nanometers, a GaAs active layer 148 which comprises one to two quantum wells, each with a thickness of five to ten nanometers, and a second AlGaAs cladding layer 150 having an aluminum content of about 40% and a thickness of approximately 65 nanometers. Although the quantum wells are preferably formed of GaAs, In x Ga 1-x As or Al x Ga 1-x As may also be used, depending upon the desired output wavelength. Of course, other multiple quantum well structures ("MQW") also may be used to form the active layer 148. The p-type disorderable layers include an AlGaAs layer 152 of approximately 20 nanometers, an AlAs layer 154 of about 15 nanometers, and another AlGaAs layer 156 of about 20 nanometers. The magnesium doping of these layers is on the order of 5 x 10 18 cm -3 . Layers 152 and 156 have an aluminum content of approximately 40%, whereas layer 106 has an aluminum content of approximately 100%. After all the semiconductor layers shown in FIG. 7 have been deposited, a silicon nitride layer is deposited on the surface of the semiconductor structure and is photolithographically formed into the capping mask structure 162, as shown in FIG. 8. The portion of the capping mask 162 overlying the location where the aperture is to be formed is removed, thus defining the aperture configuration in this opening 164. The p-type disordering agent, created by the magnesium dopants in the disordering layers 152, 154 and 156 generates Group III interstitials in these layers. During the IILD process, the semiconductor structure is annealed in a furnace at about 800 to 900°C for several (about ten) hours to allow intermixing of the Group III elements, gallium and aluminum, to occur in the region 166 below the opening 164. Arsenic outdiffuses in this space, causing Group V vacancies to increase. But since the number of Group III vacancies (V V ) times the number of Group III vacancies (V III ) must remain constant (V V x V III = k), as the Group V vacancies increase due to arsenic outdiffusion, the number of Group III vacancies decrease. Since there is also a constant relationship between Group III interstitials (I III ) and Group III vacancies (V III ), i.e. I III x V III = k, as the Group III vacancies decrease the Group III interstitials increase, enhancing intermixing in layers 152, 154 and 156 under the opening 164 in the cap 162. During the intermixing process in region, the aluminum composition decreases and the gallium composition increases in the layer 154, which originally had a high aluminum content, while conversely the aluminum composition increases and the gallium composition decreases in the layers 152 and 156 which originally had a low aluminum content. Thus, after a typical IILD process, the intermixed region 166 has an average aluminum content of less than about 95%. In contrast to the first embodiment incorporating n-type disorderable layers, minimal intermixing of Group III elements occurs in the regions directly under the silicon nitride cap 162 with the p-type disorderable layers of this embodiment. After the layer disordering process has been completed, a silicon dioxide layer 168 is deposited on the surface of the semiconductor structure. Layer 168 is masked and an etching process is performed to form mesa 170, as shown in FIG. 9. This exposes the edges of the AlAs layer 154 for the next step, oxidation. The oxidation environment is water vapor at a temperature of 400 to 500°C. Since there exists a difference between the aluminum mole fractions in intermixed region 166 and in the outboard, non-intermixed, regions of the AlAs layer 154, there will be a disparity in the oxidation rates of these two regions because the oxidation rate of AlGaAs varies exponentially with the aluminum mole fraction. For example, the oxidation rate of AlAs with 100% aluminum is about 1.5 µm per minute at 450°C while it is about 0.01 µm per minute for AlGaAs with about 80 percent aluminum. Due to this significant difference in the oxidation rates, oxidation slows down substantially when it reaches the interface between the intermixed and non-intermixed regions. The oxidized regions are identified in FIG. 10 at 172. After the oxidation process has been completed, the silicon nitride cap 162 and the silicon dioxide masking layer 168 are removed. Finally, upper p-type contacts 172 of titanium/gold, and a lower n-type contact 174 of germanium/gold are formed on the semiconductor structure, as shown in FIG. 10. In both embodiments, the intermixed region in the disorderable layers, which defines the aperture of the VCSEL, is accurately formed with relatively smooth and sharp boundaries controlled by the photolithographically formed capping layer mask. Other sources which can cause layer disordering include other p- or n-type impurities as well as Group III or V vacancies. The composition, dopants, doping levels, and dimensions given above are exemplary only, and variations in these parameters are permissible. Additionally, other layers in addition to the ones shown in the figures may also be included. Variations in experimental conditions such as intermixing temperature, time, and oxidation temperature are also permitted. Lastly, instead of GaAs and GaAlAs, other semiconductor materials such as GaAlSb, InAlGaP, or other III-V alloys may also be used.

Claims: A method for forming a vertical cavity surface emitting laser including the steps of : providing a substrate (100); depositing a stack of semiconductor layers on said substrate, said semiconductor layers including: a lower mirror (108), a group of active region layers (110, 118, 114), a group of impurity doped disorderable layers (104, 106, 108), wherein said impurity functions as a disordering agent, and an upper mirror (116); forming a capping mask (120) upon a portion of the surface of said stack of semiconductor layers; annealing said capped stack of semiconductor layers to cause intermixing of a first region of said disorderable layers under the capping mask, while leaving a second region of said disorderable layers surrounding said first region to remain unintermixed; etching said stack of semiconductor layers to form a mesa and to expose the edges of said layers; and converting one of said disorderable layers to become electrically insulating solely in said second region. A method for forming a surface emitting laser as set forth in claim 1 wherein said lower mirror is n-doped, said upper mirror is p-doped, said group of active region layers is undoped, and said group of disordering layers is n-doped and is associated with said lower mirror, and said intermixing of said first region of said disorderable layers occurs directly under said capping mask. A method for forming a vertical cavity surface emitting laser as set forth in claim 1 wherein: said lower mirror is n-doped, said upper mirror is p-doped, said group of active region layers is undoped, and said group of disorderable layers is p-doped and is associated with said upper mirror, said capping mask includes an opening therein, and said intermixing of said first region of said disorderable layers occurs directly under said opening. A method for forming a surface emitting laser as set forth in claims 1 or 2 wherein: when depositing said group of disorderable layers (104, 106, 108) there is provided a central layer (106) having an aluminum content of about 100% and sandwiching layers (104, 108) having an aluminum content of about 40%, and said intermixing in said first region during said annealing step changes the aluminum content of said central layer and said sandwiching layers to an aluminum content lower than said central layer. A method for forming a surface emitting laser as set forth in claim 4 wherein said converting step comprises oxidation. A method for forming a surface emitting laser as set forth in claim 5 wherein the rate of oxidation in said high aluminum content central layer is substantially higher than the rate of oxidation in said lower aluminum content sandwiching layers and said intermixed first region, so that oxidation occurs only in said central layer and stops at the interface between said intermixed and unintermixed regions.

Inventors: FLOYD PHILIP D, SUN DECAI, FLOYD, PHILIP D., SUN, DECAI
Applicants: XEROX CORP, XEROX CORPORATION
Application year: 1998
Main classification: H01S5
IPC codes: H01S5