SYSTEM AND METHOD FOR AUTOMATED DESIGN VERIFICATION

Abstract: A system and method for automated design verification. A test bench (108) stimulates a simulated design (112) with test vectors. A coverage analysis tool (110) monitors output data from the simulated design (112) and identifies portions of the simulated design (112) that remain to be tested. A test generator (106) produces and sends test vectors to the test bench (108) which exercise (i.e., test) the portions of the simulated design (112) that the coverage analysis tool (110) has indicated still remain untested. In the method, a first step executes a simulated design on a test bench. A second step interprets the simulated design as if this design were a state diagram composed of a set of basic blocks interconnected by transition arcs. A third step generates test vectors to exercise some of the basic blocks and transition arcs. A fourth step reports the basic blocks and transition arcs which have not been tested. A fifth step generates a new set of test vectors to exercise the as yet untested basic blocks and transition arcs.

Description: SYSTEM AND METHOD FOR AUTOMATED DESIGN VERIFICATION BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to systems and methods for testing circuit design descriptions, and more particularly to systems and methods for automated design description verification within an electronic design automation (EDA) environment. 2. Discussion of Background Art Electronic Design Automation (EDA) is a process for using computer programs to design, simulate, and test electronic circuits before they are fabricated. By simulating designs with simulation software, on emulation systems, and/or by using simulation acceleration systems, design flaws are detected and corrected before fabrication of the silicon device. A testing before fabrication process saves manufacturers millions of dollars in non- recoverable engineering (NRE) costs. However, as designs increase in complexity, so too does the difficulty of testing. In fact, the difficulty of testing with traditional EDA verification tools increases geometrically with the number of gates. System designers are also asked to design and test these increasingly complex circuits within ever smaller time frames. As a result, manufacturers must choose between either taking more time to test the design, and thereby delaying product shipment, or only testing portions of the circuit, and thereby risking that many undiscovered bugs get passed on to the users. One approach to this problem is to speed up the design simulation programs. Native Code Simulators, Simulation Acceleration, and Chip Emulation System all decrease the time it takes to simulate a design, and may sometimes decrease the time it takes to identify the next bug in a design. However, during early stages of the design process, design bugs are prevalent, and speeding up the simulation does little to help identify these bugs. Another approach is to test the circuit design randomly. Random testing involves generating a plurality of unique test vectors that are randomly related to each other and then testing (or "exercising") the design with these vectors. In this approach, as time allotted for random testing increases, more of the circuit design is tested. Random testing is a time consuming and risky proposition, since discovering bugs then becomes a hit or miss proposition, and there is rarely sufficient time to test the circuit design fully. Moreover, it is quite possible, even likely that running a random simulation for ten or one hundred times longer will not significantly increase the verification density. Other types of EDA testing tools, such as an Automatic Test Pattern Generation (ATPG) tools, produce tests which only identify manufacturing defects in an already fabricated circuit. Testing is performed by successively applying known input values to the pins of the circuit, and then comparing actual output values with a set of expected output values. However, ATPG tools assume that the circuit already has a fundamentally correct design and that any anomalies that are discovered are only due to physical defects introduced in the manufacturing process, such as broken wires. EDA testing tools, such as Verilint, developed by InterHDL of Los Altos, CA; Vericov, developed by Simulation Technology of Saint Paul, Minnesota; Vera, developed by System Science of Palo Alto, CA; and Specman, developed by Verisity of Yehud, Israel; also exist but they are difficult to use, sell, and integrate into a test bench for verifying the correctness of circuit designs. What is needed is an apparatus and method for design verification that overcomes the problems of the prior art. SUMMARY OF THE INVENTION The present invention is a system and a method for automated design verification. Within the system of the present invention, a test bench is created to stimulate a simulated design with test vectors. A coverage analysis tool monitors output data from the simulated design and identifies which portions of the design remain to be tested. A test generator produces test vectors and sends them to the test bench which exercises the portions of the simulated design which the coverage analysis tool has indicated remain to be tested. With the method of the present invention, a design description is interpreted by a test generator as a state diagram composed of a set of basic blocks interconnected by transition arcs. The test generator produces a plurality of test vectors for exercising the basic blocks and transition arcs. A computer program processes the design description and creates a simulated design. Basic blocks and transition arcs within the simulated design are exercised by the plurality of test vectors. Those basic blocks and transition arcs which have (and have not) been exercised are identified by a coverage analysis program which monitors the simulated design's internal operation. The test generator receives these reports and in response produces a new set of test vectors to exercise the basic blocks and transition arcs which were not yet tested. A first set of output data from the simulated design may then be compared against a second set of output data received from a reference. The first set of output data may also be compared with a set of optional constraints. These comparisons result in an anomaly report if the first set of output data is not equivalent to either the second set of output data or the set of optional constraints. The test generator then correlates the basic blocks and transition arcs exercised by the test vectors with the results from the reporting step to localize and identify any of the basic blocks and transition arcs within the simulated design which were operating incorrectly or indeterminately. The apparatus and method of the present invention are particularly advantageous over the prior art because a critical part of design verification — previously performed, manually and on a sporadic basis due to engineering resource requirements and time-to-market considerations ~ is now automated. The present invention permits testing of basic blocks, transition arcs, and paths of interest within the simulated design using a quick, easy, comprehensive, and integrated process. As a result, designers can proceed toward fabrication with confidence that the simulated design has been verified. A time savings of months is achieved, since any design flaws are discovered before the simulated design is fabricated. These and other aspects of the invention will be recognized by those skilled in the art upon review of the detailed description, drawings, and claims set forth below. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a data-flow diagram of a first exemplary system for automated design verification according to the present invention; Figure 2 is a data-flow diagram of a second exemplary system for automated design verification according to the present invention; Figure 3 is a data-flow diagram of a third exemplary system for automated design verification according to the present invention; Figure 4 is a state diagram of an exemplary circuit design that is to be tested with the present invention; Figures 5A and 5B are a flowchart of a method for automated design verification, and are intended to be combined to represent a single flowchart; and Figure 6 is a flowchart of a method for generating a set of test vectors within the method for automated design verification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 is a data-flow diagram of a first exemplary system 100 for automated design verification according to the present invention. The system 100 includes a design database 102, a coverage database 104, a test generator 106, a test bench 108, and a coverage analysis tool 110. The test bench 108 includes a simulated design 112 and an output log database 114. The design database 102 contains one or more circuit designs. These circuit designs are typically coded in a known design language, such as Verilog, VHDL, or C++. These coding languages are also used with other Electronic Design Automation (EDA) tools to simulate, test and fabricate the design of the circuit. The coverage database 104 contains a map of each state and transition arc within a circuit design. As the circuit design's various states are entered and transition arcs are followed, the map in the coverage database 104 is updated to reflect that these states and/or transition arcs have been exercised. The coverage database 104 is coupled to the coverage analysis tool 110. The coverage analysis tool 110 is coupled to the simulated design 112 in the test bench 108, and uses output data from simulated design 112 to determine which areas of the circuit design have been tested. The coverage analysis tool 110 then updates the coverage database 104 based upon this information. Coverage analysis tools are well known in the art. The test generator 106 is coupled to receive data from the design database 102 and the coverage database 104, and in response generates a set of test vectors which are sent to the simulated design 112 in the test bench 108. The simulated design 112 is coupled to receive the test vectors from the test generator 106, and in response generates output data which is sent to both the coverage analysis tool 110 and the output log database 114. The simulated design 112 includes software (such as Verilog or VHDL) which is executed within a computer (not shown) to model the operational characteristics of the circuit design. The output log database 114 stores the output data from the simulated design 112 for later analysis by other EDA tools (not shown). The test bench 108 which executes the simulated design 112 is well known in the art. Before the test generator 106 generates the test vectors, the test generator 106 performs a complete syntax and synthesizability check on a circuit design within the design database 102 that is to be tested. The test generator 106 indicates whether there are any syntax errors in the circuit design, and whether all parts of the design are synthesizable. The test generator 106 then expands any macros and data structures within the design description. Next, the test generator 106 analyzes the design description and identifies all inputs and outputs. The test generator 106 interprets the design description as a series of basic-blocks that are connected by a series of transition arcs, forming a state diagram. This state diagram is also known as a decision tree or a design flow graph. The test generator 106 verifies the stability of each basic block within the state diagram independent of all other basic blocks. A basic block is the smallest building block in a design description. Basic blocks are defined at each point in the state diagram where either a condition is met or a calculation occurs. A set of basic blocks visited by consecutive transition arcs in the state diagram define a path. In a typical design description there are a very large number of paths. However, only a limited number of paths may be of interest to users. These are labeled 'paths- of-interest.' For example, the following design description contains four basic blocks: If (a < b) then 1 st basic block c = a - b 2 nd basic block else c = b - a endif 3 rd basic block result = c * 3 4 th basic block In the above example, transition arcs are defined between the 1 st basic block and the 2 nd basic block, the 1 st basic block and the 3 rd basic block, the 2 nd basic block and the 4 th basic block, and the 3 rd basic block and the 4 th basic block. Paths are defined from the 1 st basic block through the 2 nd basic block to the 4 th basic block, and from the 1 st basic block through the 3 rd basic block to the 4 th basic block. The test generator 106 automatically constructs a first set of test vectors for causing each state of the state machine to be visited and each transition arc to be taken. This first set of test vectors proves whether each of the basic blocks that make up the design description are correct. The test generator 106 then produces a second set of test vectors for proving that user-selected subsets of the basic blocks work together correctly. These subsets of the basic blocks, when linked together, are equivalent to the paths of interest discussed above. All test vectors are generated with the test generator 106 by first identifying any untested design description elements, such as basic blocks, transition arcs, or paths of interest, from the coverage database 104, and then automatically generating a set of test vectors to exercise those elements. This testing may take place at any level of granularity, ranging from the design description's top-level inputs and outputs, to the individual logic elements. The test generator 106 creates a test vector by first determining which basic block, transition arc, or path is to be tested next. The test generator 106 then determines what variables need to be set or what conditions need to occur so that the simulated design 112 transitions to an untested element from a currently active basic block. This is called "back-solving." The test generator may also use a "forward solving" approach to decide what sequence of actions to take in order to activate targeted arcs, blocks, or paths from the given state of the design. In general, the test generator 106 chooses test vectors that exercise a greatest number of untested elements. Active basic blocks are defined as those that are waiting for some variable to be set or condition to occur before passing control to another basic block. Conditions that need to occur are typically defined in terms of some timing constraint. For example, a variable may need to be set to a certain state ten clock pulses after another variable transitions to a different state in order for control to be passed from a currently active basic block to another basic block. A complete set of test vectors is called a test frame. The test frame is submitted to the test bench 108 where the simulated design 112 simulated by the test vectors. In response, the simulated design 112 generates and sends a set of output data to the output log database 114 and the coverage analysis tool 110, as discussed above. Based on the feedback provided by the coverage analysis tool 110, the test generator 106 again checks whether all of the basic blocks, transition arcs, and paths of interest have been tested. If any remain untested, the test generator 106 repeats the back-solving process. During the course of this iterative testing, the test generator 106 uses the data in the coverage database 104 to explore whether the simulated design 112 is stable for all given inputs, and whether the simulated design 112 contains any un-reachable states or un-exercisable transition arcs. Figure 2 is a data-flow diagram of a second exemplary system 200 for automated design verification according to the present invention. In addition to the elements introduced in Figure 1 , the second system 200 includes a functional model 202. This model 202 is coupled to receive test vectors from the test generator 106, output data from the simulated design 112, and verify the output data's accuracy. The functional model 202 compares the output data from the simulated design 112 with a set of expected values generated by the functional model 202. These expected values are intended to reflect how the design description should operate in response to the test vectors generated by the test generator 106. The functional model 202 labels the output data from the simulated design 112 as either correct or incorrect. The functional model 202 also flags indeterminate conditions, such as when the simulated design 112 does not generate any output data in response to a test vector. The functional model 202 is a non-cycle-accurate model of the simulated design 112. A non-cycle-accurate model is one that does not attempt to mimic the simulated design 112 during each cycle of the simulation. The functional model 202 can generate a set of expected values in one of several ways. For instance, the functional model 202 can be implemented as a database lookup table or as an algorithm. For example, while the simulated design may be comprised of a set of commands for defining a series of AND and OR gates interconnected with latches and registers, which together implement a multiplication function, the functional model 202 could simply perform a logical multiplication with a program written with an off-the-shelf C or C++ programming language. The test generator 106 is coupled to receive the results generated by the functional model 202, thus creating a second feedback loop in the system 200. The test generator 106 correlates the test vectors sent to the simulated design 112 with the results from the functional model 202 to localize and identify which of the basic blocks, transition arcs, and/or paths within the simulated design 112 operate incorrectly or indeterminately. The test generator 106 can then be programmed to automatically generate a more detailed series of tests focused on the incorrect or indeterminate design elements. Alternatively, the test generator 106 only prints out the set of test results which a designer then uses to manually generate a more detailed series of tests. Figure 3 is a data-flow diagram of a third exemplary system 300 for automated design verification according to the present invention. In addition to the elements introduced in Figure 1 , the third system 300 includes a cycle accurate model 302 and an output sequence comparator 304. The cycle accurate model 302 is coupled to receive the test vectors from the test generator 106 and is designed to match cycle-for-cycle the output data from the simulated design 112. The output sequence comparator 304 is coupled to receive output data from both the simulated design 112 and the cycle accurate model 302. The output sequence comparator 304 compares every cycle of the output data and generates a set of results which labels the output data from the simulated design 112 as either correct, incorrect, or indeterminate. The test generator 106 is coupled to receive the results generated by the output sequence comparator 304, thus creating a second feedback loop in the system 300. The test generator 106 then correlates the test vectors sent to the simulated design 112 with the results from the output sequence comparator 304 to localize and identify whether the basic blocks, transition arcs, and/or paths within the simulated design 112 are operating incorrectly or indeterminately. The test generator 106 is then programmed to either automatically generate a more detailed series of tests which center about any incorrect or indeterminate design elements, or to print out the results for a designer to review. The test generator 106, the coverage analysis tool 110, the simulated design 112, the functional model 202, the cycle accurate model 302, and the output sequence comparator 304 are software modules comprised of computer program instructions that run on a computer (not shown). The computer includes a processing unit and a memory. The memory stores computer program instructions for controlling how the processing unit accesses, transforms and outputs data. Those skilled in the art will recognize that the internal memory can be supplemented with other computer useable storage media, including a compact disk, a magnetic drive or a dynamic random access memory. Figure 4 is a state diagram 400 of an exemplary circuit design tested using the present invention. The following discussion illustrates how the test generator 106 produces a set of test vectors to test the state diagram 400 and how the test generator 106 responds to the test results. To begin, the test generator 106 has identified six basic blocks 402 through 412 and seven transition arcs 414 through 426. At least four paths exist, however, recursive arc 426 theoretically permits an infinite number of paths to be defined. The test generator 106 proceeds to generate test vectors which set variables A and B so that each basic block, transition arc, and path of interest is tested. Predetermined paths of interest are loaded into the test generator 106 by a user. The test generator 106 can also be pre-programmed with assertions, which will generate an alert upon the occurrence of certain conditions, (for example, if C ever equals D). During testing of basic block 410 in the state diagram 400, for example, the test generator 106 exercises transition arc 424, where C < 40, and transition arc 426, where C > 40. However, the test generator 106 also attempts to test the case where C = 40. Since a next state has not been defined in the state diagram 400 for the case where C = 40, the test generator alerts a user to this indeterminate case. It is through this automatic testing process that the circuit design is fully tested and any errors in the design are brought to a user's attention. Figures 5A and 5B are a flowchart of a method for automated design verification and are intended to be combined to represent a single flowchart. The method begins in step 502 where the test generator 106 imports a design description (typically defined in terms of a hardware description language such as Verilog or VHDL) from the design database 102, and the test bench 108 imports a reference description from another database (not shown). The reference description optionally forms the basis of either the functional model 202 or the cycle accurate model 302. Next, in step 504, the test generator 106 decomposes the design description into basic blocks, transition arcs, and paths of interest to form a state diagram. In step 506, the test generator 106 identifies all input, output, and internal variables in the design description. In step 508, the test generator 106 identifies all state machines in the design description. Then, in step 510, the test generator 106 imports coverage data, describing how much of the design description has already been tested, from the coverage database 104. In step 512, the test generator 106 generates a set of test vectors that test those areas of the design description that have not yet been covered. (Step 512 is further described in Figure 6.) In step 514, the test generator 106 creates the simulated design 112 and a simulated reference on the test bench 108. The simulated reference is equivalent to a first portion of the functional model 202, or alternatively to the cycle accurate model 302. Now, in step 516, the test generator 106 transmits the test vectors to the test bench 108 for exercising the simulated design 112 and the simulated reference. In step 518, a second portion of the functional model 202, or alternatively the output sequence comparator 304, compares output data from both the simulated design 112 and the simulated reference. In step 520, the second portion of the functional model 202, or alternatively the output sequence comparator 304, reports that a bug exists in the simulated design 112 if the output data sets are not equivalent. Next, in step 522, the test generator 106 correlates the basic blocks, transition arcs, and/or paths exercised by the test vectors with the results from the reporting step (step 520) to localize and identify the basic blocks, transition arcs, and/or paths within the simulated design which operate incorrectly or indeterminately. In step 524, the coverage analysis tool 110 modifies the coverage data to indicate which new basic blocks, transition arcs, and/or paths of interest within the simulated design 112 have now been tested. In step 526, if any basic blocks, arcs, or paths of interest are still to be tested the method returns to step 510, otherwise the process ends. Figure 6 is a flowchart of a method for generating a set of test vectors for step 512 of the method of Figures 5A and 5B. The method begins in step 602 where the test generator 106 identifies which basic blocks are currently active in the simulated design description. A data base of active basic blocks is maintained by the system by continuously tracking the flow of control and data throughout the simulated system. Then, in step 604, the test generator 106 accesses the coverage database 104 to identify which basic blocks, transition arcs, and paths of interest have not yet been tested. In step 606, the test generator 106 identifies what variables need to be set and what conditions need to occur for the simulated design 112 to exercise, using one set of test vectors, a greatest number of those basic blocks, transition arcs, or paths of interest have not yet been tested. In step 608, the test generator 106 generates a set of test vectors for setting the identified variables and for causing the identified conditions to occur. After step 608, the method for generating a set of test vectors ends. While the present invention has been described with reference to a preferred embodiment, those skilled in the art will recognize that various modifications may be made. Variations upon and modifications to the preferred embodiment are provided by the present invention, which is limited only by the following claims.

Claims: WHAT TS CLAIMED IS: 1. A method for automated design verification comprising the steps of: importing coverage data which lists an untested portion of a simulated design; and generating a test vector for stimulating the untested portion. 2. The method of claim 1 further comprising the steps of: interpreting the simulated design as a state diagram having a set of basic blocks interconnected by transition arcs; and identifying an untested basic block from the coverage data; wherein the generating step generates a test vector for testing the untested basic block. 3. The method of claim 1 further comprising the steps of: interpreting the simulated design as a state diagram having a set of basic blocks interconnected by transition arcs; and identifying an untested transition arc from the coverage data; wherein the generating step generates a test vector for testing the untested transition arc. 4. The method of claim 1 further comprising the steps of: interpreting the simulated design as a state diagram having a set of paths; and identifying an untested path from the coverage data; wherein the generating step generates a test vector for testing the untested path. 5. The method of claim 1 further comprising the step of: interpreting the simulated design as a state diagram comprised of a set of basic blocks interconnected by transition arcs; wherein the generating step comprises the steps of: identifying an active basic block; identifying an untested basic block; and generating a test vector for causing the simulated design to transition from the active basic block to the untested basic block. 6. The method of claim 5 wherein the generating step further comprises the steps of: identifying an untested transition arc; and generating a test vector for causing the simulated design to transition through the untested transition arc. 7. The method of claim 5 wherein the generating step further comprises the steps of: identifying a plurality of untested basic blocks; and generating a test vector for causing the simulated design to transition from the active basic block to a greatest number of the untested basic blocks. 8. The method of claim 5 wherein the generating step further comprises the steps of: identifying a plurality of untested transition arcs; and generating a test vector for causing the simulated design to transition through a greatest number of the untested transition arcs. 9. A method for automated design verification comprising the steps of: instantiating a simulated design and a simulated reference on a test bench; interpreting the simulated design as a state diagram having a set of basic blocks interconnected by transition arcs; exercising both the simulated design and the simulated reference with a test vector; comparing a first set of output data from the simulated design with a second set of output data from the simulated reference; reporting an anomaly in the simulated design if the first and second sets of output data are not equivalent; and correlating the basic blocks and transition arcs exercised by the test vectors with results from the reporting step to localize and identify the basic blocks and transition arcs which operate incorrectly or indeterminately within the simulated design. 10. The method of claim 9 wherein the comparing step includes comparing the first set of output data with a second set of output data stored in a database. 11. The method of claim 9 wherein the comparing step includes comparing the first set of output data with the second set of output data calculated by a non-cycle accurate procedure. 12. The method of claim 9 wherein the comparing step includes comparing the first set of output data with a second set of output data during every cycle of the simulated design. 13. A system for automated design verification comprising: means for importing coverage data which lists an untested portion of a simulated design; and means for generating a test vector for stimulating the untested portion. 14. The system of claim 13 further comprising: means for interpreting the simulated design as a state diagram having a set of basic blocks interconnected by transition arcs; and means for identifying an untested basic block from the coverage data; wherein the means for generating generates a test vector for testing the untested basic block. 15. The system of claim 13 further comprising: means for interpreting the simulated design as a state diagram having a set of basic blocks interconnected by transition arcs; and means for identifying an untested transition arc from the coverage data; wherein the means for generating generates a test vector for testing the untested transition arc. 16. The system of claim 13 further comprising: means for interpreting the simulated design as a state diagram having a set of paths; and means for identifying an untested path from the coverage data; wherein the means for generating generates a test vector for testing the untested path. 17. The system of claim 13 further comprising: means for interpreting the simulated design as a state diagram comprised of a set of basic blocks interconnected by transition arcs; wherein the means for generating comprises: means for identifying an active basic block; means for identifying an untested basic block; and means for generating a test vector for causing the simulated design to transition from the active basic block to the untested basic block. 18. The system of claim 17 wherein the means for generating further comprises: means for identifying an untested transition arc; and means for generating a test vector for causing the simulated design to transition through the untested transition arc. 19. The system of claim 1 wherein the means for generating further comprises: means for identifying a plurality of untested basic blocks; and means for generating a test vector for causing the simulated design to transition from the active basic block to a greatest number of the untested basic blocks. 20. The system of claim 17 wherein the means for generating further comprises: means for identifying a plurality of untested transition arcs; and means for generating a test vector for causing the simulated design to transition through a greatest number of the untested transition arcs. 21. A system for automated design verification comprising: means for instantiating a simulated design and a simulated reference on a test bench; means for interpreting the simulated design as a state diagram having a set of basic blocks interconnected by transition arcs; means for exercising both the simulated design and the simulated reference with a test vector; means for comparing a first set of output data from the simulated design with a second set of output data from the simulated reference; means for reporting an anomaly in the simulated design if the first and second sets of output data are not equivalent; and means for correlating the basic blocks and transition arcs exercised by the test vectors with results from the reporting step to localize and identify the basic blocks and transition arcs which operate incorrectly or indeterminately within the simulated design. 22. The system of claim 21 wherein the means for comparing includes means for comparing the first set of output data with a second set of output data stored in a database. 23. The system of claim 21 wherein the means for comparing includes means for comparing the first set of output data with the second set of output data calculated by a non-cycle accurate procedure. 24. The system of claim 21 wherein the means for comparing includes means for comparing the first set of output data with a second set of output data during every cycle of the simulated design. 25. A computer-useable medium embodying computer program code for causing a computer to effect automated design verification by performing the steps of: importing coverage data which lists an untested portion of a simulated design; and generating a test vector for stimulating the untested portion. 26. The computer-useable medium of claim 25 further comprising the steps of: interpreting the simulated design as a state diagram having a set of basic blocks interconnected by transition arcs; and identifying an untested basic block from the coverage data; wherein the generating step generates a test vector for testing the untested basic block. 27. The computer-useable medium of claim 25 further comprising the steps of: interpreting the simulated design as a state diagram having a set of basic blocks interconnected by transition arcs; and identifying an untested transition arc from the coverage data; wherein the generating step generates a test vector for testing the untested transition arc. 28. The computer-useable medium of claim 25 further comprising the steps of: interpreting the simulated design as a state diagram having a set of paths; and identifying an untested path from the coverage data; wherein the generating step generates a test vector for testing the untested path. 29. The computer-useable medium of claim 25 further comprising the step of: interpreting the simulated design as a state diagram comprised of a set of basic blocks interconnected by transition arcs; wherein the generating step comprises the steps of: identifying an active basic block; identifying an untested basic block; and generating a test vector for causing the simulated design to transition from the active basic block to the untested basic block. 30. The computer-useable medium of claim 29 wherein the generating step further comprises the steps of: identifying an untested transition arc; and generating a test vector for causing the simulated design to transition through the untested transition arc. 31. The computer-useable medium of claim 29 wherein the generating step further comprises the steps of: identifying a plurality of untested basic blocks; and generating a test vector for causing the simulated design to transition from the active basic block to a greatest number of the untested basic blocks. 32. The computer-useable medium of claim 29 wherein the generating step further comprises the steps of: identifying a plurality of untested transition arcs; and generating a test vector for causing the simulated design to transition through a greatest number of the untested transition arcs. 33. A computer-useable medium embodying computer program code for causing a computer to effect automated design verification by performing the steps of: instantiating a simulated design and a simulated reference on a test bench; interpreting the simulated design as a state diagram having a set of basic blocks interconnected by transition arcs; exercising both the simulated design and the simulated reference with a test vector; comparing a first set of output data from the simulated design with a second set of output data from the simulated reference; reporting an anomaly in the simulated design if the first and second sets of output data are not equivalent; and correlating the basic blocks and transition arcs exercised by the test vectors with results from the reporting step to localize and identify the basic blocks and transition arcs which operate incorrectly or indeterminately within the simulated design. 34. The computer-useable medium of claim 33 wherein the comparing step includes comparing the first set of output data with a second set of output data stored in a database. 35. The computer-useable medium of claim 33 wherein the comparing step includes comparing the first set of output data with the second set of output data calculated by a non-cycle accurate procedure. 36. The computer-useable medium of claim 33 wherein the comparing step includes comparing the first set of output data with a second set of output data during every cycle of the simulated design. 37. A system for automated design verification comprising: a test bench for operating a simulated design; a coverage analysis tool coupled to receive output data from the test bench, for identifying untested portions of the simulated design; a test generator coupled to the test bench and the coverage analysis tool, for generating and sending test vectors to the test bench for exercising the untested portions of the simulated design. 38. The system of claim 37 wherein the test bench further comprises a functional model coupled to receive the test vectors from the test generator and output data from the simulated design, calculate an expected set of output data using an algorithm, compare the expected data with output data from the simulated design, and report deviations. 39. The system of claim 37 wherein the test bench further comprises a functional model coupled to receive the test vectors from the test generator, output data from the simulated design, lookup an expected set of output data from a database, compare the expected data with the output data from the simulated design, and report deviations. 40. The system of claim 37 wherein the test bench further comprises a functional model coupled to receive the test vectors from the test generator, output data from the simulated design, calculate for every cycle of the simulated design an expected set of output data, compare the expected data with the output data from the simulated design every cycle, and report deviations.

Inventors: MASSEY DAVID TODD, MCNAMARA MICHAEL THOMAS YORK, TAN CHONG GUAN, MASSEY, DAVID, TODD, MCNAMARA, MICHAEL, THOMAS, YORK, TAN, CHONG, GUAN
Applicants: SUREFIRE VERIFICATION INC, SUREFIRE VERIFICATION INC.
Application year: 1998
Main classification: G06F17
IPC codes: G01R31, G06F11, G06F17