A METHOD AND APPARATUS FOR MULTI-FUNCTION ARITHMETIC

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines. The segments may be rounded by adding a rounding constant. Rounding and normalization may be performed in two paths, one assuming an overflow will occur, the other assuming no overflow will occur. The multiplier may also be configured to perform iterative calculations to evalutate constant powers of an operand. Intermediate products that are formed may be rounded and normalized in two paths and then compressed and stored for use in the next iteration. An adjustment constant may also be added to increase the frequency of exactly rounded results.

Description: Title: A Method and Apparatus for Multi-Function Arithmetic BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generally to the field of microprocessors and, more particularly, to multipliers in microprocessors. 2. Description of the Related Art Microprocessors are typically designed with a number of "execution units" that are each optimized to perform a particular set of functions or instructions. For example, one or more execution units within a microprocessor may be optimized to perform memory accesses, i.e., load and store operations. Other execution units may be optimized to perform general arithmetic and logic functions, e.g., shifts and compares. Many microprocessors also have specialized execution units configured to perform more complex arithmetic operations such as multiplication and reciprocal operations. These specialized execution units typically comprise hardware that is optimized to perform one or more particular arithmetic functions. In the case of multiplication, the optimized hardware is typically referred to as a "multiplier." In older microprocessors, multipliers were implemented using designs that conserved die space at the expense of arithmetic performance. Until recently, this was not a major problem because most applications, i.e., non-scientific applications such as word processors, did not frequently generate multiplication instructions. However, recent advances in computer technology and software are placing greater emphasis upon multiplier performance. For example, three dimensional computer graphics, rendering, and multimedia applications all rely heavily upon a microprocessor's arithmetic capabilities, particularly multiplication and multiplication-related operations. As a result, in recent years microprocessor designers have favored performance-oriented designs that use more die space. Unfortunately, the increased die space needed for these high performance multipliers reduces the space available for other execution units within the microprocessor. Thus, a mechanism for increasing multiplier performance while conserving die space in needed. The die space used by multipliers is of particular importance to microprocessor designers because many microprocessors, e.g., those configured to execute MMX™ (multimedia extension) or 3D graphics instructions, may use more than one multiplier. MMX and 3D graphics instructions are often implemented as "vectored" instructions. Vectored instructions have operands that are partitioned into separate sections, each of which is independently operated upon. For example, a vectored multiply instruction may operate upon a pair of 32-bit operands, each of which is partitioned into two 16-bit sections or four 8-bit sections. Upon execution of a vectored multiply instruction, corresponding sections of each operand are independently multiplied. Fig. 1 illustrates the differences between a scalar (i.e., non-vectored) multiplication and a vector multiplication. To quickly execute vectored multiply instructions, many microprocessors use a number of multipliers in parallel. In order to conserve die space, a mechanism for reducing the number of multipliers in a microprocessor is desirable. Furthermore, a mechanism for reducing the amount of support hardware (e.g., bus lines) that may be required for each multiplier is also desirable. Another factor that may affect the number of multipliers used within a microprocessor is the microprocessor's ability to operate upon multiple data types Most microprocessors must support multiple data types For example, x86 compatible microprocessors execute instructions that are defined to operate upon an integer data type and instructions that are defined to operate upon floating pomt data types Floating pomt data can represent numbers within a much larger range than mteger data For example, a 32-bit signed mteger can represent the mtegers between -2 31 and 2 31 -1 (usmg two's complement format) In contrast, a 32-bit ("single precision") floating pomt number as defined by the Institute of Electrical and Electronic Engineers (IEEE) Standard 754 has a range (m normalized format) from 2 126 to 2' 27 x(2-2 23 ) m both positive and negative numbers While both mteger and floating point data types are capable of representmg positive and negative values, mtegers are considered to be "signed" for multiplication purposes, while floating pomt numbers are considered to be "unsigned " Integers are considered to be signed because they are stored in two's complement representation Turning now to Fig 2 A, an exemplary format for an 8-bit mteger 100 is shown As illustrated in the figure, negative mtegers are represented using the two's complement format 104 To negate an integer, all bits are inverted to obtain the one's complement format 102 A constant of one is then added to the least significant bit (LSB) Turning now to Fig 2B, an exemplary format for a 32-bit (single precision) floating point number is shown A floating point number is represented by a significand, an exponent and a sign bit The base for the floating pomt number is raised to the power of the exponent and multiplied by the significand to arrive at the number represented In microprocessors, base 2 is typically used The significand comprises a number of bits used to represent the most significant digits of the number Typically the significand comprises one bit to the left of the radix point and the remaining bits to the right of the radix point In order to save space, the bit to the left of the radix point, known as the mteger bit, is not explicitly stored Instead it is implied in the format of the number Additional information regarding floating pomt numbers and operations performed thereon may be obtained in IEEE Standard 754 Unlike the integer representation, two's complement format is not typically used m the floating pomt representation Instead, sign and magnitude form are used Thus, only the sign bit is changed when converting from a positive value 106 to a negative value 108 For this reason, many microprocessors use two multipliers, I e , one for signed values (two s complement format) and another for unsigned values (sign and magnitude format) Thus, a mechanism for increasing floating pomt, mteger, and vector multiplier performance while conserving die space is needed SUMMARY OF THE INVENTION The problems outlmed above are m large part solved by a multiplier configured m accordance with the present mvention In one embodiment, the multiplier may perform signed and unsigned scalar and vector multiplication using the same hardware The multiplier may receive either signed or unsigned operands in either scalar or packed vector format and accordmgly output a signed or unsigned result that is either a scalar or a vector quantity Advantageously, this embodiment may reduce the total number of multipliers needed within a microprocessor because it may be shared by execution units and perform both scalar and vector multiplication This space savings may in turn allow designers to optimize the multiplier for speed without fear of usmg too much die space In another embodiment, speed may be increased by configuring the multiplier to perform fast rounding and normalization This may be accomplished configuring the multiplier to calculate two version of an operand, e g , an overflow version and a non-overflow version, m parallel and then select between the two versions In other embodiments, the multiplier may be further optimized to perform certain calculations such as evaluating constant powers of an operand (e g , reciprocal or reciprocal square root operations) Iterative formulas may be used to recast these operations into multiplication operations Iterative formulas generate intermediate products which are used in subsequent iterations to achieve greater accuracy In some embodiments, the multiplier may be configured to store these intermediate products for future iterations Advantageously, the multiplier may be configured to compress these intermediate products before storing them, which may further conserve die space In one embodiment, the multiplier may comprise a partial product generator, a selection logic unit, and an adder The multiplier may also comprise a multiplicand input configured to receive a multiplicand operand (signed or unsigned), a multiplier mput configured to receive a multiplier operand (also signed or unsigned), and a sign-m input The sign-m input is configured to receive a sign-m signal indicative of whether the multiplier is to perform signed or unsigned multiplication The partial product generator, which is coupled to the multiplicand input, is configured to generate a plurality of partial products based upon the multiplicand operand The selection logic unit, which is coupled to the partial product generator and the multiplier input, is configured to select a number of partial products from the partial product generator based upon the multiplier operand The adder, which is coupled to the selection logic unit, is configured to sum the selected partial products to form a final product The final product, which may be signed or unsigned, may then be output to other parts of the microprocessor In addition, the multiplier may further comprise an "effective sign" calculation unit In one embodiment, the calculation unit may comprise a pan: of AND gates, each configured to receive the most significant bit of one operand and the sign-m signal The output of each AND gate is used as the effective sign for that gate's operand The effective sign may be appended to each operand for use as the operand's sign durmg the multiplication process Advantageously, the effective sign may allow both unsigned operands and signed operands to be multiplied on the same hardware A method for operating a multiplier withm a microprocessor is also contemplated In one embodiment, the method comprises receiving a multiplier operand, a multiplicand operand, and a sign-m signal from other functional units withm the microprocessor An effective sign bit for the multiplicand operand is generated from the sign-m signal and the most significant bit of the multiplicand operand A plurality of partial products may then be calculated from the effective sign bit and the multiplicand operand Next, a number of the partial products may be selected according to the multiplier operand The partial products are then summed, and the results are output In other embodiments, the steps may be performed in parallel or m a different order In another embodiment, the multiplier may be capable of multiplying one pan of N-bit operands or two pans of N/2-bιt operands simultaneously The multiplier may comprise a multiplier input and a multiplicand mput, each configured to receive an operand comprising one N-bit value or two N/2-bιt values The multiplier may also compπse a partial product generator coupled to the multiplicand input, wherein the partial product generator is configured to generate a plurality of partial products based upon the value of the multiplicand operand The multiplier may further compπse a selection logic unit coupled to the partial product generator and the multiplier mput The selection logic unit may be configured to select a plurality of partial products from the partial product generator based upon the value of the multiplier operand An adder may be coupled to the selection logic unit to receive and sum the selected partial products to form a final product compπsmg either one 2N-bιt value or two N-bit values The multiplier may receive a vector_ιn signal indicating whether vector or scalar multiplication is to be formed A method for operating a multiplier capable of scalar and vector multiplication is also contemplated The method may compπse receivmg a multiplier operand, a multiplicand operand, and a vector-m signal as mputs from functional units withm the microprocessor and then calculating a number of partial products from the multiplicand operand usmg mverters and shiftmg logic Certam partial products may be selected accordmg to the multiplier operand The selected partial products may then be summed to generate a final product The final product may be m scalar form if the vector_ιn signal is unasserted, and in vector form if the vector in signal is asserted In another embodiment, the multiplier may also be configured to calculate vector dot products and may comprise a multiplier mput and a multiplicand input, each configured to receive a vector A partial product generator may be coupled to the multiplicand input and may be configured to generate a plurality of partial products based upon one of the vectors A first adder may be coupled to receive the partial products and sum them to generate vector component products for each pair of vector components A second adder may be coupled to the first adder and may be configured to receive and sum the vector component products to form a sum value and a carry value A third adder may be configured to receive the sum and carry values and one or more vector component products from the first adder The third adder may be configured to output the sum of the sum and carry values (and any carry bits resulting from the summation of the one or more vector components) as a final result In yet another embodiment, the multiplier may be configured to output the results m segments or portions This may advantageously reduce me amount of interface logic and the number of bus lines needed to support the multiplier Furthermore, the segments or portions may be rounded In this embodiment, the multiplier may comprise a multiplier input, a multiplicand input, and a partial product generator The generator is coupled to the multiplicand input and is configured to generate one or more partial products An adder, coupled to the partial product generator and the multiplier mput, may be configured to receive a number of the partial products The adder may sum the partial products together with roundmg constants to form a plurality of vector component products which are logically divided into portions One or more of the portions may be rounded In another embodiment, the multiplier may be configured to round its outputs in a number of different modes Thus, an apparatus and method for roundmg and normalizing results withm a multiplier is also contemplated In one embodiment, the apparatus comprises an adder configured to receive a plurality of redundant- form components The adder is configured to sum the redundant- form components to generate a first non-redundant-form result The adder may also be configured to generate a second non-redundant-form result comprising the sum of the redundant- form components plus a constant Two shifters are configured to receive the results Both shifters may be controlled by the most significant bits of the results they receive A multiplexer may be coupled to receive the output from the shifters and select one of them for output based upon the least significant bits in the first non-redundant- form result By generating more than version of the result (e g , the result and the result plus a constant) in parallel, roundmg may be accomplished m less time than previously required A multiplier configured to round and normalize products is also contemplated In one embodiment, the multiplier may comprise two paths Each path may compnse one or more adders, each configured to receive a redundant-form product and reduce it to a non-redundant form The first path does so assuming no overflow will occur, while the second path does so assuming an overflow will occur A multiplexer may be coupled to the outputs of the two paths, so as to select between the results from the first and second paths A method for roundmg and normalizing results withm a multiplier is also contemplated In one embodiment, the method compπses multiplying a first operand and a second operand to form a plurality of redundant-form components A roundmg constant is generated and added to the redundant-form component m two different bit positions The first position assumes an overflow will occur, while the second position assumes no overflow will occur A particular set of bits are selected for output as the final result from either the first addition or the second addition Also contemplated is an apparatus for evaluating a constant power of an operand using a multiplier In one embodiment, the apparatus comprises an initial estimate generator configured to receive the operand and output an initial estimate of the operand raised to the desired constant power A multiplier may be coupled to receive the operand and the initial estimate, wherein the multiplier is configured to calculate the product of the initial estimate and the operand A first plurality of mverters may be coupled to receive, invert, and normalize selected bits from the product to form a first approximation, wherem the first approximation assumes an overflow has occurred m the multiplier A second plurality of mverters may be coupled to receive, invert, and normalize selected bits from the product to foπn a second approximation, wherem the second approximation assumes an overflow has not occurred m the multiplier A multiplexer may be configured to select either the first or second approximations for output Also contemplated is a method for evaluatmg a constant power of an operand usmg a multiplier In one embodiment, the method comprises determining an initial estimate of the operand raised to a first constant power The operand and the initial estimate are then multiplied m the multiplier to form a first product A normalized first intermediate approximation is calculated by performing a bit- wise inversion on the first product assuming an overflow occurred durmg the multiplying A normalized second intermediate approximation is calculated by performing a bit-wise inversion on the first product assuming no overflow occurred durmg the multiplying Finally, a set of bits are selected from either the first intermediate approximation or the second intermediate approximation to form a selected approximation that may be output or used m subsequent iterations to achieve a more accurate result An apparatus for roundmg and normalizing a redundant-form value is also contemplated In one embodiment, the apparatus may comprise two adders and a multiplexer The first adder is configured to receive the redundant-form value and add a rounding constant to its guard bit position, thereby forming a first rounded result, wherem the guard bit position is selected assuming no overflow will occur The second adder is similarly configured and performs the same addition assummg, however, that an overflow will occur A multiplexer is configured to select either the first rounded result or the second rounded result based upon one or more of the most significant bits from the first and second rounded results Performing the roundmg m parallel may advantageously speed the process by allowing normalization to take place m parallel with the multiplexer's selection A method for operatmg a multiplier that compresses intermediate results is also contemplated In one embodiment, this method comprises calculating an intermediate product to a predetermined number of bits of accuracy Next, a signaling bit is selected from the intermediate product The signaling bit is equal to each of the N most significant bits of the intermediate product Next, the intermediate product is compressed by replacing the N most significant bits of the intermediate product with the signaling bit The compressed intermediate product is then stored into a storage register During the next iteration, the storage register is read to determine the value of the compressed intermediate product The compressed intermediate product may be expanded to form an expanded intermediate product by paddmg the compressed intermediate product with copies of the signaling bit A multiplier configured to perform iterative calculations and to compress intermediate products is also contemplated In one embodiment, the multiplier comprises a multiplier input, a multiplicand mput, and a partial product generatoi as described m previous embodiments The multiplier also comprises a partial product array adder which is configured to receive and add a selected plurality of partial products to form an mtermediate product Compression logic may be coupled to the partial product array adder The compression logic may comprise a wire shifter configured to replace a predetermined number of bits of the intermediate product with a smgle signal bit, which represents the information stored m the predetermined number of bits The signal bit is selected so that it equals the value of each individual bit withm the predetermined number of bits A storage register may be coupled to receive and store the compressed intermediate product from the compression logic In another embodiment, the multiplier may be configured to add an adjustment constant to increase the frequency of exactly rounded results In such an embodiment, the multiplier may comprise a multiplier mput configured to receive a multiplier operand, a multiplicand input configured to receive a multiplicand operand, a partial product generator, and selection logic In one embodiment, the partial product generator is coupled to the multiplicand mput and configured to generate one or more partial products based upon the multiplicand operand The selection logic may be coupled to the partial product generator and the multiplier, wherem the selection logic is configured to select a plurality of partial products based upon the multiplier The partial product array adder may be coupled to the selection logic, wherem the adder is configured to receive and sum a number of the partial products and an adjustment constant to form a product The adjustment constant is selected to mcrease the frequency that the result is exactly rounded A method for mcreasmg the frequency of exactly rounded results is also contemplated In one embodiment, the method compnses receivmg an operand and determining an initial estimate of the result of an iterative calculation usmg the operand The initial estimate and the operand are multiplied to generate an intermediate result The multiplication is repeated a predetermined number of times, wherem the mtermediate result is used m place of the initial estimate in subsequent iterations The final repetition generates a final result, and an adjustment constant may be added to the final result, wherem the adjustment constant increases the probability that the final result will equal the exactly rounded result of the iterative calculation BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the mvention will become apparent upon readmg the followmg detailed descπption and upon reference to the accompanying drawings m which Fig 1 is a diagram illustratmg an exemplary scalar multiplication and an exemplary vector multiplication Fig 2A is a diagram of an exemplary mteger data format usmg two's complement representation Fig 2B is a diagram of an exemplary floating pomt data format Fig 3 is a block diagram of one embodiment of an exemplary microprocessor Fig 4 is a block diagram of one embodiment of the computational core from the microprocessor of Fig 3 Fig 5 A illustrates one embodiment of the shift-and-add algorithm for binary multiplication Fig 5B illustrates one embodiment of Booth's algorithm for binary multiplication Fig 6 is a block diagram illustrating details of one embodiment of the multiplier from Fig 4 Fig 7 is a block diagram illustrating the operation of the multiplier from Fig 6 for unsigned operands Fig 8 is a block diagram illustratmg an example of the operation of the multiplier from Fig 6 for signed operands Fig 9 is a block diagram illustratmg another example of the operation of the multiplier from Fig 6 for signed operands Fig 10 is a diagram illustratmg one embodiment of the multiplier from Fig 4 that is configured to perform vector multiplication Fig 11A is a diagram that illustrates details of one embodiment of the partial product generator from Fig 6 Fig 1 IB is a diagram that illustrates m detail part of one embodiment of the selection logic from Fig 6 Fig 12A-B is a diagram that illustrates details of one embodiment of the selection logic and adder from Fig 6 Fig 13 is a diagram illustrating another embodiment of the multiplier from Fig 4 that is configured to perform vector multiplication Fig 14 is a diagram illustratmg yet another embodiment of the multiplier from Fig 4 that is configured to perform vector multiplication Fig 15 is a diagram illustratmg one embodiment of a multiplier that is configured to calculate the vector dot product of a pan of vector operands Fig 16 is a diagram illustratmg another embodiment of a multiplier that is configured to calculate the vector dot product of a pair of vector operands Fig 17 is a diagram illustratmg one embodiment of a multiplier that is configured to return vector component products in portions, some of which may be rounded Fig 18 is a diagram illustratmg another embodiment of a multiplier that is configured to return vector component products m portions, some of which may be rounded Fig 19 is a diagram illustratmg one embodiment of the multiplier from Fig 6 configured to perform roundmg Fig 20 is a diagram illustratmg a numerical example of the operation of the multiplier from Fig 19 Fig 21 is a diagram illustratmg details of one embodiment of the sticky bit logic from Fig 19 Fig 22 is a diagram illustratmg a numerical example of the operation of the multiplier from Fig 19 Fig 23 is a diagram illustratmg another embodiment of the multiplier from Fig 6 Fig 24 is a flowchart illustratmg one embodiment of a method for calculating the reciprocal of an operand Fig 25 is a flowchart illustratmg one embodiment of a method for calculating the reciprocal square root of an operand Fig 26 is a diagram illustratmg one embodiment of the multiplier from Fig 6 that is configured to perform iterative calculations Fig 27 is a diagram illustrating details of one exemplary embodiment of the non-overflow and overflow logic units from Fig 26 Fig 28 is a diagram illustrating details of another exemplary embodiment of non-overflow and overflow logic units from Fig 26 Fig 29A is a flowchart illustrating one possible method for fast compression Fig 29B is a flowchart illustrating one possible method for fast decompression Fig 30 is a diagram illustrating one embodiment of the multiplier from Fig 4 configured to compress intermediate products Fig 31A is a figure illustrating one possible method for compression Fig 3 IB is a figure illustrating another possible method for compression Fig 32 is a figure illustratmg one embodiment of a multiplier configured to achieve a higher frequency of exactly rounded results Fig 33 A is a diagram illustrating an example of a vector multiplication usmg two multipliers Fig 33B is a diagram illustrating another example of a multiplication usmg two multipliers Fig 34 is a block diagram of one embodiment of a computer system configured to utilize the microprocessor of Fig 3 While the mvention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example m the drawings and will herem be described m detail It should be understood, however, that the drawings and detailed description thereto are not mtended to limit the mvention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling withm the spirit and scope of the present mvention as defined by the appended claims DETAILED DESCRIPTION OF AN EMBODIMENT Turning now to Fig 3, a block diagram of one embodiment of a microprocessor 10 is shown As depicted, microprocessor 10 compπses a predecode logic block 12, a bus mterface unit 24, and a level one-cache controller 18, all of which are coupled to the followmg three caches a level-one mstruction cache 14, a level-one data cache 26, and an on-chip level-two cache 40 Both mstruction cache 14 and data cache 26 are configured with translation lookaside buffers, l e , TLBs 16 and 28, respectively Microprocessor 10 further compπses a decode unit 20 which receives instructions from mstruction cache 14, decodes them, and then forwards them to an execution engme 30 in accordance with inputs received from a branch logic unit 22 Execution engme 30 compnses a scheduler buffer 32, an mstruction control unit 34, and a plurality of execution units 36A-36F Note that blocks referred to herein with a reference number followed by a letter may be collectively refened to by the reference number alone For example, execution units 36A-F may be collectively refeπed to as execution units 36 Scheduler buffer 32 is coupled to receive decoded instructions from decode unit 20 and convey them to execution units 36 m accordance with mput received from mstruction control unit 34 In one embodiment, execution units 36A-F include a load unit 36 A, a store unit 36B, two ιnteger/MMX/3D units 36C and 36D, a floating point unit 36E, and a branch resolving unit 36F Load unit 36A receives mput from data cache 26, while store unit 36B mterfaces with data cache 26 via a store queue 38 Integer/MMX/3D units 36C and 36D, and floating point unit 36E collectively form a computational core 42 for microprocessor 10 Computational core 42 may further comprise other execution units and specialized hardware such as multipliers Before describing computational core 42 m detail, other features of microprocessor 10 will be discussed In one embodiment instruction cache 14 is organized mto sectors, with each sector including two 32-byte cache lmes The two cache lmes withm each sector share a common tag but have separate state bits that mdicate the status of the line Accordmgly, two forms of cache misses (and associated cache fills) may take place (1) sector replacement and (2) cache lme replacement In the case of sector replacement, the cache miss is caused by a tag mismatch m instruction cache 14 Thus the required cache lme is supplied by external memory via bus mterface unit 24 The cache lme withm the sector that is not needed is then marked invalid In the case of a cache lme replacement, a tag matches the requested address but the conespondmg cache lme is marked as invalid The required cache lme is then supplied by external memory, but unlike a sector replacement, the cache lme withm the sector that was not requested remains unaltered In alternate embodiments, other organizations and replacement policies for instruction cache 14 may be utilized In one embodiment, microprocessor 10 may be configured to perform prefetchmg only m the case of sector replacements During sector replacement, the required cache line is filled If the required cache lme is m the first half of the sector, the other cache lme m the sector is prefetched If the required cache lme is m the second half of the sector, no prefetchmg is performed Other prefetchmg methodologies may also be employed m different embodiments of microprocessor 10 When cache lmes of instruction data are retrieved from external memory by bus mterface unit 24, the data is conveyed to predecode logic block 12 In one embodiment, the instructions processed by microprocessor 10 and stored m cache 14 are variable-length (e g , the x86 mstruction set) Because decodmg vaπable-length instructions is particularly complex, predecode logic 12 may be configured to provide additional information to be stored m mstruction cache 14 to aid durmg decode In one embodiment, predecode logic 12 generates "predecode bits" for each byte m mstruction cache 14 The predecode bits may provide vaπous information useful durmg the decode process, e g , the number of bytes to the start of the next variable-length mstruction The predecode bits are passed to decode unit 20 when mstruction bytes are requested from cache 14 In one embodiment, mstruction cache 14 is implemented as a 32-Kbyte, two-way set-associative, writeback cache The cache lme size may be 32 bytes m this embodiment Cache 14 also mcludes a 64-entry TLB that may be used to speed lmear to physical address translation Other variations of mstruction cache 14 are possible and contemplated Instruction cache 14 receives instruction fetch addresses from cache controller 18 In one embodiment, up to 16 bytes may be fetched from cache 14 per clock cycle The fetched information is placed mto an mstruction buffer that feeds mto decode unit 20 In one embodiment of microprocessor 10, fetchmg may occur along a smgle execution stream with seven outstandmg branches taken In another embodiment, fetchmg may take place along multiple execution streams In one embodiment, the mstruction fetch logic withm cache controller 18 is capable of retneving any 16 contiguous mstruction bytes withm a 32-byte boundary of cache 14 with no additional penalty when the 16 bytes cross a cache lme boundary New instructions are loaded into the mstruction buffer as the current instructions are consumed by decode unit 20 Other configurations of cache controller 18 are also possible and contemplated In one embodiment, decode logic 20 may be configured to decode multiple instructions per processor clock cycle Decode unit 20 may further be configured to accept instruction and predecode bytes from the instruction buffer (m x86 format), locate actual mstruction boundaries, and generates conespondmg "RJSC ops" RISC ops are fixed-format internal instructions, most of which are executable by microprocessor 10 m a smgle clock cycle In one embodiment of microprocessor 10, RJSC ops are combined to form every function m the x86 instruction set Microprocessor 10 may use a combmation of decoders to convert x86 instructions mto RISC ops In one embodiment, the hardware comprises three sets of decoders two parallel short decoders, one long decoder, and one \ ector decoder The parallel short decoders translate the most commonly-used x86 instructions (e g , moves, shifts branches, etc ) into zero, one, or two RISC ops each The short decoders only operate on x86 instructions that are up to seven bytes long In addition, thev are configured to decode up to two x86 instructions per clock cycle Commonly-used x86 instructions which are greater than seven bytes long, as well as those semi- commonly-used instructions that are up to seven bytes long, are handled by the long decoder The long decoder in decode unit 20 only performs one decode per clock cycle generatmg up to four RISC ops All other translations (complex instructions, interrupts, etc ) are handled by a combmation of the vector decoder and an on-chip ROM For complex operations, the vector decoder logic provides the first set of RISC ops and an initial address to a sequence of further RISC ops withm the on-chip ROM The RISC ops fetched from the on-chip ROM are of the same type that are generated by the hardware decoders In one embodiment, decode unit 20 generates a group of four RJSC ops each clock cycle For clock cycles m which four RISC ops cannot be generated, decode unit 20 places RISC NOP operations m the remammg slots of the grouping These groupings of RISC ops (and possible NOPs) are then conveyed to scheduler buffer 32 It is noted that m other embodiments, microprocessor 10 may be configured to decode other instructions sets in place of, or in addition to, the x86 mstruction set Instruction control logic 34 contains the logic necessary to manage out-of-order execution of instructions stored in scheduler buffer 32 Instruction control logic 34 also manages data forwarding, register renaming, simultaneous issue and retirement of RISC ops, and speculative execution In one embodiment, scheduler buffer 32 holds up to 24 RJSC ops at one time, which is equivalent to a maximum of twelve x86 instructions When possible, mstruction control logic 34 may simultaneously issue (from buffer 32) RISC ops to any available execution units 36 In one embodiment, control logic 34 may be configured to issue up to six and retire up to four RJSC ops per clock cycle In one embodiment, store unit 36A and load unit 36B may each have two-stage pipelines Store unit 36A may be configured to perform memory and register wπtes such that the data is available for loadmg after one clock cycle Similarly, load unit 36B may be configured to perform memory reads such that the data is available after two clock cycles Other configurations for load and store units 36A and 36B are also possible with varying latencies Execution unit 36G (the branch resolvmg unit) is separate from branch prediction logic 22 m that it resolves conditional branches such as JCC and LOOP after the branch condition has been evaluated Branch resolvmg unit 36G allows efficient speculative execution, enabling microprocessor 10 to execute instructions beyond conditional branches before knowing whether the branch prediction was conect As descnbed above, microprocessor 10 may be configured to handle up to seven outstanding branches m one embodiment Branch prediction logic 22, coupled to decode unit 20, is configured to increase the accuracy with which conditional branches are predicted in microprocessor 10 Ten to twenty percent of the instructions in typical applications mclude conditional branches Branch prediction logic 22 is configured to handle this type of program behavior and its negative effects on instruction execution, such as stalls due to delayed mstruction fetchmg In one embodiment, branch prediction logic 22 includes an 8192-entry branch history table, a 16-entry by 16 byte branch target cache, and a 16-entry return address stack Branch prediction logic 22 may implement a two-level adapti . e history algorithm usmg the branch history table The table stores executed branch information, predicts individual branches, and predicts behavior of groups of branches In one embodiment, the branch history table does not store predicted target addresses in order to save space Instead, the addresses are calculated on-the-fly dunng the decode stage To avoid a clock cycle penalty for a cache fetch when a branch is predicted taken, a branch target cache withm branch logic 22 supplies the first 16 bytes at that address directly to the instruction buffer (assummg a hit occurs in the branch target cache) In one embodiment, branch prediction logic 22 achieves branch prediction rates of over 95% Branch logic 22 may also include special circuitry designed to optimize the CALL and RET instructions This circuitry allows the address of the next mstruction followmg the CALL instruction m memory to be pushed onto a return address stack When microprocessor 10 encounters a RET instruction, branch logic 22 pops this address from the return stack and begins fetchmg Like mstruction cache 14, data cache 26 may also be organized as two-way set associative 32-Kbyte storage In one embodiment, data TLB 28 includes 128 entries that may be used to translate lmear to physical addresses Like mstruction cache 14, data cache 26 may also be sectored Data cache 26 may further implement a MESI (modified-exclusive-shared-inva d) protocol to track cache line status Other configurations of data cache 26 are also possible and are contemplated Computational Core Turning now to Fig. 4, more detail of one embodiment of computation core 42 is shown. In one embodiment, computation core 42 comprises three execution units 36C-E and a multiplier 50. Integer/MMX/3D execution unit 36C is a fixed point execution unit which is configured to operate on all ALU operations, as well as multiplies, divides (both signed and unsigned), shifts, and rotates. In contrast, integer/MMX/ 3D execution unit 36E (Integer Y unit) is a fixed point execution unit configured to operate only on the basic word and doubleword ALU operations (ADD, AND, CMP, etc.). Execution units 36C and 36D are also configured to accelerate performance of software written using multimedia and 3D graphics instructions. Applications that can take advantage of multimedia and 3D graphics instructions include 3D modeling and rendering, video and audio compression/decompression, speech recognition, and telephony. Execution units 36C and 36D may be configured to execute multimedia instructions in a single clock cycle. Many of these instructions are designed to perform the same operation to multiple sets of data at once (i.e., vector processing). In one embodiment, execution units 36C and 36D use registers which are mapped onto the stack of floating point unit 36E. Execution unit 36E contains an IEEE 754-compatible floating point unit designed to accelerate the performance of software which utilizes the x86 instruction set. Floating point software is typically written to manipulate numbers that are either very large or small, require a great deal of precision, or result from complex mathematical operations such as transcendentals. Floating point execution unit 36E may comprise an adder unit, a multiply unit, and a divide/square root unit. In one embodiment, these low-latency units are configured to execute floating point instructions in as few as two clock cycles. In one embodiment, execution units 36C and 36D are coupled to multiplier 50 and are configured to utilize multiplier 50 as a shared resource. Advantageously, this configuration allows both execution units 36C and 36D to perform multiplication without requiring two multipliers. In another configuration, each execution unit 36C and 36D may each have their own dedicated multiplier. Still other configurations are possible and contemplated. For example, two n-bit multipliers may be shared by execution units 36C and 36D. Configuring microprocessor 10 with two multipliers each having a width of 32-bits advantageously allows two single precision multiplications to be executed in parallel (each operand/significand is 24 bits wide), or one MMX packed multiply (i.e., multiplying a pair of vectors wherein each vector comprises four 16-bit components). In another embodiment, multiplier 50 may be configured to accept operands that are 76-bits wide (i.e., the width of the significand in a double precision floating point data type), thereby providing the same functionality as two separate 32-bit multipliers while further alleviating the need for a separate multiplier in floating point unit 36E. In such an embodiment, execution units 36C-36E may be directly coupled to multiplier 50, with each execution unit sharing multiplier 50. Multiplier 50 may also be configured to perform both signed and unsigned multiplication. Advantageously, this allows multiplier 50 to support both integer multiplication for MMX instructions, and floating point multiplication for 3D graphics instructions. While multiplier 50 may be configured to perform multiplication using a number of different algorithms, the embodiment shown in the figure is configured to use a modified version of Booth's Algorithm to improve multiplication times. Booth's algorithm relies upon calculating a number of partial products and then summing them to obtam a final product Booth's algonthm is able to improve multiplication times over the standard "add- and-shift" algorithm by reducmg the number of partial products that need to be summed m order to obtam the final product For example, m performing an 8-bit by 8-bit multiplication, the shift-and-add algonthm generates eight partial products By contrast, same 8-bit by 8-bit multiplication usmg the 2-bit version of Booth's algonthm generates only five partial products This reduction m the number of partial products is illustrated m Figs 5 A and 5B Turning now to Fig 6, more detail of one embodiment of multiplier 50 is shown In this embodiment, multiplier 50 compπses a partial product generator 60, a partial product selection logic unit 62, and an adder 64 As shown m the figure, partial product generator 60 is coupled to selection logic unit 62, which is m turn coupled to adder 64 When one of execution units 36C-36E receives an mstruction mvokmg the multiplication function, the execution unit conveys two operands to multiplier 50, I e , a multiplicand operand 72 and a multiplier operand 74 Partial product generator 60 is coupled to receive multiplicand operand 72, which is used as a starting value for calculating a plurality of partial products 70 For example, if partial product generator 60 is configured to use the 2-bit version of Booth's algorithm, the following partial products would be generated the multiplicand itself ("+M"), a shifted version of the multiplicand ("+2M"), an inverted version of the multiplicand ("-M"), a shifted and inverted version of the multiplicand ("-2M"), and two constants, l e , a positive zero ("+0") and a negative zero ("-0") m two's complement form Partial product selection unit 62 is coupled to receive multiplier operand 74 Selection unit 62 is configured to select a number of partial products from generator 60 based upon particular fields withm multiplier operand 74 For example, using the 2-bit version of Booth's algonthm, multiplier operand 74 is padded with leadmg and trailing zeros (assuming an unsigned multiplication is bemg performed), and then one partial product is selected by each 3-bit field withm the operand Finally, adder 64 is configured to receive and sum the partial products selected by selection unit 62 As noted in the figure, the selected partial products 68 are shifted before they are summed The resultmg final product 76 is output to the execution unit that transmitted the operands As previously noted, multiplier 50 may advantageously be configured to perform both signed and unsigned multiplication This is descnbed m greater detail below Scalar Unsigned Multiplication Turning now to Fig 7, details of one embodiment of multiplier 50 are shown The figure also illustrates the operation of multiplier 50 for an unsigned multiplication While the figure shows an 8-bit by 8-bit multiplier usmg the 2-bit version of Booth's algorithm, other configurations are possible and contemplated, e g , a 32-bit by 32-bit multiplier usmg a 3-bit version of Booth's algorithm In this embodiment, multiplier 50 further compnses a "sign-m" mput 78, which indicates whether a signed or unsigned multiplication is to be performed Sign-m mput 78 is coupled to AND gate 86A, which also receives the most significant bit ("MSB") of multiplier operand 74 AND gate 86A outputs an "effective sign" bit 90 for multiplier operand 74 which is copied and appended to multiplier operand 74 for use by selection logic unit 62 Sign-m mput 78 is also routed to AND gate 88B, which similarly calculates and appends an effective sign bit 92 for multiplicand operand 72 While other effective sign calculation logic may be used, the configuration illustrated advantageously generates an effective sign of zero for all unsigned operands and positive signed operands usmg a minimum amount of logic Furthermore, in the embodiment shown only signed negative operands receive an asserted effective sign bit Partial product generation logic 60 uses multiplicand operand 72 and effective sign bit 92 to generate a number of partial products 80A-80C For example, a shifted version 80A of multiplicand operand 72 is generated by shiftmg logic 84B Shifted version 80A is equivalent to two times the multiplicand operand (+2M) Smularly, mverters 98 generate an inverted (l e , one's complement) version (-M) of multiplicand operand 72 Shifting logic 84A is used to generate a shifted and inverted version 80C (-2M) of multiplicand operand 72 Partial product generation logic 60 also generates constants for use as partial products, e g , positive zero 82B (+0) and negative zero 82A (-0) As illustrated in the figure, each partial product 80A, 80B, 80C, 72, 82A, and 82B may have an extra constant bit 88 associated with it Extra constant bit 88 is asserted only for negative partial products, l e , - M, -2M, and -0 and is added to the partial product withm adder 64 to generate two's complement versions of the inverted partial products The shaded areas of the figure denote constants that may be designed mto multiplier 50 Once partial product generator 60 has generated the partial products, selection logic 62 is configured to select partial products based upon 3-bit fields from multiplier operand 74 Multiplier operand 74 is padded with zeros and copies of effective sign bit 90 so that there are no fractional 3-bit fields Selection logic 62 may compπse a number of multiplexers 94A-94F, one for each partial product to be selected Each multiplexer 94A- 94E is controlled by a different 3 -bit field from multiplier operand 74 The 3 -bit fields determine which partial product from those generated by partial product generator 60, I e , +M, +2M, -M, -2M, +0, -0, will be selected The selected partial products are then conveyed to adder 64 Using 2-bit Booth decodmg, Table 1 describes how partial products will be selected Table 1 Adder 64 is configured to receive and sum the selected partial products As illustrated m the figure, the partial products are shifted before being summed Some of the partial products may have prefix bits added to eliminate the need for sign extendmg the partial product's most significant bit (I e , sign bit) to the maximum width of final product 76 The prefixes may be generated using simple inverters coupled to the partial product's most significant bit and constants Once the partial products are shifted, padded, and summed, final product 76 is output and com eyed to the execution unit that provided the operands Adder 64 may use a number of different algorithms for summing the partial products For example, adder 64 may configured as a carry look-ahead adder, a carry skip adder, a carry select adder, a carry-save adder, or a carry propagate adder The exemplary values m the figure illustrate the unsigned multiplication of two values, 240 10 and 230 10 Sign-m mput 78 is unasserted because unsigned multiplication to be performed Sign-m mput 78 may be provided by the same execution unit that provided the operands The execution unit may generate sign-in mput bit 78 based upon the type of multiply mstruction it received In the example shown m the figure, effective signs 90 and 92 are both zero because sign-m mput 78 is unasserted As shown m the illustration, an 8-bit by 8-bit version of multiplier 50 is able to multiply 8-bit unsigned operands (l e , operands that do not have a sign bit) havmg values from 0 to 255 to obtam a 16-bit unsigned result Scalar Signed Multiplication Turning now to Fig 8, the same 8-bit by 8-bit version of multiplier 50 is shown In this figure, however, multiplier 50 is performing signed multiplication Sign-m input 78 is asserted because signed multiplication is to be performed In the example illustrated, multiplicand operand 72 equals 100, 0 , while multiplier operand 74 equals -50, 0 Multiplier operand 74 is received m two's complement format because it is a negative signed value Thus its effective sign bit 90 (as calculated by AND gate 88 A) is asserted In contrast, effective sign bit 92 for multiplicand operand 72 is unasserted because multiplicand operand 72 is positive The final product 76 is a negative 16-bit number (-5000 10 ) represented in two's complement format with the MSB indicating the sign Turning now to Fig 9, another example of multiplier 50 performing a signed multiplication is shown In this example, however, both multiplier operand 74 (havmg a value of -50 10 ) and multiplicand operand 72 (havmg a value of -100 10 ) are received m two's complement format The multiplication results m a signed final product 76 (havmg a value of 5000 10 ) that is positive As Figs 6-8 illustrate, multiplier 50 may advantageously perform both signed and unsigned multiplication with the same hardware Furthermore, multiplier 50 may advantageously be configured to use Booth's algorithm to further mcrease multiplication performance Component-wise Vector Multiplication As previously noted, recent advances have placed a greater emphasis on microprocessors' multimedia and graphics performance Multimedia and 3D extensions to the basic x86 mstruction set mclude vectored multiply instructions to improve performance Turning now to Fig 10, an embodiment of multiplier 50 capable of performing vector multiplication is shown As m previous embodiments, multiplier 50 compnses partial product generator 60, selection logic 62, and adder 64 This embodiment of multiplier 50 is configured to perform component- wise vector multiplication of two pairs of N-bit values (AlxBl and A2xB2) simultaneously or a scalar multiplication of one pair of 2N-bιt values (AxB) Advantageously, multiplier 50 may take the place of three separate multipliers (I e , one for scalar multiplication and two for the vector multiplication), thereby saving valuable die space In this embodiment, multiplier 50 has several features which allow it to perform both scalar and component-wise vector multiplication When scalar multiplication is performed, multiplier 50 functions as previously disclosed, l e , adder 64 will sum the partial products selected by selection logic 62 from partial product generator 60 to form final product 76 When performing component-wise vector multiplication, however, multiplier 50 is configured to effectively operate as two separate multipliers This behavior ensures that the results generated by multiplier 50 will equal the results that would have been generated had two separate multipliers been used To mdicate whether multiplier 50 should perform component-wise vector multiplication or scalar multiplication, multiplier 50 receives a vector in mput signal 120 When an asserted vector in signal is received, a plurality of multiplexers within selection logic 62 (e g , multiplexers 122 and 124) effectively isolate the two "logical halves" of multiplier 50 This separation prevents partial products from one pan of vector components (e g , Al and Bl) from interfering with the multiplication of another pan- of vector components (e g , A2 and B2) The operation of multiplexers 122 and 124 is descnbed m greater detail below As shown m the figure, multiplicand operand 72 and multiplier operand 74 may each compπse a vector (two N-bit values) or a scalar value (a smgle 2N-bιt value) For example, multiplicand operand 72 may compnse a vector (A2, Al) or a smgle scalar value A The partial products selected by selection logic 62 may be logically divided into four quadrants 130-136 for component-wise vector multiplications (assummg vector operands each havmg two vector components) Quadrant 130 represents the higher order bits of partial products selected by the least significant vector component of vector multiplier 74 (l e , Bl) Quadrant 132 represents the lower order bits of partial products selected by the least significant vector component of vector multiplier 74 (l e , B 1 ) Quadrant 134 represents the lower order bits of partial products selected by the most significant vector component of vector multiplier 74 (l e , B2) Quadrant 136 represents the higher order bits of partial products selected by the most significant vector component of vector multiplier 74 (l e , B2) As the selected partial products are shifted before being summed m adder 64, the least significant bits of partial products selected by vector component B2 located withm quadrant 134 may affect the addition performed to generate A 1 xB 1 withm final product 76 To prevent this "corruption" of final product 76, multiplexer 124 is configured to "zero-out" the lower order bits of partial products located within quadrant 134 Smularly, m some embodiments the higher order bits of partial products selected by vector component Bl may extend mto quadrant 130, thereby possibly affecting the summation used to form BlxB2 within final product 76 Thus additional multiplexers similar to multiplexer 124 may be used to zero-out the higher order bits within quadrant 130 Multiplexer 122 also assists m the logical separation that is advantageous for component- wise vector multiplication Staggered bit fields within multiplier operand 74 are used to select partial products from partial product generator 60 When a bit field encompasses bits from more than one vector component within multiplier operand 74, the resulting partial product may also be "corrupted " For example, selecting a partial product usmg one bit from vector component Bl and two bits from vector component B2 (as illustrated in the figure) will result m a partial product that is partially representative of vector component Bl and partially representative of vector component B2 This is undesirable because Bl is to be multiplied with Al separately from B2 To remedy this, a multiplexer 122 may be used When a bit field encompasses bits from more than one vector component, multiplexer 122 may zero-out the unwanted bit or bits (e g , the most significant bit from Bl as shown m the figure) Thus, the partial product selected by multiplexer 94B will reflect only the bit values withm the desired vector component A second multiplexer similar to multiplexer 122 may zero out the opposite bits Thus two partial products may be selected, one representmg the end of vector operand Bl and one representing the beginning of vector operand B2 The zeromg-out of bits for partial product selection and summation are illustrated m more detail by way of a numeπcal example in Figs 11 A through 12 Turning now to Fig 11 A, more detail of one embodiment of partial product generator 60 is shown To support component-wise vector multiplication when the vector components are signed, an additional effective sign bit 172A-172F may be generated for the lower-order portion of each partial product The same logic may be used as previously disclosed, with AND-gate 86B being duplicated (see AND-gate 86C) to generate an effective sign for each lower-order vector component Advantageously, multiplier 50 may be configured to perform both signed and unsigned vector multiplication Generator 60 may also be configured to generate separate constant bits 88A-F (referred to as SI) and 170A-F (refened to as S2) to further improve separability when the selected partial products are summed m adder 64 The extra constant bits 170A-F and effective sign bits 172A-F may simply remam unused or unselected durmg scalar multiplication Note the figure illustrates one possible set of partial products generated for an unsigned component- wise vector multiplication wherem the multiplicand operand 72 has the values of (6,7), l e , A2=6 and A 1=7 Sign in mput 78 is unasserted to indicate that an unsigned multiplication is being performed Turning now to Fig 1 IB, detail of part of one embodiment of selection logic 62 is shown In order to support both scalar and vector multiplication, selection logic 62 may comprise a plurality of multiplexers 310A- B, 312A-B, 314A-B, and 316A-B These multiplexers operate to select particular bits from partial product generator 60 accordmg to the status of vector in signal 120 Each partial product has its own set of selection multiplexers (excludmg constants +0 and -0 which are simply fed through as is, see 320A and 320B) For example, multiplexer 310A selects bits [9-0] from the partial product -2M and outputs them to the rest of selection logic 62 and adder 64 if vector_m is asserted This may ensure that both effective sign bits 92A and 172 A are conveyed to adder 64 Two effective sign bits are needed because two separate multiplications are bemg performed Conversely, if vector n is unasserted (indicating a scalar multiplication), extra effective sign bit 172 A is not needed, thus multiplexer 310A selects bits [9-6, 4-0] and outputs them as bits [0-8] The extra effective sign bit 172 A is removed, and a constant zero is padded to the output to create bit [9] As mdicated m the figure, bit [SI] may be passed through as it is needed in both cases (scalar and component- ise vector multiplication) Multiplexer 310B selects bit [S2] if vector in signal 10 is asserted, thereby providmg two constants 88A and 170A If vectorjn signal 120 is not asserted and scalar multiplication is bemg performed, bit [S2] is not needed (and may cause an inconect result if it is passed through to adder 64) Thus, multiplexer 310B is configured to select and convey a constant zero m place of actual S2 bit 170A if scalar multiplication is performed Multiplexers 312A-B, 314A-B, and 316A-B operate m a similar fashion Each multiplexer may be configured to select the required bits from partial product generator 60 without passmg extra bits unless they are needed Turning now to Fig 12A-B, more details of one embodiment of selection logic 62 and adder 64 are shown In this embodiment, selection logic 62 comprises a plurality of multiplexers 94A-94F as m the previous embodiments Note that multiplexers 312A-B, 314A-B, and 316A-B are not shown, but are mstead mcluded withm partial product generator 60 Selection logic 62 further comprises multiplexers 152-156, which operate to select two portions of partial products (1) a portion of the partial product conespondmg to the higher order bits of vector operand Bl, and (2) a portion of the partial product conespondmg to the lower order bits of vector operand B2 Multiplexer 156 then selects this "combination" partial product when vector m signal 120 is asserted Advantageously, this configuration may remedy the problem of summation corruption when a bit field encompassmg bits from more than one vector operand is used to select a partial product This problem is described in greater detail below (see Figs 13 and 14) In this embodiment, adder 64 compnses three pluralities of multiplexers 160A-160D, 162A-162E, and 164C-164E Multiplexers 160A-160D are controlled by vector m signal 120 and operate to "zero-out" portions of the partial products to prevent corruption of the vector components withm final product 76 durmg the summation withm adder 64 Multiplexers 164C-E are also controlled by vector in signal 120 and operate to select either extra constant bits 140C- 140E (in the event of a vector multiplication) or a zero constant (m the event of a scalar multiplication) for addition mto the more significant product Multiplexers 162A-162D are controlled by sιgn_ιn mput 78 and are configured to select either the effective sign bit of the more significant portion of the selected partial product (in the event of a signed vector multiplication) or the actual sign (m the event of an unsigned vector multiplication) Multiplexers 164C-164E are also controlled by vector m signal 102 and perform the same function as multiplexers 310B, 312B, 314B, and 316B, I e , they select a constant zero mstead of extra constant bit S2 if scalar multiplication is performed Note that other configurations of logic for zeroing out and partial product selection are possible and contemplated Further note that multiplexers 160A- 160D, 162A-162E, and 164C-164E may be configured as part of adder 64, selection logic unit 62 or as a separate part of multiplier 50 In addition to the features disclosed above, adder 64 may further comprise a plurality of multiplexers (not shown) to prevent cames across the boundaries of vector operands withm final product 76 when summing the selected partial products This boundary is represented by a dashed lme 178 m the figure Other embodiments of multiplier 50 may utilize different configurations of multiplexers For example, multiplexers 160A-160C may be configured to select either additional sign-extension bits or the most significant bits of the selected partial products In addition, multiplexers 160A- 160C may be configured to pad each selected partial product with prefix bits until the most significant bit of each selected product conesponds to the most significant bit of final product 76 (as indicated by dashed bit positions 170A- 170B) The prefix bits may compπse a constant, sign extension bits, or a combination thereof Note that Figs 11A-B and 12 together illustrate the exemplary component-wise multiplication of two vector operands, l e , multiplier operand 74 havmg a value of (3,12), 1 e , B2=3 and Bl=12, and multiplicand operand 72 havmg a value of (6,7), l e , A2=6, and Al=7, resulting in final product 76 havmg a value of (18,84) Further note that while the figures and exemplary embodiments have illustrated a multiplier configured to perform component-wise vector multiplication on vector operands having up to two vector components, other configurations are possible and contemplated, e g vectors havmg four or six vector components may be multiplied component- wise m parallel Furthermore, a number of multipliers configured smularly to multiplier 50 may be used m parallel to achieve even higher performance The widths of multiplier operand 74 and multiplicand operand 72 may also be vaned, e g , 32-bιts or 64-bιts, as may the widths of their vector components In addition, other embodiments of multiplier 50 may be configured to return only a portion of final product 76 per clock cycle For example, the most significant vector component of final product 76 may be returned dunng a first clock cycle Other vector components may be returned durmg subsequent clock cycles in order of their significance Turning now to Fig 13, another embodiment of multiplier 50 is shown In this embodiment, multiplier 50 further compnses multiplexer 138 When vector_ιn signal 120 is asserted, component- wise vector multiplication is performed If the summing of partial products generates one or more carry bits 140, the upper vector component m final product 144 may be corrupted if carry bits 140 are allowed to propagate across boundary 176 To prevent this, multiplier 50 may comprise one or more carry multiplexers 138 to prevent carry bits from propagating to higher order vector components within final product 76 When multiplier 50 is performing scalar multiplication, multiplexers 138 may be configured to propagate carry bits normally As shown m the figure, m this embodiment of multiplier 50 the partial products m quadrant 130 are zeroed out such that they will not affect the value of final product 144 Turning now to Fig 14, another embodiment of multiplier 50 is shown In this embodiment, the partial products m quadrant 130 are not zeroed out Instead, the selected partial products in quadrant 132 are allowed to sign extend across quadrant 130 In some mstances, e g , when vector components Al and Bl have opposite signs, final product 76 will have a lower order vector component 142 that will be negative and may result m a sign extensions across quadrant 130 This sign extension may affect the value of the more significant vector component 144 withm final product 76 Multiplexer 146 is configured to insert a constant to be summed with the selected partial products to form final product vector component 144 The constant (e g , a binary value of one) is calculated to compensate for a negative sign extension across final product 144 For example, a negative sign extension may be equivalent to "11111111," thus adding a constant of one (l e , "00000001 ") will negate the effect of the sign extension on result vector component 144 As this sign extension occurs only when vector components Al and Bl have different signs, an XOR-gate 148 may be used m conjunction with vector in mput 120 to control multiplexer 146 so that the constant is only added when final product 142 will be negative and a component-wise vector multiplication is being performed As illustrated, XOR-gate 148 may receive the sign bits (l e , the most significant bits) of vector components Al and Bl as inputs Vector Dot Product Multiplier 50 may also be configured to calculate the "vector dot product" or inner product of two vectors The followmg example illustrates the calculation of a vector dot product Assuming vector A equals (xl, x2, x3), and vector B equals (yl, y2, y3), then the vector dot product A • B equals xlyl + x2y2 + x3y3 As this example illustrates, calculation of the dot product entails performing a component-wise vector multiplication and then summing the vector component products Turning now to Fig 15, one embodiment of multiplier 50 configured to calculate the vector dot product is shown As shown m the figure, partial products 190 are summed withm adder 64 to form vector component products 192A-N Each vector component product 192A-N conesponds to one vector pan- withm multiplicand operand 72 and multiplier operand 74 as previously disclosed Vector component products 192A-N are then summed usmg a plurality of carry-propagate adders 194A-N to form final result 196, which may then be output for use by other parts of microprocessor 10 Turning now to Fig 16, another embodiment of multiplier 50 configured to calculate the vector dot product is shown In this embodiment, however, partial products 190 summed by adder 64 are kept m redundant form, l e , each vector component product 192A-F is represented by more than one value For example, each vector component product 192A-F may be represented by two values, a sum value 198A-F and a carry value 200A-F A set of carry-save adders (not shown) may be used withm adder 64 to sum partial products 192 m redundant form Advantageously, carry-save adders may significantly reduce the amount of time and die space required to sum partial products 192 At the single-bit level, a carry-save adder will take three bits of the same significance and produce a sum value (havmg the same significance) and a carry value (havmg a significance one bit higher than the sum value) In contrast, the term "carry-propagate adder" denotes an adder that is not a carry- save adder In one embodiment, a carry-save adder may be implemented as a number of mdependent full adders Once vector component products 192A-192F have been formed, they may be summed together usmg a second set of carry-save adders 202A-J When the number of values remaining to be summed is reduced to two, a carry-propagate adder 204 may be used to perform the final summation Note, however, that this configuration may require further modification if multiplier 50 is configured to propagate sign extension and carry bits as illustrated in Fig 14 The embodiment of multiplier 50 illustrated m Fig 14 relies upon cames from less significant products propagatmg mto the more significant ones In this case, summing partial products 190 and products 192A-F usmg carry-save adders may cause final result 196 to be less than the conect result by one unit- ln-the-last-place (ULP) for each product below the most significant product This is because cames from lower products are not incorporated into upper products durmg carry-save adds To ensure that final result 196 is conect when multiplier 50 is configured in a manner similar to the embodiment of Fig 14, carry-propagate adder 204 may be configured to accept summands havmg a width equal to the cumulati . e width of all products 192A-F Assummg the length of each operand (multiplier and multiplicand) is n bits wide and comprises p vector components, each product 192A-F will have a width of 2nlp Thus to accommodate all products 192A-192F, adder 204 may be 2« bits wide or wider The redundant forms of each product 192-192F (e g , sum values 198A-F and cany values 200A-F) are conveyed as mputs to adder 204 (excludmg the most significant product 192F) In place of the most significant product 192F, the final two summands remaining from the carry-save summation of products 192A-192F are mput to adder 204 as the most significant mputs While adder 204 will output a 2«-bιt wide result, only the most significant 2nlp bits comprise the final result 196 This configuration advantageously allows adder 204 to propagate carry bits from lower order products to higher order products, thereby ensuring a proper result while still retaining the advantages associated with carry-save addition Furthermore, the cost in die space of having a 2«-bιt wide carry-propagate adder such as adder 204 may be reduced if other functions to performed by multiplier 50 also require a wide carry-propagate adder As with previous embodiments, this embodiment of multiplier 50 may be configured to accept operands havmg varying widths («), and varying numbers of vector components (p) For example, multiplier 50 may be configured to calculate the dot product of two vector operands, each 64-bιts wide and each having four vector components Rounded Products As previously noted, some embodiments of multiplier 50 may be configured to conserve hardware resources (e g , signal lmes and registers) by returning only a portion of the final product (or products, m the case of component- wise vector multiplication) per clock cycle For example, the higher order bits of the final product may be returned first, and then the lower order bits may be returned m subsequent clock cycles However, m some embodiments it may be advantageous to return the higher order bits rounded to the nearest unit m the last place ("ULP") Turning now to Fig 17, a diagram of another embodiment of multiplier 50 is shown This embodiment is configured to round the higher order bits of each vector component product to the nearest ULP As m the previous embodiment (illustrated m Fig 16), partial products 190 are reduced in redundant form (e g., a sum value and a carry value for each pans of vector components) by adder 64 However, m this embodiment a plurality of adders 210A-210F are used to add a roundmg constant 214 to each vector component product Roundmg constant 214 may compnse a smgle asserted bit (i.e , a "one-hot") added to the bit position below the least significant bit position m the portion of the vector component to be rounded For example, assummg a vector component product has a width of 8 bits, and the four most significant bits (MSBs) are to be rounded, then a constant one would be added to the fourth bit (as illustrated m Table 2) By adding a constant one m the appropriate bit position, the upper portion of the vector component product may be rounded efficiently and without large amounts of additional logic Table 2 As shown m Fig 17, each adder 210A-210F is configured to receive the redundant form of a smgle vector component product For example, adder 210A is configured to receive sum value 198 A and carry value 200A and combine them with roundmg constant 214 Adder 210A combmes these three values and generates a redundant form output comprising a new sum value and a new carry value Advantageously, adders 210A-210F may be configured as independent carry-save adders, thereby preventing carry-bits caused by roundmg constant 214 from propagating to more significant vector component products The outputs of each adder 21 OA-21 OF are coupled to the inputs of one of a plurality of carry-propagate adders 212A-212F Each carry-propagate adder 212A-212F is configured to sum the outputs of adders 21 OA-21 OF and thereby generate a non-redundant form of each vector component product The rounded MSBs of each vector product may be output first, while the remaining least significant bits ("LSBs") may be output during a subsequent clock cycle Adders 212A-212F may be configured mdependently to avoid the possibility of an unwanted carry-bit propagating across vector product boundaries In another embodiment, additional adders (not shown) may be configured to generate the LSBs (which are unrounded) separately from the MSBs Advantageously, this may prevent the roundmg process from altering the value of the LSBs For example, adder 212A may be configured to generate the rounded MSBs by summing the sum and carry values generated by adder 210A, while an additional adder may be configured to sum the lower bits of sum value 198A and carry value 200A to generate the LSBs In the previously described embodiments, each adder 210A-210F and 212A-212F is configured to perform addition without propagating carry bits from one vector component product to another While this may be desn able m many configurations, the non-propagation of carry bits may disrupt some configurations of adder 50 For example, the embodiment illustrated m Fig 14 relies upon the propagation of sign extension bits across vector component product boundaries If carry bits are not allowed to propagate durmg the final addition stages which convert the redundant- from vector component products to non-redundant-form, the higher order products may be incoπect Turning now to Fig 18, an embodiment of multiplier 50 which rounds the higher order bits of each vector component product, yet still allows carry bits to propagate across consecutive vector component product boundanes, is shown In this embodiment, roundmg constant 214 is once agam added to the redundant form sum values 198A-198F and carry values 200A-200F of each vector component product by carry-save adders 210A- 21 OF In order to allow cames from partial products 190 to propagate without allowing cames from roundmg constant 214 to propagate, separate carry-propagate adders 212A-212F are used for each vector component product The length of each adder 212 A-212F may equal the number of bits m the vector component product itself plus all of the bits conespondmg to less significant vector component products For example, assummg each vector component product is eight bits wide, adder 212B may be 16 bits wide and may add redundant vector component values 198A-198C and 200A-200C Advantageously, undesired carry-out bits from each vector component product will not affect higher order vector component products m this configuration Furthermore, the carry bits that may be required for conect operation of the embodiment of multiplier 50 illustrated m Fig 14 still propagate to form the conect result despite possible sign-extensions Note that other configurations of multiplier 50 are possible For example, roundmg constant 214 may be incorporated withm the logic of adder 64, thereby potentially eliminating the need for an extra level of adders Furthermore, multiplier 50 may be configured to round and return the upper portions of scalar products and vector dot products m addition to vector component products The types of adders used may also be changed according to the implementation, e g , carry-propagate adders may be used through out in conjunction with multiplexers configured to prevent carry bits from propagatmg across vector component product boundaries In addition, various control signals, e g , a round in signal, may be used to indicate whether roundmg is to be performed Fast Rounding and Normalization Another possible area for improving the speed of multiplication relates to roundmg and normalization When performing floatmg pomt multiplication, the multiplier and multiplicand operands (l e , the sigmficands of two floatmg pomt numbers) are received m normalized form A binary number is said to be normalized when the most significant asserted bit is directly to the left of the binary radix point For example, 1 010011 2 is normalized, while 10 10011 2 and 0 01010011 2 are not In order to normalize a binary number, the number is shifted either right or left until the most significant asserted bit is dnectly to the left of the binary radix pomt The number's exponent is then mcreased or decreased an amount equal to the number of positions that the number was shifted When multiplier 50 performs floatmg pomt multiplication, it receives two normalized sigmficands In some embodiments, multiplier 64 may be configured to output the results m normalized form For example, multiplier 50 may receive two 32-bit normalized sigmficands as operands and be configured to output one 32-bit result m normalized form After multiplier 50 generates and selects the partial products, they are summed by adder 64 to create the final result As the final result may be in redundant form, it may be passed through a carry- propagate adder as previously descnbed Once m non-redundant form, the result is rounded and normalized before bemg output Different methods of roundmg are possible For example, IEEE Standard 754 defines four different roundmg methods round to nearest (even), round to positive infinity, round to minus infinity, and round to zero The round to nearest method is particularly useful because it ensures that the enor m the final product is at most one-half ULP (unit m the last place) Turning now to Fig 19, another embodiment of multiplier 50 is shown This embodiment compnses two "paths" which are configured to perform IEEE roundmg and normalization by calculating two results m parallel, l e , one result assuming there is an overflow and one result assume no overflow This embodiment comprises a pair of carry-save adders 276A-B, a pan of carry-propagate adders 278A-B, a pair of sticky bit logic units 286A-B, and a pan of LSB fix-up logic units 288A-B The "no-overflow path" comprises carry-save adder 276A, carry-propagate adder 278A, sticky bit logic unit 286A, and LSB fix-up logic unit 288A, while the "overflow path" comprises carry-save adder 276B, carry-propagate adder 278B, sticky bit logic unit 286B, and LSB fix-up logic unit 288B Both carry-save adders 276A and 276B are configured to receive sum value 274A and carry value 274B from partial product anay adder 64 Each carry-save adder 276A and 276B is also configured to receive a roundmg constant 268 from multiplexer 266 Multiplexer 266 is configured to select roundmg constant 268 from one of four roundmg constants The first roundmg constant is a hard-wired constant one and is selected when roundmg mode input 270 mdicates that round to nearest (even) is the selected roundmg mode The constant is added to the guard bit position by both carry save adders 276A and 276B Ηie second rounding constant is a hard-wired zero and is selected when roundmg mode mput 270 mdicates that round to zero (truncate) is the selected roundmg mode The third roundmg constant is the sign of the final product of the multiplication being performed This sign may be obtamed by exclusively ORing the sign bit 260A of multiplicand operand 72 and the sign bit 260B of multiplier operand 74 withm XOR gate 262 The resultmg sign bit is added to the guard bit position, and each bit position less significant than the guard bit position, by carry-save adders 276A and 276B The fourth roundmg constant is the inversion of the third rounding constant It may obtained by inverting the rounding constant obtamed from XOR gate 262 with inverter 264 The resultmg inverted sign bit is added to the guard bit position and each bit position less significant than the guard bit position by carry-save adders 276A and 276B Carry-save adders 276A and 276B are configured to receive and add sum value 274A, carry value 274B, and the selected roundmg constant from multiplexer 266 Carry-save adders 276A and 276B convey then- results in redundant form to carry-propagate adders 278A and 278B, respectively Carry-propagate adders 278A and 278B reduce the results to non-redundant form 282A and 282B and convey them to LSB fix-up logic units 288A and 288B, respectively In parallel with the addition performed by adders 276A-B and 278A-B, sticky bit logic umts 280A-B calculate sticky bits 286A-B Sticky bit logic units 280A-B each receive sum value 274A and carry value 274B as mputs The calculation of sticky bits and the operation of sticky bit logic units 280A-B are descnbed m greater detail below LSB fix-up logic units 288A and 288B are coupled to carry-propagate adders 278A-B and sticky bit logic units 280A-B Fix-up logic units 288A-B are configured to conditionally invert the least significant bit of the non-redundant results received from adders 278A-B. In one embodiment, fix-up logic units 288A-B are configured to perform the inversion or "fix-up" when the "round to nearest" mode is bemg performed and the following equation is true (mverse of L) (G) (inverse of S) = 1, wherem L and G are the least significant bits (LSBs) and guard bits, respectively, of the sum of sum value 274A and carry value 274B, and wherem S is the conespondmg sticky bit (either 286A or 286B) Note that L and G may be calculated withm fix-up units 288A-B usmg sum value 274A and carry value 274 The calculation of L and G may be performed m parallel with the additions performed by adders 276A-B and 278A-B and need not mclude a roundmg constant L and G may be calculated withm fix-up units 288A-B, or by usmg an extra component withm multiplier 50 (e.g , a third pan of carry-save/carry-propagate adders) The fix-up may advantageously compensate for cases m which adders 276A- B have added a constant when a constant was not actually needed (e g , result+1 is generated when result+0 is needed) Next, the desired number of upper bits from the outputs of LSB fix-up logic units 288A and 288B may be conveyed to multiplexer 290, which selects one of the two values (overflow or no overflow) as output 292 Multiplexer 290 may be controlled by MSB 284 from the output of fix-up logic unit 288A By lookmg at the most significant bit, a determmation of whether an overflow occuned can be made If an overflow occuned, the upper bits from the output of LSB fix-up logic unit 288A are selected If an overflow did not occur, the upper bits from the output of LSB fix-up logic unit 288B are selected Note that other control configurations are also possible, e g , MSB 284 may be the most significant bit of the output from fix-up logic unit 288B Furthermore, m some embodiments of multiplier 50 only one fix-up logic unit may be needed For example, the smgle fix-up logic unit may be coupled to the output of multiplexer 290 and perform the fix-up before final result 292 is output In one embodiment, exponent control logic unit 254 is also controlled by the same signal that controls multiplexer 290 If an overflow occurs, exponent control logic unit 254 is configured to mcrement the conespondmg exponent This completes the normalization of the output Advantageously, the embodiment of multiplier 50 depicted in the figure may be able to round and normalize the final result m less time because normalization is performed in parallel Furthermore, the fix-up is performed while multiplexer 290 is selectmg a result (overflow or no overflow) This may further reduce the cycle time of this embodiment of multiplier 50 Turning now to Fig 20, a diagram illustratmg the operation of one embodiment of carry-save adders 276A and 276B is shown The example assumes eight bit sum and carry values 274A-B are bemg rounded to four bit values and that round to nearest (even) is bemg performed Adders 276A-B each receive sum value 274A, carry value 274B, and roundmg constant 268 as mputs In the example shown, adder 276A is configured to add a constant one to the guard bit position of sum value 274A and constant value 274B assummg there will not be an overflow The guard bit position is the bit position that is one bit less significant than the least significant bit of the portion to be output An overflow occurs when the summation of sum value 274A, carry value 274B, and any added roundmg constants, creates a carry out from the bit position dnectly to the left of the binary radix point An overflow may requne the result to be shifted to the right (and the conespondmg exponent to be incremented) in order to produce a normalized output As the figure illustrates, adder 276A adds a constant one to the guard bit position of sum value 274A and carry value 274B assuming there will be no overflow. In contrast, adder 276B adds rounding constant 268 to the guard bit position of sum value 274A and carry value 274B assuming there is an overflow. Thus, adder 286B adds the constant one in a different bit position than adder 276A. For this reason, adders 276A and 276B each generate a different result. The results from adder 276A are conveyed to carry propagate adder 278A, which is configured to reduce them to non-redundant form. Similarly, the results from adder 276B are conveyed to carry propagate adder 278B, which operates in manner similar to adder 278A. Turning now to Fig. 21, more detail of one embodiment of sticky bit logic unit 280A is shown. As the figure illustrates, sticky bit logic 280A receives the lower four bits of the sum and carry values (350 and 352, respectively ) generated by adder 276A. A constant 354 (e.g., 1111) is added to the sum and carry bits within carry save adder 340A, thereby generating two different 4-bit outputs which are routed to exclusive NOR gate 342A. The output from exclusive NOR gate 342A is routed to 4-input OR gate 344A, which outputs sticky bit 286A. Sticky bit logic 280B is configured similarly to sticky bit logic 280A, but it may be configured to receive one extra bit, e.g., five bits as opposed to four bits, due to the assumed overflow. Turning now to Fig. 22, a numerical example of the operation of the embodiment of multiplier 50 from Fig. 20 is shown. This example assumes an eight bit output from adder 64 is being rounded to a four bit result. The figure shows each of the four IEEE rounding modes being performed by both carry-save adders 276A and 276B. The selected rounding constant 268 conesponds to the rounding mode. The selected rounding constant 268 is added to sum value 274A and carry value 274B by carry save adders 276A and 276B. As the figure illustrates, the starting bit position to which the constant is added varies from adder 276A to adder 276B. As previously noted, this is because adder 276A adds the constant to the guard bit position assuming there is no overflow, while adder 276B assumes there is an overflow. In parallel, sticky bit logic units 280A and 280B each calculate their own version of the sticky bit (286A and 286B, respectively), also reflecting whether or not an overflow is presumed to occur. Next, LSB fix-up logic units 288A and 288B fix-up (invert) the LSB of output 282A, if necessary. As the figure illustrates, the fix-up is only performed when round to nearest (even) is the selected rounding mode and the formula (inverse of LSB) ■ (Guard bit) • (inverse of Sticky Bit) = 1 is true. Note that in this embodiment the LSB and Guard bit are taken from the sum of sum value 274A and carry value 274B without selected rounding constant 268. After the fix-up, the upper four bits are output to multiplexer 290. In one embodiment, LSB fix-up logic 288 A and 288B may each comprise a single inverter configured to invert the least significant bit of results 282A and 282B, respectively. Other configurations of multiplier 50 are possible and contemplated. Turning now to Fig. 23, another embodiment of multiplier 50 configured to perform rounding and normalization is shown. In this embodiment, the "fix-up" or inversion of the LSB is performed by a single LSB fix-up logic unit 288 after multiplexer 290 performs the overflow/no overflow selection. A second multiplexer 290B is included to select which sticky bit 286A or 286B will be used by LSB fix-up logic unit 288 in determining whether to perform the inversion. Note the rounding and normalization hardware disclosed herein may be configured to round and normalize redundant results from other functional units also, e.g., adders. Fast Newton-Raphson Iteration to Calculate the Reciprocal (1/B) As microprocessor 10 already contams a highly optimized multiplier 50, it would be advantageous to perform other calculations on multiplier 50 as well, e g , division This may be accomplished by recastmg division operations mto reciprocal operations followed by multiplication operations For example, the operation "A divided by B" (A/B) may be recast mto "A multiplied by the reciprocal of B" (A x B ') Forming the reciprocal of B may also be recast mto a series of multiplication operations by usmg a version of the Newton- Raphson iteration The Newton-Raphson iteration uses the equation X, = X 0 x (2 - X 0 x B) to calculate the reciprocal of B The initial estimate, X„, may be determined m a number of different ways For example, X,, may be read from a ROM table usmg B as the mdex, wherem X 0 approximates 1/B In another embodiment, X„ may be calculated directly from B or from one or more ROM tables configured to output seed values The seed values may be manipulated, e g , using arithmetic and combinational logic, to determine X 0 Once XQ IS known, the first iteration may be performed Thereafter, the results from each iteration are used m place of X,, in subsequent iterations This forces X n+] to converge on 1/B in a quadratic fashion Turning now to Fig 24, a flowchart depictmg one embodiment of a method to calculate the reciprocal usmg multiplier 50 is shown As previously noted, X 0 is calculated first (step 700) Once X 0 is determined, it is multiplied by B (step 702) The results are then routed down two parallel paths 706 and 708, one that assumes an overflow took place m the multiplication (path 706), and another that assumes no overflow occuned (path 708) Because X 0 is close to 1/B, the product of X 0 and B will be close to one, 1 e , either slightly over one or slightly under one As a result, an overflow will only occur durmg the multiplication if X 0 is slightly greater than one (I e , of the form 10 000 with an exponent equal to 2 ') If there is no overflow, the result will be slightly less than one (l e , m the form 01 111 with an effective exponent equal to 2 ') After the multiplication, the term (2 - X 0 x B) is formed withm each path by inverting the (X Q x B) results Since (X 0 x B) is close to one, (2 - X 0 x B) may be approximated by the absolute value of the two's complement of (X 0 x B) To further speed the calculation, the one's complement may be used because it only differs by a one in the least significant digit The approximations for (2 - X 0 x B) are performed m parallel withm each path (steps 710 and 712) Specifically, in overflow path 706, the bits are inverted to get 01 111 (with an effective exponent equaling 2 ') In non-overflow path 708, the bits are inverted to get 10 000 (with an effective exponent equalmg 2 ') Note that the sign bit of each mtermediate value may also be forced to zero (positive) Next, either the overflow path result or the non-overflow path result is selected (step 714) This selection can be performed by examining the result from the path that assumes no overflow occuned If the most significant bit of this result is a one, then an overflow occuned withm the non-overflow path, and the result from the overflow path should be selected as the proper result The conespondmg sign and exponent bits are also selected along with the result Note that different bits may be selected from each path This is illustrated by the followmg example Assuming the product from the multiplier is 64 bits wide, then the bits may be numbered from 0 (the least significant bit) to 63 (the overflow bit), with the binary radix point located between the most significant bit 62 and the most significant fractional bit 61 If an overflow has occuned, bits 62 through 0 are selected with the radix pomt positioned between bits 62 and 61 If an overflow has not occuned, bits 63 though 0 are selected with the radix pomt positioned between bits 63 and 62 Thus bits 10 000 may be selected as 1 0000 (along with a hardwired exponent equalmg 2°) Advantageously, this configuration may save time by normalizmg the mverted bits without requiring a dedicated normalization step Note that other configurations and other widths are contemplated Furthermore, all the bits from the selected path need not be used In some embodiments fewer bits may be selected, and m other embodiments extra bits may be padded with constants to meet a desned length After the appropπate bits are selected, the result is routed back to the multiplier, which multiplies it with X 0 to complete the first iteration and form X, (step 716) If the desired accuracy has been achieved (step 718), the results are output (step 722) If the desired accuracy has not been achieved (step 720), the iteration is repeated to form X 2 , wherem X 2 = X, x (2 - X, x B) As with the first iteration, the term (X, x B) is close to one The results of the multiplication are once agam passed down paths 706 and 708 in parallel Dependmg upon the accuracy of the initial guess X 0 and the accuracy desned m the final result, the iteration may be performed any number of times (e g , one, two, or five times) Using two paths may advantageously eliminate the need for normalization because the exponent and sign bits can be hard-wned based upon the known limits of the incoming operands and whether or not an overflow occurs Fast Newton-Raphson Iteration to Calculate the Reciprocal Square Root (1/VB) In another embodiment, multiplier 50 may be configured to calculate the reciprocal square root of an operand B usmg a modified version of the Newton-Raphson iteration The equation Y n+1 = Y n x (3 - B x Y n 2 ) / 2 may be used to calculate the reciprocal square root of B Once agam, the initial estimate, Y 0 , may be determmed m a number of ways, e g , by usmg initial estimate generators that perform calculations on seed values read from ROM tables usmg B In this iteration Y 0 approximately equals 1/Λ/B Each subsequent iteration of the equation forces Y n+1 to converges on 1Λ.B m a quadratic fashion In one embodiment, both Y 0 and Y 0 2 may be produced usmg the same initial estimate generator that was used for the reciprocal calculation described above This may be desirable because determining Y 0 2 may eliminate the need for a multiplication operation to form Y 0 2 from Y 0 As used herem, an initial estimate generator refers to any hardware capable of generatmg an initial value such as Xo or Y 0 , e g , one or more ROM tables configured to output seed values that may be used to calculate the initial value usmg anthmetic and combmational logic Turning now to Fig 25, a flowchart depictmg one embodiment of a method to calculate the reciprocal square root usmg multiplier 50 is shown As previously noted, Y 0 2 and Y 0 are determmed first (step 730) Once Y 0 2 is determmed, it is multiplied by B to form the term (B x Y 0 2 ) (step 732) The results are then routed down two parallel paths 734 and 736, one that assumes an overflow took place m the multiplication (path 736), and another that assumes no overflow occuned (path 734) Because Y 0 2 is close to 1 B, the product of Y 0 2 and B will be close to one, l e , either slightly over or slightly under one As a result, an overflow will only occur durmg the multiplication if the result (B x Y 0 2 ) is slightly greater than one (l e , of the form 10 000 with an effective exponent equal to 2 ') If there is no overflow, the result will be slightly less than one (l e , m the form 01 111 with an effecti \e exponent equal to 2 ') After the multiplication, the overflow path 736 forms the one's complement by inverting the result (B x Y 0 2 ) (step 740) The resultmg value has the form 01 111 with an effective exponent of 2 ' and approximates (2 - B x Y 0 2 ) To form the term (3 - B x Y 0 2 ), a one is effectively added to the result to form 1 111 with an exponent of 2° (step 744) This value is then be πght shifted one bit to reflect the division by two m the term (3 - B x Y 0 2 ) / 2 (step 748) This results in a value havmg the form 1 111 with an exponent of 2 ' (step 748) The non-overflow path 734 also forms the one's complement by inverting the result (B x Y 0 2 ) (step 738) The resulting value, however, has the form 10 000 with an effective exponent of 2 ' This form is normalized to 1 000 with an exponent of 2°, which approximates (2 - B x Y 0 2 ) To approximate the term (3 - B x Y 0 2 ), a one is effectively added to the result to form 10 000 (step 742) This value is then be shifted πght one bit to reflect the division by two m the term (3 - B x Y 0 2 ) / 2 (step 746) The result has the form 1 000 In this path, the result's exponent is forced to 2° (step 746) Next, either the overflow path result or the non-overflow path result is selected (step 750) This selection can be performed as previously disclosed, l e , based upon the value of the most significant bit of the result from each path Different bits may be selected from each path to eliminate the need for normalization The selected result is then routed back to the multiplier, which multiplies it with Y 0 (determined durmg step 730) to complete the first iteration and form Y, (step 752) If the desned accuracy has been achieved (step 754), the results are output (step 756) If the desired accuracy has not been achieved, the iteration is repeated to form Y 2 , wherem Y 2 = Y, x (3 - B x Y, 2 ) / 2 (step 758) However, unlike the first iteration, subsequent iterations may require an additional multiplication to form the term Y n 2 (step 760) As with the first iteration, the term (B x Y, 2 ) is close to one Once this term has been calculated, the results are once agam passed down the two paths (overflow 736 and non-overflow 734) in parallel Dependmg upon the accuracy of the initial guess Y 0 and the accuracy desired m the final result, the iterative calculation may be performed any number of times (e g , one, two, or five times) Advantageously, usmg two paths (overflow and non-overflow) may eliminate the need for normalization because the exponent and sign bits may be hard coded based upon the known limits of the incoming operands and whether or not an overflow occurs Note that the steps m the figures are show in a serial fashion for explanatory purposes only Some steps may be performed in parallel or m a different order Further note that the method above may also be used to determine the square root of an operand To implement the square root function, an additional multiplication may be performed durmg each iteration Turning now to Fig 26, an embodiment of multiplier 50 configured to evaluate constant powers of an operand is shown This embodiment may be configured to evaluate one or more constant powers of an operand such as -1 (reciprocal), -1/2, (reciprocal square root), and 1/2 (square root) In addition to the features of the previous embodiments, this embodiment of multiplier 50 compπses a non-overflow logic unit 770A, an overflow logic unit 770B, an initial estimate generator (IEG) 774, two multiplexers 776 and 780, and a control logic 778 Note that non-overflow logic unit 770A and overflow logic unit 770B may also be refened to herem as a "non- overflow path," and "overflow path," respectively Initial estimate generator 774 is coupled to receive multiplier operand 74 and communicate initial estimates, e g , X 0 and Y 0 , to multiplexer 776 Note as used herem, X 0 = Y 0 2 « 1/B, and Y 0 ∞ \NB Multiplexer 776 is configured to select the first multiplication operand from either multiplicand operand 72 or the initial estimate output by initial estimate generator 774 Similarly, multiplexer 780 is configured to select the second operand to be multiplied from either multiplier operand 74 or result 292 from multiplexer 290 Control logic 778 receives control signal 772 and controls multiplexers 776 and 780, exponent control logic 254, and logic units 770A-B Non-overflow logic 770A is coupled to receive values from LSB fix-up logic 288A and output values to multiplexer 290 Similarly, overflow logic 770B is coupled to receive values from LSB fix-up logic 288B and also output values to multiplexer 290 Logic units 770A-B are controlled by control logic unit 778, which mdicates which, if any, constant power operation is bemg performed If a constant power operation is not bemg performed, logic units 770A-B may be configured to simply allow values from fix-up logic units 288A-B to propagate through to multiplexer 290 unchanged When a constant power operation is bemg performed, logic umts 770A-B are configured to form approximations by inverting selected bits from the values received from fix-up logic units 770A-B Logic umts 770 A-B are also configured to force (e g , hard-wne) the exponents associated with the values received from fix- up logic units 288A-B to fixed values These fixed exponents are communicated to exponent control logic 254 Alternatively, exponent control logic 254 may force the exponents to fixed constants when instructed to do so by logic units 770A-B Logic umts 770A-B may each comprise a plurality of mverters, a wire shifter, and one or more hard- wired constants A wire shifter is a plurality of signal, data, or control lmes that are selectively connected and or offset to provide fixed shifting and routmg The following examples illustrate the operation of logic units 770A-B and multiplier 50 m more detail Example of a Reciprocal Operation When a reciprocal operation is performed, multiplier 50 receives the operand to be mverted (refened to herem as "operand B") as multiplier operand 74 Initially, multiplexer 780 is configured to select operand B Initial estimate generator 774 also receives operand B and m response outputs an initial estimate or approximation of the reciprocal (refened to as X 0 ) to multiplexer 776 Multiplexer 776 is configured to select, based upon control signals from control logic 778, the initial estimate, which is then multiplied by operand B to form the quantity (X 0 x B) The quantity (X 0 x B) propagates through multiplier 50 until it reaches logic units 770A-770B Non-overflow logic unit 770A receives a version from fix-up logic 288A that assumes no overflow has occuned Based upon control signal 772, non-overflow logic unit 770A inverts the version of (X 0 x B) it receives to approximate the quantity (2 - X 0 x B) Non-overflow logic unit 770A may be configured to normalize its output by forcing the conespondmg exponent to a constant, e g , 2° Note all references herem are to unbiased exponents For example, an unbiased exponent 2° may translate to a biased exponent of 2 7F (assummg a +7F 16 or +127 10 bias) Similarly, overflow logic unit 770B receives a version from fix-up logic 288B that assumes an overflow has occuned and inverts it Overflow logic unit 770B may also be configured to normalize its output by forcmg the conespondmg exponent to a constant, e g , 2 ' Note that m some embodiments, not all bits from fix- up logic units 288A-B may be used or mverted by logic units 770A-B Once the overflow and non-overflow approximations for the quantity (2 - X 0 x B) have been output by logic units 770A-B, multiplexer 290 is configured to select one of the approximations based upon the value of MSB 284 from the output of fix-up logic unit 288A As previously noted, by looking at the most significant bit a determmation of whether an overflow occuned can be made If an overflow occuned, the approximation for the quantity (2 - X 0 x B) from logic unit 770B (the overflow path) is selected If an overflow did not occur, the approximation for the quantity (2 - X 0 x B) from logic unit 770A (the non-overflow path) is selected Note that other control configurations are possible, e g , MSB 284 may be the most significant bit of the output from fix-up logic unit 288B Once the appropriate approximation for the quantity (2 - X 0 x B) has been selected by multiplexer 290, it is routed to multiplexers 776 and 780 Multiplexer 780 is directed by control logic 778 to select the approximation so that it may be multiplied by initial estimate X 0 to form the quantity X 0 x (2 - X„ x B) Durmg this multiplication, however, logic units 770A-B are configured to allow the values from fix-up logic units 288A- B to pass through unchanged The result selected by multiplexer 290 is the approximation of the reciprocal of operand B after one Newton-Raphson iteration As previously noted, the process may be repeated a number of times to achieve greater accuracy Example of a Reciprocal Square Root Operation When a reciprocal square root operation is performed, multiplier 50 operates m much the same fashion as previously described for a reciprocal operation The operand to be raised to the -1/2 power (refened to herem as "operand B") is received as multiplier operand 74 Initially, multiplexer 780 is configured to select operand B Initial estimate generator 774 also receives operand B and in response outputs an initial estimate or approximation of the reciprocal (refened to as Y 0 2 , which equals X 0 ) and the reciprocal square root (refened to as Y 0 ) to multiplexer 776 Multiplexer 776 is configured to select, based upon control signals from control logic 778, the initial estimate Y 0 2 , which is then multiplied by operand B to form the quantity (Y 0 2 x B) The quantity (Y 0 2 x B) propagates through multiplier 50 until it reaches logic units 770A-770B Non-overflow logic unit 770A receives a version from fix-up logic 288A that assumes no overflow has occuned Based upon control signal 772, non- overflow logic unit 770A inverts the version of quantity (Y 0 2 x B) it receives to approximate the quantity (2 - Y 0 2 x B) Logic unit 770A also pads the most significant bit of the quantity (2 - Y 0 2 x B) with a constant one to approximate the quantity (3 - Y 0 2 x B) Logic unit 770A may then normalize the quantity (3 - Y 0 2 x B) by selectively routing (e g , wire-shiftmg) bits to multiplexer 290 in a particular position or offset and by forcmg the conespondmg exponent to 2° Overflow logic unit 770B may be similarly configured to invert the version of quantity (Y 0 2 x B) it receives to approximate the quantity (2 - Y 0 2 x B) Logic unit 770B also pads the most significant bit of the quantity (2 - Y 0 2 x B) with a constant one to approximate the quantity (3 - Y 0 2 x B) Logic unit 770B may then normalize the quantity (3 - Y 0 2 x B) by selectively routmg bits to multiplexer 290 m a particular position or offset and by forcmg the conespondmg exponent to 2 ' Note that m some embodiments, not all bits from fix-up logic units 288A-B may be used or mverted by logic units 770A-B Once the overflow and non-overflow approximations for the quantity (3 - Y 0 2 x B) have been output by logic units 770A-B, multiplexer 290 is configured to select one of the approximations based upon the value of MSB 284 from the output of fix-up logic unit 288A As previously noted, by lookmg at the most significant bit a determmation of whether an overflow occuned can be made If an overflow occuned, the approximation for the quantity (3 - Y 0 2 x B) from logic unit 770B (the overflow path) is selected If an overflow did not occur, the approximation for the quantity (3 - Y 0 2 x B) from logic unit 770A (the non-overflow path) is selected Other control configurations are also possible Once the approximation for the quantity (3 - Y 0 2 x B) has been selected by multiplexer 290, it is routed to multiplexer 780 Multiplexer 780 is dnected by control logic 778 to select the approximation so that it may be multiplied by initial estimate Y 0 that was read from initial estimate generator 744 to form the quantity Y 0 x (3 - Y 0 2 x B) Durmg this multiplication, however, logic units 770A-B are configured to allow the values from fix-up logic units 288A-B to pass through unchanged The result selected by multiplexer 290 is the approximation of the reciprocal square root of operand B after one Newton-Raphson iteration As previously noted, the process may be repeated a number of times to achieve greater accuracy However, m subsequent iterations the result may be squared to form Y n 2 , which is then used m place of the initial estimate Y 0 2 from initial estimate generator 774 Note other configurations of multiplier 50 are possible and contemplated For example, non-overflow logic 770A and overflow logic 770B may mstead be configured to receive rounded and normalized value 292 from multiplexer 290, m which case a separate multiplexer (not shown) may be needed to select between the values output by non-overflow logic 770A and overflow logic 770B In some embodiments of multiplier 50, registers may be used to store various intermediate results, e g , the inputs to multiplexers 776 and 780, and the results from multiplexer 290 The registers may the store the intermediate results for use durmg subsequent clock cycles Turning to Fig 27, details of one exemplary embodiment of non-overflow logic unit 770A configured to calculate the quantity (3 - Y 0 2 x B) for the reciprocal square root calculation are shown When the quantity (Y 0 2 x B) 790A is received from LSB fix-up logic 228A, mverters 792A invert selected bits to approximate the quantity (2 - Y 0 2 x B) Note that an inverter may not be required for all bits, e g , the most and least significant bits Constants 794A are then used to replace the most significant bit of the quantity (2- Y 0 2 x B) 790A to approximate the quantity (3 - Y 0 2 x B), which is output to multiplexer 290 A constant or control signal may be routed to exponent control logic 254 to force the conespondmg exponent to 2° A numerical example further illustrates the operation of non-overflow logic unit 770A First, the value 1 111 x2 ' is received from LSB fix-up logic 228A as an approximation of the quantity (Y 0 2 x B) 790A Next, inverters 792A invert the quantity to generate 10 000 x2 ' as an approximation of the quantity (2 - Y 0 2 x B) Finally, constants 794A are used to replace the most significant bits The results are shifted, resultmg in the quantity 1 00000 , and the conespondmg exponent is forced to 2° Note that the most and least significant bits of the quantity (Y 0 2 x B) 790A may not be mcorporated mto the quantity (2 - Y 0 2 x B) Overflow logic 770B operates m a similar fashion However, the most significant bit of quantity 790B is replaced with only a smgle constant 794B, and bits 30 through 0 are mcorporated mto the quantity (2 - Y 0 2 x B) A numerical example further illustrates the operation of overflow logic unit 770B First, the value 10000 x2 ' is received from LSB fix-up logic 228B as an approximation of the quantity (Y 0 2 x B) 790B Next, inverters 792B invert the quantity to generate 01 111 x2 ' as an approximation of the quantity (2 - Y 0 2 x B) Finally, constant 794B is used to replace the most significant bit The results are shifted, resulting m the quantity 1 1111 , and the conespondmg exponent is forced to 2 ' Turning now to Fig 28, another exemplary embodiment of non-overflow logic 770A and overflow logic 770B is shown The embodiments shown m the figure are configured to return the quantity (2 - Y 0 2 x B) for the reciprocal calculation A numerical example illustrates the operation of non-overflow logic 770A and overflow logic 770B Assuming non-overflow logic 770A receives a value 1 111 x 2 ' as the quantity (Y 0 2 x B) 790A, then inverters 792A are used to invert the bits (excluding the least significant bit) to obtain a value 0.000... Constant 796A is then used to pad the most significant bit position. The remaining bits are all shifted one position, with the result 1.0000. , . being output to multiplexer 290. The conesponding exponent is forced to 2° by signal 796A. Overflow path 770B operates in a similar fashion. For example, assuming value 790B is 1.000... x 2 ' then inverters 792B generate the value 0.111... which is shifted and output to multiplexer 290 as the value 1.11... Note the least significant bit may be padded with a constant 794B, e.g., zero, while the conesponding exponent is forced to 2 "1 by signal 796B. Note the examples and figures refened to herein are exemplary. Other configurations for non-overflow logic 770A and overflow logic 770B and multiplier 50 are also contemplated. For example, the least significant bit from quantity 790B may be duplicated instead of using constant 794B. Other constant values may also be used, and the widths of quantities 770A-B may be reduced before they are routed to multiplexer 290 (e.g., from 32 bits to 24 bits). Other logic components may be used in place of inverters 792A-B, and the bit routing structure disclosed above may be replaced by other logic components, e.g., a shifter. The functionality provided by non-overflow logic 770A and overflow logic 770B may be provided in other components internal or external to multiplier 50. In addition, multiplier 50 may be configured to perform both reciprocal and reciprocal square root functions, e.g., by incorporating two versions of non-overflow logic 770A and overflow logic 770B, or by incorporating multiplexers within non-overflow logic 770A and overflow logic 770B to select which routing of bits and constants should be applied. Compression of Intermediate Products When performing iterative calculations, multiplier 50 calculates intermediate products which may be stored in registers. During the next iteration, the intermediate product may be read from the register and used as an operand. Unfortunately, each iteration may introduce rounding enors that accumulate in the final result. For example, assuming an N-bit significand, the results from each multiplication have significands that are 2N bits wide. This result may be rounded to N-bits or some other width. The greater the number of iterations, the larger the potential rounding enor may be in the final result. For obvious reasons, it is desirable to reduce the magnitude of this rounding enor. One possible method to reduce the rounding enor is to calculate extra bits for each intermediate product and then round at lower bit positions. Each iteration may generate accurate bits in lower (less significant) bit positions than the previous iteration. However, due to the fixed size of the storage registers within multiplier 50, the extra bits will not fit unless the registers within multiplier 50 are widened accordingly. There are several potential drawbacks to using wider registers, including the additional die space requirements and the additional architectural state requirements for context switches. Thus, a mechanism for maintaining the accuracy provided by the extra bits without using wider registers may be desirable. One possible method for providing such extra accuracy without increasing the size of the storage registers is to compress the intermediate results before they are stored. However, not all compression algorithms are well suited for use within multiplier 50. One concern, in particular, is speed. Another concern is the die space required to implement the compression. Turning now to Figure 29A, a flowchart illustrating one possible method for fast compression is shown In the embodiment illustrated, the mtermediate product is first calculated to N extra significant bits (step 600), wherem N is a predetermined constant For example, assummg multiplier 50 receives 24-bit operands, multiplier 50 may calculate intermediate products to a precision of 28 bits In this case, N equals 4 bits Once the mtermediate product is calculated, the next-to-most significant bit is exammed (step 602) The value of the next- to-most significant bit determines the value of a signaling bit If the next-to-most significant bit equals one (step 604), then the signaling bit equals one also If, on the other hand, the next-to-most significant bit equals zero (step 606), then the signaling bit equals zero The signaling bit is used to replace a portion of the mtermediate product, thereby compressmg the mtermediate product (step 608) In one embodiment, the portion replaced by the signaling bit is N+l bits wide While this method assumes that the portion bemg replaced compnses entirely one's or zero's, this may be a safe assumption when certam types of iterations are bemg performed For example, when performing the Newton-Raphson iterations previously disclosed for calculating the square root and mverse square root, the products (2 - B x X n ) and (3- B x Y„ 2 ) are formed durmg each iteration As previously noted, these product are very close to one (e g , either slightly over one, 1 00000000 x 2°, or slightly under one, 1 11111111 x 2 ') Accordmgly, many of the leading bits (excludmg the most significant bit m some cases) of the products are identical, I e , either all zeros or ones, from one iteration to the next with differences occurring m the less significant bits This property allows the method illustrated m Figure 29A to be used effectively The maximum number of bits that may be compressed in a particular implementation may be determmed by examining the number of bits that have the same values over the entire range of possible operand values For example, if an embodiment usmg a 32-bit significand is determmed to have nine bits that have the same value for all possible operand values, then the 32-bit results may compressed so that they may be stored m 24-bit registers While the present embodiment illustrated m the figure performs the compression whenever a particular iterative calculation is performed, m other embodiments the compression may be performed conditionally For example, in one embodiment the compression may be performed only if a comparison of the bits to be compressed shows that they all have the same value While many different types of hardware may be used to perform this comparison, one possible configuration may utilize multiple mput AND gates and multiple mput NAND gates If the testing logic determines that the bits to be compressed do not all have the same value, then the operand may stored by truncating the extra least significant bits While this implementation may lose the benefit of mcreased accuracy m some cases, this may be adequate if the bits to be compressed rarely have different values When the compressed mtermediate product is needed for the next iteration, it may be decompressed Turning now to Figure 29B, one possible method for decompressing the compressed mtermediate product is illustrated First, the compressed mtermediate product is read from the storage register (step 612) Next, the compressed mtermediate product is expanded by paddmg the next- to-most significant bits with copies of the signaling bit (step 614) The number of copies of the signaling bit that are padded or inserted below the most significant bit m this embodiment equals N-l Advantageously, the expanded mtermediate product now has the same width as the oπgmal intermediate product For example, if the compressed intermediate product compnses 24 bits, and the oπgmal intermediate product comprises 28 bits, then the signaling bit will be copied 4 times to render an expanded mtermediate product havmg 28 bits Advantageously, usmg the methods illustrated in Figures 29A and 29B, no information is lost m the compression and decompression process Note that the bits replaced by the signalmg bit need not be the most significant bit They may begm with the next-to-most significant bit For example, if the most significant bit of the mtermediate product is bit 27, the bits replaced by the signal bit may comprise bits 22 through 26 Further note that the signalmg bit may simply be a particular bit withm the mtermediate product, l e , an extra calculation to determine the signal bit is not required Furthermore, the signal bit need not be the most significant or least significant bit in the range of bits to be compressed, l e , the signal bit may be a bit in the middle of the range of bits to be compressed Turning now to Figure 30, one embodiment of multiplier 50 configured to compress mtermediate products is shown As m previous embodiments, this embodiment of multiplier 50 comprises partial product generator 60, selection logic 62, and partial product anay adder 64 This embodiment also compnses demultiplexer 622, 24-bit storage register 638, and multiplexers 776 and 780 Demultiplexer 622 receives an intermediate product 620 from partial product anay adder 64 Other embodiments are also contemplated For example, demultiplexer 622 may receive intermediate product 620 from multiplexer 290 (see Fig 26) Demultiplexer 622 routes intermediate product 620 accordmg to an iterative control signal 644 For example, if iterative control signal 644 indicates that an iterative operation is bemg performed then mtermediate pioduct 620 is routed to storage register 638 If, on the other hand, iterative control signal 644 indicates that an iterative operation is not being performed, then mtermediate product 620 may be routed to standard roundmg logic (not shown) and then output In another embodiment, intermediate product 620 may be rounded before reachmg demultiplexer 622 In this case, demultiplexer 622 may simply route product 620 to an output of multiplier 50 if an iterative calculation is not being performed In the event an iterative operation is being performed, storage register 638 is configured to store intermediate product 620 until it is needed for the next iteration The signal and data lmes coupled to the mputs and outputs of storage register 638 may be refened to herem as a wire shifter because they provide a fixed shifting function As previously noted, storage register 638 may be implemented so that it is smaller than intermediate product 620 Assuming, for example, that intermediate product is 28 bits wide, storage register 638 may be configured to store only the 24 least significant bits of intermediate product 620 Assummg the five next- to-most significant bits of intermediate product 620 all have the same value for the particular iteration bemg performed, then bit 22 may be selected as a signal bit 632 to replace the four next-to-most significant bits 636 Thus, as the figured illustrates, storage register 638 may be configured to store bits 0-21, signal bit 632, and bit 27 When the next iteration is performed, bits 0-21, signal bit 632, and bit 27 are read from storage register 638 To recreate the full 28 bits of mtermediate product 620, signal bit 632 is copied four times to recreate bits 23-26 Advantageously, no information from mtermediate product 620 is lost m the compression and decompression cycle Multiplier 50 may also be configured with optional testing logic 624, which is configured to determine whether the five most significant bits from mtermediate product 620 have the same value In one embodiment, testmg logic 624 may comprise five-input AND gate 626, five-input NOR gate 628, and two-input OR gate 630 The output from two-input OR gate 630 may be used m a number of ways, e g , to signal an enor condition or to cause register 638 to store the 24 most significant bits without compression In some embodiments, testmg logic 624 may be omitted Furthermore, demultiplexer 622 may also be omitted In such embodiments, product 620 may be rounded and then routed to both storage register 638 and the outputs of multiplexer 50 In the event of an iterative calculation, external logic may be used to ensure that functional units or other parts of the microprocessor will not use the data output by multiplier 50 until the iterative calculation is completed Turning now to Figure 31 A, a figure illustrating one possible method for compression is shown As the figure illustrates, uncompressed mtermediate product 656 may compπse 28 bits numbered 0 through 27 If the five most significant bits 652 from mtermediate product 656 all have the same value, they may be compressed mto one signal bit 654 This allows uncompressed intermediate product 656 to be represented and stored as compressed mtermediate product 658, thereby using only 24 bits When compressed mtermediate product 658 is uncompressed, signal bit 654 is copied four times to create the four most significant bits of uncompressed intermediate product 660 Turning now to Figure 3 IB, a figure illustratmg another possible method for compressing mtermediate product is shown In this embodiment, mtermediate product 676 is characterized by havmg five equal bits 672 directly below most significant bit 680 As the figure illustrates, the five equal bits 672 may be compressed mto one signal bit 674 even though they are not the most significant bits m intermediate product 676 Compressed product 678 is still able to fit within a 24 bit storage register To decompress compressed product 678, four copies of signal bit 674 are inserted below most significant bit 680 withm uncompressed product 682 Once again, no information from intermediate product 676 is lost in the process As this example illustrates, the contemplated compression method may be used regardless of where the bits having equal values are located Advantageously, no information is lost if the bits having equal values are located in the same position m each iteration Achieving Higher Frequencies of Exactly Rounded Results When an infinitely precise result is rounded to the nearest machine number, the maximum possible enor is one-half of a unit m the last place (ulp) When performing an iterative calculation such as the Newton-Raphson iterations discussed above for the reciprocal and reciprocal square root, the results converge toward the infinitely precise result However, due to limitations m the number of bits of precision that are available, the number of iterations performed, and the approximations discussed above to improve the speed of each iteration, some mput operands may generate results from multiplier 50 that do not equal the infinitely precise result rounded to the nearest machme number (also refened to as the "exactly rounded result") This holds true even when each iteration is configured to use the "round to nearest" roundmg mode Thus, it would be desirable to mcrease the frequency or probability that the calculated result equals the exactly rounded result One method to determine whether the calculated result equals the exactly rounded result is to multiply the calculated result (calculated to at least one extra bit of accuracy, l e , N+l bits) and the ongmal operand B (assummg the reciprocal of B has been calculated) The exactly rounded result may then be selected from the followmg three values the N-bit result (without the extra bit) plus one m the least significant bit, the N- bit result minus one m the least significant bit, or the N-bit result plus zero The exactly rounded result is selected based upon the value of the extra computed bit (1 e , bit N+l) and whether the result of multiplication was greater than one, less than one, or equal to one Rather than computmg the exactly rounded result with a probability of one as descnbed above (1 e , performmg an extra multiplication step), multiplier 50 may be configured to achieve nearly the same accuracy (l e , computmg the exactly rounded result with a probability close to one) by addmg an "adjustment constant" to the result produced from the last step of the iterative calculation before roundmg Dependmg upon the actual implementation of the multiplier (e g , the number of bits of precision, the number of iterations performed, and the accuracy of the initial approximation) the probability that the calculated result is higher than the exactly rounded result ("P h , gh ") mav oe greater than the probability that the calculated result is lower than the exactly rounded result ("P| 0W ") If this is the case, then addmg a negative adjustment constant m the final step of the iteration may mcrease the probability that the calculated result will equal the exactly rounded result ("P cqUa i") Similarly, if P hlgh is less than P, ow , then addmg a positive adjustment constant may mcrease P equal The probabilities P hlgh , P, ow , and P cqual may be determmed by passmg a large number of differing input operand values through the iterative calculation (as performed by the multiplier) and then comparing each result with the conespondmg exactly rounded result A computer program may be particularly useful m performmg the comparisons The comparisons may also be performed before roundmg, l e , comparmg the infinitely precise results with the results from the multiplier's final iteration before they are rounded Turning now to Fig 32, an embodiment of multiplier 50 configured to add a conection constant is shown Generally, multiplier 50 may be configured smularly to other embodiments disclosed herem that are capable of performmg iterative calculations However, m this embodiment control logic 778 is configured to convey adjustment constant 800 to partial product anay adder 64 durmg the last step of an iterative calculation Partial product anay adder 64 then sums adjustment constant 800 with the selected partial products from selection logic 62 Advantageously, this configuration may not require an additional set of adders to sum adjustment constant 800 into the result Another potential advantage of this configuration is that any overflows or denormalizations that occur as a result of adjustment constant 800 are addressed by the roundmg and normalization process already built mto multiplier 50 (l e , carry-save adders 276A-B, carry-propagate adders 278A-B, sticky bit logic units 280A-B, LSB fix-up logic units 288A-B, and logic units 770A-B) In another embodiment, adjustment constant 800 may mstead be summed mto the result by carry-save adders 276A-B and or carry-propagate adders 278A-B Another embodiment may mcorporate an extra adder (not shown) to sum adjustment constant 800 with result 292 from multiplexer 290 However, this configuration may requne additional logic m the event the result becomes denormalized or expeπences an overflow as a result of the addition Control logic 778 may be configured to convey adjustment constant 800 to partial product anay adder 64 dunng the final multiplication m each iteration, or just for the final multiplication dunng the final iteration For example, if the iterative calculation mvolves two multiplication operations for each iteration, and three iterations are required to achieve the desired accuracy, then control logic 778 may be configured to convey adjustment constant 800 dunng the final multiplication of each iteration, l e , three times, or only once dunng the second multiplication of the third and final iteration In yet another embodiment, control logic 778 may convey adjustment constant 800 to partial product adder 64 dunng every multiplication m the iteration In yet another embodiment, control logic unit 778 may store a number of different adjustment constants 800, e g , one for each type of iteration In such a configuration, control logic unit 778 may convey the appropriate adjustment constant that conesponds to the type of iterative calculation bemg performed Control logic unit 778 receives an indication of which iterative calculation is bemg perform via control signal 722 For example, when control signal 722 indicates that the reciprocal iterative calculation is to be performed, control logic 778 may convey a first adjustment constant 800 to partial product anay adder 64 However, when control signal 722 mdicates that the reciprocal square root iterative calculation is bemg performed, control logic 778 may convey a second, different adjustment constant to partial product anay adder 64 In another embodiment, multiplier 50 may be configured to calculate three versions of each result, l e , a first result generated without adding an adjustment constant, a second result generated by addmg an adjustment constant, and a third result generated by subtracting the adjustment constant Alternatively, the second and thnd results could be calculated by addmg different adjustment constants These results may be calculated in parallel by multiplier 50 Once the result without the adjustment constant is generated, a multiplication may be performed as described above to determine whether the result is conect, too high, or too low The conespondmg result may then be selected Exemplary Configuration Using Two Multipliers Turning now to Fig 33A, an example of a vector multiplication using two multipliers 50A and 50B is shown Multipliers 50A and 50B may be configured similarly to multiplier 50 as descnbed m previous embodiments As shown m the figure, multipliers 50A and 50B are configured to operate m parallel to execute a vector multiplication of a pan of vectors each compnsmg four 16-bit operands 380A-380D and 382A-382D Note operands 380A-380D may come from a first 64-bit MMX register, while operands 382A-382D may come from a second 64-bit MMX register Turning now to Fig 33B, another example of a vector multiplication usmg multipliers 50A and 50B is shown In this configuration, multipliers 50A and 50B operate in parallel to multiply a pan of vectors each comprising two 32-bit operands 384A-384B and 386A-386B Once agam, operands 384A-384B may come from a first 64-bit MMX register, while operands 386A-386B may come from a second 64-bit MMX register Further note that while a vector operation is bemg performed, each mdividual multiplier 50A and 50B is performmg a scalar multiplication Other modes of operation are also contemplated, for example, multiplier 50A may perform a 32-bit scalar multiplication independent from multiplier 50B While multiplier 50A performs the multiplication, multiplier 50B may sit idle or perform an mdependent multiplication operation Exemplary Computer System Using Multiplier Turning now to Fig 34, a block diagram of one embodiment of a computer system 400 mcludmg microprocessor 10 is shown Microprocessor 10 is coupled to a vanety of system components through a bus bridge 402 Other embodiments are possible and contemplated In the depicted system, a mam memory 404 is coupled to bus bridge 402 through a memory bus 406, and a graphics controller 408 is coupled to bus bridge 402 through an AGP bus 410 Finally, a plurality of PCI devices 412A-412B are coupled to bus bπdge 402 through a PCI bus 414 A secondary bus bridge 416 may further be provided to accommodate an electncal mterface to one or more EISA or ISA devices 418 through an EISA/ISA bus 420 Microprocessor 10 is coupled to bus bπdge 402 through a CPU bus 424 Bus bridge 402 provides an interface between microprocessor 10, mam memory 404, graphics controller 408, and devices attached to PCI bus 414 When an operation is received from one of the devices connected to bus bridge 402, bus bndge 402 identifies the target of the operation (e g a particular device or, m the case of PCI bus 414, that the target is on PCI bus 414) Bus bndge 402 routes the operation to the targeted device Bus bndge 402 generally translates an operation from the protocol used by the source device or bus to the protocol used by the target device or bus In addition to providmg an mterface to an ISA/EISA bus for PCI bus 414, secondary bus bndge 416 may further incorporate additional functionality, as desired For example, m one embodiment, secondary bus bndge 416 includes a master PCI arbiter (not shown) for arbitrating ownership of PCI bus 414 An input/output controller (not shown), either external from or integrated with secondary bus bπdge 416, may also be mcluded withm computer system 400 to provide operational support for a keyboard and mouse 422 and for various serial and parallel ports, as desired An external cache unit (not shown) may further be coupled to CPU bus 424 between microprocessor 10 and bus bridge 402 m other embodiments Alternatively, the external cache may be coupled to bus bridge 402 and cache control logic for the external cache may be integrated mto bus bπdge 402 Mam memory 404 is a memory m which application programs are stored and from which microprocessor 10 primarily executes A suitable mam memory 404 comprises DRAM (Dynamic Random Access Memory), and preferably a plurality of banks of SDRAM (Synchronous DRAM) PCI devices 412A-412B are illustrative of a vaπety of peripheral devices such as, for example, network mterface cards, video accelerators, audio cards, hard or floppy disk drives or drive controllers, SCSI (Small Computer Systems Interface) adapters and telephony cards Similarly, ISA device 418 is illustrative of vaπous types of peripheral devices, such as a modem, a sound card, and a variety of data acquisition cards such as GPIB or field bus mterface cards Graphics controller 408 is provided to control the rendering of text and images on a display 426 Graphics controller 408 may embody a typical graphics accelerator generally known m the art to render three- dimensional data structures which can be effectively shifted mto and from mam memory 404 Graphics controller 408 may therefore be a master of AGP bus 410 m that it can request and receive access to a target mterface withm bus bndge 402 to thereby obtam access to mam memory 404 A dedicated graphics bus accommodates rapid retrieval of data from mam memory 404 For certam operations, graphics controller 408 may further be configured to generate PCI protocol transactions on AGP bus 410 The AGP mterface of bus bridge 402 may thus include functionality to support both AGP protocol transactions as well as PCI protocol target and initiator transactions Display 426 is any electronic display upon which an image or text can be presented A suitable display 426 includes a cathode ray tube ("CRT"), a liquid crystal display ("LCD"), etc It is noted that, while the AGP, PCI, and ISA or EISA buses have been used as examples m the above descπption, any bus architectures may be substituted as desired It is further noted that computer system 400 may be a multiprocessing computer system including additional microprocessors (e g microprocessor 10a shown as an optional component of computer system 400) Microprocessor 10a may be similar to microprocessor 10 More particularly, microprocessor 10a may be an identical copy of microprocessor 10. Microprocessor 10a may share CPU bus 424 with microprocessor 10 (as shown m Fig 5) or may be connected to bus bridge 402 via an independent bus It is still further noted that the present discussion may refer to the assertion of vanous signals As used herem, a signal is "asserted" if it conveys a value indicative of a particular condition Conversely, a signal is "deasserted" if it conveys a value indicative of a lack of a particular condition A signal may be defined to be asserted when it conveys a logical zero value or, conversely, when it conveys a logical one value Additionally, various values have been descnbed as bemg discarded m the above discussion. A value may be discarded m a number of manners, but generally mvolves modifymg the value such that it is ignored by logic circuitry which receives the value For example, if the value comprises a bit, the logic state of the value may be mverted to discard the value If the value is an n-bit value, one of the n-bit encodmgs may indicate that the value is invalid Setting the value to the invalid encoding causes the value to be discarded Additionally, an n-bit value may include a valid bit indicative, when set, that the n-bit value is valid Resetting the valid bit may compnse discardmg the value Other methods of discardmg a value may be used as well Although the embodiments above have been descnbed m considerable detail, other versions are possible Numerous vanations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated It is intended that the followmg claims be interpreted to embrace all such vanations and modifications

Claims: WHAT IS CLAIMED IS: 1 A microprocessor comprising a multiplier capable of multiplying one pair of N-bit operands or X pairs of N/X-bit operands simultaneously, wherein N and X are positive mtegers, wherem said multiplier compπses a multiplier mput configured to receive a multiplier operand, wherem said multiplier operand compπses one N-bit value or X N/X-bit values, a multiplicand input configured to receive a multiplicand operand, wherem said multiplicand operand comprises one N-bit value or X N/X-bit values, a partial product generator coupled to said multiplicand input, wherem said partial product generator is configured to generate a plurality of partial products based upon said multiplicand operand, a selection logic unit coupled to said partial product generator and said multiplier mput, wherein said selection logic unit is configured to select a plurality of partial products from said partial product generator based upon said multiplier operand, and a first adder coupled to said selection logic unit, wherem said first adder is configured to sum the partial products selected by said selection unit to form a final product, wherem said final product comprises either one 2N-bιt value or X 2N/X-bιt values 2 The microprocessor as recited m claim 1, further comprising a second adder coupled to said first adder, wherein said second adder is configured to sum said X 2N/X-bιt values to form a vector dot product 3 The microprocessor as recited in claim 1, further comprising a first plurality of multiplexers coupled to said vector mput and said selection logic unit, wherem each multiplexer conesponds to a particular selected partial product, and wherein each multiplexer is configured to conditionally zero-out a predetermmed number of the least significant bits within the conespondmg partial product upon receiving an asserted vector m signal 4 The microprocessor as recited m claim 3, further compnsmg a second plurality of multiplexers coupled to said vector mput and said selection logic unit, wherein each of said second plurality of multiplexers conesponds to a particular selected partial product, and wherem each of said second plurality of multiplexers is configured to sign extend a portion of the conesponding partial product upon receiving an asserted vector m signal 5 The microprocessor as recited m claim 4, wherem said first adder is configured to sum the selected partial products without carrying bits from one 2N/X-bιt final product to another 2N/X-bιt final product upon receivmg an asserted vector in signal 6 The microprocessor as recited m claim 1 , wherein said first adder is configured to shift and sum the partial products selected by said selection unit to form said final product 7 The microprocessor as recited m claim 1, wherem said first adder comprises a plurality of carry-save adders and a carry-propagate adder, wherem said plurality of carry-save adders are coupled to receive said selected partial products and sum them mto a sum value and a carry value, and wherem said carry-propagate adder is configured to sum said sum value and said carry value mto said final product 8 The microprocessor as recited m claim 7, wherem said first adder is configured to generate said X 2N/X-bιt values without allowing any carry bits to propagate from one 2N/X-bιt value to another 2N/X-bιt value 9 The microprocessor as recited m claim 8, wherem said plurality of carry-save adders are configured to sum said final product in redundant form 10 The microprocessor as recited m claim 9, wherem X is the number of vector component products withm said multiplier operand and said multiplicand operand, and wherein N is the bit length of the said multiplier operand and said multiplicand operand 11 A multiplier capable of vector multiplication and scalar multiplication compnsmg a multiplier mput configured to receive a multiplier operand, wherem said multiplier operand compnses one of two forms, wherem said first form is a vector comprising a plurality of packed binary vector component values, wherem said second form is a scalar value, a multiplicand mput configured to receive a multiplicand operand, wherein said multiplicand operand compnses one of said first and second forms, a partial product generator coupled to said multiplicand mput, wherem said partial product generator is configured to generate a plurality of partial products based upon said multiplicand operand, and an adder coupled to said partial product generator, wherem said adder is configured to sum the plurality of partial products generated by said partial product generator to form a final product, wherem said final product comprises one of said first and second forms 12 The multiplier as recited m claim 11, further compnsmg a vector mput configured to receive a vector_ιn signal indicative of whether said multiplier is to perform vector multiplication 13 The multiplier as recited in claim 12, further compnsmg a first plurality of multiplexers coupled to said vector mput and said partial product generator, wherem each multiplexer conesponds to a particular partial product, and wherem each multiplexer is configured to conditionally zero-out a predetermmed number of the least significant bits withm the conespondmg partial product upon receivmg said vector_ιn signal 14 The multiplier as recited in claim 13, wherem said adder is coupled to receive said vector m signal, wherem said adder is configured to sum said partial products without carrymg bits from one of said plurality of packed binary values to another of said plurality of packed binary values upon receiving an asserted vector in signal 15 The multiplier as recited m claim 14, further compnsmg a second plurality of multiplexers coupled to said vector input and said partial product generator, wherem each of said second plurality of multiplexers conesponds to a particular partial product, and wherem each of said second plurality of multiplexers is configured to sign extend a portion of the conesponding partial product upon receiving an asserted vector in signal 16 The multiplier as recited in claim 15, wherem said partial product generator calculates said partial products by logically ANDing said multiplicand operand with each bit of said multiplier operand 17 The multiplier as recited in claim 11, wherem said adder coupled is configured to sum a number of said partial products with a rounding constant in order to form said final product, wherem said final product compnses a plurality of vector component products, wherem each of said vector component products is logically divided mto portions, wherem one or more of said portions are rounded 18 The multiplier as recited in claim 17, further comprising a multiplexer coupled to said adder, wherem said multiplexer is configured to select and output said rounded portions durmg a first clock cycle, and wherem said multiplier is configured to output said non-rounded portions durmg subsequent clock cycles 19 The multiplier as recited m claim 17, wherem said adder is configured to sum said partial products and said roundmg constants m a carry-free fashion 20 The multiplier as recited m claim 17, wherem said adder comprises a first plurality of adders configured to reduce said partial products to a redundant form compnsmg a first sum value and a first carry value, a second plurality of adders coupled to said first plurality of adders, wherem said second plurality of adders are configured to combine said first sum values, said first carry values, and said roundmg constants mto a plurality of second sum values and a second carry values, and a thnd plurality of adders coupled to said second plurality of adders, wherem said thnd plurality of adders are configured to combme said second sum values and said second carry values mto a plurality of non- redundant final vector component products, wherein said non-redundant final vector component products comprise a number of logical portions, wherem a number of said logical portions are rounded 21 The multiplier as recited m claim 20, wherem said thnd plurality of adders are configured to prevent carry- bits generated by said roundmg constants from propagatmg to higher order vector component products 22 The multiplier as recited in claim 20, wherem said first plurality of adders are carry-save adders configured to prevent carry-bits from propagatmg across vector component product boundaries 23 The multiplier as recited m claim 20, wherein said first plurality of adders are carry-save adders configured to allow carry bits generated by the summation of said partial products to propagate across vector component product boundaries, wherein said carry-propagate adders are configured to prevent cames generated by said roundmg constant from propagatmg across vector component boundaries 24 The multiplier as recited m claim 11 , wherem said adder comprises a first plurality of carry-propagate adders configured to sum said partial products to generate a plurality of vector component products, wherem said carry-propagate adders are configured to prevent carry-bits generated by the summation of said partial products from propagatmg across vector component product boundaries, and a second plurality of carry-propagate adders configured to sum said vector component products and said rounding constant to generate a plurality of rounded portions, wherem said carry-propagate adders are configured to prevent carry bits caused by the summation of said vector component products and said roundmg constant from propagatmg across vector component product boundaπes 25 The multiplier as recited m claim 11, further compnsmg an effective sign generator configured to receive a sign-m bit and a most significant bit from a multiplicand operand as an mputs, wherem said effective sign generator is configured to output an effective sign bit conespondmg to said multiplicand operand, wherem said partial product generator is coupled to receive said multiplicand operand and said effective sign bit, wherem said partial product generator is configured to generate said plurality of partial products usmg said multiphcand operand and said effective sign bit 26. The multiplier as recited in claim 25, wherem said effective sign generator comprises a first AND gate coupled to receive said sign-in bit and said most significant bit from said multiplicand operand as inputs, wherein said first AND gate is configured to generate an effective sign for said multiplicand operand, wherein said effective sign for said multiplicand operand is used by said partial product generator to generate said partial products. 27. The multiplier as recited in claim 26 wherein said effective sign generator comprises a second AND gate coupled to receive said sign-in bit and a most significant bit from said multiplier operand as inputs, wherein said second AND gate is configured to generate an effective sign for said multiplier operand, and wherein said effective sign for said multiplier operand is used by said selection logic unit together with said multiplier operand to select said number of partial products from said partial product generator. 28. A method for operating a multiplier within a microprocessor comprising: receiving a multiplier operand, a multiplicand operand, and a vector-in signal as inputs from functional units within the microprocessor; calculating a number of partial products from said multiplicand operand using inverters and shifting logic; selecting partial products according to said multiplier operand; summing the selected partial products to generate a final product, wherein said final product is in scalar form if said vector_in signal is unasserted, wherein said final product is in vector form and comprises a plurality of packed vector components if said vector_in signal is asserted; and outpurting the final product. 29. The method as recited in claim 28, further comprising zeroing out one or more bits within one or more said selected partial products if said vector in input is asserted, and wherein said summing comprises adding said selected partial products without propagating carry bits across boundaries that define said vector components within said final product if said vector_in input is asserted. 30. The method as recited in claim 29, wherein said summing further comprises adding a compensation constant to said final product if said vector n input is asserted. 31. The method as recited in claim 30, further comprising preventing carry bits from propagating across vector allowing carry bits to propagate from the summation of one vector component product to the summation of another vector component product if a vector operation is being performed. 32. The method as recited in claim 28, further comprising rounding one or more of said packed vector components by summing them with a rounding constant. 33. The method as recited in claim 32, further comprising outputting the rounded portions during a first clock cycle and the non-rounded portions during a second subsequent clock cycle. 34. The method as recited in claim 32, wherein said rounding comprises ensuring that carry bits generated by the rounding constant are not allowed to propagate across packed vector component product boundaries. 35. The method as recited in claim 28, further comprising summing the vector components of the final product if the final product is in vector form to product a vector dot product. 36. The method as recited in claim 28, further comprising generating an effective sign bit for said multiplicand operand from a sign-in signal and the most significant bit of said multiplicand operand using an AND gate, wherein said calculating comprises calculating said number of partial products from said effective sign bit and said multiplicand operand using inverters and shifting logic. 37. The method as recited in claim 36, further comprising calculating the effective sign for said multiplier operand using said sign-in signal and the most significant bit of said multiplier operand, wherein said selecting is performed according to said multiplier operand's effective sign bit and said multiplier operand. 38. A multiplier configured to round and normalize products comprising: a first path comprising one or more adders, wherein said first path is configured to receive a redundant-form product and reduce said redundant-form product to a first non-redundant-form product assuming no overflow will occur; a second path comprising one or more adders, wherein said second path is configured to receive said redundant- form product and reduce said redundant-form product to second non-redundant-form product assuming an overflow will occur; and a multiplexer coupled to first path and said second path, wherein said multiplexer is configured to select between said first non-redundant-form product and said second non-redundant-from product. 39. The multiplier as recited in claim 38, further comprising exponent control logic that is configured to adjust an exponent conesponding to said redundant form-product to reflect whether an overflow occuned during rounding. 40. The multiplier as recited in claim 38, wherein said first path comprises a first sticky bit logic unit coupled to receive said redundant-form product and calculate a first sticky bit assuming no overflow will occur, and wherein said second path compnses a second sticky bit logic unit coupled to receive said redundant-form product and calculate a second sticky bit assummg an overflow will occur 41 The multiplier as recited m claim 40, wherem said first path comprises a first fix-up logic unit configured to receive said first non-redundant-form product and said first sticky bit, wherem said first fix-up logic unit is configured to conditionally invert the least significant bit of said first non-redundant-form product, wherem said second path compnses a second fix-up logic unit configured to receive said second non-redundant-form product and said second sticky bit, wherem said second fix-up logic unit is configured to conditionally invert the least significant bit of said second non-redundant-form product 42 The multiplier as recited m claim 41, wherem said first and second fix-up logic units each comprise a carry- save adder, an XNOR gate coupled to receive the output from said carry-save adder, and an OR gate coupled to receive the output from said XNOR gate, wherem each carry-save adder is configured to add a constant to a different portion of said redundant- form product 43 The multiplier as recited m claim 38, wherein said first path comprises a carry-save adder configured to receive and sum said redundant-form product with a roundmg constant, wherein said second path also compπses a carry-save adder configured to receive and sum said redundant-form product with said roundmg constant 44 The multiplier as recited m claim 43, wherem said first path further comprises a carry-propagate adder configured to receive the output from said carry-save adder and form said first non-redundant-form output therewith, wherein said second path further comprises a carry-propagate adder configured to receive the output from said carry-save adder and form said second non-redundant form output therewith 45 The multiplier as recited in claim 43, wherem said rounding constant is a function of the sign bits of the operands being multiplied and a roundmg mode input 46 The multiplier as recited in claim 45, wherem said roundmg constant is selected from a plurality of constants and the mverted and non-inverted outputs of an XOR gate receivmg the sign bits of the operands as mputs, wherem said roundmg constant is selected based upon said roundmg mode mput 47 The multiplier as recited m claim 38, wherem said first path comprises a first adder configured to receive said redundant-form product, wherem said first adder is configured to add a roundmg constant to the guard bit position of said redundant-form value to form said first non-redundant-from product, wherem the guard bit position is selected assummg no overflow, wherem said second path compπses a second adder configured to receive said redundant-form product, wherem said second adder is configured to add said roundmg constant to the guard bit position of said redundant- form product to form a second rounded result, wherem the guard bit position is selected assummg there is an overflow, and wherem said multiplexer is configured to select either the first rounded result or the second rounded result based upon one or more of the most significant bits from the first or second rounded results. 48. The multiplier as recited in claim 43, further comprising a fix-up unit coupled to said multiplexer, wherein said fix-up unit is configured to conditionally invert the least significant bit of the selected non-redundant-form product if round to nearest (even) is being performed and the guard bit, the inverse of the least significant bit, and the inverse of the sticky bit of the selected non-redundant-form product are all one. 49. The multiplier as recited in claim 48, further comprising a rounding constant logic unit configured to generate said rounding constant, wherein said rounding constant logic comprises a second multiplexer, wherein said second multiplexer is configured to receive as inputs an effective sign for said redundant-form value, an inverted effective sign for said redundant-form value, and one or more hardwired constants, wherein said second multiplexer is configured to select of said inputs to be a rounding constant based upon a rounding mode input signal. 50. The multiplier as recited in claim 37, wherein said multiplier is configured to perform iterative calculations, and wherein said multiplier further comprises a wire shifter coupled to said multiplexer and configured to replace a predetermined number of bits of said selected non-redundant- form product with a signal bit, wherein said signal bit represents said predetermined number of bits, wherein said signal bit equals the value of each individual bit within said predetermined number of bits. 51. The multiplier as recited in claim 50, wherein said wire shifter is configured to replace said predetermined number of bits from said intermediate product with said signal bit if a predetermined type of iterative calculation is being performed. 52. The multiplier as recited in claim 51, further comprising a comparator configured to compare a plurality of bits from said selected non-redundant-form product, wherein said wire shifter is configured to compress said intermediate product only if said plurality of bits are equal. 53. The multiplier as recited in claim 38, further comprising: a multiplier input configured to receive a multiplier operand; a multiplicand input configured to receive a multiplicand operand; a partial product generator coupled to said multiplicand input, wherein said partial product generator is configured to generate a plurality of partial products based upon said multiplicand operand; and a partial product anay adder coupled to said partial product generator, wherem said anay adder is configured to sum the plurality of partial products generated by said partial product generator to form said redundant- from product, wherem said partial product anay adder is configured to receive and sum an adjustment constant with said selected plurality of partial products to generate said redundant- form product, wherem said adjustment constant is selected to increase the frequency of exact roundmg 54 The multiplier as recited m claim 53, further compnsmg a control unit coupled to said partial product anay adder, wherem said control unit is configured to prevent said adjustment constant from bemg summed unless the final step of an iterative calculation is bemg performed 55 A microprocessor capable of evaluatmg a constant power of an operand B, said microprocessor compnsmg an initial estimate generator configured to receive said operand and output an initial estimate of said operand B raised to said constant power, a multiplier coupled to receive said operand and said initial estimate, wherem said multiplier is configured to calculate a product of said initial estimate and said operand B, a first plurality of mverters coupled to receive, mvert, and normalize selected bits from said product to form a first approximation, wherem said first approximation assumes an overflow has occuned in said multiplier, a second plurality of mverters coupled to receive, mvert, and normalize selected bits from said product to form a second approximation, wherem said second approximation assumes an overflow has not occuned m said multiplier, and a multiplexer configured to select either said first or second approximations 56 The microprocessor as recited m claim 18, wherem said multiplier is configured to receive and multiply the selected approximation with said initial estimate to form an approximate result, and wherem said first and second pluralities of mverters are configured to perform mdependently and m parallel 57 The microprocessor as recited m claim 56, wherem said multiplier, said first and second pluralities of mverters, and said multiplexer are each configured to repeat their respective operations a predetermmed number of times usmg the selected approximation m place of said initial estimate 58 The microprocessor as recited in claim 56, wherem said multiplexer is configured to select either a first predetermmed set of bits from said first approximation, or a second predetermmed set of bits from said second approximation, wherem said multiplexer is configured to normalize the selected set of bits 59. The microprocessor as recited in claim 55, wherein said constant power is -' , wherein said initial estimate conesponds to operand B's reciprocal, Y 0 2 , wherein said first and second approximations approximate the quantity (2 - Y 0 2 x B) with and without overflow respectively, wherein the most significant bit of said first and second approximations are padded with a constant one to approximate the quantity (3 - Y 0 2 x B) with and without overflow. 60. The microprocessor as recited in claim 59, wherein said initial estimate generator is also configured to output an initial estimate of operand B's reciprocal square root Y 0 , and wherein said multiplier is configured to receive and multiply the selected approximation with Y 0 to form a result approximating the quantity Y 0 x (3 - Y 0 2 x B). 61. The microprocessor as recited in claim 60, wherein said multiplier, said first and second pluralities of inverters, and said multiplexer are each configured to repeat their respective operations using the selected approximation squared in place of said initial estimate. 62. The microprocessor as recited in claim 61, wherein said multiplier, said first and second pluralities of inverters, and said multiplexer are each configured to repeat their respective operations a predetermined number of times using the selected approximation squared in place of said initial estimate. 63. The microprocessor as recited in claim 61, wherein said multiplexer is configured to select either a first predetermined set of bits from said first approximation, or a second predetermined set of bits from said second approximation, wherein said multiplexer is configured to normalize the selected set of bits. 64. A method for rounding and normalizing results within a multiplier comprising: multiplying a first operand and a second operand to form a plurality of redundant- form components; generating an actual rounding constant; summing the redundant-form components and the actual rounding constant to form a first non-redundant-form product, wherein said summing comprises assigning the actual rounding constant to a first bit position, wherein the first bit position is selected assuming no overflow will occur; summing the redundant-form components and the actual rounding constant to form a second non-redundant-form product, wherein said summing comprises assigning the actual rounding constant to a particular bit position, wherein the particular bit position is selected assuming an overflow will occur; selecting a particular set of bits for output from either the first non-redundant- form product or the second non- redundant- form product based upon the most significant bit of the first non-redundant product. 65 The method as recited m claim 64, wherem said generating comprises formmg a first potential roundmg constant by exclusively ORing the sign bits from the first operand and the second operand, formmg a second potential roundmg constant by exclusively NORmg the sign bits from the first operand and the second operand, and selecting either the first potential roundmg constant, the second potential roundmg constant, or a hard-wired constant as the roundmg constant accordmg to a roundmg mode mput 66 The method as recited in claim 65, further compnsmg generatmg a first sticky bit from the plurality of redundant-form components assummg no overflow will occur durmg said summing, and generatmg a second sticky bit from the plurality of redundant- form components assummg an overflow will occur during the addmg 67 The method as recited m claim 66, further compnsmg inverting the least significant bit of the first non-redundant- form product if round to nearest (even) is bemg performed and the guard bit, the inverse of the least significant bit, and the mverse of the first sticky bit are all one, and inverting the least significant bit of the second non-redundant-form product if round to nearest (even) is bemg performed and the guard bit, the mverse of the least significant bit, and the mverse of the second sticky bit are all one 68 A method for performmg iterative calculations m a microprocessor compnsmg calculating an mtermediate product to a first predetermmed number of bits of accuracy, selecting a signalmg bit from said mtermediate product, wherem said signalmg bit is equal to each of a second predetermined number of consecutive bits of said mtermediate product, creatmg a compressed mtermediate product by replacmg said second predetermmed number of consecutive bits of said mtermediate product with said signalmg bit, storing said compressed intermediate product into a storage register; reading said compressed intermediate product from said storage register; and expanding said compressed intermediate product to form an expanded intermediate product by incorporating copies of said signaling bit. 69. The method as recited in claim 68, wherein said expanding comprises incorporating copies of said signal bit into bit positions within said expanded intermediate product that are less significant than the most significant bit of said compressed intermediate product. 70. The method as recited in claim 69, further comprising conditionally adding an adjustment constant to said final result, wherein said adjustment constant increases the probability that said final result will equal the exactly rounded result of said iterative calculation. 71. The method as recited in claim 68, wherein said iterative calculations involve evaluating a constant power of an operand, said method further comprising: determining an initial estimate of the operand raised to a first constant power; multiplying the operand and the initial estimate in the multiplier to form a first product; wherein said calculating an intermediate product comprises: generating a normalized first intermediate approximation by performing a bit-wise inversion on the first product assuming an overflow occuned during said multiplying of the operand and the initial estimate, and generating a normalized second intermediate approximation by performing a bit-wise inversion on the first product assuming no overflow occuned during said multiplying of the operand and the initial estimate; selecting a set of bits from the first intermediate approximation or the second intermediate approximation to form a selected approximation; multiplying the selected approximation by the initial estimate; and multiplying the selected approximation by an estimate of the operand raised to a second constant power. 72. The method as recited in claim 71, wherein said determining comprises reading said initial estimate from an initial estimate generator, and wherein said initial estimate approximates the reciprocal of the operand.

Inventors: CHERUKURI RAVI KRISHNA, JUFFA NORBERT, OBERMAN STUART F, SIU MING, WEBER FREDERICK D, CHERUKURI, RAVI, KRISHNA, JUFFA, NORBERT, OBERMAN, STUART, F., SIU, MING, WEBER, FREDERICK, D.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1998
Main classification: G06F7
IPC codes: G06F7, G06F9, G06F17, H03M7