ANNEALING OF A CRYSTALLINE PEROVSKITE FERROELECTRIC CELL AND CELLS EXHIBITING IMPROVED BARRIER PROPERTIES

Abstract: A method of fabricating a ferroelectric capacitor usable as a memory cell in a non-volatile integrated circuit memory integrated on a silicon substrate (22), preferably including an intermetallic barrier layer. The memory cell consists of a ferroelectric layer (50), for example of lead niobium zirconium titanate (PNZT) sandwiched between metal oxide electrodes (52 and 46), for example of lanthanum strontium cobalite (LSCO), which forms with a crystalline orientation and provides a growth template for the crystalline formation of the ferroelectric. The intermetallic layer (44) prevents diffusion of oxygen from the bottom LSCO electrode (46) down to the underlying silicon (40). At least the bottom electrode (46) is subjected to a rapid thermal anneal at an annealing temperature above its growth temperature. Thereby, the polarization and fatigue characteristics of the ferroelectric cell are improved. Also, a similar intermetallic layer may be placed above the ferroelectric cell. A preferred composition of the intermetallic layer is a refractory silicide, especially a refractory disilicide.

Description: Annealing of a Crystalline Perovskite Ferroelectric Cell and Cells Exhibiting Improved Barrier Properties FIELD OF THE INVENTION The invention generally relates to ferroelectric structures integrated onto substrates such as silicon. In particular, the invention relates to the fabrication process of producing a crystallographically oriented ferroelectric structure. BACKGROUND ART Considerable interest exists in fabricating integrated circuit (IC) memories which are non-volatile, that is, ones that continue to store data after the IC chip has been powered down. One type that is reaching the market is a ferroelectric memory in which the gap between the capacitors of an electrode is filled with a ferroelectric material which can be electrically poled into two stable states. The commercial activity to date has involved polycrystalline ferroelectric materials. Despite intensive developmental efforts, these polycrystalline ferroelectric IC memories exhibit poor fatigue characteristics and suffer from low yield in manufacture. In an alternative approach under development, the ferroelectric material is grown in a crystallographically oriented phase. It is believed that under the proper conditions the ferroelectric grows in a columnar multicrystalline structure with the <001> axis of the layered perovskite crystal structure of typical ferroelectrics being preferentially oriented normal to the ferroelectric film. Examples of the ferroelectric materials include lead zirconium titanate (PZT), lead lanthanum zirconium titanate (PLZT), lead niobium zirconium titanate (PNZT). Columnar crystallites are formed with random orientation within the plane of the film. Dhote and Ramesh, two of the present inventors, have disclosed two distinct but related structures in U.S. Patent Applications, Serial No.08/578,499 filed December 26, 1995 and Serial No. 08/582,545 filed January 3, 1996, both incorporated herein by reference in their entireties. The structure of the latter patent application is illustrated in the cross-sectional view of FIG. 1. An illustrated ferroelectric random access memory (FRAM) cell 20, of which many are formed in the IC memory, is formed on a <001>-oriented crystalline silicon substrate 22 and includes both a ferroelectric capacitor and a transistor. A metal-oxide-semiconductor (MOS) transistor is created by forming source and drain wells 24, 26 having a conductivity type opposite to that of the substrate 22. The intervening gate region is overlaid with a gate structure 28 including a lower gate oxide and an upper metal gate line, for example of aluminum, to control the gate. A first inter-level dielectric layer 30 is deposited over the substrate and the transistor structure. A through hole 32 is etched through the first inter-level dielectric layer 30 in the area over the source well 24, and polysilicon is filled into the through hole 32 to form a polysilicon contact plug to the transistor source. A metal source line 34 is photolithographically delineated on top of the first inter-level dielectric layer 30 and electrically contacts the polysilicon plug 32. A second inter-level dielectric layer 36 is then deposited over the first inter-level dielectric layer 30. Another through hole 38 is etched through both the first and second inter-. level dielectric layers 30, 36 over the area of the drain well 26, and polysilicon is filled into the second through hole 38 to form a contact plug to the transistor drain. A lower ferroelectric stack is then deposited and defined. It includes a polysilicon layer 40 to promote electrical contact to the polysilicon plug 38, a titanium nitride (TiN) layer 42 acting as a first conductive barrier between the underlying polysilicon and the oxidizing ferroelectric layer and its oxide electrodes, an inte-metallic layer 44 acting as the primary barrier, and a lower metal-oxide electrode 46. Growth of the metal-oxide electrodes 46, 52 and the ferroelectric layer 50 is performed at temperatures in the range of 500° to 650°C, the highest temperatures achieved in the processing after the deposition of the intermetallic layer 44. The mtermetallic layer 44 is novel to the cited patent application. It may have a composition of Ti 3 Al, among other possibilities to be discussed later. In brief, an intermetallic is an alloy of at least two metals, one of which is refractory, and the metals are combined in stoichiometric or near stoichiometric ratios. There results a metal with long-range atomic order, that is, a metal that is at least polycrystalline. Liu et al. provide a good introduction to intermetallics, at least as used for mechanical components, in "Ordered Intermetallics," ASM Handbook, vol. 2, Properties and Selection: Nonferrous Alloys and Special-Purpose Materials (ASM International, 1992) pp. 913-942). The lower metal-oxide electrode may have a composition of lanthanum strontium cobaltite (LSCO), and in particular a composition of approximately Laι. x Sr x CoO 3 , where 0. lS^ .δS. It is now well known that LSCO forms an acceptable electrical contact and futher promotes highly oriented growth of perovskite ferroelectric materials. Several variations on the structure of the lower ferroelectric stack are possible. Neither the polysilicon layer 40 nor the TiN layer 42 is considered crucial, and either or both may be dispensed with. A Z-shaped field-oxide layer 48 is formed around the sides of the lower ferroelectric stack and extends over its rim and laterally outwards from its bottom but leaves a central aperture for the after deposited upper ferroelectric stack. The upper ferroelectric stack is then deposited and defined to fill the aperture of the field oxide layer 48 but not to extend beyond the end of its foot. The upper ferroelectric stack includes the ferroelectric layer 50, for example of PNZT, the upper metal-oxide electrode layer 52, for example of LSCO, and a platinum layer 54. A third inter-layer dielectric layer 56 is deposited around the upper and lower ferroelectric stacks. A via hole 60 is etched down to the platinum layer 54, and Ti/W is filled into the hole to form a via 60 contacting the platinum layer 54. An aluminum layer is deposited and delineated to form an interconnect line 62 connected to the via 60. Prototype ferroelectric capacitor stacks have been grown following the vertical stack structure shown in FIG. 1. Both the LSCO electrodes 46, 52 and the ferroelectric layer 50 have been shown to exhibit highly crystalline orientation. The ferroelectric stacks were measured to have polarization, fatigue, and retention properties superior to those available from polycrystalline ferroelectric cells. Nonetheless, the results still need improvement. The cell manufactured according to the process exhibits a hysteresis curve adequate for operation at 5V. However, for high-level integration, 3 V operation is greatly desired. The polarizability of the ferroelectric cell needs to be improved for 3V operation. SUMMARY OF THE INVENTION The invenUon can be summarized as a method of fabπcating a perovskite layer over a metal-oxide layer. At least the metal-oxide layer is subjected to a rapid thermal anneal after its deposition. A ferroelectric memory cell is formed over a silicon substrate with an intermediate intermetallic layer A ferroelectric cell is formed by the sequential growth of a lower metal- oxide electrode, a ferroelectric layer, and an upper metal-oxide layer At least the lower metal-oxide electrode is annealed for a relatively short time at a temperature above the temperature at which it was grown. In another aspect of the invention, the intermetallic layer is formed of a sihcide, most preferably a disi cide of a refractory metal. In yet another aspect of the invenuon, a second intermetallic layer is formed over the upper metal-oxide layer to provide electπcal contacung to an upper metal level. The second intermetallic layer eliminates the need for plannum on the upper side. More preferably, the second intermetallic layer is formed of an intermetallic alummide to provide a robust mterface to an aluminum interconnect plug and aluminum wiring. BRIEF DESCRIPTION OF THE DRAWINGS FIG 1 is a cross-secuonal view of a ferroelectric memory cell uuhzing an lntermetalhc barrier. FIG. 2 is a cross-secuonal view of a test structure used as a prototype for the memory cell of FIG. 1 FIG. 3 is a graph showing a seπes of hysteresis curves for a ferroelectric capacitor of the invenuon. FIG.4 is a graph comparing the remanent polaπzauon of a ferroelectric capacitor with and without the annealing of the invenuon. FIG. 5 is a graph showing polaπzauon properties of a ferroelectric capacitor of the invenuon. FIG. 6 is a graph of the faugue characteπsucs at two different temperatures for ferroelectric capacitors of the invenuon. FIG. 7 is a graph of the faugue characteristics of ferroelectric capacitors with and without the annealing of the invention. FIG. 8 is a graph of the dependence of remanent polarization upon the amount of annealing of the invenuon. FIG. 9 is a graph of the dependences of remanent polarization and surface resistivity upon the amount of annealing of the invention. FIG. 10 is a graph of polarization properties of ferroelectric capacitors lacking a titanium nitπde barrier and alternately being annealed and not annealed. FIG. 1 1 is a graph of fatigue characteristics for the ferroelectric capacitors of FIG. 10 FIG. 12 is a cross-sectional view of an alternauve embodiment of the memory cell of the invention having an intermetallic upper contact layer. FIG. 13 is a graph of the hysteresis curves for two cells alternauvely using an intermetallic and a plaunum upper contact layer. FIG. 14 is a cross-secuonal view of a ferroelectric memory cell uUlizing a silicide bamer. FIG. 15 is a graph showing two hysteresis curves for a test structure with a silicide barπer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In one embodiment of the invention, the structure of FIG. 1 is fabricated by much the same techniques as are described in the referenced patent applicaϋon, as has been briefly described. As in the previously described growth of the lower ferroelectric stack, the lower metal-oxide electrode layer 46 is grown m the temperature range of 550 to 650°C and cooled in an oxygen-rich environment. However, thereafter, the substrate is removed from the growth chamber and is subjected to a rapid thermal anneal at a temperature above its growth temperature for a relatively short period of time. Following the anneal, the previously described processing is resumed, and the structure is completed. By means of the rapid thermal anneal, the polarizauon characteristics of the ferroelectric capacitor are improved while the fatigue and retenuon characteristics are at least maintained. It is believed that the rapid thermal anneal causes the columnar crystallites in the lower metal-oxide layer 46 to enlarge to larger diameters. This layer 46 acts as a crystalline growth template for the growth of the overlying ferroelectric layer 50 with a highly oπented crystalline structure. Since the underlying metal-oxide template layer 46 has large crystallite sizes after the rapid thermal anneal, the after grown ferroelectπc layer 50 also has larger crystallite sizes Feπoelectπc domains are known to have diameters of tens of nanometers. If the diameters of the columnar crystallites are several times this value, then each crystallite will contain several domains. That is. not all ferroelectπc domains will extend across grain boundaπes Hence, grain boundaπes and any subsequent diffusion along the grain boundaπes will not affect all the ferroelectπc domains, and the columnar ferroelectπc layer will more resemble a singly crystalline layer. A second effect is that the rapid thermal anneal will remove defects from the surface and the bulk of the lower metal-oxide layer 46 that would degrade the subsequent growth and would also affect the electπcal characteπsucs of that mterface For example, in an oxygen- πch anneal, the perovskites can absorb more oxygen and reduce the concentration of oxygen vacancies. In some situauons, the anneal amounts to a crystaHizauon of a generally amorphous deposited layer. A large number of expeπments were performed on prototype structures to confirm the advantages of the invenuon. Unpatterned ferroelectπc stacks were grown on either silicon wafers covered by a polysilicon layer or silicon wafers covered by polysihcon and then titanium nitπde. The growths were performed by pulsed laser deposiuon (PLD) with a KrF excimer laser pulsed at 5Hz at a fluence per pulse of 3 Jxcm 2 . The growths were performed with the substrate holder held at 600°C. The intermetallic layer 42 was deposited in a high vacuum while the metal-oxide and ferroelectπc layers were deposited m an oxygen ambient of lOOmTorr. The metal-oxide layers 46, 52 had composiuons of Lao sSr 05 CoO 3 (LSCO) and thicknesses of lOOnm- The ferroelectπc layer 50 had a compos on of PbNbo c-tZro 28T-06β0 3 (PNZT) and a thickness of 300nm. Most of the samples included the top plaunum layer 54. Most electrical characteπzauons were performed upon a prototype capacitor structure shown in FIG. 2. A base structure includes a crystalhne silicon substrate 70, a polysihcon layer 72, and a TiN layer 74. A platinum contact 75 is applied to an exposed area of the TiN layer 74. A lower ferroelectπc stack includes an intermetallic layer 76, a lower metal-oxide electrode layer 78 of LSCO, and a ferroelectric layer 82 of PNZT. An upper metal-oxide electrode layer 84 is deposited over the ferroelectπc layer 82 and formed into relatively small memory capacitors 88 and a much larger coupling capacitor 90 PlaUnum contacts 92, 94 are deposited on the memory and coupling capacitors 88, 90 pπor to the capacitor definition and defined with them. The individual memory capacitors 88 are electπcally accessed between their respective contacts 88 and either the coupling capacitor 90 at the top or the TiN contact 75 at the bottom. Details of the fabrication process are found in the latter referenced patent application to Dhote and Ramesh Experiment 1 A first test chip was fabπcated with the intermetallic layer 76 being composed of N1 3 AI All the laser ablated oxide layers were deposited at 600°C After the deposiuon of the lower LSCO layer 78, the chip was removed from the laser deposiuon chamber and subjected to rapid thermal annealing at 750°C for 120s The hysteresis loops for this chip, illustrated in the graph of FIG. 3, were measured at 100°C The loops were measured for different values of maximum applied voltage, with the largest maximum voltages applied first All the loops manifest good hysteresis, even the 2-volt loop As ferroelectπc memory ICs are extended to capacities of 256Mb and beyond, operation at lower voltages becomes highly desirable. Experiment 2 Two chips were prepared with the intermetallic layer 76 being composed of AlTι 3 with 5wt% doping of Nb They were grown at room temperature. A comparative chip was fabπcated without the rapid thermal anneal. Its polarization characteπstic, as measured by the difference between switched and unswitched polarization, is plotted as a function of applied voltage in curve 104 in FIG. 4 The pulse width of the polmg voltage was 2ms. Another chip was subjected to rapid thermal annealing at 750°C for 160s after the growth of its lower LSCO layer 78. Its correspondmg polaπzation characteπstic is shown in curve 106 The chip that was annealed showed significantly better polaπzation, and its characteπstics in the poling range of 2-3V were acceptable and even better than those of the unannealed chip at significantly higher poling voltages. Experiment 3 Another chip was grown at 600°C with its intermetallic layer of Ni 3 Al and was subjected to rapid thermal annealing. Its remanent polarization fP and coercive voltage E c were measured as a function of the applied voltage. The remanent polarization is difference between the switched and unswitched polarizations and the coercive voltage is the voltage value shown in the hysteresis loop with the polarization is zero. Curve 110 in FIG. 5 shows the remanent polarization; curve 112 shows the coercive voltage. The curves show that capacitors grown by this technique have sufficient (remanent) polarization IP at coercive voltages E c of one volt or less for an applied voltage of 3V, a desirable operating range for ULSI memories. As was shown by the data of FIG. 4, an unannealed capacitor does not afford such high polarization values. The capacitors of the data of FIG. 5 were tested for fatigue by applying a bipolar square pulse of ±5V at 1MHz. Curves 120, 122 of FIG. 6 show the remanent polarization IP as a function of the number of fatigue cycles while the sample was held at room temperature. Curves 124, 126 similarly show the remanent polarization ~P while the sample was held at 100°C during the fatiguing cycles. It is believed that the improvement in the remanent polarization fP after fatiguing at 100°C arises from an effective self-annealing during cycling at elevated temperatures. It is noted that the 10 9 cycles at which the improvement is nearly complete at 100°C corresponds to a self-annealing time of 17 minutes but that the self- annealing was performed after the complete ferroelectric stack had been grown. Experiment 4 Both an inventive and a comparative sample were grown at 600°C with an intermetallic layer of AlTi 3 plus Nb dopants. Fatiguing tests at room temperature were performed on the resultant capacitors. Curves 130, 132 of FIG. 7 show the remanent polarization IP when rapid thermal ---mealing of the bottom LSCO layer was performed at 750°C for 160s while curves 134, 136 show the remanent polarization IP when no rapid thermal annealing as described above was performed. Although the polarization for the annealed sample does fall off above about 10 9 cycles, it still remains above the polarization for the unannealed sample. Experiment 5 Retention time was determined on a sample with an intermetallic layer of Ni 3 Al and which was subjected to rapid thermal annealing. The remanent polarization was measured as a function of time over a period of about a day. The polarization decreased approximately with the logarithm of the time. If this dependence is assumed to extend to a polarization of 2mC/cm : , the retention time at room temperature is about 160,000 years and that at 100°C is about 8000 years. These retention times are considered quite adequate. Experiment 6 Several tests were performed to determine the effect of different amounts of rapid thermal annealing. A first set of samples were grown with an intermetallic layer of AlTi 3 with Nb doping. The lower LSCO layer was deposited at room temperature so that it was amorphous or polycrystalline. The samples were then subjected to rapid thermal annealing at 750°C for times between 80 and 160 seconds. The capacitor fabrication was thereafter completed, and the remanent polarization IP was measured on each sample. The results generally follow plot 140 in FIG. 8. The initial conclusion is that more annealing is beneficial. However, it is believed that excessive annealing will eventually affect the intermetallic layer and cause reliability problems. It is generally accepted that the thermal budget should be minimized consistent with other requirements. That is, the annealing time and temperature should be limited to values required for operational parameters. A second set of samples were grown with an intermetallic layer of Ni 3 Al. After the growth of the amorphous lower LSCO layer, the samples were subjected to different amounts of rapid thermal annealing at 750°C. After completion of the capacitor structures, both the remanent polarization and the resistivity were measured. The resistivity was measured with a two-point probe method using one small contact 88 and the large contact 90 of the type illustrated in FIG. 2. The measured resistance was normalized to resistivity -issuming a capacitor stack of 50mm on a side and a ferroelectric thickness of 300nm. The experimental results are shown in curve 142 of FIG. 9 for the remanent polarization IP and in curve 144 for the resistivity. Similarly to the results of FIG. 8, prolonged rapid thermal annealing increases the polarization. For lesser amounts of annealing, the lower LSCO layer remained crystallographically unoriented producing a disordered fe-Toe-ectric layer. The resistivity is nearly constant and confirms that the thickness of the ferroelectric layer did not significantly vary between the samples. The upper bounds of thermal annealing are not easily quantifiable and will need to be optimized in an overall process. Rapid thermal annealing of crystalline layers for more than 5 minutes defeats the purpose of RTA. However, an amorphous LSCO layer could benefit from a long anneal, about 15 minutes, in an oxygen-rich environment. Experiment 7 In our prior patent, we have suggested that a TiN baπier layer is not required to separate the intermetallic barrier layer from the underlying silicon. Samples were grown to confirm this result, both with and without rapid thermal annealing. Referring to FIG. 2, the intermetallic layer 76 of Ni 3 Al was grown directly on the polysilicon layer 72. The annealing, if performed, was for 120s at 750°C. Curve 150 in FIG. 10 shows the measured remanent polarization IP as a function of the applied voltage when the sample was subject to rapid thermal anneahng while curve 152 shows the corresponding values without annealing. Curves- 154, 156 show the measured coercive voltage Ec as a function of the applied voltage for the annealed and unannealed samples respectively. In comparison with the data presented in FIG. 5 for a structure including the TiN barrier layer, it is seen from FIG. 10 that the absence of the TiN barrier has little effect upon the annealed sample. However, the rapid thermal annealing of the non-TiN samples significantly improves the polarization. Fatigue tests were also performed on these samples. Curves 160, 162 in FIG. 11 show the dependence of the remanent polarization upon the number of cycles at 100°C for an annealed sample while curves 164, 166 show the corresponding dependence for an unannealed sample. Similar results are obtained for fatiguing at room temperature although then the unannealed sample is not so greatly inferior to the annealed sample. The results of FIG. 11 for no TiN barrier should be compared with those of FIG. 6 for a TiN barrier. All these results confirm that the intermetallic barrier eliminates the need for a TiN barrier. The memory cell structure shown in FIG. 1 has some potential problems. Platinum is very porous to oxygen so that the upper platinum electrode 54 presents no barrier to oxygen diffusing upwardly from the upper metal-oxide electrode 54 to the aluminum in the plug 60 or interconnect 62. Oxygen in sufficient amounts causes aluminum to ball up, introducing excessive contact resistance and greatly degrading the hysteresis characteristics observable from outside the ferroelectric stack If the plug 60 is composed of aluminum, a TiN barπer may be deposited at the bottom of the contact hole before the aluminum deposition to prevent the oxygen diffusion However, TiN does not adhere well to platinum so an intermediate glue layer of TiW may be required The result is a complex fabπcation process Alternatively, the enure plug 60 may be composed of TiW, but deposition of thick layers of Ti W is not widely practiced in silicon processing Furthermore, the platinum is difficult to etch, particularly in a production-worthy process According to another aspect of the invention, the upper platinum layer 54 of FIG 2 is replaced, as illustrated in FIG 12, by an upper intermetallic layer 170 directly overlying the upper metal-oxide layer 52 The upper intermetallic layer 170 acts as a barπer preventing the upwards migration of oxygen from the metal-oxide layer 52 to the overlying aluminum Advantageously, the upper intermetallic layer 170 is composed of an alummide mtermetalhc, such as AIT1 3 , N1 3 AI, or NiAl Then the via hole can be filled with a plug 172 of aluminum, which will bond well to the underlying alummide intermetallic layer 170 The alummide provides a good mechanical and ohmic interface between aluminum and the aluminide intermetallic The use of non-alummide intermetaUics may necessitate a glue layer between the aluminum plug 172 and the mtermetalhc layer 170 As is well known in silicon processing, the aluminum of the plug 172 and of the interconnect 62 can be deposited in one step. Alternatively, an lntermetalhc can be filled mto the plug 172 and even used as the interconnect 62 With a change in the geometry of the structure, it is possible to deposit the plug mateπal directly onto the upper metal-oxide layer 52. Experiment 8 A prototype sample following the structure of FIG. 2 was grown with the contact layer 170 composed of AlTi 3 . The lower mtermetalhc layer was sputter deposited, rather than by pulsed laser deposition, but the upper mtermetalhc layer was laser deposited. No rapid thermal processing was performed. As shown in the graph of FIG. 13, the room temperature hysteresis curve 180 for the upper mtermetalhc contact should be compared with the corresponding hysteresis curve 182 for an upper platinum contact. This process has not been optimized, and improvements are expected. The expeπence of sputteπng the mtermetalhc layer demonstrated that sputteπng has a wider process window for the deposition than does pulse laser deposiuon. It is believed that the intermetallic more easily forms in stoichiometric ratios with sputtering, and sputtering is a proven production tool in the semiconductor industry. The embodiments described above used NiAl, Ni 3 Al, and AlTi 3 as the intermetallic material. However, a wide range of intermetallic compounds can be used for the barrier material. Other specific examples of intermetallics are NiTi and CoAl. A general family is represented by the compositions AJ3, AB 2 , AB 3 , A 2 B, and A 3 B, where A includes Fe, Cr, Co, Ni, Mn, Mo, and W and where B includes Al, Ti, Cr, Si, Ru, Re. Furthermore, intermetallic compounds include AA' and BB' alloys. Reference is made to the latter referenced patent application to Dhote and Ramesh for a fuller explanation. A particularly promising set of materials for the intermetallic barrier are the silicide intermetallics, particularly intermetallic disilicides such as MoSi 2 and WSi 2 composed of disihcide Of a refractory metal. An exemplary structure is shown in the cross-sectional view of FIG. 14, which is a modification to the embodiment of FIG. 1. However, this embodiment lacks a TiN barrier layer, and a silicide layer 190 directly overlies the polysihcon layer 40. Such a silicide barrier can be combined with the upper intermetalhc barrier 170 of FIG. 12, with that intermetallic being either a silicide or a different intermetallic. Silicon-based intermetalhcs (suicides) have been used in silicon processing, particularly at boundaries between underlying sihcon and overlying metals. A silicide is in general an alloy of a refractory metal and sihcon, but better performance is obtained with stoichiometric or nearly stoichiometric compounds, particularly refractory metal disilicides. Examples of such silicides used in sihcon processing are the disilicides CoSi 2 , TiSi 2 , TaSi 2 , and WSi 2 . Particularly in the embodiments without the TiN baπier layers, the silicide intermetallics offer a reliable interface with the immediately underlying sihcon. In sihcon processing, silicides can be deposited by chemical vapor deposition (CVD), which produces a very conformal coating, even in deep and narrow holes. Alternatively, the disihcide layer may be formed by sputtering a layer of the refractory metal onto sihcon and then performing a rapid thermal anneal or a laser anneal. In practice, the rapid thermal anneahng is performed in two steps, a lower- temperature anneal to produce the monosihcide and a higher-temperature anneal to convert the monosihcide to the disihcide. The monosihcide may be selectively etched more easily than the disilicide. The two annealing temperatures for CoSi 2 are approximately 450° and 700°C, and for TiSi 2 are 680° and 750°C, temperatures consistent with the previously described steps. The laser annealing can be advantageously applied to forming the upper metallic layer by programming the laser positioning. The above described process of annealing a refractory metal and silicon into an intermetallic silicide suggests that the rapid thermal annealing of the lower part of the 5 ferroelectric cell may be fundamentally affecting the laser ablated intermetallic layer. Shindo et al. have disclosed in U.S. Patent 5,449,933 that an aluminum-rich NiAl or NiCrAl alloy can transmit crystallographic orientation from a templating layer to a perovskite layer. Although these alloys are not intermetallic alloys, they are formed of constituents which do form intermetalhcs. 0 Experiment 9 Two prototype test chips were fabricated using alternatively MoSi 2 or WSi 2 as the sihcide layer deposited by pulse laser deposition. The test structure lacked the TiN layer 74 of FIG. 2 with the silicide layer 76 formed directly on the polysilicon layer 72. and no rapid thermal anneahng was performed. The hysteresis loop for the MoSi 2 is shown in FIG. 15 for 5 both a 5V loop and a 3V loop. Fatigue and retention tests were also performed. These results generally show lifetimes similar to those described above for barriers of non-silicon intermetallics, but the polarization levels are substantially lower for sihcide barriers. The results for WSi 2 were similar to those for MoSi 2 . Although the invention has been motivated by the desire for better ferroelectric o memory cells, it is not so limited and may be extended to a number of other apphcations. Similar device geometries are used for membrane switches in piezoelectric electro- micromechanical systems, and for uncooled infrared detetors using lead titanate, lead tantalate, or similar materials. For a intermetalhc barrier layer of NiTi, which is also a shape memory ahoy, a ferroelectric layer integrated on the memory alloy can be used to control the phase 5 transformation of the layer. A ferroelectric cell has many similarities to a high-temperature superconductive junction structure since these superconductors have a perovskite crystal similar to many of the ferroelectrics, and indeed many perovskite superconductors exhibit ferroelectric behavior. High-quality crystahographically oriented perovskite thin films can be grown on metal-oxide o templating layers such as LSCO, bismuth titanate (BTO), and praeseodymium barium copper oxide (PrBCO). Many of these templating materials are layered perovskites rather than the cubic perovskite of LSCO Perovskites have a number of useful electπcal characteπstics that can be utilized in useful devices, which become more useful if they can be integrated onto silicon. The mtermetalhc barπer layer of the invention allows such templating layers, often additionally used as electrodes, to be grown over silicon and other semiconductors Although the above descπbed embodiments have included a perovskite layer sandwiched between two conductive (electrode) metal-oxide layers, other devices have been descπbed having electrodes only at the bottom of a perovskite layer Examples of such devices include magnetoresistive devices, such as spin valves. The invention thus provides a simple and inexpensive method of improving the performance of perosvkite cells acting as electronic devices. The invention also provides several novel compositions and structures for the intermetallic layer around the perovskite cell The vaπous aspects of the invention provide a commercially manufacturable, reliable perovskite cell, especially a ferroelectnc memory cell. Nonetheless, the changes required over the pπor art of minor and are obtainable at low cost.

Claims: W7ι--t is claimed is: 1. A method of fabricating a perovskite cell, comprising the steps of: a first step of depositing a metal-oxide layer upon a substrate at a first temperature; then anneahng said substrate at a second temperature higher than said first temperature; and a second step of depositing a perovskite layer comprising a perovskite material upon said metal-oxide layer. 2. The method of Claim 1, wherein said perovskite material is ferroelectric. 3. The method of Claim 1, wherein second depositing step is performed after said annealing step. 4. The method of Claim 3, wherein said second temperature is sufficiently high and said anneahng is performed for a time sufficiently long to crystallographically orient said metal-oxide layer. 5. The method of Claim 4, wherein said second temperature is at least 750°C. 6. The method of Claim 1 , wherein said substrate comprises a semiconductor material and further including a third step, performed before said first step, of forming an intermetalhc layer over said substrate. 7. The method of Claim 6, wherein said third step includes: depositing over said substrate a metal layer comprising a metal of which said intermetalhc layer is comprised; and heat treating said metal layer to form said intermetallic layer from said metal layer and said substrate. 8. The method of Claim 7, wherein said perovskite mateπal is a ferroelectric and wherein said metal-oxide layer is electπcally conductive to form a lower electrode to said perovskite layer and further comprising a third step of depositing a conductive layer over said perovskite layer to form an upper electrode to said perovskite layer. 9 The method of Claim 9, wherein said second depositing step is performed after said annealing step 10. The method of Claim 8, wherein said anneahng step is performed after said second depositing step and before said third depositing step. 11' The method of Claim 8, wherein said annealing step is performed after said third depositing step 12. The method of Claim 8, wherein said conductive layer formed over said perovskite layer compπses an intermetalhc. 13. The method of Claim 8, wherein said semiconductor mateπal compπses silicon and wherein said mtermetahic layer compπses a sihcide of a refractory metal. 14. The method of Claim 13, wherein said silicide compπses a disihcide of said refractory metal. 15. The method of Claim 13, wherem said mtermetalhc layer is formed directly over said sihcon. 16. The method of Claim 15, wherein said third step of forming said intermetallic layer compπses depositing a metal layer compπsmg said refractory metal on said sihcon and then annealing said metal layer and at least a surface of said sihcon, whereby said sihcide is formed by a reaction between said refractory metal and said sihcon. 17. The method of Claim 16, wherein said silicide comprises a disilicide of said refractory metal. 18. A perovskite cell, comprising: a substrate with a silicon surface portion; a silicide layer comprising silicon and a refractory metal formed over said silicon surface portion; a metal oxide layer formed over said sihcide layer; and a perovskite layer formed over said metal oxide layer. 0 19. The cell of Claim 18, wherein said perovskite layer comprises a ferroelectric and said metal oxide layer is conductive, and further comprising a second conductive metal-oxide layer formed over said perovskite layer. 5 20. The cell of Claim 19, wherein said sihcide comprises a disihcide of said refractory metal. 21. The cell of Claim 19, wherein said sihcide comprises a disUicide of said refractory metal. 0 22. The cell of Claim 18, further comprising an intermetalhc layer formed over said second conductive metal-oxide layer. 23. A perovskite cell, comprising: 5 a substrate; a perovskite layer formed over substrate; an upper metal-oxide electrode layer formed over said perovskite layer; and an upper intermetalhc layer formed over said upper metal-oxide electrode layer. o 24. The perovskite ceh of Claim 23, further comprising: a lower intermetalhc layer formed over said substrate; a lower metal-oxide electrode layer formed over said intermetalhc layer, said perovskite layer being formed over said lower metal-oxide electrode layer. 25. The cell of Claim 24, wherein said lower intermetal c layer is formed directly over a silicon surface portion of said substrate. 26. The cell of Claim 25, wherem said lower intermetalhc layer compπses a disi cide of a refractory metal. 27 The cell of Claim 23, wherein said perovksite layer compπses a ferroelectπc. 28. The cell of Claim 23, wherein said upper intermetal c layer compπses an intermetallic alummide and further compπsing a conductive layer formed over said upper mtermetalhc layer compπsing metallic aluminum.

Inventors: AGGARWAL SANJEEV, DHOTE ANIL M, RAMESH RAMAMOORTHY, AGGARWAL, SANJEEV, DHOTE, ANIL, M., RAMESH, RAMAMOORTHY
Applicants: BELL COMMUNICATIONS RES, BELL COMMUNICATIONS RESEARCH, INC.
Application year: 1998
Main classification: H01L29
IPC codes: H01L21, H01L27