In-system programmable interconnect circuit

Abstract: A programmable interconnect circuit includes multiple input/output cells, each corresponding to an input/output pin, and a global routing resource for routing signals received at the input pins to be output as output signals at output and bi-directional pins. The signals routed in the global routing resource can include multiplexer control signals, clock signals and output enable signals for controlling dynamic signal switching. The global routing resource allows high static routability.

Description: The present invention relates to a programmable interconnect circuit, comprising a plurality of state elements for storing configuration data; a programmable global routing resource for receiving a first plurality of signals to provide a second plurality of signals, said second plurality of signals provided as a result of routing said first plurality of signals through a switch matrix configured according to said configuration data stored in said elements; and a plurality of input/output circuits, each input/output circuit being (a) associated with a pin of said programmable interconnect circuit and (b) being programmable to be an output circuit, an input circuit, or a bi-directional circuit. Programmable interconnect circuits are used in three distinct classes of applications; programmable random signal interconnect (PRSI), programmable data path (PDP) and programmable switch replacement (PSR). In a PRSI application, the programmable interconnect circuit is used at the printed circuit board (PCB) level for programmable signal routing. In this application, the interconnect circuit provides arbitrary signal swapping between integrated circuits of the PCB. Typically, in a PRSI application, the programmable interconnect circuit provides one-to-one pin connections which are statically configured, that is the signal path does not change in response to control input signals. The signals being routed are very often control signals routed between integrated circuits and their signal paths are often changed multiple times throughout the design process. Thus, a desirable programmable interconnect circuit suitable for supporting a PRSI application must have no restrictions on pin-to-pin signal routability. (In a PDP application, the programmable interconnect circuit performs data path transceiver, multiplexer, and register or latch functions. An example of such an application can be found in a microprocessor-based system, in which a 32 bit or 64 bit data bus is "steered" to memory and peripheral systems of various data widths and timing constraints. Such an application requires capabilities for dynamically switching signal routing, data latching and data bus tri-stating. Unlike a PRSI application, however, the signal routing requirements for a PDP application are often formulated early in a design process, so that universal pin-to-pin signal routability is not as critical. In a PDP application, the desirable programmable interconnect circuit provides ample support for control of both dynamic signal routing and timing. It is also desirable to have such support as output enable signals, clock signals and minimisation of the set-up and hold time requirements. Finally, in a PSR application, the programmable interconnect circuits act as solid state replacement and integration switches for mechanical switches and jumpers, which are often used to configure a system board. These switches are often re-set from time to time during a lifetime of the system board. Thus, in a PSR application, the programmable interconnect circuit is required to be re-programmable during the lifetime of the application. A programmable logic device is described in EP 0 584 910 in which two or more programmable logic blocks are interconnected by a programmable switch matrix that includes a programmable input switch matrix and a programmable centralised switch matrix. Each programmable logic block is coupled to a plurality of programmable I/O macrocells by an output switch matrix. Each programmable I/O macrocell is connected to one of a plurality of I/O pins for the programmable logic block. An input microcell may couple an I/O macrocell and the associated I/O pin to the programmable input switch matrix. The programmable input switch matrix provides a uniform treatment of all feedback signals to the programmable centralised switch matrix and thereby simplifies signal routing, provides an improved functionality balance, and improved resource utilisation within the PLD. The output switch matrix roots output signals from a programmable logic block to any one of a multiplicity of I/O macrocells. The output switch matrix and the input switch matrix decouple the programmable logic block and centralised switch matrix from the pin out and the feedback architecture of the PLD. Thus, the output switch matrix and the input switch matrix may be effectively used with a wide variety of programmable interconnect structures and programmable logic block architectures to achieve an enhanced resource utilisation, routing and functionality. A problem with this known arrangement is that the programming of output enable cells is very unflexible, therefore the extent of its application is limited. According to the present invention, there is provided a programmable interconnect circuit of the aforesaid type, characterised in that each I/O circuit is configured to receive from said programmable global resource an output enable signal selected from one of said second plurality of signals; wherein when said I/O circuit is configured as an input circuit, said I/O circuit receives from said associated pin an input signal and provides said input signal to said global routing resource as one of said first plurality of signals, and wherein when said I/O circuit is configured as an output circuit, said I/O circuit selects one of said second plurality of signals as an output signal of said associated I/O pin. Preferably, said first plurality of signals is divided into subgroups of signals, and each I/O circuit receives a pre-determined number of data signals, each data signal being routed from a different subgroup of said first plurality of signals. The silicon architecture of AMDs 3xx/4xx macro array CMOS is described by the paper of Ohm P.Agrawal, Wescon Technical Papers, volume 36 of 17 November 1992, pages 100-106. A major strength of this proposal is identified as being in its architectural simplicity with multiple PAL-like AND -OR-XOR blocks interconnected by multi-tiered switch matrices with fixed, predictable, deterministic delays. This gives a combination of flexibility, programmable connectivity and deterministic speed. A structure for in-system programming of a programmable logic device is described in US 5,237,218. The in-system programming structure disclosed in this patent provides one dedicated pin for in system programming functions. Additional in system programming pins are multiplexed with programming input/output pins used in functional operations. When an enable signal is received at the dedicated pin, the multiplexed pins relinquish their roles as programmable input/output pins to become in system programming pins. A state machine controls the programming steps. In house programming structure can be cascaded. In a preferred embodiment, each circuit receives from said programmable global resource a clock signal selected from one of said second plurality of signals. Furthermore, the input/output circuit may select as said output signal one of said data signals. Preferably, each input/output circuit receives from said programmable global resource a multiplexor control signal selected from one of said second plurality of signals, and said input/output circuit selects said output signal in accordance with the value of said control signal. In a preferred embodiment, the input/output circuit includes a register configured to receive a data value and a clock signal. Preferably, the input/output circuit further comprises a delay element for delaying a rival of the data value with respect to the clock signal. Preferably, the clock signal is selected from the second plurality of signals. In a preferred embodiment, the input/output circuit includes an output buffer having programmable slew rates. Preferably, the state elements include electrically erasable programmable read-only memory elements. The invention will now be described by way of example only, with reference to the accompanying drawings, of which: Figure 1 shows the functional blocks of a programmable interconnect circuit 100, in one embodiment of the present invention; Figure 2 illustrates a pin out of the programmable interconnect circuit 100 of Figure 1 ; Figure 3a is a schematic representation of a global routing pool in a programmable interconnect circuit; Figure 3b is a schematic circuit representing, in a global routing pool of a programmable interconnect circuit, routing of signals received at a input/output pin group; Figure 4 is a schematic diagram of an input/output circuit used in associated with each input/output pin of a programmable interconnect circuit; Figure 5 is a schematic circuit of an adjustable slew rate amplifier; and Figure 6 is a schematic circuit of a programmable delay circuit. As shown in Figure 1, a programmable interconnect circuit 100 is provided as an in-system programmable circuit. In-system programmable circuits are non-volatile programmable circuits, that can be electrically reprogrammed in-place, that is without removal from its operating environment to a programmer circuit. In-system programmable circuits are disclosed in US 5,237,218 and this disclosure incorporated by a reference in its entirety to provide background information with respect to in-system programmable circuits. Functional block 101 , labelled "ISP" represents the control and programming circuits for in-system programming programmable interconnect circuit 100 . In the implementation of programmable interconnect circuit 100 of Figure 1, programmable interconnect circuit 100 is also provided with boundary scan test capability compliant with the IEEE Standard 1149.1 (the "JTAG standard"). The JTAG standard, which is set forth in IEEE Standard Test Access Port and Boundary- Scan Architecture , published by the Institute of Electrical and Electronics Engineers, Inc., (May 1990) is well-known to those in the art. Functional block 105, labelled "JTAG" represents the control and test circuits used in operations under the JTAG standard. Programmable interconnect circuit 100 is an integrated circuit which includes four groups of input/output (I/O) pins 104a, 104b, 104c, and 104d, respectively provided along the four sides of the integrated circuit die. Each I/O pin is associated with an I/O cell circuit, discussed in further detail below, which can be programmed to operate the I/O pin as an input pin, an output pin, or a bidirectional I/O pin with tristate capability. In Figure 2, all I/O cell circuits are represented by functional blocks 103a and 103b, labelled "I/O cells." The signals of I/O cell functional blocks 103a and 103b are interconnected through global routing pool (GRP) 102 (labelled "GRP" in Figure 1). In the present description, to facilitate cross references between figures, like elements in the figures are assigned like reference numerals. Figure 2 illustrates the pin-out of programmable interconnect circuit 100 of Figure 1. A number of power and ground pins (not shown) are provided to programmable interconnect circuit 100 to ensure that adequate and stable power supply voltages and currents are provided to operate programmable interconnect circuit 100. In this implementation, programmable interconnect circuit 100 supports 160 I/O cell circuits. Thus, four groups of I/O pins 104a, 104b, 104c and 104d, each including 40 I/O pins are provided along the four sides programmable interconnect circuit 100's integrated circuit die. In addition, four pins labelled Y 0 , Y 1 , Y 2 and Y 3 are received into programmable interconnect circuit 100 as four "global" clock signals, any one of which can be used to clock the state elements of any I/O cell circuit in programmable interconnect circuit 100. To support in-system programming (ISP) operations and the operations under the JTAG standard, control pins 202a and 202b are provided to support control and program/test data signals. In this embodiment, JTAG and ISP share the serial input signal, serial output signal, the clock signal and the mode/TMS signal. Figure 3a is a schematic representation 300 of global routing pool 102 in programmable interconnect circuit 100. As shown in Figure 3a, an input signal received at an I/O pin of I/O pin group 104a can be routed by GRP 102 as any one of one hundred and sixty output signals 301a (labelled "GRP_A" in Figure 3a). Each signal in signal group 301a is provided to one I/O cell circuit in each of the four I/O pin groups 104a, 104b, 104c and 104d. Likewise, an input signal received at an I/O pin of any of groups 104b, 104c and 104d can be routed by GRP 102 as any one of one hundred and sixty output signals in the corresponding signal group 301b, 301c or 301d (labelled "GRP_B", "GRP_C", and "GRP_D", respectively, in Figure 3a). Similarly, each signal in signal groups 301b, 301c and 301d is provided to one I/O cell circuit in each of the four I/O pin groups 104a, 104b, 104c and 104d. Within each I/O cell circuit, the four signals from signal groups 301a, 301b, 301c and 301d can then be selected internally as the output signal of the I/O cell circuit. In this manner, any signal in at any I/O pin can be routed as the output signal of any I/O pin. Thus, unrestricted pin-to-pin signal routing is achieved. Figure 3a also shows that the signals on one-quarter of the I/O pins, ten from each of I/O pin groups 104a, 104b, 104c and 104d, can each be received as a clock signal and be routed to any of the 160 I/O cell circuits as a clock signal (clock signals 302, labelled "GRP_CLK") for clocking the state elements of that I/O cell circuit. The signals on another forty I/O pins, ten from each of I/O pin groups 104a, 104b, 104c and 104d, can each be received as a multiplexer control signal and be routed to any of the one hundred and sixty I/O cell circuits as a multiplexer control signal (multiplexer control signals 303, labelled "MUX0") for controlling the multiplexing within the I/O cell circuit. Likewise, the signals on another forty I/O pins, ten from each of I/O pin groups 104a, 104b, 104c and 104d, can each be received as a multiplexer control signal and be routed to all one hundred and sixty I/O cell circuits as a multiplexer signal (multiplexer control signals 304, labelled "MUX1") for controlling the multiplexing within the I/O cell circuit. The signals on the remainder one-quarter of the I/O pins, ten from each of I/O pin groups 104a, 104b, 104c and 104d, can each be received as an output enable signal and be routed to any of the 160 I/O cell circuits as an output enable signal (output enable signals 305, labelled "GRP_OE") for enabling the output amplifier of the I/O cell circuit. If any output terminal of GRP 102 is not driven, the output signal at that output terminal is defaulted to '1'. Figure 3b is a schematic circuit 350 representing, in global routing pool 102 of programmable interconnect circuit 100, routing of signals received in I/O pin group 104a as output signals 301a. As shown in Figure 3b, circuit 350 includes an array of 40 X 160 pass or transfer transistors each controlled by a 1-bit memory cell. The 1-bit memory cells are shown in Figure 3b as memory cells 320-(0,0), 320-(1,0), 320-(2,0)... 320-(159,0), 320-(0,1), ..., 320-(159,39), forming a cross bar switch for routing any signal in I/O pin group 104a as any of the signals in signals 301a. These 1-bit memory cells are electrically erasable programmable read-only memory (E 2 PROM) elements, programmable using in-system programming techniques. Thus, global routing pool 102 implements static routing. Other portions of global routing pool 102 can be similarly implemented. Figure 4 is a schematic diagram of input/output (I/O) cell circuit 400 used in association with each I/O pin of programmable interconnect circuit 100. As shown in Figure 4, I/O cell circuit 400 receives four input data signals from GRP 102 at terminals 401, 402, 403 and 404, which are respectively signals selected from signal groups 301a, 301b, 301c and 301d. I/O cell circuit 400 also receives from GRP 102 (i) an output enable signal at terminal 421, which is an output enable signal selected from output enable signals 305 (GRP_OE), (ii) a clock signal at terminal 433, which is a signal selected from clock signals 302 (GRP_CLK), and (iii) two multiplexer control signals at terminal 405 and 406, which are signals selected from multiplexer control signals 303 (MUX0) and multiplexer control signals 304 (MUX1) respectively. I/O cell circuit 400 also receives global clock signals Y 0 , Y 1 , Y 2 and Y 3 at terminals 434, 435, 436 and 437 respectively. If I/O cell circuit 400 is configured as an output cell, or if the output signal is to be enabled by the output enable signal at terminal 421, multiplexers 441 and 442 are appropriately selected to enable output amplifier 426 by providing the output enable signal at terminal 424. Gate 420 allows a test output enable signal (labelled "TOE") to globally disable all I/O pins. The multiplexer control signals at terminals 405 and 406 are used to select one of the four input data signals 401, 402, 403 and 404 at 4-1 multiplexer 411. The signal output from multiplexer 411 is provided at terminal 412. Multiplexers 407 and 409 are provided to allow swapping of the multiplexer control signals at terminals 405 and 406, if desired. Multiplexers 408 and 409 select the signal polarity of the multiplexer control signals at multiplexer 411. The signal at terminal 412 can be provided through amplifier 426 as I/O cell circuit 400's output signal at terminal 425. The output signal at terminal 425 is synchronous, if the signal at terminal 412 is latched into register 416, through multiplexer 440 and delay element 414. Otherwise, the output signal at terminal 425 is asynchronous, being selected by multiplexer 418 from terminal 412. Multiplexer 418 is a 4-1 multiplexer, selecting both the polarity and the synchronicity of the output signal at terminal 425. The output signal at terminal 425 is provided pull-up if so configured in multiplexer 444. In the implementation shown in Figure 4, output amplifier 426 can be programmed to have one of two slew rates by setting multiplexer 445. I/O cell circuit 400 can also be configured as an input cell by properly disabling output amplifier 426 by appropriately selecting multiplexer 441 and 442 to ensure a negated output enable signal at terminal 424. The input signal at terminal 425 is provided by multiplexer 438 at terminal 439 to GRP 102, either synchronously or asynchronously. The asynchronous signal is selected from terminal 425 directly. The synchronous signal is provided by register 416 which receives, in this instance, the input signal at terminal 425 delayed by delay elements 429 and 414. When I/O cell circuit 400 is used as an input cell, multiplexer 440 is set to select the signal at terminal 413. Register 416 is controlled by a clock signal at terminal 430, which is provided by 5-1 multiplexer selecting one of the clock signals at terminals 433-437. Multiplexer 431 selects controls whether register 416 latches at a rising edge or a falling edge. To ensure hold time is minimized, delay elements 414 and 429 are provided to achieve proper timing relationship between the data signal at terminal 415 and the clock signal at terminal 430. Multiplexer 443 selects whether register 416 is to operate under register mode (i.e. edge triggered) or latch mode (i.e. transparent). Multiplexers 407-410, 418, 431-432, 438, and 440-445 are configured using in-system programming techniques, the selection signals of these multiplexers being stored in configuration registers of the E 2 PROM technology discussed above. As discussed above, the slew rate of output amplifier 426 can be programmed. Figure 5 is a schematic circuit of output amplifier 426. As shown in Figure 5, output amplifier 426 includes buffers 501, 502 and 503, and configuration circuit 505, which includes multiplexer 445 and a configuration register. Buffers 501 and 502 drives buffer 503 in parallel. Buffer 501, which is enabled by storing an appropriate value in the configuration register of configuration circuit 505, is designed to have a faster rise time than buffer 502. Thus, when buffer 501 is enabled, the output signal of buffer 503 at terminal 425 has a faster rise time. As mentioned above, hold time is minimized by inserting delay elements 429 and 414. Figure 6 is a schematic circuit of programmable delay circuit 414 of I/O circuit 400. As shown in Figure 6, delay element 414, which is placed across terminals 460 and 415, includes two signal paths 603 and 604, controlled respectively by pass or transfer transistors 605 and 606. Transfer transistors 605 and 606 are enabled by configuration registers 601 and 602 of the above-mentioned E 2 PROM technology and are programmed using in-system programming techniques. The longer signal path 603 is enabled when the clock signal selected at multiplexer 432 is the clock signal at terminal 433, which is routed by GRP 102. However, if the clock signal selected at multiplexer 432 is a global clock, i.e. any of the clock signals at terminals 434-437, the shorter signal path 604 is selected. Delay element 429 can be likewise implemented. The above detailed description is provided to illustrate specific embodiments of the present invention. Numerous variations and modifications within the scope of the present invention as set forth in the appended claims are possible.

Claims: A programmable interconnect circuit, comprising; a plurality of state elements (220) for storing configuration data; a programmable global routing resource (102) for receiving a first plurality of signals to provide a second plurality of signals, said second plurality of signals provided as a result of routing said first plurality of signals through a switch matrix configured according to said configuration data stored in said elements; and a plurality of input/output circuits (103), each input/output circuit being associated with a pin of said programmable interconnect circuit, and being programmable to be an output circuit, an input circuit, of a bi-directional circuit, characterised in that said input/output circuits are configured to receive from said programmable global resource an output enable signal selected from one of said second plurality of signals; wherein when said input/output circuit is configured as an input circuit, said input/output circuit receives from said associated pin an input signal and provides said input signal to said global routing resource as one of said first plurality of signals, and wherein when said I/O circuit is configured as an output circuit, said input/output circuit selects one of said second plurality of signals as an output signal of said associated input/output pin. A programmable interconnect circuit according to claim 1 , wherein said first plurality of signals is divided into subgroups of signals; and each input/output circuit receives a predetermined number of data signals, each data signal being routed from a different subgroup by said first plurality of signals. A programmable interconnect circuit according to claim 1 or claim 2 , wherein each circuit receives from said programmable global resource a clock signal selected from one of said second plurality of signals. A programmable interconnect circuit according to claim 2 , wherein said input/output circuit selects as said output signal one of said data signals. A programmable interconnect circuit according to claim 4 , wherein each input/output circuit receives from said programmable global resource a multiplexer control signal selected from one of said second plurality of signals, and wherein said input/output circuit selects said output signal in accordance with the value of said control signal. A programmable interconnect circuit according to claim 1 , wherein said input/output circuit includes a register configured to receive a data value and a clock signal. A programmable interconnect circuit according to claim 6, wherein said input/output circuit further comprises a delay element for delaying arrival of said data value with respect to said clock signal. A programmable interconnect circuit according to claim 7 , wherein said clock signal is selected from said second plurality of signals. A programmable interconnect circuit according to claim 7 or claim 8, wherein said clock signal is selected from one of said second plurality of signals and a clock signal received at a pin of said programmable interconnect circuit. A programmable interconnect circuit according to and of claims 7 to 9 , wherein said input/output circuit further comprises a delay element for delaying arrival of said data value with respect to said clock signal, said delay element having a delay value selectable in accordance with whether said clock signal is selected from one of said second plurality of signals or a clock signal received at a pin of said programmable interconnect circuit. A programmable interconnect circuit according to any of claims 7 to 10 , wherein said register receives a data value selected form one of said second plurality of signals or said first plurality of signals. A programmable interconnect circuit according to claim 11 , wherein said input/output circuit further comprises a delay element for delaying arrival of said data value with respect to said clock signal, wherein said delay element has a delay value selected according to whether said data value is selected from one of said second plurality of signals or said first plurality of signals. A programmable interconnect circuit according to claim 1 , wherein said input/output circuit includes an output buffer having programmable slew rates. A programmable interconnect circuit according to claim 1, wherein said state elements include electrically erasable programmable read-only memory elements. A programmable interconnect circuit according to claim 1, wherein said state elements are in-system programmable.

Inventors: FARMER JEROME CONNELLY, KOPEC STANLEY J JR, TSUI CYRUS Y, WANG CHENG-YUAN MICHAEL, FARMER, JEROME CONNELLY, KOPEC, STANLEY J., JR., TSUI, CYRUS Y., WANG, CHENG-YUAN MICHAEL
Applicants: LATTICE SEMICONDUCTOR CORP, LATTICE SEMICONDUCTOR CORPORATION
Application year: 1998
Main classification: H03K19
IPC codes: H03K19