AUTOMATED VALIDATION AND VERIFICATION OF COMPUTER SOFTWARE

Abstract: A method and apparatus for automating validation and verification of computer software confirms that during a test execution of the software, all lines of code are executed and all branches in the software are taken or not taken at least once. The computer software to be tested is compiled and a link map is generated. After compilation of the code, it is run in a test fixture to test all the design functions. During this test execution, a monitoring process is performed which documents which lines of code have been executed and when and when not certain branches were taken. Two maps are generated which indicate what instruction branches were taken and were not taken. A comparison is then made between the link map originally generated and the two branch maps generated to determine what lines of code were executed, whether each branch was taken at least once, and whether a branch was not taken.

Description: AUTOMATED VALIDATION AND VERIFICATION OF COMPUTER SOFTWARE FIELD OF THE INVENTION This invention relates to automated validation and verification of computer software. BACKGROUND OF THE INVENTION In the past, the control surfaces of aircraft were controlled through a direct mechanical connection between the pilot and the control services. This control was either provided by cables and pulleys or though various hydraulic systems. More and more often, modern aircraft are being operated through computer-assisted systems. In a fly-by- wire system, the pilot movements of the control instruments such as the foot pedal or yolk are translated into an electrical signal which are then transmitted to electric actuators which move the control services. These black boxes which convert movements into electrical signals have software which is critical to the safety of the aircraft. In order to be sure that these new computer systems operate properly on an aircraft, the Federal Aviation Administration (FAA) requires that all software used in a critical system be FAA certified. For FAA certification, software is developed and tested according to one of five levels: A, B, C, D, or E. Levels D and E require very little analysis and do not require much in order to show compliance. Level C certification is slightly more difficult. At this level of development, software must be traceable to the requirements and test procedures, and the test results must be correlated to the system requirements. This level is mostly concerned with the process of software development. Level be certification requires that a demonstration of software and implementation be provided such that it can be shown that there is no dead code (unreachable or unexecutable during the test process), in the system. The dead code check is performed from a source code perspective and the test results need to show that each source line of executable code was reached during the test. Level A certification builds upon level B and places additional requirements on the path coverage testing of the software to be performed in an embedded computer system. Where level B testing only needs to show that every source line was executed and every logic path taken, level A testing must certify that every machine instruction in the object code is executed. In addition, it must be shown that every logic path decision through the software has been exercised exhaustively during the test. The difference between level B and level A testing is most apparent in the following example: 001 - IF (A. and. B). OR) (C. and. D)) 002 - THEN set E to X 003 - set E to Y For level B testing, it is necessary to show two results: ) that lines 001, 002, and 003 are executed, and 2) that lines 001 and 003 were executed while 002 was not. For level A testing it is necessary to show that each of the possible combinations that would make the conditional of line 001 true or false. Level B testing may be performed on the source code level. Level A must be performed on the machine code level. Since each source line of executable code is translated into one or more machine instructions by the compiler and linker, a run-time tool that could verify that each machine instruction conditional branch at least once branch and at least once did not branch will go a long way towards automating the level A certification testing. Currently, level A testing is performed on aircraft-critical computer software by people comparing the results of a test run of the computer program which documents each line of code that was executed, with a link map which is generated at the time the source code is compiled. The person analyzing the code must first determine that every line of code was executed, and that each branch was both at one point taken and then not taken. Because of the amount of time it takes an individual or group of individuals to analyze computer code, especially when an aircraft system is becoming more voluminous and sophisticated, it would be a great advantage to automate this process. SUMMARY OF THE INVENTION The present invention discloses a method and apparatus for automatic validation and verification of computer software. The software to be tested is first retrieved from a software library and compiled from source code into object code and a link map is generated which lists all the lines of code in a software program. The object code is then embedded in the computer electronics. The computer electronics are tested by means of a test fixture for all the functions that they are designed to perform. During the testing of the computer electronics, the execution of the object code is monitored. The main function of this monitoring is to provide two separate instruction address maps which provide a history of the lines of object code which have been executed. The first map contains all instruction addresses for the software program where the software code did not branch off but instead executed lines of code with consecutive addresses. A second address map contains all instruction addresses for lines of code which a branch is taken and lines of code elsewhere in the program are then executed. Once the first and second maps are generated, they are then compared with the link map which was originally created to first determine if every line of code in the program was executed. For class A testing, a determination is then made as to whether every branch in the program was taken at least once and then not taken at least once. These results are then provided in a report which is output from the system. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 discloses a block diagram of the automated validation and verification of computer software system. Figure 2 discloses a flow chart of the monitoring of the software execution. Figure 3 discloses a flow chart of the comparison of the branch taken and branch not taken address maps with the link map. DESCRIPTION OF THE PREFERRED EMBODIMENTS Disclosed in Figure 1 is a block diagram showing the system configuration for the automated validation and verification of software apparatus. Software which is to be tested is initially stored in a source code and software library 12. This source code is retrieved from the source code and software library 12 by the compile link apparatus 14. This apparatus compiles the source code and outputs object code to the avionics processor 16 while also generating a link map which provides a listing of all of the lines of code in the software as well as all the links for all loops which are part of the software. The avionics processor 16 is the black box which is installed in an aircraft and provides the translation of the pilots' movements on the control sticks and instruments and translates these movements into electrical signals which are then provided to electronic actuators which then move the control services. One skilled in the art would realize that the use of the avionics processor in the present embodiment is merely the preferred embodiment; but however, any type of electronics which employ computer software can be tested in the present system. Once the object code is embedded in the avionics processor 16, a test site environment 18 then runs the processor through all its design functions. The purpose of this test is to determine whether the processor can perform all the functions it is supposed to. During the testing of the avionics processor 16, the monitoring apparatus 20 tracks the execution of each line of code in the avionics processor and generates two separate types of address maps. One map is a branch taken address map and the other is a branch not taken address map. These maps list the instructions in which, when reading consecutive instructions executed whether lines of object code were executed elsewhere in the program or whether lines of object code were executed in consecutive order. The detailed operation of the monitoring apparatus will be described in greater detail below. Both the branch taken address map and the branch not taken address map is then transmitted to the analysis apparatus 22. The analysis apparatus 22 also retrieves the link map originally generated by the compile link apparatus 14 and through a detailed comparison process with both the branch taken and branch not taken map provides a detailed analysis of how the object code was executed in the avionics processor. The purpose of the present system is to provide both level A and level B testing of software as required under Federal Aviation Administration (FAA) regulations. Level B certification requires that a demonstration of the software implementation be provided such that it can be shown that there is no dead code (unreachable, or unexecuted during the test process) in the system. This dead code check is performed from a source code perspective and the test results need to show that each source line of executable code was reached during the test. Level A certification builds upon level B and puts additional requirements on the paths coverage testing of the software to be performed on the embedded system. While Level B testing only needs to show that every source line was executed and every logic path taken, level A testing must verify that each machine instruction in the object code is executed. In addition, it must show that every logic path decision through the software has been exercised exhaustively during the test. This means that when executing instructions which require a decision as to whether to continue to the next instruction or go somewhere else in the program, it must be shown that both choices were taken at least once. Figure 2 discloses a flow chart which describes the operation of the monitoring apparatus 20. As discussed above, the monitoring apparatus provides the branch taken and branch not taken address maps to be provided to the analysis apparatus 22. In operation, while the object code is being executed in the avionics processor 16, the monitoring apparatus 20 receives the address of each line of code that is executed at step 40. Once the address is received at step 42, this current address is stored in memory. The current address is also stored in an interrupt address handler which is used in the case the operation of the avionics processor 16 is interrupted and the monitoring apparatus can then receive from the same spot once the avionics processor begins normal operations. At step 146 an inquiry is then made as to whether an interrupt signal has been received. If not, at step 48, the address of the previous instruction executed is retrieved from memory. At step 50, a comparison of addresses is then made and the question is asked whether the current address is more than two greater than the previous address. An answer greater than two would indicate that the address instructions are not being executed consecutively and that the previous address was a decision instruction and that an instruction was executed which is remote from the previous instruction address. At step 56 if the current address is greater than two more than the previous address, a branch taken bit is set for the previous address and then the previous instruction address is placed in the branch taken map. If the current address is not more than two greater than the previous address, then it is clear that a branch is not taken and the instructions were executed consecutively. At step 52, a bit is set for the previous address for branch not taken. At this point the instruction address is put in the branch not taken map. At step 60 the completed branch taken map and branch not taken map are transmitted to the analysis apparatus 22. Figure 3 discloses a flow chart which describes the operation of the analysis apparatus 22.

Claims: CLAIMS 1. A method for verifying that a method for automated validation and verification of computer software comprising the steps of: providing the software program in source code form and compiling the source code to object code and generating a link map; executing the object code in the manner such that all functions of the software program are executed; monitoring the execution of the object code to generate first and second address maps, where the first map contains all instruction addresses for execution of the software program where the branch is not taken, and the second map contains all instruction addresses for the execution of the software program where the branch is taken; comparing the link map with the first and second address map to determine that all the lines of code were executed, and identify lines of code which were not executed. 2. The method for automated validation and verification of computer software of claim 1 wherein the step of comparing the link map with the first and second address maps further comprises the steps of determining that for certain instruction addresses both the branch was taken and the branch was not taken. 3. The method for automated validation and verification of computer software of claim 1 further comprising the steps of comparing the address of the current instruction being executed with the address of the previous instruction, where if the current instruction is more than two addresses greater than the previous address, placing the previous address in the second branch map, and if the current address is less than two greater than the previous address, placing the previous address in the first map. 4. The method of automated validation and verification of computer software of claim 1 wherein asynchronous interrupts are accounted for during execution of the object code. 5. An apparatus for automatic validating and verifying of computer software comprising: means to compile the software program and generate a link map; means to execute the software program so that functions of the software program are fully executed; means to monitor the execution of the software program and to generate first and second address maps, first address map containing all instruction addresses for execution of the software program when a branch is not taken and the second address map containing all the instruction addresses for execution of the software program when a branch is taken; and means to compare the link map with the first and second address map to determine whether all lines of code in the software code have been executed, and whether all the branches have been taken at least once in the computer software and whether all the branches have not been taken at least once. 6. The apparatus for automated validation and verification of computer software of claim 1 wherein the means to execute the software program is a test fixture. 7. The apparatus for automated validation and verification of computer software of claim 5 further including means during the code execution to account for asynchronus interrupts.

Inventors: GOOSSEN EMRAY R, LIPPITT CARL E, SHEMA DAVID K, GOOSSEN, EMRAY, R., LIPPITT, CARL, E., SHEMA, DAVID, K.
Applicants: HONEYWELL INC, HONEYWELL INC.
Application year: 1998
Main classification: G06F11
IPC codes: G06F11