MANUFACTURE OF A SEMICONDUCTOR DEVICE WITH A POLY-EMITTER BIPOLAR TRANSISTOR

Abstract: A method of manufacturing a semiconductor device with a bipolar transistor, by which method consecutively: a surface (9) of a silicon body (1, 2) is provided with a first layer of silicon oxide (20) by means of oxidation, a base zone (21) is formed by means of ion implantation, a second layer of silicon oxide (22) is formed on the first layer of silicon oxide by means of deposition, a window (26) is formed in the two layers of silicon oxide, within which window the surface of the silicon body is exposed, a layer of polycrystalline silicon (28) is deposited on the second layer of silicon oxide and in the window, and an emitter zone (29) is formed in the base zone through diffusion of a dopant from the layer of polycrystalline silicon. A protective top layer (23) which is resistant to a cleaning bath containing HF is provided on the second layer of silicon oxide before the layer of polycrystalline silicon is deposited. Thus a usual HF dip can be carried out before the layer of polycrystalline silicon is deposited, without the bipolar transistors in an integrated circuit exhibiting strongly differing electrical properties as a result of this.

Description: Manufacture of a semiconductor device with a poly-emitter bipolar transistor The invention relates to a method of manufacturing a semiconductor device with a bipolar transistor, by which method consecutively: - a surface of a silicon body is provided with a first layer of silicon oxide by means of oxidation, - a base zone is formed by means of ion implantation, - a second layer of silicon oxide is formed on the first layer of silicon oxide by means of deposition, - a window is formed in the two layers of silicon oxide, within which window the surface of the silicon body is exposed, - a layer of polycrystalline silicon is deposited on the second layer of silicon oxide and in the window, .and - an emitter zone is formed in the base zone through diffusion of a dopant from the layer of polycrystalline silicon. The method is particularly suitable for being combined with methods for the manufacture of semiconductor devices, i.e. integrated circuits, comprising MOS transistors. Bipolar transistors may then be included in these MOS circuits through the addition of no more than a few process steps. The base zone of the bipolar transistor is formed through implantation of ions of a dopant in the method. This implantation is carried out through the first layer of silicon oxide. This silicon oxide layer, which is formed through oxidation of silicon, can be formed with an accurately defined thickness. The base zone formed by implantation accordingly has an accurately defined depth. If the semiconductor device comprises very many bipolar transistors, as is usual, the bases of all these transistors will have one uniform depth. The emitter of the bipolar transistor is formed through diffusion of a dopant from the layer of polycrystalline silicon which was provided in the window. This layer may be provided with the dopant during the deposition or after, for example through implantation of ions of the relevant dopant. The second layer of silicon oxide ensures that a capacitor having only a low capacitance value is formed between the layer of polycrystalline silicon lying on said second layer of silicon oxide and the base zone, so that the transistor is suitable for processing signals of high frequency. A method of the kind mentioned in the opening paragraph is known from US patent no. 5,171,702, wherein the second layer of silicon oxide is a layer deposited from a vapor comprising tetraethoxysil.ane (TEOS). The layer of polycrystalline silicon is deposited in the window -and directly on the second layer of silicon oxide. The window is etched in a plasma formed in CHF 3 , C 2 F 6 , and He, in which mixture silicon oxide can be etched selectively with respect to the monocrystalline silicon of the silicon body. It is found in practice in the manufacture of integrated circuits which comprise many bipolar transistors thus m-anufactured that the bipolar transistors in such a circuit sometimes exhibit strongly differing properties. In particular, signals of high frequencies may be differently amplified by the individual transistors. The invention has for its object to counteract this disadvantage. According to the invention, the method is for this purpose ch-aracterized in that a protective top layer which is resistant to a cleaning bath containing HF is provided on the second layer of silicon oxide before the layer of polycrystalline silicon is deposited. Before the layer of polycrystalline silicon is deposited, a usual "HF dip" is carried out in practice, i.e. a short etching treatment in an etching bath containing HF. This is done for the purpose of removing impurities and oxide remnants which may be left behind on the silicon after the process of etching of the window into the first .and second layers of silicon oxide. It is found, however, that the deposited second layer of silicon oxide may be strongly attacked locally, especially if it was deposited from a vapor of tetraethoxysilane, owing to such a cleaning treatment. The layer may subsequently show major local variations in thickness. The capacitors formed between the polycrystalline silicon and the base zones, with the second layer of silicon oxide forming the dielectric, may thus have different capacitance values for individual transistors. Signals of high frequency may accordingly be given different gains. The use of the protective top layer prevents the second layer of silicon oxide from being locally attacked during the HF dip. It is found in practice that said differences in properties of the individual bipolar transistors in the integrated circuit are strongly reduced by the use of said top layer. The top layer may be provided on the second layer of silicon oxide after the window has been etched into the layer, but preferably the top layer is provided on the second layer of silicon oxide before the window is formed. The window is then formed in the two layers of silicon oxide .and in the top layer. A simple method is obtained thereby. A material usual in semiconductor technology may be used for the top layer such as, for example, silicon nitride or amorphous or polycrystalline silicon. Preferably, a layer of a hydrophilic material is deposited as the top layer. If a hydrophobic top layer is used, such as a layer of amorphous or polycrystalline silicon, it is found that a comparatively high contact resistance may arise between the layer of polycrystalline silicon and the emitter zone in some transistors of an integrated circuit. The result is that signals of low frequency may then be amplified differently by the various transistors. This is prevented when a hydrophilic top layer is used. The silicon body is rinsed with water after the HF dip. Some water with which the silicon body was rinsed after the HF dip may remain behind on the hydrophilic silicon oxide wall of the window. If a hydrophobic top layer is used, the water on the wall can flow down along the top layer during drying, but this is impossible with the use of a hydrophobic top layer, and water may remain behind on the wall. The presence of water on the wall of the window renders it possible for the silicon to oxidize within the window during the deposition of the polycrystalline silicon, which in fact is carried out at an elevated temperature. A thin layer of silicon oxide may thus be created between polycrystalline silicon and the emitter zone. Preferably, a layer of silicon oxynitride is deposited as the top layer. A layer of silicon oxynitride is hydrophilic. In addition, such a layer does not cause problems during etching of the window and during etching of the layer of polycrystalline silicon into a pattern. The window may be etched in a plasma which etches both the top layer of silicon oxynitride and the two layers of silicon oxide highly selectively with respect to silicon, so that the silicon within the window is practically not attacked during etching of the window. Patterning of the layer of polycrystalline silicon by etching, whereby the connection electrode of the emitter is formed, may be carried out such that the polycrystalline silicon and the silicon oxynitride are etched highly selectively with respect to silicon oxide in one -and the same plasma etching process. The second layer of silicon oxide is practically not attacked during patterning of the layer of polycrystalline silicon. The invention will be explained in more detail below by way of example with reference to a drawing, in which: Figs. 1 to 5 diagrammatically and in cross-section show a few stages in the manufacture of a semiconductor device for which the method according to the invention is used. Figs. 1 to 5 diagrammatically and in cross-section show a few stages in the manufacture of a semiconductor device, an integrated circuit with NMOS and PMOS transistors, the method according to the invention being used for including bipolar transistors in this circuit. Although such a circuit may comprise a very large number of such transistors, the manufacture of only one of each of these transistors is shown to keep the Figure clew. The present example starts with the situation as shown in Fig. 1. An n- type layer 2 comparatively weakly doped with approximately 8*10 15 atoms per cc was epitaxially grown on a wafer of silicon 1 in a usual manner. An n-type buried layer 3 comparatively strongly doped with approximately 10 19 atoms per cc was formed in a usual manner where the bipolar transistor is to be manufactured. A p-type region 4 with a doping concentration of approximately 5*10 16 atoms per cc was provided through ion implantation where the NMOS transistor is to be formed. The regions 5, 6, .and 7 where the NMOS, the PMOS, and the bipolar transistor are to be formed, respectively, are insulated from one another by field insulation regions 8 in a usual manner. A layer of gate oxide 10 with a thickness of approximately 12 nm is formed on the surface 9 of the active regions 5, 6 and 7. Then a layer of polycrystalline silicon is deposited in a usual manner, in which a gate electrode 11 for the NMOS transistor and a gate electrode 12 for the PMOS transistor are formed. Comparatively weakly doped n- type source and drain zones 13 and p-type source and drain zones 14 are formed by means of the gate electrodes 11 and 12 through ion implantation with approximately 5*10 17 atoms per cc. The gate electrodes 11 and 12 are then provided with insulation strips (spacers) 15 of silicon oxide at their lateral sides in a usual manner. The surface 9 on the active regions 5, 6, and 7 mixed to the gate electrodes 11 and 12 with their spacers 15 is exposed during this. Finally, comparatively strongly doped connection zones are formed by ion implantation with approximately 10 19 atoms per cc; these are n-type zones 16 for the NMOS tr-ansistor. Fig. 1 shows the stage in which the p-type connection zones 17 for the PMOS transistors and the p-type connection zones 18 for the bipolar transistor are simultaneously formed. The active region for the NMOS transistor is covered with a photoresist mask 19 for this purpose. The same mask 19 .also covers that portion of the active region 7 where the base zone 20 of the bipolar transistor is to be formed. The next process step for manufacturing the bipol.ar transistor is the removal of the photoresist mask 19. Then a first layer 20 of silicon oxide with a thickness of 12 nm is formed by oxidation of silicon. The base zone 21 of the bipol.ar transistor is subsequently formed by means of ion implantation through the layer 20. For this purpose, approximately 4*10 13 p-type ions per cm 2 , boron ions in this example, are implanted into all active regions 5, 6, and 7 without masking. In the exposed zones 16, 17, and 18, which are strongly doped, the doping level practically does not change. The base zone 21 is formed between the connection zones 18. This leads to the situation as shown in Fig. 2. The first layer of silicon oxide 20 which is formed by oxidation of silicon can be formed to an accurately defined thickness. The base zone 21 formed by implantation as a result has an accurately defined depth. The depth of the base zone 21 of each and every bipolar transistor in the circuit will accordingly be the s.ame. Subsequently, as shown in Fig. 3, an approximately 100 nm thick second layer of silicon oxide 22 provided with an approximately 30 nm thick top layer 23 is deposited. A photoresist mask 24 with an opening 25 where the emitter zone of the bipolar transistor is to be formed is provided on the former layers in a usual manner. A window 26, within which the surface 9 of the silicon body is exposed, is etched into the layers 20 and 22 of silicon oxide and into the top layer 23 by means of an etching plasma. The window 26 has a wall 27 bounded by the layers 20 and 22 of silicon oxide. Then, as shown in Fig. 4, a layer of polycrystalline silicon 28 is deposited on the top layer 23, on the second insulating layer 22, and in the window 26. This layer is provided with an n-type dopant in that during the deposition a gaseous compound of the dopant is conducted into the reaction chamber where the deposition takes place, or in that ions of the dopant are implanted into the layer after the deposition. In the present example, approximately 5*10 15 arsenic ions per cm 2 are implanted into the layer of polycrystalline silicon. Then an emitter zone 29 is formed in the base zone 21 through diffusion of this dopant from the layer of polycrystalline silicon 28. Finally, an emitter electrode 30 is formed in the layer of polycrystalline silicon 28. During this, the top layer 23 is also removed from the second layer of silicon oxide 22 next to the emitter electrode. The use of the two layers of silicon oxide 20 and 22 and the top layer 23 achieves that a capacitor having only a low capacitance value is formed between the emitter electrode 30 and the base zone 21. The transistor is accordingly suitable for processing signals of high frequency. The protective top layer 23 is provided on the second layer of silicon oxide 22. This top layer is resistant to a cleaning bath containing HF. It is achieved thereby that bipolar transistors have practically identical electrical properties in the case of a manufacture of integrated circuits which contain many such bipolar transistors. In particular, signals having high frequencies can be amplified to the same extent by the individual transistors. Before the layer of polycrystalline silicon 28 is deposited, a usual HF dip is carried out, i.e. a short etching treatment in an etching bath containing HF, for example 1 to 5% of HF in water. This is done for the purpose of removing impurities and oxide remnants which remain on the silicon after the process of etching of the window 26. It is found that a deposited layer of silicon oxide, in particul-ar if it was deposited from a vapor of tetraethoxysilane, may be strongly attacked locally by such a cleaning treatment. The layer 22 could exhibit major local thickness variations if the protective top layer 23 were not used. Thickness differences of 30% were measured in practice. The capacitors formed between the polycrystalline silicon and the base zones may have different capacitance values for different transistors as a result of this. The differences mentioned earlier may be caused thereby. The use of the protective top layer 23 prevents the second layer of silicon oxide from being attacked locally during the HF dip. It is found that said differences in properties among the individual bipolar transistors in the integrated circuit are strongly reduced thereby. Without the protective layer 23, moreover, pinholes could be formed in the second layer of silicon oxide 22 during die HF dip. These pinholes could even become filled up with the polycrystalline silicon subsequently deposited on this layer, so that short- circuits would arise in the semiconductor device. Said local thickness variations in the second layer of silicon oxide 22 could also have the result that capacitors having this layer as their dielectric and formed elsewhere in the semiconductor device have different capacitance values. Such capacitors are formed, for example, by the gate electrodes 11 and 12 and aluminum tracks to be provided on the second layer of silicon oxide 22. The top layer 23 may be formed on the second layer of silicon oxide after the window 26 has been etched into the layer 22, but preferably the top layer 23, as shown in the Figures, is provided on the second layer of silicon oxide 22 before the window 26 is formed. The window 26 in that case is formed in the two layers silicon oxide 20 and 22 and in the top layer 23. A simple method is thus obtained. A layer of a material usual in semiconductor technology may be used for the top layer 23, for example, silicon nitride or .amorphous or polycrystalline silicon. Preferably, a layer of a hydrophilic material is deposited as the top layer 23. If a hydrophobic top layer were used, such as a layer of amorphous or polycrystalline silicon, it is found that a comparatively great contact resistance can arise between the layer of polycrystalline silicon and the emitter zone in some transistors of an integrated circuit. Signals of low frequency may also be differently amplified by the individual transistors as a result of this. Differences in gain by a factor 2 were found here. This is prevented through the use of a hydrophilic top layer. The silicon body is rinsed with water after the HF dip. Some water with which the silicon body was rinsed after the HF dip may remain behind on the hydrophilic silicon oxide wall 27 of the window 26. If a hydrophilic top layer is used, the water on the wall is capable of flowing off via the top layer, which is not possible in the case of a hydrophobic top layer, where water may remain behind on the wall. The presence of water on the wall of the window enables the silicon to oxidize inside the window during the deposition of the layer of polycrystalline silicon 28, which deposition is carried out at an elevated temperature. A thin layer of silicon oxide may thus arise between the polycrystalline silicon and the emitter zone. Preferably, a layer of silicon oxynitride is deposited as the top layer 23. A layer of silicon oxynitride is hydrophilic. In addition, such a layer does not cause any problems during etching of the window 26 and during etching of the emitter electrode 30 into the layer of polycrystalline silicon 28. The window 26 may be etched in a plasma formed in a gas mixture comprising Ar, CF 4 and CHF 3 , which mixture etches both the top layer 23 of silicon oxynitride and the two layers of silicon oxide 20 and 22 highly selectively with respect to silicon, so that the silicon inside the window 26 is practically not attacked during etching of the window 26. Etching of the emitter electrode 30 into the layer of polycrystalline silicon 28 may be carried out in a plasma formed in a gas mixture comprising Cl and He, in which the polycrystalline silicon 28 and the silicon oxynitride 23 are etched highly selectively with respect to silicon oxide. The second layer of silicon oxide 22 is practically not attacked during this.

Claims: Claims: 1. A method of m-anufacturing a semiconductor device with a bipolar transistor, by which method consecutively: - a surface of a silicon body is provided with a first layer of silicon oxide by means of oxidation, - a base zone is formed by means of ion implantation, - a second layer of silicon oxide is formed on the first layer of silicon oxide by means of deposition, - a window is formed in the two layers of silicon oxide, within which window the surface of the silicon body is exposed, - a layer of polycrystalline silicon is deposited on the second layer of silicon oxide and in the window, and - an emitter zone is formed in the base zone through diffusion of a dopant from the layer of polycrystalline silicon, characterized in that a protective top layer which is resistant to a cleaning bath containing HF is provided on the second layer of silicon oxide before the layer of polycrystalline silicon is deposited. 2. A method as claimed in claim 1, characterized in that the top layer is provided on the second layer of silicon oxide before the window is formed, and in that the window is formed in the two layers of silicon oxide and in the top layer. 3. A method as claimed in claim 1 or 2, characterized in that a layer of a hydrophilic material is deposited as the top layer. 4. A method as claimed in claim 3, characterized in that a layer of silicon oxynitride is deposited as the top layer.

Inventors: MURPHY WILLIAM MARK, PETERS W C M, POSTMA FOKKE, VAN DER MEER HENDRIK HUBERTUS, MURPHY, WILLIAM, MARK, PETERS, W., C., M., POSTMA, FOKKE, VAN DER MEER, HENDRIK, HUBERTUS
Applicants: KONINKL PHILIPS ELECTRONICS NV, PHILIPS SVENSKA AB, KONINKLIJKE PHILIPS ELECTRONICS N.V., PHILIPS AB
Application year: 1998
Main classification: H01L
IPC codes: H01L21, H01L27, H01L29