Differential detector with error correcting function

Abstract: A differential detector imparted with error correcting function for detecting a differentially phase shifted signal while performing error correction includes a one-symbol differential detector (1) for performing phase comparison between a current input signal (4) and a signal preceding by one symbol, a delay circuit (26) for delaying a one-symbol differential detection signal (5) by two symbol periods, a two-symbol differential detector (2) for performing phase comparison between the current input signal (4) and an input signal preceding by two symbol periods, a four-symbol differential detector (24) for performing phase comparison between the current input signal (4) and an input signal preceding by four symbol periods, and two error correction circuits (25, 27). By making use of the four-symbol differential detection signal, error correction of the two-symbol differential detection signal is performed by the error correction circuit (25) while error correction of the one-symbol differential detection signal is performed by using the corrected two-symbol differential detection signal. By diminishing the error of the two-symbol differential detection signal (6), the error correcting capability for the one-symbol differential detection signal (5) is enhanced with bit error rate characteristic being improved.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to a differential detector imparted with an error correcting function, which detector is employed in a radio receiver of a digital mobile communication system for demodulating a differentially phase modulated or shifted signal. More particularly, the present invention is concerned with a differential detector with the error correcting function for correcting a two-symbol differential detection signal by making use of a four-symbol differentially detected signal and then correcting a one-symbol differentially detected signal by utilizing the corrected two-symbol differentially detected signal. Description of Related Art In the digital mobile communication such as a digital cellular mobile phone system, there is used a differential phase-shifted signal such as signal undergone π/4-DQPSK (π/4 differential quadrature phase shift keying) or the like. The differentially phase-shifted signal can be detected by a synchronous detector or a differential detector. Although the circuit configuration of the differential detector is relatively simple, the differential detector suffers a higher bit error rate when compared with the synchronous detector. Under the circumstances, the differential detector with error correcting function is employed with a view to reducing the bit error rate. For having better understanding of the concept underlying the present invention, description will first be made of a conventional differential detector with error correcting function. Figure 8 of the accompanying drawings is a functional block diagram showing schematically a structure of a conventional differential detector with error correcting function. Referring to Fig. 8, a reference numeral 1 denotes a one-symbol differential detection circuit for performing phase comparison between a current input signal and an input signal preceding by one symbol relative to the current input signal to thereby output a phase difference signal, numeral 2 denotes a two-symbol differential detection circuit for performing phase comparison between a current input signal and an input signal preceding by two symbols relative to the current input signal to thereby output a phase difference signal, and numeral 3 denotes an error correction circuit. Further, Fig. 9 of the accompanying drawings is a functional block diagram showing schematically a typical structure of the one-symbol differential detection circuit 1. In the differential detector with error correcting function implemented in such a configuration as shown in Fig. 8, the input signal 4 is inputted at first to the one-symbol differential detection circuit 1 to undergo phase comparison with the input signal preceding by one symbol (hereinafter also referred to as the one-symbol preceding input signal for convenience of the description), whereby a one-symbol differentially detected signal 5 is obtained. In general, the one-symbol differential detection circuit 1 is composed of a delay circuit 8 for delaying the input signal 4 by one symbol and a digital multiplier 9, as shown in Fig. 9, wherein the one-symbol differentially detected signal 5 can be derived by multiplying the current input signal 4 by the one-symbol preceding input signal. Similarly, the input signal 4 is also inputted to the two-symbol differential detection circuit 2 to undergo phase comparison with the input signal preceding by two symbols (hereinafter also referred to as the two-symbol preceding input signal for convenience of the description), whereby a two-symbol differentially detected signal 6 is obtained. In this conjunction, it should be mentioned that the two-symbol differential detection circuit 2 differs from the one-symbol differential detection circuit 1 in the respect that a delay circuit for delaying the input signal 4 by two symbols is provided in place of the delay circuit 8 designed for delaying the input signal 4 by one symbol and thus the two-symbol differential detection circuit 2 can be implemented in a circuit structure similar to that of the one-symbol differential detection circuit 1. Finally, the one-symbol differentially detected signal 5 and the two-symbol differentially detected signal 6 are inputted to the error correction circuit 3, wherein the one-symbol differentially detected signal 5 undergoes error correction processing, and thus an error-corrected differentially detected output signal 7 is obtained, as can be seen from Fig. 8. Figure 10 of the accompanying drawings is a schematic circuit diagram showing a typical structure of the error correction circuit 3. In the figure, reference numerals 91 and 92 denote phase discrimination or decision circuits, respectively, numeral 12 denotes a digital adder, numerals 13, 14 and 17 denote digital subtractors, respectively, numerals 11 and 15 denote delay circuits, respectively, for delaying the input signal 4 by one symbol, and reference numeral 16 denotes a coincidence detection circuit. Operation of the error correction circuit 3 will be described by reference to Fig. 10. In the first place, the phase of the one-symbol differentially detected signal 5 is discriminatively decided by means of the phase decision circuit 91 whereon the one-symbol differentially detected signal 5 is delayed by one symbol by the delay circuit 11, whereby a delayed signal 18 is obtained. Representing by N(n) the phase of the input signal 4, a phase difference signal DN 1 (n) corresponding to the one-symbol differentially detected signal 5 and a delayed phase difference signal DN 1 (n-1) corresponding to the above-mentioned signal 18 can be given by the following expressions (1) and (2), respectively: DΦ 1 (n) = Φ(n) - Φ(n - 1) DΦ 1 (n - 1) = Φ(n - 1) - Φ(n - 2) where n (= 0, 1, 2 ...) indicate time points at which symbols make appearance, respectively. Assuming that the one-symbol differentially detected signal 5 contains error e(n), the above expression (2) can be rewritten as follows: DΦ 1 (n - 1) = Φ(n - 1) - Φ(n - 2) + e(n) In succession, the one-symbol differentially detected signal 5 and the delayed signal 18 are added together by means of the digital adder 12, whereby a signal 19 is obtained. This signal 19 can be given by the following expression (4): DΦ 1 (n) + DΦ 1 (n - 1) = {Φ(n) - Φ(n - 1)} + {Φ(n - 1) - Φ(n - 2) + e(n)} = Φ(n) - Φ(n - 2) + e(n) On the other hand, a phase difference signal DΦ 2 (n) corresponding to the two-symbol differentially detected signal 6 is given by the undermentioned expression (5) on the presumption that no error is contained in the two-symbol differentially detected signal 6. DΦ 2 (n) = Φ(n) - Φ(n - 2) Subsequently, the two-symbol differentially detected signal 6, having undergone the phase discrimination in the phase decision circuit 92 is subtracted from the signal 19 by means of the digital subtractor 13, as a result of which a signal s(n) corresponding to the output signal 20 of the digital subtractor 13 is obtained. The signal s(n) can be given by the following expression: s(n) = {Φ(n) - Φ(n - 2) + e(n)} - {Φ(n) - Φ(n - 2)} = e(n) Subsequently, a signal "error(n)" corresponding to an error pattern signal 23 is subtracted from the signal 20 by the digital subtractor 14, whereby a signal 21 which is free of influence of the error before one symbol is outputted from the digital subtractor 14 as a signal si(n). This signal si(n) is then delayed by one symbol by means of a delay circuit 15 whose output signal 22 is represented by si(n-1). Now, the signals s(n) and si(n-1) corresponding to the signal 20 and the signal 22, respectively, are inputted to the coincidence detection circuit 16, whereby the signal "error(n)" is derived as the error pattern signal 23. The signal "error(n)" corresponding to the error pattern signal 23 is defined as follows: error(n) = 0 in case s(n) = si(n - 1) = 0 error(n) = 0 in case s(n) ≠ 0 and si(n - 1) = 0 error(n) = 0 in case s(n) = 0 and si(n - 1) ≠ 0 error(n) = m in case s(n) = si(n - 1) = m ≠ 0 Finally, the error pattern signal 23 is subtracted from the signal 18 by the digital subtractor 17, whereby the error-corrected differentially detected output signal 7 can be obtained. With the arrangement of the conventional differential detector equipped with the error correcting function described above, the error correction can be performed for the one-symbol differentially detected signal so far as no error exists in the two-symbol differentially detected signal. However, when the two-symbol differentially detected signal suffers error, the error correction can not be carried out correctly for the one-symbol differentially detected signal, but erroneous correction of error will be performed, giving rise to a problems that error becomes more serious due to the erroneous correction, whereby the bit error rate characteristic is degraded rather than improved. In this conjunction, there is disclosed in Japanese Patent JP-A-54-8908 a differential detection error correcting scheme based on the concept underlying the error correction code in conjunction with the detection scheme for an m-value digital carrier transmission system such as of an m-phase differential phase shift keying (DPSK) scheme or an m-value continuous phase frequency shift keying (CPFSK) scheme. According to the differential detection error correcting scheme mentioned above, error detection as well as error correction can be performed by making use of the inherent redundancy that the symbol contained in the data for transmission represents a modulo-m sum value of the information symbol contained in the time slot relevant to the above-mentioned symbol and the information symbol preceding by one time slot. However, when two or more of four elements constituting the syndromes si(n) and si(n-1) suffer error, the error detection as well as the error correction are rendered impossible as in the case of the conventional differential detector described previously. US-A-5208836 describes a delay detector which includes the features of the pre-characterising part of claim 1. SUMMARY OF THE INVENTION In the light of the state of the art described above, it is an object of the present invention to provide a differential detector imparted with error correcting function for demodulating a differentially phase-shifted signal, which detector is capable of correcting the error contained in the signal with enhanced effectivity, thus improving significantly the error rate characteristic. According to the present invention there is provided a differential detector provided with an error correcting function comprising: first detecting means for delaying an input signal substantially by one symbol period to obtain a first delayed input signal for thereby generating a first detection signal corresponding to phase difference between the input signal and the first delayed input signal: second detecting means for delaying the input signal substantially by two symbol periods to obtain a second delayed input signal for thereby generating a second detection signal corresponding to phase difference between the input signal and the second delayed input signal; and third detecting means for delaying the input signal substantially by four symbol periods to obtain a third delayed input signal for thereby generating a third detection signal corresponding to phase difference between the input signal and the third delayed input signal; characterised by comprising: first error correcting means connected to said second detecting means and said third detecting means for carrying out error correction for the second detection signal by making use of the third detection signal; delay means connected to said first detecting means for delaying the first detection signal substantially by two symbol periods; second error correction means connected to said first error correcting means and said delay means for carrying out error correction for the first detection signal output from said delay means by making use of an output signal of said first error correction means; first decision means connected to said second detecting means for making decision as to whether data contained in the second detection signal is correct or erroneous; first selecting means connected to said first decision means for selectively deciding whether or not error correction is to be validated for the second detection signal on the basis of result of the decision made by said first decision means; second decision means connected to said delay means for making decision as to whether data contained in the first detection signal is correct or erroneous; and second selecting means connected to said second decision means for selectively deciding whether or not error correction is to be validated for the first detection signal on the basis of result of the decision made by said decision means. By virtue of the arrangement in which the error correction for the second detection signal is performed by making use of the third detection signal while the error correction for the first detection signal is performed by making use of the second detection signal as corrected, there can be realized the differential detector which can effectively reduce error contained in the first detection signal with enhanced error correcting capability, whereby the error rate characteristic can significantly be improved. The above and other objects, features and attendant advantages of the present invention will more easily be understood by reading the following description of the preferred embodiments thereof taken, only by way of example, in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS In the course of the description which follows, reference is made to the drawings, in which: Fig. 1 is a functional block diagram showing schematically a structure of a differential detector equipped with an error correcting function according to a first embodiment of the present invention; Fig. 2 is a functional block diagram showing an error correction circuit designed for performing error correction for a two-symbol differential detection signal in the differential detector according to the first embodiment of the invention; Fig. 3 is a view for graphically illustrating results of computer simulation of the differential detector according to the first embodiment of the invention; Fig. 4 is a functional block diagram showing an error correction circuit designed for performing error correction for a one-symbol differentially detected signal which can be used in the detector of Figure 1; Fig. 5 is a functional block diagram showing an error correction circuit designed for performing error correction for a two-symbol differentially detected signal which can be used in the detector of Figure 1; Fig. 6 is a functional block diagram showing another example of an error correction circuit designed for performing error correction for a one-symbol differentially detected signal which can be used in the detector of Figure 1; Fig. 7 is a functional block diagram showing another example of an error correction circuit designed for performing error correction for a two-symbol differentially detected signal which can be used in the detector of Figure 1; Fig. 8 is a functional block diagram showing schematically a structure of a conventional differential detector equipped with error correcting function; Fig. 9 is a schematic block diagram showing a typical structure of a one-symbol differential detection circuit in a conventional differential detector known heretofore; and Fig. 10 is a schematic block diagram showing a typical structure of an error correction circuit in the conventional differential detector. DESCRIPTION OF THE PREFERRED EMBODIMENTS Now, the present invention will be described in detail in conjunction with what is presently considered as preferred or typical embodiments thereof by reference to the drawings. Embodiment 1 A first embodiment of the present invention relates to a differential detector imparted with error correcting function for correcting error contained in a two-symbol differentially (or delayed) detected signal by making use of a four-symbol differentially (or delayed) detected signal and then correcting error contained in a one-symbol differentially (or delayed) detected signal by utilizing the corrected two-symbol differentially detected signal. Now, referring to Figs. 1 and 2, description will be directed to the differential detector having the error correcting function according to the first embodiment of the invention, wherein Fig. 1 is a block diagram showing schematically a structure of the differential detector having the error correcting function. Referring to Fig. 1, a reference numeral 1 denotes a one-symbol differential detection circuit for performing phase comparison between a current input signal 4 and an input signal preceding by one symbol relative to the current input signal, numeral 2 denotes a two-symbol differential detection circuit for performing phase comparison between the current input signal 4 and an input signal preceding by two symbols relative to the current input signal, numeral 24 denotes a four-symbol differential detection circuit for performing phase comparison between the current input signal 4 and an input signal preceding by four symbols relative to the current input signal, and numerals 25 and 27 denote error correction circuits. At first, the input signal 4 is inputted to the one-symbol differential detection circuit 1 to undergo phase comparison with the input signal preceding by one symbol (hereinafter referred to as the one-symbol preceding input signal for convenience of the description), whereby a one-symbol differentially detected signal 5 which represents a phase difference between the input signal and the one-symbol preceding input signal is obtained. The one-symbol differential detection circuit 1 can be realized in such a structure as shown in Fig. 9. Similarly, the input signal 4 is inputted to the two-symbol differential detection circuit 2 and the four-symbol differential detection circuit 24, respectively, to undergo phase comparison with a two-symbol preceding input signal and a four-symbol preceding input signal, respectively, whereby a two-symbol differentially detected signal 6 and a four-symbol differentially detected signal 28 can be obtained, respectively. In this conjunction, it should be mentioned that the two-symbol differential detection circuit 2 differs from the one-symbol differential detection circuit 1 in the respect that the delay circuit for delaying the input signal 4 by two symbols (which is similar to the delay circuit 26) is provided in place of the delay circuit 8 designed for delaying the input signal 4 by one symbol. Thus, the two-symbol differential detection circuit 2 can be implemented in a circuit structure similar to that of the one-symbol differential detection circuit 1. Similarly, the four-symbol differential detection circuit 24 can be implemented in the circuit structure similar to that of the one-symbol differential detection circuit 1 except that a delay circuit for delaying the input signal 4 by four symbols is provided in place of the delay circuit 8 designed for delaying the input signal 4 by one symbol. Next, the two-symbol differentially detected signal 6 and the four-symbol differentially detected signal 28 are inputted to the error correction circuit 25, wherein the two-symbol differential detection signal 6 undergoes error correction processing. Thus, an error corrected signal 29 can be derived from the correction of the two-symbol differential detection signal 6. The one-symbol differentially detected signal 5 is delayed by two symbols through the delay circuit 26, whereby a signal 30 is obtained. Ultimately, the signals 30 and 29 are inputted to an error correction circuit 27, wherein the signal 30 undergoes error correction. In this way, an error-corrected differentially detection output signal 31 can be obtained. Figure 2 is a schematic circuit diagram showing a typical structure of the error correction circuit 25 in the differential detector according to the first embodiment of the invention. Description will be made of the error correction circuit 25 by reference to Fig. 2. In this figure, numeral 33 denotes a digital adder, numerals 34, 35 and 38 denote digital subtracters, respectively, and reference numeral 32 and 36 denote delay circuits, respectively, for delaying the input signal 4 by two symbols, and numeral 37 denotes a coincidence detection circuit. In the first place, the phase of the two-symbol differential detection signal 6 is discriminatively decided by a phase discrimination or decision circuit 93 to be subsequently delayed by two symbols by the delay circuit 32, whereby the signal 39 is obtained. Representing by Φ(n) the phase of the input signal 4, a phase difference signal DΦ 2 (n) corresponding to the two-symbol differential detection signal 6 and a phase difference signal DΦ 2 (n-2) corresponding to the signal 39 can be given by the following expressions (11) and (12), respectively. DΦ 2 (n) = Φ(n) - Φ(n - 2) DΦ 2 (n - 2) = Φ(n - 2) - Φ(n - 4) where n (= 0, 1, 2 ...) indicate time points at which symbols make appearance, respectively. Assuming that the signal 39 contains error e(n), the above expression (12) can be rewritten as follows: DΦ 2 (n - 2) = Φ(n - 2) - Φ(n - 4) + e(n) In succession, the two-symbol differentially detected signal 6 and the signal 39 are added together by means of the digital adder 33, whereby a signal 40 is obtained. The signal 40 can be given by the following expression (14): DΦ 2 (n) + DΦ 2 (n - 2) = {Φ(n) - Φ(n - 2)} + {Φ(n - 2) - Φ(n - 4) + e(n)} = Φ(n) - Φ(n - 4) + e(n) On the other hand, a phase difference signal DΦ 4 (n) corresponding to the signal 28 can be given by the undermentioned expression (15) on the presumption that no error is contained. DΦ 4 (n) = Φ(n) - Φ(n - 4) Subsequently, the four-symbol differentially detected signal 28 having undergone the phase discrimination in the phase decision circuit 94 is subtracted from the signal 40 by the digital subtractor 34, as a result of which a signal s(n) corresponding to the output signal 41 of the digital subtractor 34 is obtained. The signal s(n) can be given by the following expression: s(n) = {Φ(n) - Φ(n - 4) + e(n)} - {Φ(n) - Φ(n - 4)} = e(n) In succession, a signal "error(n)" corresponding to an error pattern signal 44 is subtracted from the signal 41 by the digital subtractor 35, whereby a signal 42 which is free of the influence of error prevailing by two symbols before is outputted from the digital subtractor 35 as a signal si(n) which is then delayed by two symbols by means of a delay circuit 36, whose output signal 43 is represented by si(n-2). The signals s(n) and si(n-2) corresponding to the signal 41 and the signal 43, respectively, are inputted to the coincidence detection circuit 37, whereby the above-mentioned signal "error(n)" is derived as the error pattern signal 44. The signal "error(n)" corresponding to the error pattern signal 44 is defined as follows: error(n) = 0 in case s(n) = si(n - 2) = 0 error(n) = 0 in case s(n) ≠ 0 and si(n - 2) = 0 error(n) = 0 in case s(n) = 0 and si(n - 2) ≠ 0 error(n) = m in case s(n) = si(n - 2) = m ≠ 0 Finally, the error pattern signal 44 is subtracted from the signal 39 by the digital subtractor 38, whereby the two-symbol differentially detected signal 29 undergone the error correction can be obtained. Parenthetically, the error correction circuit 27 can be implemented in a substantially same structure as the one shown in Fig. 10 and serve for substantially same functions or operations as the latter. As is apparent from the foregoing description, the differential detector with the error correcting function according to the first embodiment of the invention performs error correction of the two-symbol differentially detected signal 6 by means of the error correction circuit 25 by making use of the four-symbol differentially detected signal 28 and then performs error correction of the one-symbol differentially detected signal 30 by means of the error correction circuit 27 by utilizing the corrected two-symbol differentially detected signal 29, whereby error of the two-symbol differentially detected signal 6 can be reduced with the error correcting capability for the one-symbol differentially detected signal 5 being enhanced, which in turn is effective for improvement of the bit error rate characteristic. Figure 3 is a view for graphically illustrating Eb/No (a ratio of the received signal energy per bit to the noise density at a receiver) vs. bit error rate characteristics. In the figure, a curve affixed with circles "0" represents result of computer simulation in the case where only the one-symbol differential detector is used as the differential detector, while a curve with rectangular symbols "□" represents result of computer simulation of the differential detector in the case where no error correction is performed for the two-symbol differential detection signal. Further, a curve with "×" represents result of computer simulation performed for the differential detector with error correcting function according to the present invention. As can be seen from Fig. 3, according to the teachings of the invention incarnated in the first embodiment, the bit error rate can be improved by magnitude of two orders when compared with the differential detector where only the one-symbol differential detector is used as the differential detection circuit in case Eb/No = 11 dB. Further, when compared with the case where no error correction is performed for the two-symbol differentially detected signal, the bit error rate can be improved by magnitude of one order or so. Figure 4 shows an example of the circuit 27 of Figure 1. In this error correcting circuit a switch circuit is provided or discriminated for allowing the error correction of the one-symbol differential detection signal to be validated only when the decision-destined phase difference of the one-symbol differential detection signal exceeds a reference value. Fig. 4 shows in a functional block diagram an error correction circuit designed for performing the error correction for the one-symbol differentially detected signal. The circuit arrangement now under consideration includes a decision-destined phase difference signal generation circuit 45, a digital subtractor 46, a decision circuit 47 and a switch circuit 48 are additionally provided, wherein the error correction is performed for the one-symbol differentially detected signal only when the decision-destined phase difference exceeds a reference value. Referring to Fig. 4, the signal 30 is a phase difference signal before undergoing the phase discrimination or decision. More specifically, the signal 30 undergoes phase discrimination or decision operation (hereinafter referred to as the phase decision) by the phase decision circuit 91, the output signal of which is then inputted to both the delay circuit 11 and the digital adder 12, respectively. The signal 30 is supplied to the decision-destined phase difference signal generation circuit 45 as well, whereby a decision-destined phase difference signal 49 is outputted from the circuit 45. A reference signal (REF) 50 is subtracted from the decision-destined phase difference signal 49 by means of a digital subtractor 46 to thereby derive a signal 51 which is then inputted to the decision circuit 47. Thus, a control signal 52 is obtained as the output signal of the decision circuit 47. The switch circuit 48 is adapted to select either the error pattern signal 23 or a zero signal 53. The output signal of the error pattern signal 44 in Fig 2 is shown as a signal 54 in Figure 4. The signal 54 is subtracted from the signal 18 by means of the digital subtractor 17, whereby an error-corrected differentially detected output signal 55 is obtained. The decision-destined phase difference signal generation circuit 45 is so designed as to subtract from the signal 30 a corresponding centre phase wherein a signal resulting from the subtraction is outputted as the decision-destined phase difference signal 49. By way of example, in the π/4-DQPSK system, the center phase is ±π/4 or ±3π/4. Consequently, threshold phase is zero, ±π/2 or ±π. Assuming now that the phase of the signal 30 is 0.4π, the center phase is then π/4. Thus, the decision-destined phase difference signal 49 is of 0.15π (= 0.4π - 0.25π). Consequently, when the phase of the reference signal (REF) 50 is 1/8π, the signal 51 meets the condition that 0.15π - 0.15π = 0.025π > 0. Since the decision-destined phase difference signal 49 exceeds the reference signal (REF) 50, the decision in the circuit 47 results in "positive or plus". Consequently, the switch circuit 48 is changed over to the position for validating the error correction in response to the control signal 52. Unless the decision-destined phase difference signal 49 exceeds the reference signal (REF) 50, the switch circuit 48 is changed over to the position for invalidating the error correction. As will be appreciated from the above description, the error correction is performed for the one-symbol differentially detected signal only when the decision-destined phase difference of the one-symbol differential detection signal exceeds the reference value. In this conjunction, it is to be noted that the decision-destined phase difference being small indicates that the probability of error occurrence is small. In that case, if the error correction is performed, the probability of incurring erroneous correction will undesirably increase. With a view to evading such undesirable situation, the error correction for the one-symbol differentially detected signal is performed only when the decision-destined phase difference is large, to thereby prevent the erroneous correction of the one-symbol differentially detected signal when the decision-destined phase difference signal is of a small value. With this arrangement, the bit error rate characteristic can be improved. FIgure 5 shows an example of the circuit 25 of Figure 1. In this error correcting circuit, a switch circuit is provided for allowing the error correction of the two-symbol differentially detected signal to be validated only when the decision-destined phase difference of the two-symbol differentially detected signal exceeds a reference value. Fig. 5 is a functional block diagram showing an error correction circuit designed for performing the error correction for the two-symbol differentially detected signal. The circuit includes a phase difference signal generation circuit 56, a digital subtractor 57, a decision circuit 58 and a switch circuit 59 are additionally provided, wherein the error correction is performed for the two-symbol differential detection signal only when the decision-destined phase difference signal has a value which exceeds a reference value. The two-symbol differentially detected signal 6 is supplied to the decision-destined phase difference signal generation circuit 56 as well, whereby a decision-destined phase difference signal 60 is outputted from the circuit 56. A reference signal (REF) 61 is subtracted from the decision-destined phase difference signal 60 by the digital subtractor 57 to thereby derive a signal 62 which is then inputted to the decision circuit 58. Thus, the control signal 63 is obtained as the output signal of the decision circuit 58. The switch circuit 59 is adapted to select either the error pattern signal 44 or a zero signal 64. The output signal of the error pattern signal 44 is shown as a signal 65. The signal 65 is subtracted from the signal 39 by means of the digital subtractor 38, whereby an error-corrected differentially detected output signal 66 is obtained. The two-symbol differentially detected signal 6 represents a phase difference signal. The decision-destined phase difference signal generation circuit 56 subtracts the center phase from the phase difference signal to thereby output a decision-destined phase difference signal 60. When the decision-destined phase difference signal is of a small value, it is then decided that no error exists. In this case, no error correction is carried out. On the other hand, when the decision-destined phase difference signal is of a large value, being close to the threshold value, this means that the probability of error occurrence is large. Accordingly, error correction is performed. As will be appreciated from the above description, the error correction is performed for the two-symbol differentially detected signal only when the decision-destined phase difference of the two-symbol differentially detected signal exceeds the reference value. In this way, by preventing the erroneous correction of the two-symbol differentially detected signal when the decision-destined phase difference is small, the bit error rate characteristic can be improved. Figure 6 shows another example of the circuit 27 of Figure 1. This error correction circuit has an arrangement for making variable the reference value to be compared with the decision-destined phase difference in association with the error correction circuit which performs error correction for the one-symbol differentially detected signal. Fig. 6 shows in a functional block diagram an error correction circuit designed for performing the error correction for the one-symbol differentially detected signal. The circuit arrangement now under consideration differs from the one described hereinbefore in conjunction with Figure 4 in that a level detection circuit 67, a digital subtractor 68, a decision circuit 69 and a switch circuit 70 are additionally provided in the differential detector having the error correcting function for the one-symbol differentially detected signal, wherein the reference value compared with the decision-destined phase difference is adapted to be variable. Incidentally, components and signals same as or equivalent to those described hereinbefore in conjunction with Figure 4 are denoted by like reference characters, and repeated description thereof is omitted. Further, the process carried out up to the generation of the decision-destined phase difference signal 49 is same as in the case of the Figure 4 circuit. The signal 30 and the corrected two-symbol differentially detected signal 29 are inputted to the level detection circuit 67 for detecting an input signal level and a noise level, respectively, to derive a signal 71 indicating the input signal level relative to the noise level. Each of the signal 30 and the corrected two-symbol differentially detected signal 29 represents a phase difference signal. Difference between the phase difference signal and the center phase as detected by the level detection circuit 67 can be regarded as representing magnitude of noise. Accordingly, by integrating the difference mentioned above over a period of appropriate duration, the noise level can be determined. Subsequently, the reference signal 72 is subtracted from the signal 71 by means of the digital subtractor 68, whereby a signal 73 is derived. The signal 73 then undergoes decision processing by the decision circuit 69, as a result of which a control signal 74 is obtained. This control signal 74 serves for controlling the switch circuit 70 which selects either the reference signal 75 or 76. The output signal of the switch circuit 70 is designated by numeral 77. Incidentally, the succeeding process carried out up to the generation of the error-corrected differentially detected output signal 78 is same as in the case of Figure 4. In general, as the signal-to-noise power ratio increases, the probability of the decision-destined phase difference of the input signal becomes high when error takes place. In this conjunction, it is however noted that when the noise level is high, the probability of error occurrence due to the noise increases. Accordingly, even when the phase difference signal is closer to the center phase (being remote from the threshold phase) with the decision-destined phase difference being small, there is a possibility that error is generated due to the noise of large magnitude. Such being the circumstances, it is preferred to set wide ranges for the error correction at both sides of the threshold level. By contrast, when the noise level is low, the probability of error occurrence due to noise is low, which in turn means that the probability of error is low when the decision-destined phase difference is small. For these reasons, possibility of the erroneous correction can be suppressed by regarding that occurrence of error is limited to the vicinity of the threshold phase. Thus, by increasing the reference value for comparison with the decision-destined phase difference as the signal-to-noise power ratio increases, the erroneous correction can be prevented more positively. To say in another way, the error rate on the whole can be lowered by performing the error correction even when the decision-destined phase difference is small provided that the noise level is high, while when the noise level is low, the error correction is validated only if the decision-destined phase difference is sufficiently large. As is apparent from the above description, in the circuit of Figure 6, the level detection circuit 67, the digital subtractor 68, the decision circuit 69 and the switch circuit 70 are provided in the error correction circuit for performing the error correction for the one-symbol differentially detected signal, wherein the reference value to be compared with the decision-destined phase difference is so designed as to be made variable. By increasing the reference value for the error correction when the noise level is low, the erroneous correction can be excluded more positively when compared with the differential detector having the error correcting function according to Figure 4. Figure 7 shows an alternative form of the circuit 25 of Figure 1. This error correction circuit has an arrangement for making variable the reference value to be compared with the decision-destined phase difference in association with the error correction circuit which performs error correction for the two-symbol differentially detected signal. Fig. 7 shows in a functional block diagram an error correction circuit designed for performing the error correction for the two-symbol differentially detected signal. The circuit arrangement now under consideration differs from the one described hereinbefore in conjunction with Figure 5 in that a level detection circuit 79, a digital subtractor 80, a decision circuit 81 and a switch circuit 82 are additionally provided in the error correction circuit which performs error correction for the two-symbol differentially detected signal, wherein the reference value for comparison with the decision-destined phase difference is adapted to be variable. Incidentally, components and signals same as or equivalent to those described hereinbefore in conjunction with Figure 5 are denoted by like reference characters, and repeated description thereof is-omitted. Further, the process carried out up to the generation of the decision-destined phase difference signal 60 is substantially same as in the case of Figure 5. The two-symbol differentially detected signal 6 and the four-symbol differentially detected signal 28 are inputted to the level detection circuit 79 for detecting an input signal level and a noise level, respectively, to thereby derive a signal 83 indicating the input signal level relative to the noise level. Subsequently, the level signal 83 is subtracted from the reference signal 84 by the digital subtractor 80, whereby a signal 85 is derived. The signal 85 then undergoes decision processing by the decision circuit 81, as a result of which a control signal 86 is obtained. This control signal 86 serves for controlling the switch circuit 82 which selects either the reference signal 87 or 88 to output a signal 89. When the noise level is high, the reference signal 89 for comparison with the decision-destined phase difference signal 60 is set low for thereby allowing the error correction of the two-symbol differentially detected signal to be performed within a wide or broad range, while when the noise level is low, the reference signal for comparison with the decision-destined phase difference signal is set high for thereby allowing the error correction of the two-symbol differentially detected signal to be performed within a narrow range. The succeeding process carried out up to the generation of the error-corrected differentially detected output signal 90 is same as in the case of Figure 5. As is apparent from the above description, in the error correcting circuit of Figure 7, the level detection circuit 79, the digital subtractor 80, the decision circuit 81 and the switch circuit 82 are provided in the error correction circuit performing error correction for the two-symbol differentially detected signal, wherein the reference value to be compared with the decision-destined phase difference is made variable. By increasing the reference value for enabling the erroneous correction when the noise level is low, the error correction can be excluded more positively when compared with the differential detector having the error correcting function according to Figure 5. As is apparent from the foregoing description, the present embodiment teaches that the error correction is performed for the two-symbol differentially detected signal by making use of the four-symbol differentially detected signal and then performing the error correction for the one symbol differentially detected signal by utilizing the corrected two-symbol differentially detected signal. Thus, the erroneous correction due to the error contained in the two-symbol differentially detected signal can be prevented, whereby the bit error rate characteristic can be improved Further, by performing no error correction when the decision-destined phase difference is small while enabling the error correction only when the decision-destined phase difference is large, the error correction can be disabled when the decision-destined phase difference signal is of small magnitude, whereby the bit error rate characteristic can further be improved. Furthermore, by performing the error correction over a wide range when the noise level is high while carrying out the error correction within a narrow range when the noise level is low, erroneous correction can be prevented when the noise level is low, whereby the bit error rate characteristic can be improved more significantly.

Claims: A differential detector provided with an error correcting function comprising first detecting means (1) for delaying an input signal (4) substantially by one symbol period to obtain a first delayed input signal for thereby generating a first detection signal (5) corresponding to phase difference between the input signal (4) and the first delayed input signal: second detecting means (2) for delaying the input signal (4) substantially by two symbol periods to obtain a second delayed input signal for thereby generating a second detection signal (6) corresponding to phase difference between the input signal (4) and the second delayed input signal; and third detecting means (24) for delaying the input signal (4) substantially by four symbol periods to obtain a third delayed input signal for thereby generating a third detection signal (28) corresponding to phase difference between the input signal (4) and the third delayed input signal; characterised by comprising: first error correcting means (25) connected to said second detecting means (2) and said third detecting means (24) for carrying out error correction for the second detection signal (6) by making use of the third detection signal; delay means (26) connected to said first detecting means (1) for delaying the first detection signal substantially by two symbol periods; second error correction means (27) connected to said first error correcting means (25) and said delay means (26) for carrying out error correction for the first detection signal (30) output from said delay means (26) by making use of an output signal (29) of said first error correction means (25); first decision means (56, 57, 58) connected to said second detecting means (2) for making decision as to whether data contained in the second detection signal (6) is correct or erroneous; first selecting means (59) connected to said first decision means (56, 57, 58) for selectively deciding whether or not error correction is to be validated for the second detection signal on the basis of result of the decision made by said first decision means (56, 57, 58); second decision means (45, 46, 47) connected to said delay means (26) for making decision as to whether data contained in the first detection signal (30) is correct or erroneous; and second selecting means (48) connected to said second decision means (45, 46, 47) for selectively deciding whether or not error correction is to be validated for the first detection signal (30) on the basis of result of the decision made by said decision means (45, 46, 47). A differential detector according to claim 1, characterised is that said first error correcting means (25) includes: a first delay circuit (32) for delaying the second detection signal (6) substantially by two symbol periods; an adder (33) for adding together the second detection signal (6) and an output signal (39) of said first delay circuit (32); a first subtractor (34) for subtracting the third detection signal (28) from an output signal (40) of said adder (33); a second subtractor (35) for subtracting an error pattern signal (44) from the output signal (41) of said first subtractor (34); a second delay circuit (36) for delaying an output signal (42) of said second subtractor (35) substantially by two symbol periods; a coincidence detection circuit (37) for comparing the output signal (41) of said first subtractor (84) and the output signal (43) of said second delay circuit (36) with each other to thereby generate the error pattern signal (44) in accordance with result of said comparison; and a third subtractor (38) for subtracting the error pattern signal (44) from the output signal (39) of said first delay circuit (32). A differential detector according to claim 1, characterised in that said second error correcting means (27) includes: a first delay circuit (11) for delaying the first detection signal (30) output from said delay circuit (26) substantially by one symbol period; an adder (12) for adding together the first detection signal (30) output from said delay circuit (26) and an output signal (18) of said first delay circuit (11); a first subtractor (13) for subtracting the output signal (29) of said first error correction means (25) from an output signal (19) of said adder (12); a second subtractor (14) for subtracting an error pattern signal (23) from the output signal (20) of said first subtractor (13); a second delay circuit (15) for delaying an output signal (21) of said second subtractor (14) substantially by one symbol period; a coincidence detector circuit (16) for comparing the output signal (20) of said first subtractor (13) and the output signal (22) of said second delay circuit (15) with each other to thereby generate the error pattern signal (23) in accordance with result of said comparison; and a third subtractor (17) for subtracting the error pattern signal (23) from the output signal (18) of said first delay circuit (11). A differential detector according to claim 1, characterised in that said first decision means (56, 57, 58) is so arranged as to generate a decision difference signal (60) indicating whether data contained in the second detection signal (6) is correct or erroneous for thereby comparing the decision difference signal (60) with a reference value (89) to make decision as to whether the data carried by the second detection signal (6) is correct or erroneous; and characterised by further comprising means (79, 80, 81, 82) for detecting a signal level and a noise level of the second detection signal (6) for thereby outputting the reference value as a variable value on the basis of the signal level and the noise level as detected. A differential detector according to claim 1, characterised in that said second decision means (45, 46, 47) is so arranged as to generate a decision difference signal (49) indicating whether data contained in the first detection signal (30) is correct or erroneous for thereby comparing the decision difference signal (49) with a reference value (77) to make decision as to whether the data carried by the first detection signal (30) is correct or erroneous; and characterised by further comprising means (67, 68, 69, 70) for detecting a signal level and a noise level of the first detection signal (30) for thereby outputting the reference value as a variable value on the basis of the signal level and the noise level as detected.

Inventors: HIRAMATSU KATSUHIKO, SUDO HIROAKI, UESUGI MITSURU, HIRAMATSU, KATSUHIKO, SUDO, HIROAKI, UESUGI, MITSURU
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1998
Main classification: H04L27
IPC codes: H04L1, H04L27