Method for reading a multiple-level memory cell

Abstract: Method (200) for reading a multiple-level memory cell (C 12 ) capable of taking on three or more states which are represented by different values of a physical quantity (Icell) and each of which is associated with a corresponding logical value (LVcell), comprising the steps of setting (210) an actual physical quantity (Is 1 ) to a value correlated with the value of the physical quantity (Icell) corresponding to the state of the memory cell (C 12 ), and repeating (235), up to the complete determination of the logical value (LVcell) corresponding to the state of the memory cell (C 12 ), a cycle (215-235) comprising the steps of setting (227, 232) a component of the logical value (D i ) to a value which is a function of a range in which the actual physical quantity (Is i ) lies, determined by comparing (215, 220) the actual physical quantity (Is i ) with at least one reference physical quantity (Ir i ) having a predetermined value lying between a minimum value and a maximum value for the actual physical quantity (Is i ), and setting (237) the actual physical quantity for a possible next cycle (Is (i+1) ) to a relative value of the actual physical quantity (Is i ) with respect to the range in which it lies.

Description: The present invention relates to a method for reading a multiple-level memory cell. A memory which can store data in a transitory or permanent way generally consists of a set of cells. Each memory cell can be programmed in such a way as to take on a plurality of states, represented by different values of a physical quantity (typically an electrical quantity), with each of which a corresponding logical value is associated. In particular, a multiple-level memory cell can take on three or more different states (levels); typically there are used memory cells with m = 2 n levels (where n≥2), each of which allows a whole number, n = log 2 m, of data bits to be stored. The reading of the logical value stored in a memory cell, typically of the non-volatile type (capable of retaining the stored information even in the absence of an electrical power supply), is generally carried out by comparing the electrical quantity which defines the state of the memory cell with the same electrical quantity of suitably programmed reference cells. In a reading method of the parallel type, the state electrical quantity of the memory cell is compared simultaneously with m-1 reference electrical quantities, each of which has a value lying between two adjacent values which can be programmed into the memory cell; this method enables the logical value stored in the memory cell to be read in a single comparison operation. A disadvantage of this method consists in the fact that it requires m-1 separate comparator circuits to compare the state electrical quantity of the memory cell with the same electrical quantity of the m-1 reference cells. This results in a considerable power consumption and an excessive occupation of space in a chip of semiconductor material in which the memory is formed. Moreover, the connections between the memory cell and the comparator circuits for the transfer of the state electrical quantities are subject to noise (known as "kick-back"); this disadvantage makes it necessary to have circuitry dedicated to the elimination of the noise, which results in additional occupation of the area of the chip and a general slowing of the reading operation. In a reading method of the serial type, on the contrary, the state electrical quantity of the memory cell is compared on successive occasions with a single reference electrical quantity whose value is varied in a predetermined way. In particular, in a method of the sequential type, the comparison electrical quantity initially has a value lying, for example, between the first and the second values which can be programmed into the memory cell, then a value lying between the second and third values which can be programmed, and so on; the reading method is interrupted as soon as the comparison electrical quantity exceeds the value of the state electrical quantity of the memory cell (or when it has reached the value lying between the penultimate and the last programmable values). This method requires a number of comparison operations varying from 1 to m-1, giving a mean of m/2. With a different serial method, of the dichotomous type, the comparison electrical quantity is initially set to a mean value between the minimum and the maximum values which can be programmed into the memory cell; by comparing this electrical quantity with the state quantity of the memory cell, it is possible to determine whether the state electrical quantity falls in a first range delimited by the minimum value and the comparison value or in a second range delimited by the comparison value and the maximum value. A similar procedure is then carried out on this range, and so on, until the value of the state quantity of the memory cell is determined exactly. This reading method requires a number of comparison operations equal to log 2 m. The serial reading methods described above require only a single comparator circuit. The comparison operations, however, are rather complicated and therefore require dedicated circuitry which results in a greater occupation of the area of the chip. Moreover, these reading methods require a number of comparison operations which have to be carried out in succession, since it is necessary to await the result of a preceding comparison operation before selecting the comparison electrical quantity to be used for the next operation. This results in a considerable slowing of the reading operation, which may be unacceptable in various applications. There is also a known method of reading of a mixed serial-parallel type, in which the state electrical quantity of the memory cell is compared simultaneously with two or more reference electrical quantities having a value lying between the minimum value and the maximum value which can be programmed into the memory cell; the result of these comparisons can be used to determine the range (defined by these electrical quantities) to which the state quantity of the memory cell belongs. The reading method then proceeds in a similar way up to the exact determination of the value of the state quantity of the memory cell. If k denotes the number of ranges defined by the comparison electrical quantities, this reading method requires a number of comparison operations equal to log 2 m/log 2 k. The mixed type reading method provides a compromise between the two reading methods (parallel and dichotomous serial) described above, since it requires a smaller number of comparator circuits (k-1) and enables the memory cell to be read with a limited number of comparison operations. However, the reading operation is rather complicated and too slow for many applications. All the known reading methods require in all cases the presence of m-1 reference cells (although in the reading methods of the serial and mixed type not all the reference electrical quantities are used in every reading operation), with a corresponding increase in power consumption and in the occupation of space in the chip. This also makes it necessary to program a large number of reference cells in a highly accurate way, in order to ensure a high precision of the comparison operations and consequently to permit the use of a large number of different values for the state electrical quantity within a given range. The object of the present invention is to overcome the aforesaid disadvantages. To achieve this object, a method is proposed for reading a multiple-level memory cell as described in the first claim. A corresponding device is also proposed for reading a multiple-level memory cell, together with a memory structure comprising such a device. Further characteristics and the advantages of the method for reading a multiple-level memory cell according to the present invention will be understood from the following description of a preferred embodiment of the invention, provided for guidance and without restriction, with reference to the attached figures, in which: Fig. 1 shows a memory structure in which the reading method according to the present invention can be used; Fig. 2 is a block diagram of an example of a reading method according to the present invention; Fig. 3 is a schematic block diagram of a device which can be used to carry out the reading method; Fig. 4 is a circuit diagram of one unit of the reading device. With reference to Fig. 1 in particular, a memory structure 100, comprising a multiple-level matrix of cells (4 in the example shown in the figure) C 11 , C 12 , C 21 and C 22 , is shown. The memory 100 is, for example, an EEPROM (or E 2 PROM) memory of the flash type, in which each cell C 11 -C 22 consists of a field-effect (MOS) transistor of the floating-gate type. Each cell C 11 -C 22 can be programmed at a plurality of levels represented by corresponding values of a threshold voltage of the MOS transistor, which depends on the charge accumulated in the floating gate. The transistors of each cell C 11 -C 22 have their source terminals connected to a common line for each sector (source line), which is generally set to a reference voltage (ground) during the reading operation. The gate terminals of the transistors of each row C 11 , C 12 and C 21 , C 22 are connected to the same word lines W 1 and W 2 respectively; the drain terminals of the transistors of each column C 11 , C 21 and C 21 , C 22 are connected to the same bit lines B 1 and B 2 respectively. The bit lines B 1 and B 2 are connected to separate input terminals of a selector circuit (SEL) 110, which has an output terminal connected to only one of the bit lines B 1 and B 2 , according to the value taken by a selection command Ws. The output terminal of the selector 110 is connected to a conditioning circuit (COND) 120. In a quiescent state, the word lines W 1 , W 2 are at a low potential (0 V for example), so that the transistors of all the cells C 11 -C 22 are cut off. To read a memory cell (the cell C 12 for example), the corresponding bit line B 2 is connected (through the selector 110) to the conditioning circuit 120, in such a way that the drain terminals of the corresponding transistors are brought to a suitable potential (1 V for example) for the correct polarization of the memory cell; this process requires a not insignificant time interval (pre-charge time) owing to the considerable capacitive load connected to the bit line. During this pre-charge phase, the memory cell C 12 is selected by setting the corresponding word line W 1 to a high value. In this situation, the capacity to supply current (conductance) of the transistor of the selected cell C 12 is proportional to the difference between the voltage on its gate terminal (in other words on the word line W 1 ) and its threshold voltage (the conductance is zero if the threshold voltage is greater than the voltage on the gate terminal). Thus the current Icell supplied by the selected cell C 12 corresponds to the logical value stored in it. The cell current Icell is supplied to a first input terminal of a comparison circuit (SENS) 130, which receives at further input terminals various reference currents (indicated in their totality by Ir) generated by a suitable circuit (REF) 140; the circuit 130 is connected to the conditioning circuit 120 (and in particular to transistors other than those used for the pre-charging of the selected cell). The circuit 130 compares the cell current Icell with the reference currents Ir and produces at its output terminals the logical value LVcell corresponding to the data element stored in the selected cell. Similar considerations are applicable to other memory cells, with corresponding accessory circuits (not shown in the figure), which may possibly be read in parallel to produce a memory word at the output; for example, in the case of memory cells with 16 levels (i.e. with log 2 16 = 4 bits), 8 cells will be read simultaneously if the memory word consists of 32 bits. However, the present invention is also suitable for application with memory cells of a different type, for examples those consisting of metal-nitride-oxide semiconductor (or MNOS) transistors, and in general with any multiple-level memory cell which can take on three or more states which are represented by different values of a physical quantity and with each of which a corresponding logical value is associated. Similarly, the memory structure may have a linear or square arrangement, and may consist of a plurality of memory banks or a simple register, and in general a memory structure is provided which comprises at least one multiple-level memory cell, means for selecting a memory cell and supplying at the output a physical quantity corresponding to the state of the memory cell, and at least one device for reading the memory cell. If we now consider Fig. 2, a method 200 for reading the selected memory cell is illustrated in the form of a flow chart. Let us assume, for example, that the memory cell is capable of storing m=16 different logical values (from 0 to 15), in other words n = log 2 16 = 4 bits. The logical value 0 is associated, for example, with a zero cell current Icell 0 ; this makes it unnecessary to program the corresponding threshold voltage in a very precise way (it is sufficient for the threshold voltage to be greater than that applied to the gate terminal at the reading stage). The difference between the cell current associated with each logical value and the cell current associated with the immediately preceding logical value is fixed, at 8 µA for example; therefore, the logical value 1 is associated with a cell current Icell 1 = 8 µA, the logical value 2 is associated with a cell current Icell 2 = 16 µA, and so on, up to the logical value 15 which is associated with a cell current Icell 15 = 120 µA. In practice, owing to variations in the ambient conditions, the degradation with time of the charge stored in the floating gate, the phenomena of disturbances at both the programming and the reading stage, and similar, each logical value is associated with a range of cell currents around the value stated above; these ranges are very narrow (for example ±1 µA), in such a way that the cell currents corresponding to different logical values are spaced sufficiently far apart from each other that it is possible to discriminate between them without error at the reading stage. Similar considerations are applicable in the case in which the logical value 0 is associated with a non-zero cell current, in which the difference between the cell current associated with two adjacent logical values is not fixed (for example with an upper value between the logical value 0 and the logical value 1), and in similar cases. The reading method 200 starts at the box 205 and then moves to the box 210 in which an initial actual current Is 1 (used as described in detail below) is set to be equal to the cell current Icell. The method then repeats the cycle described below for a number of times n = log 2 m. Every i-th cycle (where i = 1...n) starts at the box 215, in which a reference current Ir i is considered. The actual current Is i lies between the values associated with a minimum logical value Min and a maximum logical value Max; the reference current Ir i has a value lying preferably halfway between the currents associated with the median logical values (Max+1)/2-1 and (Max+1)/2. Next, in the box 220, the actual current Is i is compared with the reference current Ir i . If the actual current Is i is less than the reference current Ir i , the method proceeds to the box 227, in which a corresponding bit D i of the logical value stored in the cell is set to a first value, for example 0; if the actual current Is i is greater than the reference current Ir i , the method proceeds to the box 232, in which the corresponding bit D i of the logical value stored in the cell is set to a second value, for example 1. It should be noted that, owing to the way in which the reference current Ir i is set, there can never be a situation of equality between the actual current Is i and the reference current Ir i . In both cases, the method continues to the box 235, in which a check is made for the presence of the condition for output from the cycle, namely i = n. If the result is positive, the method proceeds to the box 240 (described below), while if it is negative the method goes to the box 237, in which the actual current for the next cycle Is (i+1) is set; in particular, the actual current for the next cycle Is (i+1) is set to be equal to the actual current Is i (if Is i < Ir i ), or equal to the value 2 · Ir i - Is i (if Is i > Ir i ). It should be noted that, preferably, as described in detail below, the actual current for the next cycle Is (i+1) is determined automatically by the actual current Is i and by the reference current Ir i , without the need for a decision and selection structure. The method then returns to the box 215 to repeat the cycle described above. During a first execution of the cycle defined by the boxes 215-237 (i=1), the actual current Is i lies between the values associated with the minimum logical value Min=0 and the maximum logical value Max=m-1, and therefore the reference current Ir 1 is set to a value lying halfway between the currents associated with the logical values (Max+1)/2-1=m/2-1 and (Max+1)/2=m/2 ; in the example in question, the reference current Ir 1 is set to a value lying halfway between Icell 7 =56µA and Icell 8 =64µA, in other words 60 µA. The actual current Is 2 for the next cycle is determined in such a way that the cell currents Icell j (where j=0...m/2-1) and Icell (m-j-1) (where m-j-1=m/2...m-1) disposed symmetrically about the reference current Ir 1 produce the same actual current Is 2 ; for example the cell current Icell 4 =32µA (corresponding to the logical value j=4) produces the actual current Is 2 =Is 1 =Icell 4 =32µA, and similarly the cell current Icell 11 =88µA (corresponding to the logical value m-j-1=16-4-1=11) produces the actual current Is 2 =2·Ir 1 -Is 1 =2·Ir 1 -Icell 11 =2·60-88=32µA. Consequently the actual current Is 2 will lie in every case between the values associated with the minimum logical value Min=0 and with the maximum logical value Max=m/2-1, so that the corresponding reference current Ir 2 is set to a value lying between the currents associated with the logical values (Max+1)/2-1=m/4-1 and (Max+1)/2=m/4 , and so on, making the method extremely simple and effective. It should be noted that the reference currents Ir i used in the various cycles have predetermined values which do not depend on the outcome of the preceding comparisons. For example, in the case considered above, Ir 1 =60µA, Ir 2 =28µA, Ir 3 =12µA and Ir 4 =4µA. The actual currents Is i and the bits D i for each logical value which can be stored in the cell in the example in question are represented in the following table: Value IS 1 IS 2 IS 3 Is 4 D 1 D 2 D 3 D 4 15 120 0 0 0 1 0 0 0 14 112 8 8 8 1 0 0 1 13 104 16 16 8 1 0 1 1 12 96 24 24 0 1 0 1 0 11 88 32 24 0 1 1 1 0 10 80 40 16 8 1 1 1 1 9 72 48 8 8 1 1 0 1 8 64 56 0 0 1 1 0 0 7 56 56 0 0 0 1 0 0 6 48 48 8 8 0 1 0 1 5 40 40 16 8 0 1 1 1 4 32 32 24 0 0 1 1 0 3 24 24 24 0 0 0 1 0 2 16 16 16 8 0 0 1 1 1 8 8 8 8 0 0 0 1 0 0 0 0 0 0 0 0 0 It is easy to check that the method described above generates a logical value represented in binary code of the Gray type (in which two adjacent encoded values differ from each other by the value of one bit only). If we now consider the box 240, the logical value in Gray code is converted into binary weighted code; alternatively, the logical value in Gray code is converted into a different code, for example ASCII or EBCDIC, or no conversion is carried out. The method then terminates at the end box 245. Similar considerations are applicable in cases in which a memory cell having a different number of levels (possibly not equal to a power of 2) is read, the actual current for the first cycle is set to another value, the actual current is compared with two or more reference currents in each cycle, the reference currents are set to other values, the actual current for the next cycle is determined in a different way (for example so that it equals the actual current, or the actual current minus the reference current, depending on the result of the comparison), or similar; in general, the reading method according to the present invention provides the steps of setting an actual physical quantity to a value correlated with the value of the physical quantity corresponding to the state of the memory cell, and of repeating, until the logical value corresponding to the state of the memory cell has been fully determined, a cycle comprising the steps of setting a component of the logical value to a value which is a function of a range in which the actual physical quantity lies, determined by comparing the actual physical quantity with at least one reference physical quantity having a predetermined value lying between a minimum value and a maximum value for the actual physical quantity, and setting the actual physical quantity for a possible successive cycle to a relative value of the actual physical quantity with respect to the range in which it lies. The method according to the present invention can be used to obtain a very high reading speed (slightly less than that of the known reading method of the parallel type). This is because the value of each reference electrical quantity is predetermined (and does not depend on the outcome of the preceding comparisons), the actual electrical quantities are obtained in an extremely simple way, and the various components of the logical value can be found without waiting until the preceding components have been determined. This method requires a smaller number of reference cells (log 2 m instead of m-1) and uses a correspondingly reduced number of comparison circuits. This results in a saving in terms of power consumption and of occupation of space in the chip. The solution according to the present invention is particularly advantageous in the case of a memory cell having a large number of levels (at least eight or sixteen, for example), although its use with a memory cell having any number of levels is not excluded. An example of a device which can be used to apply the reading method described above is illustrated in Fig. 3 (the elements previously shown in Fig. 1 are indicated with the same reference numbers or symbols). The reference circuit 140 includes n cells R i , each of which generates the corresponding reference current Ir i . Each reference cell R i consists of a floating-gate MOS transistor identical to those used for the memory cells (with the reference and memory cells formed in the same chip); this ensures an optimal reading accuracy, since it minimizes the differences (between memory and reference cells) caused by the manufacturing process and by variations in the operating and environmental conditions. The transistors of each reference cell R i have their source terminals connected to a common line set to the ground voltage during the reading operation, while the gate terminal is kept at a potential equal to that used to select the word lines (W 1 , W 2 in Fig. 1) of the memory structure. The drain terminal of the transistor of each reference cell R i is connected to a terminal of a switch SW i , the other terminal of which is connected to the conditioning circuit 120. Thus, in the reading stage, the reference cells R i and the selected memory cell are biased with substantially identical voltages. When the switches SW i are closed, each reference cell R i supplies a predetermined reference current Ir i , which is a function of the threshold voltage of the corresponding MOS transistor. The comparison circuit 130 includes n units S i , each of which receives at a reference input terminal INr i the corresponding current Ir i . These units are cascade connected, in such a way that each unit S i receives at an input terminal INs i the actual current Is i supplied by an output terminal OUTs (i-1) of the preceding unit S (i-1) ; the first unit S 1 receives at the input terminal INs 1 the first actual current Is 1 , which is equal to the cell current Icell, while the output terminal OUTs n of the last cell S n is not used. Each unit S i produces at a digital output terminal OUTd i the corresponding bit D i (in Gray code) of the logical value stored in the cell; these bits are supplied to corresponding input terminals of a converter unit (GRAY2BIN) 310. The converter unit 310 converts the logical value at the input from Gray code to binary code (if necessary), and supplies at its output terminals the bits b 0 , b 1 , ..., b n-1 representing the logical value LVcell. The circuit diagram of a preferred embodiment of a generic unit S i is shown in Fig. 4 (the elements previously shown in Fig. 3 are indicated by the same reference numbers or symbols). The input terminal INr i (to which the reference current Ir i is applied) is connected to an input terminal of a current generator unit 405. The unit 405 has two output terminals which supply (for example by means of suitable internal current mirror structures) the same reference current Ir i . The first output terminal of the unit 405 (junction A) is connected to the source terminal of an n-channel MOS transistor Mn1, and the second output terminal of the unit 405 (junction B) is connected to the source terminal of an n-channel MOS transistor Mn2. The gate terminal of the transistors Mn1 and Mn2 is connected to a unit 410 which generates a suitable voltage Vgs for the correct biasing of the transistors Mn1 and Mn2. The source terminal of the transistor Mn1 is also connected to the input terminal INs i (to which the actual current Is i is applied) and to a first terminal of a voltage comparator unit (COMP) 415, whose second terminal is connected to the digital output terminal OUTd i (which produces the corresponding bit D i , in Gray code, of the logical value stored in the memory cell). An n-channel MOS transistor Mn3 has its drain terminal and source terminal connected to junction A and junction B respectively. The transistor Mn3 is connected in diode configuration with the gate terminal short-circuited to the drain terminal; alternatively, other equivalent means with unidirectional conduction may be used. Preferably, an equalizing switch SWeq1 (formed by a MOS transistor or a pair of complementary MOS transistors, or similar) is also connected between the drain terminal and the source terminal of the transistor Mn3; similarly, an additional equalizing switch SWeq2 is preferably connected between the drain terminals of the transistors Mn1 and Mn2. The unit S i also includes a current mirror with a cascode structure, formed by four p-channel MOS transistors Mp1, Mp2, Mp3 and Mp4. In particular, the transistors Mp1 and Mp3 and the transistors Mp2 and Mp4 have their gate terminals in common; the source terminals of the transistors Mp1 and Mp3 are connected to the drain terminals of the transistors Mp2 and Mp4 respectively. The gate terminals of the transistors Mp1 and Mp2 are short-circuited to their drain terminals. The source terminals of the transistors Mp2 and Mp4 are connected to the positive terminal of a power supply Vdd (whose negative terminal is connected to the ground terminal). Preferably, the current mirror Mp1-Mp4 also includes a stand-by p-channel MOS transistor Mpsb1 whose source terminal and drain terminal are connected in short circuit to the source terminals and gate terminals of the transistors Mp2 and Mp4 respectively. The gate terminal of the transistor Mpsb1 is controlled (as described in detail below) by a suitable negated signal -SB. An additional current mirror formed by four n-channel MOS transistors Mn4, Mn5, Mn6 and Mn7 (with a stand-by n-channel MOS transistor Mnsb whose gate terminal is controlled by the signal SB), having a dual structure with respect to that described above, is cascade connected to the current mirror Mp1-Mp4. In particular, the drain terminal of the transistor Mn1 is connected to the drain terminal of the transistor Mp1 (the first branch of the current mirror Mp1-Mp4); the drain terminal of the transistor Mp3 (the second branch of the current mirror Mp1-Mp4) is connected to the drain terminal of the transistor Mn4 (the first branch of the current mirror Mn4-Mn7), and the drain terminal of the transistor Mn6 (the second branch of the current mirror Mn4-Mn7) is connected to the output terminal OUTs i (which supplies the actual current Is (i+1) for the next unit). The unit S i includes a similar current mirror with a cascode structure formed by four p-channel MOS transistors Mp5, Mp6, Mp7 and Mp8 (with a stand-by p-channel MOS transistor Mpsb2). The drain terminal of the transistor Mn2 is connected to the drain terminal of the transistor Mp5 (the first branch of the current mirror Mp5-Mp8) and the drain terminal of the transistor Mp7 (the second branch of the current mirror Mp5-Mp8) is connected to the output terminal OUTs i . The current mirrors with cascode structure described above provide a high accuracy of the mirror factor, in other words of the equality between the currents in their two branches. This ensures a very high overall accuracy of the reading device, which is particularly advantageous in the case of memory cells with a large number of levels. Alternatively, it is possible to use conventional current mirrors (with only one transistor in each branch), high-swing current mirror structures with high output resistance, as described for example in P.J. Crawley and G.W. Roberts, "High-swing MOS current mirror with arbitrarily high output resistance", Electronics Letters , Feb. 1992, v. 28, No. 4, pp. 361-363, where a high mirror factor accuracy with a low supply voltage (less than 5 V for example) is required, or other equivalent means. To explain the operation of the circuit described above, we shall consider a steady condition in which the equalizing switches SWeq1 and SWeq2 are open and in which the control signal SB is at a low level (with the dual control signal -SB at a high level), so that the stand-by transistors Mnsb and Mpsb1, Mpsb2 are cut off. In this situation, it is assumed that an actual current Is i which is lower than the reference current Ir i is applied to the input terminal INs i . Since the transistor Mn3 connected in diode configuration cannot conduct current from junction B to junction A, this transistor will be cut off, and the current (Ir i -Is i ) required for the correct balance of the currents at junction A will be supplied by the transistor Mn1. This current is mirrored by the structures Mp1-Mp4 and Mn4-Mn7, so that a current In6=I-r i -Is i will be present at the drain terminal of the transistor Mn6. The current which flows through the transistor Mn2 (since the transistor Mn3 is cut off) is equal to the reference current Ir i . This current is mirrored by the structure Mp5-Mp8, so that a current Ip7=Ir i will be present at the drain terminal of the transistor Mp7. The current supplied by the output terminal OUTs i will therefore be Is (i+1) =Ip7-In6=Ir i -(Ir i -Is i )=Is i . Let us now assume that an actual current Is i which is greater than the reference current Ir i is applied to the input terminal INs i . The current (Is i -Ir i ) required for the correct balance of the currents at the junction A will flow through the transistor Mn3 (the transistor Mn1 will therefore be cut off). Since the current passing through Mn1 is zero, the current In6 at the drain terminal of the transistor Mn6 will also be zero. The current flowing through the transistor Mn2 is equal to Iri -(Isi -Iri ) = 2·Iri -Isi . This current is mirrored by the structure Mp5-Mp8, and therefore there will be a current Ip7 = 2·Ir i -Is i at the drain terminal of the transistor Mp7. The current supplied by the output terminal OUTs i will therefore be Is (i+1) = Ip7-In6 = 2·Ir i -Is i . The voltage at the junction A varies with the value of the actual current Is i . More precisely, the voltage at the junction A will be higher when the actual current Is i is greater than the reference current Ir i (as a result of the voltage drop across the transistor Mn3 connected in diode configuration) and will be lower when the actual current Is i is less than the reference current Ir i . The comparator unit 415 generates at the output terminal OUTd i a binary value (0 or 1) which changes as a function of the value of the voltage at the junction A. Similar considerations are applicable in a case in which use is made of a current comparator, which receives at its input (through suitable current mirrors, for example) the actual current Is i and the reference current Ir i , or other equivalent means. The non-linear circuit structure described above is particularly simple and compact. Moreover, the actual current for the next unit is obtained automatically without the necessity for a true comparison operation and a subsequent selection, and therefore this circuit structure ensures a high overall operating speed. Similar considerations are applicable when the p-channel MOS transistors are replaced with n-channel MOS transistors (and vice versa), or when bipolar transistors, different non-linear circuit structures, and in general other equivalent reading devices, are used. The equalizing switches SWeq1 and SWeq2 are used to increase further the operating speed of the unit S i . In a time interval preceding the reading operation, for example during the stage of pre-charging of the memory cells and of the reference cells in which the unit S i cannot be used because the selected memory cell and the reference cells are not capable of supplying the corresponding current correctly, the equalizing switch SWeq1 and SWeq2 are closed. In this situation, the equalizing switch SWeq1 brings the junctions A and B substantially to the same voltage, while the switch SWeq2 makes the voltages at the drain terminals of the transistors Mn1 and Mn2 substantially equal. This causes an equalization of the unit S i , with the circuit in an optimal condition for its operation (similar considerations are applicable in the case in which the comparator unit 415 is also equalized). Consequently, when the equalizing switches SWeq1 and SWeq2 are open at the end of the pre-charging stage (so that they do not affect the operation of the circuit), the operation of the unit S i (in particular the generation of the actual current for the next unit Is (i+1) ) can be correctly executed in an extremely rapid way. This solution can be used to execute an operation of reading a memory cell rapidly as soon as it is required, for example as soon as a preceding reading has ended or even while the preceding reading is still in progress. The stand-by transistors Mpsb1, Mpsb2 and Mnsb are used to minimize the power consumption of the unit S i in the quiescent state, in other words when the operation of the reading device is not required. In this state, the control signal SB is at a high level (with the dual control signal -SB at a low level), so that the stand-by transistors Mpsb1, Mpsb2 and Mnsb are conducting. This ensures the substantial cancellation of the current flowing in the corresponding current mirror structures. To minimize the overall power consumption, in the quiescent state the reference currents Ir i generated by the unit 405 and the actual current Is i will be cancelled (the next actual currents will be zero, owing to the cancellation of the currents of the mirrors of the individual units). Clearly, a person skilled in the art may make numerous modifications and changes to the method for reading a multiple-level memory cell described above, in order to meet contingent and specific requirements, all these modifications and changes being included within the scope of protection of the invention as defined by the following claims.

Claims: Method (200) for reading a multiple-level memory cell (C 12 ) capable of taking on three or more states which are represented by different values of a physical quantity (Icell) and each of which is associated with a corresponding logical value (LVcell), the method comprising the step of: a) setting (210) an actual physical quantity (Is 1 ) to a value correlated with the value of the physical quantity (Icell) corresponding to the state of the memory cell (C 12 ), and being characterized by the further steps of: b) repeating (235), up to the complete determination of the logical value (LVcell) corresponding to the state of the memory cell (C 12 ), a cycle (215-237) comprising the steps of: b1) setting (227, 232) a component of the logical value (D i ) to a value which is a function of a range in which the actual physical quantity (Is i ) lies, determined by comparing (215, 220) the actual physical quantity (Is i ) with at least one reference physical quantity (Ir i ) having a predetermined value lying between a minimum value and a maximum value for the actual physical quantity (Is i ), and b2) setting (237) the actual physical quantity for a possible next cycle (Is (i+1) ) to a relative value of the actual physical quantity (Is i ) with respect to the range in which it lies in comparison with said reference physical quantity (Ir i ). Method (200) according to Claim 1, in which in the step a) the actual physical quantity (Is i ) is set (210) to be equal to the physical quantity (Icell) corresponding to the state of the memory cell (C 12 ). Method (200) according to Claim 1 or 2, in which the memory cell (C 12 ) can take on m = 2 n states and in which the step b) consists in repeating (235) the said cycle (215-237) for a number of times equal to n, the step b1) consisting in setting (227, 232) one bit of the logical value (D i ) to a first value (0) or to a second value (1) according to the result of a comparison (215, 220) between the actual physical quantity (Is i ) and a single reference physical quantity (Ir i ) having a value lying between two median values among the possible values of the actual physical quantity (Is i ). Method (200) according to Claim 3, in which the step b2) consists in setting (237) the actual physical quantity for the next cycle (Is (i+1) ) equal to the actual physical quantity (Is i ) if the actual physical quantity (Is i ) is less than the reference physical quantity (Ir i ) or equal to twice the reference physical quantity (Ir i ) minus the actual physical quantity (Is i ) if the actual physical quantity (Is i ) is greater than the reference physical quantity (Ir i ). Method (200) according to Claim 4, in which the actual physical quantity for the next cycle (Is (i+1) ) has the same value for actual physical quantities (Is i ) having a symmetrical value with respect to the reference physical quantity (Ir i ). Method (200) according to any of Claims 1 to 5, further comprising the step of converting (240) the logical value to a binary weighted value. Device (120, 130, 140) for reading a multiple-level memory cell (C 12 ) capable of taking on three or more states which are represented by different values of a physical quantity (Icell) and each of which is associated with a corresponding logical value (LVcell), the device (120, 130, 140) comprising means (120, 140) for generating a plurality of reference electrical quantities (Ir i ) and sensing means (130) for comparing a physical quantity (Icell) corresponding to the state of the memory cell (C 12 ) with the reference electrical quantities (Ir i ), characterized in that the sensing means (130) include a plurality of units (S i ) cascade connected, each being capable of receiving at its input an actual physical quantity (Is i ) from a preceding unit (S (i-1) ), a first unit (S 1 ) receiving at its input an actual physical quantity (Is 1 ) correlated with the physical quantity (Icell) corresponding to the state of the memory cell (C 12 ), and at least one reference electrical quantity (Ir i ) having a predetermined value lying between a minimum value and a maximum value of the actual physical quantity (Is i ), the unit (S i ) producing at its output a component of the logical value (D i ) which is a function of a range within which the actual physical quantity (Is i ) lies, determined by comparing the actual physical quantity (Is i ) with at least one reference electrical quantity (Ir i ), and an actual physical quantity (Is (i+1) ) for a possible next unit (S (i+1) ) equal to a relative value of the actual physical quantity (Is i ) with respect to the range within which it lies in comparison with said reference electrical quantity (Ir i ). Device (120, 130, 140) according to Claim 7, in which each unit (S i ) includes a non-linear circuit structure for automatically generating the actual physical quantity (Is (i+1) ) for the next unit (S (i+1) ). Device (120, 130, 140) according to Claim 7 or 8, in which the first unit (S 1 ) receives at its input the physical quantity (Icell) corresponding to the state of the memory cell (C 12 ). Device (120, 130, 140) according to any of Claims 7 to 9, in which the memory cell (C 12 ) can take on m = 2 n states and in which the sensing means (130) comprise n units (S i ), each unit (S i ) receiving at its input a single reference physical quantity (Ir i ) having a value lying between two median values between the possible values of the corresponding actual physical quantity (Is i ) and producing at its output a bit of the logical value (D i ) having a first value (0) or a second value (1) as a function of the result of a comparison between the actual physical quantity (Is i ) and the reference physical quantity (Ir i ). Device (120, 130, 140) according to Claim 10, in which each unit (S i ) produces at its output an actual physical quantity (Is (i+1) ) for the next unit (S (i+1) ) equal to the actual physical quantity (Is i ) if the actual physical quantity (Is i ) is less than the reference physical quantity (Ir i ) or equal to twice the reference physical quantity (Ir i ) minus the actual physical quantity (Is i ) if the actual physical quantity (Is i ) is greater than the reference physical quantity (Ir i ). Device (120, 130, 140) according to Claim 11, in which each unit (S i ) produces at its output an actual physical quantity (Is (i+1) ) for the next unit (S (i+1) ) having the same value for actual physical quantities (Is i ) having a symmetrical value with respect to the reference physical quantity (Ir i ). Device (120, 130, 140) according to any of Claims 7 to 12, further comprising means (310) for converting the logical value to a binary weighted value. Device (120, 130, 140) according to Claim 12 or 13, in which the actual physical quantity (Is i ) and the reference physical quantity (Ir i ) are currents, each unit (S i ) having a first input terminal (INr i ) and a second input terminal (INS i ) for receiving, respectively, the reference current (Ir i ) and the actual current (Is i ), a first output terminal (OUTs i ) and a second output terminal (OUTd i ) for supplying, respectively, the actual current (Is (i+1) ) for the next unit (S (i+1) ) and the corresponding bit of the logical value (D i ), and in which the unit (S i ) comprises means (405) connected to the first input terminal (INr i ) and to a first junction (A) and to a second junction (B) to apply the reference current (Ir i ) to the first junction (A) and to the second junction (B), the second input terminal (INs i ) being connected to the first junction (A), comparing means (415) connected between the first junction (A) and the second output terminal (OUTd i ) for generating the said bit (D i ), unidirectionally conducting means (Mn3) connected between the first junction (A) and the second junction (B), first current mirror means (Mp1-Mp4, Mn4-Mn7) and second current mirror means (Mp5-Mp8) connected between the first output terminal (OUTs i ) and the first junction (A) and the second junction (B) respectively. Device (120, 130, 140) according to Claim 14, in which the comparing means (415) include a voltage comparator for generating the said bit (D i ) as a function of a voltage value at the first junction (A). Device (120, 130, 140) according to Claim 14 or 15, in which the first current mirror means (Mp1-Mp4, Mn4-Mn7) include a first current mirror (Mp1-Mp4) and a second current mirror (Mn4-Mn7) with opposite polarity which are cascade connected together, and in which the second current mirror means (Mp5-Mp8) include a third current mirror (Mp5-Mp8). Device (120, 130, 140) according to Claim 16, in which the first current mirror (Mp1-Mp4), the second current mirror (Mn4-Mn7) and the third current mirror (Mp5-Mp8) have a cascode structure. Device (120, 130, 140) according to Claim 16 or 17, additionally comprising means (Mpsb1, Mpsb2, Mnsb) for cancelling the current in the first current mirror (Mp1-Mp4), the second current mirror (Mn4-Mn7) and the third current mirror (Mp5-Mp8) in a quiescent state of the device (120, 130, 140). Device (120, 130, 140) according to any of Claims 16 to 18, further comprising a first transistor (Mn1) and a second transistor (Mn2) connected, respectively, between the first junction (A) and the first current mirror (Mp1-Mp4) and between the second junction (B) and the third current mirror (Mp5-Mp8). Device (120, 130, 140) according to any of Claims 14 to 19, further comprising a first equalizing switch (SWeq1) connected between the first junction (A) and the second junction (B), the first equalizing switch (SWeq1) being in an open state during an operation of reading of the memory cell (C 12 ) and being in a closed state in a time interval preceding the reading operation. Device (120, 130, 140) according to Claim 19 or 20, further comprising a second equalizing switch (SWeq2) connected between a third junction common to the first transistor (Mn1) and to the first current mirror (Mp1-Mp4) and a fourth junction common to the second transistor (Mn2) and to the third current mirror (Mp5-Mp8), the second equalizing switch (SWeq2) being in an open state during an operation of reading the memory cell (C 12 ) and being in a closed state in a time interval preceding the reading operation. Memory structure (100) comprising at least one multiple-level memory cell (C 11 -C 22 ), means (110, 120) for selecting a memory cell (C 12 ) and supplying at the output a physical quantity (Icell) corresponding to the state of the memory cell (C 12 ), and at least one device (120, 130, 140) for reading the memory cell (C 12 ) according to any of Claims 7 to 21. Memory structure (100) according to Claim 22, in which each memory cell (C 11 -C 22 ) includes a floating-gate MOS transistor, each state of the memory cell (C 11 -C 22 ) being defined by a different threshold voltage of the floating-gate MOS transistor.

Inventors: MALOBERTI FRANCO, ONETO ANDREA, TORELLI GUIDO, MALOBERTI, FRANCO, ONETO, ANDREA, TORELLI, GUIDO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1998
Main classification: G11C11
IPC codes: G11C16, G11C11