Bidirectional electronic switch

Abstract: A guard circuit of a diagnostic output line (K-line) of a control unit (ECU) in the event of a ground (GND) disconnection or of a "below ground" condition, where the diagnostic output line (K-line) comprises a first interface DMOS transistor (MI) with a source connected to ground and a drain coupled to the diagnostic output lines (VOUT) through a second DMOS transistor (MP) with a source connected to the output line (VOUT) and a drain connected to the source of the first DMOS transistor (MI), a comparator (COMP) of the voltage (VOUT) of the diagnostic output line with the potential of the ground node (GND), a two-input logic (AND) gate (A1), with an input connected to the output of the comparator (COMP) and the other input coupled to the gate of said first DMOS transistor (MI), whose output controls a current generator (I) forcing a current, limited by a resistor (R), on the diagnostic output line (VOUT), the gate of the second DMOS transistor (MP) being coupled to the connection node between the generator (I) and the limiting resistor (R), employs a third MOS transistor (M) for switching off the second DMOS transistor (MP), functionally coupled in parallel to the resistor (R) and controlled by a line comprising a second current generator (I 1 ) controlled through an inverter (INV) by the output of the comparator (COMP) and forcing a current through a voltage divider (R 1 , R 2 ) on said diagnostic output line (VOUT). The intermediate node of the voltage divider is coupled to a gate of the third MOS transistor (M), and a third current generator (I 2 ) connected between the gate of the third transistor (M) and ground is controlled by the output of the comparator (COMP) in phase to the first current generator (I) and in phase opposition to the second current generator (I 1 ).

Description: FIELD OF THE INVENTION The present invention relates to circuits for protecting devices and circuits of electronic control units from accidental current overloads, and more in particular to a bi-directional electronic switch for enabling a diagnostic output line of a control unit with intrinsic capacities to avert accidental current injections through said diagnostic output line. BACKGROUND It is increasingly widespread the use of electronic control units (CPU) for controlling industrial processes equipments in a more precise manner than possible with traditional automatic, mechanic and/or electromechanic controllers of the functioning of the equipment or of a motor. These electronic control units generally provide also for a diagnostic interface of the operating conditions of the motor or of the device being controlled. These diagnostic functions require the presence of dedicated diagnostic output lines, to which may be coupled a suitable electronic testing apparatus. A typical example of these types of applications is the electronic control unit of the engine of a car or of similar means of transportation. Hence, the ensuing description refers to a generic motor's control unit (ECU) having one or more diagnostic output lines (K-lines) through which a tester may be coupled. These diagnostic lines may be useful to detect malfunctions and/or exploited to activate alarm or antitheft system, such as for example a so-called motor vehicle "immobilizer". A typical application scheme is shown in Fig. 1. The engine's control unit or simply the ECU may be represented by a resistive load R load (current being absorbed by the control unit) and by a capacitor load C load (electrolytic capacitors of large value usually connected in parallel to the control unit). The diagnostic output interface is a so-called the K-line that may be represented by an interfacing DMOS transistor MI for motor vehicles, the characteristics of these diagnostic interfaces are defined by the standard ISO 9141. The tester is generally represented by an electrical model composed of a mechanical switch and a pull-up resistance Rp, as in Fig. 1. A serious problem arises if the ECU is accidentally disconnected from ground, due to a false contact or to any other cause. In this case the only point that at that instant may be coupled to ground is a K-line output, through the switch (tester). An undue flow of the current absorbed by the ECU through such an output line must be averted in order to avoid damages to the interface device MI. DISCUSSION OF THE PRIOR ART A simple solution to this problem is to place a diode in series to the K-line output If by any cause a ground disconnection occurs, the diode is reverse biased so that the current cannot flow and thus the ECU is protected. The drawback of this known solution is the voltage drop on the guard diode which may reach about 1V during normal functioning conditions and therefore the minimum voltage at the output of the diagnostic line K-line becomes: Vdiode + Vdmos. Under certain circumstances, this condition may jeopardize a correct recognition of a logic zero. Another known solution is depicted in Fig. 3. In this case the diode is substituted by a guard DMOS transistor MP, the source of which is connected to the K-line output and the drain to the interface DMOS transistor MI that is used for communicating through the K-line. During normal operating conditions, the second guard DMOS transistor MP is turned on with a gate voltage, which in the illustrated example, is equal to R * I, through the comparator COMP of the output voltage VOUT, the logic AND gate A1, the controlled current generator I and the resistance R. The output voltage drop does not sensibly increase if the areas of the two power transistors MI and MP are properly dimensioned. Should a "below ground" potential or a ground disconnection occur during normal functioning, the comparator COMP turns off the current generator I. The voltage present on the gate of the DMOS MP decreases with a time constant τ=RC par ,DMOS, turning it off and impeding the passage of an inverse current through the interface DMOS transistor MI. In order to attain a low conduction resistance Ron, the two DMOS transistors should have a large area of integration, but this implies relatively large parasite capacitances (C par , Mos ), in the order of tens pF. By hypothesizing a parasite capacitance of 100pF, with R=10KΩ the time constant will be γ=1µs. The complete switch-off of the DMOS MP could occur after approximately 1.5τ. During this interval, a large inverse current that be of several amperes, flows through the DMOS transistor MP. This current is large because of a relatively low R load and because of a large C load that contributes to lower the impedance during the transients. A solution of the problem could be that of reducing as much as possible the resistance, but this would markedly increase the bias current of the circuit that, in modern applications, is required to be lower and lower. A below condition may occur also during normal functioning. The standard ISO 9141 considers that the diagnostic line K-line output may drop to -1V, as compared to the ground potential of the circuit. During the switch-off transient a portion of the inverse current cones from the integration substrate of the DMOS transistor MI, through the parasite diode D par . It is important to limit this current in order to prevent problems in other areas of the integrated circuit that may be caused by substrate currents. EP-A-0556663 discloses a switching power supply provided with below ground current sensing with current input to a comparator for controlling treshold. OBJECT AND SUMMARY OF THE INVENTION. It has now been found an efficient solution to the above cited problems and limitations of known circuits to the point of achieving an almost complete elimination of the inverse current during the transient of a "below ground" occurrence or an accidental ground disconnection, while minimizing at the same time minimizing the bias current of the protection or guard circuit. According to this invention, these benefits and advantages are attained using an additional MOS transistor for switching off a second DMOS guard transistor, during a "below ground" condition. This solution allows to have a time constant of two orders of magnitude lower than that possible with the known circuits where it is relatively high because of a value of the resistance R that cannot be lowered below a certain limit for other reasons. The circuit of the invention is defined in claim 1 and a particularly preferred embodiment is defined in claim 2. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a scheme representing a critical functioning condition of a control unit having a diagnostic line engaged by a testing apparatus, as described above. Figure 2 shows a known solution to protect the interface devices of a diagnostic line output, as described above. Figure 3 shows another known solution for protecting the interface devices of a diagnostic line. Figure 4 is a basic scheme of the guard circuit of the invention. Figure 5 shows an alternative embodiment of the guard circuit of the invention. DESCRIPTION OF SEVERAL EMBODIMENTS OF THE INVENTION By referring to the basic scheme of Fig. 4, a condition of "below ground" potential of the substrate of integration of the devices that form a diagnostic interface is detected by the comparator COMP which, through a logic AND gate A1, switches off the current generator I. Simultaneously, the current generator I2 that maintains the MOS transistor M in a state of high impedance during the normal functioning of the control unit is also switched off, while through the inverter Inv the current generator I 1 is switched on for determining immediately switching on the MOS transistor M. The circuit functions perfectly even during an accidental ground disconnection that may occur while the current path through the external tester's switch is closed and the capacitances, electronically in parallel to the ECU control unit, supply the circuits for a non negligible time. If a ground disconnection occurs, the MOS M is positively switched on in any case even though the load capacitance C load is completely discharged. In this case, the ground node GND of the control unit is at the voltage of the powering battery voltage and the circuit is unpowered. The parasite diode D par , schematically indicated in Figures 4 and 5, keeps the resistance R 1 connected to the substrate of integration. Therefore, the MOS transistor M is activated by virtue of the voltage drop on the resistance R 2 , which together with R 1 constitute a voltage divider between the substrate and the output node VOUT of the diagnostic line. In practice and preferably, both the resistor R and the resistor R 2 of the basic scheme of Fig. 3 may be functionally replaced by Zener diodes, as shown in Fig. 5. In this case, during normal functioning conditions, when the M transistor is off, the voltage on its gate node is lower by a VBE voltage than the source voltage of the same transistor M. Thence, the MOS transistor M is switched on even faster than in the case of the circuit of Fig. 4, whenever a "below ground" condition occurs. The stated goals are thus fulfilled by the guard circuit of the invention because, by comparison with the known circuit of Fig. 3, the circuit of the invention can minimize, to the point of a practically complete elimination, the inverse current flowing through diagnostic line during a transient in case of a "below ground" or ground disconnection condition of the circuits of the control unit and makes the dimensioning of the interface devices free from the above noted restraints allowing for a minimization of bias current levels.

Claims: Guard circuit of a diagnostic output line (K-line) of a control unit (ECU) in the event of a disconnection from ground (GND) of the circuits of said control unit or of a "below ground" condition, said diagnostic output line (K-line) comprising a first interface DMOS transistor (MI) with a source connected to ground and a drain coupled to said diagnostic output lines (VOUT) through a second DMOS transistor (MP) with a source connected to said diagnostic output line (VOUT) and a drain connected to the source of said first DMOS transistor (MI), a comparator (COMP) of the voltage (VOUT) of said diagnostic output line with the potential of the ground node (GND) of the circuits of said control unit, a two-input logic (AND) gate (A1), a first input connected to the output of the comparator (COMP) and a second input coupled to the gate of said first DMOS transistor (MI), whose output controls a current generator (I) forcing a current, limited by a resistor (R), on said diagnostic output line (VOUT), the gate of said second DMOS transistor (MP) being coupled to the connection node between said controlled current generator (I) and said limiting resistor (R), characterized in that it comprises further a third MOS transistor (M) for switching off said second DMOS transistor (MP), functionally coupled in parallel to said resistor (R) and controlled by a line comprising a second current generator (I 1 ) controlled through an inverter (INV) by the output of said comparator (COMP) and forcing a current through a voltage divider (R 1 , R 2 ) on said diagnostic output line (VOUT) the intermediate node of said voltage divider being coupled to a gate of said third MOS transistor (M), and a third current generator (I 2 ) connected between the gate node of said third transistor (M) and ground, controlled by the output of said comparator (COMP) in phase to said first current generator (I) and in phase opposition to said second current generator (I 1 ). The circuit according to claim 1, characterized in that said limiting resistance (R) and the branch (R 2 ) of said voltage divider between said diagnostic output line (VOUT) and said intermediate node are functionally substituted by respective Zener diodes (Z, Z 1 ).

Inventors: CHICCA STEFANIA, MILANESI ANDREA, MORELLI MARCO, POLETTO VANNI, CHICCA, STEFANIA, MILANESI, ANDREA, MORELLI, MARCO, POLETTO, VANNI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1998
Main classification: H02H1
IPC codes: H03K17, H01L27, H01L21