A coding/decoding method for high density data recording and reproduction

Abstract: In a coding/decoding method for high density data recording and reproduction a 16/17 RLL(0,6/6) coding/decoding method is improved by adopting an encoder/decoder (3,8) having a simplified structure. The invention also provides an optimal lookup table between input and output, for encoding/decoding the rate 16/17 RLL(0,6/6) block code, and a simplified relational equation between input and output.

Description: The present invention relates to an coding/decoding method for a high density data recording and reproduction, and more particularly, to a coding/decoding method for a high density data coding and reproduction in a partial response maximum likelihood (PRML) channel. Much research has been conducted on methods for recording data with a high density in a given storage capacity and transferring reliable information at high speed. In an effort to achieve high speed processing on large quantities of data in a data storage device, various methods relating to physical properties have been developed. The methods include improvement in the physical properties of a storage disk and in the precision of a data storing apparatus. Also, as an aspect of signal processing, a method of reducing data detection error, a method of increasing the recording density of a storage device by effective encoding and a method for facilitating detection of a reproduction signal have been proposed. Currently, due to the increase in the amount of data to be processed, much higher recording densities are required in storage devices. To achieve this objective, the data to be recorded in the storage device is encoded to increase the recording density and facilitate the detection of a reproduction signal. Also, as the recording density in the storage device increases, large quantities of useful information can be recorded on a storage disk having a predetermined size. Thus, an effective coding method is required such that the recording density is increased and detection of signals is facilitated, by applying less redundancy. In general, as a useful coding method for a storage device, there is a run length limited (RLL) method satisfying a (d,k) condition. The aim of this coding method is to reduce interference between signals while maintaining a self-clocking characteristic of a data signal. That is, according to the RLL(d,k) coding method, the number of successive "0"s between "1"s is limited to the minimum d and the maximum k. The former d is for facilitating signal detection, and the latter k is for maintaining the timing for restoring a reproduction signal. Typical coding methods using the RLL code include the rate 1/2 RLL(2,7) modulation code, rate 2/3 RLL(1,7) modulation code, rate 8/9 RLL(0,3) modulation code, and the rate 8/9 RLL(0,4/4) modulation code. In the rate 1/2 RLL(2,7) modulation code and rate 2/3 RLL(1,7) modulation code, the number of "0"s between "1"s is equal to 1 and 2, respectively. Accordingly, interference between signals is decreased while redundancy is high due to the low code rate. Also, since the value of "k" is comparatively smaller than those of the rate 8/9 RLL(0,3) and rate 8/9 RLL(0,4/4) modulation codes, it holds much timing information which is helpful in the operation of a phase locked loop (PLL). Generally, when recording or reproducing data on or from a storage device, a channel must be modeled similarly to an actual channel. Channel characteristics of the storage device can be expressed by the following equation (1). (1+D) n , or (1-D)(1+D) n where n = 1, . . ., 2. Partial response maximum likelihood (PRML) pre-codes input signal to provide controlled inter-symbol interference (ISI) between a current data and a previous data, and then modifies the same into the following target response (2), and data is detected using a Viterbi decoder. d k = a k + a k-1 or d k a k - a k-2 The PRML method exhibits excellent detecting capacity in a channel in which n=1. RLL codes with a "d" greater than zero are not necessary in PRML channels. Since the compensation for the ISI is inherent in the maximum likelihood (ML) detector, it is preferable to increase the channel signal-to-noise ratio (SNR) while reducing interference between signals by increasing the code rate, rather than by reducing the interference by coding which is dependent on d. Thus, the rate 8/9 RLL(0,4/4) coding and rate 16/17 RLL(0,6/6) coding methods are incorporated into the PRML method utilizing the interference between signals to improve performance while maintaining a high recording density and holding more timing information. Also, since the rate 8/9 RLL(0,3) coding and the rate 16/17 RLL(0,6/6) coding methods have a high code rate, a good effect is provided to an equalizer with respect to a given partial response class due to its higher channel SNR compared to the rate 1/2 RLL(2,7) coding or rate 2/3 RLL(1,7) coding method. If the data sequence of an input signal is divided into an even-bit subsequence and an odd-bit subsequence, ML detection is independently applied to each subsequence. Also, the number of continuous zeros in each subsequence causes a delay in detection, and limits the hardware size. The maximum number of continuous "0"s between "1"s required for each subsequence is called "k1". The condition of kl required for each subsequence is to reduce a path memory for the ML detector. The RLL(0,k/k1) modulation code satisfying the above condition is the rate 8/9 RLL(0,4/4) modulation code and the rate 16/17 RLL(0,6/6) modulation code. The rate 16/17 RLL(0,6/6) modulation code provides a higher rate than the rate 8/9 RLL(0,4/4) modulation code, and the recording can be performed on the data storage device with a much higher recording density. Thus, the rate 16/17 RLL(0,6/6) modulation code can be a proper coding method in PRML channels. However, in the conventional rate 16/17 RLL(0,6/6) modulation code, there is a problem in that the hardware size of an encoder and a decoder required is comparatively great. IBM Technical Disclosure Bulletin, Jan. 1989, Vol. 31, nr. 8, pages 21-23 "Rate 16/17 (0,6/6) Code" and pages 455-457 "High Rate (0,4) Code for Peak-Detect Channel" and EP-A-0 751 522 each disclose a Rate 16/17 coding process, in which a centre (or catenating) bit is introduced to enable mapping from 16 to 17 bits. P.H. Siegel and J.K. Wolf, "Modulation and Coding for Information Storage", IEEE Communications Magazine, vol. 29, nr. 12, December 1991 discloses PRML coding systems in general, and the use of RLL coders in such systems. According to a first aspect of the present invention there is provided a coding method for encoding a binary data symbol X k (k=1, 2, 3, ...) having 16 bits, received from a storage device or a communications channel, into a codeword Y l (l=1, 2, 3, ...) having 17 bits (l), the coding method comprising the steps of: (a) dividing the binary data symbol X k into first and second groups, one group comprising the odd bits and the other group comprising the even bits; (b) mapping the first group of 8 bits into a codeword (C) having 9 bits using a one-to-one mapping; and, (c) interleaving the second group with the mapped codewords, and outputting the result as the codeword Y l of 17 bits. The one-to-one mapping is defined by the table in claim 1. According to a second aspect of the present invention, there is provided a decoding method for decoding a codeword Y l (l=1, 2, 3, ...) having 17 bits (l), received from a storage device or a communications channel, into a binary data symbol X k (k=1, 2, 3, ...) having 16 bits (k), the decoding method comprising the steps of: (a) dividing the codeword Y l into one group comprising the odd bits and another group comprising the even bits, one of the groups comprising 8 bits and the other of the groups comprising 9 bits; (b) decoding the 9 bit group into a codeword (C) having a 8 bits using a one-to-one mapping; and, (c) deinterleaving the 8 bit group with the decoded codewords, and outputting the result as the binary data symbol X k . The one-to-one mapping is defined by the table in claim 4. In the present invention, an encoder/decoder adopting the coding/decoding method requires little hardware due to the relatively simplified structure of the method. Also, the present invention provides an optimal lookup table between an input and output with respect to the coding and decoding of the rate 16/17 RLL(0,6/6) block code, and a simplified relational equation between the input and output. An example of the present invention will be described in detail with reference to the accompanying drawings, in which: FIG. 1 is a block diagram showing the structure of an encoder/decoder for high density data recording and reproduction; and, FIG. 2 is a block diagram showing the structure of an encoder/decoder to which a coding/decoding method according to the present invention is applied. The present invention is designed to provide a coding/decoding method of a modulation code which is suitable for partial response (PR) channels for maximum likelihood (ML) detection. Such modulation code provides frequent non-zero samples, to improve the timing of a channel and the performance of a gain control circuit. Also, during the process by a Viterbi detector, paths are forcibly merged to reduce the capacity of a path memory, thereby limiting the complexity of the ML detector. A modulation code according to the present invention is expressed by three parameters d, k and k1. The parameters d and k represent the minimum run length and the maximum run length of each codeword, and the parameter k1 represents the maximum run length of zeros in an even-bit subsequence or an odd-bit subsequence. In the code of the present invention, the d constraint is "0". The reason for this is that the minimum run length of the zero values is not necessary in the PRML channel. The small k is required for precision in the timing and gain control, k1 reduces the size of a path memory required for the ML detectors. The k and k1 parameters with respect to the rate 16/17 RLL(0,k/k1) block are (0,6/6). The present invention provides a lookup table for coding/decoding the rate 16/17 block code having such parameters. Also, a simplified relational equation with respect to the coding/decoding is provided. FIG. 1 is a block diagram showing the structure of a coding/decoding system for high density data recording and reproduction the data. The operation of the system shown in FIG. 1 will be described as follows. A user data to be recorded on a storage device becomes protected against noises or other factors causing various kinds of signal distortion via a compression encoder 1 and an error correction encoder 2. Then the signal is coded by a run length limited (RLL) modulation encoder 3 which is suitable for the channel characteristics of the storage device. Then, the modulated data is input to a signal generator 4 to generate a signal, and pre-compensated for by a write equalizer 5 to be written on a head/disk composing a channel. The signal written on the head/disk are reproduced and then processed by a read equalizer 6 such that the signal is detected easily. Then, a signal is detected by a detector 7 to minimize an error probability. The signal detected by the detector 7 is restored into the original user data via an RLL modulation decoder 8 and an error correction decoder 9 and a compression decoder 10. FIG. 2 is a detailed block diagram of an encoding/decoding system using the coding/decoding method according to the present invention. In the system 20 shown in FIG. 2, the rate 16/17 RLL(0,6/6) codeword is used as a binary data to be written. The system 20 includes an encoder 24, a precoder 26, media & heads 28, an equalizer 30, a Viterbi detector 32 and a decoder 34. In FIG. 2, D 16 represents user data input in groups of 16 bits, and D 17 represents an encoded 17-bit codeword. In the system 20, the encoder 24 receives the input data D 16 in groups of 16 bits to encode the corresponding 17-bit codeword D 17 . The precoder 26 has a transfer function 1/(1⊕D) 2 which is appropriate for use in the partial response class 4 (PR 4), and the media & heads 28 has a media to be a partial response read signal channel and heads for reading the encoded data from the media and recording data thereon. Also, the decoder 34 decodes the 17-bit codeword D 17 into the user data D 16 in groups of 16 bits. In detail, the encoder 24 includes an input latch 40, an 8/9 RLL encoder 42, an output latch 44 and a parallel-to-serial converter 46. The input data D 16 input to the system 20 is divided into two groups of 8 bits each via the input latch 40. Here, supposing that the first group of 8 bits is "group A" and the second group of 8 bits is "group B", the groups A and B can be expressed as follows. A = [A 7 , A 6 , A 5 , A 4 , A 3 , A 2 , A 1 , A 0 ] B = [B 7 , B 6 , B 5 , B 4 , B 3 , B 2 , B 1 , B 0 ] The 8/9 RLL encoder 42 performs a logic function to map the group A into a 9-bit codeword C. C = [C 8 , C 7 , C 6 , C 5 , C 4 , C 3 , C 2 , C 1 , C 0 ] The output latch 44 interleaves the group B and the 9-bit codeword C to output a 17-bit codeword W which satisfies the given 16/17 RLL(0,6/6) code. W = [C 8 , B 7 , C 7 , B 6 , C 6 , C 5 , B 5 , C 4 , B 4 , C 3 , B 3 , C 2 , B 2 , B 1 , C 1 , B 0 , C 0 ] The parallel-to-serial converter 46 provides the 17-bit codeword W to the precoder 26, and the precoder 26 provides its output to the media & heads 28. Such encoded 17-bit codeword W is input to the equalizer 30 via the media & heads 28, and the equalizer 30 equalizes the signal to a desired target signal according to the PR4. Then, the signal goes through the Viterbi detector 32. The detected sequence is grouped by the serial-to-parallel converter 50 by as much as 17 bits. Then, each bit group is divided into 9 bits and 8 bits by the input latch 52. The first 9-bit group is decoded into an 8-bit data via the 9/8 RLL decoder 54, and the obtained 8-bit data is deinterleaved with one 8-bit group by the output latch 56, to output a 16-bit data as originally input. Each codeword W is divided into two subsequences: a first subsequence W 1 and a second subsequence W 2 . The first subsequence W 1 includes odd bits of 17-bit codeword W and the second subsequence W 2 includes even bits of the 17-bit codeword W, as follows. W 1 = [C 8 , C 7 , C 6 , B 5 , B 4 , B 3 , B 2 , C 1 , C 0 ] W 2 = [B 7 , B 6 , C 5 , C 4 , C 3 , C 2 , B 1 , B 0 ] In order to obtain 16/17 RLL(0,6/6), the first 8-bit group A must be effectively mapped into a 9-bit codeword C. That is, the 8/9 RLL encoder 42 must provide a 17-bit codeword W which satisfies the given constraints even in the worst case where the group B of the input 8-bit data includes all zeros. That is, in order to satisfy the condition in which d is equal to 0, and both K and k1 are equal to 6 in the RLL(0,k/k1) constraints, the codeword C encoded from the first 8-bit binary data must satisfy the following constraints. Here, "+" represents a logical OR operation, and "·" represents a logical AND operation. C 8 +C 7 +C 6 =1 C 1 +C 0 =1 C 7 +C 6 +C 5 +C 4 =1 C 6 +C 5 +C 4 +C 3 =1 C 3 +C 2 +C 1 = 1 C 4 +C 3 +C 1 =1 C 7 +C 6 +C 1 =1 There are 256 9-bit codewords satisfying the above constraints, which are provided in a hexadecimal form as shown in Table 1. 256 9-bit codewords satisfying the above constraints can be mapped on a one to one basis into the first 8-bit group A (2 8 ) one by one. Table 2 is a lookup table used to implement the 16/17 RLL(0,6/6) codeword, where the input-output relationship of the 8/9 RLL code is expressed as a hexadecimal number. In Table 2, "LS" represents the least significant digit, and "MS" represents the most significant digit. 250 codewords of Table 2 can be divided into six partition groups in order to simplify the Boolean logic equations. Here, capital letters G, H, J, K, L and M represent six partition groups, respectively. 1FF 1B2 155 0EF 09B 18E 1FW 1AD 14A 0F7 09A 18D 1FD 16D 153 0F6 099 0C9 1CF 19F 152 0F5 0E6 18B 1FB 19E 1AA 04F 097 18A 1FA 19D 16A 0F3 096 189 1F9 1C6 13F 0F2 095 0E9 1EF 19B 13E 0AF 046 1E7 1F7 19A 12F 06F 093 1C7 1F6 199 1C9 0DF 092 1A7 1F5 1E6 13B 0DE 0A6 049 14F 197 13A 0DD 066 167 1F3 196 12B 0CE 07F 147 1F2 195 1E9 0DB 07E 0A9 1AF 146 137 0DA 07D 069 16F 193 136 0D9 0CB 08F 1DF 192 127 0EE 07B 08E 1DE 1A6 149 0D7 07A 08D 1DD 166 133 0D6 079 0C5 1CE 17F 132 0D5 0EB 08B 1DB 17E 1A9 04E 077 08A 1DA 17D 169 0D3 076 089 1D9 1CB 11F 0D2 075 0E5 1EE 17B 11E 0AE 04B 0E7 1D7 17A 12E 06E 073 0C7 1D6 179 1C5 0BF 072 0A7 1D5 1EB 11B 0BE 0AB 045 14E 177 11A 0BD 06B 067 1D3 176 12A 0CD 05F 047 1D2 175 1E5 0BB 05E 0A5 1AE 14B 117 0BA 05D 065 16E 173 116 0B9 0CA 1BF 172 126 0ED 05B 1BE 1AB 145 0B7 05A 1BD 16B 113 0B6 059 1CD 15F 112 0B5 0EA 1BB 15E 1A5 04D 057 1BA 15D 165 0B3 056 1B9 1CA 0FF 0B2 055 1ED 15B 0FE 0AD 04A 1B7 15A 0FD 06D 053 1B6 159 0CF 09F 052 1B5 1EA 0FB 09E 0AA 14D 157 0FA 09D 06A 1B3 156 0F9 0C6 18F In a case of the first partition G, the first 4 bits and the last 4 bits of the first 8-bit group A are mapped into the first 4 bits and the last 4 bits of the 9-bit codeword C without any changes. Also, the middle bit, that is, the fifth bit of the cordword C is always "1". 148 9-bit codewords C belong to the partition G, which is as follows. G = (A 6 +A 5 ) · ((A 1 +A 0 ) · (A 3 + A 3 ·A 2 )+ A 3 · A 2 ·A 1 )+A 7 · A 6 · A 5 · A 1 The second partition H includes 48 9-bit codewords, which is as follows. H = A 2 · A 1 · ( A 3 + A 3 · A 0 ) The third partition J includes 32 9-bit codewords, which is as follows. J = A 2 · A 1 · A 0 The fourth partition K includes 32 9-bit codewords, which is as follows. K = A 7 · A 6 · A 5 ( A 3 · A 2 ·A 1 + A 3 · A 2 · (A 1 +A 0 )) The fifth partition L includes 32 9-bit codewords, which is as follows. L = A 7 · A 6 · A 5 · A 3 · (A 1 +A 0 ) The sixth partition M includes 32 9-bit codewords, which is as follows. M = A 7 · A 6 · A 5 ·(A 3 · A 2 · A 2 ) · A 1 · A 0 The Boolean logic equation of the 8/9 RLL encoder 42 for encoding A 7 ∼A 0 data bits into C 8 ∼C 0 codewords can be simplified by the six partitions of Table 2. The equation of the 8/9 RLL encoder 42, which is simplified by the six partitions G, H, J, K, L and M, is as follows. C 8 =G · A 7 + H · A 7 + J · A 7 + K · A 4 + L · A 4 +M C 7 =G · A 6 + H · (A 3 +A 0 ) + J · A 3 + K · A 3 + K · A 2 + L C 6 = G · A 5 + H · A 1 · A 0 + J + K · A 1 C 5 = G ·A 4 + H + K · A 0 + M C 4 =G C 3 = G · A 3 + H ·(A 5 +A 5 ) +J · (A 5 +A 4 ) + L + M · A 2 C 2 = G · A 2 + H · ( A 5 · A 4 + A 6 )+ J · ( A 5 · A 4 + A 6 ) + K + L · A 2 + M · A 2 C 1 =G·A 1 + H ·(A 5 +A 6 · A 5 · A 4 ) +J · (A 5 +A 6 · A 5 · A 4 )+ K + L · A 1 + M C 0 = G · A 0 + H · (A 4 + A 6 · A 5 ) + J · (A 4 + A 6 · A 5 )+ K + L · A 0 + M · A 4 Also, the Boolean logic equation of the 9/8 RLL decoder 54 can be expressed in a similar manner as the above, using six partitions G, H, J, K, L and M as follows. Each partition can be represented by codewords C 8 ∼C 0 , respectively. G=C 4 H=C 5 · C 4 (C 7 +C 6 ) · (C 3 +C 2 ) · (C 1 +C 0 ) · (C 3 + C 3 · ( C 1 + C 0 )) J=C 6 · C 5 · C 4 · (C 3 +C 2 ) · (C 1 +C 0 ) · (C 3 + C 3 · ( C 1 + C 0 )) K= C 4 · C 3 · C 2 · C 1 · C 0 · (C 6 +C 5 ) · (C 7 +C 6 ) L=C 7 · C 6 · C 5 · C 4 · C 3 · (C 1 +C 0 ) M=C 8 · C 7 · C 6 · C 5 · C 4 · (C 3 +C 2 ) · C 1 The Boolean logic equation of the 9/8 RLL decoder 54 for decoding 9-bit cordwords C 8 ∼C 0 into 8-bit data A 7 ∼A 0 can be simplified by the six partitions G, H, J, K, L and M of Table 2, as follows. A 7 =G · C 8 +H · C 8 + J · C 8 +M A 6 =G · C 7 + H · C 2 · (C 3 +C 1 )+J · C 2 · (C 3 +C 1 ) A 5 = G · C 6 + H · C 1 · (C 3 +C 0 )+J · C 1 · C 3 A 4 = G · C 5 +H · C 0 · (C 3 +C 1 ) +J · C 0 · C 3 + K · C 8 +M · C 0 A 3 = G · C 3 + H · C 7 · C 6 + J · C 7 +L+M · C 3 A 2 = G · C 2 + J + K · C 7 + L · C 2 + M · C 2 A 1 =G · C 1 +K · C 6 + L · C 1 A 0 =G · C 0 + H · C 6 + K · C 5 + L · C 0 + M In the method for mapping 8-bit data bits A 7 ∼A 0 into 9-bit codewords C 8 ∼C 0 based on the cordwards of Table 1, the logic equations of the 8/9 RLL encoder and 9/8 RLL decoder can be simplified by various methods. That is, a mapping logic equation which is different from the input/output mapping of the present invention may be used, and a logic gate circuit may be implemented at an optimum level based on the given logic equation of the present invention. The coding/decoding method of the present invention is simpler than the conventional rate 16/17 RLL(0,6/6) coding/decoding method, by adopting an encoder/decoder having a simple structure. Thus, the size of the hardware can be reduced. Also, the present invention provides an optimal lookup table between input and output, for encoding/decoding the rate 16/17 RLL(0,6/6) block code, and a simplified relational equation between input and output.

Claims: A coding method for encoding a binary data symbol X k (k=1, 2, 3, ...) having 16 bits, received from a storage device or a communications channel, into a codeword Y l (l=1, 2, 3, ...) having 17 bits (l), the coding method comprising the steps of: (a) dividing the binary data symbol X k into first and second groups, one group comprising the odd bits and the other group comprising the even bits; (b) mapping the first group of 8 bits into a codeword (C) having 9 bits using the following table for 8/9 RLL encoding: where LS represents the least significant digit, and MS represents the most significant digit; and (c) interleaving the second group with the mapped codewords, and outputting the result as the codeword Y l of 17 bits. The coding method of claim 1, wherein the mapped cordwords and the second groups are the same in the maximum run length. The coding method of any preceding claim, wherein the value of the maximum run length is equal to 6. A decoding method for decoding a codeword Y l (l=1, 2, 3, ...) having 17 bits (l), received from a storage device or a communications channel, into a binary data symbol X k (k=1, 2, 3, ...) having 16 bits (k), the decoding method comprising the steps of: (a) dividing the codeword Y l into one group comprising the odd bits and another group comprising the even bits, one of the groups comprising 8 bits and the other of the groups comprising 9 bits; (b) decoding the 9 bit group into a codeword (C) having a 8 bits using the following table for 8/9 RLL encoding: where LS represents the least significant digit, and MS represents the most significant digit; and (c) deinterleaving the 8 bit group with the decoded codewords, and outputting the result as the binary data symbol X k .

Inventors: KIM JIN-SOOK, KIM, JIN-SOOK
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1998
Main classification: H03M5
IPC codes: G11B20, H03M13, H03M5, H04L25, H03M7