Phase-locked loop with improved trade-off between lock-up time and power dissipation

Abstract: In a phase-locked loop with reference, feedback, and error signals, the trade-off between lock-up time and power dissipation is improved by one of the following methods: supplying a continuous error signal, instead of an intermittent error signal, to a charge pump during lock acquisition; employing a half-integer frequency divider and making multiple phase-and-frequency comparisons during each reference signal cycle; employing a prescaled feedback signal and making multiple phase-and-frequency comparisons during each reference signal cycle; providing multiple feedback loops and employing a selectable number of the loops during lock acquisition; and employing multiple feedback loops with prescaling of the reference and feedback signals.

Description: BACKGROUND OF THE INVENTION The present invention relates to a phase-locked loop combining rapid lock acquisition with low power dissipation. Phase-locked loops (PLLs) are widely used as frequency synthesizers in radio receivers and wireless telephone sets. A conventional PLL comprises a reference oscillator, a voltage-controlled oscillator, a programmable frequency divider, a phase detector, and a low-pass filter. Various types of phase detectors are known, including phase detectors employing charge pumps. A desirable capability in a PLL is the capability to lock onto new frequencies quickly. In certain types of wireless telephone sets, for example, the PLL needs to switch rapidly between the frequency of a traffic channel and the frequency of a control channel. Rapid frequency switching is also useful in radio receivers, for quick response to input from channel selection buttons. In a conventional PLL, however, the lock acquisition time or lock-up time is determined by parameters such as the loop gain, the time constant of the low-pass filter, and the reference frequency, which is normally equal to or less than the channel spacing. When parameters that give optimum performance in the locked state are selected, the lock-up time tends to be undesirably long. In PLLs with charge-pump phase detectors, a particular problem is that the phase detector generates error signals only intermittently. The lock-up time can be shortened by increasing the reference frequency to a value exceeding the channel spacing, but complex compensation circuitry then becomes necessary to receive channels with frequencies that are not integer multiples of the reference frequency. Unexamined Japanese Patent Publication No. 69794/1994 discloses a PLL that accelerates the acquisition of phase lock by generating a reset signal when the desired frequency is reached, but this reset signal does not shorten the time required to reach the desired frequency. The present inventor has proposed a PLL with multiple feedback loops, which shorten the entire lock-up process by increasing the loop gain, but these multiple feedback loops also increase the power dissipation of the PLL. Much of the power dissipated in a PLL is dissipated by the programmable frequency divider, which has a complex internal structure and operates at the same high frequency as the voltage-controlled oscillator. Complementary metal-oxide-semiconductor (CMOS) circuitry is commonly employed in the programmable frequency divider; power is dissipated by the rapid charging and discharging of a large number of capacitive loads in the CMOS circuits. A known method of reducing power dissipation is to prescale the signals output from the reference oscillator and input to the programmable frequency divider, but this method causes a proportionate lengthening of the lock-up time. In general, there is a trade-off between power dissipation and lock-up time in a PLL, one of these two characteristics being improved only at the expense of the other characteristic. A phase-locked loop frequency synthesizer according to the preamble part of claim 1 is known from US-A-5 254 959. This frequency synthesizer uses a fractionally frequency divider with frequency division ratio varying between N and N + 1. The output of the frequency divider is input to phase discriminators after passing delay elements with different delay times. Summary of the invention. It is accordingly an object of the present invention to reduce the lock-up time of a PLL without increasing the power dissipation. Another object of the invention is to reduce the power dissipation of a PLL without increasing the lock-up time. These objects are solved by the features of the main claim. Advantageous embodiments are mentioned in the subclaims. BRIEF DESCRIPTION OF THE DRAWINGS In the attached drawings: FIG. 1 is a block diagram illustrating a frequency synthesizer; FIG. 2 is a block diagram illustrating an embodiment of the invention; FIG. 3A is a block diagram of the programmable frequency divider in FIG. 2; FIG. 3B is a block diagram of the pulse distributor in FIG. 3A; FIG. 4 is a waveform diagram illustrating the operation of the programmable frequency divider in FIG. 3A; FIG. 5 is another waveform diagram illustrating the operation of the programmable frequency divider in FIG. 3A; FIG. 6A is a waveform diagram illustrating the operation of the embodiment; FIG. 6B is another waveform diagram illustrating the operation of the embodiment; FIG. 7 is a block diagram illustrating a variation of the programmable frequency divider in FIG. 2; FIG. 8 is a waveform diagram illustrating the operation of the programmable frequency divider in FIG. 7; FIG. 9 is another waveform diagram illustrating the operation of the programmable frequency divider in FIG. 7; DETAILED DESCRIPTION OF THE INVENTION Embodiments of the invention will be described with reference to the attached drawings. Referring to FIG. 1, a PLL having a reference signal generator 2 in which a reference divider (REF DIV) 4 divides the output frequency of a reference oscillator (REF OSC) 6 by a fixed ratio to produce a reference signal fr having a constant frequency. A voltage-controlled oscillator (VCO) 8 generates an output signal fo with a variable frequency controlled by a control voltage Cv. This output signal fo, which is the output signal of the PLL, is also supplied to a programmable frequency divider 10. The programmable frequency divider 10 is operable in two modes, as selected by a mode control signal Cm. In the first mode (Cm high), the programmable frequency divider 10 operates as a free-running counter, counting cycles of fo and generating a count value (n). In the second mode (Cm low), the programmable frequency divider 10 divides the frequency of fo by a programmable quantity N (for example, an integer such as one hundred) to generate a feedback signal fv, which is supplied to a phase detector (PD) 12. The phase detector 12 compares the reference signal fr and feedback signal fv, and generates two error signals, Pu 1 (pump-up) and Pd 1 (pump-down), both of which are active low. Pu 1 is activated when the feedback signal fv lags the reference signal fr in frequency or phase, going low from the rising edge of fr to the rising edge of fv, for example. Pd 1 is activated when the feedback signal fv leads the reference signal fr in frequency or phase, going low from the rising edge of fv to the rising edge of fr, for example. Only one of the two error signals Pu 1 and Pd 1 is active at a time. When fr and fv are locked in frequency and phase, Pu 1 and Pd 1 both remain inactive (high). The error signals Pu 1 and Pd 1 are supplied to a selector control circuit 14 that receives a similar pair of signals Pu 2 and Pd 2 from a control unit such as a microcontroller unit (MCU) 15. The selector control circuit 14 also receives the mode control signal Cm, selects Pu 1 and Pd 1 when Cm is low, selects Pu 2 and Pd 2 when Cm is high, and supplies the selected pair of signals as control signals Pu 3 and Pd 3 to a charge pump 16. The charge pump 16 generates an error current signal Ce that is positive when Pu is active, negative when Pd is active, and in the high-impedance state when Pu and Pd are both inactive. The error current signal Ce charges and discharges a capacitor (not visible) in a low-pass filter (LPF) 18, thus raising and lowering the output voltage of the low-pass filter 18. This output voltage is the control voltage Cv supplied to the VCO 8. The mode control signal Cm is generated by a frequency detection circuit 20 comprising a first latch 22, a second latch 24, a frequency estimator 26, and a comparator 28. The first latch 22 latches the count (n) output by the programmable frequency divider 10 at rising edges of the reference signal fr. The second latch 24 latches the contents of the first latch 22 at rising edges of the reference signal fr. The frequency estimator 26 takes the difference between the contents (n 1 ) of the first latch 22 and the contents (n 2 ) of the second latch 24, thereby determining the number of cycles n 3 of the output signal fo in one cycle of the reference signal fr. Operating according to settings made by the MCU 15, the comparator 28 compares n 3 with the programmable frequency division ratio N, and generates the mode control signal Cm. The mode control signal Cm is supplied to the programmable frequency divider 10 and selector control circuit 14 as noted above, and as a reset signal to the reference divider 4. The frequency division ratio N is programmed by the MCU 15 in response to, for example, manual input from frequency selection buttons (not visible) on a radio receiver, or instructions transmitted from a base station in a wireless communication system. Next, the operation of the first embodiment will be described. The symbols fr, fo, and fv denoting the reference, output, and feedback signals will occasionally also be used to denote the frequencies of these signals. When the mode control signal Cm is low and the PLL is in the locked state, the output frequency is N times the reference frequency. For example, if N is one hundred (N = 100) and the reference frequency is ten kilohertz (fr = 10 kHz), then the output frequency is one megahertz (fo = 1 MHz), and the feedback frequency fv is 10 kHz, matching the reference frequency fr. The error signals Pu 1 and Pd 1 generated by the phase detector 12, supplied through the selector control circuit 14 to the charge pump 16, operate to keep the feedback signal fv locked in frequency and phase with the reference signal fr. For example, if the feedback signal fv begins to lag the reference signal fr, then the pump-up error signals Pu 1 and Pu 3 go low for part of each cycle of the reference signal fr, causing the charge pump 16 to supply charge to the low-pass filter 18, thereby raising the control voltage Cv, increasing the output frequency fo, and moving the feedback signal fv back into lock with the reference signal fr. If the desired output frequency is changed to, for example, two megahertz (2 MHz), the MCU 15 calculates that the frequency division ratio N must be increased from one hundred to two hundred (N = 200), and sets this value of N in the programmable frequency divider 10. Since N has been increased, the MCU 15 activates the Pu 2 signal (Pu 2 goes low), deactivates Pd 2 (Pd 2 goes high), and sets the comparator 28 to output a high mode control signal Cm as long as n 3 is less than N. Cm immediately goes high, causing the selector control circuit 14 to select Pu 2 and Pd 2 for output as control signals Pu 3 and Pd 3 . Pu 2 and hence Pu 3 are continuously active, so the charge pump 16 supplies charge continuously to the low-pass filter 18, and the output frequency fo begins to rise rapidly. In addition, since Cm is high, the programmable frequency divider 10 begins to operate as a free-running counter. Following the next complete cycle of the reference signal fr, the frequency estimator 26 takes the difference between the count value (n 1 ) at the end of the cycle, latched in the first latch 22, and the count value (n 2 ) at the beginning of the cycle, latched in the second latch 24, and obtains a value of, for example, one hundred fifty (n 3 = 150). Although the programmable frequency divider 10 is not operating as a frequency divider, n 3 is nevertheless a frequency division ratio, giving an estimate of the frequency of the output signal fo divided by the frequency of the reference signal fr. The comparator 28 compares this measured frequency division ratio (n 3 ) with the desired frequency division ratio (N). Since n 3 is still less than N, the mode control signal Cm remains high, and the selector control circuit 14 continues to hold control signal Pu 3 in the continuously active state. At the end of the next cycle of the reference signal fr, the frequency estimator 26 again takes the difference between counts n 1 and n 2 , now obtaining, for example, a frequency division ratio n 3 of two hundred. Comparing n 3 with N, the comparator 28 finds that n 3 is not less than N, and drives the mode control signal Cm to the low level. The error signals Pu 1 and Pd 1 output by the phase detector 12 now begin to control the VCO frequency through the selector control circuit 14, the signals Pu 2 and Pd 2 from the MCU 15 being disregarded. At this point, the output frequency fo is close to the desired frequency (2 MHz). The high-to-low transition of the mode signal Cm causes the programmable frequency divider 10 to stop operating as a free-running counter and begin a new counting cycle lasting just N counts. A feedback pulse fv is output at the end of these N counts, and at every N counts thereafter, the programmable frequency divider 10 thus operating as a 1/N frequency divider (N = 200). The high-to-low transition of Cm also resets the reference divider 4, so that the reference divider 4 begins a new counting cycle at the same time as the programmable frequency divider 10. The reference signal fr and feedback signal fv are therefore mutually close in both phase and frequency. From this state, a locked state is quickly reached under control of the error signals Pu 1 and Pd 1 . Next, if a lower desired output frequency such as 1.1 MHz is selected, the MCU 15 calculates that the frequency division ratio must be decreased from two hundred to one hundred ten (N = 110), and sets this value of N in the programmable frequency divider 10. Since the value of N has been decreased, the MCU 15 deactivates the pump-up signal Pu 1 , activates the pump-down signal Pd 2 , and sets the comparator 28 to hold the mode control signal Cm high as long as the measured frequency division ratio (n 3 ) exceeds the new value of N. Cm immediately goes high, causing the programmable frequency divider 10 to begin operating as a free-running counter, and causing the selector control circuit 14 to select Pu 2 and Pd 2 . The selector control circuit 14 therefore deactivates Pu 3 and activates Pd 3 . The charge pump 16 withdraws charge continuously from the low-pass filter 18, and the output frequency fo begins to fall rapidly. Following the next complete cycle of the reference signal fr, the frequency estimator 26 takes the difference between the latched count values (n 1 and n 2 ) and obtains a frequency division ratio of, for example, one hundred fifty (n 3 = 150). The comparator 28 compares this value (n 3 ) with the desired value (N). Since n 3 still exceeds N, the mode control signal Cm remains high, and the selector control circuit 14 continues to hold Pd 3 in the continuously active state. At the end of the next cycle of the reference signal fr, the frequency estimator 26 again takes the difference between counts n 1 and n 2 , now obtaining, for example, a frequency division ratio n 3 of one hundred. Since this n 3 value does not exceed N, the comparator 28 drives the mode control signal Cm to the low level, allowing the error signals Pu 1 and Pd 1 output by the phase detector 12 to control the frequency of the VCO 8. At this point, the output frequency fo is less than but still close to the desired frequency (1.1 MHz). The high-to-low transition of the mode signal Cm resets the programmable frequency divider 10 and reference divider 4, so that both start counting in phase, the programmable frequency divider 10 now operating as a 1/110 frequency divider. From this state, a locked state is quickly reached under control of the error signals Pu 1 and Pd 1 . By supplying a continuous pump-up or pump-down signal during the early stages of lock acquisition, the first embodiment enables the output frequency fo to approach the desired frequency quickly. By resetting both the reference divider 4 and the programmable frequency divider 10 at the same time, the first embodiment also enables the final stages of lock acquisition to be completed quickly. By using the same programmable frequency divider both to measure and to divide the frequency of the VCO output signal, the first embodiment reduces hardware costs and avoids needless power dissipation. In a variation of the first embodiment, the signals Pu 2 and Pd 2 are supplied from external sources and switched on and off under control of the MCU 15, instead of being supplied by the MCU 15 itself. In another variation, the selector control circuit 14, the frequency detection circuit 20, or both the selector control circuit 14 and the frequency detection circuit 20 are integrated into the MCU 15. In a further variation, the frequency detection circuit measures the frequency division ratio of the output signal on the basis of more than two latched count values. In a still further variation, in the first mode, the programmable frequency divider 10 is reset at the beginning of each cycle of the reference signal fr. Next, a second embodiment will be described. Referring to FIG. 2, the embodiment according to the invention is a PLL frequency synthesizer comprising a VCO 8 controlled by a control voltage Cv from a low-pass filter 18. The VCO output signal fo enters a frequency divider unit 30 comprising a prescaler 32 that divides the VCO output frequency by two, and a programmable frequency divider 34 that is programmable to both integer values (N) and half-integer values (N + 1/2). Equivalently, the programmable frequency divider 34 divides the VCO output frequency by N/2, where N is a positive integer, even values of N giving integer frequency division ratios, and odd values of N giving half-integer ratios. The equivalent notation (N/2) is used below and in the drawings. The frequency divider unit 30 as a whole then divides the VCO output frequency by N, and distributes the resulting pulses among four feedback signals fv 1 , fv 2 , fv 3 , and fv 4 , which are passed through respective gate circuits 36, 38, 40, 42 to respective phase detectors 44, 46, 48, 50. The second embodiment also has a reference signal generator 51 comprising a reference oscillator 6 and delay circuits 52, 54, 56. The delay circuits have delay times equal to one-fourth of one cycle of the reference signal fr output by the reference oscillator 6. This signal fr is supplied as a first reference signal fr 1 to the first phase detector 44, delayed in delay circuit 52 and supplied as a second reference signal fr 2 to the second phase detector 46, further delayed in delay circuit 54 and supplied as a third reference signal fr 3 to the third phase detector 48, and delayed still further in delay circuit 56 and supplied as a fourth reference signal fr 4 to the fourth phase detector 50. Each of the four phase detectors 44, 46, 48, 50 is equivalent to the combination of phase detector 12 and charge pump 16 in the first embodiment. The first phase detector 44 compares fv 1 with fr 1 and generates a first error current signal Ce 1 , the second phase detector 46 compares fv 2 with fr 2 and generates a second error current signal Ce 2 , the third phase detector 48 compares fv 3 with fr 3 and generates a third error current signal Ce 3 , and the fourth phase detector 50 compares fv 4 with fr 4 and generates a fourth error current signal Ce 4 . The low-pass filter 18 receives the sum Ce of all four error current signals. The programmable frequency divider 34, gate circuits 36, 38, 40, 42, phase detectors 44, 46, 48, 50, and delay circuits 52, 54, 56 are controlled by a control unit such as a microcontroller unit (not visible). Referring to FIG. 3A, the programmable frequency divider 34 comprises an adder 58, a reloadable down-counter 60, a coincidence detector 62, D-type flip-flops 64, 66, 68, an inverter 70, a selector 72 comprising three NAND gates 74, 76, 78, and a pulse distributor 80. Reference characters A1 to A10 designate input and output signals of these circuit elements, A1 being the prescaled signal output by prescaler 32. Adder 58 adds a one-bit input received at input terminal A to bits (D1 to D4) representing the integer part of the frequency division ratio N, which are received at input terminals B. Down-counter 60 has clock (CLK), load, and data (D1 to D4) input terminals, and count (Q1 to Q4) output terminals. The clock input terminal receives the prescaled signal A1. The data input terminals receive the sum output by the adder 58, which is reloaded while the load input signal is high. The coincidence detector 62 comprises logic circuits (not visible) that determine whether the count output by down-counter 60 is equal to two. The flip-flops 64, 66, 68 have data (D) input terminals, clock (CLK) input terminals, and complementary (Q and Q ) output terminals. The D input is latched at rising edges of the clock input, and becomes the Q output signal. Flip-flop 64 also has a preset input terminal that receives the fraction part (bit D0) of the frequency division ratio. When the preset input is active (D0 = 1), the Q output of flip-flop 64 (A3) is held high, and the Q output (A4) is held low. Selector 72 selects the Q output of either flip-flop 66 (A5) or flip-flop 68 (A7) as an internal feedback signal (A10). The selection is made according to signals A3 and A4 from flip-flop 64. Various internal structures are possible for the pulse distributor 80. FIG. 3B shows one example, comprising a two-bit up-counter 81 and a delay circuit 82 that both receive the internal feedback signal A10, and a four-line decoder 83 that decodes the count (m) output by up-counter 81 and the delayed internal feedback signal (A10') output by delay circuit 82 to generate the four feedback signals fv 1 , fv 2 , fv 3 , and fv 4 . Delay circuit 82 has a fixed propagation delay equal to or greater than the propagation delay of up-counter 81. Decoder 83 drives fv 1 high when A10' is high and m is '01,' drives fv 2 high when A10' is high and m is '10,' drives fv 3 high when A10' is high and m is '11,' and drives fv 4 high when A10' is high and m is '00.' Next, the operation of the second embodiment will be described. When the desired output frequency is changed, the control unit sets a new frequency division ratio N/2 in the programmable frequency divider 34. To obtain a frequency division ratio N/2 equal to 11/2, for example, the control unit sets bits D0 to D4 in FIG. 3 to the binary value '01010' (the zero value of bit D0 designates a fractional value of one-half.) FIG. 4 illustrates the subsequent operation of the programmable frequency divider 34 by showing waveforms of signals A1 to A10 and fv 1 to fv 4 , and the value of the count (n) in down-counter 60. Each time n reaches two, the detector output signal A2 goes high, toggling flip-flop output signals A3 and A4; then flip-flop output signal A5 goes high, loading the value five, if A3 is high, or six, if A3 is low, into the down-counter 60. Due to a delay (not visible) from the rise of A1 to the rising and falling edges of A5, the loaded value appears in the down-counter 60 for almost two complete A1 cycles. The count (n) thus follows a repeating pattern with a length of eleven A1 cycles (n = 5, 5, 4, 3, 2, 6, 6, 5, 4, 3, 2, ...). The inverted signal A6 is delayed by one-half cycle from A1, so the output signal A7 of flip-flop 68 is delayed by one-half of one A1 cycle from A5. Due to the operation of NAND gates 74 and 76, low pulses appear in signal A8 when A3 and A5 are both high, and in signal A9 when A4 and A7 are both high. These low pulses are combined by NAND gate 78 as high pulses in the internal feedback signal A10, which goes high at regular intervals equal to five and one-half (11/2) A1 cycles. The A10 pulses are distributed cyclically, with a slight propagation delay, to feedback signals fv 1 , fv 2 , fv 3 , and fv 4 by the pulse distributor 80. FIG. 5 illustrates the operation of the programmable frequency divider 34 when the input data bits (D0 to D4) are '11010,' corresponding to a frequency division ratio of 10/2. Since D0 is '1' (designating a fractional value of zero), A3 is held high, A4 is held low, down-counter 60 is always loaded with the value (five) of bits D1 to D4, and signal A5 is always selected for output as the internal feedback signal A10, which goes high at regular intervals of five (10/2) A1 cycles. The A10 pulses are distributed to the feedback signals fv 1 , fv 2 , fv 3 , and fv 4 as in FIG. 4. The prescaled signal A1 has a frequency of fo/2. The internal feedback signal A10 has a frequency fo/N (fo/2 divided by N/2). The frequency of each of the feedback signals fv 1 , fv 2 , fv 3 , and fv 4 is fo/(4N). FIG. 6A illustrates the operation of the synthesizer when the desired output frequency fo is increased. The control unit sets a new frequency division ratio (N/2), activates delay circuits 52, 54, 56 so that all four reference signals are produced, closes gate circuits 36, 38, 40, 42, and disables the phase detectors 44, 46, 48, 50, so that the error current signals are all in the high-impedance state. At time T 1 , in synchronization with a rising edge of the first reference signal fr 1 , the control unit reloads the programmable frequency divider 34, opens the first gate circuit 36, and enables the first phase detector 44. The down-counter 60 in the programmable frequency divider 34 begins counting down at this time. At time T 2 , in synchronization with the following rising edge of the second reference signal fr 2 , the control unit opens the second gate circuit 38 and enables the second phase detector 46. At time T 3 , in synchronization with the following rising edge of the third reference signal fr 3 , the control unit opens the third gate circuit 40 and enables the third phase detector 48. At time T 4 , in synchronization with the following rising edge of the fourth reference signal fr 4 , the control unit opens the fourth gate circuit 42 and enables the fourth phase detector 50. The interval (Tref) from time T 1 to time T 5 corresponds to one cycle of the reference signal fr output by the reference oscillator 6. Reference signals fr 1 , fr 2 , fr 3 , and fr 4 are mutually offset one-fourth cycle (Tref/4), thus by phase angles of π/2 radians. During each fr cycle, four rising edges of the various reference signals occur. At time T 5 , the first phase detector 44 detects that the first feedback signal fv 1 lags the first reference signal fr 1 , and begins output of a positive error current signal Ce 1 . At time T 6 , the second phase detector 46 detects that the second feedback signal fv 2 lags the second reference signal fr 2 , and begins output of a positive error current signal Ce 2 . At time T 7 , the third phase detector 48 detects that the third feedback signal fv 3 lags the third reference signal fr 3 , and begins output of a positive error current signal Ce 3 . At time T 8 , the fourth phase detector 50 detects that the fourth feedback signal fv 4 lags the fourth reference signal fr 4 , and begins output of a positive error current signal Ce 4 . Output of these positive error current signals continuous intermittently thereafter, depending on the timing relationships between rising edges of the reference signals and feedback signals. Together, the four phase detectors compare the feedback signals and reference signals four times during each cycle of the reference signal fr output by the reference oscillator 6, different phase detectors making comparisons at different timings. During the early stages of lock acquisition, the combined error current signal Ce is continuously positive and large, leading to a rapid increase in the output frequency fo. The phase detectors 44, 46, 48, and 50 also generate signals (not visible) indicating when the locked state is reached. When lock is detected, the control unit closes gate circuits 36, 38, and 40, disables phase detectors 46, 48, 50, and disables delay circuits 52, 54, 56. The second, third, and fourth error current signals Ce 2 , Ce 3 , and Ce 4 are held in the high-impedance state. The locked state is then maintained under control of the first error current signal Ce 1 generated by the first phase detector 44, which continues to compare the first feedback signal fv 1 with the first reference signal fr 1 . FIG. 6B illustrates the operation when the frequency division ratio is decreased. Negative error current signals Ce 1 , Ce 2 , Ce 3 , and Ce 4 are produced, starting at the initial pulses of the four feedback signals fv 1 , fv 2 , fv 3 , and fv 4 . The combined error current signal Ce has a large negative value, causing the output frequency fo to decrease rapidly until the locked state is reached. In the locked state, feedback frequency fo/(4N) is equal to the reference frequency fr, and the output frequency fo is equal to 4N x fr. By using four reference signals, four feedback signals, and four error current signals, the second embodiment greatly reduces the lock-up time of the PLL. By obtaining all four feedback signals from the same programmable frequency divider 34, the second embodiment reduces the necessary amount of hardware, as compared with a PLL employing four programmable frequency dividers. By staggering the opening of gate circuits 36, 38, 40, and 42, the second embodiment enables the four phase detectors 44, 46, 48, and 50 to begin operating in similar phase relationships to their respective reference signals fr 1 , fr 2 , fr 3 , and fr 4 , so that all of the phase detectors generate positive error current signals, or all generate negative current error signals. By prescaling the VCO output signal fo before input to the programmable frequency divider 34, the second embodiment reduces the power dissipation of the programmable frequency divider 34. In particular, the power dissipation of the down-counter 60 is reduced. Similarly, the embodiment enables the VCO output frequency to be twice the maximum operating frequency of the programmable frequency divider 34. By employing a programmable frequency divider 34 with the capability to divide frequency by half-integer ratios (N/2), the second embodiment increases the number of output frequencies that can be generated. In the embodiment as described above, the available output frequencies are integer multiples of four times the reference frequency (4N x fr). The second embodiment can be modified as follows, however, to obtain arbitrary integer multiples of the reference frequency. If data bit D0 is suitably manipulated, the programmable frequency divider 34 can be made to alternate between the operation shown in FIG. 4 and the operation shown in FIG. 5. For example, if bit D0 is manipulated so that down-counter 60 is reloaded with a value of six in one out of every eight counting cycles, and with a value of five in the other seven counting cycles, a total counting cycle with a length of forty-one A1 periods, or eighty-two fo periods, is obtained. During this total cycle, two pulses appear in each of the four feedback signals, giving each feedback signal a frequency of fo/41. Feedback frequencies from fo/42 to fo/47 can be obtained by reloading down-counter 60 with a value of six in two to seven of every eight counting cycles. Feedback frequencies of fo/M, where M is any positive integer, are obtainable in a similar way. The necessary manipulations can be performed by the control unit, but are preferably performed in the programmable frequency divider 34 itself, by an additional circuit that, for example, uses bit D0 and the output (m) of the two-bit up-counter 81 in FIG. 3B to manipulate the A input to adder 58 and the inputs to selector 72, replacing flip-flop 64 in FIG. 3A. The required circuit modifications can be made in various ways, detailed descriptions of which will be omitted. FIG. 7 shows a variation of the programmable frequency divider 34, in which bits D1 to D4 are supplied directly to the down-counter 60. The coincidence detector 62, flip-flops 66 and 68, inverter 70, selector 72, and pulse distributor 80 are identical to the corresponding elements in FIG. 3A, and are interconnected in the same way. Additional flip-flops 84 and 86 and an additional selector 88 are also provided. The Q output terminal of flip-flop 66 is coupled to the D input terminal of flip-flop 84, the output of which is coupled to the clock input terminal of flip-flop 86. Bit D0 is provided to the preset input terminal of flip-flop 86. The Q output of flip-flop 86 is coupled to the D input of flip-flop 86, causing flip-flop 86 to operate as a toggle flip-flop. Selector 88 selects the Q output (A11) of flip-flop 66 or the Q output (A12) of flip-flop 84 according to the Q output (A13) and Q output of flip-flop 86. The selected signal (A14) becomes the load signal input to the down-counter 60. Reloading occurs while A14 is low. Selector 72 uses the outputs of flip-flop 86 to select the Q output (A5) of flip-flop 66 or the Q output (A7) of flip-flop 68 as the intermediate feedback signal A10. This variation operates as illustrated in FIG. 8, which shows the case in which bit D0 is low, and FIG. 9, which shows the case in which bit D0 is high. A detailed description of the operations will be omitted, as they are similar to the operations shown in FIGs. 4 and 5. Like the circuit in FIG. 3A, the circuit in FIG. 7 generates an internal feedback signal A10 with a frequency of fo/N, and feedback signals fv 1 , fv 2 , fv 3 , and fv 4 with frequencies of fo/(4N). This circuit can also be modified to provide feedback signals fv 1 , fv 2 , fv 3 , and fv 4 with frequencies of fo/M, where M is an arbitrary integer, by suitable control of the inputs to selectors 72 and 88. Incidentally, the propagation delay of inverter 70 causes a slight jitter in the internal feedback signal A10 when bit D0 is low, in the circuits in both FIGs. 3A and 7. Analysis by the inventor has shown, however, that if the propagation delay of inverter 70 does not exceed one hundred nanoseconds (100 ns), the jitter is negligible. In another variation of this embodiment, the prescaler 32 is omitted, enabling the reference frequency to be doubled to shorten the lock-up time. The embodiments described above reduce lock-up time without increasing power dissipation in the locked state, or reduce power dissipation without increasing lock-up time. Several variations of these embodiments have been mentioned, but those skilled in the art will recognize that further variations are possible within the scope of the invention as claimed.

Claims: A phase-locked loop frequency synthesizer generating an output signal locked in phase with a reference signal, comprising: a frequency divider (34) generating a feedback signal by dividing said output signal by a frequency division ratio of N and/or N + 1/2; a first phase detector (44) comparing a phase of said feedback signal and a phase of said reference signal at a first timing and generating a first error signal; a second phase detector (46) comparing a phase of said feedback signal and a phase of said reference signal at a second timing and generating a second error signal; and a voltage-controlled oscillator (8) generating said output signal according to said first error signal and said second error signal, characterized in that said voltage-controlled oscillator (8) generates said output signal according to both said first error signal and said second error signal until said output signal reaches a desired frequency, then generates said output signal according to said first error signal. The phase-locked loop frequency synthesizer of claim 1, wherein N is an arbitrary integer. The phase-locked loop frequency synthesizer of claim 1, wherein said frequency divider (34) is programmable. The phase-locked loop frequency synthesizer of claim 1, wherein: said reference signal has cycles; said first phase detector (44) compares said feedback signal with said reference signal at said first timing in each of said cycles of said reference signal; and said second phase detector (46) compares said feedback signal with said reference signal at said second timing in each of said cycles of said reference signal. The phase-locked loop frequency synthesizer of claim 1, wherein said feedback signal has pulses, and said frequency divider (34) comprises a pulse distributor (80) distributing different pulses of said feedback signal to said first phase detector (44) and said second phase detector (46). The phase-locked loop frequency synthesizer of claim 1, further comprising a prescaler (32) coupled between said voltage-controlled oscillator (8) and said frequency divider (34), dividing said output signal by a fixed frequency division ratio. The phase-locked loop frequency synthesizer of claim 6, wherein said fixed frequency division ratio is two. The phase-locked loop frequency synthesizer of claim 1, further comprising: a first gate circuit (36) coupled between said frequency divider (34) and said first phase detector (44), initiating supply of said feedback signal to said first phase detector in synchronization with said first timing in a first cycle of said reference signal; and a second gate circuit (38) coupled between said frequency divider (34) and said second phase detector (46), initiating supply of said feedback signal to said second phase detector in synchronization with said second timing in said first cycle of said reference signal. The phase-locked loop frequency synthesizer of claim 8, wherein said second gate circuit (38) stops supplying said feedback signal to said second phase detector (46) when said feedback signal is locked in frequency and phase with said reference signal.

Inventors: SUMI YASUAKI, SUMI, YASUAKI, Sumi, Yasuaki Tottori Sanyo Electric Co., Ltd.
Applicants: SANYO ELECTRIC CO, TOKYO SANYO ELECTRIC CO, SANYO ELECTRIC CO., LTD., TOTTORI SANYO ELECTRIC CO., LTD.
Application year: 1998
Main classification: H03L7
IPC codes: H03L7, H03K23