A TAILORED BARRIER LAYER WHICH PROVIDES IMPROVED COPPER INTERCONNECT ELECTROMIGRATION RESISTANCE

Abstract: Disclosed herein is a barrier layer structure useful in forming copper interconnects and electrical contacts of semiconductor devices. The barrier layer structure comprises a first layer of TaNx which is applied directly over the substrate, followed by a second layer of Ta. The TaNx/Ta barrier layer structure provides both a barrier to the diffusion of a copper layer deposited thereover, and enables the formation of a copper layer having a high {111} crystallographic content so that the electromigration resistance of the copper is increased. The TaNx layer, where x ranges from about 0.1 to about 1.5, is sufficiently amorphous to prevent the diffusion of copper into the underlying substrate, which is typically silicon or a dielectric such as silicon dioxide. The thickness of the TaNx and Ta layers used for an interconnect depend on the feature size and aspect ratio; typically, the TaNx layer thickness ranges from about 50 ANGSTROM to about 1,000 ANGSTROM , while the Ta layer thickness ranges from about 20 ANGSTROM to about 500 ANGSTROM . For a contact via, the permissible layer thickness on the via walls must be even more carefully controlled based on feature size and aspect ratio; typically, the TaNx layer thickness ranges from about 10 ANGSTROM to about 300 ANGSTROM , while the Ta layer thickness ranges from about 5 ANGSTROM to about 300 ANGSTROM . The copper layer is deposited at the thickness desired to suit the needs of the device. The copper layer may be deposited using any of the preferred techniques known in the art. Preferably, the entire copper layer, or at least a "seed" layer of copper, is deposited using physical vapor deposition techniques such as sputtering or evaporation, as opposed to CVD or electroplating. Since the crystal orientation of the copper is sensitive to deposition temperature, and since the copper may tend to dewet/delaminate from the barrier layer if the temperature is too high, it is important that the copper be deposited and/or annealed at a temperature of less than about 500 DEG C, and preferably at a temperature of less than about 300 DEG C.

Description: A TAILORED BARRIER LAYER WHICH PROVIDES IMPROVED COPPER INTERCONNECT ELECTROMIGRATION RESISTANCE BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention pertains to a particular TaN x Ta barrier/wetting layer structure which increases the degree of { 111 } crystal orientation in an overlying copper layer, thereby providing improved electromigration resistance of the copper. 2. Brief Description of the Background Art As microelectronics continue to miniaturize, interconnection performance, reliability, and power consumption has become increasingly important, and interest has grown in replacing aluminum alloys with lower-resistivity and higher-reliability metals. Copper offers a significant improvement over aluminum as a contact and interconnect material. For example, the resistivity of copper is about 1.67 μΩcm, which is only about half of the resistivity of aluminum. There are two principal competing technologies under evaluation by material and process developers working to enable the use of copper. The first technology is known as damascene technology. In this technology, a typical process for producing a multilevel structure having feature sizes (i. e. , width of the aperture) in the range of 0.5 micron (μm) or less would include: blanket deposition of a dielectric material; patterning of the dielectric material to form openings; deposition of a diffusion barrier layer and, optionally, a wetting layer to line the openings; deposition of a copper layer onto the substrate in sufficient thickness to fill the openings; and removal of excessive conductive material from the substrate surface using chemical-mechanical polishing (CMP) techniques. The damascene process is described in detail by C. Steinbruchel in "Patterning of copper for multilevel metallization: reactive ion etching and chemical- mechanical polishing", Applied Surface Science 91 (1995) 139 - 146. The competing technology is one which involves the patterned etch of a copper layer. In this technology, a typical process would include deposition of a copper layer on a desired substrate (typically a dielectric material having a barrier layer on its surface); application of a patterned hard mask or photoresist over the copper layer; pattern etching of the copper layer using wet or dry etch techniques; and deposition of a dielectric material over the surface of the patterned copper layer, to provide isolation of conductive lines and contacts which comprise various integrated circuits. Typically, the copper layer can be applied using sputtering techniques well known in the art. The sputtering of copper provides a much higher deposition rate than evaporation or CVD (chemical vapor deposition) and provides a purer copper film than CVD. In integrated circuit interconnect structures where copper is the material used to form conductive lines and contacts, it is recognized that copper diffuses rapidly into adjacent layers of SiO 2 and silicon and needs to be encapsulated. Gang Bai et al. in "Copper Interconnection Deposition Techniques and Integration", 1996 Symposium on VLSI Technology, Digests of Technical Papers (0-7803-3342-X/96, IEEE), describe the effectiveness of Ta, TiN, W and Mo as barrier layers for use with copper. They concluded that Ta annealed in UHV (ultra high vacuum) after copper deposition provided the best barrier layer. Sputtered copper appeared to be preferable over CVD copper and over electroplated copper, although all the data for electroplated copper was not available at the time of presentation of the paper. SUBSTITUTE SHEET (RULE 2B) U.S. Patent No. 4,319,264 of Gangulee et al., issued March 9, 1982 and titled "Nickel-gold-nickel Conductors For Solid State Devices" discusses the problem of electromigration in solid state devices. In particular, the patent discusses the application of direct current over particular current density ranges which induces motion of the atoms comprising the thin film conductor, the effect known as electromigration. Electromigration is said to induce crack or void formation in the conductor which, over a period of time, can result in conductor failure. The rate of electromigration is said to be dependent on the current density imposed on the conductor, the conductor temperature, and the properties of the conductor material. In high current density applications, potential conductor failure due to electromigration is said to severely limit the reliability of the circuit. In discussing the various factors affecting performance of the conductive materials, grain structure is mentioned as being important. (In order to obtain adequate lithographic line width resolution, it is recommended that the film be small grained, with a grain size not exceeding about one-third of the required line width.) Uniformity of grain size and preferred crystallographic orientation of the grains are also said to be factors which promote longer (electromigration limited) conductor lifetimes. Fine grained films are also described as being smoother, which is a desirable quality in semiconductor applications, to lessen difficulties associated with covering the conductor with an overlayer. U.S. Patent No. 5,571,752 to Chen et al., issued November 5, 1996, discloses a method for patterning a submicron semiconductor layer of an integrated circuit. In one embodiment describing an aluminum contact, titanium or titanium nitride having a thickness of between approximately 300 and 2,000 A is formed by sputter deposition to reach the bottom of a contact opening. Finally, a second conductive layer, typically aluminum, is applied over the surface of the conformal conductive layer. The aluminum is sputtered on, preferably at a temperature ranging between approximately 100°C and 400°C. This method is said to make possible the filling of contact openings having smaller device geometry design requirements by avoiding the formation of fairly large grain sizes in the aluminum film. As described in U.S. Patent Application Serial No. 08/824,911, of Ngan et al., filed March 27, 1997 and commonly assigned with the present invention, efforts have been made to increase the {111 } crystallographic content of aluminum as a means of improving electromigration of aluminum. In particular, the {111 } content of an aluminum layer was controlled by controlling the thickness of various barrier layers underlying the aluminum layer. The underlying barrier layer structure was Ti/TiN/TiN x , which enabled aluminum filling of high aspect vias while providing an aluminum fill exhibiting the high degree of aluminum {111 } crystal orientation. The Ti TiN/TiN x barrier layer was deposited using IMP (ion metal plasma) techniques, and the barrier layer thicknesses were as follows. The thickness of the first layer of Ti ranges from greater than about 100 A to about 500 A (the feature geometry controls the upper thickness limit). The thickness of the TiN second layer ranges from greater than about 100 A to less than about 800 A (preferably, less than about 600 A). And, the TiN x third layer (having a Ti content ranging from about 50 atomic percent titanium to about 100 atomic percent titanium) ranges from about 15 A to about 500 A. A Ti/TiN/TiN x barrier layer having this structure, used to line a contact via, is described as enabling complete filling of via with sputtered warm aluminum, where the feature size of the via or aperture is about 0.25 micron or less and the aspect ratio ranges from about 5 : 1 to as high as about 6 : 1. Subsequently, in U.S. Patent Application Serial No. 08/924,487, of Ngan et al., filed August 23, 1997 (Docket No. 1987), the inventors disclose that to maintain a consistently high aluminum {111 } crystal orientation content of an interconnect during the processing of a series of semiconductor substrates in a given process chamber, it is necessary to form the first deposited layer of the barrier layer to a minimal thickness of at least about 150 A, to compensate for irregularities in the crystal orientation which may be present during the initial deposition of this layer when the process chamber is initially started up (and continuing for the first 7 - 8 wafers processed). Ngan et al. teach that in the case of a copper conductive layer, it may also be necessary that the first layer of a barrier layer structure underlying the copper layer have a minimal thickness of at least about 150 A, to enable a consistent crystal orientation within the copper layer during the processing of a series of wafers in a semiconductor chamber. SUMMARY OF THE INVENTION We have discovered that tantalum nitride (TaN x ) is a better barrier layer for copper than tantalum (Ta). However, copper deposited directly over TaN x does not exhibit a sufficiently high degree of { 111 } crystal orientation to provide the desired copper electromigration characteristics. We have developed a barrier layer structure comprising a layer of Ta overlying a layer of TaN x which provides both a barrier to the diffusion of a copper layer deposited thereover, and enables the formation of a copper layer having a high {111 } crystallographic content, so that copper electromigration resistance is increased. The TaN x layer, where x ranges from about 0.1 to about 1.5, is sufficiently amorphous to prevent the diffusion of copper into underlying silicon or silicon oxide surfaces. The desired thickness for the TaN x layer is dependent on the device structure. For a typical interconnect, the TaN x layer thickness ranges from about 50 A to about 1 ,000 A. For a contact, the TaN x layer, the thickness on the wall of a contact via ranges from about 10 A to about 300 A, depending on the feature size. The TaN x layer is preferably deposited using standard reactive ion sputtering techniques at a substrate temperature ranging from about 20°C to about 500°C. However, ion deposition sputtering techniques may be used to deposit this layer. The Ta layer deposited over the TaN x layer has a desired thickness ranging from about 5 A to about 50θA, wherein the thickness is preferably greater than about 20 A, depending on the feature size. The Ta layer is preferably deposited using standard ion sputtering techniques at a substrate temperature ranging from about 20 °C to about 500°C. However, ion deposition sputtering techniques may be used to deposit this layer. The copper layer is deposited at the thickness desired to suit the needs of the device. The copper layer may be deposited using any of the preferred techniques known in the art. Preferably, the entire copper layer or at least a "seed" layer of copper is deposited using physical vapor deposition techniques such as sputtering or evaporation, as opposed to CVD. Since the crystal orientation of the copper is sensitive to deposition temperature, it is important that the maximum temperature of the copper either during deposition or during subsequent annealing processes not be higher than about 500 °C. Preferably, the maximum temperature is about 300 °C. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a schematic of a cross sectional view of a sputtering chamber of the kind which can be used to deposit the barrier layer of the present invention. Figure 2 shows a graph representative of the copper {111 } crystal orientation on a TaN x /Ta barrier layer as a function of the thickness of the Ta layer, with the TaN x layer held constant at about 500 A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present disclosure pertains to a TaN x /Ta/Cu structure and a method of creating that structure. The TaN x /Ta barrier layer structure enables the deposition of an overlying copper layer having a high { 111 } crystallographic content, so that electromigration resistance of the copper is increased. I. DEFINITIONS As a preface to the detailed description, it should be noted that, as used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents, unless the context clearly dictates otherwise. Thus, for example, the term "a semiconductor" includes a variety of different materials which are known to have the behavioral characteristics of a semiconductor, reference to a "plasma" includes a gas or gas reactants activated by an RF glow discharge, reference to "the contact material" or "interconnect material" includes copper and copper alloys, and other conductive materials which have a melting point enabling them to be sputtered over the temperature range described herein. Specific terminology of particular importance to the description of the present invention is defined below. The term "aspect ratio" refers to the ratio of the height dimension to the width dimension of particular openings into which an electrical contact is to be placed. For example, a via opening which typically extends in a tubular form through multiple layers has a height and a diameter, and the aspect ratio would be the height of the tubular divided by the diameter. The aspect ratio of a trench would be the height of the trench divided by the minimal travel width of the trench at its base. The term "contact via" or "via" refers to an electrical contact having an aspect ratio which is typically greater than 1:1. A contact via most frequently extends through multiple layers of material to connect one electrically conductive element with another. The term "copper" includes alloys of copper of the kind typically used in the semiconductor industry. The preferred embodiments described herein were for a copper alloy comprising about 98% by weight copper. The term "feature" refers to contacts, vias, trenches, and other structures which make up the topography of the substrate surface. The term "interconnect" generally refers to conductive structures within a semiconductive device. For purposes of this patent application, electrical contacts in the form of a "contact via" or "via" (which has a higher aspect ratio than conductive lines in trenches, for example) is distinguished from other conductive structures which form interconnects. The term "ion-deposition sputtered" and the term "reactive ion metal plasma (IMP)" refer to sputter deposition using a particular technique, wherein a high density, inductively coupled RF plasma is positioned between the sputtering cathode and the substrate support electrode, whereby at least a portion of the sputtered emission is in the form of ions at the time it reaches the substrate surface. Typically, 10% or more of the sputtered emission is in the form of ions at the time it reaches the substrate surface. The term "traditional sputtering" refers to a method of forming a film layer on a substrate wherein a target is sputtered and the material sputtered from the target passes between the target and the substrate to form a film layer on the substrate, and no means is provided to ionize a substantial portion of the target material sputtered from the target before it reaches the substrate. One apparatus configured to provide traditional sputtering is disclosed in U.S. Patent No. 5,320,728, the disclosure of which is incorporated herein by reference. In such a traditional sputtering configuration, the percentage of target material which is ionized is less than 10%, more typically less than 1%, of that sputtered from the target. The term "XRD" (X-ray Diffraction) refers to a technique commonly used to measure crystalline orientation, wherein radiation over particular wavelengths is passed through the material to be characterized, and the diffraction of the radiation, caused by the material through which it passes, is measured. A map is created which shows the diffraction pattern, and the crystal orientation is calculated based on this map. A "traditionally sputtered" tantalum nitride-comprising film or layer is deposited on a substrate by contacting a tantalum target with a plasma created from an inert gas such as argon in combination- with nitrogen gas. A portion of the tantalum sputtered from the target reacts with nitrogen gas which has been activated by the plasma to produce tantalum nitride, and the gas phase mixture contacts the substrate to form a layer on the substrate. II. AN APPARATUS FOR PRACTICING THE INVENTION A process system in which the method of the present invention may be carried out is the Applied Materials, Inc. (Santa Clara, California) Endura® Integrated Processing System. This process system is not specifically shown in the Figures. However, the system is generally known in the semiconductor processing industry and is shown and described in United States Patents Nos. 5,186,718 and 5,236,868, the disclosures of which are incorporated by reference. A schematic of a typical sputtering apparatus useful in forming the smooth-surfaced TaN x /Ta barrier layer of the present invention is shown in Figure 1. Sputtering apparatus 100 includes a sputtering target 110 which has two major surfaces, a back surface 112 from which heat is removed, and a front surface 114 which is the sputtering surface. The sputtered material is deposited on the surface of semiconductor workpiece 116 which is supported on platen 118. The spacing between the workpiece 116 and the target 110 may be adjusted by moving the platen 1 18. The sputtering target (cathode) 110 operates at power levels up to about 24 kW. An ionized gas, typically generated from an inert gas such as argon is used to impact sputtering target 110, to produce sputtered metal atoms which are deposited on workpiece 116. The inert gas enters vacuum chamber 117 in the vicinity to target 112 through openings which are not shown on Figure 1. Additional gas may enter vacuum chamber 117 from the surface of workpiece support platen 118, which includes openings (not shown) in its surface to permit the flow of heat transfer gas between workpiece 116 and support platen 118. Such gases are evacuated through an opening (not shown) in vacuum chamber 117, which opening is connected to a conduit (not shown) leading to a vacuum pump (not shown). Vacuum chamber 117 can be operated at pressures ranging from about 0.1 mT to about 60 mT, depending on the particular process involved. III. A METHOD FOR PRACTICING THE INVENTION EXAMPLE ONE: FORMATION OF A TaN x /Ta BARRIER LAYER To form the TaN x /Ta barrier layer structure, a tantalum target cathode 1 10 was used, and a DC power was applied to this cathode over a range from about 0.5 kW to about 8 kW. The spacing between target cathode 110 and workpiece 116 was approximately 200 - 300 mm. During the formation of the TaN x first layer, argon gas feed to vacuum chamber 117 was about 15 seem to the substrate support platen 118 and about 7 seem to the openings in the vicinity of target cathode 110. Nitrogen gas was also fed into vacuum chamber 117 in the vicinity of target cathode 110. The nitrogen gas feed rate ranged from about 2 to about 20 seem, depending on the DC power applied, with the nitrogen feed rate being increased as the DC power was increased. With the DC power set at 4 kW and a nitrogen feed rate of about 14 seem, the TaN x layer produced was TaN 07 , containing about 40 atomic percent nitrogen. The substrate 116 was a 200 mm diameter silicon wafer having a silicon dioxide dielectric layer on its surface. The substrate was placed a distance of about 10 inches (25 cm) from target cathode 110. The operational pressure in vacuum chamber 117 was about 1.7 mT, and the substrate temperature of the silicon wafer was about 25°C. Under these conditions, a 500 A thick layer of TaN was applied in approximately one minute. Subsequent to application of the TaN layer, the nitrogen gas was shut off, the power to tantalum target cathode 110 was reduced from about 4 kW to about 1 kW, and the argon gas feed was maintained. The pressure in the vacuum chamber remained at about 1.7 mT, and the substrate temperature remained at about 25 °C. Under these conditions, a 60 A thick layer of tantalum was formed over the TaN layer in about 10 seconds. The data generated in Figure 2 was for TaN/Ta barrier layers produced in the manner described above, where the length of time for tantalum deposition was increased to produce a thicker tantalum layer, as appropriate. EXAMPLE TWO: FORMATION OF THE COPPER CONDUCTIVE LAYER The copper layer overlying the TaN barrier layer was applied using the same apparatus described with regard to application of the TaN barrier layer. The target cathode 110 was copper. During the formation of the overlying Cu layer, argon gas feed to vacuum chamber 117 was about 15 seem to the substrate support platen 118 and about 90 seem to the openings in the vicinity of target cathode 110. The substrate, having a tantalum layer as its upper surface, was placed a distance of about 10 inches (25 cm) from target cathode 110. The operational pressure in vacuum chamber 117 was about 1.0 mT, and the substrate temperature was about 150°C. Under these conditions, a 1 ,000 A thick layer of copper was applied in about one minute. With reference to the formation of the TaN x /Ta/Cu structure in general, it is advisable to use the minimal thickness possible for the tantalum layer, as a flatter structure is preferred for planarization and imaging purposes, and it is difficult to remove excess tantalum from the surface of the workpiece. When chemical mechanical polishing is used to remove material on the surface of the workpiece between features (known as the "field"), the removal rate for tantalum is much slower than the copper removal rate. As a result, in order to ensure complete removal of copper and Ta TaN x from the field, the copper may be over polished, creating a "dishing effect" in the area of a contact, where the copper is removed from the contact to a level below the surface of the substrate/workpiece. In addition, there is a cost in substrate processing time. The minimal thickness for the tantalum layer is determined by the desired performance features for the layer. The layer must be sufficiently thick to provide a tantalum {002} crystalline orientation which enables easy wetting of the tantalum surface by the copper and depositing of a copper layer having a high {111} crystal orientation. Although a higher temperature is required to dewet/delaminate a depositing copper layer from a Ta surface than from a TaN x surface, copper delamination is a problem in some instances. Typically, the copper layer is deposited at temperatures in the range of about 300°C to about 500°C (or a copper seed layer is deposited at lower temperatures, but additional copper is deposited and the combination is annealed at temperatures in this range), where delamination of the copper layer is a real possibility. When the copper is deposited for flat interconnect lines, the wetting criteria is not as important as it is when the copper is deposited to fill a contact via having a high aspect ratio (i.e., depth greater than width). As the thickness of the tantalum layer increases, the wetting of the tantalum by a layer of copper applied thereover generally improves. As the thickness of the tantalum layer increases, the copper {111 } crystallographic content generally increases as well. The limitation on tantalum layer thickness is defined by the device feature size, in particular. If the TaN x or the Ta layer is too thick, the overall resistance of the conductive feature increases. If these layers are too thin, the barrier may not be adequate to prevent diffusion; further, if the Ta layer is too thin, the copper {111 } crystallographic content may be inadequate to provide the desired electromigration resistance. In general, the copper {111 } crystallographic content is poorer when copper is applied directly over a TaN x layer due to the amorphous structural content of the TaN x layer. Further, copper applied by means other than sputtering, where the copper layer itself has a higher impurity level (such as copper applied by CVD), may result in an unacceptably low copper {111 } crystallographic content. The use of a Ta layer over the TaN x layer can produce an acceptable surface for growth of a high copper {111 } crystallographic content. Deposition of a seed layer of copper over the Ta surface prior to application of the entire copper contact by other means, such as CVD, provides a starting matrix for copper growth, since some CVD precursors and electroplating require a conductive substrate for the copper deposition process to take place. Further, the copper seed layer promotes an increase in the copper {111} crystallographic content. IV. THE STRUCTURE OF THE TaN π a BARRIER LAYER AND ITS EFFECT ON THE COPPER {1 11 } CRYSTALLOGRAPHIC CONTENT Figure 2 shows a graph 200 of the {111 } crystallographic content (measured by XRD) of a copper layer as a function of the thickness of the Ta layer of a TaN x /Ta barrier layer. In particular, the various specimens examined (prepared using the method described above) are represented on the scale labeled 207. The layers of material were deposited using standard, traditional sputtering techniques. In all instances, the copper layer was 1,000 A thick. In all instances, except the data point labeled 206, the underlying layer of TaN x was 500 A thick. The data point labeled 206 represents a 500 A thick Ta (only) barrier layer. The data point labeled 208 represents a 500 A thick TaN x (only) barrier layer. The data point labeled 210 represents the TaN x /TaN structure where the overlying Ta layer was 57 A thick. The data point labeled 212 represents the TaN x /Ta structure where the overlying Ta layer was 114 A thick. The data point labeled 214 represents the TaN x /Ta structure where the overlying Ta layer was 170 A thick. The data point labeled 216 represents the TaN x /Ta structure where the overlying Ta layer was 227 A thick. And, the data point labeled 218 represents the TaN x /Ta structure where the overlying Ta layer was 456 A thick. The XRD scanning of these specimens was done using the standard θ - 2Θ technique, with the relative normalized area under the Cu {111 } intensity peak shown on the scale labeled 203. Curve 202 illustrates the normalized area under the Cu {111 } CPS (counts per second) intensity peak for the specimens previously described, with the Ta layer thickness increasing from left to right on the curve beginning with data point 210. A second measurement indicating the amount of the Cu {111} orientation present is provided in the rocking curve data shown on the scale labeled 205. The data represents the Cu { 111 } F WHM measured in degrees θ . In the rocking curve measurement technique, the sample is rotating and the detector is rotating. The CPS measurement is made at a set angle and then the detector is slightly rotated and a new CPS is measured. A plot of the CPS at increasing angle of measurement is made, generating a distribution curve of the quantity of the specific crystal orientation measured at increasing angles. FWHM = full width half max. FWHM is calculated by measuring the width of the curve at a position on the curve which represents one half of the maximum height of the curve. The FWHM is expressed in degrees and represents the number of degrees spanned by the width of the curve at half of its maximum height. A wider curve (a higher number on the scale), spanning a larger number of degrees, indicates that the signal for the crystallographic orientation of interest is not a strong signal and less copper {111 } crystallographic orientation is present. A narrow curve (a lower number on the scale), spanning a limited number of degrees, is a strong signal, indicating a larger quantity of the crystallographic orientation is present. Curve 204 illustrates the FWHM for the specimens previously described, with the Ta layer thickness increasing from left to right on the curve beginning with data point 210. Data point 206 on curve 202 shows the normalized area under the Cu {1 11 } intensity peak for the specimen having a 500 A thick Ta layer underlying the 1 ,000 A thick sputtered copper layer. As is evident from the curve 202, the quantity of Cu { 1 11 } crystal orientation is relatively high. However, as previously mentioned, a layer of pure Ta does not provide a diffusion barrier which performs as well as the TaN x /Ta barrier layer structure in preventing copper diffusion into the underlying silicon dioxide dielectric layer. Data point 208 on curve 202 shows the normalized area under the Cu { 111 } intensity peak for the specimen having a 500 A thick TaN layer underlying the 1 ,000 A thick sputtered copper layer. Although the TaN layer provides a good diffusion barrier, the quantity of Cu {111} is minimal. Data points 210 through 216 on curve 202 show the normalized area under the Cu { 111 } intensity peak for specimens having a 500 A thick TaN layer, with increasing thicknesses of an overlying Ta layer (as the data point 1 number increases), all with a 1,000 A layer of copper applied over the TaN/Ta barrier 2 layer. The 500 A TaN/57 A Ta barrier layer of data point 210 provides about 10% less 3 area under the Cu { 111 } peak than the 500 A layer of Ta provided. The exact 4 significance of this decrease in electromigration performance has not yet been 5 determined; however, the difference is not expected to have a significant influence on 6 device performance. 7 At data point 214 on curve 202, which represents the 500 A TaN/ 170 A Ta barrier 8 layer, the area under the Cu {111 } peak is equivalent to the pure layer of Ta. 9 Surprisingly, at some point between the 500 A TaN/227 A Ta barrier layer represented 10 by data point 216 and the 500 A TaN/456 A Ta barrier layer represented by data point 1 1 218, the Cu { 1 11 } crystal content increases drastically, rising to a value about 20% 12 greater than that for the pure layer of Ta. The FWHM data shown on curve 204 for the 13 same specimens described above confirms the same trends illustrated by the normalized 14 area under the Cu {111 } intensity peak. See, for example, a lower FWHM after data 15 point 216 on curve 204, indicating an increased amount of the copper {111} 16 crystallographic orientation. 17 Based on this disclosure, one skilled in the art can provide a barrier layer which 18 prevents the diffusion of a copper layer deposited thereover, and enable the formation of 19 a copper layer having a high { 1 11 } crystallographic content. 20 The above described preferred embodiments are not intended to limit the scope 21 of the present invention, as one skilled in the art can, in view of the present disclosure 22 expand such embodiments to correspond with the subject matter of the invention claimed 23 below.

Claims: CLAIMS We claim: 1. A barrier layer for use in combination with a conductive layer, said barrier layer having a particular structure comprising: a) a first layer of TaN x having a thickness ranging from greater than about 10 A to about 1,000 A; and b) a second layer of Ta overlying said first layer and having a thickness ranging from about 5 A to about 500 A. 2. The barrier layer of Claim 1, wherein the conductive layer is copper. 3. The barrier layer of Claim 1, wherein said barrier layer is used in an interconnect structure, and wherein the thickness of said TaN x layer ranges from about 50 A to about 1 ,000 A and the thickness of said Ta layer ranges from about 20 A to about 500 A. 4. The barrier layer of Claim 1 , wherein said barrier layer is used in a contact via structure, and wherein the thickness of said TaN x layer ranges from about 10 A to about 300 A and the thickness of said Ta layer ranges from about 5 A to about 300 A. 5. The barrier layer of Claim 2, or Claim 3, or Claim 4, wherein x ranges from about 0.1 to about 1.5. 6. A copper interconnect structure comprising the barrier layer of Claim 2 and an overlying copper layer, wherein the Cu {1 1 1 } crystallographic content of said overlying copper layer is at least 70% of the Cu { 1 1 1 } crystallographic content which can be obtained using a pure Ta barrier layer which is about 500 A thick. 7. A copper contact via-comprising structure including the barrier layer of Claim 2 and a copper fill, wherein the copper fill layer Cu { 111 } crystallographic content is at least 70% of the Cu {111 } crystallographic content which can be obtained using a pure Ta barrier layer which is about 250 A thick. 8. A method of producing a barrier layer useful in combination with a conductive layer, said method comprising the steps of: a) depositing a first layer of TaN x having a thickness ranging from greater than about 10 A to about 1,000 A; and b) depositing a second layer of Ta having a thickness ranging from about 5 A to about 500 A. 9. The method of Claim 8, wherein the conductive layer is copper. 10. The method of Claim 8, wherein said first layer of TaN x is deposited upon a substrate having a substrate temperature ranging from about 25 °C to about 500°C. 11. The method of Claim 8, wherein said second layer of Ta is deposited upon a substrate having a substrate temperature ranging from about 25 °C to about 500°C. 12. The method of Claim 8, wherein said barrier layer is used in an interconnect structure, and wherein the thickness of said TaN x layer ranges from about 50 A to about 1,000 A and the thickness of said Ta layer ranges from about 20 A to about 500 A. 13. The method of Claim 8, wherein said barrier layer is used in a contact via structure, and wherein the thickness of said TaN x layer ranges from about 10 A to about 300 A and the thickness of said Ta layer ranges from about 5 A to about 300 A. 14. The method of Claim 8, or Claim 12, or Claim 13, where x ranges from about 0.1 to about 1.5. 15. The method of Claim 8, wherein at least a portion of said Ta layer is deposited using a traditional, standard sputtering technique. 16. The method of Claim 12, wherein at least a portion of said Ta layer is deposited using a traditional, standard sputtering technique. 17. The method of Claim 8, wherein at least a portion of the TaN x layer is deposited using a traditional, standard sputtering technique. 18. The method of Claim 8, wherein at least a portion of said Ta layer is deposited using ion-deposition sputtering. 19. The method of Claim 13, wherein at least a portion of said Ta layer is deposited using ion-deposition sputtering. 20. The method of Claim 8, wherein at least a portion of the TaN x layer is deposited using ion-deposition sputteirng. 21. A method of producing a copper interconnect structure comprising the barrier layer of Claim 1 and an overlying copper layer, wherein the Cu {111 } crystallographic content of said overlying copper layer is at least 70 % of the Cu {111 } crystallographic content which can be obtained by depositing said copper layer using a pure Ta barrier layer which is about 500 A thick, said method comprising the steps of: a) depositing a first layer of TaN x having a thickness ranging from greater than about 50 A to about 1 ,000 A; b) depositing a second layer of Ta having a thickness ranging from about 5 A to about 500 A over the surface of said first layer of TaN x ; and c) depositing a third layer of copper over the surface of said second layer of Ta, wherein at least a portion of said third layer of copper is deposited using a physical vapor deposition technique, and wherein the substrate temperature at which said third layer of copper is deposited is less than about 500°C. 22. The method of Claim 21 , wherein said copper interconnect structure is annealed at a temperature of less than about 500°C. 23. A method of producing a copper-comprising contact via structure comprising the barrier layer of Claim 1 and an overlying copper layer, wherein the Cu { 111 } crystallographic content of said overlying copper layer is at least 70% of the Cu {111} crystallographic content which can be obtained by depositing said copper layer using a pure Ta barrier layer which is about 300 A thick, said method comprising the steps of: a) depositing a first layer of TaN x having a thickness ranging from greater than about 10 A to about 300 A; b) depositing a second layer of Ta having a thickness ranging from about 5 A to about 300 A over the surface of said first layer of TaN x ; and c) depositing a third layer of copper over the surface of said second layer of Ta, wherein at least a portion of said third layer of copper is deposited using a physical vapor deposition technique, and wherein the substrate temperature at which said third layer of copper is deposited is less than about 500°C. 24. The method of Claim 23, wherein said contact-comprising structure is annealed at a temperature of less than about 500°C. 25. The method of Claim 23, wherein said copper layer is deposited at a temperature of less than about 300°C. 26. The method of Claim 25, wherein said structure is annealed at a temperature of less than about 500°C. 27. A method of producing a copper-comprising contact structure including the barrier layer of Claim 1 and an overlying copper layer, wherein the Cu {111} crystallographic content of said overlying copper layer is at least 70% of the Cu {111 } crystallographic content which can be obtained by depositing said copper layer using a pure Ta barrier layer which is about 300 A thick, said method comprising the steps of: a) depositing a first layer of TaN x having a thickness ranging from greater than about 10 A to about 300 A; b) depositing a second layer of Ta having a thickness ranging from about 5 A to about 300 A over the surface of said first layer of TaN x ; and c) depositing a third layer of copper over the surface of said second layer of Ta, wherein at least a portion of said third layer of copper is deposited using a physical vapor deposition technique, and wherein the substrate temperature at which said third layer of copper is deposited is less than about 500 °C, wherein at least a portion of said first layer, or said second layer, or said third layer, or a combination thereof, is deposited using ion-deposition sputtering.

Inventors: CHIANG TONY, CHIN BARRY, DING PEIJUN, CHIANG, TONY, CHIN, BARRY, DING, PEIJUN
Applicants: APPLIED MATERIALS INC, APPLIED MATERIALS, INC.
Application year: 1998
Main classification: H01L23
IPC codes: H01L21, H01L23