Method for storing data structures in a memory

Abstract: A compiler system (190) stores a data structure (101, e.g., a program) to a memory (110) of an execution system (100). The data structure (101) comprises, for example, processor instructions coded by compressed portions of variable lengths. The compiler system (190) partitions some or all memory lines (115) of the memory (110) into P≥ 2 partitions, e.g., α and β, and writes code portions A to a first partition (e.g., α) and second code portions B to a second partition (e.g., β) of an adjacent memory line (115).

Description: Field of the Invention The present invention generally relates to computer systems and, more particularly, to methods and to systems for storing and retrieving data structures in and from memory. Background of the Invention Embedded systems technology has become an important aspect of our daily life, starting with remote control devices for TV sets up to automotive engine control and navigation systems. Embedded systems development must take into account design constraints on size, weight, power consumption and other cost related parameters. The performance benefits of adopting Reduced Instruction Set Computer (RISC) architectures in embedded systems are well recognized in the art. RISC offer efficient and small cores. In comparison to Complete Instruction Set Computers (CISC), the RISCs suffers from relatively large instruction sizes and need therefore more memory space for the software program. The program, and generally any data structure, should be stored with a high code density. This can be achieved, for example, by off-line compressing and decompressing before execution. However, such an approach requires additional memory space for permanently or temporarily storing expanded instructions (e.g., a cache). Despite falling prices for some kind of memory (e.g., disks), memory space is still precious in embedded or similar systems. There is a technical task to develop storing and retrieving methods which substantially do not require additional space. The present invention seeks to provide methods and computer systems which mitigate or avoid these and other disadvantages and limitations of the prior art. Brief Description of the Drawings FIG. 1 illustrates a simplified block diagram of an execution system and a compiler system in which methods of the present invention are applied; FIG. 2 illustrates a simplified block diagram of an instruction word with instruction portions and a code word with code portions; FIG. 3 illustrates a simplified block diagram of a memory of the execution system of FIG. 1 which is virtually partitioned according to a storage method of the present invention; FIG. 4 illustrates a simplified flow chart diagram of the storage method; FIG. 5 illustrates a simplified block diagram of an address used in a preferred embodiment of the storage method; FIGS. 6-1 to 6-3 illustrate memory lines of the memory of FIG. 3 as they are used in the first embodiment; and FIG. 7 illustrates a simplified flow chart diagram of a retrieval method according to the present invention. Detailed Description of a Preferred Embodiment The present invention can be used, for example, in an embedded system which combines the advantages of RISC performance and compressed instruction storage. Decompressing can take place during program execution, and not substantially before execution. Intermediate memories (e.g., caches) are substantially not required. The present invention can save memory of external memories (e.g., disks) and internal memories (e.g., RAM, ROM). Also, existing development tools for prior art systems can be used with only minor modifications. These and other advantages of the present invention are explained in the following description. For convenience, a glossary of terms is provided prior to the claims. As used herein, the symbol @ is optionally used to combine reference numbers and indices when needed for explanation. FIG. 1 illustrates a simplified block diagram of execution system 100 (dashed frame) and compiler system 190 in which methods of the present invention are applied. Preferably, execution system 100 comprises memory 110, data bus 120, converter 130, instruction bus 135, processor 140, and address bus 150. Preferably, converter 130 comprises P ≥ 2 decoders (e.g., decoders 131 and 132). Memory 110 comprises a plurality of memory lines 115. Some or all of memory lines 115 are virtually divided into P ≥ 2 partitions (e.g., partitions α and β, details later). The partitions have varying lengths to accommodate different data length stored therein. In other words, partitions are defined by dynamic boundaries. Memory 110 is coupled to data bus 120 which forwards compressed code words 220 (details in FIG. 2) to converter 130. Converter 130 expands code words 220 and sends instruction words 210 (cf. decoding 242 in FIG. 2) to processor 140 via bus 135. Optionally, converter 130 can bypass some code words 220 and send them as instruction words 210 without expanding. The bypass option can be supported, for example, by an indication within code words 220 or by additional control signals from processor 140. Optionally, processor 140 sends addresses 250 (details in FIG. 5) to memory 110 via address bus 150. Code words 220 in memory 110 can also have the function of addresses 250 so that address information can also go from memory 110 to processor 150. Optionally, busses 120, 135 and 150 are bi-directional busses which can also carry instruction words 210 from processor 140 to converter 130, code words 220 from converter 130 to memory 110, or addresses 250 from processor 140 to memory 110. For the purpose of explanation, it is assumed that addresses 250 and data words 220 can all be stored in memory lines 115 of memory 110. Optionally, memory 110 can be divided into areas for code words 220 and for addresses 250. But this is not essential for the present invention. Compiler system 190 is illustrated as being temporarily coupled to memory 110 of execution system 100 via bus 195 (dashed) and, optionally via master memory 196 (dashed). According to a storage method (e.g., method 300) of the present invention, compiler system 190 stores data structure 101 (e.g., pluralities of code portions A and B) with compressed instructions, data and addresses in memory 110 of execution system 100. For example, portion A goes into partition α and portion B goes into partition β of an adjacent memory line 115@i'. Using partitions in adjacent lines is an important aspect of the present invention. Details for data structure 101 in memory 110 are explained later. Preferably, compiler system 190 is coupled to execution system 100 once before operation of execution system 100. It is also possible, that compiler system 190 writes data structure 101 first to master memory 196. Then, second data structure 101 is exported to many execution systems 100. For simplicity of further explanations, master memory 196 and memory 110 should be assumed to be similar so that the term "memory 110" includes also memory 196. According to a retrieval method of the invention (e.g., method 400), memory 110 retrieves data structure 101 and sends data words 220 to converter 130. Preferably, the retrieval method is applied at run time of execution system 100. Retrieving takes advantage from storing data structure 101 according to the present invention. The retrieval method can be considered as an inverse method in respect to the storage method. Details for the operation of data bus 120, converter 130, address bus 150, and processor 140 are not subject of the present invention and are therefore not explained further. It is known in the art, how to provide, for example, busses, decoders and central processing units (CPUs) so that those of skill in the art are able to implement these system elements without the need for further explanation. It is an important advantage of the present invention, that the software program stored in compressed form in memory 110 need less space than a similar program stored uncompressed. Also, buses 120 and 150, convener 130 and processor 140 of execution processor 100 can conveniently be embedded into a single semiconductor substrate. The present invention is especially suitable when processor 140 is a RISC machine. FIG. 2 illustrates a simplified block diagram of instruction word 210 (dashed frame) with instruction portions 212@$A and 212@$B and code word 220 (dashed frame) with code portions 222@A and 222@B. Instruction word 210 can be transformed to code word 220 and vice versa. In the following, code portions 222@A and 222@B are conveniently referred to as portions A and B, respectively. The division of words 210 and 220 into P = 2 portions each (A and B) is intended to be a non-limiting example. Those of skill in the art, are able, based on the description herein, to apply the present invention also for P ≥ 2. Pluralities of code portions A and B stored in memory 110 form data structure 101 (cf. FIG. 1). Splitting the words into portions is an advantage of the present invention and saves operation time. Parallel operating devices, such as, for example decoders 131 and 132, need less time to transform separate portions than a single device would need to transform a complete word. In FIG. 2 and in other figures, data units 230, which are not further divided, have symbols , , 1 ○, 2 ○ or simply ○. Preferably, data units 230, for convenience hereinafter "bits", represent binary quantities with logical "0" and "1" values, as the case may be. But this is only a convention used for the simplicity of explanation. Those of skill in the art are able, based on the description herein, to use other values. The actual value (e.g., "0" or "1") of bits 230 is not important for the present invention. Conveniently, instruction portions 212@$A and 212@$B each have U instruction bits 231 (e.g., U = 8 bits and U = 8 bits , respectively). The lengths V A and V B (collectively V) of code portions A and B, respectively, can vary. Portion A has V A code bits 232 (e.g., V A = 10 bits 1 ○ ) and portion B has V B code bits 232 (e.g., V B = 7 bits 2 ○ ). The numbers V of code bits 232 are limited by a minimum number V MIN ("bounded code") and a maximum number V MAX , that is: V MIN ≤ V ≤ V MAX with the ≤ symbol for smaller than or equal to. In the example used for explanation herein, V can assume the following values: 3 ≤ V ≤ 12. Having equal MIN-MAX numbers for portions A and B is convenient for explanation, but not necessary for the invention. Optionally, the numbers can also be different, that is: V A MIN ≠ V B MIN V A MAX ≠ V B MAX As shown by unidirectional arrows, coding 241 transforms instruction portion 212@$A to code portion A and instruction portion 212@$B to code portion B. Preferably, coding is performed with compression so that V ≤ U. This is convenient, but not essential for the present invention. Preferably, decoding 242, is performed by expanding in, for example, decoders 131 and 132. Code portion A and B are re-transformed to instruction portions 212@$A and 212@$B, respectively. Methods and devices for coding and decoding are well known in the art. The following reference [1] ] gives an introduction to coding and decoding: Bernard Sklar: "DIGITAL COMMUNICATIONS Fundamentals and Applications", published by Prentice Hall, Englewood Cliffs 1998, ISBN 0-13-211939-0, especially chapter 11.6 "Source Coding" on pages 595-667. Therefore, persons of skill in the art are able, based on the description herein, to practice the present invention using known coders and decoders (e.g., in compiler system 190 and decoders 131/132 of converter 130) without the need for further explanation. Conveniently, code words 220 used in the present invention are Huffman coded (see sub-chapter 11.6.2 of [1] with a coding tree). The Huffman code is a prefix-free code (e.g., no additional bits between 1 ○ and 2 ○ required) and a variable length code (e.g., lengths V are different). Huffman coding (e.g., coding 241) is assumed here only for the purpose of explaining the present invention and not intended to be limiting. The present invention can also be applied for encrypting or decrypting data. Preferably, the number of possible variations (e.g., 2 (U*P) ) of instruction bits 231 is adapted for RISC processors (e.g., processor 140). As explained later, compiler system 190 receives instruction words 210, performs coding 241, and writes portions A and B to adjacent memory locations in memory 100. When execution system 100 operates, converter 130 receives portions A and B substantially simultaneously or with a time delay which can be neglected. In converter 130, decoder 131 of converter 130 decodes (cf. step 242) portion A to instruction portions 212@A; and decoder 132 decodes portion B to instruction portion 212@B. Decoders 131 and 132 operate substantially in parallel and provide instruction word 210 substantially to processor 140 in a just-in-time schedule at processor run time. Extra memory (e.g., cache) to store instruction words is not required. This is an important advantage of the present invention. FIG. 3 illustrates a simplified block diagram of memory 110 of execution system 100 of FIG. 1 which is virtually partitioned according to a storage method of the present invention. Memory 110 has memory lines 115@i with line index i = 0 to I-1, wherein e.g., I = 14 is not important for the invention. For simplicity, FIG. 3 illustrates only memory lines 115@0, 115@5, 115@6, 115@10, 115@11, 115@13 and 115@14. Line number I is usually much higher, e.g., I = 2 22 ≈ 4.000.000. Preferably, each memory line 115@i has J memory fields 118@i@j identified by line index i and position index j = 0 to J-1 (e.g., J = 32). A number of J BIT (e.g., J BIT = 27) fields are "bit fields" and store code bits 232 (cf. FIG. 2, O symbols). A number of J TAG (e.g., J TAG = 5) fields are "tag fields" and store a line tag T(i). The numbers are related as: J BIT + J TAG = J For convenience, FIG. 3 has double-arrowed measuring lines for bit numbers. Preferably, the positions of the bit fields and tag fields within the range between j = 0 and j = J-1 are constant. In the example, of FIG. 3, bit fields have position indices between j = 0 and (J BIT - 1) (e.g., 0 and 26). Tag fields have position indices between j = (J - J TAG ) and (J-1) (e.g., 27 and 31) shown on the right side. In each memory line 115@i, line tag T(i) is a partition indicator and classifies the plurality of bit fields into P ≥ 2 partitions. For convenience of explanation, assume, that P has the value P = 2 (as in FIG. 2). Hereinafter, partitions are referred to as "partition α" and "partition β". T(i) conveniently comprises a representation for partition index j X (i). In the example of FIG. 3, the 5 bits of T(i) can identify any number j X (i) between 0 and J BIT -1 ≤ 2 5 . For example, T(0) of memory line 115@0 points to j X (0) = 11 and partition α comprises the 11 bit fields 118 from j = 0 to j = 10 and partition β comprises the 16 bit fields 118 from j = j X (0) = 11 to j = J BIT -1 = 26. Using J BIT and position index j X (i), partition lengths L α (i) and L β (i) can be defined as follows: L α (i) + L β (i) = J BIT L α (i) = j X (i) L β (i) = J BIT -L α (i) In other words, L α is a complement to L β . Primed index i' which identifies memory line 115@i' is used accordingly. For convenience of explanation, boundary 119 is illustrated in each memory line 115@i between memory field 118@i@(j X (i)-1) and field 118@i@j X (i). Boundary 119 is virtual and used only for convenience of explanation. In a real hardware implementation of memory 110 there is no need for a boundary. According to the invention, compiler system 190 writes portions A into partition α of memory line 115@i and portion B into partition β of memory line 115@i' (primed), wherein memory lines 115@i and 115@i' are adjacent lines. Portions are illustrated by partly hatched boxes (reference 222) surrounding the V A and V B code bits ○. The term "adjacent" used herein is intended to include that memory lines 115@i and 115@i' can be single memory line 115@i = 115@i' or two lines which are located at a predetermined line distance d between i' and i: d = | i' - i | Symbols | | stand for absolute values. "Adjacent" should also include, that portion A can have code bits 232 stored in memory line 115@i and further code bits 232 stored in memory line 115@(i+1). FIG. 3 gives an example by portion A' (reference 222') having first code bits 232' in partition α of line memory 115@13 and further code bits 232" in partition α of memory line 115@14. Similarly, portion B can have code bits 232 stored in memory lines 115@i' and memory lines 115@(i'+1). Preferably, line distance d is one: d = 1. This is convenient, but other values for d can also be used. For d = 1, three cases ("instruction placements") can be distinguished: In case (1), both portions A and B are stored in single memory line 115@i (e.g., portions A (1) and B (1) in memory line 115@0); in case (2), portion A is stored in memory line 115@i and portion B is stored in next memory line 115@(i+1) (e.g., A (2) in memory line 115@5 and B (2) in memory line 115@6): and in case (3), portion A is stored in line i and portion B is stored in line i-1 (e.g., B (3) in memory line 115@10 and A (3) in memory line 115@11). Superscripts (1), (2) and (3) are used here to distinguish portions in different lines. In other words, portion A is stored in line i and portion B is stored in primed line i', wherein i' = i for case (1) common line for A and B i' = i+1 for case (2) consecutive lines for A and B i' = i-1 for case (3) consecutive lines for B and A | i - i' | ≤ 1. According to the storage method (e.g., method 300), compiler system 190 partitions consecutive memory lines 115@i such that i and i' are within the line distance d. Using adjacent memory lines 115@i and 115@i' for storing portions A and B is convenient for retrieving and is therefore an important advantage of the present invention. According to the retrieving method (e.g., method 400, details later), converter 130 can read portions A and B substantially simultaneously so that decoders 131 and 132 can receive portions A and B, respectively, substantially simultaneously. For further explanation, it is convenient to define start position j A (i) and j B (i') for portions A and B, respectively. A start position j A (i) within memory line 115@i indicates memory field 118@i@j (j = j A ) which stores the first code bit 232 of portion A. The V A code bits of portion A are counted in a first direction, that is: from j A (i) to (j A (i) +V A -1) with 0 ≤ j A (i) and (j A (i) +V A -1) < (j X (i)-1) such as, for example, from the left to the right. In the example of FIG. 3, portion A (1) with V A (1) = 4 code bits 232 start at j A = 4 and ends at j = 7. Similarly, start position j B (i') indicates memory field 118@i'@j (j = j B ) in memory line 115@i' which stores the first code bit 232 of portion B. The V B code bits are counted in a second, opposite direction, that is: from j B (i') to (j B (i) - V B ) with J BIT -1 ≥ j B (i') and (j B (i') - V B ) ≥ j X (i') In case of portions going over 2 memory lines, V A and V B can be replaced by V' A ≤ V A and V' B ≤ V B which indicate the numbers of code bits in memory lines 115@i and 115@i', respectively. In this case, the remaining V A - V' A code bits of portion A are stored in memory line 115@(i+1); and the remaining V B - V' B code bits of portion B are stored in memory line 115@(i'+1). The end positions of portions A and B are conveniently not identified. It is possible to send also the remaining code bits (e.g., from j A +V A -1) to (j X -1)) stored in partitions α and β to converter 130. If Huffman coding is used, then decoders 131 and 132 can detect portion lengths V A and V B automatically. In order to reduce J TAG , allowable values for position index j X (i) can be limited. For example, j X (i) could be within a minimum/maximum range, that is: j X MIN ≤j X (i) ≤j X MAX Or, j X (i) should be an even number j X MIN = 0, 2, 4, .. For convenience of explanation, and intended to give a nonlimiting example, the embodiments of the present invention are explained with J BIT = 31 bits, j X (i) with an allowable range of only two numbers and T(i) being a single bit. According to T(i), partition length L α (i) and L β (i) (collectively L) can assume values between a minimum value L MIN and a maximum value L MAX , that is L MIN ≤ L ≤ L MAX e.g., L MAX = L α MAX = L β MAX = 19 bits "long" e.g., L MIN = L α MIN = L β MIN = 12 bits "short" The partition lengths can be coded, for example, as follows: L α (i) = L MAX and L β (i) = L MIN for T(i) = 0 L α (i) = L MAX and L β (i) = L MIN for T(i) = 1 For further explanation it is convenient to introduce field distances X A (i) and X B (i) in memory line 115@i. In the following, index i is not written for simplicity. Field distance X A is defined as the number of bit fields 118 between portion A and identifier j X (at boundary 119). The X A bit fields 118 belong to partition α and do not store code bits 232 of portion A (e.g., fields 115@i@(j A +V A -1) to @(j X -1)). The fields are illustrated to the right of portion A. Field distance X A is conveniently calculated as: X A = j X - j A - V A In the example of memory line 115@1 of FIG. 3, this means: 3 = 11 - 4 - 4 Accordingly, field distance X B is defined as the number of bit fields 118 between portion B and identifier j X (left of portion B). The X B fields 118 belong to partition β and do not store code bits 232 of portion B. Field distance X B can be calculated as: X B = j B - j X + 1 - V B 3 = 17 - 11 + 1 - 4 (example in line 115@1 Those of skill in the art are able, based on the description herein, to calculate X A and X B in a different way, but without departing from the scope of the present invention. Conveniently, the X A and X B bit fields 118 of partitions α and β, respectively, are referred to as "partition tails". Memory 110 can also be described as a memory having address lines (such e.g., lines 115) for storing addresses (250 explained later) and data lines (e.g., lines 115) for storing pluralities of paired data portions (portions A and B), characterized in that (i) the data lines are virtually partitioned (cf. boundary 119) and store first data portions in first partitions (e.g., A in α) with first offsets (e.g., j A ) and store second data portions in second partitions (e.g., B in β) with second offsets (e.g. j B ), wherein the second partition is located in an adjacent data line (see cases (1), (2), (3)); (ii) the address lines comprise addresses each having ( i ) base addresses (e.g., 255 explained later) for identifying the data lines and ( ii ) pointers (e.g., a and b , explained later) which indicate the first and second offsets. FIG. 4 illustrates a simplified flow chart diagram of storage method 300 of the present invention. According to method 300, compiler system 190 distributes portions A and B of variable lengths V A and V B to partitions α and β such that the partitions are located in adjacent memory lines. Preferably, method 300 is used for storing code portions A and B, but can also be applied to store instruction portions $A and $B. The terms "data portion" and "portion" used to describe method 300 are intended to include code and instruction portions or similar bit combinations. For convenience of explanation, assume that compiler system 190 performs method 300. However, this is not important for the invention. Persons of skill in the art, are able based on the description herein, to use system 100 or other means without the need for further explanation. Method 300 comprises the following steps: receiving step 310, selecting step 320, calculating tails and combination step 330, comparing step 340, moving boundary step 350, storing step 360, and, optionally, providing address step 370. In receiving step 310, compiler system 190 receives code portions A and B and lengths V A and V B , respectively. In selecting boundary step 320, compiler 190 chooses any boundary identifier j X . Identifier j X can be a random number between j = 0 and J BIT-1 . Conveniently, compiler system 190 takes j X from predetermined first, second, or further values. For example in memory lines with J BIT = 31 bit fields 118, j X has either a first value of, e.g., j X = 12 (partition α with 12 fields, partition β with 19 fields) or a second value of, e.g., j X = 19 (α with 19 fields, β with 12 fields). In calculating tails and combination step 330, compiler system 190 obtains X A and X B distances, for example according to above mentioned equations (3.21) to (3.24). With such a calculation, X A and X B are obtained as if portions A and B would have been already written into line 115. Also, compiler calculates a distance combination Y. For example, Y is the absolute value (| | symbols) of the difference between X A and X B , that is: Y = | X A - X B | Combination Y is an indication for the symmetry by which boundary 119 virtually divides the space between memory fields 118 which are designated for portions A and B. In comparing step 340, compiler system 190 compares combination Y to predetermined reference Y MIN , such as, for example: (a) Y > Y MIN (b) Y ≤ Y MIN Preferably, reference Y MIN has a value of Y MIN = 1 but other value can also be used. The next steps depend on alternatives (a) and (b). For alternative (a) on line 341, compiler system 190 stores portion A in partition α and portion B in partition β in storing step 360. Compiler can store portions A and B in adjacent memory lines 115 according to cases (1), (2), and (3) which are, preferably, chosen at random. Also, in storing step 360, compiler system 190 writes tags T(i) and T(i') into memory lines 115. Then, optionally, in providing address step 370, compiler system 190 provides addresses with bases addresses and pointers a and b (see FIG. 5). The address can identify code portions A and B at any memory location (cf. jA(i), j B (i')) within, for example, memory 110. This feature is especially important, when the address is part of a branch instruction and points to an instruction which is located far away from the branch instruction. Details for address definitions are explained later. For alternative (b) on line 341, in moving boundary step 350, compiler system 190 changes identifier j X . Preferably, compiler system 190 changes j X such that Y becomes smaller and repeats (line 351) steps 350, 330 and 340 until case (a). In other words, boundary 119 is shifted until it is virtually located in the center (with e.g., Y MIN = 1 allowable offset) between the portions. Now, compiler system 190 can repeat steps 310, 320, 330, 340, 350, 360 and 370 for further portions A and B for the same memory line 115 or for further memory lines 115. Preferably, in the receptions of method step 360, a number n A of portions A 1 , A 2 , A 3 and so on (each with V... ≤ V A MAX ) goes into a single partition α and a number n B of portions B 1 , B 2 , B 3 and so on (each with V... ≤ V B MAX ) is written into a single partition β of the same memory line 115. The numbers are conveniently related as: n A * V MIN = n B * V MAX In other words, method 300 can also be described as a method for storing a data structure (e.g., structure 101) in a memory (e.g., memory 110) comprising the steps of: (1) receiving a first data portion (e.g., A) having a first length (e.g., V A ) and a second data portion (e.g., B) having a second length (e.g., V A ) (cf. step 310); (2) selecting an identifier (e.g., j X ) (or a "boundary") which virtually partitions a memory line (e.g., line 115) into a first partition and a second partition (e.g., α and β) (cf. step 320); (3) determining a first distance (e.g., X A ) between the boundary and the first portion, a second distance (e.g., X B ) between the boundary and the second portion, and a distance combination (e.g., Y) (cf. step 330); ( 4 ) comparing (cf. step 340) the combination to a predetermined reference (e.g., Y MIN ) and ( a ) changing the boundary (cf. step 350), determining and comparing again or ( b ) storing the first portion in the first partition and the second portion in the second partition (cf. step 360). Optionally, in storing step 360, compiler system 190 can store code portions into memory line 115 which do not convey an instruction. This portions are referred to hereinafter as "void portions". During retrieving (method 400), converter 130 can ignore a void portion and fetch the next portion. Or, converter 130 decodes the void portion to a non-operation instruction for processor 140. Void portions can have variable length. Using void portions is convenient to fill in gaps and to balance boundary 119. In other words, method 400 can be described as a method for storing a data structure (e.g., structure 101) of pluralities of code portions (e.g., A, B) into pluralities of memory lines 115 which comprises the following steps: ( a ) providing a first portion (e.g., portion A) and a second portion (e.g., portion B); (b) assigning a first start position (e.g., j A ) of the first portion within a first line (e.g., line i), and assigning a second start position of the second portion; and ( c ) writing into a first partition (e.g., α) of the first line: code bits of the first portion from the first start position in a first direction (e.g., to the right) and writing into a second partition (e.g., β) of the first line (e.g., as β(1)) or of a second line (e.g., as β(2)): code bits of the second portion from the second start position in a second, opposite direction (e.g., to the left), wherein partitions are chosen such, that first and second portions are stored in adjacent lines. Further, method 400 can be described as a method for storing a data structure in memory with the following steps: ( a ) receiving first and second portions which in combination (e.g., A and B) belong to a single data word (e.g., code word 220), each code portion having a predetermined length (e.g., V); ( b ) virtually partitioning a first memory line and an second adjacent memory line into first and second partitions (e.g., α and β) by first and second partition indicator (e.g., j X (i), j X (i') defining boundaries 119); ( c ) writing the first code portions into the first partition and writing the second code portion into the second partition (e.g., A to α, B to β); (d) writing representations of the first partition indicator (e.g., tag line T(i)) to the first memory line and of the second partition indicator to the second memory line (e.g., tag line T(i')); and ( e ) repeating the receiving, partitioning, and writing steps for further code portions (e.g., stored in next lines 115). In the following, relations between pointers a and b , tags T(i) and T(i'), an optional indicator z, and the start positions j A (i) and j B (i) are explained. FIG. 5 illustrates a simplified block diagram of address 250 used in the preferred embodiment of storage method 300 by way of example. Address 250 comprises K address bits which are distinguished as follows. K q bits form base address 255 which points to memory line 115@i; K z bits represent cases (1), (2) and (3) by location indicator z (256); K a bits represent pointer a (251); and K b bits represent pointer b (252). The bit numbers are related as: K = K q + K z + K a + K b Convenient values are, for example, K = 32, K q = 20 to point to I ≤ 2 20 memory lines 115@i, K z = 2 for the 3 cases, and K a = K b = 5 which identify j X (i) by pointer a and j X (i') by pointer b, respectively. Indicator z can be a pair of two dedicated bits z = (z 1 , z 2 ) which indicate, for example: z 2 = "1" : case (1) z 1 = "1" and z 2 any value: case (2) z 1 = "0" and z 2 any value: case (3) In other words, indicator z in address 250 corresponds to tag T(i) and T(i') stored in memory 110. FIGS. 6-1 to 6-3 illustrate memory lines 115@1 and 115@2 of memory 110 of FIG. 3 as they are used for storing portions A and B in the preferred embodiment of the present invention. FIG. 6-1 to FIG. 6-3 correspond to cases (1), (2) and (3). Lines indices 1 and 2 are used here only for convenience and can stand for any adjacent lines: in FIG. 6-1, i = i' = 1; in FIG. 6-2, i = 1, i' = 2; and in FIG. 6-2 i = 2, i' = 1. For simplicity only, portions A and B are illustrated with equal sizes V A and V B . But this is not important for the present invention. Boundaries 119@1 and 119@2 and tags T(1) and T(2) indicate the virtual partitioning of memory lines 115@1 and 115@2. Partitions α(1) and α(2) are illustrated left of boundaries 119@1 and 119@2, respectively; and partitions β(1) and β(2) are illustrated right of boundaries 119@1 1 and 119@2, respectively. Left edge 113 marks the begin of partitions α(1) and α(2) and right edge 114 marks the begin of partitions β(1) and (2). For convenience, double-arrowed lines indicate e.g., J = 32 bit, J BIT = 31 bit, L MAX = 19 bit, and L MIN = 12 bit. Knowing indicator (z 1 ,z 2 ) (cf. 256 in FIG. 5), pointer a identifies start position j A (i) of portion A to be in partition α(1) or α(2); and pointer b identifies start position j B (i') of portion B to be in partition β(1) or β(2). For convenience, pointer a is illustrated by a dashed arrow; and pointer b is illustrated by a plain arrow. Start positions related to pointers a and b as follows: j A (i) = a j B (i') = J BIT - b In other words, pointer a goes within portion α(i) from position j = 0 (e.g., left edge 113) to the right (first direction) across a number of a code bits which do not belong to portion A; and pointer b goes within portion β(i') from position J BIT - I (right edge 114) to the left (second direction) across a number of b code bits. Pointers a and b are thereby guided by indicator (z 1 ,z 2 ) telling which lines 115@1 1 or 115@2 to use in cases (1), (2) or (3) for i and for i'. For example, possible values for pointer a are 0 ∼ 11 when partition α has 12 memory fields (e.g., α(1) in FIG. 6-1) or 0 ∼ 18 when partition α has 19 memory fields (e.g., α(2) in FIG. 6-2). The representation in the form "min ~ max" stand for numbers between min (including) and max (also including), that is: min ≤ number ≤ max . number ∈ [ min ~ max ] Symbol ∈ stands for "element of set [ ]". Similarly, pointer b can also have values 0 ∼ 12 or 0 ∼ 18. In general, pointer a can assume values 0 ~ L α (i)-1 and pointer b can assume values 0 ~ L β (i)-1, wherein the portion lengths are identified by tags T(1), T(2). For example, portion A could start at left edge 113 of partition α , ( a = 0 (j A = 0)). Or, portions A could have e.g., V' A = I bit stored in portion α(i) of memory line 115@i (e.g., a = L α (i)-1 = 11 ) and the remaining V' A code bits are stored in memory line 115@(i+1). FIG. 6-3 also illustrates an estimation for a possible of number start position combinations. Alternatively, start positions for portions A and B can be defined in reference to two lines. For example, j' A can indicate the distance from left edge 113 to a start position j A (1) in line 115@1 or to j A (2) in line 115@2. Similarly, j' B can indicate the distance from right edge 114 to start position j B (1) in line 115@1 or to j B (2) in line 115@2. Dashed frame 111 indicates 2 * L α MIN = 2* 12 = 24 bit fields 118 in memory lines 115@1 and 115@2 (assuming "short" partitions α(1) and α(2)). Dashed frame 112 indicates also 2 * L β MIN = 2 * 12 = 24 bit fields 118 in memory lines 115@1 and 115@2 (assuming short partitions β(1) and β(2). Dashed frame 116 indicates 2 * (L MAX - L MAX ) = 2* (19 - 12) = 14 bit fields (assuming "long" α, "short" β or vice versa). Identifier j' A can be either j A (1) in line 115@1 or j A (2) in line 115 and point to one of the 24 fields in frame 111. Similarly, identifier j' B can point to one of the 24 fields in frame 112. The number of combinations (j' A ,j' B ) in frames 111 and 112 is 24 * 24 = 576. The number of combinations (j' A ,j' B ) in frame 116 is calculated as 14 * 14 = 196. The total number of combinations (j' A ,j' B ) is obtained as, for example, 576 + 196 = 772. This number includes cases (1), (2), (3) and a further case if portion A and B would both be stored in line 115@2. In this case, the K a = 5 bits and K b = 5 bits of pointers a and b , respectively, alone would be sufficient to indicate any number of combinations (j' A ,j' B ) smaller then 2 to the power of (K a + K b ), for example 772 ≤ 1024. Optionally, pointers a and b can form combination pointer C. Every combination (j' A ,j' B ) can be mapped to a single value of C. For example, pointer a forms the most significant bits (MSB) of C and pointer b forms the least significant bits (LSB) of C. For example, for position j' A = 1 (portions A starting at left edge 113 in α(1) ) and j' B for any number 1 ∼ 24 (any possible starts of portion B in frame 112), C can have values 1 ∼ 24; for j' A = 2 and j' B any 1 ~ 24, C can have values 25 ∼ 48 and so on. Persons of skill in the art are able to implement such or a similar addressing mode (with storing and retrieving) without the need of further explanation. FIG. 7 illustrates a simplified flow chart diagram of retrieval method 400 of the present invention. Retrieval method 400 is, preferably, performed by execution system 100 and, preferably, comprises identifying an address step 410, forwarding code bits step 420, converting step 430, query step 440, jumping step 450, and incrementing base address step 460. In identifying an address step 410, processor 140 checks the currently processed instruction for addresses, for example address 250 (cf. FIG. 5). For example, the instruction (cf. instruction word 210) can be a jump instruction which comprises an address. Optionally, the address itself is coded and is converted by converter 130. This is convenient, but not essential for the invention. In forwarding code bits step 420, memory 110 receives base address 255 of address 250 which identifies memory line 115@i and 115@i'. Then, memory 110 conveniently sends all code bits 232 (cf. FIG. 3) j = 1 to J BIT - 1 from memory lines 115@i and 115@i' to converter 130. The plurality of code bits 232 comprises portions A and B. In converting step 430, decoders 131 and 132 of converter 130 receives pointers a and b from address 250 and selects portions A and B from the plurality of code bits 232. Converter 130 applies case distinction criteria (e.g., cases (1), (2), (3)). For example, converter 130 receives tags T(1) and T(2) from memory lines 115 and indicator z from address 250 (cf. FIG. 5). Decoders 131 and 132 substantially simultaneously converts portions A and B to instruction portions 212$A and 212$B (cf. FIG. 2) of instruction word 210. Start positions j A (i) and j B (i) are used by converters 131 and 132, respectively, for example, as shift pointers, to identify portions A and B from the plurality of code bits 232. As illustrated by query step 440 ("JUMP ?"), the next steps depend on whether instruction word 210 has a jump indication ("yes"-line 441") line or does not have a jump indication ("no"-line 442"). In case of a jump instruction (line 441), memory 110 receives the new address from instruction words 210 ( jumping step 450) and system 100 continues with forwarding step 420. In the other case (line 442), system 100 obtains the new address, preferably, by incrementing the base address (incrementing base address step 460) and also continues with forwarding step 420. Persons of skill in the art are able, based on the description herein, to implement method 400 with hardware elements of execution system 100 without the need for further explanation. Also, persons of skill in the art, based on the description herein, to apply the present invention also to memory line partitioning with P > 2. For such cases, the number of pointers, pointer vectors and tags can be increased. While the invention has been described in terms of particular structures, devices and methods, those of skill in the art will understand based on the description herein that it is not limited merely to such examples and that the full scope of the invention is properly determined by the claims that follow. Glossary of Terms @ combiner for reference numbers and indices A identifies code portion a pointer to code portion A, in the drawings with a dashed line B identifies code portion b pointer to code portion B, in the drawings with a plain line d line distance i, i' indices for memory lines j position index for memory field within a memory line j A (i), j B (i') start positions of portions A and B J number of memory fields in memory line J BIT number of bit fields in memory line J TAG number of tag fields in memory line j X (i) partition index K number of address bits L MAX maximum partition length L MIN minimum partition length L α (i), L β (i), L partition lengths n A , n B number of portions in a single partition T(i) line tag for indicating j X (i) P number of portions U number of bits in instruction portion V A , V B portion lengths V' A , V' B number of bits which go to a single memory line X A , X A field distance Y combination z = (z 1 , z 2 ) indication $A, $B identifies instruction portions α, β partitions (1) (2) (3) as superscript, distinguish cases ∈ element of ∼ from to, including

Claims: A method (300) for providing a data structure (101) into a plurality of memory lines i (115) each having j = 0 to J BIT -1 bit fields i@j, said method characterized by the following steps: receiving (310) code portions A (222@A) with V A ≤ V MAX code bits (232) and code portions B (222@B) with V B ≤ V MAX code bits (232), said portions A and B belonging to single instructions words (210); determining (320,340, 350) partition indices j X (i) and j X (i') of memory lines i and i', respectively, into partitions α(i) in fields i@0 to i@j X (i)-1 and partitions β(i') in fields i'@j X (i') to i'@J BIT -1; and writing (360) portions A into α(i) and portions B into β(i') such that | i - i' ≤ 1. The method of claim 1 wherein L MIN -1 ≤ j X (i) ≤ L MAX with L MIN being the minimum length of said partitions α(i) and β(i') and L MAX being the maximum length of said partitions α(i) and β(i'). The method of claim 1 wherein j X (i) is either j X (i) = L MIN or j X (i) = L MAX and wherein in said writing step, an indication for j X (i) is written to memory line i by a single bit tag. The method of claim 1 wherein in said determining step, a first partition tail of α(i) which does not store portion A and a second partition tail of β(i') which does not store portion B are substantially balanced by changing said partition indices in iterations (340, 350). The method of claim 1 wherein in said writing step, void portions are written into α(i) and β(i'). The method of claim 1 characterized by a step of providing an address (250) for lines i and i', wherein said address has indicator bits (256) which indicate that: (1) α(i) and β(i') are located in a common line i = i', (2) α(i) and β(i') are located in consecutive lines i and i', or (3) β(i') and α(i) are located in consecutive lines i' and i. The method of claim 1 further comprising a step of providing an address (250) for lines i and i' wherein pointers (251, 252) indicate a start position of said portions A and B and indicate that: (1) α(i) and β(i) are located in a common line i = i', (2) α(i) and β(i') are located in consecutive lines i and i', or (3) β(i') and α(i) are located in consecutive lines i' and i. A method for storing pluralities of code portions (222) in pluralities of memory lines (115) with J BIT memory fields 0 ≤ j ≤ J BIT -1 each, said method characterized by the following steps: providing (310) a first code portion A with V A code bits and a second code portion B with V B code bits; assigning a first start position j A (i) of said code portion A within a first memory line i, and assigning a second start position j B (i') for said code portion B in line i' which is either said first memory line or a second memory line (320, 330, 340, 350); and writing (360) into said first memory line V' A ≤ V A code bits of said code portion A from position j A (i) in a first direction to position (j A (i) + V' A ) ≤ j X (i) and writing into first memory line or into said second memory line V' B ≤ V B code bits of said code portion B from position j B (i') ≤ J BIT -1 in a second direction to position j X (i') ≤ (j B (i') - V' B ), wherein j X (i) and j X (i') are virtual partition indices chosen such, that said first portion A and said second portion B are stored in adjacent lines. The method of claim 8 wherein in said writing step, said second direction is opposite to said first direction. The method of claim 8, wherein in said writing step, a single code bit (232) is written into a single memory field (118) and wherein V A ≤ V MAX and V B ≤ V MAX , with V MAX a maximum number of code bits in said code portions. The method of claim 8 wherein the remaining V A -V' A code bits of portion A are written to line i+1 and the V B -V' B code bits of portion B are written to line i'+1. The method of claim 8 further comprising a step of providing an address in which a base address is provided which indicates said first memory line i. A method for storing a data structure (101) in a memory (110) comprising the steps of: receiving (310) a first data portion (222@A) having a first length and a second data portion (222@B) having a second length; selecting (320) an identifier (119) which virtually partitions a memory line into a first partition and a second partition; determining (330) a first distance between said identifier and said first data portion, a second distance between said identifier and said second data portion, a combination of said first and second distances; and comparing (340) said combination to a predetermined reference and ( a ) changing said identifier (350), repeating said determining and comparing steps or ( b ) storing (360) said first data portion in said first partition and store said second data portion in said second partition. The method of claim 13 wherein in said selecting step, said identifier is selected at random from predetermined boundary values. The method of claim 13 wherein said identifier is selected from a range of identifier values. The method of claim 13 wherein said identifier is changed between two alternative values. The method of claim 13 wherein in said selecting step, said identifier is assigned either a first value or a second value. The method of claim 13 wherein in repetitions of said storing step, a first number n A of first data portions each having a maximum length V A MAX is written into said first partition and a second number n B of second data portions each having a maximum length V B MAX is written into said second partition of the same memory line, and wherein n A * V MIN = n B * V MAX . The method of claim 13 wherein in said determining step, said first and second distances are obtained as if said first and second portions would have been already written into said memory line. The method of claim 13 in which j A and j B are start positions of first data portion A within said first partition and second data portion B within said second partition, respectively, and V A and V B are lengths of data portions A and B, respectively, and j X is said identifier, wherein in said determining step, said first distance is obtained as X A = j X -j A - V A , said second distance is obtained as X B = j B - j X +1 - V B , and said combination is Y = | X A - X B | and wherein in said comparing step case (a) corresponds to Y > Y MIN and (b) corresponds to Y ≤ Y MIN . The method of claim 13 wherein said receiving, selecting, and storing steps are repeated for further data portions going into said memory line or into further memory lines. The method of claim 13 wherein in said selecting step, said identifier partitions a memory line (115) with J BIT = 31 bit fields (118) into a first partition α and a second partition β and wherein in said selecting step, said first value is j X = 12 for partition α with 12 bit fields and partition β with 19 bit fields and said second value is j X = 19 for partition α with 19 bit fields and partition β with 12 bit fields. The method of claim 20 wherein Y MIN = 1.

Inventors: BEN-EPHRAIM ARIE, GINSBERG AVI, SAPER ALEXANDRE, BEN-EPHRAIM, ARIE, GINSBERG, AVI, SAPER, ALEXANDRE
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1998
Main classification: G06F9
IPC codes: G06F9