Adiabatic charging logic circuit

Abstract: An adiabatic charging logic circuit includes a logic circuit and a power supply section. The logic circuit is constituted by a plurality of logic elements. The power supply section supplies power to the logic circuit to cause the logic circuit to perform logic processing after an input signal is supplied to the gate of each of the logic elements, and stops supply of the power before a new input signal is supplied to the gate of each of the logic elements after completion of the logic processing.

Description: Background of the Invention The present invention relates to a logic circuit such as a D latch logic circuit which greatly reduces the power consumption and the circuit size by performing adiabatic charging logic using a supply voltage whose waveform moderately rises and falls. An adiabatic charging logic method has received attention as a method of performing logic processing with low power consumption. One of the characteristics of this adiabatic charging logic method is that the supply voltage moderately and periodically changes (moderately rises and falls). Assume that the supply voltage rises from Low (low voltage level) to High (high voltage level) sufficiently slowly as compared with the RC time constant of an inverter serving as a logic circuit. In this case, it is known that the work done by the supply voltage is 1/2•CV 2 , which coincides with the energy stored in a load capacitance. It is also known that when the supply voltage changes from High to Low, the energy stored in the load capacitance is not discharged to ground (GND) but returns to the power supply circuit (charger recycling), thereby ideally performing logic processing of "Low → High → Low" with almost no consumption of energy (reference 1: "Energy-Recovery CMOS" William C. Athas, LOW POWER DESIGN METHODOLOGIES, edited by J. M. Rabaey et al., KLUWER ACADEMIC PUBLISHERS, pp. 66 - 72, 1996). As a power supply circuit for implementing this logic, an AC circuit using an inductor and a capacitor are available. The inductor and the capacitor constitute a resonance circuit to generate an AC voltage. By using this circuit as a charge recycle generator, adiabatic charging and charge recycling can be performed. A circuit that uses N - 1 capacitors to generate an N-step staircase voltage (a voltage that changes/rises in N steps and changes/falls in N steps) is also known (reference 1). With this circuit as well, adiabatic charging and charge recycling can be performed. When, however, adiabatic charging or charge recycling is to be performed in a general CMOS circuit by using a charge recycle generator, even if the rise/fall timing of an output voltage from the charge recycle generator is properly adjusted for one logic gate, the rise/fall timing must be adjusted again for the logic gate on the next stage. A transmission gate type retractile logic circuit, which differs from the above CMOS circuit but is known as a circuit capable of easily realizing adiabatic charging and charge recycling, will be described below as an example of how the timing is difficult to adjust. Fig. 11A shows such retractile logic circuit. Reference numerals 501 to 504 denote logic gates; and 505 and 506, capacitors. This circuit receives input signals A and B, performs AND logic (= A•B) processing for the input signals, and obtains the OR logic (= A•B + C) of the AND logic processing result and an input signal C. As a logic gate of this retractile logic circuit, a two-wire logic element using transmission gates 507 has been proposed, as shown in Figs. 12B and 12C. This element receives complementary input signals A and *A and complementary input signals B and *B and outputs output signals A•B and *(A•B). Note that the symbol "*" indicates that the corresponding signal is an inverted signal. In this retractile logic circuit, the waveforms of supply voltage V1 and V2 are controlled in accordance with the number of gates, as shown in the timing charts of Figs. 11B to 11F. More specifically, control must be performed to cause the supply voltage V1 to moderately (with a constant slope) rise later and fall earlier than the input signals A and B. The same applies to the relationship between the input signal C and the supply voltage V2. Figs. 13A and 13B show a conventional BDD logic circuit. As shown in Fig. 13A, the BDD graph (Binary Decision Diagram) used for this logic circuit is a graph having beginning points 1 and 2 and ending points 3 and 4. Input variables (A, B, and C in Fig. 13A) correspond to nodes 5. When the value of a logic output is to be obtained from supplied input variable values, the input enters from the beginning point 1 or 2 of the graph, goes down along the respective nodes 5, and reaches one of the two ending points 3 and 4. At each node 5, the input goes along one of two branches 6 and 7 in accordance with the input variable value. If, for example, the input variable C is "0", the input goes along 0 branch 6. If C = "1", the input goes along 1 branch 7. That is, when an input is supplied, one path from a beginning point to an ending point is designated. If the ending point of the path is "0", the logic output becomes "0". If the ending point is "1", the logic output becomes "1". In the BDD logic circuit, as shown in Fig. 13B, logic elements that satisfy the above conditions, e.g., N-channel MOSFETs 8 and wires 9, are made to correspond to the respective branches of the BDD on the basis of the BDD graph shown in Fig. 13A. In addition, logic outputs are made to correspond to the beginning points 1 and 2 of the BDD graph. Furthermore, ground (GND) is connected to the ending point 3 of "0" of the BDD graph, and a constant supply voltage VDD is connected to the ending point 4 of "1" of the BDD graph (reference 2: Kuroda and Sakurai, "Overview of Low-Power ULSI Circuit Techniques" IEICE TRANS. ELECTRON., Vol. E78-C, NO. 4 April 1995, pp. 334 - 344). Fig. 14 shows the arrangement of a conventional D latch logic circuit. This logic circuit is made up of two transmission gates 601 and 602 constituting a data receiving circuit, and transmission gates 603 and 604 and inverters 605 and 606 which are cross-connected to constitute a storage circuit. A clock signal CK and an inverted signal *CK thereof are input to the transmission gates 601 to 604, and constant supply voltages VDD are applied to the inverters 605 and 606. In this D latch logic circuit, when the clock signal CK is at High, the signals input to nodes 607 and 608 respectively reach nodes 609 and 610 through the transmission gates 601 and 602 and are inverted by the inverters 605 and 606. The resultant signals are then output to nodes 611 and 612. When the clock signal CK changes to Low, the nodes 610 and 611 are connected to each other, and the nodes 609 and 612 are connected to each other. As a result, the output signals from the inverters 605 and 606 are supplied to the input sides of the inverters 605 and 606 on the opposite sides. The output signals are held until the clock signal CK is set at High again (storage mode). A wire 400 in Fig. 15, which is used in a conventional CMOS logic circuit such as a combinational logic circuit or a D latch logic circuit, has a large cross-sectional area to drive the gate on the next stage at high speed on the order of ps. As shown in Fig. 15, this wire cross-sectional area is 550 nm (0.55 µm: signal wire width W 0 ) x 550 nm (0.55 µm: signal wire thickness H 0 ) in the 0.25-µm process of Nippon Telegraph and Telephone Corporation (NTT). In this case, the CR time constant is about 0.5 ns. In the above retractile logic circuit, as the number of gates increase to several hundreds and several thousands, several hundred and several thousand supply voltage waveforms must be controlled. If, therefore, adiabatic charging and charge recycling are performed by using a charge recycle generator, the power consumption increases contrarily. In the D latch logic circuit, at a transmission gate portion, charging/discharging must be performed with respect to the gate of a MOSFET as an element of the transmission gate or a clock signal line. In this charging/discharging operation, the energy corresponding to C TG VDD 2 (where VDD is the supply voltage and C TG is the sum of the gate capacitance of the transmission gate and the capacitance of the clock signal line) is consumed. In the storage circuit as well, the energy corresponding to C ME VDD 2 (where C ME is the capacitance of the storage circuit) is consumed. In the conventional CMOS logic circuit, since the wire cross-sectional area is set to be large, it is difficult to reduce the circuit size. In addition, the self-capacitance of each wire and the mutual capacitance between the wires cannot be reduced. Summary of the Invention The present invention has been made in consideration of the above situation, and its major object is to provide a logic circuit which can efficiently implement adiabatic charging logic, and can decrease the cross-sectional area of each wire, thereby realizing reductions in power consumption of the circuit and circuit size. In order to achieve the above object, in an adiabatic charging logic circuit comprising a logic circuit constituted by a plurality of logic elements, and a power supply section for supplying power to the logic circuit to cause the logic circuit to perform logic processing after an input signal is supplied to a gate of each of the logic elements, and stopping supply of the power before a new input signal is supplied to the gate of each of the logic elements after completion of the logic processing, as basically disclosed in US-A 5 493 240, there is provided, according to the present invention, a D latch logic circuit forming said logic circuit, which has the features according to the characterizing clause of claim 1. Brief Description of the Drawings Figs. 1A to 1C are views for explaining a D latch logic circuit according to a first embodiment and the waveforms of supply voltages; Figs. 2A and 2B are graphs for comparing/explaining charged/discharged energy at clock portions and storage circuit portions in the present invention and the prior art; Fig. 3 is a circuit diagram showing a D latch logic circuit according to a second embodiment; Figs. 4A to 4C are circuit diagrams showing circuits for generating signals A, B, and C in the circuit in Fig. 3; Figs. 5A to 5H are timing charts showing voltage waveforms in the circuit in Fig. 3; Figs. 6A to 6D are views for explaining a D latch logic circuit according to a third embodiment and supply voltage waveforms; Fig. 7 is a circuit diagram showing a D latch logic circuit according to a fourth embodiment; Figs. 8A to 8D are timing charts showing voltage waveforms in the circuit in Fig. 7; Figs. 9A and 9B are circuit diagrams each showing a D latch logic circuit according to a fifth embodiment; Fig. 10 is a block diagram showing how power supply control is performed on a BDD logic circuit and D latch logic circuit; Figs. 11A to 11F are views for explaining a conventional retractile logic circuit and waveforms in operation; Figs. 12A to 12C are views for explaining how a retractile logic circuit is implemented; Figs. 13A and 13B are circuit diagrams showing a conventional BDD logic circuit; Fig. 14 is a circuit diagram showing a conventional D latch logic circuit; and Fig. 15 is a view showing the cross-sectional area of a wire in a conventional CMOS logic circuit. Description of the Preferred Embodiments The present invention will be described below with reference to the accompanying drawings. [First Embodiment] Fig. 1A shows a D latch logic circuit 90 as a logic circuit according to the first embodiment of the present invention. This circuit 90 is made up of two transmission gates 91 and 92 and cross-connected transmission gates 93 and 94 and inverters 95 and 96 which constitute a storage circuit. In this case, as a supply voltage for each of the inverters 95 and 96, a voltage V3ac whose waveform moderately rises and falls as shown in Fig. 1B is used. As clock signals, a voltage V4ac, which rises after the voltage V3ac falls, falls before the voltage V3ac rises, moderately rises and falls, and has a small duty, and an inverted voltage *V4ac are used, as shown in Fig. 1C. These voltages V3ac and V4ac are generated by using an oscillation type power supply circuit, which is a combination of an inductor and a capacitor, the staircase power supply circuit, which uses a plurality of capacitors to generate a staircase voltage by switching and charging/discharging the capacitors, a charge recycle generator 10(#1), 10(#2) as shown in Fig. 10 such as a power supply circuit for generating a voltage by using one or a plurality of sine waves or an AC voltage obtained by an inductor for inducing the electromagnetic wave. In addition, waveforms obtained by shifting the phase of V2ac from that of V1ac by 180° can be used. Furthermore, a charge no recycle generator can be used to generate the voltage V3ac and V4ac. In this D latch logic circuit 90, while the voltage V4ac changes like Low → High → Low, the transmission gates 91 and 92 are temporarily turned on. At this time, the signals input to nodes 97 and 98 are transferred to nodes 99 and 100. When the voltage V4ac changes from High to Low, the transmission gates 91 and 92 are turned off, and the transmission gates 93 and 94 are turned on. As a result, the circuit is set in the storage mode. In the storage mode, since V3ac = 0 at first, even if the output signals from nodes 102 and 103 should be set High, the potentials of the nodes have decreased to the voltage Vth (the threshold voltage of p-channel MOSFETs constituting the inverters 95 and 96). When the output signals are to be set Low, the potentials of the nodes remain at 0 V. When the voltage V3ac rises from 0 V to a supply voltage VDD, the potentials of the nodes 102 and 103 set at the threshold Vth slowly rise to the supply voltage VDD. When the voltage V3ac rises from VDD to 0 V afterward, the potentials of the nodes 102 and 103, which have been set at the supply voltage VDD, decrease to the threshold voltage Vth. With this process, adiabatic charging is performed while the voltage V3ac rises from the threshold voltage Vth to the supply voltage VDD. If a charge recycle generator is used to generate the voltage V3ac, the charge is adiabatically recycled to the V3ac power supply side while the voltage V3ac drops from the supply voltage VDD to the threshold Vth. Such adiabatic charging and charge recycling are also executed at the transmission gate portion driven by the voltages V4ac and *V4ac in the same manner as described above. As described above, in the conventional circuit (Fig. 14), the energy required for charging at the portion (transmission gates 91 to 94) driven by clock signals is C TG VDD 2 , whereas the energy required for charging in the circuit of the present invention is C TG VDD 2 •2τ/T, i.e., 2τ/T times the energy in the conventional circuit. In this case, τ is the CR time constant of the circuit that is charged by the voltage V4ac, and T is the rise time (fall time) of the voltage V4ac. If, therefore, τ << T is set to perform charging/discharging sufficiently slowly, the energy can be sufficiently reduced, as shown in Fig. 2A. This allows a reduction in power consumption. On the other hand, the charge energy in the portion associated with a storage circuit in the circuit of the present invention can be reduced from 1/2•C ME VDD 2 in the conventional circuit to 1/2•C ME Vth 2 because information is stored at Vth instead of VDD. Therefore, the energy required to charge/discharge this portion, which is C ME VDD 2 in the conventional circuit as described above, becomes C ME Vth 2 + C ME VDD 2 •2τ/T (Fig. 2B). Note that T and τ are equal to those in the portion driven by clock signals. As is obvious from the above description, the D latch logic circuit 90 allows reduction in power consumption at both the transmission gate portion and the storage circuit portion. [Second Embodiment] Fig. 3 shows a D latch logic circuit according to the second embodiment of the present invention. In this circuit, the outputs of charge recycle type BDD logic circuits 110 and 120 are connected to the nodes 97 and 98 on the input side of the D latch logic circuit 90 in Fig. 1A. The BDD logic circuits 110 and 120 are formed by combining n-channel MOSFETs 8 and p-channel MOSFETs 24. Signals A, B, and C to be applied to the gates of these MOSFETs are obtained by waveform conversion of input signals *a, *b, and *c, each having a rectangular wave, (inverting each signal and making the rising and falling slopes correspond to the rising and falling slopes of a voltage V3ac) by using inverters 131 to 133 to which the voltage V3ac is applied as supply voltage, as shown in Figs. 4A to 4C. In this case, the p-channel MOSFETs 24 are connected between the outputs of the BDD logic circuits 110 and 120 and nodes 97 and 98 of the D latch logic circuit 90 in Fig. 3, and the inverted voltage *V5ac of a voltage V5ac having a waveform like the one shown in Fig. 5B is applied to the gate of each p-channel MOSFET 24. This voltage V5ac is also generated by the charge recycle generator or the charge no recycle generator described above. This voltage has a waveform that rises later and falls earlier than the voltage V3ac in Fig. 5A, and is also applied to one of the ending points of the BDD logic circuit 110 and the other ending point of the BDD logic circuit 120. The operation of the BDD logic circuit shown in Fig. 3 will be described next. First of all, the input signals A, B, and C are input to the BDD logic circuits 110 and 120 while changing to High and Low in synchronism with the voltage V3ac. When the voltage V5ac rises, supply voltages are applied to the BDD logic circuits 110 and 120. In these circuits, logic processing (Exclusive OR (XOR) of the signals A, B, and C is performed in the BDD logic circuit 110, and Exclusive NOR (XNOR) of the signals A, B, and C is performed in the BDD logic circuit 120), and the logic processing results (Low-level or High-level signals) are transferred to the nodes 97 and 98 in synchronism with the leading edge of the voltage V5ac. Thereafter, the voltage V5ac falls. At this time, the signals are stored in the nodes 97 and 98. After the voltage V5ac falls, the voltage V3ac also falls. As a result, the input signals A, B, and C at the BDD logic circuits 110 and 120 fall. When a voltage V4ac rises, transmission gates 91 and 92 are turned on, and the signals at the nodes 97 and 98 are transferred to nodes 99 and 100. Subsequently, the same operation as that of the circuit in Fig. 1A is performed in the D latch logic circuit 90 to output the inverted signals of the signals input to the nodes 97 and 98 to nodes 102 and 103 in synchronism with the voltage V3ac. A signal Q or an inverted signal *Q output from each of the nodes 102 and 103 can be used as an input signal to a D latch logic circuit on the next stage, which has the same arrangement as that described above, or as one of the input signals A, B, and C to the BDD logic circuits 110 and 120. Figs. 5D to 5H explain a case wherein the outputs from the D latch logic circuit 90 are input to the BDD logic circuits 110 and 120. As described above, in the logic circuit according to the second embodiment, logic processing is performed in the BDD logic circuits 110 and 120 by adiabatic charging and charge recycling, and the processing results are input to the D latch logic circuit 90 to be subjected to logic processing by adiabatic charging and charge recycling in the same manner as described above. Since the output signals can be sent to another circuit on the next stage or the input sides of the BDD logic circuits 110 and 120, low power consumption can be realized. [Third Embodiment] Fig. 6A shows a D latch logic circuit according to the third embodiment of the present invention, in which an inverter circuit 130 constituted by inverters 104 and 105 is connected to the nodes 102 and 103 of the D latch logic circuit 90 shown in Fig. 1A. Referring to Fig. 1A, reference numerals 106 and 107 denote output nodes. As shown in Fig. 6C, a supply voltage V6ac applied to each of the inverters 104 and 105 moderately rises and falls, and rises later and falls earlier than voltage V3ac in Fig. 6B. This supply voltage V6ac is also generated by the charge recycle generator or charge no recycle generator described above. Assume that a load having a very large capacitance is connected to the output nodes 102 and 103 of the D latch logic circuit 90 without the inverter circuit 130. In this case, even when the node 102 or 103 should be set High by a signal transferred through a transmission gate 93 or 94 (since V3ac = 0 V in this case, the node is set at a threshold Vth as described above), the node instantaneously becomes 0 V. This potential is transferred to the load side. This may cause a data retention error. In contrast to this, in this embodiment, the inverter circuit 130 is connected to the nodes 102 and 103, and a load having a large capacitance is connected to the nodes 106 and 107 of the inverter circuit 130. With this arrangement, since the nodes 106 and 107 do not directly receive the signals transferred through the transmission gates 93 and 94, data can be properly retained. [Fourth Embodiment] Fig. 7 shows a D latch logic circuit according to the fourth embodiment of the present invention, in which the BDD logic circuits 110 and 120 shown in Fig. 3 are connected to the nodes 97 and 98 on the input side of the D latch logic circuit 90 shown in Fig. 6A. In this embodiment, voltages V3ac, V4ac, V5ac, and V6ac having timings and waveforms like those shown in Figs. 8A to 8D are used. Of these voltages, the voltage V5ac has a waveform that rises later and falls earlier than that of the voltage V6ac, and the voltage V6ac has a waveform that rises later and falls earlier than that of the voltage V3ac. As a result, processing contents (XOR and XNOR) of signals A, B, and C input to the respective MOSFETs of the BDD logic circuits 110 and 120 are output to nodes 97 and 98 in synchronism with the voltage V5ac, and then transferred to nodes 99 and 100 in synchronism with the voltage V4ac, the nodes 102 and 103 in synchronism with the voltage V3ac, and nodes 106 and 107 in synchronism with the voltage V6ac. The signals obtained at the nodes 106 and 107 can be used as input signals to the BDD logic circuits 110 and 120. [Fifth Embodiment] Fig. 9A shows a D latch logic circuit 90A according to the fifth embodiment of the present invention, in which the transmission gates 91 and 92 of the D latch logic circuit 90 in Fig. 1A are replaced with n-channel MOSFETs 8. In this case, a non-inverted voltage V4ac is applied to the gate of each n-channel MOSFET 8. Note that the transmission gates 91 and 92 may be replaced with p-channel MOSFETs 24 as in a D latch logic circuit 90B in Fig. 9B. In this case, an inverted voltage *V4ac of the voltage V4ac is applied to the gate of each p-channel MOSFET 24. By using a single MOSFET as transmission gate in this manner, the number of transistors can be decreased. As has been described above, according to the present invention, in a D latch logic circuit, or the like having several hundred or several thousand gates, adiabatic charging and charge recycling can be realized very easily. This can attain reduction in power consumption and circuit size as compared with the conventional CMOS logic circuit and D latch logic circuit. In addition, according to the present invention, since charging/discharging is performed adiabatically, the density of a current flowing in each metal wire and each transistor is very low. For this reason, the electromigration effect on each wire is small, and the cross-sectional area of each wire can be greatly decreased as compared with the cross-sectional area of each wire in a CMOS logic circuit. This allows a reduction in wire capacitance. As described above, according to the present invention, efficient logic processing can be realized by transfer of a smaller number of electrons, and hence the energy per logic operation can be greatly reduced as compared with the conventional CMOS logic circuit.

Claims: An adiabatic charging logic circuit comprising: a logic circuit (30A, 30B, 90) constituted by a plurality of logic elements; and a power supply section (10(#1), 10(#2)) for supplying power to said logic circuit to cause said logic circuit to perform logic processing after an input signal is supplied to a gate of each of the logic elements, and stopping supply of the power before a new input signal is supplied to the gate of each of the logic elements after completion of the logic processing, characterized in that said logic circuit is a D latch logic circuit (90) including a signal receiving circuit constituted by a first transmission gate pair (91, 92), and a storage circuit having a first inverter pair (95, 96) for inverting output signals from the first transmission gate pair and a second transmission gate pair (93, 94) which are turned on to cross-couple the output of each inverter of the first inverter pair to the input of the respective other inverter of the first inverter pair when the first transmission gate pair are turned off, whereby said logic circuit uses a first voltage that moderately rises and falls as a supply voltage from said power supply section to the first inverter pair, and uses a second voltage, which rises after the first voltage falls and falls before the first voltage rises, and an inverted voltage thereof as gate voltages to be applied to the first and second transmission gate pairs. A circuit according to claim 1, wherein a second inverter pair (104, 105) is connected to output sides of the first inverter pair, and a supply voltage to the second inverter pair is a third voltage that rises later and falls earlier than the first voltage. A circuit according to claim 1 or 2, wherein the first transmission gate pair is a transmission gate pair comprising one of a p-channel MOSFET and an n-channel MOSFET.

Inventors: DOUSEKI TAKAKUNI, HARADA MITSURU, NAKATA SHUNJI, TAKEYA KEN, DOUSEKI, TAKAKUNI, HARADA, MITSURU, NAKATA, SHUNJI, TAKEYA, KEN, Douseki, Takakuni, Nippon Telegr. &amp; Teleph. Corp., Harada, Mitsuru, Nippon Telegr. &amp; Teleph. Corp., Nakata, Shunji, c/o Nippon Telegr. &amp; Teleph. Corp., Takeya, Ken, c/o Nippon Telegr. &amp; Teleph. Corp.
Applicants: NIPPON TELEGRAPH & TELEPHONE, NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Application year: 1998
Main classification: H03K19
IPC codes: G06F7, H03K19