INVERTER CIRCUIT BIASED TO LIMIT THE MAXIMUM DRIVE CURRENT TO A FOLLOWING STAGE AND METHOD

Abstract: An inverter circuit (110), suitably implemented in the feedback loop of a series pass regulator, limits the maximum drive current through an output drive transistor (Q2) connected to control the regulator's pass transistor (Q3). A first current source i1 biases an inverting amplifier that includes a transistor (Q1) and an output resistor R (R1), which inverts an input signal received from an emitter follower (Q4) and feeds the inverted signal to an output drive transistor (Q2) which has its collector connected to the base of the pass transistor. A second current source i2 is connected to allow the inverter's input signal to follow the emitter follower negative. When the follower is cut-off, i2 flows through the output resistor and increases the voltage of the signal fed to the output drive transistor by i2 x R. The increased voltage establishes a maximum drive current based on i1, i2 and R, which is independent of the betas of the individual transistors.

Description: INVERTER CIRCUIT BIASED TO LIMIT THE MAXIMUM DRIVE CURRENT TO A FOLLOWING STAGE AND METHOD BACKGROUND OF THE INVENTION Field of the Invention This invention relates to the field of current limiting circuits, particularly circuits used to limit the drive current delivered to the control input of a voltage regulator's pass transistor. Description of the Related Art A conventional series pass voltage regulator is shown in FIG. la. A supply voltage V ιr is connected to the emitter 10 of a "pass transistor" 12, typically a pnp bipolar transistor, and an output voltage V out is taken at the transistor's collector 14. The output voltage is regulated by controlling pass transistor 12 via its base terminal 16. Regulation is accomplished with a feedback loop: the output voltage is fed back to the inverting input 18 of an error amplifier 20, typically an operational transconductance amplifier (OTA) , usually via a voltage divider 22. A voltage reference V ref is connected to the non-inverting input 24 of the amplifier. The amplifier's output is connected to the control input 26 of an output drive transistor 28, whose current circuit is connected to the pass transistor' s control input 16. In operation, error amplifier 20 produces the output necessary to make the voltage at its inputs 18 and 24 equal. Increasing the drive current to output drive transistor 28 increases its collector current i c , which in turn increases the current flow through pass transistor 12 and raises output voltage V out . A regulator such as that shown in FIG. 1 is commonly fabricated as an integrated circuit (I.C.) . A problem arises with such an integrated regulator as a result of the unpredictability of the respective "betas" (β) of the transistors in the regulation loop. The OTA 20 has an output transistor 30 having a beta of βl, output drive transistor 28 has a beta of β2, and the pass transistor has a beta of β3. Manufacturing tolerances make it difficult to attain a particular beta value for a particular transistor; rather, a range of possible beta values is typically all that can be predicted. To insure that the regulator can deliver its rated output voltage and current, the regulation loop is usually designed based on "worst case" beta values, resulting in transistors that are likely to be oversized. If V 0j- drops below its rated value, because the regulator output is short-circuited, for example, the regulator loop will attempt to force V ou back up. However, if βl is not at its "worst case" value, the drive into output drive transistor 28 may be higher than desired. This high drive current can be compounded by a higher-than-expected β2, resulting in a very high i c at the pass transistor's base 16. A higher-than-expected β3 compounds the problem further, and can result in a current through pass transistor 12 that is high enough to damage transistor 12 and associated components. A simplified schematic of a "low drop-out" (LDO) series pass regulator, described in U.S. Patent No. 5,631,598 to Miranda et . al and assigned to the present assignee, is shown in FIG. lb. The signals connected to the inputs 18 and 24 of OTA 20 are reversed, and an inverting stage 50 is interposed between the OTA' s output and output drive transistor 28. The phase inversion provided by inverting stage 50 permits the connection of a frequency compensation capacitor C c between the output of OTA 20 and the V out terminal. This regulator, however, also suffers from the problem discussed above: because the regulator must be designed to accommodate uncertain "worst case" beta values, the potential for overdriving and damaging the pass transistor is unacceptably high. SUMMARY OF THE INVENTION An inverter circuit is presented which overcomes the problems described above. The circuit, suitably implemented in the feedback loop of a series pass regulator, limits the maximum drive current through an output drive transistor connected to control a following stage, while also providing a phase inversion. Limiting the drive current serves to protect the device to which the drive transistor is connected, typically the pass transistor of a series pass regulator. The limit is established by appropriately selecting the values of two current sources and a resistor, and is independent of the betas of the transistors in the loop. In a preferred embodiment, a bipolar transistor is configured as an inverting amplifier: an input resistor is connected to its base, an output resistor is connected between base and collector, and the transistor is biased with a first current source il. The input to the inverter is produced by an emitter follower or diode, and the inverter's output is fed to the base of an output drive transistor whose collector is connected to the base of a pass transistor. As the input to the inverter increases, the signal to the output drive transistor decreases, as does the current to the pass transistor. When the input to the inverter decreases, output drive transistor current increases. However, because the follower voltage at the input to the inverter can only fall to about the same level as the inverter's output voltage, the output drive current is limited to a value about equal to il (or N x il if the inverter and output drive transistors have different emitter areas, with N equal to the ratio between them) . This is remedied by adding a second current source i2 to the circuit, connected to allow the inverter input to follow the emitter follower's output negative, so that the base of the output drive transistor can be driven more positive. Current source i2 serves two beneficial purposes. First, it provides for an increased current in the output drive transistor because, when the emitter follower is cut-off, i2 flows through the output resistor and increases the output drive transistor's base voltage. This enables an output drive current to be obtained that is substantially greater than il even without using an emitter area ratio, though both techniques are preferably employed. Secondly, as explained below, the output drive current is related to the increased base voltage obtained with i2. As a result, a hard limit is established for the output drive current with appropriate selection of the circuit's il, i2 and output resistor values, which is set as necessary to protect the pass transistor and associated components. Variations on the basic inverter circuit include circuitry which establishes a maximum current limit that falls with increasing temperature, and which can accommodate manufacturing variations in the pass transistor's beta. Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. la is a schematic diagram of a prior art series pass voltage regulator. FIG. lb is a schematic diagram of a prior art series pass voltage regulator which includes an inverter stage. FIG. 2a is a schematic diagram of an inverter circuit biased to limit the maximum current through an output drive transistor, as implemented m a series pass voltage regulator. FIG. 2b is a schematic diagram illustrating an alternative connection of a current source in the circuit of FIG. 2a. FIG. 2c is a schematic diagram illustrating an alternative configuration of a current source in the circuit of FIG. 2a. FIG. 3a is a schematic diagram of a preferred embodiment of the present invention. FIGs. 3b and 3c are schematic diagrams of alternate implementations of a pull-down current source in the circuit of FIG. 3a. FIG. 4 is a schematic diagram of an embodiment of the present invention using pnp transistors and using a current source with a negative temperature coefficient. FIG. 5 is a schematic diagram of an embodiment of the present invention illustrating a technique for accommodating manufacturing variations in the beta of a series regulator's pass transistor. DETAILED DESCRIPTION OF THE INVENTION A schematic diagram of an inverter circuit 100 per the present invention is shown m FIG. 2a, implemented in the feedback loop of a series pass voltage regulator. A transistor Ql, shown here as an npn bipolar transistor (though other transistor types are permitted, as discussed below) , is configured as an inverting amplifier: an output resistor Rl is connected between Ql's collector and base, an input resistor R2 is connected between its base and the inverter' s input node 102, and a current source il is powered by a positive supply voltage V+ and supplies current il to the node 104 between Rl and the collector. As used herein, reference labels attached to respective current sources also refer to the current generated by that current source; i.e., current source il generates a current il. Ql's emitter is connected to a supply voltage V-, which can include regulator ground. Node 104 serves as the inverting amplifier's output, with the amplifier's gain given by - R1/R2. Rl and R2 are preferably made equal to provide maximum bandwidth, which is desirable in feedback control applications. Node 104 is connected to the control input of an output drive transistor Q2, shown here as an npn bipolar transistor. The collector of transistor Q2 serves as the output of the inverter circuit, with Q2 ' s collector current herein referred to as "drive current" i c2 ; Q2 ' s collector is connected to the base of pass transistor Q3. The current through pass transistor Q3 is controlled by the drive current i c2 through Q2, which is modulated in accordance with the signal applied at Q2's base; i.e., i c2 increases as the voltage at Q2's base increases. Pass transistor Q3 is connected to a supply voltage V ιn at its emitter, and the regulator' s output voltage V ou , appears at its collector. The inverter' s input node 102 is typically driven by a follower device 106, typically either an emitter follower transistor Q4 (shown) or a diode, which may be a component of or separate from an operational amplifier 108, typically an operational transconductance amplifier (OTA) . Amplifier 108 is configured as a non-inverting error amplifier and forms part of the regulator' s feedback loop, receiving a voltage fed back from the regulator' s output V out at a non-inverting input and a reference voltage V ref at an inverting input, and producing an error voltage at an output. Voltage regulation is accomplished as follows: when V out falls below its desired value, error amplifier 108 causes the voltage at the output of follower 106 to also fall. The voltage at inverter amplifier output node 104 increases as inverter input node 102 falls, increasing the current i c2 through output drive transistor Q2. An increase in i =2 increases the current through the pass transistor Q3, which raises the output voltage V out . Conversely, a V out that is too high increases the voltage at input node 102, which decreases i c2 and the current through pass transistor Q3, lowering V out . Voltage regulators of the sort shown in FIG. 2a are commonly fabricated as an I.e., and are often battery- powered. As a result, small component size and high efficiency are important design considerations. A regulator's pass transistor typically passes a considerable amount of current, and in turn requires a good deal of current at its control input to provide the necessary regulation. In light of these design considerations, it is desirable that the inverter circuit 100 consume as little current as possible to produce the necessary amount of drive current i c2 . One way in which current source il and Ql can be kept small is by fabricating Q2 with a bigger emitter area than Ql, with a ratio N between Q2's emitter area and Ql's emitter area. With nothing connected to inverter input node 102 except follower 106 and R2, when the input to follower 106 goes negative enough to cut off Q4, the voltage at the base of Q2 is about the same as that at the base of Ql (neglecting the small current into the base of Ql). Q2 essentially mirrors the current through Ql, so that the collector current i c2 is limited to a maximum of about N x il. In order to: l)get more collector current i c2 for a given il, and to 2 ) simultaneously provide a simple means of establishing a maximum value for i c2 , a current source i2 is connected to inverter input node 102. Now, as the output of follower 106 falls, more and more of i2 is drawn through output resistor Rl, with all of i2 drawn through Rl when Q4 is cut-off. With i2 flowing through Rl, the voltage at the base of Q2 is increased over the voltage at the base of Ql by an amount ΔV = i2 x Rl . This increased voltage acts to increase the collector current i c2 for a given il, achieving the first of the goals stated above. The second stated goal is achieved by noting that the emitters of Ql and Q2 are connected to the same potential, so that ΔV is given by: ΔV = V De2 - V bel = kT/q ln(i c /(N x il)) (Eq. 1) Solving for the drive collector current i c2 through Q2 (and neglecting base currents and the loading of il by 12) : i c2 = W(il)e (l2 x w w* (Eq. 2) Thus, a maximum drive current i c2 (max.) through Q2 is established by specifying particular values for il, i2 and Rl . The drive current X(max.) is independent of the betas of any of the transistors in the feedback loop. Therefore, even when a regulator is designed based on its transistors' "worst case" betas, use of the innovative inverter circuit herein described eliminates the danger of overdriving and damaging regulator components arising from that practice. In addition to its current-limiting function, the present inverter circuit also provides a phase inversion in a voltage regulator's feedback loop. Thus, a capacitor C c can be connected between the regulator's output V out and the output of error amplifier 108 to frequency compensate the regulator, as described in the U.S. patent to Miranda et . al cited above. Though the inverter circuit is implemented in FIG. 2a with npn transistors (except for pass transistor Q3) , the circuit can also be implemented with pnp transistors - an example of which is discussed below in conjunction with FIG. 4. FET's can also be used to implement a functionally similar inverter circuit, preferably driving a bipolar pass transistor. Note, however, that Equations 1 and 2 above would not be applicable to an all-FET implementation, though similar equations based on the behavior of FETs could still be used to define a maximum limit on drive current. The invention is described as implemented in the feedback loop of a voltage regulator, but is not limited to this application. The inverter circuit would be useful whenever it is desirable to establish a maximum drive current through an output drive transistor which is connected to control a following stage, such as in an amplifier in which a common emitter stage drives a complementary common emitter stage. Also, because the invention can drive common emitter pass devices, it is useful for amplifiers that need to drive their output voltage close to the supply voltage. Two inverter circuits could be used to create a "rail-to-rail" output stage, one inverter using npn transistors as in FIG. 2a, and one using pnp transistors, with the collectors of the respective output drive transistors tied together to make an output driver that could source or sink current. An alternative connection of current source i2 is shown in the schematic diagram of FIG. 2b, in which a portion 110 of the schematic of FIG. 2a is redrawn. Here, current source i2 is connected directly to the base of Ql. Current i2 continues to affect i c2 (max.) as defined in Equation 2, but the voltage range over which the follower output affects i c2 is shifted. When connected as shown in FIG. 2b, the follower is cut-off (and i c2 (max.) is reached) when the voltage at node 102 falls below that at the base of Ql . When configured as in FIG. 2a, i c2 (max.) is reached when the voltage at node 102 falls below the voltage at the base of Ql minus (i2 x R2) . These two configurations of i2 offer some design flexibility over the value of the voltage at the emitter of Q4 when i c2 (max.) is reached. An advantage of connecting i2 directly to the base of Ql is shown in FIG. 2b: that of generating a signal which indicates when i =2 has reached its maximum value. A threshold detector is created by arranging two transistors Q thl and Q th2 into a differential pair biased with a current source i tn . An output OUT is taken from the collector of Q thl ; a signal appears at OUT when the voltages at the bases of Q thl and Q th2 are unequal. A dual- emitter transistor Q tr3 is used as the follower device 106, with one emitter 112 connected to inverter input node 102. The base of Q thl is connected to the base of Ql, and the base of Q th2 is connected to Q th3 ' s other emitter 114. The voltage at each of Q t X s emitters will be about equal, tracking Q C X s base voltage, until i c2 (max.) is reached. As noted above, with i2 connected as shown in FIG. 2b, the voltage at the base of Ql and at input node 102 are about equal when i c2 (max.) is reached. If Q t X s base continues to go negative, emitter 112 will remain at Ql's base voltage. Emitter 114, however, not connected to node 102, will continue to fall with Q th3 ' s base, as long as a small pull-down current source i pd is connected to it. A differential voltage is thus developed across Q thl and Q th2 when the regulator calls for a drive current in excess of i c2 (max.), and a signal indicating this condition appears at the OUT terminal. Another approach to the implementation of current source i2 is shown in FIG. 2c. Here, output resistor Rl is split into two resistors R a and R b and i2 is split into two current sources i2a and i2b. R a , R b , i2a and i2b are arranged to produce a ΔV at node 104 which provides the desired i c2 (max.); ΔV is now given by: ΔV = (R b x i2a) + (R a + R b ) x i2b This type of arrangement, illustrated as a composite of two current sources but amenable to further division, permits i2 to be a composite of several different currents, each of which can have a different behavior with respect to temperature, transistor beta, or some other parameter which one might choose to set i =2 (max.). Alternatively, i2a and i2b might be currents that happen to be available, but which need to be properly proportioned to produce the desired value of i2. R a and R b are chosen as necessary to produce the desired scaling. A more detailed schematic diagram of the present invention as used in a voltage regulator is shown in FIG. 3a. One convenient means of implementing current source i2 employs a transistor Q5, shown here as an npn bipolar transistor, having its base connected to the base of Ql and its collector connected to inverter input node 102, with a resistor R3 connected between Q5's emitter and V- . Together, Ql, Q5 and R3 operate like a Widlar mirror to produce a well-defined current i2 from the collector of Q5. In this arrangement, i2 is a function of il, so that i c2 (max.) is a function of il and R3. Note that while convenient to connect the base of Q5 to the base of Ql, the base of Q5 can be driven with other voltages unrelated to the inverter circuit. This will be discussed in more detail below. Base currents were neglected in Equation 2 above. However, if the ratio of i c2 (max.) to il is large, as it usually will be, the loading due to the base current of Q2 may not be negligible. In order to accommodate a high i c2 (max.) to il ratio, a buffer transistor Q6, shown here as an npn bipolar transistor, is included in the circuit of FIG. 3a. The base of Q6 is connected to the inverter amplifier's output node 104 and its emitter connected to the base of output drive transistor Q2. In this emitter follower configuration, Ql's collector, i.e., high impedance node 104, is no longer required to supply base current to Q2. Q6 buffers node 104, serving to drive Q2, and to supply i2 by way of Rl and R2. A source of current 116 must be connected to the emitter of Q6 to allow it to swing negative. One convenient way of providing the necessary pull-down current is with a current source i3. This configuration is shown in the schematic diagram of FIG. 3b, in which a portion 120 of the schematic of FIG. 3a is redrawn. A transistor Q7, shown here as an npn bipolar transistor, has its base connected in common with the base of Ql, its collector connected to the emitter of Q6, and a resistor R4 connected between Q6's emitter and V- . Note that while convenient to connect the base of Q6 to the base of Ql, the base of Q6 can be driven with other voltages unrelated to the inverter circuit. Another possible way to implement the source of current 116 is shown in the schematic diagram of FIG. 3c, in which a portion 120 of the schematic of FIG. 3a is redrawn. Here, a resistor R5 is connected between the emitter of Q6 and V- to supply pull-down current to Q6. The use of pull-down resistor R5 may also improve the stability of the regulator at light loads. The base- emitter voltage of output drive transistor Q2 is across R5, so that the current through Q6 is at least partially complementary-to-absolute-temperature (CTAT) . If Q6's collector current is drawn through a base hold-down resistor R hd connected across the base and emitter of pass transistor Q3, the collector current will approximately track demand by R hd over temperature. This enables the use of smaller R hd values, which is desirable because large R hd values can lead to non-linear relaxation oscillation at light loads. The novel inverter circuit can also be implemented with pnp transistors as shown in FIG. 4, and used, for example, in a voltage regulator circuit which receives a negative supply voltage V ιn _ and generates a negative output voltage V out .. Here, pass transistor Q10 is an npn , and inverter transistor Qll, output drive transistor Q12, and buffer transistor Q13 are all pnps . The input to the inverter is typically a pnp follower transistor Q14. The inverter amplifier is biased by a current source i4, the follower transistor by a current source i5, and the buffer transistor by a current source i6. The beta of pass transistor Q10 increases with temperature. This can be approximately compensated for by making current source i4 have a negative temperature coefficient (TC) . One implementation of current source i4 which produces a bias current with a negative TC is shown in FIG. 4. A pnp transistor Q15 has a resistor R6 connected between its emitter and its base, which is connected to the emitter of a pnp transistor Q16. Q16's emitter-base junction is forward-biased, and the resulting current through Q16 pulls Q15's base low and makes Q15 active. Q15's V be appears across R6, making the current through R6 CTAT. This CTAT current flows through Q16 and is reflected with a current mirror formed from a diode-connected transistor Q17 and a transistor Q18 whose base is connected to Q17's base. A bias current with a negative TC thus appears at Q18's collector, i.e., i4 ' s output, which approximately compensates for the variation in QlO's beta over temperature. As noted in Equation 2 above, for the circuits in FIGs. 2a and 3a, the drive current i c2 is given by: i c2 = N( i l ) e ( l2 x RD/i -w i) Because temperature (T) appears in the equation, the ratio of i c2 to il varies with temperature. However, if current source i2 is implemented to generate a current that is largely proportional-to-absolute-temperature (PTAT), T can be virtually eliminated from the equation, making the ratio of i c2 to il virtually temperature- invariant . In the embodiments discussed to this point, current source i2 has been derived from current source il. It is not essential, however, that i2 be derived from il; i2 can, if fact, be completely independent of il. In the schematic diagram of FIG. 5, a current source i PTAT is connected to node 102 which generates a PTAT or nearly PTAT current. Current i PTAT through an approximately constant value of Rl results in a PTAT ΔV (= i PTAT x Rl), and therefore an approximately constant ratio of i c2 to il over temperature. Current sources which produce a PTAT output are well-known, and are discussed, for example, in P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits. (2 nd Ed.) John Wiley & Sons (1984), pp. 282-283. A further improvement in the inverter circuit is also illustrated in FIG. 5. In general, i c2 (max.) is tailored to fit an estimate of the base current required to produce a minimum output from the pass transistor Q3. One factor included in this estimate is the temperature sensitivity of the pass transistor's beta, with i c2 (max.) required to provide a current large enough to drive a pass transistor having the lowest beta anticipated in manufacture, as influenced by temperature, to produce the stated minimum output. The technique described below enables the inverter circuit to accommodate the expected manufacturing variability found in the betas of different pass transistors. In the circuit of FIG. 5, i c2 is made to correlate to the actual beta of a transistor Q19, which is about equal to that of pass transistor Q3. A current i out , proportional to a desired maximum regulator output current i max , is delivered to the collector of a pnp transistor Q19 whose emitter is connected to a positive voltage. A means 130, preferably a pnp transistor Q20 with its base connected to i out and its emitter connected to Q19's base, supplies current to the base of Q19. Current i out causes the collector of Q19 to go negative, driving Q20 on until it supplies the base current needed by Q19 to operate at i out . This arrangement results in Q19's base current being about equal to i out divided by the beta of Q19, and this beta-dependent current is produced at Q20's collector as bias current il, which falls as Q19's beta rises. Current il is connected to the collector of inverter transistor Ql and the base of buffer transistor Q6. As seen in Equation 2 above, the current i c2 driving Q3 is directly proportional to il, and is independent of the betas of the inverter and output drive transistors. However, i raax , about equal to i c2 (max.) x β Q3 , remains dependent on Q3 ' s beta. Q19 and pass transistor Q3 are operated at similar current densities and are manufactured on the same I.C. die, so that their respective betas are typically well correlated. This correlation reduces the dependence of i max on Q3 ' s beta: if Q3 ' s beta is near the top of its expected range, so too will be Q19's, which results in a reduction in the il current delivered to the output drive transistor. Conversely, a Q3/Q19 beta near the low end of their expected range increases the value of il. Having il depend on the Q3/Q19 beta that happens to result when Q3 is manufactured keeps i max within a tightly constrained range. Bias current il is delivered to inverter transistor Ql and is mirrored to output drive transistor Q2. This mirroring includes the factor N equal to the ratio of Q2 ' s emitter area to Ql's emitter area, and a factor set by the ΔV (= i PTAT x Rl) . Both of these factors must be taken into account to properly size i out . For example, assume i out is set to 1 ma, i max is 100 ma, N is 5, and i c2 increases by a factor of 20 due to i PTAT flowing through Rl at i =2 (max.) (which occurs when i PTAT x Rl = (kT/q)ln20 = 78mv at T~300°K) . The drive current limit i c2 (max.) is given by: i c2 (max.) = 1 ma/β Q19 x 5 x 20 = 100 ma/β Q19 Delivering this current to the base of Q3 results in an i raax of 100 ma when i c2 (max.) flows through Q2. Though FIG. 5 is shown using npn transistors for Ql, Q2, and Q6, and pnp transistors for Q3, Q19, and Q20, an equivalent circuit that generates a negative V out is made by reversing the polarities of the transistors, as well as the directions of the respective current source outputs . Use of a beta-dependent il enables i max to be kept within a tightly constrained range at a particular temperature. This arrangement is preferably combined with the use of current source i PTAT (discussed above in connection with FIG. 5) and its resulting temperature invariant i c2 (max.) to il ratio, to provide an i max that is kept within a tightly constrained range over a broad temperature range. While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.

Claims: I CLAIM : 1. An inverter circuit biased to establish a maximum drive current connected to control a following stage, comprising: an inverter transistor (Ql) having a control input and first and second current terminals, a first resistance Rl connected to feed back the voltage at said first current terminal to said control input, a first current source il connected to said first current terminal and biasing said inverter transistor to invert an input signal suitably produced by a follower device (106) and presented at said control input, said inverted signal appearing at said first current terminal, an output drive transistor (Q2) having a control input and a current circuit, said output drive transistor connected to receive said inverted signal at its control input and producing a drive current i c2 in said current circuit in response to said inverted signal, and a second current source i2 connected to enable the voltage at said inverter transistor's control input to be pulled lower than the voltage at said first current terminal and thereby increasing the voltage attainable at said first current terminal, the values of il, i2, and Rl establishing a maximum drive current i c2 (max.) which can flow in said output drive transistor's current circuit independent of the respective gain characteristics of said inverter and output drive transistors. 2. The inverter circuit of claim 1, wherein i2 increases the voltage at said first current terminal by a voltage given by i2 x Rl when i c2 (max.) flows through said output drive transistor. 3. The inverter circuit of claim 2, wherein said drive current is given by i c2 = (il) e (l2 x R1),(kτ c3) . 4. The inverter circuit of claim 1, further comprising a second resistance R2 connected between said inverter transistor's control input and the source of said input signal, said inverter transistor forming an i inverting amplifier with said resistances, said amplifier having a gain which is approximately given by -R2/R1. 5. The inverter circuit of claim 4, wherein said second current source i2 is connected to the junction (102) between said input signal source and R2 such that said junction can swing as low as i2 x R2 volts below the control input of said inverter transistor when said maximum drive current flows through said output drive transistor. 6. The inverter circuit of claim 4, wherein said second current source i2 is connected to the junction between said first resistance Rl and said second resistance R2 such that the voltage of said junction can swing as low as the control input of said inverter transistor when said maximum drive current flows through said output drive transistor. 7. The inverter of claim 1, wherein said first current source il is arranged to produce a current with a negative temperature coefficient to approximately compensate for an increase in beta with temperature of a transistor connected to receive said output drive current P -c2 • 8. The inverter of claim 1, wherein said current source i2 produces a current that is proportional-to- absolute temperature (PTAT) such that the ratio of i c2 (max.) to il is temperature invariant. 9. A series pass voltage regulator which includes circuitry that accommodates anticipated manufacturing variations in pass transistor beta values, said regulator comprising: a bipolar pass transistor (Q3) arranged to produce an output voltage at a desired maximum regulator output current, said pass transistor having a particular beta characteristic, an error amplifier (108) connected to receive a voltage proportional to said output voltage at a first terminal and a reference voltage at a second terminal, and producing an error voltage at an output, a follower device (106) connected to said amplifier's output, an inverter circuit (110) arranged to establish a maximum drive current through an output drive transistor (Q2) connected to control said pass transistor, said inverter circuit comprising: an inverter transistor Ql having a control input and first and second current terminals, a first resistance Rl connected to feed back the voltage at Ql's first current terminal to Ql's control input, a first current source il connected to Ql's first current terminal and biasing Ql to invert an input signal produced by said follower device and presented at Ql's control input, said inverted input signal appearing at Ql's first current terminal, il comprising: a first bipolar transistor (Q19) having a beta characteristic which is about equal to that of said pass transistor and biased with a current i out that is proportional to said desired maximum regulator output current, means (Q20) connected to supply the current to said first transistor' s base needed to operate said first transistor at i out , said current supplied to said first transistor's base thereby dependent on the beta of said first transistor, said beta-dependent current conveyed by said means to Ql's first current terminal as the output of current source il, an output drive transistor (Q2) having a control input and a current circuit, connected to receive said inverted input signal at its control input and producing said drive current i c2 in its current circuit in response to said inverted input signal, a second current source i2 connected to bias said follower device and enabling the voltage at Ql ' s control input to be pulled lower than the voltage at Ql's first current terminal in response to said input signal and thereby increasing the voltage attainable at Ql's first current terminal, the values of il, i2, and Rl establishing the maximum drive current i c2 (max.) which can flow in said output drive transistor' s current circuit independent of the respective gain characteristics of said inverter and output drive transistors, thereby limiting the drive current delivered to said pass transistor, and current source il's beta-dependent output reducing variations in maximum regulator output current due to manufacturing variations in the beta of said pass transistor. 10. A method of limiting the drive current which is produced by an inverter circuit and which drives a following stage, comprising the steps of: connecting a resistance R (Rl) between a first current circuit terminal and a control input of a first transistor (Ql) , biasing said first transistor with a current il to invert an input signal received at its control input and to produce said inverted signal at said first current circuit terminal as an output, modulating a second transistor (Q2) with the output from said first current terminal to produce a drive current suitable for controlling a following stage, and supplying a current i2 through said resistance R when said input signal is at a negative limit, said current increasing the voltage of said modulating signal to said second transistor by an amount equal to i2 x R and thereby establishing a maximum drive current based on the values of il, i2 and R.

Inventors: BROKAW A PAUL, BROKAW, A., PAUL
Applicants: ANALOG DEVICES INC, ANALOG DEVICES, INC.
Application year: 1998
Main classification: G05F1
IPC codes: G05F1