Method of test sequence generation

Abstract: Flip-flops (FFs) to replace with scan FFs are selected for an integrated circuit designed at the gate level in order that the integrated circuit has an n-fold line-up structure. All FFs in an integrated circuit are temporarily selected as FFs to replace with scan FFs. Each FF to replace with a scan FF is temporarily selected as a FF to replace with a non-scan flip-flop. and the structure of the integrated circuit is checked if it has an-fold line-up structure, and if so, then the FF is selected as a FF to replace with a non-scan flip-flop. For an integrated circuit designed at the gate level, flip-flops to replace with scan flip-flops are selected in order that the integrated circuit has an n-fold line-up structure, without recognizing load/hold FFs as self-loop structure FF. Thereafter, FFs to replace with scan FFs are selected in such a way as to facilitate testing on load/hold FFs. For example, timeframe expansion on the basis of the state justification of load/hold FFs is carried out. From such timeframe expansion, FFs to replace with scan FFs are selected. This guarantees high fault efficiency in identifying FFs to replace with scan FFs. In generating test sequences for the post-fabrication testing of ICs, a buffer length for a buffer storing a test sequence is set and a test sequence for an integrated circuit is generated while sequentially compaction storing test sequences for respective faults in buffers with the set buffer length. This achieves a higher compaction rate than conventional technology.

Description: BACKGROUND OF THE INVENTION The present invention relates to design for testability and test sequence generation for integrated circuits (LSIs). Scan design is a conventionally used design as a typical design for testability technology. In a scan design method, flip-flops (FFs) in a logic-designed integrated circuit are replaced by scan FFs and hence can be controlled (scan-in) and observed (scan-out) directly from outside and the problem of sequential circuits is simplified into that of combinational circuits, for test sequence generation facilitation. One such technology is described in Digital Systems Testing and Testable Design, Chapter 9, Design For Testability, published in 1990 by Computer Science Press. Scan design may be classified into two types, namely a full scan design method and a partial scan design method. In the former design method, all FFs in a circuit are replaced by scan FFs. On the other hand, in the latter design method, only some FFs in a circuit are replaced by scan FFs. A method of identifying (selecting) scan FFs in the partial scan design is fully discussed in a paper, entitled An Exact Algorithm for Selecting Partial Scan Flip-Flops, DAC (Design Automation Conference), pp.81-86, 1994 as well as in its references. Additionally, as to test sequence generation for sequential circuits, test sequence compaction is fully described in a paper entitled Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Technique, FTCS (Fault Tolerant Computing Symposium), pp. 53-61, 1996 as well as in its references. The above-noted prior art techniques however have their respective problems. A conventional partial scan design method produces the problem that in identification of FFs to replace with scan FFs it is not always possible to guarantee sufficiently high fault efficiency, i.e., 95% or more. Additionally a conventional test sequence compaction method for sequential circuits also produces the problem that it is poor in compaction rate. An automatic test pattern generation system is described in "PLANE: A New ATPG System for PLAs" by Huang J-D et al, Proceedings Asian Test Symposium, Being, China, Nov. 1993, IEEE Comput. Soc., 1993. A crosspoint fault model is adopted for testing programmable logic arrays. A test cube - a test vector in which a bit unassigned by ATPG is denoted as "don't care" - is generated for a crosspoint fault and stored in a buffer of finite length. Test compaction is achieved by combining - if possible - newly generated test cubes with existing test cubes when new test cubes are added to the buffer. It is an object of the present invention to provide an improved test sequence generation method. This is achieved by the features of claim 1. Further embodiments are subject-matter of the dependent claims. FIGURE 1 is a flowchart showing procedures in a method of design for testability according to a first example useful for the understanding of the present invention. FIGURE 2 is an illustration of an integrated circuit (LSI) which becomes an object of the method of design for testability. FIGURES 3(a)-(e) show timeframe expansions when FF r1 of the integrated circuit of FIGURE 2 is selected as a FF to replace with a non-scan FF. FIGURES 4(a)-(d) show timeframe expansions when FF r2 of the integrated circuit of FIGURE 2 is selected as a FF to replace with a non-scan FF. FIGURE 5 shows a timeframe expansion when FF r4 of the integrated circuit of FIGURE 2 is selected as a FF to replace with a non-scan FF. FIGURE 6 is an illustration of a method of design for testability of the first example applied to the integrated circuit of FIGURE 2. FIGURES 7(a) and 7(b) show respectively L/H FFs. FIGURE 8 is a flowchart showing procedures in a method of test sequence generation according to a first embodiment of the invention. FIGURE 9 is a flowchart showing the details of step SG11 of FIGURE 8. FIGURES 10(a) and (b) are diagrams useful in understanding the method of test sequence generation of the first embodiment. FIGURES 11(a) and (b) are diagrams useful in understanding the method of test sequence generation of the first embodiment. FIGURES 12(a) and (b) are diagrams useful in understanding the method of test sequence generation of the first embodiment. FIGURE 13 is a diagram useful in understanding the method of test sequence generation of the first embodiment. FIGURE 14 is a flowchart showing procedures in a method of test sequence generation according to a second embodiment of the invention. FIGURE 15 is a flowchart showing the details of step SH13 of FIGURE 14. FIGURES 16(a) and (b) are diagrams useful in understanding the method of test sequence generation of the second embodiment. FIGURES 17(a) and (b) are diagrams useful in understanding the method of test sequence generation of the second embodiment. FIGURES 18(a) and (b) are diagrams useful in understanding the method of test sequence generation of the second embodiment. FIGURES 19(a) and (b) are diagrams useful in understanding the method of test sequence generation of the second embodiment. FIGURE 1 is a flowchart showing procedures in a method of design for testability according to a first example useful for the understanding of the present invention. In FIGURE 1, in step SA1 as a full scan step, all the flip-flops (FFs) in a target integrated circuit are temporarily selected as FFs to replace with scan FFs. Note that such a FF temporarily selected as FF to replace with scan FF is hereinafter called temporary scan FF. At steps SA2 to SA8, for each temporary scan FF, it is examined whether the target integrated circuit has an n-fold line-up structure or not in assuming each the temporary scan FFs is selected as a FF to replace with a non-scan FF (step SA7), and if such examination shows that the target integrated circuit has an n-fold line-up structure, the temporary scan FF in question is temporarily selected as a FF to replace with a non-scan FF. At step SA9, temporary scan FFs, i.e., FFs temporarily selected as FFs to replace with scan FFs by steps SA1 to SA8 are finally selected as flip-flops to replace with scan FF. An n-fold line-up structure means a circuit structure in which all paths between a flip-flop and an output have n or less sequential depths. A circuit having the n-fold line-up structure circuit has a characteristic that at most n identical FFs exist in timeframe expansion with respect to a primary output. For instance, a 1-fold line-up structure (when n is equal to 1) has a characteristic that the number of identical FFs is one in timeframe expansion with respect to a primary output. In accordance with the present example, the selecting of FFs to replace with scan FFs is made in order that a target integrated circuit has an n-fold line-up structure, wherein an input and an output of a FF to replace with a scan FF are assumed as a pseudo-primary output and as a pseudo-primary input, respectively. SA2 is the step of recognizing a flip-flop having a self-loop structure. When a flip-flop selected at step SA4 is recognized as a FF having a self-loop structure at step SA2, the procedure returns to step SA3 (step SA5). In other words, step SA7 is omitted for the FF having a self-loop structure, leaving the FF remained as temporary scan FF. The method of deign for testability of this example will be described with reference to FIGURES 2-6. Here, n is 1 in the n-fold line-up structure, and in step SA7 it is examined whether a target integrated circuit has a 1-fold line-up structure. FIGURE 2 represents a target integrated circuit (a sequential circuit) for the method of design for testability of this example. A-E are combinational circuits. r1-r4 are flip-flops (FFs). P11 and P12 are primary inputs. PO1 and PO2 are primary outputs. Interconnections among elements are represented by arrows. All of the clocks of FF rl-FF r4 are coupled to the same clock input, the description of which is omitted in FIGURE 2. With respect to a temporary scan FF, its data input and output are assumed as a pseudo-primary output and as a pseudo-primary input, respectively. PPOi and PPI1 represent, respectively, a pseudo-primary output and a pseudo-primary input, the character 1. being indicative of a corresponding FF. For example, when FF r1 is a temporary scan FF, its data input and output are assumed as a pseudo-primary output PPO1 and as a pseudo-primary input PPI1, respectively. At step SA1, all flip-flops in FIG. 2, i.e., FF r1-r4, are selected as temporary scan FFs. At step SA2, the circuit structure of FIG. 2 is analyzed and the result shows that FF r3 is the only FF that has a self-loop structure. Hereinafter, steps SA4-SA8 are performed on each of FF r1-r4. At step SA4, FF r1 is selected. Since FF r1 does not have a self-loop structure, at step SA6 FF r1 is temporarily selected as a FF to replace with a non-scan FF, and at step SA7 the circuit is examined whether to have a 1-fold line-up structure. FIGURE 3 shows a timeframe expansion when FF r1 is temporarily selected as a FF to replace with a non-scan FF. At step SA7c, timeframe expansion is performed with respect to the primary output PO1 selected at step SA7b (FIGURE 3(a)). Since there exists no FF in the expanded timeframe, the procedure returns to step SA7a from step SA7d. Then the primary output PO2 is selected and timeframe expansion is performed (FIGURE 3(b)). Since there exists no FF in the expanded timeframe, the procedure again returns to step SA7a. Then the pseudo-primary output PPO2 (i.e., the data input of FF r2 as a temporary scan FF). is selected, and timeframe expansion is performed (FIGURE 3(o)). Since there exists only one FF r1 in the expanded timeframe, the procedure again returns to step SA7a. Then the primary output PPO3 (i.e., the data input of FF r3 as a temporary scan FF) is selected and timeframe expansion is performed (FIGURE 3(d)). Since there exists only one FF r1 in the expanded timeframe, the procedure again returns to step SA7a. Then the pseudo-primary output PPO4 (i.e., the data input of FF r4 as a temporary scan FF) is selected, and timeframe expansion is performed (FIGURE 3(e)). Since there exists no FF in the expanded timeframe, the procedure again returns to step SA7a. Timeframe expansion processing is now completed with respect to all the primary outputs and all the pseudo-primary outputs. The procedure therefore returns to step SA3. At step SA4, a next FF is selected. At step SA4, FF r2 is selected. Since FF r2 does not have a self-loop structure, at step SA6 FF r2 is temporarily selected as a FF to replace with a non-scan FF. Step SA7 examines whether the circuit has a 1-fold line-up structure. FIGURE 4 shows a timeframe expansion when FF r2 is temporarily selected as a FF to replace with a non-scan FF. At step SA7c, timeframe expansion is performed with respect to the primary output PO1 selected at step SA7b (FIGURE 4(a)). Since there exists only one FF r1 and one FF r2 in the expanded timeframe, the procedure returns to step SA7a from step SA7d. Then, the primary output PO2 is selected, and timeframe expansion is performed (FIGURE 4(b)). Since there exists no FF in the expanded timeframe, the procedure again returns to step SA7a. Then, the pseudo-primary output PPO3 is selected, and timeframe expansion is performed (FIGURE 4(o)). Since there exists only one FF r1 in the expanded timeframe, the procedure again returns to step SA7a. Then, the pseudo-primary output PPO4 is selected, and timeframe expansion is performed (FIGURE, 4(d)). Since there exist only one FF r1 and only one, FF r2 in the expanded timeframe, the procedure again returns to step SA7a. Timeframe expansion processing is now completed with respect to all the primary outputs and all the pseudo-primary outputs. The procedure therefore returns to step SA3. At step SA4, a next FF is selected. At step SA4, FF r3 is selected. However, since FF r3 was already recognized as a FF having a self-loop structure, the procedure returns to step SA3 from step SA5. At step SA4, a next FF is selected. At step SA4, FF r4 is selected. FF r4 does not have a self-loop structure. Accordingly, at step SA6 FF r4 is temporarily selected as a FF to replace with a non-scan FF. Step SA7 examines whether the circuit has a 1-fold line-up structure. FIGURE 5 shows a timeframe expansion when FF r4 is temporarily selected as a FF to replace with a non-scan FF. At step SA7c, timeframe expansion is performed with respect to the output terminal PO1 selected at step SA7b. There exist two FFs r1 and two FFs r2 in the expanded timeframe, which means that the circuit does not have a 1-fold line-up structure. The procedure moves to step SA8 from step SA7d, and FF r4 is selected as a temporary scan FF. Steps SA4-SA8 has been performed for all the FF r1-r4. The temporary scan FFs. i.e., FF r3 and FF r4, are finally selected as flip-flops to replace with FFs at step SA9, and the procedure is finished. FIGURE 6 shows a result of the method of design for testability of the present example for the integrated circuit of FIG. 2. In FIGURE 6, FF r3 and r4 which are finally selected as flip-flops to replace with, are really replaced with scan FFs. SI represents a scan-in primary input. SO represents a scan-out primary output. SE represents a scan enable primary input. A scan path is constructed such that it extends from the scan-in primary input SI to the scan-out primary output SO by way of a scan input DT and a scan output Q of the scan FF r4 and a scan input DT and a scan output Q of the scan FF r3. In accordance with the present method of design for testability, FFs to replace with scan FFs are determined in order that a sequential circuit has an n-fold line-up structure, hence, high fault efficiency can be guaranteed at scan FF identification. The described algorithm can be applied easily to methods of design for testability for an integrated circuit designed at register transfer level (RTL). At first, full scan step is performed in which all registers in an RTL-designed integrated circuit are temporarily selected as registers to replace with scan registers. Then, non-scan register selection step is performed in which, for each temporary scan register selected by the full scan step, it is examined whether the RTL-designed integrated circuit has an n-fold line-up structure or not in assuming each the temporary scan register is selected as a register to replace with a non-scan register, and if such examination shows that the RTL-designed integrated circuits has an n-fold line-up structure, each the temporary scan registers in question is temporarily selected as a register to replace with a non-scan register. And, the registers temporarily selected as registers to replace with scan registers by the full scan step and the non-scan register selecting step are finally selected as registers to replace with scan registers. FIGURE 8 is a flowchart showing procedures in a method of test sequence generation according to a first embodiment of the present invention. In accordance with the present method of test sequence generation, test sequence is generated for a given circuit while sequentially compaction storing test sequences generated for respective faults in buffers. In FIGURE 8, SG1 is the step of examining the given circuit for a loop. In the presence of a loop, the procedure moves to step SG2, while in the absence of a loop, the procedure moves to step SG3. SG2 is the step of setting a predetermined value as buffer length, providing a single buffer having such a buffer length, and initializing all data thereof to "don't care". SG3 is a step of setting a value obtained by addition of 1 to the sequential depth of the circuit as buffer length, providing a single buffer having such a buffer length, and initializing all data thereof to "don't care". After setting of the buffer lengths at steps SG2 or SG3, the maximum number of buffers is designated at step SG4. SG5 is the step of determining whether test sequence has been generated (ATPG) for every fault. If YES, the procedure advances to step SG6, while if NO, the procedure advances to step SG7. At step SG6, a fault simulation is performed using all the test sequences stored in a group of buffers. SG7 is the step of selecting a single fault as a target fault for which no test sequences have been generated. SG8 is the step of generating a test sequence for the target fault selected at step SG7. SG9 is the step of determining whether the test sequence generated at step SG8 has a greater length than buffer length set at step SG2 or SG3. If YES, the procedure moves to step SG10, while if NO, the procedure moves to step SG11. Note that in the absence of a loop in the circuit the test sequence length does not exceed the buffer length, which is set to the sequential depth plus 1 at step SG3. At step SG10, a fault simulation is performed using the generated test sequence. At step SG11, the generated test sequence is compaction stored in the buffer. The details of step SG11 are described later. SG12 is the step of determining whether the number of buffers is greater than the maximum number of buffers designated at step SG4 at compaction storage at step SG11. If YES, the procedure moves to step SG13, while if NO, the procedure returns to step SG5. At step SG13, a fault simulation is preformed using a test sequence held in a buffer with the minimum number of "don't care"s and this buffer is deleted. FIGURE 9 is a flowchart showing the details of step SG11 of FIGURE 8. SG11a is the step of determining whether compaction storage of the test sequence generated at step SG8 has been tried to every buffer. If compaction storage has been tried to every buffer, the procedure advances to step SG11, while if not, the procedure moves to step SG11b. SG11b is the step of selecting one buffer to which compaction storage has not been tried. SGllc is the step of determining whether compaction storage has been tried on every start position, for the buffer selected at step SG11b. If YES, the procedure returns to step SG11a, while if not, the procedure advances to step SG11d. SG11d is the step of selecting a start position to which compaction storage is tried. It is possible to select (BL - TPL + 1) start positions per buffer, where BL is the buffer length and TPL the test sequence length. SG11e is the step of determining whether compaction storage in the buffer selected at step SG11b is successful from the start position selected at step SG11d. Step SG11e determines whether the test sequence can be compaction stored based on the compaction rule, where the test sequence's "0" is compactible with "0" or "don't care" but incompactible with "1" in-buffer, and the test sequence's "1" is compactible with "1" or "don't care" but incompactible with logical "0" in-buffer. When step SG11e determines that the test sequence can be compaction stored, the test sequence is compaction stored in the buffer based on the foregoing compaction rules at step SG11f. When the test sequence cannot be compaction stored in any buffer, at step SGllg a new buffer in which to store the test sequence is additionally provided. SG11h is the step of sorting the buffers in order of the number of 'don't care"s. The method of test sequence generation of FIGURE 8 and FIGURE 9 will be described by reference to FIGURES 10-13. Here, suppose that a target circuit has no loops and has a sequential depth of 3, and has four faults, i.e., FAULT-a, FAULT-b, FAULT-c, and FAULT-d, as undetected faults. In FIGURES 50-53, X1-X3 are primary inputs. A and B are buffers. In buffers, 0 represents logic value "0". 1 represents logic value "1". X represents "don't care". Since the target circuit has no loop, at step SG3, a value of 3 obtained by addition of 1 to the sequential depth is set as buffer length. As shown in FIGURE 10(a), buffer A whose buffer length is 3 is generated and all data of buffer A are initialized to "don't care". At step SG4, a value of 2 is designated as the maximum number of buffers. Next, at step SG8, a test sequence is generated for FAULT-a selected at step SG7. At step SG11, the test sequence generated for FAULT-a is compaction stored in the buffer A. Such compaction storage is successful based on the foregoing compaction rules. Because 0 is the only possible start position since the buffer length is equal to the length of test sequence for FAULT-a and, in addition, all the data of the buffer A have been initialized to "don't care". As a result, as shown in FIGURE 10(b), the test sequence for FAULT-a is compaction stored in the buffer A. Subsequently, at step SG8, a test sequence is generated for FAULT-b selected at step SG7. The buffer length is equal to the length of the test sequence for FAULT-b and 0 is therefore the only possible start position. As shown in FIGURE 11(a), compaction storage based on the foregoing compaction rules is unsuccessful. A new buffer B in which to store the test sequence is additionally provided, as shown in FIGURE 11(b). The number of "don't care"s in the buffer A is four and the number of "don't care"s in the buffer B is five. Accordingly, the buffers A, B are sorted in the order of B, A. Subsequently, at step SG8, a test sequence is generated for FAULT-c selected at step SG7. The test sequence generated for FAULT-c has a length of 2, and 0 and 1 are therefore the only possible start positions. As shown in FIGURE 12(a), based on the foregoing compaction rules, compaction storage of the test sequence is tried to both the buffers A and B. In the buffer B, compaction storage is unsuccessful, not only when the start position is 0 but also when the start position is 1. In the buffer A, compaction storage is unsuccessful when the start position is 0 but successful when the start position is 1. As a result, the test sequence generated for FAULT-c is compact stored in the buffer A with the start position at 1 (see FIGURE 52(b)). The number of "don't care"s in the buffer A is one and the number of "don't care"s in the buffer B is five. Accordingly, the buffer B, A are sorted in the order of B, A. Subsequently, at step SG8, a test sequence is generated for FAULT-d selected at step SG7. The length of the test sequence generated for FAULT-d is equal to the buffer length and 0 is therefore the only possible start position. Based on the foregoing compaction rules, compaction storage of the test sequence is tried to both the buffers A and B. Compaction storage is unsuccessful in both the buffers A and B. A new buffer C in which to store the test sequence is additionally provided. The number of "don't care"s in buffer A is one, and the number of "don't care"s in buffer B is five, and the number of "don't care"s in buffer C is three. Accordingly, the buffers A, B, C are sorted in the order of B, C, A. Since the number of buffers exceeds 2 that is the maximum number of buffers (step SG12), each "don't care" is randomly replaced with either "0" or "1" in a buffer with the minimum number of "don't care"s of the buffers A, B, and C, i.e., the buffer A, to execute a fault simulation. The buffer A is then deleted and the buffer C, in which the test sequence for FAULT-d is stored, serves now as a new buffer A (step SG13). Since test sequences are generated for all undetected faults (step SG5), each "don't care" is randomly replaced with either "0" or "1" in the buffers A and B, to execute a fault simulation (step SG6). In accordance with the present embodiment, compaction is performed dynamically with buffers in test sequence generation. This achieves generation of shorter test sequences. FIGURE 14 is a flowchart showing procedures in a method of test sequence generation according to a second embodiment of the present invention. In accordance with the present method of test sequence generation, test sequence is generated for a given circuit while sequentially compaction storing test sequences generated for respective faults in buffers. The present embodiment is different in algorithm for compaction storage of test sequences in buffer from the first embodiment. In FIGURE 14, SH1 is the step of examining the given circuit for a loop. In the presence of a loop, the procedure moves to step SH2, while in the absence of a loop, the procedure moves to step SH3. SH2 is the step of setting a predetermined value L as buffer length, and providing N buffers having such a buffer length L, wherein the number N is a positive integer, and initializing all data thereof to "don't care". SH3 is the step of setting a value obtained by addition of 1 to the sequential depth of the circuit as buffer length, and providing N buffers having such a buffer length, and initializing all data thereof to "don't care". SH4 is the step of determining whether the "don't care" ratio in the N buffers exceeds a predetermined upper limit P. If the "don't care" ratio exceeds the upper limit P, at step SH5, each "don't care" is replaced with either "0" or "1" in the N bummers to execute a fault simulation. At step SH6, all the data of the buffers are initialized to "don't care". While, if the "don't care" ratio does not exceed the upper limit P, the procedure moves to step SH7. SH7 is the step of determining whether test sequences have been generated for all the faults. If YES, at step SH8, each "don't care" is replaced with either "0" or "1" to execute a fault simulation. SH9 is the step of selecting a single fault as a target fault for which no test sequences have been generated. SH10 is the step of generating a test sequence for the target fault selected at step SH9. SH11 is the step of determining whether the test sequence generated at step SH10 has a greater length than the buffer length set at step SH2 or SH3. If YES, the procedure moves to step SH12, while if NO, the procedure moves to step SH13. Note that in the absence of a loop in the circuit the test sequence length does not exceed the buffer length, which is set to the sequential depth plus 1 at step SH3. At step SH12, a fault simulation is performed with the generated test sequence. In step SH13, the generated test sequence is compaction stored in the N buffers. The details of step SH13 are described later. Step SH14 determines whether such compaction storage is performed successfully. If YES, the procedure returns to step SH4, while if NO, a fault simulation is executed using this the test sequence at step SH12 before returning to step SH4. FIGURE 15 a flowchart showing the details of step SH13 of FIGURE 14. In FIGURE 15, SH13a is the step of initializing a start position, i, to 0. SH13b-SH13e are the steps of determining whether the test sequence can be compaction stored in the N buffers, while incrementing the start position i. If YES, the test sequence is compaction stored in the N buffers, while if NO, processing is finished. The method of test sequence generation of FIGURE 14 and FIGURE 15 will be described by reference to FIGURES 16-19. Here, suppose that a target circuit has no loops and has a sequential depth of 2. The number of buffers N is two. The upper limit P of the "don't care" ratio is 60%. The target circuit has four faults, i.e., FAULT-a, FAULT-b, FAULT-c, and FAULT-d as undetected faults. In FIGURES 16-19, X1-X3 are primary inputs. In buffers, 0 represents logic value "0". 1 represents logic value "1". X represents "don't care". Also, a set of N buffers is regarded as a single buffer in this embodiment. Since the target circuit has no loops at SH3, a value of 3 obtained by addition of 1 to the sequential depth is set as buffer length. As shown in FIGURE 16(a), two buffers whose a buffer length is 3 are generated. These two buffers being regarded as a single buffer whose buffer length is 6, all data stored therein are initialized to "don't care". At step SH4, whether the "don't care" ratio exceeds the upper limit P is determined. Here, the "don't care" ratio is 0% and the procedure advances to step SH7. Next, a test sequence is generated at step SH10 for FAULT-a selected at step SH9. At step SH13, the test sequence thus generated is compaction stored in the buffer. As shown in FIGURE 16(a), such compaction storage is successful when the start position is 0. Therefore, the generated test sequence is compaction stored as shown in FIGURE 16(b). The "don't care" ratio is 5/18 which is smaller than the upper limit P (= 60%). Next, a test sequence is generated at step SH10 for FAULT-b selected at step SH9. At step SH13, the test sequence thus generated is compaction stored in the buffer. As shown in FIGURE 17(a), such compaction storage is successful when the start position is 1. Therefore, the generated test sequence is compaction stored as shown in FIGURE 18(b). The "don't care" ratio is 8/18 which is smaller than the upper limit P (= 60%). Next, a test sequence is generated at step SH10 for FAULT-c selected at step SH9. At step SH13, the test sequence thus generated is compaction stored in the buffer. As shown in FIGURE 18(a), such compaction storage is successful when the start position is 4. Therefore, the generated test sequence is compaction stored as shown in FIGURE 18(b). The "don't care" ratio is 12/18 which is greater than the upper limit P (= 60%). A fault simulation is accordingly performed at step SH5, and all the buffer data are initialized to "don't care" at step SH6. Subsequently to the above, a test sequence is generated at step SH10 for FAULT-d selected at step SH9. At step SH13, the test sequence thus generated is compaction stored in the buffer. As shown in FIGURE 19(a), such compaction storage is successful when the start position is 0. Therefore, the generated test sequence is stored as shown in FIGURE 19(b). The "don't care" ratio is 6/18 which is smaller than the upper limit P (= 60%). In accordance with the present embodiment, it is determined whether further compaction storage can be performed successfully according to "don't care" ratio in buffer. This achieves dynamic test sequence compaction with high efficiency. In addition, it becomes possible to perform compaction storage over a plurality of buffers by regarding a plurality of buffers as a single buffer, therefore compaction rates increases.

Claims: A method of test sequence generation for an integrated circuit, comprising: a buffer length set step (SG1-SG4, SH1-SH3) of setting a buffer length for a buffer for storing a test sequence; and a test sequence compaction step (SG5-SG13, SH4-SH14) of generating a test sequence for said integrated circuit, in performing compaction storage (SG11, SH12) of test sequences for respective faults sequentially in buffers having said buffer length set in said buffer length set step (SG1-SG4, SH1-SH3), characterized in that said buffer length set step (SG1-SG4, SH1-SH3) including the steps of examining (SG1, SH1) said integrated circuit for a loop, and setting (SG2, SH2) a predetermined value as the buffer length in the presence of a loop and setting (SG3, SH3) a value, obtained by addition of 1 to the sequential depth of said integrated circuit, as the buffer length in the absence of a loop. The method of test sequence generation of claim 1, wherein said buffer length set step (SG1-SG4) is the step of providing a single buffer having said buffer length, and said test sequence compaction step (SG5-SG13) includes; a first step of generating (SG7) a test sequence for a fault; a second step of performing (SG11) compaction storage of the test sequence generated at said first step (SG7) in said already provided buffer if such compaction storage is carried out successfully and, if not, providing (SG11g) a new buffer having said buffer length and storing said test sequence in said new buffer; and a third step of executing (SG13) a fault simulation by using a test sequence stored in a buffer with the minimum number of "don't care"s when the number of buffers exceeds a given limit at said second step (SG11) and deleting said buffer, wherein said first to third steps (SG7, SG11, SG13) are iterated for respective faults. The method of test sequence generation of claim 1, wherein said buffer length set step (SH1-SH3) is the step of providing a given number of buffers having said buffer length; and said test sequence compaction step (SH4-SH14) includes: a first step of generating (SH10) a test sequence for a fault; a second step of performing (SH13) compaction storage of the test sequence generated in said first step (SH10) in said given number of buffers if such compaction storage is carried out successfully and, if not, executing (SH12) a fault simulation using said test sequence; and a third step of executing (SH5) a fault simulation by using the test sequence stored in said given number of buffers when the "don't care" ratio in said given number of buffers exceeds a given limit at said second step (SH13) and initializing (SH6) all data in said given number of buffers to "don't care", wherein said first to third steps (SH10, SH13, SH5, SH6) are iterated for respective faults.

Inventors: HOSOKAWA TOSHINORI, OHTA MITSUYASU, HOSOKAWA, TOSHINORI, OHTA, MITSUYASU
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1998
Main classification: G01R31
IPC codes: G01R31