IMAGE PICK-UP METHOD AND APPARATUS USING THE IMAGE PICK-UP METHOD

Abstract: An image pick-up apparatus is provided which can achieve a decrease in cost and in circuit size and a decrease in dissipation power. In a recording mode, YUV data of one frame output at a given period from a YUV signal processing circuit (11) is periodically written to a DRAM (14) through a DRAM transfer route via a DMA controller (12). The writting-in of YUV data of one frame is done by a predetermined map. The DMA controller (12) allows YUV data which is periodically developed onto the DRAM (14) to be read out/output from the YUV signal processing circuit (11) to a video encoder (15) in a way to correspond to the image map. Thus, in accordance with the periodic updating, on the DRAM (14), of image information picked up by a CCD (6), the video encoder (15) creates a video signal on the basis of automatically updated information and a current image can be displayed on a display device (16) without using a VRAM controller and VRAM.

Description: D E S C R I P T I O N IMAGE PICK-UP METHOD AND APPARATUS USING THE IMAGE PICK-UP METHOD Technical Field The entire contents of Japanese Patent Application No. 9-118764 filed on April 22, 1997 are incorporated herein by reference. Background Art The present invention relates to an image pick-up apparatus, image pick-up method and display method, for picking up an image of an object and effecting display and recording based on image data. The structure and operation of a conventional image pick-up apparatus are so constructed as to enable a selection of a recording mode for picking up and recording the image of an object and a reproducing mode for reproducing and displaying image picked-up data already recorded. And in the recording mode, image data picked up from a CCD (charge coupled device) is handled in the following sequence . First, the CCD generates a photoelectric conversion output as one corresponding image for a predetermined cycle. This output is sampled/held by a sampling/holding circuit and converted by an A/D converter to digital data. The digital signal is converted by a YUV signal processing circuit to a multiplexed signal (signal containing at least a luminance signal and color difference, hereinafter referred to YUV data) containing a digital luminance and color difference and it is output to a DMA (Direct Memory Access) controller. The DMA controller allows the YUV data which is input to be written to its interior buffer and the data to be DMA-transferred to a DRAM (Dynamic Random Access Memory) via a DRAM I/F (Dynamic Random Access Memory Interface) . After the YUV data has been DMA-transferred to the DRAM, a CPU enables the YUV data to be read out from the DRAM via the DRAM I/F and the data to be written to a VRAM (Video Random Access Memory) via a VRAM controller. Then a digital video encoder (hereinafter referred to simply as a video encoder = VE) periodically reads out the YUV data from the VRAM via the VRAM controller and, from the data, a video signal is generated and output to a display device. By doing so, a display device displays an image based on image information currently obtained from the CCD. With a current image displayed on the display device, a shutter key is operated in a timing for the user to record/preserve it, generating a trigger. After the YUV data of one image currently obtained from the CCD in accordance with the trigger has been DMA-transferred to the DRAM, CPU (Central Processing Unit) stops a path from the CCD to the DRAM, effecting a shift to a recording/reserving state. In this recording/preserving state, the CPU enables YUV data of one frame written to the DRAM to be read out via the DRAM I/F and the data to be written to the compandor circuit. And the CPU enables the code data which is compressed in the compandor circuit to be read from the compandor circuit and the data to be written to a flash memory comprised of a nonvolatile memory. With the YUV data of one frame compress-processed and full compressed data written to the flash memory, the CPU enables the restarting of data transfer from the CCD to the DRAM. In the state of the reproducing mode, the image data stored in the flash memory is displayed on the display device in the following sequence. When the image pick-up apparatus is switched from the recording mode to the reproducing mode, the CPU stops the path from the CCD to the DRAM and enables the code data of a specific one frame to be read out from the flash memory in accordance with the depression of an image select key, etc., by the user and the data to be written to the compandor circuit. And the CPU enables expand-processing to be effected by the compandor circuit and the YUV data of one frame to be developed into the VRAM through the VRAM controller. Then a video encoder creates a video signal from the YUV data of one frame developed into the VRAM and it is displayed on the display device. In such a conventional digital camera, however, the YUV data of one frame is developed into the DRAM at the recording and reproducing modes as set out above and, at each completion of the development of the YUV data into the DRAM, the YUV data is transferred from the DRAM to the VRAM by the video encoder and it is displayed. That is, since the display of the image is effected while using the DRAM as a memory for operation and the VRAM as a memory for display, these separate memories, for operation and for display, exist, thus leading to an increase in cost and a larger increase in the size of a circuit. Further, if both the memories exist separately, at each updating of the image information obtained from the CCD in the recording mode and at each expansion of the compressed YUV data in the reproducing mode the YUV data developed into the DRAM has to be transferred to the VRAM, so that there unavoidably occurs a dissipation power loss. Disclosure of Invention It is accordingly the object of the present invention to provide an image pick-up apparatus and image pick-up method which can achieve a decrease in cost and a small-sized circuit and a decrease in dissipation power. A preferred aspect of the present invention comprises : image pick-up means for picking up an image of an object and for generating a corresponding signal; generating means for generating image data of the object image based on the signal generated from the image pickup means; recording means for recording, in response to a picking-up operation, the image data generated from the generating means ; display control means for displaying the object image based on the image data generated from the generating means and for displaying, in response to a reproducing operation, an image based on the image data stored in the recording means; memory means for operation; and transfer means for transferring the image data from the generation means and recording means, in predetermined format, to the memory means while transferring the image data, in the predetermined format, from the memory means to the display control means . By doing so, it is possible to achieve a decrease in cost and in circuit size and, in addition, it is also not necessary to effect data transfer to a VRAM, so that a loss in dissipation power can be avoided. Further, an image stored in the preservation memory can be displayed on the display screen of the display device . Another preferred aspect of the present invention comprises : image pick-up means for picking up an image of an object and for generating image data corresponding to the object; a temporary storing memory for temporarily storing the image data from the image pick- up means ; display means for displaying the image data of the temporary storing memory; and transfer means for transferring the image data of the image pick-up means to the temporary storing memory and display means . Thus, it is possible to achieve a decrease in cost and in circuit size and, in addition, it is also not necessary to effect data transfer to a VRAM, so that a loss in dissipation power can be avoided. Further, since the data transfer is not via control means, there arises less load on the control means. Another preferred aspect of the present invention comprises : an image pick-up element for picking up image data; a temporary storing memory for temporarily storing the image data from the image pick-up element; a compressing circuit for compressing the image data stored in the temporary storing memory; a preservation memory for preserving the image data compressed by the compressing circuit; display means for displaying the image data stored in the temporary storing memory; and transferring means for transferring the image data in the temporary storing memory to the compressing circuit and display means . Thus , an image stored in the preservation memory can be displayed on the display screen of the display device without using a VRAM controller and VRAM in the conventional apparatus. Further, since it is possible to reduce the data transfer via the control means, so that there arises less load on the control means . Another preferred aspect of the present invention comprises : a preservation memory for preserving compressed image data; an expanding circuit for expanding the compressed image data of the preservation memory; a temporary storing memory for storing the image data expanded by the expanding circuit; display means for displaying data encoded by the video encoder; and transfer means for transferring the image data which is expanded by the expanding circuit to the temporary storing memory and display means . Thus, the image stored in the preservation memory can be displayed on the display screen of the display device without using the VRAM controller and VRAM in the conventional apparatus. Further, it is possible to reduce the data transfer via the control means, so that less load is exerted on the load. Another preferred aspect of the present invention comprises : picking up image data by an image pick-up element (SI); storing the image data from the image pick-up element in the temporary storing means (S2); and reading out the image data of the temporary storing memory while overlapping with the step, and sending the image data to display means (S3, S4). Thus it is possible to achieve a decrease in cost and in circuit size and, in addition, it is also not necessary to effect data transfer to the VRAM, so that a loss in dissipation power can be avoided. Since the data transfer is not via the control means, less load is exerted on the control means . Another preferred aspect of the present invention comprises : picking up the image data by an image pick- up element (SI); storing the image data from the image pick-up element in a temporary storing memory (S2); compressing, by a compandor circuit, the image data stored in the temporary storing memory (S5); storing the image data which is compressed by the compandor circuit in a preservation memory (S6); and displaying, by displaying means , the image data which is stored in the temporary storing memory (S8) while overlapping with the step (S5) . Thus , the image stored in the preservation memory can be displayed on the display screen of the display device without using the VRAM controller and VRAM in the conventional apparatus. Further, it is possible to reduce the data transfer via the control means, so that less load is exerted on the control means . Still another preferred aspect of the present invention comprises: sending compressed image data from a preservation memory to the expander circuit (S9); and sending the image data which is expanded by the expander circuit to a temporary preservation memory and sending the image data which is stored in the temporary preservation memory to display means (S10-S12). Thus , the image stored in the preservation memory can be displayed on the display screen of the display device without using the VRAM controller and VRAM in the conventional apparatus. Further, since the data transfer via the control means can be reduced, less load is exerted on the control means. Brief Description of Drawings FIG. 1A is a perspective view showing an outer appearance of a digital camera according to one aspect of the present invention; FIG. IB is a perspective view showing the digital camera as viewed in a different direction; FIG. 2 is a schematic block diagram of the digital camera; FIG. 3 is a schematic block diagram showing a detail of a DMA controller and a state of connection to any other blocks ; FIG. 4 is a view showing an image map of YUV data corresponding to one frame; FIGS. 5A to 5D, each, show a relation between YUV data writing lines of a YUV signal processing circuit and YUV data reading lines of a video encoder; FIG. 6 is a view showing a relation between YUV data writing lines of a YUV signal processing circuit and YUV data reading lines of a video encoder in a second aspect of the present invention; FIG. 7A is a view showing a moving path of data in a recording mode; FIG. 7B is a view showing a moving path of data at a time of taking an image in a recording mode; and FIG. 7C is a view showing a moving path of data in a reproducing mode. Best Mode of Carrying Out the Invention One embodiment of the present invention will be explained below with reference to the drawing. FIGS. 1A and IB are external views showing a digital camera according to an aspect of the present embodiment. As shown in these Figures, the digital camera has a body 1 of a rectangular parallelepiped configuration with a display screen 2 on the back surface of the body 1, a lens 3 on a. front corner portion and a shutter key 4 on an upper face, any other keys, such as an image select key, being arranged. FIG. 2 is a block diagram of a digital camera according to the aspect of the present embodiment. A CCD 6 is arranged behind the lens 3 and driven by a timing generator 7 and vertical driver 8 to produce a photoelectric conversion output as one corresponding image at each given frequency. The photoelectric conversion output is subjected to sample/hold-processing by a sample/hold circuit 9 and it is converted by an A/D converter 10 to digital data. And a multiplexed signal (signal containing at least a luminance signal and color difference signal, herein- after referred to as a YUV data) containing a digital luminance and color difference is output by a YUV signal processing circuit 11 to a DMA (Direct Memory Access) controller 12. To the DMA controller 12 connected are a compandor circuit 13, DRAM (Dynamic Random Access Memory) 14 and video encoder 15. To the video encoder 15 is connected a display device 16 having the display image screen 2. To the DMA controller 12 are connected, via a bus line, a CPU 17 and flash memory 18. Operation information is input to the CPU 17 from a key section 19 comprising the shutter key 4 and other keys 5. FIG. 3 is a block diagram showing the DMA controller 12 and a state of connection between the DMA controller 12 and other blocks. The YUV data output of the YUV signal processing circuit 11 is written into a first FIFO (First in First Out) 20 and, by a DMA controller circuit 21, DMA-transferred to the DRAM 14 through a DRAM I/F 22. Further, through a DMA transfer from the DRAM 14 via a DRAM I/F 22 to a video encoder 15, the DMA control circuit 21 allows the YUV data to be written into a second FIFO 23 and the YUV data to be output in response to a read-out control signal of the video encoder 15. Further, the DMA control circuit 21 extracts a 8x8 basic block of the YUV data through the DRAM I/F 22 from the DRAM 14 and transfers the block through the DMA transfer to a third FIFO 24. And the DMA control circuit 21 outputs the YUV data from the third FIFO 24 to a compandor circuit 13 in accordance with a read-out control signal of the compandor circuit 13. In connection with the aspect of the present embodiment thus arranged, an explanation will be given below about the data movement path in the recording mode by referring to FIG. 7A (S1-S4). First, as set out above, the image data obtained from the CCD is made to correspond to the YUV data of one frame output from the YUV signal processing circuit 11 at a given frequency (SI). The data is written, in a periodic fashion, by the DMA transfer in the DRAM 14 via the DMA controller 12 (S2). Further, the DMA controller 12 periodically reads out the YUV data which is developed from the YUV signal processing circuit 11 onto the DRAM 14 from the DRAM 14 in a way to correspond to the image map and the DMA controller 12 delivers the data to the video encoder 15 (S2-S3). In accordance with the periodic updating, on the DRAM 14, of the image information obtained by the CCD 6 the video encoder 15 generates a video signal based on the automatically updated information, so that it is possible to display a current image on a display screen 2 of the display device 16 without using the VRAM controller and VRAM provided on the conventional apparatus (S4) . By doing so, it is possible to make a cost lower and a circuit size smaller and to avoid a loss in dissipation power since there is no need for effecting data transfer to the VRAM. It is to be noted that, though one series of operations (S1-S4) is done by instructions of the CPU 17, the data are not passed through the CPU 17 so that the data can be moved at high speeds . With reference to FIG. 7B, an explanation will be given below about the path through which data is moved when the shutter key 4 is depressed on the digital camera by the operator at an imaging time, that is, in the recording mode (SI to S4). The CPU 17 allows a shift to an image recording/holding state and, at a completion of the transfer of a frame from the YUV signal processing circuit 11 to the DRAM 14, allows the DMA controller 12 to stop the obtainment of the YUV data. Simultaneously with this stopping, the compandor circuit 13 is started and the DMA controller 12 allows the YUV data of one frame to be DMA transferred from the DRAM 14 toward the compandor circuit 13 in an 8X8 basic block unit to correspond to the image map (S5) . The CPU 17 sequentially reads, from the compandor circuit 13, compressed data generated at the compandor circuit 13 and writes it to the flash memory 18 (S6). At this time, also during data compression at the compandor circuit 13 the transfer (S7) of the YUV data of the DMA controller 12 to the video encoder 15 can be continued. And by a video signal from the video encoder 15 it is also possible for the display device 16 to display the same image as the image information being compress-processing (S8). Other than the data readout from the compandor circuit 13 and data writing to the flash memory 18 is done by the DMA controller, etc., under an instruction of the CPU 17. Further in the reproduction mode, the data is moved as shown in FIG. 7C. That is, the YUV signal processing circuit 6 and its proceeding stage are set in a stopping state by the instruction of the CPU 17. In accordance with the operation of the image select key of any other keys by the operator, the code data of a specific image is read out from the flash memory 18 and written to the compandor circuit 13 (S9). And the data of the 8x8 basic block unit obtained by the expand-processing of the compandor 13 is DMA- transferred, by the DMA controller 12 under the instruction of the CPU 17, in a way to correspond to the image map to the DRAM 14 (S10). Simultaneously the DMA controller 12 effects the DMA-transfer to the video encoder 15 in a way to correspond to the image map and the image expanded thereby is displayed automatically on the display screen 2 of the display device 16 (S11-S12). Therefore, as in the same way as set out above, an image selected by the operation of the image select key which is stored in the flash memory 18 can be displayed on the display screen 2 of the display device 16 without using the VRAM controller and VRAM in the prior art apparatus . It is to be noted that other than the data readout from the flash memory 18 and data writing to the compandor circuit 13 is done by the DMA controller, etc., under the instruction of the CPU 17 and it is possible to effect a high-speed data movement because the data is not via the CPU 17. In the aspect of the present invention, a periodic development area of the YUV data in the YUV signal processing circuit 11 onto the memory area and readout area of it onto the memory of the video encoder 15 becomes matched to the same area on the DRAM 14. Since, however, the frame development period of the YUV data in the YUV signal processing circuit and frame readout period of the YUV data in the video encoder 15 are not necessarily synchronized with each other, if both gain access to the same area in such a way, there are sometimes the cases where an image display on the display device 16 is degenerated depending upon their periodic relation as shown in FIGS. 5A to 5D. That is, FIGS. 5A to 5C represent, on a time base, a YUV data writing line of the YUV signal processing circuit 11 and a YUV data reading line of the video encoder 15 in the case where the development area of the YUV data in the YUV signal processing circuit 11 and readout area of the YUV data of the video encoder 15 are the same. Here, the line means a horizontal line of the image and the horizontal line of this image is indicated by the ordinate axis and the time is set on the abscissa. Further, in FIGS. 5A to 5C, a dot- dash line shows the development of the YUV signal processing circuit 11 and a spacing between those adjacent dot-dash lines is a development period. Further, the solid line corresponds to the readout of the first field of the video encoder 15 and the dotted line to the second field. Thus, the spacing between those adjacent solid lines and that between those adjacent dotted lines are the readout period of the video encoder 15. Further, in FIGS. 5A to 5C, a relation between the development period of the YUV signal processing circuit 11 and the readout period of the video encoder 15 corresponds to the case of FIG. 5A being the development period = the readout period, the case of FIG. 5B being the development period > the readout period and the case of FIG. 5C being the development period < the readout period. It has been found that, in the case of FIGS. 5A and 5C, there occur crossings between the development lines and the readout lines at respective times tl, t2 and t3 and that, in the case of FIG. 5B there occur crossings between the development lines and the readout lines at respective times tl, t2, t3 and t4. In this way, the occurrence of the crossings between the development lines and the readout lines means that there occurs a mixed state between pre- and post- updated images of the development frames at the field (1/2 frame) displayed on the display screen 2. If any moving object is imaged, then a displayed object image is displaced on the display screen 2. In the case where, as shown in FIG. 5D, an intermittent relation are present between the development timing of the YUV signal processing circuit 11 and the readout timing of the video encoder 15, crossings (tl, t2) occur, but the time interval is broadened and, as in the case of FIGS. 5A to 5C, a displacement occurs on the displayed object image. However, this displacement is not prominent to the sense of the eye. Even if, by driving the peripheries of the CCD 6 or YUV signal processing circuit 11 by means of the timing generator 7 so as to obtain such an intermittent relation, the same area is accessed by the YUV signal processing circuit 11 and video encoder 15 and it is possible to suppress the displacement on the displayed object image caused upon picking up an image from a moving object. FIG. 6 shows the aspect of another embodiment of the present invention according to which any displace- ment on a displacement object image is eliminated by using two areas. That is, the relation of the development period of a YUV signal processing circuit 11 and the readout period of the field (1/2 frame) of the video encoder 15 is set to the development period > the readout period. Further, an area A and area B are provided at a DRAM 14 and, by a DMA controller circuit 21, the YUV signal processing circuit 11 performs an alternate development onto the areas A and B. At this time, the YUV signal processing circuit 11 allows an area control signal S which rises at a completion of a development onto the area A and falls at a completion of a development onto the area B to be generated at the DMA control circuit 21. The video encoder 15 effects a signal readout from the area B when the area control signal S is in a low-level state and a signal readout from the area A when the control signal S is in a high- level state. By doing so, no crossing occurs between the development and readout lines on the same area and it is possible to eliminate any displacement of a displayed object image in the display screen caused when a moving object image is taken.

Claims: C L A I M S 1. An image pick-up apparatus comprising: image pick-up means for picking up an image of an object and for generating a corresponding signal; generating means for generating image data of the object image based on the signal generated from the image pickup means ; recording means for recording, in response to a picking-up operation, the image data generated from the generating means; display control means for displaying the object image based on the image data generated from the generating means and for displaying, in response to a reproducing operation, an image based on the image data stored in the recording means; memory means for operation; and transfer means for transferring the image data from the generation means and recording means , in predetermined format, to the memory means while transferring the image data, in the predetermined format, from the memory means to the display control means . 2. The image pick-up apparatus according to claim 1, wherein the memory means includes one pair of areas in which the image data generated by the generating means is alternately written and the transferring means transfers, to the display control means, the image data on an area of the paired areas which is set in a not-written state. 3. An image pick-up apparatus comprising: image pick-up means for picking up an image of an object and for generating image data corresponding to the object; a temporary storing memory for temporarily storing the image data from the image pick-up means ; display means for displaying the image data of the temporary storing memory; and transfer means for transferring the image data of the image pick-up means to the temporary storing memory and display means . 4. The image pick-up apparatus according to claim 3, further comprising control means for controlling the image pick-up means, video encoder and transfer means. 5. The image pick-up apparatus according to claim 3, wherein the transfer means transfers the image picked-up data to the temporary storing memory to alternately write the data to a pair of areas of the temporary storing memory and reads the imaged data from the memory in a non-written state of the pair of areas to transfer the data to the display means. 6. The image pick-up apparatus according to claim 3, further comprising a video encoder for encoding the data of the temporary storing memory to a video signal and sending the video signal to the display means . 7. An image pickup apparatus comprising: an image pick-up element for picking up image data; a temporary storing memory for temporarily storing the image data from the image pick-up element; a compressing circuit for compressing the image data stored in the temporary storing memory; a preservation memory for preserving the image data compressed by the compressing circuit; display means for displaying the image data stored in the temporary storing memory; and transferring means for transferring the image data in the temporary storing memory to the compressing circuit and display means. 8. The image pickup apparatus according to claim 7, further comprising control means for controlling the transfer means and transferring the image data which is compressed by the compressing circuit to the preservation memory. 9. The image pickup apparatus according to claim 7, further comprising a video encoder for encoding the image data which is stored in the temporary storing memory to a video signal and for supplying the signal to the display means. 10. A recording image display apparatus comprising: a preservation memory for preserving compressed image data; an expanding circuit for expanding the compressed image data of the preservation memory; a temporary storing memory for storing the image data expanded by the expanding circuit; display means for displaying data encoded by a video encoder; and transfer means for transferring the image data which is expanded by the expanding circuit to the temporary storing memory and display means . 11. The recording image display apparatus according to claim 10, further comprising control means for controlling the transfer means and for transferring the image data of the preservation memory to the expanding circuit. 12. The recording image display apparatus according to claim 10, further comprising a video encoder for encoding the image data which is stored in the temporary storing memory to a video signal and for supplying the signal to the display means. 13. The recording image display apparatus according to claim 10, wherein the transferring means further transfers the picked-up data to the temporary storing memory and alternately writes the data to a pair of areas in the temporary storing memory and reads the image data from a memory at a non-written state one of the pair of areas and transfers the image data to the display means . 14. An image picking-up method comprises the steps of: picking up image data by an image pick-up element (Si); storing the image data from the image pick-up element in the temporary storing means (S2); and reading out the image data of the temporary storing memory while overlapping with the step, and sending the image data to display means (S3, S4). 15. The method according to claim 14, wherein the steps (S3, S4) further comprising the steps of: encoding the image data from the temporary storing memory by a video encoder (S3); and sending the data which is encoded by the video encoder to the display means (S4). 16. An image recording/displaying method comprising the steps of: picking up the image data by an image pick-up element (SI) ; storing the image data from the image pick-up element in a temporary storing memory (S2); compressing, by a compandor circuit, the image data stored in the temporary storing memory (S5); storing the image data which is compressed by the compandor circuit in a preservation memory (S6); and displaying, by displaying means, the image data which is stored in the temporary storing memory (S8) while overlapping with the step (S5). 17. The method according to claim 16, further comprising the step for encoding, by a video encoder, the image data stored in the temporary storing memory (S7 ) . 18. An image recording/displaying method comprising the steps of: sending compressed image data from a preservation memory to a compandor circuit (S9); and sending the image data which is expanded by the compandor circuit to a temporary preservation memory and sending the image data which is stored in the temporary preservation memory to display means (S10-S12) . 19. The method according to claim 18, wherein the step of sending the image data expanded by the compandor circuit to a temporary preservation memory reads the image data which is expanded by the expander circuit into transfer means and sends the data the temporary preservation memory (S10). 20. The method according to claim 18, wherein the step (S9) of sending compressed image data from a preservation memory to a compandor circuit comprises a step of reading the compressed image data from the preservation memory into control means and sending the data to the expander circuit (S9). 21. The method according to claim 18, wherein the step (S10-S12) of sending the image data which is stored in the temporary preservation memory to display means includes the step (Sll) of reading the image data which is stored in the temporary preservation memory into said transfer means and transferring the data to encoding means (Sll).

Inventors: YOKOI MAKOTO, YOKOI, MAKOTO
Applicants: CASIO COMPUTER CO LTD, YOKOI MAKOTO, CASIO COMPUTER CO., LTD., YOKOI, MAKOTO
Application year: 1998
Main classification: H04N5
IPC codes: H04N5, H04N9