OUTPUT STAGE WITH SELF-CALIBRATING SLEW RATE CONTROL

Abstract: An output stage comprising a first (1) and a second (2) supply terminal for receiving a supply voltage (SV), a pre-drive circuit (PDS) coupled to an input terminal (IP) for receiving an input signal (Vi), the pre-drive circuit (PDS) comprising a series transistor (TS) with a control electrode (TSg) for receiving a control voltage (Vcntrl) for controlling a maximum current from an output (PDSOUT) of the pre-drive circuit (PDS), and a capacitor (C) for retaining the control voltage (Vcntrl); an output-drive circuit (ODS) for delivering an output signal (Vo) at an output terminal (OP) in response to the input signal (Vi); and a control circuit (CC) for delivering the control voltage (Vcntrl). The output stage further comprises a control circuit (CC) which is coupled between the output terminal (OP) and the control electrode (TSg). The pre-drive circuit (PDS) and the output-drive circuit (ODS) together form a non-inverting output stage. If the slew rate of the output signal (Vo) is too large it will gradually be reduced by adapting the control voltage (Vcntrl). The control circuit (CC), the pre-drive circuit (PDS), and the output-drive circuit (ODS) together form a clocked feedback loop in order to automatically calibrate the slew rate of the output signal (Vo) during a few clock cycles.

Description: Output stage with self calibrating slew rate control. The invention relates to an output stage comprising a first and a second supply terminal for receiving a supply voltage; a pre-drive circuit coupled to an input terminal for receiving an input signal, the pre-drive circuit comprising a series transistor with a control electrode for receiving a control voltage for controlling a maximum current from an output of the pre-drive circuit, and a capacitor for retaining the control voltage; an output- drive circuit for delivering an output signal at an output terminal in response to the input signal; and a control circuit for delivering the control voltage. Such an output stage is known from US Patent 4,972, 101. In this known output stage the maximum current which can be drawn from the output of the pre-drive circuit is limited and as a consequence the rate of change of the output signal is limited as well. This is done to limit the rate of change of current through the first supply terminal and thus also limit the rate of change of current through the output terminal (when a load is coupled with the output terminal). The limitation of the rate of change through the first supply terminal and/or the output terminal is needed to reduce parasitic voltage spikes at the first supply terminal and/ or at the output terminal caused by parasitic inductances in series with the first supply terminal and/ or in series with the output terminal. In the known output stage the control circuit comprises a dummy output stage and a buffer stage. The dummy output stage supplies, via the buffer stage, the control voltage. Especially when applied in an integrated circuit the addition of the dummy output stage is by itself disadvantageous because of the relatively large amount of extra chip-area needed. In the aforementioned patent the dummy output stage is provided with several capacitors. Also these capacitors increase the needed chip-area. Further the presence of the buffer stage also increases the needed chip-area considerably. A further drawback of the known output stage is that the accuracy of the control voltage is dependent on matching between components in the control circuit and components in other parts of the output stage. It is an object of the invention to provide an improved output stage which eliminates the above mentioned drawbacks. To this end, according to the invention, the output stage of the type defined in the opening paragraph is characterized in that the control circuit is coupled between the output terminal and the control electrode. With this it is accomplished that the control voltage is dependent on the rate of change of the output signal. In fact the slew rate of the output signal is calibrated by the output stage itself. An advantage of this is that no accurate matching of components is required between components in the control circuit and components in other parts of the output stage. An embodiment of an output stage according to the invention may be characterized in that the control circuit CC comprises level detecting means LDMNS for delivering at least one digital signal dependent on a level of the output signal. The digital level is used to determine whether the control voltage must be adapted or not. Another embodiment of an output stage according to the invention may be characterized in that the output stage comprises means for delivering a clock signal during a first clock edge of the clock signal; and in that the control circuit comprises means for adapting the control voltage in dependency of the at least one digital signal, the adapting of the control voltage being triggered by the first or a second clock edge of the clock signal. By doing so the control voltage is adapted in a synchronized way in respect of the input signal. This makes it more easy to adapt the control voltage in a proper way. Yet another embodiment of an output stage according to the invention may be characterized in that the pre-drive circuit comprises means for discharging or charging the capacitor. By this a leakage path for the capacitor is provided so that under DC conditions the capacitor is fully discharged (or charged), and the series transistor is fully turned on. With this the output stage has a fail safe mode of operation in that the natural tendency of the slew rate of the output signal is maximal. By this the output stage always starts with a maximal slew rate of the output signal just after the start-up of the output stage. With this a valid output signal can be generated at the output terminal as soon as possible. After the end of the start-up of the output stage the control voltage will be adapted in order to reduce the slew rate of the output signal and thereby reducing the parasitic voltage spikes at the first supply terminal and/or at the output terminal. If for some reason the control voltage is adapted too much (overcompensation) during normal operation, that is to say not during the start-up of the output stage, then over time the leakage path will pull back the control voltage to its correct value. A further embodiment of an output stage according to the invention may be characterized in that the output stage comprises evaluation means for delivering a digital evaluation signal for avoiding the control voltage being adapted when the input signal has not changed during a next clock cycle of the clock signal. With this an undesirable change of the control voltage is avoided. The invention will be described in more detail with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram of an embodiment of an output stage in accordance with the invention; and Figures 2, 3 and 4 are sets of diagrams showing signals in order to better explain the output stage shown in Figure 1. In these Figures parts or elements having like functions or purposes bear the same reference symbols. Figure 1 is a circuit diagram of an embodiment of an output stage in accordance with the invention. The output stage comprises an input terminal IP for receiving an input signal V j and an output terminal OP for delivering an output signal V 0 . A supply voltage SV is connected between a first supply terminal 1 and a second supply terminal 2. A load, implemented with a load capacitor C L , is connected between the output terminal OP and the first supply terminal 1. A parasitic inductance L is shown in series with the load capacitor C L . The parasitic inductance L_ will cause relatively large voltage spikes at the output terminal OP if the slew rate of the output signal V 0 is relatively large. Like the parasitic inductance L in series with the output terminal OP also other parasitic inductances in series with the first supply terminal 1 or the second supply terminal 2 can cause relatively large voltage spikes at the first supply terminal 1 and the second supply terminal 2, respectively. By way of example the invention only describes the reduction of the voltage spikes at the output terminal OP due by the parasitic inductance L^, but the invention also reduces the voltage spikes at the first and the second supply terminals 1,2 in a similar way. The output stage further comprises an output drive circuit ODS, a pre- drive circuit PDS, a further pre-drive circuit PDS A , a control circuit CC, evaluation means EVMNS, and means CLKMNS for delivering a clock signal V CLK at a clock terminal CLK. The input signal V j is a clocked signal. This is indicated by the dashed arrow DRRW. The output drive circuit ODS comprises a field effect transistor T 0 and a further field effect transistor T 0A . The first field effect transistor T 0 comprises a gate GN, a source connected to the first supply terminal 1 , and a drain connected to the output terminal OP; and the further field effect transistor T 0A comprises a gate GP, a source connected to the second supply terminal 2, and a drain connected to the output terminal OP. The pre-drive circuit PDS is connected via an output PDS 0UT to the gate GN of the field effect transistor T 0 , and with a input PDS IN to the input terminal IP. The pre-drive circuit PDS comprises first, second, third, fourth, and fifth transistors Qi , Q 2 , Q 3 , Q 4 , Q 5 ; a series transistor TS; and a capacitor C. The first and second transistors Q j , Q 2 both have an input electrode connected to each other, in that way constituting the input PDS IN of the pre-drive circuit PDS. The first and second transistors Q l s Q 2 both have a first main electrode connected to each other, in that way constituting the output PDS 0 τ j τ °f e pre-drive circuit PDS. A second main electrode of the first transistor Q j is connected to the first supply terminal 1. The series transistor TS comprises a control electrode TS g , and a main current path coupled between the second supply terminal 2 and a second main electrode of the second transistor Q 2 . The capacitor C is connected between the control electrode TS g and the first supply terminal 1. The third transistor Q 3 has an input electrode, a first main electrode connected to the control electrode TS„, and a second main electrode. The fourth transistor Q 4 is arranged as a diode configuration between the second supply terminal 2 and the second main electrode of the third transistor Q 3 . The fifth transistor Q 5 is arranged, as means for discharging the capacitor C, between the control electrode TS and the first supply terminal 1. Though not excluded, the fifth transistor Q 5 is generally not implemented as a diode configuration because a diode configuration would discharge the capacitor C too rapid. More appropriate is that the fifth transistor Q 5 is, for instance, implemented with a bipolar transistor (but a field effect transistor can also be applied) with its base and emitter both connected to the first supply terminal 1, and its collector connected to the control electrode TS„. However any high ohmic impedance across the capacitor C can serve as means for discharging the capacitor C. The further pre-drive circuit PDS A is connected via an output PDS 0UT to the gate GP of the further field effect transistor T 0A , and with a input PDS INA to the input terminal IP. The further pre-drive circuit PDS A comprises sixth, seventh, eighth, ninth, and tenth transistors Q 1A , Q 2A , Q 3A , Q 4A , Q 5A ; a further series transistor TS A ; and a further capacitor C A . The sixth and seventh transistors Q 1A , Q 2A both have an input electrode connected to each other, in that way constituting the input PDS INA of the further pre-drive circuit PDS A . The sixth and seventh transistors Q 1A , Q 2A both have a first main electrode connected to each other, in that way constituting the output PDS QUTA of the further pre-drive circuit PDS A . A second main electrode of the first transistor Q 1A is connected to the second supply terminal 2. The series transistor TS A comprises a further control electrode TS A , and a main current path coupled between a second main electrode of the second transistor Q 2 and the first supply terminal 1. The further capacitor C A is connected between the control electrode TS A and the first supply terminal 1. The eighth transistor Q 3A has an input elec- trode, a first main electrode connected to the further control electrode TS gA , and a second main electrode. The ninth transistor Q 4A is arranged as a diode configuration between the second main electrode of the eighth transistor Q 3A and the first supply terminal 1. The tenth transistor Q 5A is arranged, for instance in the same way as the fifth transistor Q 5 , as further means for discharging the further capacitor C A , between the second supply terminal 2 and the further control electrode TS gA . It is to be noticed that the third, fourth, and fifth transistors Q 3 , O^, Q 5 form a common part of the pre-drive circuit PDS and the control circuit CC. The control circuit CC further comprises means LDMNS for delivering at least one digital signal having a digital level dependent on a level of the output signal V 0 . The means LDMNS comprises a first comparator CMP, ^ and a second comparator CMP 2 . All kind of comparators, such as inverter stages, can be used for the first and second comparators CMPi , CMP 2 . An input of the first comparator CMP j is connected to the output terminal OP, an output of the first comparator CMP, is connected to a first control terminal ABV95. An input of the second comparator CMP 2 is connected to the output terminal OP, an output of the second comparator CMP 2 is connected to a second control terminal ABV05. The comparator CMPi is dimensioned in such a way that when the level of the output signal V 0 exceeds a high reference level RF H , for example 95 % of the supply voltage SV, the signal at the first control terminal ABV95 will become logic "high" . Analog- ous to comparator CMPi , comparator CMP 2 is dimensioned in such a way that when the level of the output signal V 0 exceeds a low reference level RF L , for example 5 % of the supply voltage SV, the signal at the second control terminal ABV05 will become logic "high" . The control circuit CC also comprises a logic and-gate AND with a first, a second, a third and, a fourth input, and an output connected to a third control terminal SLP; and a logic or-gate OR with a first, a second, a third and a fourth input, and an output connected to a fourth control terminal SLN; a first inverter IV with an input and an output; and a second inverter IV 2 with an input and an output. The evaluation means EVMNS comprises a flip-flop FF with a data input D Fp which is connected to the input terminal IP, a clock input CLK FF connected to the clock terminal CLK, and an output Q FF ; and an exclusive or-gate E with a first input A connected to the input terminal IP, a second input A 2 connected to the output Q FF of the flip-flop FF, and an output Q E connected to the first input of the and-gate AND, and connected to the input of the second inverter IV 2 . The second input of the and-gate AND, and the fourth input of the or-gate O OR are connected to the input terminal IP. The second input of the or-gate OR, and the input of the first inverter IV j are connected to the clock terminal CLK. The output of the first inverter IV, is connected to the fourth input of the and-gate AND. The third input of the and-gate AND is connected to the first control terminal ABV95. The third input of the or- gate OR is connected to the second control terminal ABV05. The output of the second inverter IV 2 is connected to the first input of the or-gate OR. The input electrode of the third transistor Q 3 is connected to the fourth control terminal SLN. The input electrode of the eight transistor Q 3A is connected to the third control terminal SLP. In Figure 2 diagrams I, II, III, IV and V represent respectively the clock signal V CLK , the input signal V j , the output signal V 0 , a first slew rate control signal V SLP at the third control terminal SLP, and a second slew rate control signal V SLN at the fourth control terminal SLN. The operation of the field effect transistor T 0 and the further field effect transistor T 0A are complementary that is to say that when the output signal V 0 changes from logic "high" to logic "low" the field effect transistor T 0 will be conducting whereas the further field effect transistor T 0A will be non-conducting. The reverse will happen when the output signal V 0 changes from logic "low" to logic "high" . The elements of the following pairs have a mutual similar operation: T 0 /T 0A , GN/GP, PDS/PDS A , PDS IN /PDS INA , PDS 0UT /PDS 0UTA , C/C A , TS/TS A , TS g /TS gA , QjVQi A , Q 2 /Q 2A' QVQSA * Q 4 /Q 4A ' Q 5 /Q 5A< V SLN /V SLP , S DWN /S UP , W N /W P , RF L /RF H , V cntrl /V cntrlA . The operation of the output stage is as follows. To begin with assume that the input signal V j changes every time when the clock signal V CLK changes from a logic "low" to a logic "high" level as indicated in Figure 2. As a consequence, as will be explained later, an evaluation signal EVS (see Figure 3) at the output Q E of the exclusive or- gate E is logic "high". Because the pre-drive circuit PDS is an inverting amplifier, the signal at the output PDS 0UT of the pre-driver circuit PDS has an opposite phase with respect to the input signal V j . However since the output drive circuit ODS is also an inverting amplifier the output signal V 0 has the same phase with respect to the input signal V j . Thus in the time interval t 0 -tι the output signal V 0 changes from logic "low" to logic "high". The up going slopes of the output signal V 0 are indicated by S UP (for instance in the time interval tg-t j ). The down going slopes of the output signal V 0 are indicated by S DWN (for instance in the time interval t 3 -t 4 ). Let us (for the time being) leave out of consideration the down going slopes S DWN , the second slew rate control signal V SLN , and a control voltage V cntrl across the capacitor C because they have similar functions as the up going slopes S UP , the first slew rate control signal V SLP , and a further control voltage V cntrlA across the further capacitor C A , respectively. The up going slope Syp is considered to be too steep in the time interval t -t j and must thus be reduced in order, to reduce parasitic voltage spikes at the output ter- minal OP caused by the parasitic inductance L p in series with the output terminal OP. This is done by adapting the further control voltage V cntrlA during a certain time interval when the clock signal V CLK is logic "low". The first slew rate control signal V SLP is only logic "high" when the level of the output signal V 0 is higher than the high reference level RF H and when the clock signal V LK is at the same time logic "low". At time t 2 the clock signal V CL κ becomes logic "low" and since the level of the output signal V 0 is already higher than the high reference level RF H , the first slew rate control signal V SLP becomes logic "high" . The first slew rate control signal V SLP stays logic "high" up to time t 3 because then the clock signal V CLK becomes logic "high" again. The pulse width W p of the first slew rate control signal V SLP is defined as the duration of time in which the first slew rate control signal V SLP is logic "high". Since during the time interval t 2 -t 3 the first slew rate control signal V SLp , at the third control terminal SLP, is logic "high" the eighth transistor Q 3A is conducting. As a consequence the further capacitor C A is, partly, discharged via the eighth transistor Q 3A and the ninth transistor Q 4A . By this the further control voltage V cntrlA across the further capacitor C A is reduced and as a consequence the transconductance of the further series transistor TS A is reduced as well. By this a maximum current at the output PDS 0 TJ T A °f me further pre-drive circuit PDS A is reduced. As a consequence the gate-source capacitance of the further field effect transistor T 0A will be charged less rapidly when the output signal V 0 has to change from logic "low" to logic "high" again. For this reason the up going slope Sτ jP in the time interval t 6 -t 8 is less steep than in the time interval tφ-ti . Therefore when the clock signal V CLK changes from logic "high" to logic "low" at time t 7 the first slew rate control signal V SLP does not yet change from logic "low" to logic "high" because at time t 7 the level of the output signal V 0 is still lower than the high reference level RF H . At time t 8 the level of the output signal V 0 is equal to the high reference level RF H . The first slew rate control signal V SLP becomes logic "high" and stays logic "high" up to time Xg because then the clock signal V CLK becomes logic "high" again. So because the up going slope Sτ jP is less steep in the time interval t 6 -t 8 , in respect to the time interval t^-t j , the pulse width W p in the interval t 8 -t 9 is smaller than it was the case in the time interval t 2 -t 3 . Analogous to the case in the time interval t 2 -t 3 the maximum current at the output PDS 0UTA of the further pre-drive circuit PDS A is further reduced. The amount of further reduction of the maximum current at the output PDS Q UTA * S however less than the reduction earlier in the time interval t 2 -t 3 because of the fact that the pulse width W p in the interval t 8 -t 9 is smaller than it was the case in the time interval ^-t β . The up going slope S UP in the time interval t 11 -t 12 is less steep than in the time interval tg-tg. The level of the output signal V 0 equals the high reference level RF H at time t 12 . However at time t 12 the clock signal V CLK changes from logic "low" to logic "high". For this reason the first slew rate control signal V SLP keeps logic "low". The slope S UP has reached the desired steepness and the first slew rate control signal V SLP will, in principle, stays logic "low" . In Figure 3 diagrams I, II, III, IV, V, VI, and VII represent respectively the clock signal V CLK , the input signal V j , the output signal V 0 , the first slew rate control signal V SLP , a delayed input signal V iDLD , the evaluation signal EVS, and an adapted first slew rate control signal V SLPa at the third control terminal SLP. Until now it has been assumed that the input signal V j changes every time when the clock signal V CLK changes from a logic "low" to a logic "high" level. In practice this is rarely the case. It often happens that the input signal V j , and as a consequence the output signal V 0 as well, does not change for a couple of clock cycles. At time T 0 both the clock signal V CLK and the input signal V j change from logic "low" to logic "high". This causes the output signal V 0 to change, gradually, from logic "low" to logic "high". In the time interval T T 2 the first slew rate control signal V SLP is logic "high", which is in accordance with the time interval t 8 -t 9 as shown in Figure 2. At time T 3 the first slew rate control signal V SLP also becomes logic "high" since the clock signal V CLK becomes logic "low" while the level of the output signal V 0 is already higher than the high reference level RF H . This is in accordance with time ^ shown in Figure 2. However the reason that the level of the output signal V 0 is already higher than the high reference level RF H is not because the up going slope S UP is too steep, as was the case in the time interval tø-ti as shown in Figure 2, but because the output signal V 0 did not change at time T 2 . Therefore the "high" logic value of the first slew rate control signal V SLP in the interval T 3 -T 4 , which is shown shaded in Figure 3, is false. For this reason the first slew rate control signal V SLP must be replaced by the adapted first slew rate control signal V SLPa . This is done with the aid of the evaluation signal EVS. The evaluation signal EVS evaluates the first slew rate control signal V SLP . When the evaluation signal EVS is logic "high" the adapted first slew rate control signal V SLPa is equal to the first slew rate control signal V SLP , otherwise the first slew rate control signal V SL p a is logic "low". In order to accomplish this the delayed input signal V iDLD at the output Q FF of the flip-flop FF, and thus at the second input A 2 of the exclusive or-gate E is compared with the input signal V t at the first input A, of the exclusive or-gate E. This results in the evaluation signal EVS at the output Q E of the exclusive or-gate E. It is to be noticed that the output stage as described so far attempts to control the up going slope S υp and the down going slope S D N so that the level of the output signal V 0 just reaches the logic "high" or logic "low" level at the end of the clock cycle. This may not be "safe" enough for some applications. A slight modification to the control circuit CC allows the up going slope Stjp and the down going slope S D WN t0 De controlled so that the level of the output signal V 0 just reaches the logic "high" or logic "low" level at the end of half a clock cycle. The level of the output signal V 0 will therefore easily reach a valid logic "high" or logic "low" level by the end of the clock cycle. This solution also simplifies the dimensioning of the first and the second comparators CMP 1 ; CMP 2 . The modification is as follows: the fourth input of the logic and-gate AND must be connected to the input of the first inverter IV , instead of to the output of the first inverter IV , ; and the second input of the logic or-gate OR must be connected to the output of the first inverter IV, instead of to the input of the first inverter IV, . In Figure 4 the effect of the above mentioned modification is shown. Figure 4 should be compared with Figure 2. The main difference is that the first slew rate control signal V SLP is only logic "high" when the level of the output signal V 0 is higher than the high reference level RF H and when the clock signal V CLK is at the same time logic "high" (in stead of logic "low" as in the case shown in Figure 2). The capacitor C may also be connected between the control electrode TS and the second supply terminal 2 (in stead of the first supply terminal 1). This also holds for the further capacitor C A . If appropriate, instead of discharging the capacitor (C, C A ) also charging the capacitor (C, C A ) may be interpreted. The transistors may be implemented by all kind of transistors. Also the logic gates of the control circuit CC and the evaluation means EVMNS may be implemented differently. In stead of the capacitive load C L connected , between the output terminal OP and the first supply terminal 1 any kind of load may be coupled between the output terminal OP and the first supply terminal 1 and/ or between the output terminal OP and the second supply terminal 2. The output stage can be constructed as an integrated circuit or also by means of discrete components.

Claims: CLAIMS 1. An output stage comprising a first (1) and a second (2) supply terminal for receiving a supply voltage (SV); a pre-drive circuit (PDS) coupled to an input terminal (IP) for receiving an input signal (V j ), the pre-drive circuit (PDS) comprising a series transistor (TS) with a control electrode (TS g ) for receiving a control voltage (V cntrl ) for controlling a maximum current from an output (PDS 0UT ) of the pre-drive circuit (PDS), and a capacitor (C) for retaining the control voltage (V cntrl ); an output-drive circuit (ODS) for delivering an output signal (V 0 ) at an output terminal (OP) in response to the input signal (V j ); and a control circuit (CC) for delivering the control voltage (V cntrl ), characterized in that the control circuit (CC) is coupled between the output terminal (OP) and the control electrode (TS g ). 2. An output stage as claimed in Claim 1, characterized in that the control circuit (CC) comprises level detecting means (LDMNS) for delivering at least one digital signal dependent on a level of the output signal (V 0 ). 3. An output stage as claimed in Claim 2, characterized in that the output stage comprises means (CLKMNS) for delivering a clock signal (V CLK ) during a first clock edge of the clock signal (V CLK ); and in that the control circuit (CC) comprises means (Q 3 ,Q 4 ) for adapting the control voltage (V cmrl ) in dependency of the at least one digital signal, the adapting of the control voltage (V cntrl ) being triggered by the first or a second clock edge of the clock signal (V CLK ). 4. An output stage as claimed in Claim 3, characterized in that the pre-drive circuit (PDS) comprises means (Q 5 ) for discharging or charging the capacitor (C). 5. An output stage as claimed in Claim 3 or 4, characterized in that the output stage comprises evaluation means (EVMNS) for delivering a digital evaluation signal (EVS) for avoiding the control voltage (V cntrl ) being adapted when the input signal (V j ) has not changed during a next clock cycle of the clock signal (V CLK ). 6. An output stage as claimed in Claim 5, characterized in that the evaluation means (EVMNS) comprises a flip-flop (FF) with a data input (D FF ) for receiving the input signal (V j ), a clock input (CLK FF ) for receiving the clock signal (V CLK ), and an output (QFF) f° r delivering a delayed input signal (VJΓJL ΓJ ); and an exclusive or-gate (E) with a first input (A j ) for receiving the input signal (Vj), a second input (A 2 ) coupled to the output (Q FF ) of the flip-flop (FF), and an output (Q E ) for delivering the digital evaluation signal (EVS).

Inventors: LABRAM STEVEN MARK, LABRAM, STEVEN, MARK
Applicants: KONINKL PHILIPS ELECTRONICS NV, PHILIPS SVENSKA AB, KONINKLIJKE PHILIPS ELECTRONICS N.V., PHILIPS AB
Application year: 1998
Main classification: H03K17
IPC codes: H03K17