Symbol synchronization in multicarrier receivers

Abstract: Improved synchronization of OFDM signals is achieved. A controlled oscillator (8) provides clock pulses to derive complex samples of an input signal which are applied both to a fast Fourier transform (5) for data recovery and to a synchronization unit (9). The synchronization unit generates the complex product XY* of the input and the delayed input, which is applied to a high-pass filter (30) to suppress frequencies below the symbol frequency. The filter output is applied through a symbol comb filter (40) to an adaptive slicer (50) which determines the larger magnitude of the real and imaginary components of the signal. A pulse processor (60) generates a single pulse at the leading edge of the symbol pulse which is applied to a symbol counter (70). The symbol counter includes two count stages (74,75) arranged to lock in quickly and yet be variable to accommodate different guard intervals in the OFDM signal.

Description: Background of the Invention This invention relates to apparatus for synchronizing with a signal which consists of a succession of symbol periods each consisting of an active symbol period and a guard interval. In particular the invention relates to apparatus for synchronizing with Orthogonal Frequency Division Multiplex (OFDM) signals, such as may be used for broadcasting digital television signals in the uhf (ultra high frequency) bands, or for digital audio broadcasting (DAB). The form of OFDM signal proposed for this purpose consists of data signals and reference information modulated as QPSK (quadrature phase shift keying) or QAM (quadrature amplitude modulation) on to several thousand individual carriers, evenly spaced in frequency and occupying a total bandwidth of several Megahertz in the uhf spectrum. The data signal on each carrier has a relatively long symbol period and this, in part, gives the signal its good performance in conditions of multipath propagation. The multipath performance is further enhanced by the inclusion of a guard interval in which a portion of the modulated signal waveform taken from the end of each symbol is also included at the beginning of the same symbol period. Different fractions of the basic symbol period, such as 1/32, 1/16, 1/8 or 1/4, can be used in this way to provide immunity to multipath distortion of increasingly long delays. More specifically, each symbol is extended by a period T G (the guard interval) which precedes the "useful" or "active" symbol period T S , so that the whole symbol now lasts T T in total. T S is the reciprocal of the carrier spacing f S , and is the duration of the time domain signal produced or analysed by the FFT (fast Fourier transform) in the transmitter and receiver respectively. Each carrier is continuous over the boundary between the guard interval and the active part of the same symbol, keeping the same amplitude and phase. If the signal at complex baseband is considered, with all the carrier frequencies not only spaced f S , but also equal to multiples of f S , then the signal in the guard interval is effectively a copy of the segment of the signal occupying the last T G 's worth of the active part, as shown in Figure 4 of the accompanying drawings. It follows that the signal has the same value at any two instants which are separated by T S but lie within the same symbol. Specific proposals for synchronization of OFDM receiving apparatus have been published for example in European Patent Applications EP-A-0 653 858 and 0 608 024, and International Patent Applications WO95/07581, WO95/05042 and WO95/03656. The principal requirement for synchronization in a receiver is to obtain from the signal waveform a reliable time synchronization pulse related to the start of the symbol period. Such a pulse could then be used to start, at the correct position in the waveform, the process of Fourier transformation which accomplishes a major portion of the demodulation process. A second requirement for synchronization is to lock the digital sampling clock in the receiver to an appropriately chosen harmonic of the symbol period. However, the modulated OFDM waveform produced by adding together all the modulated carriers is essentially noise-like in nature and contains no obvious features such as regular pulses which could be used to synchronize the circuitry of a receiver. Because of this, we have previously proposed techniques for synchronization which are based on correlation of the signal with a version of itself delayed by the basic symbol period. The similarity between the portion included to form the guard interval and the final part of the basic symbol is then shown as a region of net correlation, while the remainder of the symbol period shows no correlation. Even so, the correlated waveform still reflects the noise-like nature of the signal waveform and can be impaired by signal distortions, so it is necessary to process the signal further to obtain reliable synchronization. Our European patent application No. 96307964.5, publication No. 0 772 332 (publication date 7 May 1997), describes the use of a correlator with a filter which exploits the periodicity of the waveform to form a complex symbol pulse and then uses the argument of the pulse to obtain frequency control for a local oscillator. In addition, the modulus of the pulse signal is used to derive a pulse related to the start of the symbol period and to derive a signal to control the clock frequency in the demodulator. A complex integrate-and-dump technique is included in the clock loop to suppress interference. Attention is also drawn to US Patent 5,559,833, which describes a device for recovering symbol timing in an OFDM system, in which a difference signal is obtained by subtracting from a symbol block a corresponding delayed symbol block, and is used to control a phase-locked.loop oscillator. Summary of the Invention The present invention is defined in claim 1 below, to which reference should now be made. Advantageous features of the invention will be described in more detail by way of example with reference to the drawings. A preferred embodiment of the invention is described in more detail below. The preferred embodiment also uses correlation and a filter which exploits the periodicity of the waveform to form a symbol pulse, but additionally uses a symbol period counter to provide stable and correctly timed pulses to start the process of Fourier transformation and to provide a control signal to lock the sampling clock in the demodulator. The symbol period counter is of particularly ingenious construction which does not require the counter to rephase itself through a full symbol period. Instead we have appreciated that the counter can be split into two parts, in such a way as to lock in much more quickly. The present improvement can with advantage be used together with the improvements of the parent application EP-A-0 876 031 and sister application EP-A-1 267 539. It can be used with the complex conjugate (XY*) method described in our above-mentioned European patent application No. 96307964.5, but does not require use of the complex conjugate method and can be used with other methods of deriving the complex signal. Brief Description of the Drawings The invention will now be described in more detail, be way of example, with reference to the accompanying drawings, in which: Figure 1 is a block circuit diagram of the relevant part of an OFDM receiver embodying the invention; Figure 2 is a block circuit diagram of the synchronization unit of the receiver of Figure 1; Figure 3 is a block circuit diagram of the symbol counter of the synchronization circuit in the receiver of Figure 1; and Figure 4 (described above) is a diagram showing how each symbol comprises an active symbol and a guard interval, and illustrates the relationship between them. Detailed Description of the Preferred Embodiment The system will be described using parameter values from a particular system of digital OFDM signal transmission by way of example. More details of this system are contained in ETSI draft document prETS 300 744, November 1996, now document ETS 300 744 dated March 1997. The relevant parts of an OFDM receiver embodying the invention are shown in block diagram form in Figure 1. The receiver has a uhf input 1 which applies a received signal to a down-converter 2. The output of the down-converter is applied to an a-d (analog-to-digital) converter 3 which receives a clock input from a voltage-controlled crystal oscillator 8 and supplies an output to a real-to-complex converter 4. The output of the real-to-complex converter 4 is applied first to a Fourier transform circuit, such as a well-known FFT (fast Fourier transform), and also to a synchronization unit 9. The output of the Fourier transform circuit is applied to data recovery circuitry 6, based on that in a known OFDM receiver, to provide a data output at 7. The synchronization unit 9 has two outputs, namely an output 10 which is coupled to the Fourier transform circuit 5, and an output 11 which is applied to the controlled oscillator 8. Finally, the synchronization unit 9 receives the clock signal from the controlled oscillator 8. The operation of the circuit of Figure 1 is as follows. A received uhf OFDM input signal at the input 1 is down-converted by frequency shifting in the down-converter 2 to occupy a bandwidth of nominally 8MHz in the region 0-9MHz. It is then sampled by the a-d converter 3, operating with a sampling frequency of 18·285714 MHz from the voltage-controlled crystal oscillator 8. The real samples from the a-d converter are converted by the real-to-complex converter 4 into the form of complex samples at 9·142857 MHz required for Fourier transformation in the Fourier transform circuit 5. As each complex sample consists of real (R) and imaginary (I) components, it is convenient to multiplex the two together in a sequence R 1 I 1 R 2 I 2 ... thus retaining the 18·285714 MHz rate of the data stream. Accordingly, the synchronization unit 9 accepts the OFDM signal waveform as a series of complex samples which are then processed to produce a series of regular symbol pulses at output 10 to start the transform at the appropriate time in the symbol. Additionally, the synchronization unit can provide a signal at output 11 to lock the controlled oscillator 8. This is achieved by comparing the timing of regular symbol pulses which are produced by dividing the sampling clock by an appropriate ratio, with the timing of the symbol pulses extracted from the incoming signal waveform. The main elements of the synchronization unit 9 are shown in Figure 2. Referring to Figure 2, the complex input from the real-to-complex circuit 4 is applied to an input terminal 21 and thence to a delay 20 with a duration equal to the basic symbol period T S and to a conjugating circuit 24. The conjugating circuit 24 forms the complex conjugate of each sample by inverting the imaginary part. The outputs of the delay 20 and conjugating circuit 24 are both applied to a full four-component complex multiplier 22. Thus, the multiplier provides an output XY*, where Y is the input signal, X is the signal Y after the delay 20, and the asterisk (*) indicates the complex conjugate. The delay 20, conjugating circuit 24 and multiplier 22 operate as a correlator, as described in our above-mentioned European patent application No. 96307964.5. The output of the multiplier 22 is applied to a high-pass filter circuit 30, the output of which is applied to a symbol-period comb filter 40. The output of the filter is then applied to an adaptive slicing circuit 50 the output of which in turn is applied to a pulse processing circuit 60. The output of the pulse processing circuit 60 is then applied to a symbol counter 70. The operation of the synchronization circuit shown in Figure 2 is as follows. The noise-like OFDM signal in complex form is applied to the delay 20 with a duration equal to the basic symbol period, and to the conjugating circuit 24 which forms the complex conjugate of each sample by inverting the imaginary part. The correlation between the two signals is produced by the complex multiplier 22 and appears as a noisy pulse waveform at symbol rate. It should be recognised that the conjugation process 24 can alternatively be placed in the delayed signal, that is in series with the delay 20, with equal effectiveness. That is, the signal YX* is generated rather than XY*. The high-pass filter circuit 30 is included to remove complex-valued offsets introduced by interference. This is followed by the symbol-period comb filter 40, which exploits the periodic nature of the waveform to suppress noise and other impairments so as to produce a rectangular pulse, the duration of which is related to the guard interval. It should be noted that the comb filter 40 could be placed before the high-pass filter 30 with similar effectiveness. The adaptive slicing circuit 50 is used to prepare the complex waveform for slicing at the most advantageous point, taking account of the effects of local oscillator frequency errors, amplitude variations, and distortions arising from multipath propagation. This circuit 50 is followed by the pulse processing circuit 60, which generates a single pulse at the leading edge of the symbol pulse, and prevents the generation of spurious pulses which might arise from multiple crossings of the slicing level in a noisy signal. The timing of the pulses produced by the pulse processing circuit 60 is compared with the timing of pulses produced by dividing the sampling clock frequency down to symbol rate in the symbol counter 70. The comparison produces a signal at output 11, which is used to control the clock oscillator 8. Regular appropriately-timed symbol rate pulses at output 10 are derived from the symbol counter 70 and are used to start the Fourier transform processing on each symbol. The pulses from the pulse processing circuit 60 are also used for initial resetting of the symbol counter 70 during lock-up; but after the initial period, adjustment of the position of the pulses at output 10 is obtained only by controlling the sampling clock frequency. This ensures that the number of clock periods between symbol pulses remains constant, which is necessary for simplifying the operation of subsequent processing in the data recovery circuitry 6 in Figure 1. The operation of Figure 2 will now be described in more detail. For a description of the circuits 30, 40, 50 and 60, see EP 876 031A. Symbol pulses to start the Fourier transform are generated by the symbol counter 70, as shown in more detail in Figure 4. The symbol counter is divided into a lower stage 75 and an upper stage 74. The symbol pulses from the pulse processor 60 received at an input 71 are applied to an OR gate 73. The output of the gate 73 is applied to the upper stage 74, the output of which is applied to an AND gate 76 which provides the output 10, and also to the other input of the gate 73. Received clock pulses from the clock oscillator 8 at an input 72 are applied to the lower stage 75, the output of which is applied to the other input to gate 76 and as an enabling input to the upper stage 74. The output of the lower stage 75 is also applied to a register 78, which receives the input symbol pulses as an enabling input. The register 78 constitutes the output 11 of the symbol counter 70 which is fed back to control the oscillator 8. The symbol counter 70 is designed to work with OFDM signals which have different guard intervals, namely equal to 1/32, 1/16, 1/8, or 1/4 of the active symbol period. Nevertheless this is achieved with a minimum of complexity. Furthermore it does it in such a way that it is not necessary for the symbol counter to rephase itself through the total symbol period T T ; if this were the case it would take a very long time to pull the counter round to synchronization. This is achieved by splitting the counter into two parts of which the lower part is common, regardless of the guard interval, and the upper part is simply variable. The counter is based on the realisation that for all the possible values of the guard interval, a highest common factor (hcf) exists for the duration, in clock pulses, of the symbol period. In the present example the actual values are: Guard interval Duration of Symbol Period in Clock Pulses 1/32 4224 1/16 4352 1/8 4608 1/4 5120 The highest common factor of the values in the right-hand column above is the value 128. This is used as the basis of the lower stage 75, which counts up to 128. The symbol counter 70 operates in such a way that the lower stage 75 completes a whole number of count cycles in a symbol period, while the upper stage 74 advances by one each time the lower stage completes a count cycle. Thus, for the example of a system with approximately two thousand carriers and a clock frequency of 18·285714 MHz, the lower stage counts over the range 0 to 127, while the upper stage counts 0 to 32, 0 to 33, 0 to 35, or 0 to 39, depending on whether the guard interval is 1/32, 1/16, 1/8, or 1/4. The lower stage 75 simply counts the incoming clock pulses from input 72 and is not reset. It counts modulo-128, so cycles from 0 to 127 and then returns to 0. The separated symbol pulses, from input 71, sample the lower count, storing the value in the register 78. The output signal from the register 78 is interpreted as a signal for controlling the frequency of the clock oscillator 8, through an appropriately chosen loop filter, such that a value of 0 constitutes a large negative signal and a value of 127 constitutes a large positive signal. A value of 64 gives a zero signal, so that ultimately the loop will settle with a clock frequency such that the average position of the incoming symbol pulses coincides with value 64 in the lower stage of the counter. The lower stage 75 operates by effectively producing a ramp waveform. This waveform is identical regardless of the relative duration of the guard interval in the OFDM signal. The upper stage 74 synchronizes to the incoming symbol pulse, and this needs to be a clean and precise signal. This is why the pulse processor 60 is included. The upper stage 74 is reset by both the incoming symbol pulses and by the upper count completing its count range. Thus the symbol counter rapidly achieves a coarse lock through the action of the symbol pulse reset, while the precise lock position is determined more gradually as a result of the action of the clock loop moving the phase of the lower count to match the incoming symbol pulses. This avoids the lockup penalties of potentially having to move the symbol counter through a whole symbol to achieve the correct phase, while maintaining regular symbol pulses to start the Fourier transform process. The symbol period counter 70 has been described in the context of the system of Figure 2 which takes the product XY* as described above. However, the counter 70 could be used with other arrangements in which the symbol pulses are derived in other ways. While one example of the invention has been described, it will be appreciated that many variations may be made in the implementation of the invention.

Claims: Apparatus for synchronizing with a signal which comprises a succession of symbol periods T T each consisting of an active symbol period T S and a guard interval T G , the apparatus comprising: means (4) for forming a complex signal from the received signal; clock means (8) for generating clock signals for use in forming the complex signal; means (20-50) for forming symbol pulses from the input signal; synchronization means (9) coupled to receive the symbol pulses and the clock signals, the synchronization means being characterized by : a first recirculating counter (75) for counting clock signals; register means (78) for receiving the output of the first recirculating counter and for holding the count at a time determined by the receipt of the symbol pulses, the clock means being controlled by the held count; an OR gate (73) coupled to receive the incoming symbol pulses; a second recirculating counter (74) coupled to receive the output of the OR gate, the output of the second recirculating counter (74) being applied to a second input of the OR gate(73); and an AND gate (76) coupled to receive the outputs of the first recirculating counter and the second recirculating counter to provide synchronized symbol pulses. Apparatus according to claim 1, including a pulse shaping circuit (60) between the complex signal forming means and the synchronization means. Apparatus according to claim 1, including a Fourier transform circuit (5) coupled to receive the complex signal and the synchronized symbol pulses from the synchronizing means.

Inventors: CLARKE CHRISTOPHER K, ROBINSON ADRIAN PAUL, STOTT JONATHAN HIGHTON, CLARKE, CHRISTOPHER K., ROBINSON, ADRIAN PAUL, STOTT, JONATHAN HIGHTON, Clarke, Christopher K., British Broadcasting Corp., Robinson, Adrian Paul, British Broadcasting Corp, Stott, Jonathan Highton, British Broadcasting Corp
Applicants: BRITISH BROADCASTING CORP, BRITISH BROADCASTING CORPORATION
Application year: 1998
Main classification: H04L27
IPC codes: H04N7, H04N5, H04L27