Storage apparatus, data write-in method, and data read-out method

Abstract: The present invention prevents a damage concentration caused by a data erase/write-in to a particular cell, so as to increase a service life of a flash memory (2, 22). A CPU 17 determines whether a data which has been read out is a new one or a data having a reverse flag set (step S1 and S2). If the reverse flag is not set, a reverse flag is set (step S3), so as to reverse the bit of the data when writing the data into a flash memory (2, 22) (steps S4 and S6). If a reverse flag is set, the reverse flag is reset (step S5) and the data is written into the flash memory (2, 22) (step S6).

Description: The present invention relates to a storage apparatus and a storage method which can be preferably used for a NAND type flash memory. Conventionally, there has been suggested to use a flash memory as a storage apparatus for storing a data for computer application and data of a still camera, a video camera, and the like as well as an audio data such as music. This flash memory stores a data by an electric charge accumulated in a cell and erases a data on a block basis which is an erase unit. In the flash memory, prior to carrying out a data write-in, the cell should be in a clear state, i.e., data should have been erased by removing electrons from the cell. Then, a data is written into the flash memory when an electric charge is poured into the cell so as to reverse the cell state. As has been described above, the flash memory erases a data by removing electric charge from the cell on block basis. A large load is applied to the memory when electric charge is removed from the cell. Moreover, when writing a data, a large load is also applied to the cell into which electric charge is poured. Consequently, when a data re-write is repeated without carrying out bit reverse or when a data remained almost unchanged, there exist those cells to which electric charge is poured every time and cells to which no electric charge is poured. Thus, there arises a deviation in cell damage within a block, which in turn may shorten the block service life. Especially in the case of a management file or directory file where a partial modification is often carried out, repetition of a data write-in easily causes a cell damage deviation within the block. In contrast to this, there can be considered a flash memory where a data re-write is carried out in a different block. However, there arises a problem that a management configuration is required for using a different block each time a data is written, which results in a complicated configuration of the flash memory. An storage apparatus in which all features of the precharacterizing part of claim 1 are disclosed, is described in US-A-5 396 468. SUMMARY OF THE INVENTION It is an object of the present invention to provide a storage apparatus and a storage method which prevent concentration of a damage to a particular cell caused by a data erase/write-in, thus enabling to prolong a service life. This object is achieved by a storage apparatus and a storage method according to the enclosed independent claims. Advantageous features of the present invention are defined in the corresponding subclaims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a configuration of a memory (storage) apparatus according to the present invention. Fig. 2 is a block diagram showing a specific configuration of a memory card of the memory apparatus. Fig. 3 schematically shows a configuration of blocks serving as erase units in a flash memory provided in the memory card. Fig. 4 is a flowchart explaining operation executed when a data is written in the memory card. Fig. 5 is a flowchart explaining operation executed when a data is read out a data stored in the memory card. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Hereinafter, description will be directed to preferred embodiments of the present invention with reference to the attached drawings. As shown in Fig. 1, the present invention can be applied to a memory apparatus including a host computer 1 and a memory card 2. The host computer 1 writes a data into the memory card 2 and reads out a data stored in the memory card 2. More specifically, the host computer 1, as shown in Fig. 1, includes: a hard disc 11 for storing various data such as a still image data and an audio data; a RAM (random access memory) 12 for temporarily storing and reading out a data from the hard disc 11; a display interface (hereinafter, referred to as a display I/F) 13; a display 14 for displaying an image according to a data supplied via the display I/F 13; a serial interface (hereinafter, referred to as a serial I/F) 15 for carrying out a data transmission and reception to/from the memory card 2 via three data lines; a bus 16; and a CPU (central processing unit) 17 for controlling the entire system. The RAM 12, for example, temporarily stores a data from the hard disc 11 via the bus 16 and when required, supplies the data via the bus 16 to the serial I/F 15. The display 14 is supplied via the bus 16 and the display I/F 13 with the data read out from the hard disc 11 as well as a data from the memory card 2, so as to display a still image and a moving picture according to these data. The serial I/F 15, via the three data lines, transmits a data to the memory card 2 and receives data from the memory card 2. More specifically, via a first data line, the serial I/F 15 transmits a data to be written into the memory card 2 and a control data and receives a data which has been read out from the memory card 2. Via a second data line, the serial I/F 15 outputs a status signal State indicating a switched state according to a serial data DIO switching consisting of a data or a control data in the first data line. Furthermore, via a third data line, the serial I/F 15 transmits a serial clock SCLK when transmitting the aforementioned control data and data. The CPU 17 controls a data read out from the RAM 12 and the hard disc 11 and a data write-in to the RAM 12 and the like as well as control a data transmission and reception to/from the memory card 2. For example, the CPU 17 issues a register instruction used to determine whether an erroneous erase preventing switch of the memory card (which will be detailed later) is set to a write protect mode and issues a predetermined data write instruction with an address specification to the memory card 2. On the other hand, as shown in Fig. 2, the memory card 2 is connected to the aforementioned host computer 1 via two positive electrode DC power source line Vcc, a grounding line INT, a negative electrode DC power source Vss, and two reserved lines besides the aforementioned three data lines. Consequently, the memory card 2 is supplied via these DC power lines with power from the host computer 1 so as to enable to drive respective circuits inside the memory card 2. Here, the memory card 2, as shown in Fig. 2, includes: a control IC 21 for receiving a data and a control data from the aforementioned host computer 1; a flash memory 22 for storing a data; and an erroneous preventing switch 23 for preventing an erroneous erase of a data stored in the flash memory 22. The control IC 21 determines whether the erroneous erase preventing switch 23 is set to the write protect ON or OFF state before writing a data transmitted from the host computer 1, into the flash memory 22. Only if the write protect is in the OFF state, the data is written in the flash memory. The flash memory 22 is, for example, made from a NAND type flash memory. As shown in Fig. 3, in the flash memory 22, a data transmitted from the host computer 1 is stored in each of the blocks serving as erase units. Each of the blocks 0, 1, 2, ..., n consists of a data area for storing one page (512 bytes) of the data transmitted from the host computer 1 and a 16-bytes redundant area. In the redundant area, there is stored a management information for management of the data contained in the data area of the block. This management information, for example, includes: a block flag indicating a data write state; a linkage information indicating a linkage destination when a plurality of blocks constitute a single file; and a reverse flag indicating whether a data has been reversed when written in the data area. These management information items are read out by the host computer 1, so as to be used to determine a state of the flash memory 22 when carrying out a data read-out and write-in. Here, the control IC 21, more specifically, includes a serial/parallel - parallel/serial interface sequencer (hereinafter, referred to as S/P & P/S sequencer) 31; a page buffer for temporarily storing a data from the S/OP & P/S sequencer 31; a flash interface sequencer (hereinafter, referred to as a flash I/F sequencer) for supplying a data from the page buffer 32 to the flash memory 22; an ECC encoder/decoder 34 for carrying out an error correction; a command generator 46 for generating a predetermined control command; a configuration ROM (read only memory) 36 which contains a version information and the like; and an oscillator 37 for supplying a clock to respective circuits. The S/P & P/S sequencer 31 is connected, via the aforementioned first to the third data lines, to the serial I/F 15 of the host computer 1. consequently, the S/P & P/S sequencer 31 is supplied from the host computer 1 with a status signal State, a serial clock SCLK, and a serial data DIO consisting of a data and a control data. The S/P & P/S sequencer 31 converts the serial data DIO supplied from the host computer 1, into a parallel data in synchronization with the aforementioned serial clock SCLK. Among these parallel data, the S/P & P/S sequencer 31, for example, supplies the command data to the command generator 35 and the data to the pager buffer 32. The pager buffer 32 is a buffer memory for storing the data supplied from the S/P & P/S sequencer 31 on page basis. The data stored in the pager buffer 32 is added with an error correction sign by the ECC encoder/decoder 34. The pager buffer 32 supplies one-page data added with the error correction sign, via the flash I/F sequencer 33, to flash memories 22a to 22d. Thus, the data from the host computer 1 is written in the flash memories 22a to 22d. Moreover, a data read out from the flash memories 22a to 22d is supplied via the flash I/F sequencer 33 to the page buffer 32. The pager buffer 32 stores the data from the flash I/F sequencer 33. Here, the ECC encoder/decoder 34 executes an error correcting processing according to the error correction sign added to the data stored in the pager buffer 32. The pager buffer 32 reads out each page of data which has been subjected to the error correcting processing and supplies the data to the S/P & P/S sequencer 31. The S/P & P/S sequencer 31 converts the parallel data supplied from the pager buffer 32, into a serial data DIO and transmits the obtained serial data DIO to the aforementioned host computer 1. The command generator 35 generates a control command according to the control data form the S/P & P/S sequencer 31. For example, when the command generator 35 receives a read status register instruction for checking the operation state of the memory card 2, the command generator 35 determines a setting state of the erroneous erase preventing switch 23 and determines whether to write the data according to the setting state. Moreover, the command generator 35 generates a busy command (hereinafter, referred to as a busy signal) indicating a state when a data is being written into the flash memory 22 or a data is being read out from the flash memory 22 and transmits the busy signal via the S/P & P/S sequencer 31 to the host computer 1. When the data write-in or read-out is complete, the command generator 35 generates a ready command (hereinafter, referred to as a ready signal) indicating the end of the data write-in or read-out and transmits the ready signal via the s/P & P/S sequencer 31 to the host computer 1. The host computer recognizes the operation state of the memory card 2 by receiving the busy signal and the ready signal. The configuration ROM 36 contains information such as a version information and an initial setting value of the memory card 2. Consequently, when a connection is made between the host computer 1 and the memory card 2, the command generator 35 firstly reads out via the S/P & P/S sequencer 31 the aforementioned version information from the configuration ROM 36 and according to this information, generates a predetermined command, so as to execute a predetermined initialization of the memory card 2. In the memory apparatus having the aforementioned configuration, the host computer 1 reads out in advance a management information of the flash memory 22 of the memory card 2 and stores this information in the RAM 12. When writing a data in the memory card 2, the host computer 1 uses the aforementioned management information to execute the processing of steps S1 to S6 shown in Fig. 4. In step S1, the CPU 17 of the host computer 1 determines whether a data which has been read out from the hard disc 11, for example, so as to be transmitted to the memory card is a new data. If the data is a new data, control is passed to step S5. If the data is not a new data, control is passed to step S2. That is, the CPU 17 determines whether the data is a completely novel data or a data similar to a data transmitted to the memory card 2 and partially modified. If the data is determined to be a new data, control is passed to step S5 and if the data is similar to an old data, control is passed to step S2. In step S2, the CPU 17 determines whether a reverse flag is set in respective blocks to be used for a data write-in. If the reverse flag is set, control is passed to step S5, and if not set, control is passed to step S3. In step S3, the CPU 17 via the serial I/F 15 and the control IC 21 of the memory card 2, sets a reverse flag in the redundant area of the flash memory 22 and stores a data to be transmitted, for example, in the RAM 12 from the hard disc 11, passing control to step S4. On the other hand, when step 1 determines that the data is determined to be new and when step 2 determines that a reverse flag is set, in step S5 the CPU 17, via the control IC 21 of the memory card 2, resets the verse flag in the redundant area of the flash memory 22 and stores a data to be transmitted, for example, in the RAM 12 from the hard disc 11, passing control step S6. In step S6, the CPU 17 transmits a data stored in the RAM 12 and a management information to be updated by this data, to the memory card 2 via the serial I/F 15, and writes these data and the like in the flash memory, thus completing the processing. As has been described above, when repeatedly writing a similar data such as a data partially modified, the host computer 1 executes bit reverse/non-reverse at each data write-in of such a data. This prevents concentration of cell damage to a particular cell in the flash memory caused by a data write-in and erase, averaging the cell damage, which in turn increases the service life of the flash memory 22. Moreover, when the host computer 1 reads out a data stored in the memory card 2, the host computer 1 uses a management information stored in the RAM 12 so as to execute a processing of steps S11 to S13 shown in Fig. 5. In step S11, the CPU 17 of the host computer 1 determines whether a reverse flag stored in the RAM 12 is set. If the reverse flag is set, control is passed to step S12. If not, control is passed to step S13. In step S12, the CPU 17, via the serial I/F 15 and control IC 21 of the memory card 2, reads out a data from the flash memory 22, stores it in the RAM 12, and reverses the bit of this data, thus completing the read-out processing. In step S13, the CPU 17, via the serial I/F 15 and the control IC 21 of the memory card 2, simply reads out a data from the flash memory 22, thus completing the read-out processing. As has been described above, when the reverse flag is set, the host computer 1 reads out a data from the flash memory 22 and reverses the bit; and when no reverse flag is set, the host computer 1 directly reads out a data from the flash memory 22. Thus, it is possible to read out a data written in the flash memory 22 through the bit reverse-non-reverse processing. It should be noted that the present invention is not to be limited to the aforementioned embodiment but can be modified in design within the scope of the technical concept described in the Claims. For example, as the host computer 1, it is possible to apply a still camera and a video camera. In such a case, the memory card 2 is controlled by the still camera or the like, so that an image data is written in. Moreover, as the host computer 1, it is possible to apply a reproduction apparatus capable of reading out an audio data of a music stored in the memory card 2 and outputting a sound. In this case, a data transfer rate between the host computer 1 and the memory card 2 is much faster than a data read-out speed from a magnetic tape and a CD (compact disc) and it is possible, for example, to carry out at a high speed a setting of a music start.

Claims: A storage apparatus comprising: interface (15) for sending/receiving data from a stora ge means (22), said storage means (22) storing data divided into a plurality of blocks and a reverse flag indicating whether the bits of said data are reversed for each of said blocks; and control means (17) for controlling said storage means (22), wherein said control means (17) determines whether in a block said reverse flag is set, sets or resets said reverse flag of said block and writes data into said block according to the flag status of said block, characterised in that the control means (17) further determines whether the data to be written into a block and the data previously stored in said block are similar or same (S1) and the control means (17) further proceeds according to the following: if said control means (17) determines that data to be written into a block and the data previously stored in said block are similar or same (S1), and the reverse flag of said block indicates that bits are reversed (S2), then said reverse flag is reset (S5) and said data are written into said block (S6) , if said control means (17) determines that the data to be written into a block and the data previously stored in said block are similar or same (S1), and the reverse flag of said block indicates that bits are not reversed (S2), then the reverse flag is set (S3) and said data with bits reversed are written into said block (S4, S6), if said control means (17) determines that data to be written into a block and the data previously stored in said block are not same or similar (S1), then a reverse flag indicating no bit reversed is set (S5) and said data are written into said block (S6). A storage apparatus as claimed in Claim 1, wherein if data to be written into a block are not the data previously stored in said block (S1), said control means (17) determines that said data to be written into said block and the data previously stored in said block are not similar or same (S1). A storage apparatus as claimed in Claim 1 or 2, wherein if data to be written into a block are the data partially modified previously stored in said block (S1), said control means (17) determines that said data to be written into said block and the data previously stored in said block are similar (S1). A storage apparatus as claimed in anyone of Claims 1 to 3, wherein said control means (17) controls a read-out of data from said storage means (22), wherein if a reverse flag of a block to which data which have been read out from said control means (17) belongs indicates that the bits are reversed (S11), said control means (17) controls to reverse the bits of said data which have been read out (S12). A storage method comprising: a step for storing data divided into a plurality of blocks and a reverse flag indicating whether bits of said data are reversed for each of said blocks, characterised in that the control means (17) further determines whether the data to be written into a block and the data previously stored in said block are similar or same (S1) and the control means (17) further proceeds according to the following: if data to be written into a block and the data previously stored in said block are similar or same (S1), and the reverse flag of said block indicates that bits are reversed (S2), then said reverse flag is reset (S5) and said data are written into said block (S6), if that the data to be written into a block and the data previously stored in said block are similar or same (S1), and the reverse flag of said block indicates that bits are not reversed (S2), then the reverse flag is set (S3) and said data with bits reversed are written into said block (S4, S6), if data to be written into a block and the data previously stored in said block are not same or similar (S1), a reverse flag indicating no bit reversed is set (S5) and said data are written into said block (S6). A storage method as claimed in Claim 5, wherein if data to be written into a block are not the data previously stored in said block (S1), it is determined that said data to be written into said block and the data previously stored in said bl ock are not similar or same (S1). A storage method as claimed in Claim 5 or 6, wherein if data to be written into a block are the data partially modified previously stored in said block (S1), it is determined that said data to be written into said block and the data previously stored in said block are similar (S1). A storage method as claimed in anyone of Claims 5 to 7, wherein when data stored into a block are read-out, a control (S11) is carried out to reverse the bits of said data which has been read out if a reverse flag of said block indicates that the bits of said block are reversed.

Inventors: SASSA AKIRA, SUZUKI YUICHI, SASSA, AKIRA, SUZUKI, YUICHI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1998
Main classification: G11C16
IPC codes: G06F12, G11C16