SHIELDED INTEGRATED CIRCUIT CAPACITOR

Abstract: An integrated circuit (IC) capacitor offers reduced sensitivity to parasitic capacitance, reduced-size, and increased noise immunity, such as for use in digital-to-analog converters (DACs), analog-to-digital converters (ADCs), switched-capacitor filters, and other IC circuits. The capacitor includes a first polysilicon layer, a superjacent second polysilicon layer separated from the first polysilicon layer by an insulator, and an overlying metal layer separated from the second polysilicon layer by an insulator. The metal layer provides a shield that is connected to a known voltage, or to the first polysilicon layer. When connected to the first polysilicon layer, the overlying metal layer also provides additional parallel capacitance, thereby reducing the integrated circuit area of the capacitor. In one example, the overlying metal layer is a second metal layer that is also used, together with a first metal layer, for interconnecting IC components.

Description: SHIELDED INTEGRATED CIRCUIT CAPACITOR Technical Field of the Invention This invention relates generally to integrated circuits, and particularly, but not by way of limitation, to a shielded-integrated circuit capacitor that is less sensitive to parasitic capacitances from overlying dielectrics. Background of the Invention The implementation of complex signal processing functionality on an integrated circuit requires a variety of circuit elements, such as transistors, resistors, and capacitors. Some integrated circuit fabrication processes provide a "precision" capacitor for uses including switched-capacitor filters, digital-to- analog converters (DACs), and analog-to-digital converters (ADCs), such as in telecommunications, implantable medical devices, and other applications. One integrated circuit capacitor includes separately formed conductive polysilicon layers having an insulator interposed therebetween. The first-formed polysilicon layer is referred to as the bottom plate of the capacitor, and the second-formed polysilicon layer is referred to as the top plate of the capacitor. The bottom plate is formed over the integrated circuit semiconductor substrate, and is separated therefrom by an insulator. Connection is made to each of the bottom and top plates by contact and metal layers. A protective passivation layer is formed over the top plate of the capacitor and the entire integrated circuit. The above-described capacitor structure includes an unwanted parasitic capacitor, consisting of the bottom plate and substrate as parasitic capacitor terminals, and the insulator between the bottom plate and substrate as a parasitic capacitor dielectric. The unwanted parasitic capacitor, which is referred to as the bottom plate parasitic capacitor, can have a capacitance value that is approximately 10% of the capacitance value of the desired capacitor. As a result, designers of switched-capacitor integrated circuits adopt circuit designs that are insensitive to the bottom plate parasitic capacitor. The above-described capacitor structure also includes a second unwanted parasitic capacitor, consisting of the top plate as a first parasitic capacitor terminal and at least one other circuit node, such as the substrate, as a second parasitic capacitor terminal. Passivation and other insulating layers form a second parasitic capacitor dielectric. The second unwanted parasitic capacitor, which is referred to as a top plate parasitic capacitor, results from electric fields originating from the top plate, passing through the superjacent dielectric passivation layer and the air above the passivation layer, and terminating at the substrate or other circuit nodes. Although the dielectric passivation layer can have a significant permitivitty, the air above the passivation layer has a low permitivitty. As a result, the top plate parasitic capacitor typically has a capacitance value that is relatively small, and circuit designs may be relatively unaffected by the top plate parasitic capacitor. However, manufacturers of electronic devices using integrated circuits often require an additional coating over the passivation layer of the integrated circuit die. Such die coatings provide encapsulation of the integrated circuit die, resulting in numerous practical advantages. For example, a die coating may provide opacity so that the underlying semiconductor integrated circuit is unaffected by incident light, such as during testing of the integrated circuit or otherwise. In another example, the die coating may be used to adhere other electronic components of an electronic system to the integrated circuit die. Unfortunately, the materials used for integrated circuit die coatings (e.g., epoxy, polyamide, etc.) often have a large permitivitty, thereby increasing the value of the unwanted top plate parasitic capacitor. These die coatings are relatively thick and replace the low-permitivitty air space above the die. As a result, the electric fields of the top plate parasitic capacitor pass through the superjacent dielectric passivation layer and the die coating above the passivation layer. Since both the passivation layer and die coating have a high permitivitty, the capacitance value of the unwanted top plate parasitic capacitor increases, resulting in deleterious effects on circuit operation. For example, the increased top plate parasitic capacitance can introduce nonlinearity in a digital-to-analog converter. Furthermore, since the die coating process may not be well-controlled, the die coating thickness may vary between capacitors on the same integrated circuit die as well as between different integrated circuit die. Such variations in die coating thickness introduce variations in top plate parasitic capacitance values. The increased top plate parasitic capacitance values and variations thereof are difficult to correct for using traditional digital-to-analog converter calibration and compensation techniques. For these reasons, and other reasons that will become apparent upon reading the following detailed description of the invention, there is a need for providing an integrated circuit capacitor that is insensitive to parasitic capacitances, particularly those parasitic capacitors introduced by overlying dielectric layers. There is also a need for reducing the integrated circuit die area of the capacitor. There is a further need for improving the operation of digital- to-analog converters, analog-to-digital converters, switched-capacitor filters, and other signal processing circuits, by reducing the sensitivity of such circuits to parasitic capacitances, signal crosstalk, and external noise. Summary of the Invention The present invention provides an integrated circuit capacitor for use in digital-to-analog converters, analog-to-digital converters, switched-capacitor filters, and other integrated circuit signal processing circuits. According to one aspect of the invention, the capacitor is relatively insensitive to unwanted parasitic capacitances, including such unwanted parasitic capacitances resulting from overlying dielectrics. Another aspect of the invention provides a reduced- size capacitor. Yet another aspect of the invention provides a capacitor having increased immunity to signal crosstalk and external noise. The integrated circuit capacitor includes a first, second, and third conductors and first, second, and third insulators. The first conductor is formed on a substrate, but separated from the substrate by a first insulator. The second conductor, which provides a second terminal of the capacitor, is separated from the first conductor by a second insulator. The third conductor is separated from the second conductor by a third insulator. In one embodiment, the first conductor is electrically coupled to the third conductor for providing a first terminal of the capacitor. Another embodiment of the present invention provides an integrated circuit, formed on a substrate. The integrated circuit includes a plurality of transistors and a capacitor, having first and second terminals and shield. A first polysilicon layer, forms gate regions of the transistors and the first terminal of the capacitor. A first metal interconnection layer interconnects ones of the transistors. A second metal interconnection layer is formed outwardly from the first metal interconnection layer. Together with the first metal interconnection layer, the second metal interconnection layer interconnects particular transistors. The second metal interconnection layer also forms the shield of the capacitor. A second polysilicon layer is interposed between at least part of the first polysilicon layer and the shield. The second polysilicon layer is separated from each of the first polysilicon layer and the shield by an insulator. The second polysilicon layer forms the second terminal of the capacitor. Another aspect of the present invention includes a method of providing an integrated circuit capacitance between first and second terminals. In one embodiment, a first conductor is formed, separated from the substrate by a first insulator. A second conductor is formed, for providing the second terminal. The second conductor is separated from the first conductor by a second insulator. A third conductor is formed, separated from the second conductor by a third insulator. In one embodiment, the first and third conductors are electrically coupled to each other for providing the first terminal. Another aspect of the present invention includes a method of fabricating an integrated circuit. In one embodiment, a first polysilicon layer is formed. Gate regions of a plurality of transistors and the first terminal of a capacitor are formed from the first polysilicon layer. A second polysilicon layer is formed outward from the first polysilicon layer. A second terminal of the capacitor is formed from the second polysilicon layer. First and second metal layers are respectively formed. Ones of the transistors are interconnected using the first and second metal layers. A capacitor shield is formed, outward from the second terminal of the capacitor, using the second metal interconnection layer. In one embodiment, the shield is electrically coupled to the first terminal of the capacitor. Another aspect of the invention includes several methods of using an integrated circuit capacitor. In one embodiment, in which the capacitor has a first terminal, a second terminal formed outward from the first terminal, and a shield formed outward from the second terminal, a first voltage is provided to each of the first terminal and the shield, and a second voltage is provided to the second terminal. In another embodiment, in which the capacitor has a first terminal, a second terminal formed outward from the first terminal, and a shield formed outward from the second terminal, a first voltage is provided to the first terminal and a second voltage is provided to each of the second terminal and the shield. In a further embodiment, in which the capacitor has a first terminal, a second terminal formed outward from the first terminal, and a shield formed outward from the second terminal, a first voltage is provided to the first terminal, a second voltage is provided to the second terminal, and a stable reference voltage is provided to the shield. As described in the following detailed description of the invention, various embodiments of the integrated circuit capacitor of the present invention offers reduced sensitivity to parasitic capacitance, reduced-size, and increased noise immunity. Brief Description of the Drawings In the drawings, like numerals describe substantially similar components throughout the several views. Figure 1 is a combined schematic and cross-sectional view, labeled prior art, illustrating a conventional integrated circuit capacitor. Figure 2 is a combined schematic and cross-sectional view illustrating generally one embodiment of a capacitor according to the present invention. Figures 3A, 3B, 3C, and 3D are schematic diagrams illustrating generally several embodiments of capacitors according to the present invention. Figure 4A is a cross-sectional view illustrating generally one embodiment of a capacitor according to the present invention and its environment. Figure 4B is a cross-sectional view illustrating generally one embodiment of a capacitor according to the present invention together with a transistor fabricated on the same integrated circuit. Figures 5A and 5B are plan views illustrating generally several embodiments of portions of a capacitor according to the present invention. Figures 6A and 6B are graphs of error voltage (in millivolts) vs. code value for a digital-to-analog converter (DAC) using a prior art capacitor. Figures 7A and 7B are graphs of error voltage (in millivolts) vs. code value for a DAC using one embodiment of a capacitor according to the present invention. Figures 8A and 8B are graphs of error voltage (in milliVolts) vs. code value for a DAC using one embodiment of a capacitor according to the present invention. Detailed Description of the Invention In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. The present invention provides an integrated circuit capacitor for use in digital-to-analog converters, analog-to-digital converters, switched-capacitor filters, and other signal processing circuits. According to one aspect of the invention, the capacitor is relatively insensitive to unwanted parasitic capacitances, including such unwanted parasitic capacitances resulting from overlying dielectrics. Another aspect of the invention provides a reduced-size capacitor. Yet another aspect of the invention provides a capacitor having increased immunity to signal crosstalk and external noise. Other advantages will also become apparent upon reading the following detailed description of the invention. Figure 1 is a combined schematic and cross-sectional view, labeled prior art, illustrating a conventional integrated circuit capacitor 150. A first terminal of capacitor 150 is provided by a polysilicon bottom plate 110, which is formed over substrate 100. Bottom plate 110 is separated from substrate 100 by insulator 105. A second terminal of capacitor 150 is provided by a polysilicon top plate 120, which is formed over bottom plate 110. Top plate 120 is separated from bottom plate 110 by insulator 115. A passivation layer 135 is formed over top plate 120. An optional die coating, such as encapsulant 140, is formed over passivation layer 135. Figure 1 also schematically illustrates capacitor 150, the above-described unwanted bottom plate parasitic capacitance 155, and the above-described unwanted top plate capacitance 160. The unwanted top plate capacitance 160 is between top plate 120 and any other circuit node or nodes. As described above, the unwanted top plate capacitance 160 exists regardless of whether or not encapsulant 140 is present, but its capacitance value increases when high permitivitty encapsulant 140 is present rather than low permitivitty air. The effects of bottom plate parasitic capacitance 155 can be minimized by known circuit design techniques. Figure 2 is a combined schematic and cross-sectional view illustrating generally by way of example, but not by way of limitation, one embodiment of a portion of the present invention and its environment. Figure 2 includes a semiconductor or other substrate 200. In one embodiment, substrate 200 is a lightly-doped p " bulk silicon semiconductor. In other embodiments, substrate 200 is a semiconductor-on-insulator (SOI) or a lightly-doped epitaxial layer formed on an underlying more heavily doped semiconductor, or any other suitable substrate. A first insulator 205 is formed on substrate 200. In one embodiment, first insulator 205 includes thermally grown silicon dioxide. A first conductor 210 is formed on first insulator 205. In one embodiment, first conductor 210 includes conductively doped polycrystalline silicon (polysilicon). A second insulator 215 is formed on first conductor 210. In one embodiment, second insulator 215 includes silicon dioxide. A second conductor 220 is formed on second insulator 215. In one embodiment, second conductor 220 includes conductively doped polysilicon. Other layers are formed outwardly from second conductor 220, including, but not limited to, third insulator 225. In one embodiment, third insulator 225 includes insulating silicon dioxide. A third conductor 230 (also referred to as a shield) is formed over third insulator 225. In one embodiment, third conductor 230 includes a metal, such as aluminum. A protective passivation layer 235 is formed over third conductor 230. In one embodiment, passivation layer 235 includes silicon dioxide. A die coating such as encapsulant 240 is optionally formed over passivation layer 235. Various embodiments of encapsulant 240 include epoxies, polyamide, or any other die coating. One aspect of the present invention provides capacitors 250A and 250B. First conductor 210, second insulator 215, and second conductor 220 respectively provide a first terminal, a capacitor dielectric, and a second terminal of capacitor 250A. Second conductor 220, third insulator 225, and third conductor 230 respectively provide a first terminal, a capacitor dielectric, and a second terminal of capacitor 250B. In one embodiment, capacitors 250 A and 250B are used in parallel to form a reduced integrated circuit area capacitor 250 that is insensitive to any parasitic capacitance 260 resulting from overlying dielectric layers such as passivation layer 235 or encapsulant 240, or both. In one such embodiment, third conductor 230 and first conductor 210 are electrically interconnected, as described below. In another such embodiment, third conductor 230 and first conductor 210 are not electrically interconnected, but are instead driven to receive approximately the same voltage, such as by an amplifier or voltage follower circuit, also described below. The unwanted top plate parasitic capacitor 160 accompanying prior art capacitor 150 does not affect capacitor 250 according to the present invention. More particularly, the problematic top plate parasitic capacitor 160 to substrate 100 of Figure 1, which results from overlying dielectric layers, is advantageously transformed in Figure 2 such that it appears in parallel with, and as part of, the desired capacitor 250 by providing a third conductor 230 that is electrically interconnected to, or driven to the same voltage as, first conductor 210. This also increases the effective capacitance value of capacitor 250, thereby requiring less integrated circuit area to obtain a particular capacitor value. In another embodiment, third conductor 230 is not electrically interconnected to first conductor 210, but third conductor 230 is instead driven to a known voltage such that underlying capacitor 250A is shielded from parasitic capacitance 260 from overlying passivation layer 235 or encapsulant 240. Also, top plate 120 of prior art capacitor 150 is susceptible to noise resulting from capacitive coupling (crosstalk) from nearby integrated circuit wiring lines or external noise, such as received from other electronic components in the operating environment of the integrated circuit. Many complementary metal-oxide-semiconductor (CMOS) integrated circuit designs permit only one terminal of the capacitor to be driven by a low impedance voltage source, requiring the other terminal of the capacitor to be electrically coupled to a high input impedance amplifier. In order to minimize any capacitive voltage division resulting from the parasitic bottom plate capacitance 155, bottom plate 110 is typically driven by the low impedance voltage source, leaving top plate 120 electrically coupled to the high impedance node. As a result, top plate 120 is particularly sensitive to noise as well as to capacitive voltage division resulting from parasitic top plate capacitance 160. By contrast, the capacitor 250 allows each of third conductor 230 and first conductor 210 to be driven by a relatively low impedance voltage source. If required by a particular circuit design, second conductor 220 is electrically coupled to a high impedance node, and is effectively shielded from crosstalk and external noise by electrically driven third conductor 230. Thus, the present invention advantageously provides a capacitor 250 or 250 A having increased noise immunity. Figures 3A, 3B, 3C, and 3D are schematic diagrams that illustrate generally, by way of example, but not by way of limitation, several embodiments of portions of the present invention. In Figure 3 A, third conductor 230 and first conductor 210 are electrically interconnected for providing a first terminal 300 of capacitor 250. Second conductor 220 is electrically interconnected for providing a second terminal 305 of capacitor 250. This embodiment provides reduced capacitor area, increased immunity to parasitic capacitances from overlying dielectrics, and reduced susceptibility to crosstalk and external noise. In Figure 3B, third conductor 230 and first conductor 210 are each electrically interconnected to approximately the same voltage for providing a first terminal 300 of capacitor 250. In one embodiment, a low impedance voltage source, such as voltage follower 310, provides the voltage to one or both of third conductor 230 and first conductor 210. Second conductor 220 is electrically interconnected for providing a second terminal 305 of capacitor 250. This embodiment also provides reduced capacitor area, increased immunity to parasitic capacitances from overlying dielectrics, and reduced susceptibility to crosstalk and external noise. In Figure 3C, first conductor 210 is electrically interconnected for providing a first capacitor terminal 300 of capacitor 250A. Second conductor 220 provides a second capacitor terminal 305 of capacitor 250A. Third conductor 230 provides a shield that is driven to approximately the same voltage as second conductor 220, such as by voltage follower 310. This embodiment provides increased immunity to parasitic capacitances from overlying dielectrics, and reduced susceptibility to crosstalk and external noise. In Figure 3D, first conductor 210 is electrically interconnected for providing a first capacitor terminal 300 of capacitor 250A. Second conductor 220 provides a second capacitor terminal 305 of capacitor 250 A. Third conductor 230 provides a shield that is driven to a ground voltage or any other stable reference voltage. This embodiment provides increased immunity to parasitic capacitances from overlying dielectrics, and reduced susceptibility to crosstalk and external noise. Figure 4A is a cross-sectional view illustrating generally by way of example, but not by way of limitation, one embodiment of a portion of the present invention and its environment. In Figure 4A, third insulator 225 is separately formed as insulator 225A and insulator 225B. First, insulator 225A is formed over second conductor 220. Contacts 400 are selectively formed through insulator 225A, and any underlying portions of second insulator 215. A conductive layer, such as metal layer 405, is formed over insulator 225A and within contacts 400. Metal layer 405 is selectively removed to provide electrical interconnections to first conductor 210 and second conductor 220. In one embodiment, metal layer 405 also forms electrical interconnections between transistors and other circuit components fabricated on the same integrated circuit. Insulator 225B is formed on metal layer 405. Third conductor 230 is formed on insulator 225B, and selectively patterned. In one embodiment, third conductor 230 is a metal layer that, together with metal layer 405, also provides electrical interconnections between transistors and other circuit components fabricated on the same integrated circuit. In one embodiment, in which first conductor 210 and third conductor 230 are electrically interconnected, via 410 is selectively formed through insulator 225B before third conductor 230 is formed, such that a portion of third conductor 230 fills via 410. In embodiments in which first conductor 210 and third conductor 230 are not electrically interconnected (See e.g.. Figure 3B, 3C, and 3D), via 410 is omitted. Figure 4B is a cross-sectional view illustrating generally by way of example, but not by way of limitation, one embodiment of a portion of a capacitor 440 according to the present invention on the same integrated circuit with other transistors such as field-effect transistor 450. Transistor 450 includes source 455 and drain 460 diffusions and polysilicon gate 465. In this embodiment, polysilicon gate 465 is formed from the same layer as first conductor 210. Transistor 450 is interconnected with other transistors, such as by first metal layer 405, vias 410, and metal layer 470. In this embodiment, metal layer 470 is formed from the same layer as third conductor 230. Figures 5A and 5B are plan views that illustrate generally, by way of example, but not by way of limitation, several embodiments of portions of a capacitor according to the present invention. In Figure 5A, first conductor 210 is patterned into a polygon, such as a square having an extension for forming a contact 400 thereto. Second conductor 220 is patterned into a polygon, such as a square, that is substantially enclosed by the polygon of first conductor 210. Third conductor 230 is patterned into a polygon, such as a square. In one embodiment, the polygon of third conductor 230 is in substantial registration with the polygon of first conductor 210, with only a slight overlap or underlap thereto. Third conductor 230 includes an extension for filling underlying via 410. In one embodiment, separately patterned portions of metal layer 405 provide electrical interconnections, such as between via 410 and the contact 400 to first conductor 210, and to second conductor 220 through contact the 400 thereto. Figure 5B is similar to Figure 5A, with one difference being that in Figure 5B, the patterned polygon formed by second conductor 220 includes an extension for forming a contact 400 thereto, wherein the contact 400 is outside the areas enclosed by the polygons provided by first conductor 210 and third conductor 230. Figures 5A and 5B provide useful illustrative examples, but other arrangements of forming a capacitor according to the present invention are also possible. Figures 5A and 5B illustrate, by way of example, unit capacitors, such as are typically used in switched-capacitor integrated circuit designs. Other capacitance values are obtained by interconnecting ones of the unit capacitors in parallel. However, it is understood that the above-described techniques of the present invention are not limited to application in unit capacitors, but are also applicable to any arbitrarily-shaped integrated circuit capacitor. It is also understood that in certain embodiments of practicing the invention, a unitary portion of third conductor 230 is shared by multiple unit capacitors, whether or not such unit capacitors are wired in parallel, such as, for example, in the circuit embodiment illustrated in Figure 3D. In other embodiments of practicing the invention, a uniquely formed portion of third conductor 230 is provided for each unit capacitor, such as, for example, in the circuit embodiment illustrated in Figure 3A. Figures 6A and 6B are graphs of error voltage (in milliVolts) vs. code value for an 8-bit (e.g., having 0 - 255 digital codes) subranging switched- capacitor digital-to-analog converter (DAC) using the prior art capacitor 150 of Figure 1. In Figure 6 A, the solid lines, labeled 600, illustrate data from 5 different DACs, none of which are coated with a die coating. In Figure 6B, the solid lines, labeled 605, illustrate data from 3 of the same DACs, none of which are coated with a die coating. The dashed lines, labeled 610, illustrate data from the other 2 DACs, each of which are coated with a thermal plastic encapsulant 140. As seen in Figures 6A and 6B, the absolute error voltage can be as large as approximately 60 mV for the uncoated parts illustrated by lines 600 and 605, and as large as approximately 120 mV for the coated parts illustrated by lines 610. Figures 7A and 7B are graphs of error voltage (in milliVolts) vs. code value for an 8-bit (e.g., having 0 - 255 digital codes) subranging switched- capacitor digital-to-analog converter (DAC) using the capacitor 250 of Figure 2 according to one aspect of the present invention. In Figures 7A and 7B, the DAC uses unit capacitors 250 that are similar to the unit capacitor illustrated in Figure 5B. In Figure 7A, the solid lines, labeled 700, illustrate data from 10 different DACs, none of which are coated with a die coating. In Figure 7B, the solid lines, labeled 705, illustrate data from the same 10 DACs after coating with a conductive epoxy die coating, which ordinarily induces more parasitic capacitance than the thermal plastic die coating of Figure 6B. As seen in Figures 7A and 7B, the absolute error voltage can be as large as approximately 50 mV for the coated parts illustrated by lines 705, which do not differ significantly from uncoated parts illustrated by lines 700. Figures 8A and 8B are graphs of error voltage (in milliVolts) vs. code value for an 8-bit (e.g., having 0 - 255 digital codes) subranging switched- capacitor digital-to-analog converter (DAC) using the capacitor 250 of Figure 2 according to the present invention. In Figures 8A and 8B, the DAC uses unit capacitors 250 that are similar to the unit capacitor illustrated in Figure 5B, except that the polygon formed by third conductor 230 is shared in common by all unit capacitors in the DAC and electrically coupled to a reference voltage (e.g., grounded). In Figure 8A, the solid lines, labeled 800, illustrate data from 10 different DACs, none of which are coated with a die coating. In Figure 8B, the solid lines, labeled 805, illustrate data from the same 10 DACs after coating with a conductive epoxy die coating, which ordinarily induces more parasitic capacitance than the thermal plastic die coating of Figure 6B. As seen in Figures 8A and 8B, the absolute error voltage can be as large as approximately 40 mV for the coated parts illustrated by lines 805, which do not differ significantly from the uncoated parts illustrated by lines 800. It should be noted that in Figures 8A and 8B, data from only approximately 160 of the 256 digital codes was obtainable. Conclusion As described above, the present invention provides, among other things, an integrated circuit capacitor for use in digital-to-analog converters, analog-to- digital converters, switched-capacitor filters, and other signal processing circuits. According to one aspect of the invention, the capacitor is relatively insensitive to unwanted parasitic capacitances, including such unwanted parasitic capacitances resulting from overlying dielectrics. Another aspect of the invention provides a reduced-size capacitor. Yet another aspect of the invention provides a capacitor having increased immunity to signal crosstalk and external noise. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims: WHAT IS CLAIMED IS: 1. An integrated circuit capacitor formed on a substrate, the capacitor comprising: a first insulator, formed on the substrate; a first conductor, separated from the substrate by the first insulator; a second insulator, formed on the first conductor; a second conductor, for providing a second terminal of the capacitor, wherein the second conductor is formed on the second insulator and is separated from the first conductor by the second insulator; a third insulator, formed on the second conductor; and a third conductor, formed on the third insulator and separated from the second conductor by the third insulator. 2. The capacitor of claim 1, wherein the first conductor is electrically coupled to the third conductor for providing a first terminal of the capacitor. 3. The capacitor of claim 1, wherein at least one of the first and second conductors comprises polysilicon. 4. The capacitor of claim 1, wherein the third conductor comprises a metal. 5. The capacitor of claim 1, wherein at least one of the first, second, and third insulators comprises silicon dioxide. 6. An integrated circuit capacitor, formed on a semiconductor substrate, the capacitor comprising: a field oxide, formed on the substrate; a polysilicon first conductor, formed on the field oxide; a gate oxide, formed on the polysilicon first conductor; a polysilicon second conductor, formed on the gate oxide; an interlayer third insulator, formed on the polysilicon second conductor; and a metal shield, formed on the interlayer third insulator. 7. The capacitor of claim 6, further comprising an electrical interconnector between the metal shield and the polysilicon first conductor. 8. The capacitor of claim 7, wherein the electrical interconnector between the metal shield and the polysilicon first conductor comprises: a via, extending at least partially through the interlayer third insulator; a contact, extending at least partially through the gate oxide; and a metal conductor, electrically connected to the metal shield through the via, and electrically connected to the polysilicon first conductor through the contact. 9. An integrated circuit, formed on a substrate, the integrated circuit comprising: a plurality of transistors; a capacitor, having first and second terminals and shield; a first polysilicon layer, forming gate regions of the transistors and the first terminal of the capacitor; a first metal interconnection layer, interconnecting ones of the transistors; a second metal interconnection layer, formed outwardly from the first metal interconnection layer, and, together with the first metal interconnection layer, interconnecting ones of the transistors, wherein the second metal interconnection layer forms the shield of the capacitor; and a second polysilicon layer, interposed between at least part of the first polysilicon layer and the shield, the second polysilicon layer separated from each of the first polysilicon layer and the shield by an insulator, and the second polysilicon layer forming the second terminal of the capacitor. 10. The integrated circuit of claim 9, wherein the shield is electrically coupled to the first terminal of the capacitor. 11. The integrated circuit of claim 9, wherein the shield is electrically coupled to receive a reference potential. 12. The integrated circuit of claim 9, wherein the shield is electrically coupled to the substrate. 13. The integrated circuit of claim 9, wherein each of the first terminal of the capacitor and the shield are electrically coupled for receiving approximately equal voltages. 14. The integrated circuit of claim 9, wherein each of the second terminal of the capacitor and the shield are electrically coupled for receiving approximately equal voltages. 15. A method of providing an integrated circuit capacitance between first and second terminals, the method comprising: forming a first conductor, separated from the substrate by a first insulator; forming a second conductor, for providing the second terminal, wherein the second conductor is separated from the first conductor by a second insulator, forming a third conductor, separated from the second conductor by a third insulator; and electrically coupling the first and third conductors for providing the first terminal. 16. A method of fabricating an integrated circuit, the method comprising: forming a first polysilicon layer; forming gate regions of a plurality of transistors and the first terminal of a capacitor from the first polysilicon layer; forming a second polysilicon layer, outward from the first polysilicon layer; forming a second terminal of the capacitor from the second polysilicon layer; forming a first metal layer; forming a second metal layer; interconnecting ones of the transistors using the first and second metal layers; and forming a capacitor shield, outward from the second terminal of the capacitor, using the second metal interconnection layer. 17. The method of claim 16, further comprising interconnecting the shield and the first capacitor terminal. 18. A method of using an integrated circuit capacitor having a first terminal, a second terminal formed outward from the first terminal, and a shield formed outward from the second terminal, the method comprising: providing a first voltage to each of the first terminal and the shield; and providing a second voltage to the second terminal. 19. The method of claim 18, wherein providing a first voltage to each of the first terminal and the shield includes electrically interconnecting each of the first terminal and the shield. 20. A method of using an integrated circuit capacitor having a first terminal, a second terminal formed outward from the first terminal, and a shield formed outward from the second terminal, the method comprising: providing a first voltage to the first terminal; and providing a second voltage to each of the second terminal and the shield. 21. A method of using an integrated circuit capacitor having a first terminal, a second terminal formed outward from the first terminal, and a shield formed outward from the second terminal, the method comprising: providing a first voltage to the first terminal; providing a second voltage to the second terminal; and providing a stable reference voltage to the shield.

Inventors: HARGUTH ROBERT S, LINDER WILLIAM J, HARGUTH, ROBERT, S., LINDER, WILLIAM, J.
Applicants: CARDIAC PACEMAKERS INC, CARDIAC PACEMAKERS, INC.
Application year: 1998
Main classification: H01L29
IPC codes: H01L21