Arithmetic unit

Abstract: For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit mounted in a digital signal processor and the like. 2. Description of the Prior Art A prior art data processing unit for performing data comparison will be described below. The prior art data processing unit hereinafter described is primarily used as a special-purpose circuit when performing variable length encoding of image information, etc. after a discrete cosine transform. The prior art data processing unit has the circuitry shown, for example, in Figure 4, in which reference character 1x is a memory (8-bit-data memory with addresses 0 to 63), 2x is a read control circuit, 3x is a zero run counter, 4x is a zero decoder, 5x is memory data, 6x is a memory read control signal, 7x is an enable signal, 8x is a zero decode signal, and 9x is a zero run count signal. Further, reference character 10x is a variable length encoder for performing variable length encoding. Operation of the thus configured data processing unit will be described below with reference to the waveform diagram of Figure 5 (reference characters shown correspond to those in Figure 4). In Figure 5, a typical memory readout address signal is depicted as the memory readout control signal 6x. Waveform 1w in Figure 5 is used as the operating clock (CLK) of the data processing unit of Figure 4. The read control circuit 2x in Figure 4 reads out the memory data 5x at the address specified by the memory readout control signal 6x when the enable signal 7x is at a high level (hereinafter referred to as H level) (in the illustrated example, addresses are generated in the order of 0, 1, 2, ..., 63). The zero decoder 4x decodes the memory data 5x and, when the memory data shows a value 0, sets the zero decode signal 8x to the H level. At this time, the zero run counter 3x counts up, thus counting the number of 0s occurring consecutively. When the zero decode signal 8x is at a Low level (hereinafter referred to as the L level), the zero run counter 3x shows a value 0. The thus generated zero run count signal 9x and the zero decode signal 8x are output together with the memory data 5x; the variable length encoder circuit 10x at the following stage performs data processing using the zero run count signal 9x and memory data 5x at the time that the zero decode signal 8x is at the L level. Variable length encoding is a process in which data is compressed by treating the number of consecutive data zeros and the nonzero data following the data zeros as one set of data. Strictly speaking, quantization is performed before the variable length encoding. In the illustrated example, the zero run count signal 9x indicates the number of consecutive data zeros and the memory data 5x the nonzero data. Since specialized circuitry, such as the zero run counter 3x and the zero decoder 4x, is used to sequentially detect and output the number of consecutive zeros and the nonzero data following the data zeros, the prior art data processing unit lacks versatility and cannot, for example, detect the number of consecutive data values other than zeros; further, when, for example, it becomes necessary to perform an addition or comparison in addition to sequentially detecting and outputting the number of consecutive data zeros and the nonzero data following the data zeros, extra circuitry for performing the addition or comparison has to be added. Furthermore, the prior art data processing unit, when mounted as a special-purpose circuit in a digital signal processor or the like, is not able to continuously perform the data processing using the zero run count signal 9x and memory data 5x if zeros continue to appear in the memory data. The reason is that, since data compression is performed using both the number of consecutive zeros and the nonzero data, it is not possible to produce the output of the zero run counter 3x and the output of the nonzero data in every cycle. The prior art data processing unit has also had the problems that it lacks versatility because it is designed for performing data processing on fixed data (in the above example, data zeros), and that the processing time increases since data retrieval is performed through the entire memory even in the case of data that may be all zeros beyond a certain memory range. US-A-5210713 discloses a prior art encoding unit. SUMMARY OF THE INVENTION It is an object of the present invention to provide an arithmetic unit with sufficient versatility to be able to not only perform the processing to sequentially detect and output the number of consecutive data zeros and the nonzero data following the data zeros but also perform other processing. It is another object of the present invention to provide an arithmetic unit with sufficient versatility to be able to not only perform the processing to sequentially detect and output the number of consecutive data zeros and the nonzero data following the data zeros but also perform similar processing on data of values other than zero. According to the present invention, these objects are accomplished by an arithmetic unit as defined by the independent claim 1. A further advantageous embodiment of the invention is set forth in the dependent claim. A first arithmetic unit of the present invention comprises a comparator circuit, a shifter, an adder circuit, a register, and a selection circuit. The comparator circuit takes as inputs first data as comparison reference data and second data as data to be compared with the first data, and performs a comparison between the first and the second data; when the first and the second data match as the result of the comparison, the comparator circuit outputs a value 1 and sets a match signal active, while, when the first and the second data do not match, the comparator circuit outputs the second data and sets the match signal inactive. The shifter accepts an output of the comparator circuit at its input, and shifts, or does not shift, the output of the comparator circuit, depending on the state of the match signal supplied from the comparator circuit. The adder circuit accepts an output of the shifter at one input thereof. The register accepts an output of the adder circuit at its input. The selection circuit accepts a value 0 at one input thereof and an output of the register at the other input, and couples one or the other of its inputs to the other input of the adder circuit in accordance with a selection signal. With the selection circuit selecting either the value 0 or the output of the register in accordance with the selection signal, when the first and the second data do not match, the second data that does not match the first data is output by being paired with a count of the number of times that the second data matched the first data since the last occurrence of a mismatch between the first and the second data. According to the above configuration, with the provision of the comparator circuit for performing a comparison between the first and second data, the shifter for accepting the output of the comparator circuit at its input, and for shifting or not shifting the output of the comparator circuit depending on the state of the match signal supplied from the comparator circuit, the adder circuit for cumulatively adding the output of the shifter, and the selection circuit, not only can the processing to sequentially detect and output the number of consecutive data zeros and the nonzero data following the data zeros be performed, but similar processing can also be performed on data of values other than zero. This provides great versatility. It is also possible to use only the function of the comparator circuit by controlling the shifter, adder circuit, and selection circuit, only the function of the shifter by controlling the comparator circuit, adder circuit, and selection circuit, or only the function of the adder circuit by controlling the comparator circuit, shifter, and selection circuit. This adds great versatility to the arithmetic unit. A second arithmetic unit of the present invention comprises a comparator circuit, a flag register, a first register, a shifter, a second register, a third register, and a selection circuit. The comparator circuit takes as inputs first data as comparison reference data and second data as data to be compared with the first data, and performs a comparison between the first and the second data; when the first and the second data match as the result of the comparison, the comparator circuit outputs a value 1 and sets a match signal active, while, when the first and the second data do not match, the comparator circuit outputs the second data and sets the match signal inactive. The flag register accepts the match signal at its input. The first register accepts an output of the comparator circuit at its input. The shifter accepts an output of the first register at its input, and shifts, or does not shift, the output of the first register, depending on the state of the match signal supplied from the flag register. The second register accepts an output of the shifter at its input. The adder circuit accepts an output of the second register at one input thereof. The third register accepts an output of the adder circuit at its input. The selection circuit accepts a value 0 at one input thereof and an output of the third register at the other input, and couples one or the other of its inputs to the other input of the adder circuit in accordance with a selection signal. With the selection circuit selecting either the value 0 or the output of the third register in accordance with the selection signal, when the first and the second data do not match, the second data that does not match the first data is output by being paired with a count of the number of times that the second data matched the first data since the last occurrence of a mismatch between the first and the second data. According to the above configuration, in addition to the same effects as achieved with the first arithmetic unit, the interposition of the first and second registers and the flag register between the comparator circuit, the shifter, and the adder circuit offers an additional effect; that is, with this arrangement, if the comparator circuit, the shifter, and the adder circuit are not fast in operation, not only can the processing to sequentially detect and output the number of consecutive data zeros and the nonzero data following the data zeros be performed, but similar processing can also be performed on data of values other than zero. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing the configuration of an arithmetic unit according to first and second embodiments of the present invention; Figure 2 is a diagram showing operating waveforms of the arithmetic unit according to the first embodiment of the present invention; Figure 3 is a diagram showing operating waveforms of the arithmetic unit according to the second embodiment of the present invention; Figure 4 is a block diagram showing the configuration of a prior art data processing unit; and Figure 5 is a diagram showing operating waveforms of the prior art data processing unit. DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An arithmetic unit according to a first embodiment of the present invention will be described with reference to Figures 1 and 2. (Numeric values are given in hexadecimal notation) Figure 1 is a block diagram showing the configuration of the arithmetic unit according to the first embodiment of the present invention. In Figure 1, reference character 1A is a comparator circuit, 2A is an 8-bit first register, 3A is a flag register, 4A is a shifter, 5A is a 9-bit second register, 6A is a selection circuit, 7A is an adder circuit for performing cumulative additions, and 8A is a 14-bit third register. The operation of the arithmetic circuit will be described below. The comparator circuit 1A performs a comparison between the first data (waveform 3B in Figure 2 , value 0 in HEX) and second data (waveform 2B in Figure 2) output in synchronism with the rising of an operating clock (waveform 1B in Figure 2) and, when the value of the second data is 0, sets a match signal to a high level and outputs it to the flag register 3A which latches it (waveform 7B in Figure 2) in synchronism with the rising of the operating clock. At the same time, the comparator circuit 1A outputs a value 1 (waveform 4B in Figure 2) to the first register 2A which latches it (waveform 6B in Figure 2) in synchronism with the rising of the operating clock. On the other hand, when the first and second data do not match, the comparator circuit 1A sets the match signal (waveform 5B in Figure 2) to a low level and outputs it to the flag register 3A which latches it (waveform 7B in Figure 2) in synchronism with the rising of the operating clock. At the same time, the comparator circuit 1A outputs the second data (waveform 4B in Figure 2) to the first register 2A which latches it (waveform 6B in Figure 2) in synchronism with the rising of the operating clock. When the match signal (waveform 7B in Figure 2) is at the high level, the shifter 4A shifts the value of the first register 2A (waveform 6B in Figure 2) by 8 bits to the left, and outputs the resulting value 100 (in HEX, waveform 8B in Figure 2) to the second shift register 5A (waveform 8B in Figure 2) which latches it (waveform 9B in Figure 2) in synchronism with the rising of the operating clock. On the other hand, when the match signal is at the low level, the shifter 2A does not shift the value of the first register 2A (waveform 6B in Figure 2), but outputs the value of the first register 2A unchanged (waveform 8B in Figure 2) to the second register 5A which latches it (waveform 9B in Figure 2) in synchronism with the rising of the operating clock. The selection circuit 6A outputs a value 0 (waveform 10B in Figure 2) when a selection signal (waveform 12B in Figure 2) is at the low level and, when it is at the high level, selects the output of the third register 8A (waveform 11B in Figure 2) which latches the output of the adder circuit 7A in synchronism with the rising of the clock. The adder circuit 7A takes as inputs the output of the second register 5A (waveform 9B in Figure 2) and the output of the selection circuit 6A (waveform 10B in Figure 2), adds them together, and outputs the result of the addition to the third register 8A for accumulation. Here, the third register 8A must be initialized before performing a series of arithmetic operations, and the value when the selection signal is low is output as the result of the calculation from the arithmetic unit. Of the 14 bits in the result of the calculation from the arithmetic unit, the low order 8 bits indicate nonzero data and the high order 6 bits represents a count of the number of consecutive zeros. This arithmetic unit is capable of performing the above-described operations not only on data of value zero but also on every other data by changing the value of the first data, and is also capable of using only the function of the comparator circuit 1A by controlling the shifter 4A, adder circuit 7A, and selection circuit 6A, only the function of the shifter 4A by controlling the comparator circuit 1A, adder circuit 7A, and selection circuit 6A, or only the function of the adder circuit 7A by controlling the comparator circuit 1A, shifter 4A, and selection circuit 6A. This adds great versatility to the arithmetic unit. Furthermore, with the provision of the first and second shift registers 2A and 5A and the flag register 3A, if the comparator circuit 1A, the shifter 4A, and the adder circuit 7A are not fast in operation, not only can the processing to sequentially detect and output the number of consecutive data zeros and the nonzero data following the data zeros be performed, but similar processing can also be performed on data of values other than zero. In the above embodiment, the first register 2A and flag register 3A are arranged between the comparator circuit 1A and the shifter 4A, and the second register 5A between the shifter 4A and the adder circuit 7A, but if further advances are made in miniaturization in the design of the arithmetic unit, achieving faster operations of the comparator circuit 1A, shifter 4A, and adder circuit 7A, it will become possible to omit the first register 2A, flag register 3A, and second register 5A. In that case, one-cycle delay through the first register 2A and flag register 3A would be eliminated from the signal applied from the comparator circuit 1A to the shifter 4A, and one-cycle delay through the second shift register 5A would also be eliminated from the signal applied from the shifter 4A to the adder circuit 7A Embodiment 2 An arithmetic unit according to a second embodiment of the present invention will be described with reference to Figures 1 and 3. (Numeric values are given in hexadecimal notation) Figure 1 is a block diagram showing the configuration of the arithmetic unit according to the second embodiment of the present invention. The configuration is the same as that described in the first embodiment, the only difference from the first embodiment being that the 9-bit second register 5A is replaced with a 14-bit register. The operation of the arithmetic circuit will be described below. The comparator circuit 1A performs a comparison between the first data (waveform 3C in Figure 3, value 0 in HEX) and second data (waveform 2C in Figure 3) output in synchronism with the rising of the operating clock (waveform 1C in Figure 3) and, when the value of the second data is 0, sets the match signal to a high level and outputs it to the flag register 3A which latches it (waveform 7C in Figure 3) in synchronism with the rising of the operating clock. At the same time, the comparator circuit 1A outputs a value 1 (waveform 4C in Figure 3) to the first register 2A which latches it in synchronism with the rising of the operating clock. On the other hand, when the first and second data do not match, the comparator circuit 1A sets the match signal (waveform 5C in Figure 3) to a low level and outputs it to the flag register 3A which latches it (waveform 7C in Figure 3) in synchronism with the rising of the operating clock. At the same time, the comparator circuit 1A outputs the second data (waveform 4C in Figure 3) to the first register 2A which latches it in synchronism with the rising of the operating clock. When the match signal (waveform 7C in Figure 3) is at the low level, the shifter 4A shifts the value of the first register 2A (waveform 6C in Figure 3) by 6 bits to the left, and outputs the resulting value (in HEX, waveform 8C in Figure 3) to the second shift register 5A (waveform 8C in Figure 3) which latches it (waveform 9C in Figure 3) in synchronism with the rising of the operating clock. On the other hand, when the match signal is at the high level, the shifter 2A does not shift the value of the first register 2A (waveform 6C in Figure 3), but outputs the value of the first register 2A unchanged, that is, the value 1 (waveform 8C in Figure 3), to the second register 5A which latches it (waveform 9C in Figure 3) in synchronism with the rising of the operating clock. The selection circuit 6A outputs a value 0 (waveform 10C in Figure 3) when the selection signal (waveform 12C in Figure 3) is at the low level and, when it is at the high level, selects the output of the third register 8A (waveform 11C in Figure 3) which latches the output of the adder circuit 7A in synchronism with the rising of the clock. The adder circuit 7A takes as inputs the output of the second register 5A (waveform 9C in Figure 3) and the output of the selection circuit 6A (waveform 10C in Figure 3), adds them together, and outputs the result of the addition to the third register 8A for accumulation. Here, the third register 8A must be initialized before performing a series of arithmetic operations, and the value when the selection signal is low is output as the result of the calculation from the arithmetic unit. Of the 14 bits in the result of the calculation from the arithmetic unit, the high order 8 bits indicate nonzero data and the low order 6 bits represents a count of the number of consecutive zeros. The arithmetic unit, like the one in the foregoing first embodiment, has greatly increased versatility. The effect obtained by the provision of the first and second registers 2A and 5A and flag register 3A is the same as that obtained in the first embodiment. Furthermore, in common with the first embodiment, the second embodiment has the potential of being able to omit the first and second registers 2A and 5A and flag register 3A; in that case, the one-cycle delay through the first and second registers 2A and 5A and flag register 3A would be eliminated, as in the case of the first embodiment. The arithmetic unit described in the first and second embodiments can be incorporated as a major constituent element of an execution unit in a data processing unit.

Claims: An arithmetic unit for run length encoding comprising: a comparator circuit (1A) which is arranged to sequentially take as inputs first data of n bits as comparison reference data and second data of n bits as data to be compared with said first data, and perform a comparison between said first and said second data, and which, when said first and said second data match as the result of said comparison, is arranged to output a value 1 and set a match signal active, and when said first and said second data do not match, output said second data and set said match signal inactive; a shifter (4A) to which an output of said comparator circuit is input, and which is arranged to shift up, by n bits, the output of said comparator circuit when the match signal supplied from said comparator circuit is active; an adder circuit (7A) which is arranged to accept an output of said shifter at one input thereof; a first register (8A) to which an output of said adder circuit is input; and a selection circuit (6A) which is arranged to accept a value 0 at one input thereof and an output of said first register at the other input, and which is arranged to couple one or the other of its said inputs to the other input of said adder circuit in accordance with a selection signal, and said arithmetic unit further arranged, each time said first and said second data do not match, to output said second data paired with a count of the number of times that said second data matched said first data since the last time said first and said second data did not match. An arithmetic unit according to claim 1, further comprising: a flag register (3A) to which said match signal is input; a second register (2A) to which an output of said comparator circuit is input; and a third register (5A) to which an output of said shifter is input.

Inventors: KOUHASHI HARUO, KUROHMARU SHUNICHI, MATSUO MASATOSHI, OHASHI MASAHIRO, SAISHI MANA, TOUJIMA MASAYOSHI, YONEZAWA TOMONORI, KOUHASHI, HARUO, KUROHMARU, SHUNICHI, MATSUO, MASATOSHI, OHASHI, MASAHIRO, SAISHI, MANA, TOUJIMA, MASAYOSHI, YONEZAWA, TOMONORI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1998
Main classification: G06F7
IPC codes: G06F7, H03M7