A trellis encoder for encoding a digital data stream

Abstract: A trellis encoder circuit comprises receiving means to receive a stream of digital bits, loading means for loading M successive data bits into a first data register from one of said receiving means and another data register, N successive data registers, each successive data register connected in series with one of said successive data registers and said first data register, means for cycling the digital bits in the last of said N successive data registers into said first data register, first multiplexer means for selecting one of plural sets of digital bits from said last data register, means for trellis encoding said one set of digital bits and providing a trellis encoded set of digital bits, and logic means for cycling the digital bits in said successive registers until all the digital bits have been trellis encoded and for reloading said successive registers from said stream of digital bits wherein N and M are integers greater than 1.

Description: The present invention is directed to circuits and systems for communicating analog and digital signals and, in particular, to electronic circuits and systems for generating and communicating digital television signals. For many years commercial television signals have been broadcast using a format known as NTSC. With the advent of high definition television and the increasingly occupied radio spectrum, it has been determined that television broadcasters will provide a simulcast of both NTSC signals and Digital television ("DTV") signals so that the large installed base of NTSC receivers and the newly installed DTV receivers will be simultaneously able to enjoy the same broadcasts. Thus, simultaneous broadcasting will involve the simultaneous transmission of identical programs encoded in two different formats over respective television channels. Both the NTSC and the DTV channels have been defined as being 6 MHZ in bandwidth. Simultaneous broadcasting in both NTSC and DTV formats will involve the use of two different channels. Because the available spectrum for the additional channels is quite limited, it has been proposed that the additional channels be allocated in channels which are nearby to other existing channels. Where both NTSC and DTV signals are being transmitted over nearby channels, there exists a considerable problem of co-channel interference where the NTSC and DTV signals interfere with each other. The interference problem between nearby channels will be worsened if signals carried on the DTV and/or NTSC waveforms are not precisely located and are not kept within their assigned channel bandwidth. In proposed DTV systems, and as shown in Figure 1, a signal bearing video and audio data may be sent from a signal source, such as a television studio to a RF/Transmission site which may not be co-located therewith. In such a system, the video and audio data signals may be transmitted (or transported) from the studio to the RF/Transmission site using conventional communications techniques, such as microwave links. This signal, often referred to as the Transport Signal, will contain both the data and the clock for the data, either separately or by the use of a self-clocking coding such as Manchester coding. Conventionally, the RF/Transmission facility would use the data clock for the purpose of recovering the data at the Transmission facility. EP-A-0677966 discloses a modulation scheme for high definition television using a concatenated code comprising a Reed-Solomon coder followed by an N-dimensional trellis coder with N>1, the output of the trellis coder being used to modulate a one-dimensional vestigial sideband modulator. An object of the present invention is to provide a trellis encoding circuit for encoding a digital data stream in a digital television transmission. In one aspect, the invention provides a trellis encoding circuit for encoding a digital data stream, comprising: an input multiplexer having an input for receiving the digital data stream; a series of sequentially arranged registers having a first register connected to an output of the multiplexer, means for loading the series of registers with data bits of the digital data stream received by the multiplexer, a nibble select circuit for selecting a nibble from the contents of the last register in accordance with a protocol; a trellis encoder connected to the nibble select circuit for encoding data bits output by the nibble select circuit; and means for cycling the contents of the registers through the series of registers until all the loaded bits have been trellis encoded. In another aspect, the invention provides a trellis encoding circuit for encoding a digital data stream comprising: an input multiplexer for receiving the data stream; a plurality of storage registers arranged in parallel and connected to the multiplexer for loading with data bits of the digital data stream; a nibble select circuit associated with each of the storage registers for selecting two data bits from the contents of the register in accordance with a protocol; a trellis encoder associated with each nibble select circuit for receiving the selected bits from the associated nibble select circuit and encoding the received bits in accordance with the protocol; and a multiplexer for receiving the encoded output of trellis encoders and selecting the encoded output from the appropriate trellis encoder in accordance with the protocol. The present invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 is a functional block diagram of a prior art digital television system; Figure 2 is a functional block diagram of a circuit in the RF transmission system; Figure 3 is a functional block diagram of the RF transmission system; Figure 4 is an amplitude versus frequency plot for a DTV signal as produced; Figure 5 is a functional block diagram of a sync confidence counter circuit; Figure 6 is a functional block diagram of an interleaving circuit of the prior art; Figure 7 is a functional block diagram of an interleaver buffer circuit; Figure 8 is a functional block diagram of a rate conversion circuit; Figure 9 is a functional block diagram of a first embodiment of a control circuit for a trellis encoder; Figure 10 is a functional block diagram of a first embodiment of a trellis encoder; and Figure 11 is a functional block diagram of a second embodiment of a trellis encoder. As defined by the U. S. Government Advanced Television Standards Committee ("ATSC") Digital Television Standard, dated September 16, 1995, a basic DTV system 100 block diagram consists of three sections, as shown in Figure 1, including a source coding and compression section 102, a service multiplex and transport section 104, and a RF/Transmission System 106. The source coding and compression section 102 receives a video signal 108 and an audio signal 110 and encodes these signals, respectively, into digital data streams. The encoding may include bit rate reduction methods and compression techniques known and appropriate for video and audio data. Figure 1 shows the encoded video and audio data may be provided to the service multiplex and transport section 104 along with ancillary data signals 112 and control data signals 114. The ancillary signals 112 and control signals 114 may include control data, conditional access control data and data associated with the audio and video services, such as closed captioning. Generally the video signals may be compressed using a MPEG-2 video stream syntax and the audio signals may be compressed using the Digital Audio Compression (AC-3) Standard. In the service multiplex and transport section 104, the compressed data stream may be divided into packets of information and means for identifying each packet or packet type may be appended. In the process, the video data stream, audio stream and ancillary data stream packets may be multiplexed into a single data stream. The packeted data may be transported by the MPEG-2 transport system for the packetizing and multiplexing of video, audio and data signals for digital broadcast systems. In the RF/Transmission section 106 the packeted data is channel coded and modulated. A channel coder 120 may modify the data stream and add additional information that can be used by the receiver to reconstruct the data from a received signal which has been affected by typical transmission interference sources. The modulation 122 uses the digital data stream to modulate the transmitted signal. In a DTV standard, the modulation can use an 8 VSB modulation scheme. The modulated signal may be amplified and applied to an antenna 124 for broadcast in a conventional fashion. Figure 2 shows a RF/Transmission system may receive a data and clock signal 10 from a transport section as shown in the system of Figure 1. The data and clock signal may be applied to a data recovery circuit 202 which extracts the data from the transport format, and if necessary extracts the data clock from the same signal. The data signal may be applied to a randomizer 204 which alters the order of the data within the data stream in accordance with the DTV standards. The randomizer 204 may operate based on a generator polynomial and a pseudo random binary sequence. The signal output from the randomizer 204 may be applied to a Reed Solomon encoder 206 which uses the Reed Solomon encoding technique to provide packets which have been encoded in a predetermined manner, known to the receiver of the signal. The encoded packets are applied to an interleaver 208 which performs a convolutional interleaving on the data in accordance with a predetermined scheme. The Reed Solomon encoder 206 writes to a data buffer (not shown) at the transport layer data rate, and the interleaver 208 reads the data buffer at the transmission layer data rate. This allows the system to operate on two asynchronous clocks without synchronous handshaking. The signal output from the interleaver 208 may be applied to a trellis encoder 210. In a DTV system, the trellis encoder employs a 2/3 rate trellis code with one unencoded bit. In the DTV system, one input bit is encoded into two output bits using a 1/2 rate convolutional code while the other input bit is precoded. In accordance with the DTV specification, the signalling waveform used with the trellis code is an 8-level (3 bit) one dimensional constellation. The signal output from the trellis encoder 210 may be applied to a synch insert circuit 212 which inserts the Data Segment Sync and Data Field Sync at the appropriate locations within the digital data stream. The digital data stream output from the sync insert circuit 212 may be applied to a Nyquist filter 214 to limit the spectrum of the encoded data stream to the bandwidth of the transmission system (6 Mhz for the standard DTV system). The filtering function in the present invention comprises the steps of: 1) interpolating and upconverting the signal; 2) correcting the signal for non-linearities; 3) equalizing existing frequency response imperfections with an adaptive filter; and 4) downconverting and storing the digital sample. After the Nyquist filter 214 (and related pulse shaping), a pilot signal may be added. The pilot signal insertion saves on circuitry by performing the pilot signal insertion after the pulse shaping by the Nyquist filter. The digital signal provided by the Nyquist Filter 214 to which the pilot has been added is converted to an analog signal by a digital to analog converter 216 and applied to one of the inputs of an IF mixer 30. The other input signal to the IF mixer 30 is an IF carrier frequency which has been derived from an IF Frequency Phase Lock Loop circuit 218. The IF signal generated by the IF mixer is applied to an IF Circuit 40 which filters the IF signal and applies the output signal to one of the inputs of a channel mixer 50. The other input of the channel mixer 50 is a channel frequency which has been derived from a UHF Phase Lock Loop 170. In one embodiment of the present invention, the IFF PLL 218 and the UHF PLL 70 may generate their respective signals from a common clock reference 190. The clock reference 190 may base its clocking signal on an externally derived signal (EXT REF) or on an appropriate clocking signal developed locally or from the data received by the exciter. The signal output from the channel mixer 50 may be applied to a band pass filter 60 in a conventional fashion to develop a filtered signal which may be amplified sufficiently and provided to an antenna 220 for broadcasting. Figure 2 shows the signal input to the data recovery circuit 202 may be either separate data and clock signals or a single embedded clock signal (such as from the use of Manchester encoding). The clock recovery circuit may use a standard phase lock loop to lock onto the clock embedded in the received data. Once the clock is recovered, it may be used to drive the system timing. The data recovery circuit 202 may also include a frame synchronizer to locate the sync signals within the signal sent from the transport section (of Figure 1) and to align the received data streams into bytes for processing. Figure 2 depicts in the standard DTV system, the Reed Solomon encoder requires 20 modula 256 multiplies and 20 exclusive-or (XOR) adds for each data byte received from the transport section. At the high data rates used in the DTV system, the encoding requires a processor capable of 97 million operations per second. The Reed Solomon encoder may be implemented to achieve such a high data rate in a Field Programmable Gate Array in conjunction with a look-up table. The Nyquist filter 214 may be implemented as a root-raised- cosine filter with an alpha factor of 0.1152. The filter may be implemented as a Finite Impulse Response filter. In a preferred embodiment, the filter is a complex filter to handle the vestigial sideband function. Figures 2 and 3 (in which common elements have been provided with common reference numerals) show that, in a RF transmission system employing a trellis encoder embodying the invention, the mixers 30, 50 of Figure 1 and their associated PLLs 218, 70 may be implemented in a circuit in which the modulator 20 portion of the circuit of Figure 1 is simplified as a single block, modulator 20, of Figure 3. A data signal 10 applied to the modulator 20 generates a clock signal 302 and a encoded data signal 21 (in analog format). Because both the clock signal 302 and the encoded data signal 21 were originally generated from a digital data stream, the resulting frequencies of these signals are directly proportional to the digital data rate. If these signals were used to develop the signal which is to be transmitted, the transmission signal will be locked to the frequency of the data source. In a situation, in which the Transmission layer is remote from the Transport layer (and may not even be under common control), a broadcaster transmitting a signal based on a remote data source in such a situation is not in control of the broadcast frequency to the rigid specification required of such broadcasters. In addition, any frequency offsets to the transmitted signals required by the regulating authorities, such as the U. S. Federal Communications Commission, for co-channel or adjacent channel interference problems cannot be performed without changing the original data rates. In one aspect of the present invention, the dependency of the transmission frequency on the digital data rate is removed by the circuit shown in Figure 3. This circuit also provides a means for making precision frequency offsets which may be required. Figures 3 and 4 depict the modulator 20 generating an analog modulated frequency signal of encoded data 21. In a standard DTV signal, the encoded data signal 21 may be in the format of an 8VSB signal such as specified for DTV. The encoded data signal 21 could be any other modulated signal, such as an NTSC signal, an FM signal, an AM signal and/or a SSB signal, etc. For the situation of an 8 VSB signal, the signal will have a form as represented in Figure 4, in which the signal has a nominal center frequency at 10.76 MHz and has a VSB pilot signal nominally at 8.06 Mhz. Normally, the encoded data signal 21 is at a frequency considerably below the frequency at which the signal is to be broadcast and must be upconverted to the broadcast frequency. The encoded data signal 21 is first applied to a frequency translator 30 (such as a mixer) to produce an IF signal 31. A signal having a nominal frequency of 54.76 MHz is applied to the frequency translator to produce the IF signal 31. The IF signal 31 is then applied to a second frequency translator 50 (such as a mixer) to upconvert the IF signal to the desired channel frequency. The signal output from the second frequency translator 50 may be applied to a load, after amplification as desired. The frequencies used by the frequency translator 30 to upconvert the encoded data signal is derived from a reference frequency 190 as modified by the data clock 302. In this way, the encoded data signal has its dependence on the frequency of the digital data rate removed and the frequency of the signal is corrected to at or near its nominal condition. Figure 3 shows the digital modulator 20 which also produces the digital data clock 302 which is applied to a programmable frequency divider 180 which is 1 to 1 proportional to the carrier or pilot frequency of the digital modulator 20. Thus, the signal 181 output from the frequency divider 180 for a DTV system is nominally at 8.06 MHz. The signal 181 is applied to a third frequency translator 150. The reference frequency 190 is applied to a reference divider 80, phase detector 90, loop filter 92, and a Voltage Controlled Oscillator ("VCO") 94. The reference signal 191 is applied to a Numerically Controlled Oscillator ("NCO") 120. The signals output from both the VCO 94 and the NCO 120 are applied to a fourth frequency translator 130. The output signal from the fourth frequency translator 130 is band pass filtered ("BPF" 140) and applied to a second input terminal of the third frequency translator 150. The output signal from the third frequency translator 150 is band pass filtered by a second BPF 170 and is divided by a second programmable frequency divider 98 before being applied to the phase detector 90. In operation, the frequency of the NCO 120 is controlled by the reference frequency 190. The reference frequency may be locally generated or may be received from an external circuit or device (not shown). The reference frequency may be applied to other, similar circuits so that multiple digitally-generated signals may be frequency locked to the same reference. The NCO 120 should be capable of providing frequency resolution to the extent required by the IF signal 31. The output of the NCO 120 is subtracted from the output of the VCO 94 in the fourth frequency translator 130. The BPF 140 is used to filter out any undesired output from the fourth frequency translator 130. In operation the third frequency translator 150 subtracts the output signal of the programmable divider 180 from the output of the first BPF 140. The second BPF 70 removes any undesired output from the third frequency translator 150 and applies this difference frequency to the second programmable frequency divider 98. For the nominal signal condition, the second programmable divider 98 and the reference divider 80 are set such that their output frequencies are the same. The outputs of these two dividers 98, 80 are provided to the phase detector 90. Thus, the output of the phase detector 90 is proportional to the phase difference between its two inputs and is applied to the loop filter 92. The loop filter 92 converts the output of the phase detector 90 into a voltage which is proportional to the phase difference and applies this voltage to the VCO 94. As a result, the VCO 94 is frequency locked to the reference frequency and not to the original digital rate. In operation with an input data signal at an off-nominal data rate, the circuit of Figure 3 removes the effect of the off- nominal rate. For example, if the clock rate of the incoming data 10 is off nominal by "delta" the frequency of the signal 302 will equal 10.76 MHz + delta and of the signal 181 will equal 8.06 MHz + delta. The delta is propagated through the reference frequency components and ultimately through the VCO 94 so that the signal used to upconvert at the first frequency translator 30 is also offset from the nominal by delta. Since the data signal at signal 21 is also offset by delta, the first frequency translator 30 will subtract out the two delta components leaving the signal 31 free of the delta offset. In the DTV standard transport protocol, the sync signal (a byte) is not a unique number. Accordingly, a false indication of synchronization may be given if any eight contiguous bits of data are identical to the sync byte. The present system overcomes the effect of this false sync by using a confidence counter. The confidence counter counts the number of sync bytes continuously. With reference to Figure 2, if a sync byte is not detected by the data recovery circuit 202 when expected, confidence of having sync lock is reduced and the confidence counter is decremented. If several frames occur without a sync byte being detected at a specific byte location within the data stream, the frame synchronizer will indicate that the system is out of sync lock and can automatically begin a new frame search and acquire operation. Figure 5 depicts a frame and bit synchronizer using a confidence counter, which may receive data as received from the transport layer in a serial form (SERIAL DATA), the serial data being converted to a parallel form (such as an 8 bit parallel data word) by a serial to parallel converter 750 and provided to a sync detector 752. The sync detector compares the data word to a predetermined sync word and a signal indicating whether sync was found is provided to a confidence counter 754. The confidence counter 754 increments a counter if sync was found where expected and decrements the counter if sync was not found where expected. A sync is "expected" exactly one frame from the last detected sync word. Thus, a modulo counter 758 counts the number of words encountered since the last sync detection and enables the confidence counter 754 at that word at which sync is expected. If the confidence counter 754 reaches a predetermined value, the frame is considered in sync and a SYNC LOCK signal is sent to other elements in the circuit and/or displayed for the system operator. If the confidence counter 754 is decremented to zero, sync is considered to be lost causing the SYNC LOCK signal to be removed and resetting the modulo counter 758 to begin the search for sync anew (i.e., starting a new frame search and acquire mode). Figure 5 shows the modulo counter 758 also provides a modulo 8 count of serial bits coming into the serial to parallel converter 750. In this way, the converter 750 remains bit aligned with the rest of the sync detection circuit. At the end of each modulo 8 count, the data word is provided to the data randomizer along with being provided to the sync detector. The data randomizer and other elements of the circuit can use the SYNC LOCK signal to determine whether the data byte is valid. The confidence counter can readily be modified to obtain any degree of confidence that sync lock has been achieved; generally, the higher confidence required necessitating a longer sync detection time. In addition, the loss of sync lock need not wait until the confidence counter returns to zero ( e .g., five correct sync detections could be required to obtain lock but only three consecutive failures to detect sync could cause a loss of sync.) Similarly, the number of successful sync detections can be capped so that once sync has been locked, the confidence counter will not increment past the locking value (but will decrement if a expected sync is not found). At the startup of after the loss of input sync, the confidence counter circuit is set to begin an acquisition mode. In the acquisition mode, the serial data bits are clocked serially into the serial to parallel converter 750 which may take the form of an 8-bit buffer. Thereupon, at each clock cycle, the 8bit data word is checked for the presence of the sync byte. If the sync byte is detected, a count enable bit is set and the circuit enters a confidence testing mode. Whenever the count enable bit is set, the module 1504 counter begins counting until the next 1504 bits (188 words of 8 bits each, or 1 frame) have been transmitted. At this time, the sync is checked again and if present the process is repeated. If the sync byte is not present, the count enable bit is reset and the acquisition mode is restarted. If a predetermined number of consecutive frame syncs are detected, the SYNC LOCK signal is set and the circuit enters a Frame Lock mode. thereafter, normal operation begins and the frame sync is checked continually to ensure reliable transmission. If frame sync is not found for a predetermined number of frames, the circuit will switch back to the acquisition mode, restarting the entire process. Note that the confidence counter circuit may be utilized in both the transmission of the DTV signal and in receivers attempting to receive and display DTV or other digitally framed signals. Such receivers are faced with a similar problem of establishing and maintaining frame sync as described above and the described circuit will also be useful to such receivers. The frequency of the signal used in the transport layer can be made independent of the frequency of the signal in the transmission layer by a data interleaver. It was known in the prior art to interleave data in a manner in which the frequency of the data was changed. For example, Figure 6 shows a signal from the transport layer, carrying the data at a 19.39 MHz rate, would typically be provided to a Reed Solomon encoder for encoding in a conventional fashion. The data exiting the Reed Solomon encoder 550 would be provided to a microprocessor 552 which would interleave the encoded data and provide it, at an arbitrary rate, usually in a burst mode, to a Re-Timer Buffer 554. The Re-Timer Buffer 554 will typically buffer the burst mode data from the microprocessor and output a signal at a specific rate as governed by its clock, usually the standard 10.76 MHz rate. Often in prior art systems, the 10.76 MHz clock signal provided to the Re-Timer Buffer 554 would generated from a PLL 556 being driven from the 19.39 MHz clock (often obtained from the data). In a RF transmission system including a trellis encoder embodying the invention, the burst mode microprocessor of the prior art may be eliminated with a suitable interleaver buffer. Figure 7 shows a Reed Solomon encoder may receive the data at the frequency of the transport layer, 19.39 MHz, and provide the encoded data to a data interleaver buffer 208. The data is read out of the interleaver buffer 208 at a rate of 43.04 MHz and provided to the trellis encoder 210 which outputs the trellis encoded data at the 10.76 MHz rate associated with the transmission layer. Note that the rate converted 43.04 MHz clock is available to the trellis encoder 210 and therefor can be used totime the extraction of the data from the interleaver buffer 208 and for the trellis encoding. The clocks to the trellis encoder are provided by a rate converter 650 which converts its incoming 19.39 MHz clock signal by a ratio of 313*207*832/312/188/828 to develop a 43.04 MHz clock signal. The resulting clock signal can be decreased or divided by a factor of 4 to provide a 10.76MHz clock and may be provided to other elements in the transmission layer. The digital elements to either side (input or output) of the interleaver buffer 208 are made more simple than in the prior art because these elements can operate in a continuous mode and do not have to be sized for burst mode operations. Figure 7 shows the 19.39 MHz clock that may be obtained from the data (as received or as corrected in another aspect of the present invention) or from a local oscillator. The use of a local oscillator ensures that the trellis encoder will continue to operate despite the loss of the transport signal or the loss of the clock in the transport signal. Indeed, the local clock can be used to drive the Reed Solomon encoder in the event of a loss of signal from the transport layer (the encoded signal). Because at least one promulgated standard requires that the transmission layer continue to transmits a signal (generally a pseudorandom signal) even if the originally encoded signal is lost, keeping the Reed Solomon encoder in operation provides the necessary data signals to maintain a transmission signal. If a sufficiently robust Digital Signal Processor ("DSP") is used, all of the Reed Solomon encoding, data interleaving and trellis encoding and frequency conversion can be accomplished in a chain of one or more suitably programmed DSPs which have been provided with the desired clock(s). Figure 8 shows a rate converter circuit that may include a Divide By 141 circuit 570 which receives a clock signal (such as a 19.39 MHz signal) and provides the frequency divided signal to a phase detect circuit 572 and, subsequently, to a loop filter 574 which drives a thermally compensated voltage controlled oscillator 576. The output of the TXCO 576 is provided to a buffer and is fed back to a Divide By 313 circuit 580 which is also connected to the phase detector 572. The TXCO 576 has a center frequency at the desired output frequency ( e .g., 43.04 MHz) and has a rail at +/- 3 Hz which is the maximum permitted deviation of the carrier frequency in a standard DTV system. In operation, so long as a clock frequency is present at the input to the circuit and the frequency of that signal is within the desired limits of the system, the generated 43.04 MHz clock may be permitted to track the input signal. If the input signal varies in frequency outside the limits, the TXCO 576 will not go outside its rails and will limit maintain the output frequency within the required specification. Figure 8 depicts the useability of the input signal to serve as the basis for the output signal may be indicated by an external signal, such as the SYNC LOCK signal described herein in association with the confidence counter circuit. When the system is out of sync, a gate 582 can provide a voltage signal which will drive the TXCO 576 to the desired output frequency. If desired, the magnitude of the voltage signal can be set by the operator of the system, such as through a user-settable potentiometer (not shown). Figures 9, 10, and 11 show a trellis encoder which receives a stream of digital data to be encoded (DATA IN). The digital data steam is applied to a FIFO Buffer 52 and a Staging/Timer Circuit 54 to align the data in time with the remainder of the circuit. At the appropriate time, the data are applied to a nibble select circuit 56 which selects the appropriate two bit nibbles from the input digital data in accordance with the rules of the encoding scheme. In turn, the selected nibbles are encoded by a trellis encoder 58 (which for the DTV system supplies 3 bits of output data for each two bits of data input to it). The data output from the trellis encoder 58 are supplied/ to a multiplexer which multiplexes the data with sync bits and/or with pseudo random number encoding output of the multiplexer 59 is supplied to an output register 59. The operation of the circuit of Figure 9 is controlled by control logic 51 which coordinates framing of the data, resetting symbol and segment counters 53, 55 as appropriate. The outputs of the counters 53, 55 are provided to an enabler 57 which provides pacing signals to the other elements of the circuit so that each element needing to know the location of the incoming data within the frame will have that data available. In operation, a digital data stream is provided to the trellis encoder circuit and is received by the input buffer and staging elements. The control logic 51 reviews the incoming data to determine frame boundaries. Once framing has been established, the control logic 51 resets the symbol counter 53 and the segment counter 55 to start a new frame. As the data is thereafter received, the symbol and segment counters 53, 55 are incremented and cycle themselves in accordance with the format of the data. The symbol and segment counters 53, 55 drive the enabler 57 which sends the appropriate control/selection signals to the other elements of the circuit. Figure 9 depicts that guided by the signals from the enabler 57, the nibble select circuit 56 selects the appropriate nibbles from the input data stream to be encoded next. In the case of a standard DTV signal, the nibbles selected are done in accordance with the DTV specification [Annex D, table 2 to the Digital Television Standard], although any other conversion scheme could be implemented. Thereafter, each nibble is encoded in the order selected by the trellis encoder 58. As appropriate for the specified protocol and as guided by the enabler 57, the multiplexer alternatively outputs the trellis encoded data or sync data in accordance with the protocol being followed by the system. In the event that an input data signal is lost or loses sync, a pseudorandom stream of data bits ("PN") can be applied by the multiplexer 54 to the output data stream. The nibble select circuit 56 (Figure 11) receives a stream of digital data (DATA IN) at each of twelve storage registers R1,R12. The stream of input data arrives serially and may be cycled into successive ones of the storage registers R1,R12. The twelve registers are connected to one side of a first multiplexer 62. Under control of a multiplexer control signal (not shown) based on the location of the input data within the frame, the first multiplexer 62 presents one of the bytes of input data at its output terminals. A second multiplexer 64 under control of a second multiplexer control signal, receives the selected byte and selects two bits of the data to output. The output bits are applied to the trellis encoder 66 which encodes the two bits into three bits which are then passed to the next stage in the transmission system. Figure 10 shows a trellis encoding circuit embodying the present invention which receives a stream of digital data (DATA IN). A trellis encoding circuit may include an input multiplexer 72 which loads the first of a series of twelve registers R1,R12 with data from either the DATA IN input of multiplexer 72 or from the contents of the last register in the series (R12) so as to cause all of the registers to cycle through. At each bit selection time, the contents of the last register (R12) are presented to a nibble select circuit 74 which selects two of the bits from the last register R12 in accordance with the preselected protocol. As each nibble is selected from the last register, the contents of the registers are cycled one register at a time, so that all of the twelve bytes within a segment are provided to the nibble select circuit 74, in turn, a total of four times. When all of the bits of the twelve words have been output from the nibble select circuit 74, the input multiplexer 72 loads new data into the twelve registers R1,R12 to encode the next segment of data. In still another embodiment of a trellis encoder circuit embodying the present invention, an input data stream (DATA IN) is directed by a first multiplexer to twelve parallel registers. Once the registers are loaded, nibble select circuits associated with each of the storage registers will select two data bits from their associated storage registers and provide the selected bits to an associated trellis encoder. Each trellis encoder encodes the received bits in accordance with the predetermined encoding scheme and provides the three encoded bits to the input of an output multiplexer. The output multiplexer selects the encoded bits from the appropriate trellis encoder in accordance with the protocol. Note that the trellis encoder of this embodiment requires a depth of 1 whereas the trellis encoders of Figure 10 requires a depth of 12 if the trellis encoding scheme of the standard DTV system is being used.

Claims: A trellis encoding circuit for encoding a digital data stream, comprising: an input multiplexer (72) having an input for receiving the digital data stream; a series of sequentially arranged registers (R1 to R12) having a first register (R1) connected to an output of the multiplexer (72); means for loading the series of registers (R1 to R12) with data bits of the digital data stream received by the multiplexer; a nibble select circuit (74) for selecting a nibble from the contents of the last register (R12) in accordance with a protocol; a trellis encoder connected to the nibble select circuit (74) for encoding data bits output by the nibble select circuit (74); and means for cycling the contents of the registers (R1 to R12) through the series of registers until all the loaded bits have been trellis encoded. A trellis encoder circuit according to claim 1 wherein the means for cycling the contents of the registers cycles the contents of the registers until all the loaded bits have been cycled to the nibble select circuit (74) four times. A trellis encoding circuit for encoding a digital data stream comprising: an input multiplexer for receiving the digital data stream; a plurality of storage registers arranged in parallel and connected to the input multiplexer for loading with data bits of the digital data stream; a plurality of nibble select circuits each associated with one of the storage registers for selecting two data bits from the contents of the register in accordance with a protocol; a plurality of trellis encoders each associated with one nibble select circuit for receiving the selected bits from the associated nibble select circuit and encoding the received bits in accordance with the protocol; and a further multiplexer for receiving the encoded output of the trellis encoders and selecting the encoded output from the appropriate trellis encoder in accordance with the protocol.

Inventors: SECCIA JOSEPH, TWITCHELL ED, SECCIA, JOSEPH, TWITCHELL, ED.
Applicants: HARRIS CORP, HARRIS CORPORATION
Application year: 1998
Main classification: H04L1
IPC codes: H04N7, H03M13, H04N11, H03L7, H04N1, H04N5, H04L7, H01Q5, H04L1, H04J3, H01Q21, G11B20, H04B1, H04L27, H04L5