METHODS AND APPARATUS FOR WRITING TO TRACKS ON MAGNETIC-STRIPE CARDS

Abstract: Techniques are provided for writing to a track on a magnetic stripe card using position information derived from reading other tracks. A magnetic stripe encoder is provided for writing to track II (24) using positional information read from track I (2). In accordance with a further aspect of the present invention, track III (27) is used to cancel out crosstalk arising during writing of track II (24).

Description: METHODS AND APPARATUS FOR WRITING TO TRACKS ON MAGNETIC-STRIPE CARDS CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 60/067,016 filed December 1, 1997. FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT Not applicable. BACKGROUND OF THE INVENTION 1. Technical Field The present invention relates, generally, to methods and apparatus for writing to magnetic tracks on magnetic stripe cards and, more particularly, to techniques for writing to a track on a magnetic stripe card using information read from one or more other tracks on the card. 2. Background Information Magnetic stripe cards, often referred to as "mag-stripe" cards, have enjoyed increased popularity in recent years, and are widely used in the form of credit cards, debit cards, ID badges and the like. Consumer information in these cards is typically stored in narrow "tracks," approximately one-tenth of an inch wide, lying within a magnetic stripe bonded to the card media, wherein the card media is typically PVC plastic or plasticized paper. The magnetic stripe stores data as a series of magnetic field transitions oriented either "north" or "south." A transition from north to south or south to north as the magnetic stripe card is swiped past the read coils of a magnetic head induces a signal on the read coil. In accordance with one coding scheme, the number of transitions sensed within a certain time period (given a varying but known card speed) is used to encode one of two logical states. A sequence of such logical states is then used to represent numbers, characters, or other information depending on the particular context. A number of standards have been developed in regard to magnetic stripe technology, for example: ISO 7811-2,Part 2: Magnetic Stripe (1995); ISO 7811- 4, Part 4: Location of read-only magnetic tracks — Tracks 1 and 2 (1995); ISO 7811- 5, Part 5: Location of read-write magnetic track -- Track 3 (1995); ISO DIS 7811- 6, Part 6: High coercivity magnetic stripe (1995); ISO 7813, Financial transaction cards (1995). These standards are hereby incorporated by reference. In addition, general information regarding magnetic stripe and other cards can be found in a number of texts, e.g., Zoreda & Oton, SMART CARDS (1994); and Rankl & Effing, SMART CARD HANDBOOK (1997), the contents of which are hereby incorporated by reference. Financial institutions commonly use two tracks within the magnetic stripe card: track I for alphanumeric data identifying the customer, account number, expiration date, and any discretionary data such as PIN offset. Financial institutions and other parties therefore desire the capability of writing to track II of standard ATM and debit cards, as this track is often used to hold important discretionary data (i.e, account number, PIN number offset, expiration data, and the like). However, presently known methods utilizing controlled motorized mechanisms (e.g., stepper motors and other mechanical systems) to accurately sense card position are prohibitively expensive for many applications. Moreover, the mechanical rather than solid-state nature of such systems make them susceptible to mechanical failure and other reliability problems. Systems and methods are therefore needed to overcome these and other limitations of the prior art. More particularly, magnetic stripe encoder systems are desired which more reliably and cost-effectively write to tracks on magnetic stripe cards. BRIEF SUMMARY OF THE INVENTION The present invention overcomes the limitations of the prior art by providing techniques for writing to a track on a magnetic stripe card using position information derived from reading one or more other tracks on the card. In accordance with one aspect of the present invention, a magnetic stripe encoder is provided for writing to track II of a magnetic stripe card using positional information derived from track I. In accordance with a further aspect of the present invention, track III information is used to cancel out crosstalk arising during writing of track II. In this way, tracks on a magnetic stripe card may be written to without the use of expensive and relatively unreliable mechanical position sensors. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS The subject invention will hereinafter be described in conjunction with the appended drawing figures, wherein like numerals denote like elements, and: FIG. 1 is a schematic overview in accordance with an exemplary embodiment of the present invention; FIGS. 2 - 7 are flowcharts depicting a method of using a magnetic stripe encoder in accordance with the present invention; FIG. 8 is a timing diagram useful in illustrating the serial recording of self- clocking data; and FIGS. 9-14 are schematic diagrams presenting various details of a preferred embodiment of the present invention. DETAILED DESCRIPTION OF PREFERRED EXEMPLARY EMBODIMENTS Systems and methods in accordance with various aspects of the present invention provide a magnetic stripe encoder which uses previously written track data to derive position information enabling writing to another track. In accordance with the traditional three-track paradigm, for example, while the card is being swiped past the magnetic head, track I data is read dynamically and, using this data, the apparatus determines where and when to write information onto track II. In a preferred embodiment, track III is used to cancel out cross-talk induced during the write process. The present invention may be described herein in terms of functional block components and various processing steps. It should be appreciated that such functional blocks may be realized by any number of hardware and/or software components configured to perform the specified functions. For example, the present invention may employ various integrated circuit components, e.g., memory elements, digital signal processing elements, look-up tables, and the like, which may carry out a variety of functions under the control of one or more microprocessors or other control devices. The present invention may also employ any number of filters, amplifiers, invertors, capacitors, resistors, diodes, transistors, and the like. Such conventional components that are known to those skilled in the art are not described in detail herein. Referring now to the diagrammatic block diagram shown in FIG. 1, an exemplary magnetic stripe encoder suitably comprises a magnetic head 1 having, in the illustrated embodiment, three read heads 70, 72, and 74, associated with three respective outputs: track I (2), track II (24), and track III (27). Magnetic head 1 preferably includes a track II write head (76), described in further detail below. Track I-III outputs (2, 24, and 27) are suitably coupled to pre-amp/filter circuits 3, 25, and 28. The outputs 4 and 29 of pre-amp/filters 3 and 28 are then coupled to filters 5 and 30 respectively, each of which feed into a difference amplifier 8 — track I associated with the inverting input, and track III associated with the non-inverting input. A phase adjustment 23, described further below, is preferably employed in connection with pre-amp/filter 3. The output of amplifier 8 is preferably coupled to a peak detector 11 and an error feedback block 67. Error feedback block 67 preferably includes an absolute value circuit 10, a peak detector 14, and a pseudo-log convertor 16. The output of error feedback block 67 is coupled to microcontroller 20. The output of a Schmitt trigger 18 associated with a peak detector 11 is also coupled to microcontroller 20. Amplifier 8 preferably includes a suitable offset adjustment 21 and gain adjustment 22. The output of pre-amp/filter 25 (track II) is suitably delivered to microcontroller 20 through an amplifier 32 and Schmitt trigger 34. Track II write data output 42 and selector signal 43 communicate with write current selector 44, which feeds into write output amplifier 64 through filter 46. In the illustrated embodiment, write output amplifier 64 comprises amplifier 68, amplifier 48, amplifier 53, and current sensor 50, the details of which are described below. The output 56 (write coil + and write coil - signals) are fed to write head 76 in accordance with the chosen write current. Microcontroller 20 also suitably interfaces with a keypad 37, a biometric input 39, a bi-directional interface 40, a display 60, a smartcard interface 58, and a supervisory reset circuit 65. In addition, the various components are fed from a suitable power supply 61. Having thus given an overview of the exemplary system illustrated in FIG. 1, the various components of the system will now be described in detail. Magnetic head 1 is preferably configured to read three tracks (I, II, and II), and write to one track (II). As one aspect of the present invention is directed at canceling cross-talk arising during operation, it is preferable that the various heads used for reading and writing are symmetrical — i.e., that tracks I and III are equidistant from central track II (for example, about 130 mils). For the same reason, it is also important that the coil impedances for tracks I and III be sufficiently matched (i.e., with respect to coil reactance and resistance). Magnetic heads suitable for this purpose include, for example, the model 96006E magnetic head manufactured by Michigan Magnetics. It will be appreciated that the present invention may be employed in the context of magnetic heads with additional read and write heads. Pre-amp/filter circuits 3, 25, 28 are used to process the signal received from the respective track outputs 2, 24, and 27. More specifically, these circuits are used to amplify the signals induced on the read coils of the magnetic heads and filter out high frequency noise. In a preferred embodiment, these filters are characterized by a 3db point of about 100 kHz. More particularly, referring now to the schematic detail shown in FIG. 10, the track I, II, and III information (communicated through connector 1004), is fed to pre-amp/filter 3, 25, and 28 respectively. In this embodiment, the filter circuits are substantially the same, comprising, as in circuit 3, an amplifier 1006 (e.g., part LM358) and associated passive components (R28A, R25, C23, C19, R26) chosen to effect a particular frequency response. In this embodiment, a phase adjustment 23 is shown as a manual analog potentiometer. Alternatively, a digital potentiometer controlled by microcontroller 20 may be employed. Referring again to FIG. 1, filters 5 and 30 are suitably used to provide a sharper roll-off to the signal produced by pre-amp/filters 3 and 28. In a preferred embodiment, filters 5 and 30 comprise third-order Bessel filters having a 3 db point of about 10 kHz. More particularly, referring now to FIG. 12, filters 5 and 30 are suitably implemented as amplifiers 1204 and 1206 (e.g., part numbers LM358A) used in conjunction with various capacitors and resistors having values chosen to effect the desired frequency response (in this case, 3 db at 10 kHz). A connector 1202 (corresponding to connector 1002 shown in FIG. 10) is suitably used to pass the track I and II input and output values. Difference amplifier 8 is used to derive a signal (9) consisting of magnetic card track I data induced on track I read head 70. The outputs of filters 5 and 30 are coupled to the inverting and non-inverting inputs respectively. In this way, track III can be used to cancel out cross-talk noise arising during the write operation. An offset adjustment 21 and gain adjustment 22 employing, for example, an analog or digital potentiometer, may be used to compensate for any offset or gain errors present in the output of the amplifier. Such offset and gain adjustment circuits are well known in the art. Similarly, phase adjustment 23 may comprise digital or analog potentiometers suitable for correcting for any phase errors associated with reading track I as compared with track III (e.g., any errors associated with manufacturing variations). In a preferred embodiment, difference amplifier 8 suitably comprises an amplifier 1008 as shown in FIG. 10 (e.g., part LM358) and associated passive components. Amplifier 8 operates such that when a write pulse is presented to the coil of track II (76), the non-linear crosstalk waveform presented on track I (70) and track III (74) is applied to the inputs of amplifier 8. If a card having timing information stored on track I is being swiped by magnetic head 1 while writing to track II, and no magnetic data is on track III of the card, then the difference at the amplifier 8 output should be close to what would be read from track I if no data were being written to track II. That is, the output of amplifier 8 corresponds to the information read from track I. Thus, the third track produces a baseline flux such that symmetrical fluxes (between track-pair I-II and track-pair II-III) are substantially canceled. As mentioned above, peak detector 11 is used to identify and amplify the output of amplifier 8, thus producing a signal representing the data being read from track I head 70. More particularly, referring now to FIG. 10, peak detector suitably comprises two amplifiers 1030 and 1031 (e.g., LM393 amplifiers) and associated passive components configured to control where the upper and lower trigger points occur during operation. Schmitt trigger 18 is employed to provide a logic 1 or logic 0 (19) to microcontroller 20. More particularly, with reference to FIG. 9, Schmitt trigger 18 suitably comprises a conventional IC such as the MC74HC14AD Schmitt trigger manufactured by Motorola. Referring once again to FIG. 1, error feedback block 67 is suitably configured to provide a track I-track III error signal for use by microcontroller 20. Absolute value circuit 10 rectifies the waveform, which is then applied to the input of the peak detector 14 to produce a substantially constant voltage output. The output of peak detector 14 is then applied to the input of pseudo-log converter 16. This provides a wider dynamic range near the track I - track III "null point" to minimize the cross-talk error being presented to amplifier 8 during track II write. More particularly, referring now to FIG. 11, a preferred embodiment of the present invention includes an absolute value circuit 10 comprising an amplifier 1102 (e.g., part no. LM358A), two diodes 1104 and 1106, a second amplifier 1108, and various resistors as shown. The output of amplifier 1108 (13) is processed by peak detector 14, which in this embodiment comprises amplifier 1110 (e.g., LM358A), diodes 1112 and 1114, and various passive components as shown. The pseudo-log convertor 16 suitably comprises an amplifier 1116 used in conjunction with NPN transistor 1118 and assorted resistors as shown to produce an output 17. With reference to FIG. 1, amplifier 32 functions to amplify the output of pre- amp/filter 25 prior to Schmitt trigger 34, which produces a binary input (35) for microcontroller 20. Based on a pre-determined input signal level presented to the Schmitt trigger circuit, a hysteresis is provided to present a "solid" logic high signal or a "solid" logic low signal to microcontroller 20. Track II read data is, in this embodiment, used to verify data that has been written to track II of the magnetic stripe. Microcontroller 20 comprises any suitable component or group of components configured to carry out the various functions of the magnetic stripe encoder. In the illustrated embodiment, microcontroller 20 comprises a Motorola MC68HC711E9 or MC68S711E9 microcontroller running at a clock speed of about 2 MHZ. More particularly, referring now to FIG. 9, in a preferred embodiment microcontroller 20 interfaces with other system components through various connectors, or "headers" as shown. Many components and connectors shown in FIG. 9 are primarily used for test purposes, specifically: header 902 (microcontroller port A test point header), header 904 (microcontroller port B test point header), header 914 (supervisory circuit, microcontroller reset test point header), header 910 (microcontroller port C test point header), and header 912 (microcontroller port D test point header). With continued reference to FIG. 9, header 906 in this embodiment is used to communicate various signals to other portions of the circuit, including, for example, track II write data 42, track II read data 35, and track Ill-track II read signal 19. Header 908 is suitably used as a connection to bidirectional interface 40 (FIG. 16), header 918 is suitably used to communicate the track I-track II error signal 17, and connections to keypad 37 may be made through header 916. In addition, a master reset switch 918 is preferably provided to allow manual resetting of the device, and an array of Schmitt triggers (922) may be employed as buffers to microprocessor 20. Those skilled in the art will recognize that various other microprocessors may be used to implement the present invention, and that many of the schematic details shown in FIG. 9 may be altered or even dispensed with in alternate embodiments. Write current selector 44 is used to select the amount of current used during the write operation ~ i.e., in accordance with whether the magnetic stripe media is low coercivity or high coercivity. Write current selector preferably takes as its input track II write data 42 and write current selector 43. In the illustrated embodiment, a 330 mA write current may be selected for a high-coercivity card, and a 35 mA write current may be selected for a low-coercivity card. In a preferred embodiment, referring now to FIG. 13, current selector 44 suitably includes an analog multiplexer 1302 (e.g., a Motorola MC74HC4351) and a voltage divider section 1304 (including resistor 1312). Multiplexer 1302 receives track II write data 42 and channel selector bits 43. Three resistor pairs 1310, 1306, and 1308 are employed in conjunction with VCC and VSS to provide to supply the requisite current. In this embodiment, resistor pair 1306 is configured to provide the low-coercivity current (i.e., 35 mA), and resistor pair 1308 is configured to provide the high-coercivity current (i.e., 330 mA). A third pair (1310) provides a third current level which may be used as appropriate (in this case, a 250 mA source). The resulting write current is passed through a filter , which is used to condition ~ e.g., round off the corners of— the signal received from write current selector 44. The filtered signal (47) is then provided as input to the write output amplifier. In a preferred embodiment, filter 46 comprises a Bessel filter with a 3db point at approximately 10 kHz as described above in conjunction with FIG. 12. As mentioned briefly above, write output amplifier 64 suitably comprises amplifiers 68, 48, 53, and current sensor 50. The output of filter 46 is used as the non- inverting input to amplifier 48, the output of which enters the inverting input of amplifier 68. The two resulting signals (56) are used as the positive and negative track II write signals applied to write head 76. Current sensor 50 is then used in conjunction with amplifier 53 to produce a substantially constant write current. Referring now to FIG. 14, in a preferred embodiment of the present invention, write output amplifier 64 comprises follower side and inverter side amplifiers 1402 and 1422 respectively (e.g., LM358A devices), amplifier 1404, NPN/PNP transistor pairs 1406/1408 and 1418/1420, and diodes 1410, 1412, 1414, 1416, 1424, and 1426. In this embodiment, current sensor 50 suitably comprises a 1 ohm resistor in series with the output of follower side amplifier 48. Those skilled in the art will recognize that other current sensing circuits may be used. A fuse 1428, e.g., a 50 mA thermal fuse, is suitably used in conjunction with the supply voltage line. Keypad 37 comprises any suitable set of keys for receiving user input such as PIN numbers, account data, and the like For example, in one embodiment, keypad comprises 10 digits (0-9) as well as "clear" and "enter" keys. Other keypads, including, for example, alphanumeric keypads, custom keypads, and the like, may also be used. Biometric input 39 can be used to supply biometric data for authentication or other purposes. Biometric input 39 may used to provide, for example, information related to retina scan data, fingerprint data, face-recognition data, etc. Bi-directional interface 40 may be used as a general interface to microcontroller 20 for supplying data to be written to track II, pin offset information, and other appropriate data. Bi-directional interface 40 may interface with microcontroller 20 through various forms of communication modes, including, for example, USB, firewire, Apple Desktop Bus, and the like. Display 60 is suitably configured to provide a graphical interface to present the user with prompts and other information useful in a particular context. Display 60 may comprise, for example, a full, high resolution display or, alternatively, a single- line or multi-line LCD display. Those skilled in the art will appreciate that many other display types and sizes may be employed. Smartcard interface 58 may be used to access smartcard data, for example, any of the various smartcards conforming to the ISO-7816 standard. In this regard, smartcard interface 58 may include any of the various smartcard readers and associated software and hardware well known in the art. Supervisory reset circuit 65 operates to initiate a transaction or session as detailed further below. Power supply 61 is used to provide suitable power for both the digital and analog aspects of the magnetic stripe encoder. Any suitable conventional supply may be used to provide the necessary power levels (e.g., +/- 5VDC,+/- 7.5VDC, 12VDC, etc.) Having thus given a detailed description of the various components of a magnetic stripe encoder in accordance with the present invention, a method of using the invention will now be described in conjunction with the flowcharts shown in FIGS. 2-7 and the schematic overview shown in FIG. 1. It should be understood that the exemplary process illustrated may include more or less steps or may be performed in the context of a larger processing scheme. Furthermore, the various flowcharts presented in the drawing figures are not to be construed as limiting the order in which the individual process steps may be performed. Referring now to FIG. 2, the system generally begins with the generation of a reset signal 66 applied to Microcontroller 20 by supervisory reset circuit 65 (Step 101). This reset suitably initiates a firmware program which configures the various ports, registers, watch-dog-timer, and the like associated with microcontroller 20. Next, in step 103, a self-test of the apparatus of the system is performed, including testing of the functionality and memory of the system. During the self-test, a message is suitably presented via the display (step 105), e.g., an integrated LCD display 60 or a message sent via bi-directional interface 40 to a personal computer (PC) for display by an associated monitor. After performing the self-test (step 103), a calibration cycle suitably commences starting with adjusting the offset errors of the difference amplifiers 8 to result in a minimal offset error without a signal being applied to the write coil 76 of magnetic head 1 (step 107). In an alternate embodiment, it may be desirable to adjust the offset errors of all amplifiers in the system. A digital potentiometer attached to the difference amplifier 8 and offset adjustment 21 interfaced to microcontroller 20 may be used to provide automated adjustment. Next, in step 109, the phase and gain are suitably adjusted (e.g., through phase adjustment 23 and gain adjustment 22) to minimize crosstalk coupled to track I and track III read coils (70 and 74) when the track II write coil 76 is active. This adjustment may be performed, for example, by writing a 1 kHz square wave to Track II write coil 76 without inserting a magnetic stripe card into the apparatus card-guide slot. The microcontroller 20 generates the 1 KHz square wave via timers and suitably configured firmware residing in the microcontroller 20. Microcontroller 20 also suitably provides channel selection input to the magnetic write current selector 44 to select the desired current to be applied to the magnetic write coil 76. At this time, a graphical or text message such as "calibrating device" is preferably displayed (e.g., at display 60). Next, the system suitably slews the phase adjustment signal 23 using, for example, a digital potentiometer (step 113). In another embodiment, a manual potentiometer and a bi-color red/green LED is used for this purpose, wherein the LED being controlled by the microcontroller 20 program is at it's maximum green output when the cross-talk error signal is at a minimum. The purpose of the phase adjustment is to adjust the phase of track I signal 2 to minimize the crosstalk signal being applied via signal 7 and signal 31 of difference amplifier 8 when a calibration signal (e.g., a 1 kHz signal) is applied to write head 76. Similarly, the system adjusts the gain of difference amplifier 8 via a manual or digital potentiometer signal 22 being applied to difference amplifier 8 for various phase adjustment signals 23 being applied to pre-Amp/filter 3. The output of difference amplifier 8 is also sent to error feedback calibration circuit 67. Absolute value circuit 10 suitably rectifies input signal 9 (the output of amplifier 8) during calibration magnetic head 1 in order to minimize crosstalk errors. The output signal 13 of absolute value circuit 10 is then applied to the input of the peak detector 14 to produce a substantially constant voltage output signal 15. The signal 15 is then applied to the input of pseudo-log converter 16, thus allowing for a wider range of error output voltage signal 17 for a given change in input voltage 15 (resulting from changing phase adjustment 23 and gain adjustment 22). Microcontroller 20 continues to slew the phase adjustment 23 and gain adjustment 22 for a sufficient period of time (e.g., about 2 seconds) until the system finds a suitably minimum crosstalk error (step 115). When the minimum crosstalk error is found, the magnetic head assembly 1 is calibrated (step 119) and a message is presented to the display 60 (step 121). The system is then ready to execute the main executive loop (step 122). FIG. 3 presents the main executive loop starting point (122). The system suitably receives commands from a PC or other first processor with a suitably connected interface 41 via one or more bi-directional interface 40 bus types such as RS-232, PS/2, USB, ADB, Firewire (IEEE 1394), IEEE 488, SCSI, fiber optics, infrared, RF, and the like. One command sent to the apparatus will allow data to be written to track II by applying current to write coil 76 as the card is being swiped past magnetic head 1 (step 203). The data to be written to the write coil can be sent to the apparatus via the bi-directional bus 40 or from data entered into the apparatus via keypad 37, biometric input 39, smart card interface 57 and 58, or any combination thereof, including data that may be encrypted in the program residing in the microcontroller 20. Referring now to FIG. 4, the data to be presented to write coil 76 is suitably prepared via firmware and/or software residing in or executed by microcontroller 20 (step 302). In step 304, a user prompt such as "swipe card to erase" is preferably displayed via display 60 or other convenient display. When the user swipes his or her magnetic stripe card in the card slot of the apparatus (step 306), track I data will be read into microcontroller 20 as shown in FIG. 5, step 402. The system then determines the relative position along the magnetic stripe by keeping track of the number of flux transitions recorded during the swiping of the magnetic strip card (step 409). Additionally, the system suitably determines the speed of travel for a given card swipe for use in predicting where to write the next logic 1 or logic 0 magnetic flux transition on the magnetic stripe (step 404 and 407). This is suitably performed by utilizing an averaging technique or, alternatively, employing a Kalman filter approach to predict the location by modeling the travel distance and speed of travel of the magnetic card being swiped. With continued reference to FIG. 5, the binary data to be written to track II is determined to be either a logic 1 or logic 0 via conditional step 413. For erasing track II, either all logic 1 or all logic 0 is written to track II magnetic stripe. If the data to be written to track II is a logic 1 , the microcontroller suitably controls magnetic write output amplifier 64 to apply a flux transition (step 415), then delays a prescribed amount of time (step 417) based on the speed of travel of the magnetic stripe card the magnetic stripe bit density, e.g., 75 bits per inch bit density for a standard ISO 7811 magnetic stripe card. In accordance with an exemplary embodiment, track I information is packed on the card at a spacing of 210 bits/inch, whereas track II spacing is packed at 75 bits/inch; as a result, it is possible to determine track II location by reading the higher- density track I information. It will be appreciated that the present technique may used even in cases where there are variations in bit density, provided there are enough flux transitions being read from track I magnetic stripe to determine the position along the magnetic stripe card. With advanced prediction techniques (such as the Kalman filter) it would be possible to process segments along track I where the flux transition are not changing at a rate at least double the number of required track II flux transitions. If the binary data to write to track II is a logic 0 (as determined in step 413), then only one transition is required for a given ISO 7811-2 bit with a bit density of 75 bits per inch ±5% when measured along the line parallel to the longitudinal centerline of the track. After writing a logic 1 or logic 0 flux transition to the magnetic stripe, the program returns. Prior to writing a logic 1 or logic 0 to the magnetic stripe, the amount of current for a high-coercivity flux transition or low-coercivity flux transition is suitably determined (step 423), and a "coercivity selection type" command is sent to microcontroller 20 via bi-directional interface 40 communicating with a PC or other processor. Referring again to FIG. 4, the data will continue to be written to track II until the system in step 310 determines that all the required data (i.e., erase bits) have been written to the magnetic stripe card. It will be appreciated that to meet ISO 7811-2 encoding requirements, "lead-in" bits and last data bits to the end of the encoding (writing to file magnetic stripe) are recorded with clocking bits (logic 0). Upon completion of encoding the data to track II, a message is preferably presented via the PC monitor and/or LCD 60 prompting the user of the apparatus to swipe their magnetic swipe card again (step 313). This time, when the user swipes his or her magnetic swipe card (step 315), the new data to be written to track II will be sent to write output amplifier 64 and controlled by microcontroller 20 ~ i.e., the process described above in conjunction with FIG. 5 is repeated, except that actual data is written to track II rather than just erase bits. It should be noted that erasing the Track II data is optional, as writing over track II will effectively erase any residual flux transitions. Upon completion of encoding data to track II (step 318), another message is presented to the user to swipe his or her magnetic card a second time (step 321). The purpose of this card swipe is to verify that the data written to track II is indeed the correct data. After the card is swiped (steps 323, 211, and 326), the system compares the read track II data with the data already stored in the resident memory of microcontroller 20 — i.e., the data to be written to track II (step 329). If the comparison is not correct, the process suitably begins again starting with step 205 (FIG. 4). If the comparison is correct, however, then a message is presented to the user to the effect that verification of track II was successful (step 332), at which point the system returns (step 334). As shown in FIG. 3, another operation mode within main executive flow 122 involves reading track I and II (step 207). In general, this step involves swiping the card until complete (steps 209, 211, and 213). More particularly, an exemplary method for reading tracks I and II is presented in FIG. 6. This flow applies, for example, to the standard ISO 7811-2 encoding requirement, wherein one flux transition is a logic 0 and two flux transitions represents a logic 1. In this regard, it will be appreciated that a logic 1 is a flux transition between a timing interval (as shown in FIG. 8), while a logic 0 will have no flux transition for a given timing interval (known as "two-frequency coherent phase recording"). Thus, as shown in FIG. 6, the system suitably determines whether one magnetic flux transition has occurred (step 502) and, if so, whether two flux transactions occur (step 505). If there is no magnetic flux transition, the system returns (step 504). If, at conditional step 505, two flux transitions occur, then a logic 1 is returned; otherwise, a logic 0 is returned. This technique allows for serial recording of self-clocking data as presented in FIGS. 8A-8C. FIG. 8A presents a string of logic 0's; that is, between defined timing intervals t, there are no flux transitions. FIG. 8B, on the other hand, shows the case where flux transitions are present between timing intervals, thereby representing logical ones. FIG. 8C shows a composite example presenting logic l's and logic 0's and the corresponding logic state. In a preferred embodiment, operation of the system will conform to certain mechanical and geometric standards. For example, the angle of the recording is preferably normal to the edge of the card, parallel to the magnetic stripe within tolerances specified by ISO 7811-2. A mechanical apparatus suitably guides the card to help keep it within the "angle of recording" requirements. Optical sensor methods may also be used to detect if the card's angle remains within these requirements. ISO 7811-2 specifies that the least significant bit is encoded first and the parity bit is recorded last. The bit density for Track I is 210 bits per inch ±5%, and Track II is 75 bits per inch ±3%. To meet ISO 7811 encoding requirements, a parity bit for each encoded character is suitably used and generated in microcontroller 20. Additionally, a longitudinal redundancy check (LRC) character may be produced. The coded character set, including start sentinel, separator, and end sentinel to encoded data to Track II, is preferably in accordance with ISO 7811-2 requirements, although other coded character sets could be used if desired. It is advantageous in many contexts to authenticate the user prior to allowing data to be altered an track II of be magnetic stripe card. Commands from a PC can be sent to microcontroller 20 via bi-directional communication link 40 and 41 to request authentication of the user by one or more authentication techniques as presented in Figure 7. One purpose of authentication is to positively identify the user prior to changing the Personal Identification Number (PIN) offset previously recorded on, for example, a debit card Track II magnetic stripe. The offset can be recorded in a discretionary field of Track II beyond the standard Primary Account Number (PAN) and expiration data fields. Additionally, it is desirable in some applications to obtain information related to, for example, knowledge of a secret code, a biometric characteristic (e.g. fingerprint scan, voice scan, facial scan, iris scan, etc.) and encrypt the information prior to encoding it to the magnetic stripe of Track II. A comparison of the encrypted encoded magnetic stripe data read from the user's magnetic stripe card could later be decrypted and compared within the apparatus or at a host computer remotely connected to the apparatus for user authentication. Authentication biometric input 39 presented in FIG. 1, smart card interface 58, and other authentication parameters connected via the bi-directional interface 40 can be used to authenticate the user of the apparatus. Card swipe data read from track I and/or track II, along with a PIN entered via PIN-pad 37, is suitably used to authenticate a user prior to changing the PIN offset. Yet another purpose for the authentication inputs to the apparatus is to reduce fraudulent use of credit and debt cards or other magnetic stripe identification cards. The apparatus can be used to periodically encode encrypted information in the discretionary fields of track II that can be used in a formula resident in the apparatus configured for use as a point-of-sale terminal. The encrypted information recorded on track II is then used to generate a pass or fail authentication result based on the PAN, expiration date, and possibly other parameters. If the user is positively identified via one or more inputs, including biometric characteristics, voice prints, fingerprints, PINs, smart card digital certificates, and the like, then data is suitably recorded on the magnetic stripe card, thus indicating the user of that card has been authenticated. This newly encoded information may also be sent to a central processing location (e.g., the card issuer) which may offer lower discount transaction rates to merchants who have terminals that can offer a higher degree of authentication, especially if that merchant's terminal can encode information on track II magnetic stripe indicating that the individual has been authenticated. Known POS terminals are typically configured to read track II data and send it to the authentication processor for a cross-check. A possible advantage of this technique is the use of artificial intelligence at the authentication processor, which may include a probability of fraud based upon, inter alia, the length of time since positive identification of the user based on biometric or other authentication inputs. If the card was recently authenticated at a given location, and the authentication data was recorded on track II magnetic stripe discretionary field, then it is less likely that the current use (within a certain time and location of the last use of the card) is fraudulent. Another purpose for combining additional authentication data and the ability to encode data to track II is to allow merchants to quickly authenticate and accept credit card transactions based on how recently the card was authenticated, as well as other relevant information in the card (e.g., most recently available credit for the given credit card). This is desirably for the merchant, as it allows offline credit card authorizations that are later sent to the credit card processor for batch approval and settlement. This scheme is particularly suited to fast-food restaurants, sporting event facilities, and other locations where speed of credit card authorization is critical. The merchant could pre-program the POS terminal to analyze and set limits regarding the discretionary track II data field that would contain positive authentication data, recent spending limit, date of last track II update, and other useful information to intelligently determine if an offline credit card transaction should be authorized. Figure 7 presents three primary user authentication branches applicable to the various aspects of the present invention, including, generally: possession (602) (something that you and only you should have), knowledge (612) (e.g. something you and only you should know), and characteristic (623) (e.g. a biometric characteristic of you that should be unique to identify you and only you). If possession path is required (step 602), then the system reads the magnetic stripe card (604) as set forth above in conjunction with FIG. 6 (step 211). After which, the system returns (step 607). Alternatively, an attached smart card may be read (step 608) through smart card interface 58. If knowledge authentication is required (step 612) then the system suitably requires that a PIN be entered, for example, upon integrated keypad 37, and sent to the microcontroller 20 via link 36 (step 614). The PIN is suitably encrypted prior to sending it to the PC or other first processor (e.g. set-top box, Personal Digital Assistant, Internet Screen Phone) and then sent to a host remotely connected across possibly the Internet or other communication media (e.g, RF, cable, fiber optic) for authentication of the user. The PIN or secret code entered in step 614 could also be used to "unlock" the smart card interface 58 via link 57 to microcontroller 20 for additional security prior to allowing information to be read and/or written to the smart card. If for some reason the secret code was not entered ("no" branch from step 617), then a suitably message is presented to the user requesting reentry of the PIN (step 620). If, as shown in step 623, a "characteristic" authentication is required, the user would input the requested biometric characteristic (e.g. fingerprint scan, hand scan, facial scan, voice print, smell scan, iris scan, etc.) via interface link 38 and biometric interface 39 (step 625). The biometric characteristic is then suitably compared (step 627) with the smart card data (read in step 608) for verification of the user. The information stored in the smart card, or for that matter even Track I or Track II of a magnetic stripe card, is suitably decrypted in the apparatus for comparison with the raw biometric data acquired through biometric characteristic input interface 39 or any other interface. If there is no biometric match ("no" branch from step 628), then the user is prompted to rescan or otherwise provide the biometric data (step 629). Yet another authentication method using biometric characteristic information involves encrypting the entered biometric characteristic in microcontroller 20 prior to sending the biometric characteristic via the bi-directional interface 40 to the PC or other processor. As described above, the system may be configured such that the user swipes the card once to erase track II, swipes the card again to write to track II, then swipes the card a third time to read and verify track II. Alternatively, the system may employ three separate magnetic heads: one head to erase, a second to write to track II, and a third to read and verify the track II information. In a further embodiment of the present invention, the apparatus comprises two heads: one head to encode track II, and one head for verification. Such a system is capable of verifying and writing to track II during a single swipe. It is estimated that an apparatus embodying the present invention would be on the order of one-tenth the price of a controlled motorized version. In addition to cost- effectiveness, another benefit of the present invention is that, when used in a PC application (i.e., when the device is incorporated within a module between the keyboard and keyboard input, or is incorporated within the keyboard or mouse itself) the apparatus need not occupy an added PC card slot, thereby conserving valuable PC real estate. Furthermore, an embodiment of the present invention does not require a dedicated external power source if writing to a low-coercivity magnetic stripe card as the keyboard may supply the necessary power. In this regard, see, for example, U.S. Pat. No. 5,815,577, issued to Clark, the entire contents of which are hereby incorporated by reference. Although the invention has been described herein in conjunction with the appended drawings, those skilled in the art will appreciate that the scope of the invention is not so limited. Modifications in the selection, design, and arrangement of the various components and steps discussed herein may be made without departing from the scope of the invention as set forth in the appended claims.

Claims: CLAIMS What is claimed is: 1. A method for writing information to a magnetic stripe card, said method comprising the steps of: reading information from a first track on said magnetic stripe card; calculating the position of said magnetic stripe card based on said information read from said first track; writing to a second track on said magnetic stripe card in accordance with said position of said magnetic stripe card. 2. The method of claim 1, further comprising the steps of: canceling crosstalk arising from said writing step using flux information derived from said first track on said magnetic stripe card and a third track on said magnetic stripe card. 3. An apparatus for writing to a magnetic stripe card, said card having a first track and a second track, said apparatus comprising: a read head for reading information from said first track of said card; a write head for writing information to said second track of said card; means for calculating the position of said card with respect to said read head in accordance with said information read from said first track; 4. The apparatus of claim 3, wherein said magnetic stripe card further comprises a third track, and wherein said apparatus further comprises: a second read head for reading said third track; an amplifier circuit for canceling crosstalk arising from said writing step using flux information derived from said first track on said magnetic stripe card and said third track on said magnetic stripe card. 5. The apparatus of claim 3, further comprising a magnetic write output amplifier coupled to said write head. 6. The apparatus of claim 3, further comprising a write current selector configured to supply a current to said write head in accordance with the coercivity of said magnetic stripe card. 7. The apparatus of claim 3, wherein said calculating means comprises a microcontroller communicating with said read head. 8. The apparatus of claim 3, further comprising a biometric input. 9. The apparatus of claim 3, further comprising a smartcard interface. 10. The apparatus of claim 3, further comprising a keypad. 11. The apparatus of claim 3, further comprising a bi-directional interface. 12. The apparatus of claim 4, further comprising a calibration circuit coupled to said amplifier circuit.

Inventors: CLARK DERECK B, CLARK, DERECK, B.
Applicants: CLARK DERECK B, INNOVONICS INC, CLARK, DERECK, B., INNOVONICS, INC.
Application year: 1998
Main classification: G06K7
IPC codes: G06K1