Sequence estimation for partial response channels

Abstract: A data decoding apparatus and the method thereof are provided. When decoding a reproduction signal in a digital magnetic recording/reproducing apparatus, a Viterbi decoder comprised of a channel is constructed such that the noise level corresponds to that of an E n PR4 system and the aperture ratio of an eye pattern corresponds to that of a PR(+1, -1) system, thereby improving the efficiency of the Viterbi decoder and allowing state detection by the PR(+1, -1) system. Data can be decoded by a system having a PR4 or E n PR4 channel or selectively by other various systems.

Description: The present invention relates to data decoding, and more particularly, to a data decoding apparatus which can greatly reduce hardware size by decoding data using a maximum likelihood decoder comprised of a channel in a digital recording/reproducing apparatus having a partial-response class 4 (PR4) or extended-partial response class 4 (E n PR4) channel, and a method therefor. As a method of increasing recording density by a signal processing without greatly changing the characteristics of a conventional recording and reproducing apparatus, techniques related to a Partial Response Maximum Likelihood (PRML) have been developed, including a Viterbi decoding processing, and many specific means have been proposed. Figure 1 is a block diagram of a digital video cassette recorder (DVCR) having a PR4(1, 0, -1) channel. In Figure 1, a Non-Return-to-Zero-Inversion (NRZI) converter 102 converts an input signal into an NRZI code represented by 1 or -1. A precoder 108 converts the NRZI code into an interleave NRZI code. Here, the NRZI converter 102 and the precoder 108 are constructed to have a 1/1+D characteristic, where D refers to a 1-bit delay (unit delay) of recording data. In the NRZI converter 102 or the precoder 108 having a 1/1+D structure, an input signal and a signal delayed by a delay element 106 or 112 are XOR-performed in an XOR gate 104 or 110 to be output and the XOR-performed signal is fed back to the delay element. A reproducing amplifier 116 of a reproducing system amplifies a reproduction signal through a channel 114 having a 1-D characteristic, i.e., a differential characteristic. At this time, the amplified reproduction signal is a PR(+1, -1) mode signal. An equalizer 118 compensates for waveform distortion and amplitude distortion of the signal amplified in the reproducing amplifier 116. A channel demodulator 120 having a 1+D characteristic, i.e., an integral characteristic, converts a PR(+1, -1) mode signal output from the equalizer 118 into a PR4(+1, 0, -1) mode signal. In other words, the channel demodulator 120 includes an adder 124 and a delay 122 and has the 1+D characteristic inverse to the 1/1+D characteristic of the precoder 108, so that noise characteristics are improved and the aperture ratio of an eye pattern is decreased. A timing detector 140 detects timing of the reproduction signal equalized in the equalizer 118 using an internally installed phase locked loop (PLL) and outputs driving clocks required for the equalizer 118 and the maximum likelihood decoder 126. Here, since the recording system of the digital recording/reproducing apparatus having the PR4 channel includes two delays, the reproducing system requires four (2 2 ) 4-state Viterbi decoders. However, in the DVCR, two (1+D) channels are interleaved, 2-state Viterbi decoders are necessary. In other words, the maximum likelihood decoder 126 shown in Figure 1 is constructed such that two state detectors 130 and 132 and two Viterbi decoders 134 and 136, performing the same operation, are connected in parallel, respectively. A demultiplexer 128 and a multiplexer 138 operate according to a driving clock output from a timing detector 140. Decoded data is output from the multiplexer 138. The reason why the state detectors and the Viterbi decoders are constructed by two channels is to apply a Viterbi algorithm such that PR4(+1, 0, -1) data output from a channel demodulator 120 is converted into PR(+1, -1) data, to satisfy conditions that "0" or "-1" is read out after "+1" and "+1" is never read out and that "0" or "+1" is read out after "-1" and "-1" is never read out. Also, the DVCR having the PR4 channel shown in Figure 1 may perform decoding of data using the maximum likelihood decoding algorithm such as Viterbi decoding algorithm, which is referred to as a PRML system. Figure 2 is a block diagram of a digital recording/reproducing system having an EPR4(1, 1, -1, -1) channel having the simplest structure among E n PR4 channels, and detailed explanation of the same elements corresponding to those shown in Figure 1 will be omitted herein. A typical example of the digital recording/reproducing apparatus having the EPR4 channel is a hard disk driver. In Figure 2, compared to the PR4 system shown in Figure 1, a precoder 208 includes one more delay 214 to have a 1/(1+D) 2 characteristic, in which the precoder 208 is called an EPR4(1, 1, -1, -1) precoder. Since a recording system includes three delays 206, 212 and 214, a reproducing system requires 2 3 8-state Viterbi decoders 250 through 264 and eight state detectors 234 through 248. Also, a channel demodulator 222 includes an adder 228 and two delays 224 and 226 to have a (1+D) 2 characteristic, in correspondence with the precoder 208 having the 1/(1+D) 2 characteristic. In Figure 2, "SD" refers to a state detector and "VD" refers to a Viterbi decoder. A driving clock CK output from a timing detector 268 is supplied to a demultiplexer 232, first through eighth Viterbi decoders 250 through 264 and a multiplexer 266. Reference numerals 218 and 220 denote an amplifier and an equalizer, respectively. Figure 3 is a conceptual block diagram of a digital recording/reproducing apparatus having an E n PR4 channel. A channel demodulator 312 corresponding to a precoder 304 having a 1/(1+D) n+1 characteristic is constructed to have a (1+D) n+1 characteristic. A maximum likelihood decoder 314 includes 2 n+2 Viterbi decoders, 2 n+2 state detectors, a demultiplexer for demultiplexing outputs of the channel demodulator 312 to output to the 2 n+2 state detectors, and a multiplexer for multiplexing outputs of the 2 n+2 Viterbi decoders to output decoded data. In other words, each 2 n+2 of the state detectors and the Viterbi decoders are constructed in parallel. Demodulated data are demultiplexed into 2 n+2 channels, independently decoded by the Viterbi decoders constructed to correspond to the respective channels and then multiplexed again. This is for applying a Viterbi algorithm by separating the E n PR4 signals of the channel demodulator 312 into PR(1, -1) signals to satisfy conditions that "0" or "-1" is read after "+1" and "+1" is never read and that "0" or "+1" is read after "-1" and "-1" is never read. In the final analysis, an EPR4 system and an E 2 PR4 system have greater noise resistance noise than a PR4 system and an EPR4 system, respectively, and signal bands thereof are reduced. Thus, the recording density of a channel band is increased. However, the aperture ratio of an eye pattern is decreased and the hardware becomes complex. A conventional PR4 system requires four maximum likelihood decoders constructed in parallel (two for a DVCR), an EPR4 system requires eight maximum likelihood decoders constructed in parallel, and an E n PR4 system requires 2 n+2 maximum likelihood decoders constructed in parallel. Thus, the hardware burden becomes sharply increased. WO 97/16011 describes the addressing of data tracks in a disk drive having a partial response, maximum likelihood synchronous sampled detection channel. The described system has a PR4 channel with 1/(1+D) characteristic, with the data decoder comprising a Viterbi decoder and a channel demodulator having a (1+D) characteristic. US 5,448,424 describes an automatic gain control circuit for use with magnetic recording and reproducing apparatus, which controls an amplitude value in accordance with a set value. It is a first aim of embodiments of the present invention to provide a data decoding apparatus which can greatly decrease the hardware size by decoding data by a maximum likelihood decoder comprised of a channel while maintaining the performance of a PR4 system in view of noise, in a digital recording/reproducing apparatus having a PR4 channel. It is a second aim of embodiments of the present invention to provide a data decoding apparatus which can greatly decrease the hardware size by decoding data by a maximum likelihood decoder comprised of a channel while maintaining the performance of an E n PR4 system in view of noise, in a digital recording/reproducing apparatus having an E n PR4 channel. It is a third aim of embodiments of the present invention to provide a data decoding apparatus for selectively decoding data into a PR4 mode or an E n PR4 mode, in a digital recording/reproducing apparatus in which data is recorded in a PR4 mode. It is a fourth aim of embodiments of the present invention to provide a data decoding apparatus for decoding data into various types, in a digital recording/reproducing apparatus in which data is recorded in an E n PR4 mode. It is a fifth aim of embodiments of the present invention to provide a data decoding method for decoding data in a PR(+1, -1) state by a maximum likelihood decoder comprised of a channel while maintaining the performance of a PR4 system in view of noise, in a digital recording/reproducing apparatus having a PR4 channel. According to the present invention in a first aspect, there is provided a data decoding apparatus for a system having a PR4 channel including a precoder having a 1/(1+D) characteristic, the apparatus comprising: a maximum likelihood decoder comprised of a channel, for maximum-likelihood-decoding a PR(+1, -1) signal received through said channel to output maximum-likelihood-decoded data; and a channel demodulator having a (1+D) characteristic which is a reverse characteristic of said precoder, for channel-demodulating said maximum-likelihood-decoded data to output decoded data, wherein said maximum likelihood decoder comprises: a state detector for detecting positive and negative state values of the PR(+1, -1) signal according to positive and negative threshold values varying according to the PR(+1, -1) signal received through said channel; and a Viterbi decoder for receiving the positive and negative state values and Viterbi-decoding the same. Suitably the apparatus further comprises a pre-filter having a (1+D) characteristic, for converting the PR(+1, - 1) signal received through said channel into a PR4(+1, 0, - 1) signal; and a reverse pre-filter having a 1/(1+D) characteristic, for converting the PR4(+1,0,-1) signal received through said channel into a PR(+1,-1) signal again; wherein the maximum likelihood decoder (540, 550) is for maximum-likelihood-decoding the PR(+1, -1) signal output from said reverse pre-filter. Suitably said pre-filter comprises: a first delay (D) for delaying the PR(+1, -1) signal received through said channel by a unit value to output the delayed signal; and a first adder for adding the delayed signal to the PR(+1, -1) signal received through said channel to output a first addition signal of a PR4(+1, 0, -1) mode. Suitably said reverse pre-filter comprises: a subtractor for subtracting the positive state value from the negative state value; a second delay for delaying the output of said subtractor by a unit value to output a feed-back signal; and a second adder for adding the first addition signal to the feed-back signal to output a PR(+1, - 1) signal. Suitably said channel demodulator comprises: a D-flipflop for unit-delaying the maximum-likelihood decoded data by a unit value; and an XOR logic circuit for performing an XOR operation on the maximum-likelihood decoded data and the output of said D-flipflop. Suitably the apparatus further comprises: a sample and hold circuit for sampling and holding the PR(+1, -1) signal received through said channel; and a timing detector for detecting the timing of the PR(+1, -1) signal received through said channel to generate driving clock of said sample & hold circuit, said maximum likelihood decoder and said channel demodulator. Suitably, the apparatus further comprises: an analog-to-digital (A/D) converter for converting the PR(+1, -1) signal received through said channel into digital data; and a timing detector for detecting the timing of the PR(+1, - 1) signal received through said channel to generate driving clock of said sample & hold circuit, said maximum likelihood decoder and said channel demodulator. Suitably, the apparatus further comprises: a unit having n+1 sets connected in series, each set comprising a pre-filter, a state detector and a reverse pre-filter, each set having a pre-filter having a (1+D) characteristic, for converting the PR(+1, -1) signal received through said channel into a PR4(+1, 0, -1) signal, and a reverse pre-filter having a 1/(1+D) characteristic, for feed-back receiving the positive and negative state values, converting again the PR4(+1, 0, -1) signal into the PR(+1, - 1) signal and outputting the converted signal to said state detector; the channel demodulator comprising first and second channel demodulators, the first channel demodulator having said (1+D) characteristic which is a reverse characteristic of said precoder, for channel-demodulating the Viterbi-decoded data to output decoded data of a PR4 mode; and the second channel demodulator having a (1+D) n characteristic, for channel-demodulating the output of said first channel demodulator to output decoded data of an E n PR4 mode; and a selector for selecting one of the outputs of said first and second channel demodulators according to a PR4/E n PR4 mode signal. Suitably, said first channel demodulator comprises: a unit delay for delaying the maximum-likelihood decoded data by a unit value; and an XOR logic circuit for performing an XOR operation on the maximum-likelihood decoded data and the output of said unit delay. Suitably, said second channel demodulator comprises: n delays serially connected for n-bit delaying the output of said first channel demodulator; and an XOR logic circuit for performing an XOR operation on the outputs of said first channel demodulator and the outputs of said n delays. According to the present invention in a second aspect, there is provided a data decoding apparatus for a system having an E n PR4 channel including a precoder having a 1/(1+D) n+1 characteristic, the apparatus comprising: a unit having n+1 sets connected in series, each set comprising a pre-filter, a state detector and a reverse pre-filter, each set having a pre-filter having a (1+D) characteristic, for converting the PR(+1, -1) signal received through said channel into a PR4(+1, 0, -1) signal, a state detector for detecting positive and negative state values of the PR(+1, -1) signal depending on positive and negative threshold values varying according to the PR(+1, -1), and a reverse pre-filter for feed-back receiving the positive and negative state values, converting again the PR4(+1, 0, -1) signal into the PR(+1, -1) signal and outputting the converted signal to said state detector; a Viterbi decoder comprised of a channel, for Viterbi-decoding the PR(+1, -1) signal output from said unit and outputting the Viterbi-decoded data; and a channel demodulator having a (1+D) n+1 characteristic which is a reverse characteristic of said precoder, for channel-demodulating the Viterbi-decoded data to output decoded data. Suitably, said channel demodulator comprises: n+1 delays connected in series, for (n+1) bit-delaying the maximum-likelihood decoded data; and an XOR logic circuit for performing an XOR operation on maximum-likelihood decoded data from the Viterbi decoder and the outputs of said n+1 delays. Suitably, the first pre-filter of said unit comprises: a first delay for delaying the PR(+1, -1) signal received through said channel by a unit value to output a first delayed signal; and an adder for adding the PR(+1, -1) signal received through said channel to said delayed signal to output a first addition signal of a PR4(+1, 0, -1) mode, and wherein each of the second through (n+1)th pre-filters comprises: a delay for delaying the PR(+1, -1) signal output from the directly previous reverse pre-filter by a unit period to output a delayed signal; and an adder for adding the PR(+1, -1) signal output from the directly previous reverse pre-filter to said delayed signal to output a PR4(+1, 0, -1) signal. Suitably, each of said reverse pre-filters comprises: a subtractor for subtracting the positive state value from the negative state value output from said state detector; a second delay or delaying the output of said subtractor by a unit value to output a feed-back signal; and a second adder for adding the output signal of said precoder to the feed-back signal. Suitably, the apparatus further comprises: a sample and hold circuit for sampling and holding the PR(+1, -1) signal received through said channel; and a timing detector for detecting the timing of the PR(+1, -1) signal received through said channel to generate driving clock of said sample & hold circuit, said Viterbi decoder and said channel demodulator. Suitably, the apparatus further comprises: an analog-to-digital (A/D) converter for converting the PR(+1, -1) signal received through said channel into digital data; and a timing detector for detecting the timing of the PR(+1, - 1) signal received through said channel to generate driving clock of said sample & hold circuit, said Viterbi decoder and said channel demodulator. Suitably, m (m is an integer greater than n+1) of said sets are connected in series; and wherein the apparatus further comprises: a second channel demodulator having a (1+D) p (p = m-n-1) characteristic, for channel-demodulating the output of said first channel demodulator to output second decoded data; and a selector for selecting one of the outputs of said first and second channel demodulators according to a mode signal. According to the present invention in a third aspect, there is provided a data decoding method for use in apparatus having a PR4 channel including a precoder having a 1/(1+D) characteristic, said data decoding method comprising the steps of: (a) directly maximum-likelihood-decoding a PR(+1, -1) signal received through said channel to output maximum-likelihood-decoded data; and (b) unit-bit delaying said maximum-likelihood-decoded data to have a (1+D) characteristic which is a reverse characteristic of said precoder, adding the delayed data to the maximum-likelihood decoded data to output decoded data, wherein said step (a) comprises the steps of: (a1) detecting positive and negative state values of the PR(+1, -1) signal depending on positive and negative threshold values varying according to the PR(+1, -1) signal received through said channel; and (a2) receiving the positive and negative state values and Viterbi-decoding the same. According to the present invention in a fourth aspect, there is provided a data decoding method for use in apparatus having a PR4 channel including a precoder having a 1/(1+D) characteristic, said data decoding method comprising the steps of: (a) unit-bit delaying a PR(+1, -1) signal received through said channel to have a (1+D) characteristic, adding the delayed signal to the PR(+1, -1) signal to convert again the result into the PR4(+1, 0, -1) signal; (b) adding the PR4(+1, 0, -1) signal to a feed-back signal to have a (1+D) characteristic, to convert again the result into the PR(+1, -1) signal; (c) detecting positive and negative state values of the PR(+1, -1) signal depending on positive and negative threshold values varying according to the PR(+1, -1) signal converted in said (b) step, and outputting the feed-back signal obtained by subtracting the positive state value from the negative state value; (d) receiving the positive and negative state values and Viterbi-decoding the same to output Viterbi-decoded data; and (e) delaying the Viterbi-decoded data to have a (1+D) characteristic which is a reverse characteristic of said precoder, and adding the delayed data to the Viterbi-decoded data to output decoded data. Suitably, said (a) through (c) steps are repeated (n+1)-times; and wherein step (d) comprises Viterbi-decoding the PR(+1, -1) signal output after repeating said (a) through (c) steps (n+1)- times, and outputting the Viterbi-decoded data; and step (e) comprises unit-bit delaying the Viterbi-decoded data to have a (1+D) characteristic which is a reverse characteristic of said precoder, and adding the delayed data to the Viterbi-decoded data to output a PR4-mode decoded data; the method further comprising the steps of: (f) n-bit delaying the PR4-mode decoded data to have a (1+D) n characteristic, and adding the n-bit delayed data to the PR4-mode decoded data to output E n PR4-mode decoded data; and (g) selecting one of the PR4-mode decoded data and the E n PR4-mode decoded data according to a PR4/E n PR4 mode signal. According to the present invention in a fifth aspect, there is provided a data decoding method for use in apparatus having an E n PR4 channel including a precoder having a 1/(1+D) n+1 characteristic, said data decoding method comprising the steps of: (a) unit-bit delaying a PR(+1, -1) signal received through said channel to have a (1+D) characteristic, adding the delayed signal to the PR(+1, -1) signal to convert the result into a PR4(+1, 0, - 1) signal; (b) adding the PR4(+1, 0, -1) signal to a feed-back signal to have a (1+D) characteristic, to convert again the result into the PR(+1, -1) signal; (c) detecting positive and negative state values of the PR(+1, -1) signal depending on positive and negative threshold values varying according to the PR(+1, -1) signal converted in said (b) step, and outputting the feed-back signal obtained by substracting the positive state value from the negative state value; (d) repeating said (a) through (c) steps (n+1)-times; (e) Viterbi-decoding the PR(+1, -1) signal output after performing said (d) step, and outputting the Viterbi-decoded data; and (f) adding (n+1)-bit delayed data of the Viterbi-decoded data to the Viterbi-decoded data to have a (1+D) n+1 characteristic which is a reverse characteristic of said precoder, and outputting decoded data. Suitably, in step (d), said (a) through (c) steps are repeated m times (m is an integer greater than n+1), and wherein step (f) comprises; n+1-bit delaying the Viterbi-decoded data to have a (2+D) n+1 characteristic which is a reverse characteristic of said precoder, and adding the n+1-bit delayed data to the Viterbi-decoded data to output first decoded data decoded in an E n PR4 mode; the method further comprising the steps of: (g) p-bit delaying the first decoded data to have a (1+D) p (p = m-n-1) characteristic, adding the p-bit delayed data to the first decoded data to output a second decoded data; and (h) selecting one of the first decoded data and the second decoded data according to a mode signal. For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figure 1 is a block diagram of a conventional digital video cassette recorder having a PR4 channel; Figure 2 us a block diagram of a conventional digital recording/reproducing apparatus having an EPR4 channel; Figure 3 is a block diagram of a conventional digital recording/reproducing apparatus having an E n PR4 channel; Figure 4 is a block diagram of a data decoding apparatus according to an embodiment of the present invention; Figure 5 is a block diagram of a data decoding apparatus according to another embodiment of the present invention; Figures 6A through 6H are operational waveform diagrams of the data decoding apparatus shown in Figure 5; Figure 7 is a block diagram of a data decoding apparatus according to still another embodiment of the present invention; Figure 8 is a block diagram of a data decoding apparatus according to still yet another embodiment of the present invention; and Figures 9A through 9L are operational waveform diagrams of the data decoding apparatus shown in Figure 8. In Figure 4, a sample and hold circuit (SAMPLE & HOLD 410) samples and holds an equalized signal output from an equalizer (not shown). Here, the output state of the SAMPLE & HOLD 410 retains an analog level at the moment when sampling is performed according to driving clocks generated in a timing detector 450, not a digital level "1" or "0." A peak detector 420 is an example of an implemented state detector. In other words, a positive peak value detector 423 and a negative peak value detector 425 are examples of a positive state value detector and a negative state value detector, respectively. A positive peak value detecting threshold value (to be referred to as a positive threshold value hereinafter) and a negative peak value detecting threshold value (to be referred to as a negative threshold value hereinafter) are set in conjunction with a signal Vs output from the SAMPLE & HOLD 410 of the peak detector 420. The respective threshold values are controlled by peak detection values having opposite polarities to each other. A positive peak value (Hn) and a negative peak value (Ln) are detected from the signal equalized according to the set threshold values. In other words, a demultiplexer and an amplifier (DEMUX & AMP 421 of the peak detector 420 detects only positive (+) values from the signal Vs output from the SAMPLE & HOLD 410 to output a positive signal Va amplified in a predetermined level to a first automatic threshold controller (ATC1) 422 and the positive peak value detector 423. Also, the DEMUX & AMP 421 detects only negative (-) values from the signal Vs output from the SAMPLE & HOLD 410 to output a negative signal Vb amplified in a predetermined level to a second automatic threshold controller (ATC2) 424 and the negative peak value detector 425. The ATC1 422 automatically sets a threshold value Vra of "+1" for detecting a positive peak value in conjunction with the amplified positive signal Va output from the DEMUX & AMP 421, and resets the threshold value Vrb of "-1" to a predetermined value at the time when a negative peak value of an active state (here, logic "1") is detected from the negative peak value detector 425. The positive peak value detector 423 compares the amplified positive signal Va with the positive threshold value set by the ATC1 422 to then output a positive peak value Hn corresponding to the amplified positive signal Va and feed back the positive peak value Hn to the ATC2 424. The ATC2 424 automatically sets a threshold value Vrb of "-1" for detecting a negative peak value in conjunction with the amplified negative signal Vb output from the DEMUX & AMP 421, and resets the threshold value Vrb of "-1" to a predetermined value at the time when a positive peak value of an active state (here, logic "1") is detected from the positive peak value detector 423. The negative peak value detector 425 compares the amplified negative signal Vb with the negative threshold value set by the ATC2 424 to then output a negative peak value Ln corresponding to the amplified negative signal Vb and feed back the negative peak value Ln to the ATC1 422. The positive peak value Hn of the positive peak value detector 423 and the negative peak value Ln of the negative peak value detector 425 are digital data. However, the peak detector 420 according to the present invention can employ any configuration that positive and negative values of an input signal are detected by means of a threshold value. Alternatively, a peak detector using ATC is disclosed in an article entitled "Signal processing method PRML, achieving large capacity memory device of the next generation." in Japan Nikkei Electronics No. 599, pp. 72-79, January 1994 by Imai and Miyaki et al. The peak detector disclosed in the above article detects a positive peak value of an input signal since positive and negative peak values of the signal basically correspond to matrices in the case of a binary state number, and makes a provision for detecting the next positive peak value by retaining the detected value for being used as a new threshold value and simultaneously renews the threshold value for detecting a negative peak value. Similarly, the peak detector detects a negative peak value of an input signal, and makes a provision for detecting the next negative peak value by retaining the detected value for being used as a new threshold value and renews the threshold value for detecting a positive peak value. However, this peak detector cannot renew opposite threshold values completely at a desired time. Therefore, there has been proposed a peak detector shown in Figure 4, for better Viterbi decoding efficiency. Here, ATC means that threshold values are renewed in conjunction with the input signal. A Viterbi decoder 430 which is a PR(+1, -1) Viterbi decoder receives and Viterbi-decodes the positive peak value Hn and the negative peak value Ln detected from the peak detector 420. The Viterbi decoder 430 can take any kind of a Viterbi decoder using a Viterbi algorithm. Specifically, a Viterbi decoder which does not require an analog-to-digital (A/D) converter can be used. The configuration and operation of an analog Viterbi decoder having a shift register as a chief element is disclosed in U.S. Patent Application Serial No. 08/743,912, granted as US 5,917,863. The analog Viterbi decoder has a simple circuit, compared to a conventional one, which minimizes the area of an integrated circuit, thereby reducing the cost and power consumption. Thus, this decoder is suitable for a small-sized product necessitating low electricity such as a digital video camcorder. The data decoding apparatus shown in Figure 4 adopts an analog Viterbi decoder. In the case of adopting a conventional digital Viterbi decoder, the SAMPLE & HOLD 410 must be replaced with an A/D converter. A channel demodulator 440 having a (1+D) characteristic demodulates Viterbi-decoded data and outputs finally decoded data. Since the output of the Viterbi decoder 430 is digital data, the channel demodulator 440 may be constructed by a D-flipflop by which a delay 442 operates according to driving clock generated in a timing detector 450. An adder 441 may be constructed by an exclusive OR gate. The timing detector 450 detects timing of an equalized reproduction signal to output driving clock necessary for the SAMPLE & HOLD 410, the Viterbi decoder 430 and the channel demodulator 440. The data decoding apparatus shown in Figure 4 Viterbi-decodes the PR(+1, -1) signal whose channel is demodulated without decoding the PR4(+1, 0, -1) signal demodulated by the channel demodulator, in contrast with that shown in Figure 1. Thus, the peak detector 420 and the Viterbi decoder 430 can be comprised of only a single channel. The output of the Viterbi decoder 430 is demodulated by the channel demodulator 440 having the (1+D) characteristic and then finally decoded data is output. However, since the data decoding apparatus shown in Figure 4 detects peaks prior to channel demodulation using the (1+D) characteristic, when much noise is overlapped with the reproduction signal, errors in the positive peak value Hn and the negative peak value Ln output from the peak detector 420 are increased, thereby lowering the overall performance of the data decoding apparatus. Therefore, the data decoding apparatus shown in Figure 4 can be adopted for a recording/reproducing apparatus having a PR4 channel having good noise tolerance. Particularly, if the noise overlapped with the reproduction signal is a negligible level that cannot affect the desired performance of the decoded data, the apparatus shown in Figure 4 will have remarkable competitiveness in view of implementation simplicity and cost. However, since many factors are involved in generating noise in a magnetic recording/reproducing apparatus using a magnetic head or a magnetic tape as a channel, the level of the noise overlapped with the reproduction signal is not usually negligible. It is important to decrease the noise level in determining the data decoding efficiency. Here, the main causes of noise generation include the property of tape particles, head impedance and initial bias resistance of a reproducing amplifier. Also, since the Viterbi decoder is reached after passing through various processors including a reproducing head, reproducing amplifier and equalizer, the spectrum of the input signal varies. Figure 5 shows a data decoding apparatus comprised of one channel state detector and Viterbi decoder, capable of solving such a noise problem. A SAMPLE & HOLD 510, a peak detector 540 as an example of a state detector, a channel demodulator 560 and a timing detector 570 shown in Figure 5 are the same as the corresponding elements shown in Figure 4, and the detailed operation thereof will not be explained herein. In Figure 5, a pre-filter 520 having a (1+D) characteristic delays the output signal Vs of the SAMPLE & HOLD 510 by a period D corresponding to one bit of recorded data and adds the delayed signal with the output signal Vs of the SAMPLE & HOLD 510 in an adder 521. Since the pre-filter 520 serves as a low-pass filter, the noise characteristic is improved, but the aperture ratio of an eye pattern is decreased. The pre-filter 520 converts a PR(+1, -1) signal into a PR4(+1, 0, -1) signal. An inverse pre-filter 530 has a 1/(1+D) characteristic which is an inverted characteristic of the pre-filter 520. A subtractor 531 subtracts a positive peak value Hn output from a positive peak value detector 543 from a negative peak value Ln output from a negative peak value detector 545 in a peak detector 540. The subtraction result is delayed by a delay 532 by a period D corresponding to one bit of recorded data and then a feed-back signal Fs is fed back to an adder 533. The adder 533 adds the output of the pre-filter 520 and the feed-back signal Fs to output the result to the peak detector 540. At this time, the feed-back signal Fs is a signal having a negative value. Here, the PR4(+1, 0, -1) signal output from the pre-filter 520 is again converted into the original PR(+1, -1) signal according to a 1/(1+D) characteristic of the inverse pre-filter 530 to allow data decoding using only the peak detector 540 and the Viterbi decoder 550. In view of the noise problem, since the digital-state output of the peak detector 540 is fed back and the adder 533 adds the feed-back signal Fs with the analog output signal of the pre-filter 520 having a digital form, the noise level is almost the same as that in the conventional PR4 system having a channel demodulator in front of the state detectors and the Viterbi decoders. In other words, the data decoding apparatus shown in Figure 5 can obtain a reproduction output corresponding to a noise characteristic of the PR4(+1, 0, -1) system and corresponding to an aperture ratio of the PR(+1, -1) system. Thus, the performance of the Viterbi decoder is improved and the structure thereof is simplified, thereby becoming sufficiently competitive. Figures 6A through 6H are operational waveform diagrams of the data decoding apparatus shown in Figure 5. Figure 6A shows a waveform of an output signal Vs of the SAMPLE & HOLD 510, and Figure 6B shows a waveform of a signal obtained by delaying the output signal Vs of the SAMPLE & HOLD 510 by a one-bit period D of recorded data by the delay 522 of the pre-filter 520. Figure 6C shows a waveform of an output of the adder 521 of the pre-filter 520, Figure 6D shows a waveform of a positive peak value Hn output from the positive peak value detector 543 of the peak detector 540, Figure 6E shows a waveform of a negative peak value Ln output from the negative peak value detector 545, and Figure 6F shows a waveform of a feed-back signal Fs output from the delay 532 of the inverse pre-filter 530. Figure 6G shows a waveform of a Viterbi-decoded data output from the Viterbi decoder 550, and Figure 6F shows a waveform of a finally decoded data output from the channel demodulator 560. Figure 7 is a block diagram of a data decoding apparatus which can be adopted to a digital recording/reproducing apparatus having an E n PR4 channel. For convenience of explanation, an EPR4 mode will be described as an example. The explanation of the same elements as those shown in Figure 5 will be omitted herein. The main difference between the systems of the present invention and the conventional EPR4 system shown in Figure 2 lies in the fact that the former is comprised of a 1-state detector and a Viterbi decoder and the latter is comprised of 8 (2 3 ) state detectors and 8 Viterbi decoders. Also, a channel demodulator 690 is disposed in the rear end of the Viterbi decoder 680 to have a (1+D) 2 characteristic to correspond to the precoder of the EPR4 system, having a 1/(1+D) 2 characteristic. The data decoding apparatus of Figure 7 includes a first pre-filter 620 having a (1+D) characteristic to cope with the noise characteristic of the EPR4 system, a first reverse pre-filter 630 having a 1/(1+D) characteristic which is reverse to that of the pre-filter 620, a first peak detector 640 for detecting a positive peak value and a negative peak value from the output of the first reverse pre-filter 630 to feed back the same to the first reverse pre-filter 630, a second pre-filter 650 for converting the output of the first reverse pre-filter 630 into a PR4(+1, 0, -1) signal, a second reverse pre-filter 660 for converting the output of the second pre-filter 650 into a PR(+1, -1) signal, and a second peak detector 670 for detecting a positive peak value and a negative peak value from the output of the second reverse pre-filter 660 to feed back the same to the second reverse pre-filter 660. Thus, the data decoding apparatus employs a one-channel Viterbi decoder such that the signal input to the Viterbi decoder 680 is made to take a PR(+1, -1) form while maintaining the noise level of the EPR4 system by using two pre-filters 620 and 650 and two reverse pre-filters 630 and 660. Here, the data decoding apparatus adopted to the digital recording/reproducing apparatus having an E n PR4 channel includes n+1 pre-filters having a (1+D) characteristic, n+1 reverse pre-filters having a 1/(1+D) characteristic, and a channel demodulator having a (1+D) n+1 characteristic in the rear end of a Viterbi decoder. Since the data decoding apparatus adopted to an E n PR4 system has a magnetic channel having a (1-D) characteristic, the output thereof takes a PR(1, -1) signal form, which meets a requirement of a Viterbi decoding algorithm. Thus, the goal of the present invention is to use a one-channel Viterbi decoder using this reproduction signal as a decoding signal without being converted into another form signal. In this case, conventionally, since the signal does not pass through the channel demodulator having a lowpass filter characteristic, i.e., (1+D) n+1 , the effect of noise is severe, which lowers the efficiency of the decoding apparatus. However, according to the present invention, the output signal of a peak detector, having digital information, is fed back and a reverse pre-filter for adding the output signal of the peak detector to that of a pre-filter having a lowpass filter characteristic (1+D) is constructed in front of a Viterbi decoder, thereby improving the noise level to a level of the EPR4(1, 1, -1, - 1) system while maintaining the signal of the data decoding apparatus as a PR(+1, -1) state. Thus, the data decoding apparatus in a recording/reproducing system having a magnetic channel can be very easily implemented. Also, according to the present invention, as shown in Figures 5 and 7, the data decoding apparatus can be constructed to cope with only the system of a PR4 mode or an E n PR4 mode. Otherwise, as shown in Figure 8, the data decoding apparatus can be constructed to cope with various type systems. Figure 8 is a block diagram of a data decoding apparatus having a PR4 channel which can selectively reproduce a signal into a PR4 signal or an EPR4 signal, in which the same elements as those shown in Figure 7 will not explained in detail. For convenience of explanation, an EPR4 mode will be described as an example of an E n PR4 mode. In Figure 8, a first reverse pre-filter 730 converts the output signal of a first pre-filter, being a PR4(1, 0, - 1) mode, into a PR(+1, -1) mode signal. A second pre-filter 750 and a second reverse pre-filter 760 are constructed in the same manner as the first pre-filter 720 and the first reverse pre-filter 730, to cope with an EPR4 decoder. A first channel demodulator 790 has a (1+D) characteristic and the output thereof is decoded data for a PR4 system to be input to a first input port of a selector 810. A second channel demodulator 800 connected to an output port of the first channel demodulator 790 has a (1+D) characteristic and the output thereof is decoded data for an EPR4 system to be input to a second input port of the selector 810. The selector 810 selects the output of the first channel demodulator 790 if the signal is a PR4 mode signal, and selects the output of the second channel demodulator 800 if the signal is an EPR4 mode signal, according to a mode signal PR4/EPR4. Therefore, if data is decoded by the EPR4 system shown in Figure 8 in a digital recording/reproducing apparatus having a PR4 channel, noise characteristics are improved and the aperture ratio of an eye pattern is also increased. Thus, the present invention can be applied to a system which requires excellent decoding efficiency. Also, referring to Figure 8, in the digital recording/reproducing apparatus having a PR4 channel, data decoding is selectively performed in a PR4 mode or an EPR4 mode. Here, by adding a precoder and a reverse pre-filter, data decoding can be selectively performed in various types such as E 2 PR, E 3 PR and E 4 PR. Also, data decoding can be performed by constructing pre-filters and reverse pre-filters more than n+1 in a digital recording/reproducing apparatus having an E n PR4 channel, thereby improving noise characteristics and increasing the aperture ratio of an eye pattern. Figures 9A through 9L are operational waveform diagrams of the data decoding apparatus shown in Figure 8, illustrating a process of decoding a reproduction signal input to the Viterbi decoder 780 in the case when no noise is overlapped with a channel. In detail, Figure 9A shows a waveform of a signal Vs output from the SAMPLE & HOLD 710, Figure 9B shows a waveform of a signal produced by delaying the signal Vs output from the SAMPLE & HOLD 710 by the delay 722 of the first pre-filter 720, Figure 9C shows a waveform of an output signal of the first pre-filter 720, and Figure 9D shows a waveform of a feed-back signal Fsl output from the delay 732 of the first reverse pre-filter 730. The feed-back signal Fsl is detected from the output signal of the peak detector 740. Thus, this signal is a signal converted into a digital level. Since the feed-back signal Fsl does not includes analog noise, the first reverse pre-filter 730 can perform a 1/(1+D) operation without increasing noise. Figure 9E shows a waveform of an output signal of the first reverse pre-filter 730, Figure 9F shows a waveform of a signal produced by delaying the output of the first reverse pre-filter 730 by the delay 752 of the second pre-filter 750, Figure 9G shows a waveform of a positive peak value Hn output from the second positive peak value detector 773, and Figure 9H shows a waveform of a negative peak value output from the second negative peak value detector 775. Figure 9I shows a waveform of a feed-back signal Fs2 output from the delay 762 of the second reverse pre-filter 760, Figure 9J shows a waveform of decoded data output from the Viterbi decoder 780, Figure 9K is a waveform of an output signal of the first channel demodulator 790, and Figure 9L shows a waveform of an output signal of the second channel demodulator 800. In systems according to the present invention, an embodiment having a PR4(+1, 0, -1) channel such as a digital magnetic recording/reproducing apparatus, when a reproduction signal is decoded by a Viterbi decoding method, is constructed such that the noise level corresponds to that of a PR4(+1, 0, -1) system and the aperture ratio of an eye pattern corresponds to that of a PR(+1, -1) system. Thus, a state detector and a Viterbi decoder are constructed into one channel, such that the efficiency of the Viterbi decoder is improved, compared to that of a PR4(+1, 0, -1) system, and state detection is allowed by a PR(+1, -1) system. In other words, remarkable competitiveness can be secured in view of easy implementation and manufacturing cost. Also, in a system having an E n PR4 channel such as a digital magnetic recording/reproducing apparatus, when a reproduction signal is decoded by a Viterbi decoding method, the system is constructed such that the noise level corresponds to that of an E n PR4 system and the aperture ratio of an eye pattern corresponds to that of a PR(+1, -1) system. Thus, a Viterbi decoder comprised of one channel is constructed, such that the efficiency of the Viterbi decoder is improved and state detection is allowed by the PR(+1, -1) system. In other words, remarkable competiveness can be secured in view of easy implementation and manufacturing cost. Further, embodiments of the present invention have the effect of selectively decoding data in various types in addition to each type in a system having a PR4 channel or an E n PR4 channel.

Claims: A data decoding apparatus for a system having a PR4 channel including a precoder having a 1/(1+D) characteristic, the apparatus comprising: a maximum likelihood decoder (420, 430; 540, 550) comprised of a channel, for maximum-likelihood-decoding a PR(+1, -1) signal received through said channel to output maximum-likelihood-decoded data; and a channel demodulator (440; 560; 790, 800) having a (1+D) characteristic which is a reverse characteristic of said precoder, for channel-demodulating said maximum-likelihood-decoded data to output decoded data, wherein said maximum likelihood decoder comprises: a state detector (420; 540; 740, 770) for detecting positive and negative state values of the PR(+1, -1) signal according to positive and negative threshold values varying according to the PR(+1, -1) signal received through said channel; and a Viterbi decoder (430; 550) for receiving the positive and negative state values and Viterbi-decoding the same. An apparatus as claimed in claim 1, the apparatus further comprising a pre-filter (520) having a (1+D) characteristic, for converting the PR(+1, -1) signal received through said channel into a PR4(+1, 0, -1) signal; and a reverse pre-filter (530) having a 1/(1+D) characteristic, for converting the PR4(+1,0,-1) signal received through said channel into a PR(+1,-1) signal again; wherein the maximum likelihood decoder (540, 550) is for maximum-likelihood-decoding the PR(+1, -1) signal output from said reverse pre-filter. An apparatus as claimed in claim 2, wherein said pre-filter (520) comprises: a first delay (D) for delaying the PR(+1, -1) signal received through said channel by a unit value to output the delayed signal; and a first adder (521) for adding the delayed signal to the PR(+1, -1) signal received through said channel to output a first addition signal of a PR4(+1, 0, -1) mode. An apparatus as claimed in claim 2 or claim 3, wherein said reverse pre-filter (530) comprises: a subtractor (531) for subtracting the positive state value from the negative state value; a second delay (532) for delaying the output of said subtractor (531) by a unit value to output a feed-back signal; and a second adder (533) for adding the first addition signal to the feed-back signal to output a PR(+1, -1) signal. An apparatus as claimed in any one of claims 2, 3, or 4,wherein said channel demodulator (560) comprises: a D-flipflop (562) for unit-delaying the maximum-likelihood decoded data by a unit value; and an XOR logic circuit (561) for performing an XOR operation on the maximum-likelihood decoded data and the output of said D-flipflop (562). An apparatus as claimed in any one of the above claims, the apparatus further comprising: a sample and hold circuit (410; 510) for sampling and holding the PR(+1, -1) signal received through said channel; and a timing detector (450; 570) for detecting the timing of the PR(+1, -1) signal received through said channel to generate driving clock of said sample & hold circuit (410; 510), said maximum likelihood decoder (420, 430; 540, 550) and said channel demodulator (440; 560). An apparatus as claimed in any one of the above claims, the apparatus further comprising: an analog-to-digital (A/D) converter for converting the PR(+1, -1) signal received through said channel into digital data; and a timing detector (450; 570) for detecting the timing of the PR(+1, -1) signal received through said channel to generate driving clock of said sample & hold circuit (410; 510), said maximum likelihood decoder (420, 430; 540, 550) and said channel demodulator (440; 560). An apparatus as claimed in claim 1, the apparatus further comprising: a unit having n+1 sets connected in series, each set comprising a pre-filter (720; 750), a state detector (740; 770) and a reverse pre-filter (730; 760), each set having a pre-filter (720; 750) having a (1+D) characteristic, for converting the PR(+1, -1) signal received through said channel into a PR4(+1, 0, -1) signal, and a reverse pre-filter (730; 760) having a 1/(1+D) characteristic, for feed-back receiving the positive and negative state values, converting again the PR4(+1, 0, -1) signal into the PR(+1, - 1) signal and outputting the converted signal to said state detector (740; 770); the channel demodulator comprising first and second channel demodulators, the first channel demodulator (790) having said (1+D) characteristic which is a reverse characteristic of said precoder, for channel-demodulating the Viterbi-decoded data to output decoded data of a PR4 mode; and the second channel demodulator (800) having a (1+D) n characteristic, for channel-demodulating the output of said first channel demodulator (790) to output decoded data of an E n PR4 mode; and a selector (810) for selecting one of the outputs of said first and second channel demodulators (790, 800) according to a PR4/E n PR4 mode signal. An apparatus as claimed in claim 8, wherein said first channel demodulator comprises: a unit delay (792) for delaying the maximum-likelihood decoded data by a unit value; and an XOR logic circuit (791) for performing an XOR operation on the maximum-likelihood decoded data and the output of said unit delay (792). An apparatus as claimed in claim 8 or claim 9, wherein said second channel demodulator (800) comprises: n delays (802) serially connected for n-bit delaying the output of said first channel demodulator (790); and an XOR logic circuit (801) for performing an XOR operation on the outputs of said first channel demodulator (790) and the outputs of said n delays (802). A data decoding apparatus for a system having an E n PR4 channel including a precoder having a 1/(1+D) n+1 characteristic, the apparatus comprising: a unit having n+1 sets connected in series, each set comprising a pre-filter (620; 650), a state detector (640; 670) and a reverse pre-filter (630; 660), each set having a pre-filter (620; 650) having a (1+D) characteristic, for converting the PR(+1, -1) signal received through said channel into a PR4(+1, 0, -1) signal, a state detector (640; 670) for detecting positive and negative state values of the PR(+1, -1) signal depending on positive and negative threshold values varying according to the PR(+1, -1), and a reverse pre-filter (630; 660) for feed-back receiving the positive and negative state values, converting again the PR4(+1, 0, -1) signal into the PR(+1, -1) signal and outputting the converted signal to said state detector (640; 670); a Viterbi decoder (680) comprised of a channel, for Viterbi-decoding the PR(+1, -1) signal output from said unit and outputting the Viterbi-decoded data; and a channel demodulator (690) having a (1+D) n+1 characteristic which is a reverse characteristic of said precoder, for channel-demodulating the Viterbi-decoded data to output decoded data. An apparatus as claimed in claim 11, wherein said channel demodulator (690) comprises: n+1 delays (682, 693) connected in series, for (n+1) bit-delaying the maximum-likelihood decoded data; and an XOR logic circuit (691) for performing an XOR operation on maximum-likelihood decoded data from the Viterbi decoder (680) and the outputs of said n+1 delays (682, 693). An apparatus as claimed in claim 8 or claim 11, wherein the first pre-filter (620; 720) of said unit comprises: a first delay (622; 722) for delaying the PR(+1, -1) signal received through said channel by a unit value to output a first delayed signal; and an adder (621; 721) for adding the PR(+1, -1) signal received through said channel to said delayed signal to output a first addition signal of a PR4(+1, 0, -1) mode, and wherein each of the second through (n+1)th pre-filters (650; 750) comprises: a delay (652; 752) for delaying the PR(+1, -1) signal output from the directly previous reverse pre-filter (630; 730) by a unit period to output a delayed signal; and an adder (651; 751) for adding the PR(+1, -1) signal output from the directly previous reverse pre-filter (630; 730) to said delayed signal to output a PR4(+1, 0, -1) signal. An apparatus as claimed in any one of claims 8, 11 or 13, wherein each of said reverse pre-filters (630, 660; 730, 760) comprises: a subtractor (631, 661; 731, 761) for subtracting the positive state value from the negative state value output from said state detector (640, 670; 740, 770); a second delay (632, 662; 732, 762) for delaying the output of said subtractor (731, 761) by a unit value to output a feed-back signal; and a second adder (623, 663; 733, 763) for adding the output signal of said precoder (620, 650; 720, 750) to the feed-back signal. An apparatus as claimed in any one of claims 8, 11, 13 or 14, the apparatus further comprising: a sample and hold circuit (610; 710) for sampling and holding the PR(+1, -1) signal received through said channel; and a timing detector (700; 800) for detecting the timing of the PR(+1, -1) signal received through said channel, to generate driving clock of said sample & hold circuit (610; 710), said Viterbi decoder (680; 780) and said channel demodulator (690; 790, 800). An apparatus as claimed in any one of claims 8, 11, 13, 14 or 15, further comprising: an analog-to-digital (A/D) converter for converting the PR(+1, -1) signal received through said channel into digital data; and a timing detector (700; 800) for detecting the timing of the PR(+1, -1) signal received through said channel to generate driving clock of said sample & hold circuit (610; 710), said Viterbi decoder (680; 780) and said channel demodulator (690; 790, 800). An apparatus as claimed in claim 11, wherein: m, m is an integer greater than n+1, of said sets are connected in series; and wherein the apparatus further comprises: a second channel demodulator (800) having a (1+D) p , p = m-n-1, characteristic, for channel-demodulating the output of said first channel demodulator to output second decoded data; and a selector (810) for selecting one of the outputs of said first and second channel demodulators according to a mode signal. A data decoding method for use in apparatus having a PR4 channel including a precoder having a 1/(1+D) characteristic, said data decoding method comprising the steps of: (a) directly maximum-likelihood-decoding a PR(+1, -1) signal received through said channel to output maximum-likelihood-decoded data; and (b) unit-bit delaying said maximum-likelihood-decoded data to have a (1+D) characteristic which is a reverse characteristic of said precoder, adding the delayed data to the maximum-likelihood decoded data to output decoded data, wherein said step (a) comprises the steps of: (a1) detecting positive and negative state values of the PR(+1, -1) signal depending on positive and negative threshold values varying according to the PR(+1, -1) signal received through said channel; and (a2) receiving the positive and negative state values and Viterbi-decoding the same. A data decoding method for use in apparatus having a PR4 channel including a precoder having a 1/(1+D) characteristic, said data decoding method comprising the steps of: (a) unit-bit delaying a PR(+1, -1) signal received through said channel to have a (1+D) characteristic, adding the delayed signal to the PR(+1, -1) signal to convert again the result into the PR4(+1, 0, -1) signal; (b) adding the PR4(+1, 0, -1) signal to a feed-back signal to have a (1+D) characteristic, to convert again the result into the PR(+1, -1) signal; (c) detecting positive and negative state values of the PR(+1, -1) signal depending on positive and negative threshold values varying according to the PR(+1, -1) signal converted in said (b) step, and outputting the feed-back signal obtained by subtracting the positive state value from the negative state value; (d) receiving the positive and negative state values and Viterbi-decoding the same to output Viterbi-decoded data; and (e) delaying the Viterbi-decoded data to have a (1+D) characteristic which is a reverse characteristic of said precoder, and adding the delayed data to the Viterbi-decoded data to output decoded data. A method as claimed in claim 19, wherein said (a) through (c) steps are repeated (n+1)-times; and wherein step (d) comprises Viterbi-decoding the PR(+1, -1) signal output after repeating said (a) through (c) steps (n+1)- times, and outputting the Viterbi-decoded data; and step (e) comprises unit-bit delaying the Viterbi-decoded data to have a (1+D) characteristic which is a reverse characteristic of said precoder, and adding the delayed data to the Viterbi-decoded data to output a PR4-mode decoded data; the method further comprising the steps of: (f) n-bit delaying the PR4-mode decoded data to have a (1+D) n characteristic, and adding the n-bit delayed data to the PR4-mode decoded data to output E n PR4-mode decoded data; and (g) selecting one of the PR4-mode decoded data and the E n PR4-mode decoded data according to a PR4/E n PR4 mode signal. A data decoding method for use in apparatus having an E n PR4 channel including a precoder having a 1/(1+D) n+1 characteristic, said data decoding method comprising the steps of: (a) unit-bit delaying a PR(+1, -1) signal received through said channel to have a (1+D) characteristic, adding the delayed signal to the PR(+1, -1) signal to convert the result into a PR4(+1, 0, -1) signal; (b) adding the PR4(+1, 0, -1) signal to a feed-back signal to have a (1+D) characteristic, to convert again the result into the PR(+1, -1) signal; (c) detecting positive and negative state values of the PR(+1, -1) signal depending on positive and negative threshold values varying according to the PR(+1, -1) signal converted in said (b) step, and outputting the feed-back signal obtained by substracting the positive state value from the negative state value; (d) repeating said (a) through (c) steps (n+1)-times; (e) Viterbi-decoding the PR(+1, -1) signal output after performing said (d) step, and outputting the Viterbi-decoded data; and (f) adding (n+1)-bit delayed data of the Viterbi-decoded data to the Viterbi-decoded data to have a (1+D) n+1 characteristic which is a reverse characteristic of said precoder, and outputting decoded data. A method as claimed in claim 21, wherein in step (d), said (a) through (c) steps are repeated m times (m is an integer greater than n+1), and wherein step (f) comprises; n+1-bit delaying the Viterbi-decoded data to have a (1+D) n+1 characteristic which is a reverse characteristic of said precoder, and adding the n+1-bit delayed data to the Viterbi-decoded data to output first decoded data decoded in an E n PR4 mode; the method further comprising the steps of: (g) p-bit delaying the first decoded data to have a (1+D) p , p = m-n-1, characteristic, adding the p-bit delayed data to the first decoded data to output a second decoded data; and (h) selecting one of the first decoded data and the second decoded data according to a mode signal.

Inventors: JEON JIN-KYU, SOICHI IWAMURA, JEON, JIN-KYU, SOICHI, IWAMURA
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1998
Main classification: H04L25
IPC codes: G11B20, H04L25, H03M13