Motion vector detection apparatus

Abstract: In a motion vector detection apparatus, cascade-connected processor elements each calculates the absolute value of the difference between each of a plurality of pixels which compose a picture and a corresponding one of the same number of pixels included in a block, and also performs cumulative addition of the difference absolute values in the block. These operations are performed for each of the blocks within the predetermined search area. A comparative means repeatedly compares the cumulative addition values of two blocks obtained sequentially in the processor element at the final stage, and selects the smaller one of the cumulative addition values. A subtracter compares the smaller cumulative addition value with a setting value. When the smaller cumulative addition value is smaller than the setting value, a control circuit halts the supply of clock signals to the processor elements and the comparison means, so as to halt the entire operations of the apparatus. Consequently, the power consumption can be reduced.

Description: The present invention relates to an improvement of a motion vector detection apparatus which detects motion vectors used for the prediction in motion compensation prediction, which is one of the motion picture compression techniques. In transmitting and storing motion picture having a large amount of data, the motion picture compression techniques are inevitable to reduce the large amount of data. The motion picture compression techniques include a compression technique called motion compensation prediction. According to the motion compensation prediction, the level of data redundancy in motion picture is lowered in the direction of the time axis by extracting the displacement between two highly-correlated pictures, so as to compress the amount of data. The displacement between the highly-correlated pictures in the motion compensation is referred to as a motion vector, which is generally detected by a block matching method. The block matching method is briefly described with reference to Fig. 4. The block matching method is a method of evaluating the correlation between two pictures in predetermined block units. In Fig. 4, when a motion vector for a block (previous picture) 502 on Picture A 501 is detected, an evaluation value is calculated for each one of a plurality of blocks within a predetermined search area 504 on Picture B 503. As a result of the calculation, when block X 505 shown in Fig. 4 has turned out to have the best evaluation value (the highest correlation), the displacement from the position on Picture B 503 on which the previous picture block 502 is projected to block X 505 is detected as a motion vector 506. As the evaluation value indicative of the degree of correlation, a total sum is generally used which is obtained by cumulatively adding the absolute value of the difference between each of the pixels included in a block and a spatially corresponding one of the same number of pixels included in another block. As the evaluation value is smaller, the two blocks have a smaller difference, that is, higher correlation. As a conventional motion vector circuit for detecting motion vectors by the above-mentioned block matching method, there is a well-known technique disclosed in Japanese Laid-Open Patent Application No. 7-184210. Another conventional block-matching algorithm is described in Ki-Chul Nam, Soo-Ik Chae: "A full-search block-matching algorithm with early retirement of processing elements", Journal of the Korean Institute of Tefematics and Electronics, Nov. 1995, South Korea, vol. 32b, no. 11, pp. 53-59. A motion vector is estimated by parallel processing using a 1-D systolic array having N processing elements. The motion vector detection process is divided into a first step of "finding a sum of absolute differences" and the second step of "comparing the obtained sums". In the first step, each of the N processing elements computes a sum of absolute differences between a reference block and one of the candidate blocks of a search window. Each processing element computes the sum of absolute differences for a particular candidate block. In the second step, the calculated sums are compared in order to detect a minimum. For reducing the required power consumption and processing time, the operation of particular processing elements is terminated before all differences are calculated and accumulated if it turns out that an accumulated partial sum already exceeds the current minimum. As only a row of candidate blocks is processed at a time, the processing proceeds to the next row of candidate blocks if the operation of all processing elements is terminated. YIN CHAN et al in "bit level block matching systolic arrays", Proc. The International Conference On Application Specific Array Processors, 24-26 JULY 1995, IEEE Computing Soc. Press describe a computation process for calculating mean absolute errors in a block-matching circuit by utilizing a bit-level systolic array. Two approaches are suggested. According to the LSB approach, a difference between two pixel values is calculated in a first step. In a second step, the difference values are accumulated. Alternatively, an MSB approach is employed for calculating and accumulating the difference values simultaneously. By disabling processing elements associated with lower significant bits in the bit-level systolic array power consumption is reduced while accepting a loss of picture quality in the coding process. Fig. 1 shows the entire structure of a motion vector detection apparatus, where one block includes 256 pixels, and each pixel has an 8-bit value. The apparatus shown in Fig. 1 includes cascade-connected processor elements (hereinafter PEs) 601 which are as many as the pixels included in one block: 256, a bus R 602 for transferring the pixel data of one block within the search area 504, a bus S 603 for transferring the pixel data of the previous picture block 502, a clock line 604 for supplying each of the PEs 601 with an operation clock, and a comparison means 605 for receiving an output of the PE at the final stage and comparing the previous value and the current value of the output. Fig. 5 show the conventional internal structure of each of the PEs 601 in the above-mentioned motion vector detection apparatus. The apparatus shown in Fig. 5 includes a difference absolute value calculator 610 for calculating the absolute value of the difference of the pixel data to be transferred via the bus R 602 and the bus S 603, an adder 611 for adding an output value of the difference absolute value calculator 610 and an output value of the PE at the previous stage together and for outputting the addition results to the PE at the following stage, a register 612 for storing the pixel data of the previous picture block to be transferred via the bus S 603, a pipeline register 613 for pipeline processing the calculations of the difference absolute value calculator 610 and the adder 611, and a pipeline register 614 for pipeline processing the calculation of the adder 611 of each of the PEs 601. The operations of the above-mentioned motion vector detection apparatus will be described as follows. The leading pixel data in the previous picture block 502 are stored in the register 612 and then transferred to the difference absolute value calculator 610 in the PE at the first stage (PE0). Also, the leading pixel data of a block (for example, block X 505) within the search area 504 are transferred to the difference absolute value calculator 610 in the PE at the first stage. The difference absolute value calculator 610 calculates the difference absolute value between the received two pixel data, and transfers the calculation results to the pipeline register 613. The adder 611 receives the difference absolute value from the register 613 and transfers it to the pipeline register 614 at the following stage, so that the difference absolute value is transferred to the PE at the next stage (PE1). Then, the second pixel data following the above-mentioned leading pixel data in the previous picture block 502 are transferred to the PE at the second stage (PE1). Also, the next pixel data in the block X 505 within the search area 504 are transferred to the PE at the second stage. In the PE at the second stage, the difference absolute value between these two pixel data is calculated and the results are stored in the pipeline register 613 in the same manner as in the PE at the first stage. Furthermore, in the PE at the second stage, the adder 611 adds the difference absolute value of the leading pixel data transferred from the PE at the first stage and the difference absolute value of the second pixel data together. The results are stored in the pipeline register 614 and then transferred to the PE at the third stage (PE2). These operations are repeated hereafter until the total sum of the difference absolute values between all the pixels in the previous picture block 502 and in block X 505 within the search area 504 is obtained in the PE at the final stage (PE255). These operations are sequentially performed for every block within the search area 504 although Fig. 4 shows only one other block Y 507. The comparison means 605 receives the total sum of the difference absolute values outputted from the PE at the final stage, compares the total sum in the previous block (for example, block X 505) and the total sum in the current block (for example, block Y507), and chooses the smaller of the two total sums. When the total sums of the difference absolute values in all the blocks within the search area 504 have been calculated and compared, the comparison means 605 obtains the smallest total sum, and outputs, as a motion vector, the displacement between the block having the smallest total sum and the previous picture block 502. However, the above-mentioned conventional motion vector detection apparatus has drawbacks of demanding huge power consumption because of a large amount of calculation processing needed and of requiring large circuit scales. These drawbacks will be detailed as follows. In Fig. 4, Picture A 501 is one of the 30 pictures displayed in one second and its size is 720 pixels×480 lines in the case of standard TV motion picture. Since the standard size of the previous picture block 502 is 16 pixels×16 lines in the motion vector detection used for the motion compensation prediction of the motion picture compression, the number of blocks included within the search area 504 amounts to 1024. Under these conditions, the number of blocks subject to the block matching amounts to 40,500 (=720×480×30÷16÷16) per second. A block matching performed for each block requires 262,144 (=1,024×16 ×16) times of calculations for the difference absolute values and the total sums. Consequently, the motion vector detection by the block matching method requires as many as 10,616,832,000 (=40,500 × 262,144) times of calculates per second for the difference absolute values and the total sums, which demands huge power consumption. In order to perform the calculations of the difference absolute values and the addition of these difference absolute values (total sum) with a high precision, it is necessary to make the difference absolute value calculator, the adder, the pipeline register, and other units in each PE have large bit widths. It is also inevitable to provide as many as 256 PEs each including these units, which leads to undesirable expansion of the circuit scales. The object of the present invention is to provide a motion vector detection apparatus which has reduced circuit scales and detects motion vectors with low power consumption. This object is achieved by the features of claim 1. Further embodiments are subject-matter of dependent claims. In order to achieve the object, the present invention has the following features. In the motion compensation prediction, when a motion vector is a displacement between the previous picture block and a block which has sufficiently high correlation with the previous picture block, even if it is not the block having the highest correlation, the level of data redundancy between the pictures can be lowered sufficiently and motion pictures can be compressed at a high compression rate. These features bring about the following effects. Firstly, in calculating the evaluation values of a plurality of blocks within a search area, if it is possible to obtain an evaluation value which is not the best, but is as good as the best evaluation value, in other words, if the evaluation value does not need to have a precision (resolution) higher than indicating the level of correlation, the bit width of the adder and other units in each PE can be reduced, and accordingly both the circuit scales and the power consumption can be reduced. Secondly, in calculating the total sum of the difference absolute values of pixels with the use of a plurality of PEs, a predetermined setting value (threshold value) can be set as the addition results of the adder in each PE, and when calculated addition results exceed the setting value, that is, when low correlation can be predicted before the total sum is obtained, the useless addition processing of the difference absolute values in the remaining PEs can be halted. As a result, the power consumption can be reduced. When the cumulative addition value of the difference absolute values finally obtained in the comparison means is a value close to the smallest value, the block having the close value can be used as a block having sufficient correlation in detecting a motion vector so as to lower the level of the data redundancy between pictures sufficiently, and to compress the motion pictures at a high compression rate. Since the addition means in each PE has a small bit width, the circuit scale can be small, which accordingly reduces the power consumption. When the addition results of the adder exceed the setting value in a PE, or when low correlation is predicted before the total value is finally obtained by continuing the remaining addition, the useless addition processing of the difference absolute values in the remaining PEs is halted, which reduces the power consumption. Fig. 1 shows the entire structure of the motion vector detection apparatus of the first embodiment useful for the understanding of the present invention. Fig. 2 shows the structure of a PE which is a component of the motion vector detection apparatus of the same. Fig. 3 shows the structure of a PE of the motion vector detection apparatus of the second embodiment of the present invention. Fig. 4 shows a diagram which illustrates the block matching method. Fig. 5 shows the structure of a PE which is a component of a conventional motion vector detection apparatus. Each preferred embodiment of the present invention will be described as follows with reference to the attached drawings. Figs. 1 and 2 show the motion vector detection apparatus of a first embodiment useful for the understanding of the present invention. Since the entire structure of the apparatus shown in Fig. 1 has been described above, the following description will be focused on the internal structure of a PE which is a component of the apparatus with reference to Fig. 2. The PE shown in Fig. 2 includes a difference absolute value calculator 110 for calculating the absolute value of a difference value so as to output an 8-bit difference absolute value, an adder (addition means) 111, a register 112 which is connected with B terminal of the difference absolute value calculator 110 and receives the pixel data of the previous picture block 502 shown in Fig. 5, a pipeline register 113 which is disposed on the side of the output of the difference absolute value calculator 110, and a pipeline register 114 which is disposed on the side of the output of the adder 111. In each of the PEs 601 of the present embodiment, only the high-order 4 bits of an 8-bit difference absolute value are entered to the adder 111 via the pipeline register 113. Therefore, the adder 111 and the two pipeline registers 113 and 114 have 4-bit widths. Of a difference absolute value outputted from the difference absolute value calculator 110, the low-order 4 bits are truncated and only the high-order 4 bits are entered to the adder 111, and as a result, a processing means 10 outputs a high-order 4-bit difference calculation value. The processing means 10 composes a restriction means for putting restrictions on the calculation in the adder 111 in a PE. The operations of the motion vector detection apparatus of the present embodiment will be described as follows. The absolute value of a difference between a pixel in the previous picture block 502 stored in the register 112 and a pixel in block X 505 which spatially corresponds to the pixel is calculated in the difference absolute value calculator 110, and the high-order 4 bits of the calculated difference absolute value are stored in the pipeline register 113. The difference absolute value stored in the pipeline register 113 and an output of the adder 111 (the sum of the difference absolute values) in the PE at the previous stage are added together by the adder 111 in the PE at the current stage. The addition results are then stored in the pipeline register 114. In each PE, the low-order 4 bits of a difference absolute value obtained in the difference absolute value calculator 110 are truncated, so that a value obtained as a result of dividing the difference absolute value of the difference absolute value calculator 110 by 16 is stored in the pipeline register 113 while the high-order 4-bit difference absolute value is given to the adder 111. Consequently, in the motion vector detection apparatus of the present embodiment, the total sum of the values each obtained as a result of dividing the difference absolute value by 16 is outputted to the PE at the final stage. As a result, the total sum has a lower precision (resolution) than its equivalent in the conventional apparatus, but is sufficiently indicative of the level of correlation, so that a motion vector obtained based on this total sum can be used for the motion compensation prediction to obtain a sufficiently high compression rate. Another advantage of the present embodiment is that the adder 111 and the pipeline registers 113 and 114 have as small as a 4-bit width, as compared with the 8-bit width in the conventional apparatus, so that the circuit scale can be small. Furthermore, the power consumption is reduced according to the reduction of the circuit scale. To be more specific, the circuit scales of the pipeline register 113, the adder 111, and the pipeline register 114 in the present embodiment can be 50%, 75%, and 75%, respectively, of those of their equivalents in the conventional motion vector detection apparatus. Although the low-order 4 bits of an output of the difference absolute value calculator 110 are truncated in the present embodiment, it goes without saying that the reduction of the bit width can be also achieved by rounding off to a predetermined bit of the output. A second embodiment of the present invention will be described based on Fig. 3. The description of the entire structure of the motion vector detection apparatus of the present embodiment will be omitted because the structure is the same as that of the first embodiment shown in Fig. 1. Fig. 3 shows the internal structure of one of the PEs. The PE shown in Fig. 3 includes a difference absolute value calculator 210, an adder 211, a register 212, and pipeline registers 213 and 214. While the conventional adder 611 shown in Fig. 9 has a 16-bit width, the adder 211 of the present embodiment is composed of a calculator with a smaller bit width, such as a 10-bit width. The adder 211 outputs an overflow signal 215 when a calculated value is larger than the maximum value (threshold value) which can be expressed in the 10-bit width. An OR circuit 216 receives the overflow signal 215 from the adder 211 and an output signal of the PE at the previous stage (not shown) via the signal path 216a, and ORs these signals. The output of the OR circuit 216 is transferred to the OR circuit in the PE at the next stage (not shown) via the pipeline register 217. A transition prohibition means 218 receives the overflow signal 215 from the adder 211 so as to prohibit the transition of the data stored in the pipeline register 214 which is at the stage following the adder 211. When the adder 211 in a PE outputs a value larger than the above-mentioned threshold value, the transition prohibition means 218 in the PE at the next stage prohibits the transition of the data stored in the pipeline register 214 of the PE at the current stage, based on the overflow signal 215. As a result, a forced halt means 20 is formed which forcibly halts the cumulative addition of the difference absolute values in the PE at and after the next stage by ignoring the addition results of the adder 211 at the current stage, and which transfers overflow signals from the PEs at the current and previous stages to the PE at the following stage via the OR circuit 216 and the pipeline register 217. The following is a description of the operations of the motion vector detection apparatus of the present embodiment. The adder 211 outputs the overflow signal 215 when its calculation results are equal to or larger than the threshold value, which is the maximum value that can be expressed in 10 bits. The OR circuit 216 ORs the overflow signal 215 from the adder 211 and the overflow signal 215 from the PE at the previous stage, and transfers the results to the PE at the next stage via the pipeline register 217. In each PE, when the overflow signal 215 is transferred from the PE at the previous stage, the transition prohibition means 218 prohibits the transition of the data stored in the pipeline register 214 by halting the supply of a clock signal or by another method. As a result, when the calculated value is equal to or larger than the threshold value, the calculation of the total sum hereafter is halted, which realizes the reduction of the power consumption. In the next time, the calculation of the total sum of the difference absolute values is performed with regard to each of the remaining blocks (for example, block Y 507 shown in Fig. 5) within the search area 504. Then, the displacement between the block having the smallest total sum and the previous picture block is detected as a motion vector. When the total sum calculation is halted based on the overflow signal 215, the evaluation value outputted from the PE at the final stage becomes indefinite value. However, this indefinite evaluation value can be prevented from being mistakenly regarded as the smallest evaluation value, by making the comparison means 605 receive the overflow signal 215 and making the indefinite value be excluded from the comparison target. When the adder 211 has a 10-bit width in the present embodiment, the circuit scales of the adder 211 and the pipeline register 214 can be 62.5% of those of their equivalents in the conventional motion vector detection apparatus. The data transition in the pipeline register 214 in the PE at the current stage is prohibited by the overflow signal 215 in the PE at the previous stage in the present embodiment. However, by prohibiting the pipeline register 213 in the PE at the current stage from performing data transition by means of the overflow signal 215 in the PE two stages before, it becomes possible to prohibit the adder 211 from performing useless calculation in the PEs after the current stage and also to prohibit the pipeline register 213 from performing data transition. Furthermore, by prohibiting the transition of a signal entered to A terminal of the difference absolute value calculator 210 at the current stage by means of the overflow signal 215 in the PE three stages before, it becomes possible to prohibit the difference absolute value calculator 210 from performing useless calculation in the PEs after the current stage. As a result, the power consumption can be further reduced. Each of the above-mentioned embodiments can obtain the effects of reducing the circuit scales and the power consumption independently, so that any of the embodiments can be combined to enhance the effects.

Claims: A motion vector detection apparatus for detecting correlation between a picture (502) consisting of a plurality of pixels and a plurality of blocks (505-507) each consisting of the same number of pixels as said picture (502), the plurality of blocks (505-507) being included within a predetermined search area (504) containing a larger number of pixels than said picture (502), said motion vector detection apparatus comprising: a plurality of processor elements (601) being cascade-connected, the number of processor elements (601) corresponding to the number of pixels included in said picture (502), wherein each processor element (601) calculates difference absolute values between a pixel of said picture (502) and corresponding pixels included in the plurality of blocks (505-507) and accumulates a calculated difference absolute value and an accumulation result received from a processing element (601) of the previous stage within the cascade-connection of processor elements (601), a comparison means (605) for repeatedly comparing accumulated difference absolute values of two of the plurality of blocks (505-507) by subtraction, the accumulated difference absolute values being obtained in a processor element (601) at a final stage, and for repeatedly selecting a smaller accumulated difference absolute value, characterized in that each processor element (601) comprises a forced halt means (20) for forcibly halting the accumulation of difference absolute values at following stages when an accumulation result of said processor element (601) being larger than the maximum value which may be expressed by the number of bits used for the accumulation result of said processor element (601). A motion detection apparatus according to claim 1, wherein the processor element (601) outputs an overflow signal (215) when the accumulation result being larger than the maximum value which may be expressed using the number of predetermined bits, and said forced halt means (20) receives the overflow signal (215) from a processor element (601) of a previous stage, ignores additional results calculated within the processor element (601) and transfers the overflow signal (215) from the current stage or previous stage to a processing element (601) of the next stage.

Inventors: AOKI KATSUJI, ARAKI TOSHIYUKI, AOKI, KATSUJI, ARAKI, TOSHIYUKI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1998
Main classification: G06T7
IPC codes: H04N7, G06T7