Output circuit

Abstract: An output circuit comprising a first type field effect transistor (P1) having a channel of one conductivity, having a gate connected a first node, having a first electrode connected a first power supply and having a second electrode connected a second node, a second type field effect transistor (P2) having a channel of one conductivity, having a gate connected a third node, having a first electrode connected said second node, having a second electrode connected a fourth node and having a substrate connected a fifth node which is floating, a third type field effect transistor having a channel of one conductivity, having a gate connected a sixth node, having a first electrode connected said third node, having a second electrode connected said fourth node and having a substrate connected said fifth node, a fourth type field effect transistor (N3) having a channel of the opposite conductivity, having a gate connected said sixth node, having a first electrode connected said third node and having a second electrode connected a second power supply, and an inverter means having an input terminal connected said fourth node and an output terminal connected said sixth node.

Description: This invention relates to an output circuit, more specifically an output circuit which can be built-in in an integrated circuit or an IC. The output circuits belonging to this invention are output circuits which acts as an interface employable for outputting a voltage signal to an external circuit which works under a power supply of which the voltage is e.g. 5V which is higher than the voltage e.g. 3V which is the voltage of a power supply under which the output circuit works. The ultimate purpose of this invention is to provide output circuits which are possible to output such voltage signals quickly with a higher speed without consuming a large amount of electric power. More precisely, the output circuits belong to the first group of this invention are output circuits which are possible to increase the potential level of such an output signal at least to the level of the voltage e.g. 3V which is the voltage of a power supply employed in the output circuits, very quickly, without consuming a large amount of electric power. BACKGROUND OF THE INVENTION An output circuit allowable to be built-in in an integrated circuit and which is available in the prior art and an input circuit allowable to be built-in in an integrated circuit and which is available in the prior art will be described below, referring to drawings. Referring to Figs. 1 and 2, an output circuit allowable to be built-in in an integrated circuit and which is available in the prior art has an open drain circuit consisting of an n channel normally on type field effect transistor (N101) connected a pull-up resister (R 1 ) through a "PAD" of the IC in which the output circuit is built-in. The pull-up resister (R 1 ) is arranged outside the IC and works under a power supply Vcc of e.g. 5V, despite the output circuit works under a power supply of e.g. 3V. The n channel normally on type field effect transistor (N101) has a function to reduce the voltage applied between the source and the drain of the n channel normally on type field effect transistor (N102). Fig. 2 shows that the voltage of the output signal very slowly increases up to the voltage of Vcc or 4V in this example, in excess of the voltage level of the voltage signal which is outputted from this output circuit and which is shown by (IN). It is noted that a very long time is required for transmission of a voltage signal having a potential level of e.g. 3V to an external circuit which works under a power supply of a higher voltage of e.g. 5V. Incidentally, it is noted the output circuit can be employed as the output circuit of an IC having a less amount of dielectric strength. Referring to Figs. 3 and 4, an input circuit allowable to be built-in in an integrated circuit and which is available in the prior art has an n channel normally on type field effect transistor (N100) which has a function to reduce the voltage of an input signal which is inputted through a "PAD" of the IC and which has a voltage range of zero through 5V to a voltage range ranging from zero to the voltage difference between the V DD voltage or the power supply voltage of circuit and the threshold voltage of the n channel normally on type field effect transistor (N100), before forwarding the input signal to the next stage circuit produced the IC. Therefore, the input circuit can be employed for an integrated circuit having a less amount of dielectric strength. The threshold voltage of the IC is designed to be less than that of the ordinary input circuit. In the drawing, "PAD" means the bonding pad for the input circuit. Fig. 4 shows the voltage of an input signal received at an input terminal (IN) is reduced to the potential level of the node (Y), before being applied to an amplifier and forwarded to the next stage circuit. In the first place, referring to Fig. 2, the output signal outputted from the output circuit illustrated in Fig. 1 increases at a rate determined by a time constant which is further determined by the amount of the pull-up resister (R 1 ). This means that if a high operation speed is required, a less amount of the pull-up resister (R 1 ) is required. If the amount of the pull-up resister (R 1 ) is made less, the power consumption increases accordingly, vice versa. This is a drawback inevitably involved with the foregoing output circuit available in the prior art, described referring to Figs. 1 and 2. In the second place, supposing the power supply voltage of the input circuit illustrated in Fig. 3 or the V DD is 3V, an input signal of 5V inputted into the input circuit through the "PAD" is reduced to a value which is V DD less the threshold voltage of the n channel normally on type field effect transistor (N100), (V DD - V th ) or approximately 2.3V, before being applied to the node (Y). Accordingly, it is not easy for such an input circuit to satisfy the requirement of VIH, which is a regulation inspecting whether or not an "H" level voltage issued by an input circuit has a sufficient amount of margin with respect to the threshold value of the internal circuit of the input circuit. This is a drawback inevitably involved with the foregoing input circuit available in the prior art, described referring to Figs. 3 and 4. OBJECTS AND SUMMARY OF THE INVENTION Accordingly, an object of this invention is to provide output circuits which are allowed to be built-in in an integrated circuit and which can output voltage signals into an external circuit which works under a power supply of which the voltage is higher than the voltage of a power supply under which the output circuits work, with a higher operation rate and without consuming a large amount of electric power. An output circuit according to the present invention is defined in claim 1. The dependent claims define embodiments of the invention. connected the first power supply, having a first electrode connected the thirteenth node and having a second electrode connected the fourth node are newly introduced. BRIEF DESCRIPTION OF THE DRAWINGS This invention, together with its various features and advantages, can be readily understood from the following more detailed description presented in conjunction with the following drawings, in which : Fig. 1 is a circuit diagram of an output circuit available in the prior art, Fig. 2 is a timing chart illustrating the time-wise move of the potential at the input and output terminals, Fig. 3 is a circuit diagram of an input circuit available in the prior art, Fig. 4 is a timing chart illustrating the time-wise move of the potential at the input terminal and the node (Y), Fig. 5 is a circuit diagram of an output circuit in accordance with a first example, Fig. 6A is a timing chart illustrating the time-wise move of the potential of some terminals and nodes of an output circuit in accordance with the first example, Fig. 6B is a timing chart illustrating the time-wise move of the current flowing in the power supply of an output circuit in accordance with the first example, Fig. 7 is a circuit diagram of an output circuit in accordance with a second example, Fig. 8A is a timing chart illustrating the time-wise move of the potential of some terminals and nodes of an output circuit in accordance with the second example, Fig. 8B is a timing chart illustrating the time-wise move of the current flowing in the power supply of an output circuit in accordance with the second example, Fig. 9 is a circuit diagram of an output circuit in accordance with a first embodiment of this invention, Fig. 10A is a timing chart illustrating the time-wise move of the potential of some terminals and nodes of an output circuit in accordance with the first embodiment of this invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIRST EXAMPLE An output circuit having an advantage in which the rising rate of an output signal is large until it arrives at the voltage of the power supply employed in the output circuit, even if the resistance of a pull-up resister is large. It is to be noted that the first and second examples described hereinafter are exemplary examples only which do not fall under the scope of the claims. Referring to Fig. 5, an output circuit which is allowable to be built-in in an integrated circuit in accordance with a first example of this invention is composed of an input terminal (IN), an enable input terminal (EB), an output terminal (OUT) arranged on a pad of the integrated circuit in which the output circuit is built-in, a NAND gate (NAND 1 ) having two input ports, a NOR gate (NOR 2 ) having two input ports, p channel normally off FETs (P 1 ) through (P 5 ), n channel normally off FETs (N 1 ) and (N 3 ) and inverters (INV 1 ) and (INV 2 ). The voltage of a power supply V DD is e.g. 3V. The output terminal (OUT) is a terminal through which a voltage signal is outputted out of the integrated circuit in which the output circuit is built-in toward an external circuit. One end of a pull-up resister arranged outside the integrated circuit is connected the output terminal (OUT). The function of the pull-up resister of which the other end is connected a power supply of the external circuit of which the power supply Vcc is e.g. 5V, is to pull-up the potential of the output terminal (OUT) to the voltage e.g. 5V. The first input terminal of the NAND gate (NAND 1 ) is connected the input terminal (IN), and the second input terminal of the NAND gate (NAND 1 ) is connected the enable input terminal (EB), and the output terminal of the NAND gate (NAND 1 ) is connected an internal node (PG). The first input terminal of the NOR gate (NOR 2 ) is connected the input terminal (IN), and the second input terminal of the NOR gate (NOR 2 ) is connected the enable input terminal (EB) via the inverter (INV 1 ). The output terminal of the NOR gate (NOR 2 ) is connected an internal node (NG). The input terminal of the inverter (INV 2 ) is connected the output terminal (OUT), and the output terminal of the inverter (INV 2 ) is connected an internal node (OUTN). The gate electrode of an n channel normally off FET (N 1 ) is connected the node (NG), the drain electrode of the n channel normally off FET (N 1 ) is connected the output terminal (OUT), and the source electrode of the n channel normally off FET (N 1 ) is connected the ground potential (GND). The gate electrode of the n channel normally off type FET (N 3 ) is connected the node (OUTN), the drain of the n channel normally off type FET (N 3 ) is connected the internal node (G), and the source electrode of the n channel normally off type FET (N 3 ) is connected the ground potential (GND). The gate electrode of the p channel normally off FET (P 1 ) is connected the node (PG), the source electrode of the p channel normally off FET (P 1 ) is connected the internal power supply (V DD ) and the drain electrode of the p channel normally off FET (P 1 ) is connected an internal node (S). The gate electrode of a p channel normally off FET (P 2 ) is connected the node (G), the drain electrode of a p channel normally off FET (P 2 ) is connected the output terminal (OUT), and the source electrode of the p channel normally off FET (P 2 ) is connected the node (S). The gate electrode of a p channel normally off FET (P 3 ) is connected the node (G) and the source electrode of the p channel normally off FET (P 3 ) is connected the node (S). The gate electrode of a p channel normally off FET (P 4 ) is connected the node (OUTN), the drain electrode of the p channel normally off FET (P 4 ) is connected the node (G) and the source electrode of the p channel normally off FET (P 4 ) is connected the output terminal (OUT). The gate electrode of a p channel normally off FET (P 5 ) is connected the internal power supply (V DD ) and the Source electrode of the p channel normally off FET (P 5 ) is connected the output terminal (OUT). The p channel normally off FETs (P 2 ), (P 3 ), (P 4 ) and (P 5 ) are produced in one common n well (B) or a bulk (B) which is floating from the internal power supply (V DD ) and from the ground potential (GND). The drain electrodes of the p channel normally off FETs (P 3 ) and (P 5 ) are connected the floating bulk (B). The source of the p channel normally off FET (P 1 ) is connected the internal power supply (V DD ) and the sources of the n channel normally off FETs (N 1 ) and (N 3 ) are connected the ground potential (GND). The drain electrode of the p channel normally off FET (P 2 ), the source electrodes of the p channel normally off FETs (P 4 ) and (P 5 ), the drain electrode of the n channel normally off FET (N 1 ) and the input terminal of the inverter (INV 2 ) are connected the output terminal (OUT). The gate electrodes of the p channel normally off FETs (P 2 ) and (P 3 ), the drain electrode of the p channel normally off FET (P 4 ) and the drain electrode of the n channel normally off FET (N 3 ) are connected the node (G). The drain electrode of the p channel normally off FET (P 1 ) and the source electrodes of the p channel normally off FETs (P 2 ) and (P 3 ) are connected the node (S). The output terminal of the inverter (INV 2 ) and the gate electrodes of the p channel normally off FET (P 4 ) and the n channel normally off FET (N 3 ) are connected the node (OUTN). Supposing the enable input terminal (EB) is set to an "L" level or 0V, the operation of the output circuit in accordance with the first example will be described below. Referring to Fig. 5, regardless the polarity of a signal applied to the input terminal (IN), the output level of the NAND gate (NAND 1 ) or the potential of the node (PG) is "H" or e.g. 3V. As a result, the p channel normally off FET (P 1 ) is in an OFF position. Since the output level of the inverter (INV 1 ) is "H", the output level of the NOR gate (NOR 2 ) or the potential of the node (NG) is "L", resultantly turning off the n channel normally off FET (N 1 ). In this manner, provided the enable input terminal (EB) is set an "L" level, both the p channel normally off FET (P 1 ) and n channel normally off FET (N 1 ) are OFF and the impedance of the output terminal (OUT) is high, regardless the potential level of the input terminal (IN). Thus the potential level of the output terminal (OUT) is identical to the potential level of the external power supply (Vcc) or 5V, due to the external pull-up resister (R 1 ). Since the potential level of the output terminal (OUT) is "H" or 5V, the output level of the inverter (INV 2 ) or the potential level of the node (OUTN) is "L". As a result, the n channel normally off FET (N 3 ) is OFF. Since the potential level of the node (OUTN) is "L", and since the potential level of the output terminal (OUT) is 5V, the p channel normally off FET (P 4 ) is ON. As a result, the potential level of the node (G) is identical to the potential level of the output terminal (OUT) or 5V. Since the potential level of the output terminal (OUT) is 5V, the p channel normally off FET (P 5 ) is ON, because the source thereof is connected the output terminal (OUT) of which the potential level is 5V and because the gate thereof is connected the internal power supply (V DD ) which is 3V. As a result, the potential level of a floating bulk (B) is identical to the potential level of the output terminal (OUT) or 5V. Since the potential level of both the output terminal (OUT) and of the node (G) is 5V, the p channel normally off FET (P 2 ) is OFF. Since the potential level of both the output terminal (OUT) and of the floating bulk (B) is 5V, the p channel normally off FET (P 3 ) is OFF. Since the p channel normally off FETs (P 2 ) and (P 3 ) are OFF, the impedance level of the drain electrode of the p channel normally off FET (P 1 ) or the node (S) is high. This prevents an electric current from flowing from the output terminal (OUT) toward the internal power supply (V DD ) through the node (S) and through the bulk of the p channel normally off FET (P 1 ). Since the floating bulk (B) is not connected the internal power supply (V DD ), no leak current is allowed to flow from the floating bulk (B) toward the internal power supply (V DD ) through the drain of the p channel normally off FET (P 2 ) and the sources of the p channel normally off FETs (P 4 ) and (P 5 ). Since the input terminal of the inverter (INV 2 ) is connected the gate of a MOS FET (not shown) constituting the inverter (INV 2 ), the impedance level thereof is high. The drain of the n channel normally off FET (N 1 ) and the bulk of the n channel normally off FET (N 1 ) are connected in a counter bias, the impedance level of the drain of the n channel normally off FET (N 1 ) is high. Therefore, no electric current is allowed to flow from the output terminal (OUT) toward the ground (GND). Supposing the enable input terminal (EB) is set an "H" level or 3V, the operation of the output circuit in accordance with the first example will be described below. Referring to Fig. 5, provided an "L" level signal or 0V is applied to the input terminal (IN), the NAND gate (NAND 1 ) outputs an "H" level signal to make the potential level of the node (PG) an "H" level or 3V. As a result, the p channel normally off FET (P 1 ) is OFF. The NOR gate (NOR 2 ) outputs an "H" level signal to make the potential level of the node (NG) an "H" level. As a result, the n channel normally off FET (N 1 ) is ON. As a result, the potential level of the output terminal (OUT) is "L" or OV. The potential level of the output terminal of the inverter (ENV 2 ) or of the node (OUTN) is "H" or 3V. Since the potential level of the node (OUTN) is "H", the n channel normally off FET (N 3 ) is ON, and the p channel normally off FET (P 4 ) is OFF. Since the n channel normally off FET (N 3 ) is ON, the potential level of the node (G) is "L". Since the potential level of the output terminal (OUT) and of the node (G) is "L", the p channel normally off FET (P 2 ) is OFF. Since the potential level of the node (S) is less than the threshold value of the p channel normally off FET (P 3 ), the p channel normally off FET (P 3 ) is OFF. It is noted, however, provided the potential level of the output terminal (OUT) is "L" and provided the potential level of the node (S) is higher than the threshold value of the p channel normally off FETs (P 2 ) and (P 3 ), the p channel normally off FETs (P 2 ) and (P 3 ) turn on to decrease the potential level of the node (S) down to the threshold value of the p channel normally off FETs (P 2 ) and (P 3 ) and to finally turn on the p channel normally off FETs (P 2 ) and (P 3 ). Since the potential level of the output terminal (OUT) is "L", the p channel normally off FET (P 5 ) is OFF. Provided an "H" level signal is applied to the input terminal (IN), the output level of the NAND gate (NAND 1 ) or the potential level of the node (PG) is shifted to "L", resultantly turning on the p channel normally off FET (P 1 ). The output level of the NOR gate (NOR 2 ) or the potential level of the node (NG) is shifted to "L" from "H", resultantly turning off the n channel normally off FET (N 1 ). Since the p channel normally off FET (P 1 ) has turned on, the potential level of the node (S) is increased to the potential level of the internal power supply (V DD ) or 3V. Since the potential level of the node (G) is "L", the p channel normally off FETs (P 2 ) and (P 3 ) turn on. Since the p channel normally off FET (P 2 ) has turned on, the potential level of the output terminal (OUT) increases up to the level of the internal power supply (V DD ) or 3V. Since the p channel normally off FET (P 3 ) has turned on, the potential level of the floating bulk (B) increases up to the level of the internal power supply (V DD ) or 3V. The function of the p channel normally off FET (P 3 ) is to increase the potential level of the floating bulk (B) precisely up to the level of the internal power supply (V DD ) or 3V, resultantly securing the stable operation of the p channel normally off FET (P 2 ). Since the potential level of the output terminal (OUT) has increased to the potential level of the internal power supply (V DD ) or 3V, the output potential of the inverter (INV 2 ) or the potential of the node (OUTN) shifts to an "L" level, resultantly turning off the n channel normally off FET (N 3 ) and turning on the p channel normally off FET (P 4 ). Since the p channel normally off FET (P 4 ) has turned on, the potential level of the node (G) shifts to an "H" level or the potential level of the output terminal (OUT). As a result, the p channel normally off FETs (P 2 ) and (P 3 ) turn off. In the foregoing manner, the output terminal (OUT) is connected the external power supply (Vcc) or 5V. As a result, the potential of the node (G) increases to 5V, causing the p channel normally off FET (P 5 ) to turn on and the potential of the floating bulk (B) to shift to 5V. In the foregoing manner, provided the potential level of the enable input terminal (EB) is "H", and provided the input terminal (IN) is inputted an "H" level signal, the p channel normally off FETs (P 2 ) and (P 3 ) are OFF, similarly to the case where the enable input terminal (EB) is "L". Since the impedance level of the p channel normally off FET (P 1 ) or the node (S) is high, no leak current flows to the internal power supply (V DD ) from the output terminal (OUT) through the node (S) and the bulk of the p channel normally off FET (P 1 ). Since the floating bulk (B) is not connected the internal power supply (V DD ), no leak current flows to the internal power supply (V DD ) from the floating bulk through the drain of the p channel normally off FET (P 2 ) and through the sources of p channel normally off FETs (P 4 ) and (P 5 ). Since the input terminal of the inverter (INV 2 ) is connected the gate of a MOS FET (not shown) constituting the inverter (INV 2 ), the impedance level thereof is high. Since the drain and the bulk of the n channel normally off FET (N 1 ) are applied a counter bias each other, the impedance level of the drain of the n channel normally off FET (N 1 ) is high as well. Accordingly, no leak current flows from the output terminal (OUT) to the ground (GND). Referring to Figs. 6A and 6B, the potential of the output terminal (OUT) quickly rises up to the potential level of the internal power supply (V DD ), regardless the amount of the pull-up resister (R 1 ) arranged in the external circuit This means that quick operation is allowed for the output circuit in accordance with the first example, without decreasing the amount of the pull-up resister (R 1 ) arranged in the external circuit for the purpose to expedite the operation of the output circuit. Thereafter, however, the potential of the output terminal (OUT) continues increasing up to the potential level of the external power supply (Vcc) or 5V. As a result, no electric current flows toward the internal power supply (V DD ), excepting the period in which the output voltage rises up to the potential level of the internal power supply (V DD ). As a result, when being employed as art interface with an external circuit which works with a power supply of 5V, the output circuit in accordance with the first embodiment of this invention is allowed to work with a high speed until the output voltage rises up to the threshold voltage (V th ) of the external circuit or approximately 2.5V. As a result, the VIH of the external circuit or 3.5V can be guaranteed. It is particularly noted that although a reduction of the pull-up resister (R 1 ) was essential for an output circuit available in the prior art to enhance the operation speed and to decrease power consumption, a power consumption is decreased for the output circuit in accordance with the first example, because a reduction of the pull-up resister (R 1 ) is unnecessary to enhance the operation speed. It is needless to emphasize that 5V representing the voltage of an external circuit is an example and the first example is allowed to be employed for all the cases where the external voltage is higher than the internal voltage. The foregoing description has clarified that an output circuit having an advantage in which the rising rate of an output signal is large until it arrives at the voltage of the power supply employed in the output circuit, even if the resistance of a pull-up resister is large, has successfully been provided by the first example. SECOND EXAMPLE An output circuit having an advantage in which the rising rate of an output signal is large until it arrives at the voltage of the power supply employed in the output circuit, even if the resistance of a pull-up resister is large, wherein a delay circuit is introduced, for the purpose to delay the time at which the p channel normally off FET (P 2 ) or the second MOS FET turns off and to shorten the time required for the potential of the output terminal (OUT) to increase up to the potential level of V DD or the potential of the first power supply, resultantly enhancing the operation speed of the output circuit Referring to Fig. 7, an output circuit which is allowable to be built-in in an integrated circuit in accordance with a second example is composed of an input terminal (IN), an enable input terminal (EB), an output terminal (OUT) arranged on a pad of the integrated circuit in which the output circuit is built in, a NAND gate (NAND 1 ) having two input ports, a NOR gate (NOR 2 ) having two input ports, p channel normally off FETs (P 1 ) through (P 5 ), n channel normally off FETs (N 1 ) and (N 3 ), inverters (INV 1 ) and (INV 2 ) and a delay element (DL 1 ). A pull-up resister (R 1 ) arranged in an external circuit is connected the output terminal (OUT). The circuit illustrated in Fig. 7 is the circuit illustrated in Fig. 5 to which a delay element (DL 1 ) is added between the node (OUTN) and the gate of the p channel normally off FET (P 4 ). As a result, the gate of the p channel normally off FET (P 4 ) is not connected the node (OUTN) but a node (OUTND). The input terminal of the delay element (DL 1 ) is connected the node (OUTN), and the output terminal thereof is connected the node (OUTND). As a result, in response to a shift of the potential level of the node (OUTN) from "H" to "L", the delay element (DL 1 ) suspends the action to shift the potential level from "H" to "L" by the period set on the delay element (DL 1 ). Although the operation of the output circuit illustrated in Fig. 7 is similar to that of the output circuit illustrated in Fig. 5, the operation is different from that of the output circuit illustrated in Fig. 5 for the operation to be conducted on the conditions that the enable input terminal (EB) is set at an "H" level and the potential level of the input signal of the input terminal (IN) is shifted from "L" to "H", as is described below. Referring to Fig. 7, if the input signal applied to the input terminal (IN) is shifted from "L" to "H" to increase the potential level of the output terminal (OUT) up to the level of the internal power supply (V DD ) or 3V, the potential level of the output terminal of the inverter (INV 2 ) or of the node (OUTN) shifts from "H" to "L" to turn off the n channel normally off FET (N 3 ). Referring to Figs. 8A and 8B, the delay element (DL 1 ) delays the transfer of the "L" level from the node (OUTN) to the node (OUTND) by a predetermined length of time. As a result, the p channel normally off FET (P 4 ) does not turn on simultaneously with the n channel normally off FET (N 3 ) but turns on at the time which is later than the time at which the potential level of the node (OUTN) is shifted to "L" by a predetermined length of time. This delays the time at which the p channel normally off FET (P 4 ) turns on and the time at which the p channel normally off FETs (P 2 ) and (P 3 ) turn off. In the foregoing manner, the length of period in which the p channel normally off FET (P 4 ) is OFF is definitely prolonged, causing the adjustment procedure to be simple and easy. As a result, since the length of period in which the p channel normally off FET (P 2 ) is ON is prolonged, the operation speed of the output circuit in accordance with the second embodiment of this invention is further enhanced. The foregoing description has clarified that an output circuit having an advantage in which the rising rate of an output signal is large until it arrives at the voltage of the power supply employed in the output circuit, even if the resistance of a pull-up resister is large, wherein the operation speed is further enhanced, has successfully been provided by the second embodiment of this invention. FIRST EMBODIMENT An output circuit having an advantage in which the rising rate of an output signal is large until it arrives at the voltage of the power supply employed in the output circuit, even if the resistance of a pull-up resister is large, wherein a circuit construction in which the power supply voltage of the following stage is not applied between the source and the drain, between the gate and the source and between the gate and the drain of a MOS FET, is employed, whereby FETs which have a less amount of dielectric strength can be employed therefor. Referring to Fig. 9, an output circuit which is allowable to be built-in in an integrated circuit in accordance with the first embodiment of this invention is composed of an input terminal (IN), an enable input terminal (EB), an output terminal (OUT) arranged on a pad of the integrated circuit in which the output circuit is built-in, a NAND gate (NAND 1 ) having two input ports, a NOR gate (NOR 2 ) having two input ports, p channel normally off FETs (P 1 ) through (P 7 ), n channel normally off FETs (N 1 ) through (N 4 ) and (N 7 ), inverters (INV 1 ) and (INV 2 ). A pull-up resister (R 1 ) arranged in an external circuit is connected the output terminal (OUT). The circuit illustrated in Fig. 9 is the circuit illustrated in Fig. 5 in which the connection of the gate of the p channel normally off FET (P 4 ) is moved from the node (OUTN) to the drain of the n channel normally off FET (N 3 ) and to which n channel normally off FETs (N 2 ), (N 4 ) and (N 7 ) and p channel normally off FETs (P 6 ) and (P 7 ) are newly introduced. A node defined by the connection point of the drain of the n channel normally off FET (N 3 ) and the gate of the p channel normally off FET (P 4 ) is named (SP 4 ). The gate of the n channel normally off FET (N 2 ) is connected the internal power supply (V DD ), the drain of the n channel normally off FET (N 2 ) is connected the output terminal (OUT) and the source of the n channel normally off FET (N 2 ) is connected the drain of the n channel normally off FET (N 1 ). The drain of the n channel normally off FET (N 3 ) is not connected the output terminal (OUT). The gate of the n channel normally off FET (N 4 ) is connected the internal power supply (V DD ), the drain of the n channel normally off FET (N 4 ) is connected the node (G) and the source of the n channel normally off FET (N 4 ) is connected the node (SP 4 ). The drain of the n channel normally off FET (N 3 ) is not connected the node (G). A parallel circuit of the n channel normally off FET (N 7 ) and the p channel normally off FET (P 7 ) is connected between the output terminal (OUT) and the input terminal of the inverter (INV 2 ). The input terminal of the inverter (INV 2 ) is not connected the output terminal (OUT). A node connected the input terminal of the inverter (INV 2 ) is named (Y). The gate and the source of the p channel normally off FET (P 6 ) are connected the internal power supply (V DD ) and the drain of the p channel normally off FET (P 6 ) is connected the node (Y). The p channel normally off FET (P 6 ) connected in the foregoing manner stays in an OFF position, as long as the potential of the node (Y) is less than the internal power supply (V DD ). The gate of the n channel normally off FET (N 7 ) is connected the internal power supply (V DD ), the first electrode (either drain or source) thereof is connected the output terminal (OUT) and the second electrode (either source or drain) thereof is connected the node (Y). The gate of the p channel normally off FET (P 7 ) is connected the node (G), the first electrode (either drain or source) thereof is connected the node (Y) and the second electrode (either source or drain) thereof is connected the output terminal (OUT). The output terminal (OUT) is connected the drain of the p channel normally off FET (P 2 ), the sources of the p channel normally off FETs (P 4 ) and (P 5 ), the second electrode of the p channel normally off FET (P 7 ), the drain of the n channel normally off FET (N 2 ) and the first electrode of the n channel normally off FET (N 7 ). The node (G) is connected the gates of the p channel normally off FETs (P 2 ), (P 3 ) and (P 7 ), the drain of the p channel normally off FET (P 4 ) and the drain of the n channel normally off FET (N 4 ). The node (OUTN) is connected the output terminal of the inverter (INV 2 ) and the gate of the n channel normally off FET (N 3 ) . Supposing the enable input terminal (EB) is set to an "L" level or OV, the operation of the output circuit in accordance with the first embodiment of this invention will be described below. Referring to Fig. 9, regardless the polarity of the signal applied to the input terminal (IN), the output level of the NAND gate (NAND 1 ) or the potential of the node (PG) is "H" or e.g. 3V. As a result, the p channel normally off FET (P 1 ) is in an OFF position. Since the output potential of the NOR gate (NOR 2 ) or the potential level of the node (NG) is "L", regardless the polarity of the signal applied to the input terminal (IN), the n channel normally off FET (N 1 ) is in an OFF position. In this manner, as long as the enable input terminal (EB) is applied an "L" level signal, both the p channel normally off FET (P 1 ) and the n channel normally off FET (N 1 ) are in an OFF position. Thus, the impedance level of the output terminal (OUT) is high, regardless of the potential level of the input terminal (IN). The potential of the output terminal (OUT) is identical to that of the external power supply (Vcc) or 5V, because it is connected with the external power supply (Vcc) via the pull-up resister (R 1 ). Since the potential level of the output terminal (OUT) is 5V, the potential level of the node (SP 4 ) is not higher than (V DD - V th ). Thus, the p channel normally off FET (P 4 ) is in an ON position. The potential level of the node (G) is identical to that of the output terminal (OUT) or 5V. Since the potential level of the output terminal (OUT) is 5V, the p channel normally off FET (P 5 ) is in an ON position, resultantly keeping the potential level of the floating bulk (B) at the potential level of the output terminal (OUT) or 5V. Since the potential level of the output terminal (OUT) and of the node (G) is 5V, the p channel normally off FET (P 2 ) is in an OFF position. Since the potential level of the output terminal (OUT) and of the floating bulk (B) is 5V, the p channel normally off FET (P 3 ) is in an OFF position as well. Since the potential level of the output terminal (OUT) and of the node (G) is 5V, the p channel normally off FET (P 7 ) and the n channel normally off FET (N 7 ) are in an OFF position. Since the p channel normally off FET (P 7 ) has increased the potential level of the node (Y) up to 3V, before it turns off, the potential level of the node (Y) stays at 3V. Thus, the potential level of the output terminal of the inverter (INV 2 ) or of the node (OUTN) is "L", and the n channel normally off FET (N 3 ) is OFF. Since the potential level of the node (G) is 5V, the potential level of the source of the n channel normally off FET (N 4 ) or of the node (SP 4 ) is (5V - 2V th ). In the foregoing manner, provided the enable input terminal (EB) is set at an "L" level, the p channel normally off FETs (P 2 ) and (P 3 ) are OFF, the impedance level of the drain of the p channel normally off FET (P 1 ) or of the node (S) is high. Thus, no leak current flows to internal power supply (V DD ) from the output terminal (OUT) through the node (S) and through the bulk of the p channel normally off FET (P 1 ). Since the floating bulk (B) is not connected the internal power supply (V DD ), no leak current flows to the internal power supply (V DD ) from the floating bulk (B) through the drain of the p channel normally off FET (P 2 ) and through the sources of the p channel normally off FETs (P 4 ) and (P 5 ). Since the input terminal of the inverter (INV 2 ) is connected the gate of a MOS FET (not shown) constituting the inverter (INV 2 ), the impedance level thereof is high. Since the drain and the bulk of the n channel normally off FET (N 1 ) is applied a counter bias each other, the impedance level of the drain of the n channel normally off FET (N 1 ) is high. Thus, no leak current flows to the ground (GND) from the output terminal (OUT). Supposing the enable input terminal (EB) is set to an "H" level or 3V, the operation of the output circuit in accordance with the first embodiment of this invention will be described below. Referring to Fig. 9, provided an "L" level signal or 0V is applied to the input terminal (IN), the NAND gate (NAND 1 ) outputs an "H" level signal to turn off the p channel normally off FET (P 1 ). The NOR gate (NOR 2 ) outputs an "H" level signal to make the potential level of the node (NG) an "H" level. As a result, the n channel normally off FET (N 1 ) is ON. As a result, the potential level of the output terminal (OUT) is "L" or OV. Since the potential level of the output terminal (OUT) is "L", the n channel normally off FET (N 7 ) is ON, resultantly making the potential level of the node (Y) "L". Thus, the potential level of the output terminal of the inverter (INV 2 ) or of the node (OUTN) is "H" or 3V. Since the potential level of the node (OUTN) is "H", the n channel normally off FET (N 3 ) is ON, and the n channel normally off FET (N 4 ) is ON. Since the n channel normally off FETs (N 3 ) and (N 4 ) are ON, the potential level of the nodes (G) and (SP 4 ) is "L". Since the potential level of the node (G) and of the output terminal (OUT) is "L", the p channel normally off FETs (P 2 ), (P 4 ), (P 5 ) and (P 7 ) are OFF. Since the potential level of the node (S) is less than the V th , the p channel normally off FET (P 3 ) is OFF as well. Provided an "H" level signal is applied to the input terminal (IN), the output level of the NAND gate (NAND 1 ) or the potential level of the node (PG) is shifted to "L", resultantly turning on the p channel normally off FET (P 1 ). The output level of the NOR gate (NOR 2 ) or the potential level of the node (NG) is shifted to "L" from "H", resultantly turning off the n channel normally off FET (N 1 ). Since the p channel normally off FET (P 1 ) has turned on, the potential level of the node (S) is increased to the potential level of the internal power supply (V DD ) or 3V. Since the potential level of the node (G) is "L", the p channel normally off FETs (P 2 ) and (P 3 ) turn on. Since the p channel normally off FET (P 2 ) has turned on, the potential level of the output terminal (OUT) increases up to the level of the internal power supply (V DD ) or 3V. Since the p channel normally off FET (P 3 ) has turned on, the potential level of the floating bulk (B) increases up to the level of the internal power supply (V DD ) or 3V. Since the potential level of the output terminal (OUT) has increased to the V th , the p channel normally off FET s (P 4 ) and (P 7 ) turn on. As a result, the potential level of the node (Y) becomes identical to the potential level of the output terminal (OUT). The potential level of the node (G) is clamped at an "L" level until the n channel normally off FET (N 7 ) turns off. An increase of the potential level of the output terminal (OUT) and of the node (G) up to that of the internal power supply or 3V shifts the potential level of the output terminal of the inverter (INV 2 ) or the node (OUTN) to an "L" level, resultantly turning off the n channel normally off FET (N 3 ). Since the n channel normally off FET (N 3 ) has turned on, the potential level of the node (G) becomes identical to that of the output terminal (OUT) or 3V, resultantly turning off the p channel normally off FET (P 7 ). The potential level of the node (SP 4 ) becomes (3V - V th ). Since the potential level of the node (G) becomes identical to that of the node (S), the p channel normally off FETs (P 2 ) and (P 3 ) turn off. Thereafter, the potential level of the output terminal (OUT) increases up to the potential level of the external power supply (Vcc) or 5V, because it is connected the external power supply (Vcc) through the pull-up resister (R 1 ). The p channel normally off FET (P 4 ) stays in an ON position. When the potential of the output terminal (OUT) has increased up to (3V + V th ), the p channel normally off FET (P 5 ) turns on, resultantly causing the potential level of the floating bulk (B) to become identical to that of the output terminal (OUT). When the potential of the output terminal (OUT) has finally increased up to the level of the external power supply (Vcc) or 5V, the potential of the node (G) and of the floating bulk (B) becomes 5V. If the potential of the output terminal (OUT) has exceeded (3V + V th ), before the p channel normally off FET (P 7 ) turns off, the p channel normally off FET (P 6 ) turns on to clamp the potential of the output terminal (OUT) at the potential (3V + V th ). In the foregoing manner, also under conditions that the enable input terminal (EB) is set at an "H" level and that the input terminal (IN) is applied an "H" level signal, the p channel normally off FETs (P 2 ) and (P 3 ) are OFF. As a result, no leak current flows into the internal power supply (V DD ) through the node (S) and the bulk of the p channel normally off FET (P 1 ). Since the floating bulk (B) is not connected the internal power supply (V DD ), no leak current flows from the floating bulk (B) to the internal power supply (V DD ). Incidentally, no leak current flows to the ground (GND) from the input terminal of the inverter (INV 2 ) and the drain of the n channel normally off FET (N 1 ). Referring to Figs. 10A and 10B, the rising rate of an output signal is large until it arrives at the voltage of the internal power supply, even if the resistance of a pull-up resister is large, and the power consumption is small, because the resistance of a pull-up resister is large. The foregoing description has clarified that the first embodiment of this invention has successfully provided an output circuit having an advantage in which the rising rate of an output signal is large until it arrives at the voltage of the power supply employed in the output circuit, even if the resistance of a pull-up resister is large, and the power consumption is small, because the resistance of a pull-up resister is large, wherein a circuit construction in which the power supply voltage of the following stage is not applied between the source and the drain, between the gate and the source and between the gate and the drain of a MOS FET, is employed, whereby FETs which have a less amount of dielectric strength can be employed therefor.

Claims: An output circuit comprising: a first type field effect transistor having a channel of one conductivity, having a gate connected a first node, having a first electrode connected a first power supply and having a second electrode connected a second node, said first node receiving the input, a second type field effect transistor having a channel of one conductivity, having a gate connected a third node, having a first electrode connected said second node, having a second electrode connected a fourth node and having a substrate connected a fifth node which is floating, said fourth node providing the output signal a third type field effect transistor having a channel of one conductivity, having a gate connected a sixth node, having a first electrode connected said third node, having a second electrode connected said fourth node and having a substrate connected said fifth node, a fourth type field effect transistor having a channel of the opposite conductivity, having a gate connected said first power supply, having a first electrode connected said fourth node and having a second electrode connected a seventh node, a fifth type field effect transistor having a channel of one conductivity, having a gate connected said third node, having a first electrode connected said seventh node, having a second electrode connected said fourth node and a substrate connected said fifth node, an inverter means having an input terminal connected said seventh node and an output terminal connected an eighth node, a sixth type field effect transistor having a channel of the opposite conductivity, having a gate connected said eighth node, having a first electrode connected a second power supply and having a second electrode connected said sixth node, and a seventh type field effect transistor having a channel of the opposite conductivity, having a gate connected said first power supply, having a first electrode connected said sixth node and having a second electrode connected said third node. An output circuit in accordance with claim 1, further comprising: an eighth type field effect transistor having a channel of one conductivity, having a gate connected said first power supply, having a first electrode connected said first power supply and having a second electrode connected said seventh node. An output circuit in accordance with claim 1, further comprising: a ninth type field effect transistor having a channel of one conductivity, having a gate connected said third node, having a first electrode connected said second node, having a second electrode connected said fifth node and having a substrate connected said fifth node. An output circuit in accordance with claim 1, further comprising: a tenth type field effect transistor having a channel of one conductivity, having a gate connected said first power supply, having a first electrode connected said fourth node, having a second electrode connected said fifth node and having a substrate connected said fifth node. An output circuit in accordance with claim 1, further comprising: a first input terminal connected said first node, a second input terminal connected a ninth node, an output terminal connected said fourth node, an eleventh type field effect transistor having a channel of the opposite conductivity, having a gate connected said ninth node, having a first electrode connected said second power supply and having a second electrode connected a tenth node, and a twelfth type field effect transistor having a channel of the opposite conductivity, having a gate connected said first power supply, having a first electrode connected said tenth node and having a second electrode connected said fourth node.

Inventors: KAWANO HARUMI, SUSHIHARA AKIHIRO, KAWANO, HARUMI, SUSHIHARA, AKIHIRO
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1998
Main classification: H03K19
IPC codes: H03K19