A method of address compression for cell-based and packet-based protocols and hardware implementations thereof

Abstract: It is disclosed an algorithm able to compress a defined set of addresses S, the set of addresses to be compressed, belonging to the set U , the whole addressing space; for each of these addresses the algorithm must identify one and only one address belonging to C , the set of compressed address (i. e. perform a transformation S → C ). The algorithm may be implemented using some low-cost random access memories (RAM) and some control logic. A performance comparison shows that is possible to perform the address compression using one order of magnitude less memory respect to the state-of-the-art techniques. Basically, the method of the invention combines the splitting of the incoming address space (U) into a plurality of sub-spaces, a tree search algorithm for clustering a defined set (S) of identifiers contained in the sub-spaces into which the incoming addresses space (U) has been split and a sequential search performed within the right cluster in order to identify the compressed address belonging to space C. The patent covers the algorithm, a preferred embodiment and some extended embodiments, that give extra gain. Thanks to the invention is thus possible to implement silicon devices able to compress one order of magnitude more managed channels with respect to the state-of-the-art techniques, without area changes. Conversely, it is possible to implement the address compression function with one order magnitude less memory resources with respect to the state-of-the-art techniques.

Description: 1 BACKGROUND OF THE INVENTION 1.1 ADDRESS COMPRESSION PROBLEM DEFINITION Notably, for each Communication Protocol, an Incoming Address Space (the maximum number of channels a specific protocol can handle) is defined. In this document reference is made to the so-called addressing space of 2 N bits as the set of Incoming Addresses. On the other hand, a telecom equipment is able to deal only with some managed channels. The number of simultaneously manageable channels is finite and is a typical design target. Each managed channel must be addressable by means of an internal identifier, that is a subset of the Incoming Address. In this document reference is made to the space of 2 Ncpr bits of the internal identifiers as the set of Compressed Addresses. In a telecom equipment, a function mapping some points belonging to the universe of Incoming addresses ( 2 N bits) to a set of Compressed Identifiers ( 2 Ncpr bits) should be implemented. This function is called the Address Compression Function. Due to network management reasons, the Incoming Address Space is very large. On the other hand, the number of channels that must be managed simultaneously nowadays by telecommunication apparatuses is also very large. Moreover, data link speed is increasing at an impressive pace: in ten years from 64 Kbit/s to 155 Mbit/s and now to 1.2 Gbit/s. Because of this, the efficiency of the design of the Address Compression Function is today a key factor in equipment like routers and switches. Altogether, designing has become critical because, due to the increased data speed, the time that can be spared to perform the Address Compression Function is reduced. On the other hand, the increasing number of manageable channels augments costs because of the increasing number of resources needed to perform the Address Compression Function. 1.1.1 ADDRESS COMPRESSION PROBLEM DEFINITION The aim of the algorithm is to compress a defined set of addresses S , the set of addresses to be compressed, belonging to the set U , the whole addressing space, as shown in Figure 1. For each of these addresses the algorithm must identify one and only one address belonging to C , the set of compressed address (i. e. perform a transformation S → C ). n dimension of the whole addressing space ( U ≡ { a 0 ,..., a 2 n }) n cpr dimension of the space of compressed addresses ( C ≡ { a 0 ,..., a 2 n cpr }) where: n cpr < n , C ⊂ U . The cardinality of S must equals the cardinality of C . 1.1.2 ADDRESS COMPRESSION FUNCTION AND IP APPLICATION The most fundamental operation in any IP routing product is the Routing Table search process. A packet is received with a specific Destination Address (DA), identified by a unique 32-bit field in current IP Version 4 implementations. The router must search a forwarding table using the IP Destination Address as its key and determine which entry in the table represents the best route for the packet to take in its journey across the network to its destination. A «flat» forwarding table would have a size of 2 32 addresses, that means 4 Gbytes of address space (16 Gbytes of data). The DA must be compressed to point to a reasonable table size. The route search operation is the single most time-consuming operation that must be performed in routers today, and typically defines the upper bound on the router's ability to forward packets. The problem has grown even more challenging in recent years. Data links now operate routinely at 100 MBits/second, and generate nearly 150,000 packets-per-second requiring routing. New protocols, such as RSVP, require route selection based not only on Destination Address, but potentially also Protocol Number, Source Address, Destination Port and Source Port. IP Version 6 will increase the size of the address field from 32 bits to 128 bits, with network prefixes up to 64 bits in length. Expanded use of IP Multicasting requires that searches include large numbers of Class D (Multicast Group) addresses with large numbers of users. Moreover, the ever-expanding number of networks and hosts on Internet is making routing table sizes larger and larger. 1.1.3 ADDRESS COMPRESSION FUNCTION AND ATM APPLICATIONS ATM data equipment, to be compliant with ITU and ATM-forum specifications, must be able to receive ATM cells for any admissible value of the header fields VPI.VCI. The total length of these fields is 24 bits (16.7 millions of admissible values). On the other hand, the ATM equipment is designed to manage a number of internal channels (at least) equal to the maximum number of engageable channels. This number depends on the application: from one to hundreds in the case of terminals; some thousands (4K, 64K) in case of core network equipment. In the following description, the univocal (shorter) internal channel identifier, will be referred to as Channel Identifier (CID). It is evident the requisite that the processing be able to map from any possible value of VPI.VCI (24 bits) to any possible CID (e.g. 12 bits). 1.2 ALGORITHM CLASSES A compression function able to map from a string of length N bits to a (unique) string of length Ncpr (Ncpr<N) can be implemented in various ways. Two main classes exist: the algorithms with an unpredictable duration belong to a first class; the others, with a predictable duration , belong to the second one. For those belonging to the first class, it is not possible to know for how much time (microprocessor instructions or clock cycles) the algorithm will run before hitting the compressed identifier. It will depend on the number of active connections. These algorithms are normally easier to implement, do not require lots of resources and can be sped-up only by improving RAM access time of the memories where the search tables are located. For the algorithms of the second class, (predictable duration algorithms) it is possible to know, UNDER ANY CONDITION, how much time (microprocessor instructions or clock cycles) the algorithm will run before hitting the compressed identifier. These algorithms often require a lot of resources. An algorithm belonging to the second class ensures that the maximum search time is less than the time used to receive the shortest packet 1 , this guarantees the maximum allowable throughput of the equipment. 1.2.1 UNPREDICTABLE DURATION ALGORITHMS IP routers companies have developed the algorithms belonging to this class some years ago. It is possible to call them «classical route search techniques». The main algorithms will be explained for an IP context to provide the reader with useful historical background. 1.2.1.1 THE PATRICIA TREE This is the most popular algorithm used in router "slow paths". The forwarding table (associating each prefix entry with an exit port and next-hop MAC address) is stored in a "Binary Root Tree" form. The table is organized in a series of "nodes", each of which contains a route of different length, and each of which has two "branches" to subsequent nodes in the tree. At the ends of the branches there are "leaves", which either represent full 32-bit host routes (for devices attached directly to the router) or most-specific routes available to a particular subnet. The algorithm is able to map ANY incoming vector to a unique outcoming identifier. Unfortunately, in the worst case, the algorithm will have to travel all the way to the end of the tree to find a leaf, and the time needed cannot be absolutely predictable. The Patricia Tree approach does not scale well to level-2 packet switching: a worst-case lookup involves a large number of memory accesses, taking far more time than that available at gigabit rates. Moreover, hardware implementation is rather complex. This algorithm was developed for general-purpose software implementations. 1.2.1.2 HASHING TABLES "Hashing" is an alternative approach. Unlike the Patricia Tree, hashing operates strictly on an exact-match basis, and assumes that the number of «channels» (IP Destination Addresses, VPI/VCIout) the system must handle at any one time be limited to a few thousands. A "hash" function - a sort of compression algorithm - is used to condense each incoming identifier (24 or 32 bits) in the table to a smaller-sized entry (8-10 bits typically). When a packet is received, an equivalent "hash value" is computed quickly from its incoming identifier. This value points to a hash table (named a "slot") that corresponds to one or more outcoming identifiers. The compression effected by a hashing function makes the table small enough to be quickly searched sequentially using simple hardware-based exact matching techniques. The main problem involved in the hashing technique is that it assumes a «flat» distribution of the values of incoming identifiers. The «hash» function maps the space of possible values of incoming identifier in a plurality of sub-spaces. In Figure 2, the ellipse indicates the U space and the incoming valid identifiers, that is the S space, are indicated as tiny circles. The «hash» function generates the boundaries between sub-spaces. If, as depicted in Figure 3, in a sub-space a number of identifiers greater than the slot size (hash table) must be mapped, it is necessary to recalculate a new the hash function in an appropriate way. This involves item sorting in hash tables that cannot be performed in a real time mode. This process is easy to implement in hardware and tends to perform fairly well, albeit in a probabilistic manner. Unfortunately there are a number of drawbacks with this algorithm. In a hardware implementation it is not possible to change «on the fly» the «hash» function, because a full item sorting is implied. This means that the only way to overcome the problem is to increase the slot length, but obviously this is not always possible. The main ATM IC developers (Motorola, IDT, Transwitch) have implemented an algorithm of this kind. A typical architecture is shown in Figure 4 A main problem is that the incoming identifier processing time is not deterministic (in some case a sequential search is needed) and eventually will become longer than one packet (cell) time). The ACF function is implemented by means of several readings in the Hash tables that are written by the controlling microprocessor in a "off-line" manner. The algorithm implies the subtle assumption that the sequence of incoming identifiers be «spread» on the entire set of sub-spaces and that in any sub-space the average search time be shorter than the packet (cell) time. Moreover, use of a quite long fifo (10, 20 packets/cell positions) is required in order to decouple the incoming rate speed from the speed of the compression algorithm, that in the average would be the same. In some cases, it may happen that the packet (cell) is lost or misrouted. The only way to cure this problem is to increase the speed of the hash table 2 . This architecture is preferred by NIC chip providers because is cheaper, but it is unable to support the mapping of any possible incoming identifier to local identifiers. In the present context sometimes use is made of different expression for indicating materially the same thing. In particular the same N-bit string or the same Ncpr-bit string is often referred to with the expressions: physical layer identifier, virtual path identifier address, vector. These are expression that are commonly used and perfectly understood by technicians and the different expressions are often used when describing an algorithm or a data processing structure, and so forth. 1.2.2 PREDICTABLE DURATION ALGORITHMS In predictable duration algorithms, the ACF is performed under any condition in a time that may be less than or even equal to the packet time (cell period). A typical architecture is shown in Figure 5. Because the algorithm duration may be knowingly shorter than a packet (cell) cycle, it is possible to admit ANY type of incoming traffic. On the other hand, more chip or system resources are needed to implement the function than those do that would be required by an algorithm of unpredictable duration. There are three well-known techniques that are able to perform ACF predictably in less than one packet (cell): CAM Sequential search Binary tree 1.2.2.1 CAM According to this approach, the incoming address (e.g. VPI.VCI) is input to a Context Access Memory. The CAM hits the correct compressed. If there is no hit the cell is discarded. The CAM is wide as the incoming address and is deep enough to accommodate the maximum number of connections. The time of execution of the ACF is typically of a few clock cycles. It is in any case less then a cell time. The main problem of this architecture is the availability of the CAM module 3 . 1.2.2.2 SEQUENTIAL SEARCH To obtain a compressed identifier from an incoming address, it is possible to perform a sequential search on a RAM, for a number of cycles less or equal the packet (cell) time. A relatively small RAM, a counter to generate addresses and a unique 24-bit comparator is all is needed, as depicted in Figure 6. 1.2.2.3 EXTENDED SEQUENTIAL SEARCH To increase the extent of the sequential search without exceeding the number of available clock cycles, it is possible to use several RAMs, several counters to generate the addresses, several 24-bit comparators and a priority encoder, as depicted in Figure 7. 1.2.2.4 BINARY TREE The mapping from the valid incoming vectors to the compressed identifier is implemented by means of a chain of memories. A pointer chain link has to be written in these memories in order to link any valid incoming vector with the right compressed identifier The first memory is addressed by a bit slice of the incoming address (typically the most significant bits). The content is a pointer to the second one. The second memory is addressed by the pointer obtained from the first one, chained with a new slice belonging to the incoming vector. The content is a pointer to the third one. The third memory is addressed by the pointer obtained from the second one, chained with another slice belonging to the incoming vector. The chain ends when any bit belonging to the incoming address has been used. In order to ensure a no-blocking probability, the wide of any memory has to be equal to Ncpr . Unfortunately, because of this, the memory utilization is really poor (around 5, 10%). Figure 8 shows the organization of the memories needed for implementing a Binary Tree Search. In Figure 9 the ellipse depicts the U space and the set of incoming valid identifiers, the S space is indicated by the tiny circles. The Binary Tree technique splits the U space in areas of equivalent size, by means of a direct addressing table or DAT; then the sub-spaces are split again, by means of RTis, in order to ensure that no more than a point belonging to S is present in a particular sub-space. Figure 10 shows a typical implementation related to ATM words of 24 bits of incoming VPI.VCI that must be converted to proper channel identifiers CID, 12 bits wide. The basic assumption is to implement a research path on some external RAM bank, addressed by means of VPI.VCI fields. Four banks (ATM Compression Blocks) of RAM are addressed for a total amount of 392 Kbytes, in order to have up to 4096 different CIDs. Four addressing cycles are needed. The dimensions of the memories depend on the maximum number of CIDs needed. US Patent No. 5,414,701 describes a method and a structure for performing address compression in an ATM system according to a so-called content addressable memory (CAM) as described above. Standing the requisite of performing the required mapping of incoming N-bit identifiers into Ncpr-bit virtual path identifiers within a cell time slot, the implementation of a consequent data processing structure for performing such an address compression function, following one of the known approaches as the ones reviewed above, implies the use of a relatively large amounts of physical resources in terms of RAM memories. Irrespectively, of the approach followed, the RAM requisite for a reliable operation of the data processing structure employed for performing address compression represents a crucial cost factor and it is evident the opportunity of finding methods of performing the address compression more efficient than the presently known ones and that may be realized at a reduced cost. 2 OBJECT AND SUMMARY OF THE INVENTION It has now been found a method of address compression outstandingly more efficient than the known methods, capable of reducing the RAM requisite for comparable performances in terms of number of clock cycles necessary to complete the compression algorithm. Moreover, when assuming an optimization of the data processing structure of the invention, the performance in terms of the two parameters of memory requisite and of number of clock cycles required, is significantly better than the performance obtainable from any of the systems realized according to the known approaches. These important advantages are achieved, according to the present invention, by a method that combines certain aspects of an unpredictable duration algorithm with those of a classical sequential search algorithm. The synergistic combination of different approaches produces the reported outstanding performance. Basically, the method of the invention combines the splitting of the incoming address space (U) into a plurality of sub-spaces, a tree search algorithm for clustering a defined set (S) of identifiers contained in the sub-spaces into which the incoming addresses space (U) has been split. Having so clustered the elements of the defined set (S) of identifiers, a sequential search is performed within each cluster so constructed for identifying the Ncpr-bit identifier belonging to the compressed address space (C). By performing the sequential search so restricted over a pre-identified cluster of a known size, ensures identification within a given number of clock cycles (a predictable time span). The system may be further optimized for either reducing the number of clock cycles required by the sequential search or for reducing the memory requisite. The method of the invention is defined in the independent claim 1 for an unclassified address space, while an embodiment of the method with a classified address space is defined in the dependent claim 5. The data processing structure that implements the method of the invention is defined in the independent claim 6 for an unclassified address space, while an embodiment of the structure with a classified address space is defined in the dependent claim 10. 1 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 - Representation of address compression problem Figure 2 - Example of "hit" distribution Figure 3 - Recompilation of "hash" function Figure 4 - Typical unpredictable duration class implementation Figure 5 - Typical predictable duration class implementation Figure 6 - Sequential Search structure Figure 7 - Extended Sequential Search structure Figure 8 - Binary Tree search structure Figure 9 - U space splitting via Binary Tree technique Figure 10 - Channel compression block data structure in ATM environment Figure 11 - U space splitting via the CSSA technique of the invention Figure 12 - Block diagram of a CSSA system of the invention Figure 13 - Layout of DAT, RTi and SST blocks Figure 14 - Example 1 of CSSA operation Figure 15 - Example 2 of CSSA operation Figure 16 - Alternative embodiments of the system of the invention Figure 17 - Extended CSSA#1 - Sequential Search Table with different SSTi Figure 18- Extended CSSA #2 - Sequential Search Table with a single, wide SST Figure 19 - Extended CSSA #3 - pipelined fifos, staged architecture Figure 20 - Problem representation example for Extended CSSA #4 Figure 21 - Extended CSSA #4 architecture Figure 22 - Implementation example for Extended CSSA #4 Figure 23 - Generic Address Compression Function Figure 24 - Performance evaluation method Figure 25 - Pure sequential search structure Figure 26 - Extended sequential search structure Figure 27 - Binary Tree search structure Figure 28 - Clustered Sequential search structure DESCRIPTION OF AN EMBODIMENT OF THE INVENTION 3.1 THE CLUSTERED SEQUENTIAL SEARCH ALGORITHM (CSSA) OF THE INVENTION The novel CSSA technique of the invention splits the U space in areas of equivalent size, by means of a DAT that is preferably made as small as possible; then the sub-spaces are effectively split again, by means of a cascade of Rtis, in order to ensure that no more that SSLL points belonging to S are present in a particular sub-space. In the example shown in Figure 11 SSLL is set to 4. To identify, in the addressed sub-spaces, the only points belonging to S , a sequential search is performed by means of a SST (sequential Search Table). The following paragraphs explain in detail the algorithm. 3.1.1 CSSA DESCRIPTION The proposed algorithm combines both clustering of space and sequential search. The set S is split in clusters and within each cluster a sequential search is performed. More precisely CSSA is performed in three main steps: 1. splitting of U in equal subspaces (each subspace can contain either the whole S or some elements of S nor any element of S ); 2. clustering of S (elements of S are divided among a set of clusters); 3. sequential search within each cluster; Splitting is performed into the Direct Addressing Table (DAT), the clustering phase is performed in a cascade of Routing Tables (RTi), while the linear search is performed in the Sequential Search Table (SST). This structure is illustrated in Figure 12. As depicted in Figure 12 the structure feeds an eventual translation table (TT), according to a common technique. The listed tables have the layout shown in Figure 13. The fields belonging to each table are described in the following boxes. RTi ( i - nth Routing Table ) RTi[i].PTR pointer to a selected page of RT ( i + 1 ) (if RTi[i].PTR = k it means that page k of RT ( i + 1 ) is pointed ( RT ( i + 1 ) [k] )); RTi[i].USED number of times a pointer is used, if RTi[i].USED=m it means that the link RTi[i].PTR is routed m times; PGL RTi page length for RTi ( PGL RTTi is a power of 2, n PGL RTi = log 2 PGL RTi ); Npg RTi number of pages of RTi; SST (Sequential Search Table) N cluster number of clusters; SSLL length of each sequential search list (Sequential Search List Length); WL SST word length of RTi (expressed in bit); The CSSA structure has three different mode of operation: Initialization Mode; Configuration Mode; Normal Operation Mode; In the Initialization Mode the contents DAT, RTi, SST and SSTPF are initialized with default values. In the configuration mode the contents of DAT, RTi and SST have to be set to values suitable for compression of a defined set of address S to be compressed. In the normal operation mode, the algorithm finds for each incoming vector (INCVECT) fed thereto, a corresponding outcoming vector (OUTVECT) that matches the INCVECT 3.1.2 INITIALIZATION MODE In the Initialization Mode the contains of DAT, RTi, SST and SSTPF are initialized with default values: USED fields are initialized with 0; PTR fields are initialized with UNASSIGNED; ADDR fields are initialized with UNASSIGNED; The pseudo-code for the Initialization Mode is: 3.1.3 NORMAL OPERATION MODE In the Normal Operation Mode the algorithm splits the whole space U in N subspace equal subspaces by means of the DAT. Then the elements of S , that may fall into anyone (and even into more than one) of the mentioned subspaces, are clustered in N cluster sets by the cascade of RTi. The result of this clustering process (that may be visualized as a further splitting of the S set) is a cluster identifier (CLID (CLuster IDentifier)) in which the sequential search is performed; this is done in the SST. Regarding the sequential search, if one of the addresses stored in the selected cluster (i.e. the one at position SSLPOS (Sequential Search List POSition)) match (in practice the Comparison Result is monitored) with the Incoming Vector INCVECT, then the Incoming Vector is compressible and its compressed form c is represented by the pair (CLID, SSLPOS); otherwise the Incoming Vector INCVECT will not be compressed. It is also possible to define the compressed form c as the absolute address of the row identified by the sequential search phase in the SST. Summarizing: if for a given INCVECT ∈ S ∃! c = (CLID, SSLPOS) I {OUTVECT = SST( c ) = INCVECT} → INCVECT is compressible; if for a given INCVECT ∈ S ∄ c = (CLID, SSLPOS) I {OUTVECT = SST( c ) = INCVECT} → INCVECT is not configured for compression; all INCVECT ∈ ( U - S ) are not configured for compression; In Figure 12 a Translation Table (TT) is shown. This block is not part of the structure and is optional. It does not intervene in the algorithm of the invention and is shown as a simple implement to perform also an address translation, the result of which is an Outcoming TAG. The pseudo-code for the algorithm (Normal Operation Mode branch) is: 3.1.4 CONFIGURATION MODE Given the set S of address to be compressed and the set C of compressed addresses the setup of CSSA consists in assigning all the parameters DAT[i] . PTR , DAT[i].USED, RTi[i].PTR, RTi[i].USED to configure for compression all the elements of S set. CSSA supports both an absolute and an incremental Configuration Mode: in an absolute mode, all elements of S are set for compression in a single Configuration Mode session, that is all parameters of DAT, RTi, SST, SSTPF are written from scratch; in an incremental mode, new elements are configured or unconfigured for compression in and incremental way, that is without rewriting all parameters of DAT, RTi, SST, SSTPF from scratch. The pseudo-code for the Configuration Mode is: where dat_rowsel(s), rt_pagesel(i,s), rt_rowsel(i,s), sst_pagesel(s) and sst_rowsel(s) are function that are bonded, to calculate the most suitable row or page to avoid routing congestion for a specific table (DAT, RTi, SST, SSTPF) starting as input data from the address s selected for compression. The pseudo-code for the listed functions is as follows: 3.1.4.1 NOTE ON OPERATING MODES The part of the algorithm that is executed in the Normal Operation Mode is wholly hardware implemented, while the part that is executed in the Configuration Mode is wholly software implemented (the implemented architecture only provides for the primitives needed by the configuration software to write the physical tables). The field USED is not really present in the physical tables, it is only present in a software image of the physical tables used by the configuration software during the configuration phase. 3.1.5 EXAMPLES Example 1 In Figure 14 an example of operation of the CSSA method of the invention is shown. This example helps in understanding both the Configuration Mode and the Normal Operation Mode. In this example the whole space U is represented by all the addresses of eight bits. We are interested in compressing the eighth ones belonging to U , namely: addr0, addr1, addr2, addr3, addr4, addr5, addr6, addr7, which form the set S . Summarizing: U ≡ { a 0 ,..., a 255 }; S ≡ {a 0 ,..., a 7 } ≡ { addr0, addr1, addr2, addr3, addr4, addr5, addr6, addr7 }; C ≡ {a 0 ,..., a 7 }; The number of clusters is chosen as N cluster = 4 and the length of each cluster is set to SSLL = 4. The parameter N subspace = 4 has been chosen, so that the whole space U is split in four equal subspaces: Sub0, Sub1, Sub2, Sub3 . The addresses configured for compression are encoded in both hexadecimal and binary code (i.e. addr0 = 42 (hex) / 01-00-00-10 (bin) ). The binary representation has its digits grouped into pairs (separated by '-'): the 1 st pair is loaded to split U into four subspaces ( Sub0, Sub1, Sub2, Sub3 ); the 2 nd , 3 rd and 4 th pairs are loaded to select the position within each page where to route each addri for the routing tables RT1, RT2 and RT3, respectively, (this degree of freedom is used by the configuration part of the algorithm to avoid routing congestion of a table RTi). The clustering of the elements of the S set in N cluster sets is performed by choosing in a proper way the pointers RTi[j.k].PTR. Example 2 Figure 15 shows another example of algorithm operation. 3.1.6 ALGORITHM PROOF The algorithm proof will be performed by a dimensioning DAT, RTi, SST and SSTPF for a given general problem and proving in a constructive way that with the calculated dimensioning, for all possible couple (INCVECT, OUTVECT), exist a set of parameters W that allows the desired transformation S → C . The proof will be carried out following this scheme: 1. for each stage, a number of links (rows * pages) sufficient to allocate all addresses to be compressed is allocated (sufficient condition); 2. between each pair of adjacent tables a convenient partitioning (number of pages, number of rows), suitable to avoid routing congestion, is defined (sufficient condition); Steps (1), (2) prove that between each pair of tables all the addresses can be allocated and routed without congestion. This prove the algorithm since steps (1) and (2) are iterated on all tables starting from, the SST and propagating backward to the DAT. 3.1.6.1 DIMENSIONING OF SST AND SSTPF The set of addresses to be compressed S has n s elements. As a consequence: (1) n cpr = ceil (log 2 ( n s )) The number of clusters N cluster (which must be a power of 2) is chosen depending on the required maximum duration of the sequential search phase, which depends on the length of each sequential search list ( SSLL ). So, SST is a table of N cluster pages where each page has SSLL rows. SSTPF is a table with N cluster rows. 3.1.6.2 DIMENSIONING OF RTI - PREAMBLE The dimensioning of the routing tables RTi starts from the one near the SST (RTnst) and propagate backward to RT1. To characterize each RTi, three dimensions are needed: PGL RTi page length for i-nth RTT ( PGL RTi is a power of 2, N PGL RTi = log 2 PGL RTi ); Npg RTi number of pages of RTi; WL RTi word width of RTi (expressed in bit). It is crucial to choose the values of Npg RTi and n PGL RTi sufficiently large to avoid routing congestion. To do this, a set of equations, each one taking in account each possible different kind of block condition, must be written. 3.1.6.3 DIMENSIONING OF RTNST Starting from the table RTnst (the one feeding the connected to SST), in order to address each page of SST the following relation must be verified. (3) WL RTnst = log 2 N cluster . (4) Npg RTnst * 2 n PGL RTnst > 2 n cpr , Equation (4) defines an increment of the number of compressed addresses sufficient to ensure that in RTnst a sufficient number of links to allocate all the n s addresses belonging to S (case of fully shuffled addresses) is present. In order to set a proper value of Npg RTnst , a strategy to avoid routing congestion must be followed. 3.1.6.3.1 No congestion condition A key factor to be kept under control in any routing process is the congestion of Routing Tables; each incoming address is in fact «routed» to the correct cluster passing through the Routing Tables. The congestion occurs in those rows where the USED fields have a relatively high value; this happens when a lot of different addresses exhibit the same slice of bits s ( b l ,... b m ) in the same RTi (case of fully collapsed addresses). In this case, these collapsing addresses must be split on different pages and this set the number of pages for each RTi. The following equation expresses this circumstance eq. (5) expresses a circumstance based on a property of binary numbers: the number of vectors of n bit which exhibit the same pattern of n PGL RTnst adjacent bits (in any arbitrary but fixed position in the vector) is The number of addresses to be considered is upper bounded by 2 n cpr . Thus, the minimum between and 2 n cpr must be chosen In eq. (5), the expression min take the value 2 n cpr in any pratical case, as a consequence eq. (5) becomes: (5') Npg RTnst ≥ N cluster ; eq.(5/5') defines a sufficient condition to avoid congestion at nst stage (RTnst). Now, substituting eq. (5') in equation (4) we obtain: (6) n PGL RTnst ≥ n cpr -log 2 ( N cluster ); The latter relationship that must be verified for n PGL RTnst is determined by a reachability condition. 3.1.6.3.2 Reacheability condition This condition imposes that all pages of SST can be reached from any fully routed page of RTnst (a page in which the USED field is different from zero for at least a row) (7) n PGL RTnst ≥ log 2 ( N cluster ). Eq. (5') and (6) and (7) give the required dimension of RTnst. Besides dimensioning, another parameter needs to be defined in order to perform the algorithm presented in the previous paragraph: that is, the maximum reuse for each row of RTnst, that is the maximum acceptable value for the RTnst[j,k].USED field must be determined; this value will be named n reuse RTnst . This value is calculated on the base of an allocability condition. 3.1.6.3.3 Allocability condition If in any row of any page of RTnst the USED field exceeds the parameter SSLL, the addresses belonging to that row will not be allocable by any page of SST (not even by an empty page because an empty page can allocate a maximum of SSLL entries). To prevent this circumstance the value for n reuse RTnst must be bounded by SSLL: (8) n reuse RTnst ≤ SSLL . When this equation is verified, the dimensioning of RTnst is completed. Summarizing: WL RTnst = log 2 N cluster ; Npg RTnst ≥ N cluster ; n PGL RTnst ≥ n cpr - log 2 ( N cluster ); n PGL RTnst ≥ log 2 ( N cluster ). To save memory and to simplify hardware implementation: WL RTnst = log 2 ( N cluster ); npg RTnst ≥ N cluster ; n PGL RTnst ≥ n cpr -log 2 ( N cluster ); n PGL RTnst ≥ log 2 ( N cluster ). 3.1.6.4 DIMENSIONING OF RTI For all the other RTi different from RTnst, the above remains valid by substituting N cluster with Npg RTnst . Thus: (9) WL RTi = log 2 ( Npg RTi ); and the following equation sets an increment for the number of compressed addresses (10) Npg RTi *2 n PGL RTi > 2 n cpr , sufficient to ensure that in the i-nth stage (RTi), a sufficient number of links to allocate all the n s addresses belonging to S (case of fully shuffled addresses) is available. As for RTnst, the maximum reuse for each row of RTi, that is the maximum acceptable value for the RTi[j,k].USED field must be determined in order to perform the algorithm presented in the previous paragraph; this value will be named n reuse RTi and is calculated on the base of the allocability condition. 3.1.6.4.1 Allocability condition If in any row of any page of any Rti, the USED field exceeds a certain function of the next RTi (RTi+1), the addresses belonging to that row will not be allocable by any row of any page of RTi+1 (not even by an empty page because an empty page of RTi+1 can allocate a maximum of PGL RTi +1 * n reuse RTi+1 entries). If this bound is exceeded, n reuse RTi+1 will be exceeded somewhere in RTi+1 and so on up to reach RTnst and eventually SST where the overallocation error (RTnst[j,k].USED > SSLL) will be evidenced. The bound PGL RTi +1 * n reuse RTi +1 is valid when the addresses routed by a row of RTi are symmetrically split among the PGL RTi +1 rows of a page of RTi+1; this is an optimistic circumstance. In the worst case all these addresses falls into the same row and consequently the bound will be n reuse RTi+1 . Summarizing: (11) n reuse RT i ≤ PGL RTi +1 * n reuse RTi +1 all addresses are symmetrically split into PGL RTi +1 row of a page of RTi+1; (12) n reuse RTi ≤ n reuse RTi +1 all addresses fall into the same row of a page of RTi+1; To set the less strict condition as a bound, a couple of equations must be simultaneously verified on both RTi and RTi+1; so the following system must be verified for each pair of adjacent Rti. Taking into account that n reuse RTi+1 can not be exceeded, it can be considered as SSLL for SST in case of fully collapsed addresses, so the no congestion condition remain valid by substituting N cluster with Npg RTi +1 where Npg RTi +1 is known. Eq.(14) can be simplified as previously done with eq.(5) and this leads to (14') Npg RTi ≥ Npg RTi +1 ; eq.(14/14') represents sufficient condition to avoid congestion at the i-nth stage. Now, by substituting eq. (14') in equation (10) we obtain: (15) n PGL RTi ≥ n cpr -log 2 ( Npg RTi ); To save in memory requisite, the same number of pages can be allocated for each RTi: Npg RTi = Npg RTi +1 . The last condition that needs to be verified for n PGL RTi is still set by the reachability condition. 3.1.6.4.2 Reacheability condition This condition impose that all the pages of RTi+1 can be reached from any fully routed page of RTi (a page in which the USED field is different from zero for anyone row): (16) n PGL RTi ≥ log 2 ( Npg RTi+ 1 ). Eq. (14') and (15) and (16) give the dimension of RTi ∀ i < nst. Summarizing: WL RTi = log 2 ( Npg RTi +1 ); Npg RTi ≥ Npg RTi +1 ; n PGL RTi ≥ n cpr - log 2 ( Npg RTi ); n PGL RTi ≥ log 2 ( Npg RTi +1 ). To save memory and to simplify the hardware implementation: WL RTi = log 2 ( N cluster ); Npg RTi ≥ N cluster ; n PGL RTi ≥ n cpr - log 2 ( N cluster ); n PGL RTi ≥ log 2 ( N cluster ). 3.1.6.5 DIMENSIONING OF DAT The slices of bits which address the rows of each DAT, RTi are related by the following equation so, Regarding the parameter WL DA T it is set by eq.(19) (19) WL DAT = log 2 ( Npg RT 1 ), Eq.(18) and (19) give the dimension of DAT WL DAT = log 2 ( Npg RT 1 ). Assuming Npg RT 1 = N cluster , as previously done with RTi WL DAT = log 2 ( N clusters ). 3.1.7 ABOUT THE ALGORITHM As already assumed a proof that routing congestion will be prevented implies that allocation of n reuseRTi links be not exceeded. This is done by monitoring all the fields RTi[j,k].USED during a Configuration Mode phase will allocating links on the emptiest pages. This allocation strategy may be referred as «maximum spread» since it spreads the addresses on the largest possible number of pages. 3.2 EXTENSIONS OF THE CSSA TECHNIQUE Performances of a CSSA system can be further improved by modifying the algorithm. These alternative embodiments of the basic CSSA technique of the invention will be referred to as EXTENDED CSSA followed by the notation #1, #2, #3, #4 for identifying as many alternative embodiments. Two kinds of improvements can be obtained: 1) further decreasing memory size (Msize); 2) further decreasing number of clock cycles needed to carry out the algorithm (Nclk). 3.2.1 EXTENDED CSSA #1 Basic CSSA algorithm can be further improved modifying the sequential search phase. The extension is named EXTENDED CSSA#1. Two kinds of improvements can be obtained: further decreasing memory size (Msize) or further decreasing number of clock cycles needed to carry out the algorithm (Nclk). These further improved embodiments generally imply replacing the Sequential Search step with an Extended Sequential Search step. In architectural terms this means replacing the SST (Sequential Search Table) with an ESST (Extended Sequential Search Table) as in Figure 16. An architecture of ESST block according to a first embodiment (EXTENDED CSSA #1) is shown in Figure 17. The ESST block is built with a bank of Nsst SST I , with Nsst independent Address Generators, each Address Generator generating an address for the corresponding SST i . A set of Nssti comparators which compare the result of the search for each SSTi with the Incoming Vector (INCVECT) complete the architecture. As the CLuster Identifier (CLID) is provided, the search phase starts in parallel on all the SSTis. As soon as a SSTi finds the Compressed Address, the search stops, the Compressed Address is sent out and validated through the Outcoming Vector Validation. To better understand the magnitude of the improvement it is useful to compare a basic CSSA system with an EXTENDED CSSA#1 system for solving the same compression problem. a) The SST in the CSSA is defined by these parameters: Ncluster_sst number of clusters (pages) of SST; SSLL_sst number of rows of each page of SST. Regarding the Memory Requirements the CSSA is characterized by these parameters: I Msize_dat_cssa amount of memory needed by DAT in CSSA; Msize_rt_cssa amount of memory needed by all the RTi in CSSA; Msize_sst amount of memory needed by SST in CSSA; Msize_cssa= Msize_dat_cssa + Msize_rt_cssa + Msize_sst. Regarding the speed Requirements the CSSA is characterized by these parameters: Nclk_dat_cssa number of clock cycles needed to perform the CSSA algorithm through DAT in CSSA; Nclk_rt_cssa number of clock cycles needed to perform the CSSA algorithm through all the RTi in CSSA; Nclk_sst number of clock cycles needed to perform the CSSA algorithm through SST in CSSA; Nclk_cssa = Nclk_dat_cssa + Nclk_rt_cssa + Nclk_sst_cssa (total number of clock cycles to perform the CSSA algorithm). b) The ESST in the EXTENDED CSSA#1 is defined by these parameters: Nssti number of SSTi which are instantiated in ESST; Ncluster_ssti number of cluster (pages) of each SSTi; SSLL_ssti number of rows of each page of each SSTi; Regarding the Memory Requirements the Extended CSSA#1 in characterized by these parameters: Msize_dat_ecssa amount of memory needed by DAT in EXTENDED CSSA#1; Msize_rt_ecssa amount of memory needed by all the RTi in EXTENDED CSSA#1; Msize_esst_ecssa amount of memory needed by all the SSTi in EXTENDED CSSA#1; Regarding the Speed Requirements the Extended CSSA#1 in characterized by these parameters: Nclk_dat_ecssa number of clock cycles needed to perform the CSSA algorithm through DAT in EXTENDED CSSA#1; Nclk_rt_ecssa number of clock cycles needed to perform the CSSA algorithm through all the RTi in EXTENDED CSSA#1; Nclk_esst_ecssa number of clock cycles needed to perform the CSSA algorithm through all the SSTi in EXTENDED CSSA#1; Nclk_ecssa = Nclk_dat_ecssa + Nclk_rt_ecssa + Nclk_esst_ecssa (total number of clock cycles to perform the EXTENDED CSSA#1 algorithm). If the goal is Msize reduction the parameters are set to obtain the maximum saving in memory requirements and the relationship between a basic CSSA system and a system according to the embodiment: EXTENDED CSSA #1 is: Ncluster_ssti = Ncluster_sst for each i; SSLL_ssti = SSLL_sst; each cluster in EXTENDED CSSA#1 is multiplied by a Nssti factor, but being used Nssti SSTi tables in parallel the total Sequential Search phase is still the same as in the normal CSSA. As a consequence of this parameters setting, the time performances are Nclk_dat_ecssa = Nclk_dat_cssa; Nclk_rt_ecssa = Nclk_rt_cssa; Nclk_esst_ecssa = Nclk_sst_cssa. Being the total number of clock cycles dominated by Nclk_esst_ecssa in EXTENDED CSSA#1 and by Nclk_sst_cssa in CSSA, we can state that Nclk_ecssa ≅ Nclk_cssa; this is only a rough estimation, the effective time performance is even better, due to the possible reduction of the number of RTi stages, as result of the increased dimension of clusters in the EXTENDED CSSA#1 case. The memory requirements are Msize_esst_ecssa = Msize_sst_cssa * Nssti; this is the only memory increase because, as will be proved in the next paragraph devoted to performance comparison, Msize_dat_ecssa < Msize_dat_cssa; Msize_rt_ecssa < Msize_rt_cssa; as a consequence, Msize_ecssa < Msize_cssa. If the goal is Nclk reduction, the parameters will be set to obtain the maximum gain in speed, while keeping constant the total amount of memory, the relationship between a basic CSSA system and a system according to the embodiment EXTENDED CSSA #1 is: Ncluster_ssti = Ncluster_sst for each i; SSLL_ssti = SSLL_sst/Nssti; Nssti must be chosen so that SSLL_ssti ≥ 1. each cluster in EXTENDED CSSA#1 still has the same size as in CSSA, but being used Nssti ssti in parallel the total Sequential Search phase is reduced by a Nssti factor. As a consequence of this parameters setting, the memory requirements are Msize_dat_ecssa = Msize_dat_cssa; Msize_rt_ecssa = Msize_rt_cssa; Msize_esst_ecssa = Msize_sst_cssa; thus, Msize_ecssa = Msize_cssa. Regarding the time performances, Nclk_dat_ecssa = Nclk_dat_cssa; Nclk_rt_ecssa = Nclk_rt_cssa; Nclk_esst_ecssa = Nclk_sst_cssa/Nssti. Being the total number of clock cycles is dominated by Nclk_esst_ecssa in EXTENDED CSSA#1 and by Nclk_sst_cssa in CSSA, we can state that Nclk_ecssa ≅ Nclk_cssa/Nssti. 3.2.2 EXTENDED CSSA #2 Another embodiment of the basic CSSA can be realized with yet another ESST implementation. This embodiment is shown in Figure 18. Instead of a plurality of SST wide as the incoming vector, as in EXTENDED CSSA#1, it is possible to use a single, wide memory, large as the incoming vector width multiplied by Nsst. In this case a single address generator is needed, but Nsst comparators are needed. In any case the performances obtained with the EXTENDED CSSA#1 and the EXTENDED CSSA#2 are equivalent. 3.2.3 EXTENDED CSSA #3 Another possible embodiment of the CSSA, EXTENDED CSSA#3, is based on splitting of the algorithm in two different steps, named respectively Cluster Detection and Sequential search. Each step can last till to one cell (packet) time, due to the two fifo pipeline, that is implemented as depicted in Figure 19. In the first phase (Cluster Detection) the DAT and RTi analysis are performed, and a cluster identifier (CLID) is detected. In the second step the Sequential Search is performed to find the compressed identifier. According to this embodiment it is possible to increase the cluster size, with strong benefits in terms of memory size reduction. The price to pay is a latency of two cells (packets) as compared to the "standard" CSSA latency of one cell. In any case the Msize reduction is limited by the size of the SST, that must be at least equal to the minimum theoretical size (CAM). This embodiment can be easily coupled with either the EXTENDED CSSA #1 or the EXTENDED CSSA #2 architecture to increase the cluster size again. 3.2.4 EXTENDED CSSA #4 Yet another and particularly efficient embodiment of the basic CSSA technique of this invention may be suitable to compress different classes or sets of addresses S 1 , S 2 , ..., S Nclasses , the sets of addresses to be compressed (whose union is named S ), belonging to the set U , the whole addressing space. For each address belonging to the generic set S j the algorithm must identify one and only one address belonging to C j , the set of compressed addresses which corresponds to the set S j (i. e. perform a transformation S j → C j ); this must be verified ∀ j ∈ 1,.., Nclass. An example of graphical representation of this problem is given in Figure 20. According to this embodiment (EXTENDED CSSA #4), a combination of the three fundamental steps of the basic algorithm: splitting of S in subspaces via direct addressing table (DAT), clustering via routing tables (RT ij ) and sequential search via at least Nclass sequential search table (SST j ), are used. However, the system of this embodiment combines in a tree, with an arbitrary number of levels, different Clustering phases (RTi,branch j-nth) working in parallel and originating from a common branch, said common branch being the end point of a Splitting phase (DAT) plus a Clustering (RT1_root, RTi_root, ..., RTn_root) phase which is the common ancestor of all the branches, each leaf of the tree being constituted by a Sequential Search phase (SST branch j-nth). This leads to a structure that may be described as a "RT tree". Figure 21 shows the general structure of an EXTENDED CSSA#4 system. The system behaves in different ways depending on the incoming vector domains, and the various SST branch j-nth and RTi,j-nth_branch are tuned in a most efficient way. This architecture allows memory savings by sharing the DAT and some RTi,j-nth_branch before any branching off. An example of implementation is depicted in Figure 22. This embodiment is particularly suitable for IP and multicast applications. 3.3 PERFORMANCE COMPARISON In order to perform a correct benchmarking between various address compression techniques, it is useful to define the main parameters of a generic «address compression function». Figure 23 shows the parameters used to evaluate the architectures. 2 N is the number of possible incoming identifiers (N is the length, in bits) 2 Ncpr is the number of possible Compressed identifiers (Ncpr is the length, in bits) AVclk is the minimum packet interarrival/cell time (in clock cycles) Nclk is the number of clock cycles needed to perform address compression Msize is the total memory size needed to perform address compression Nmem is the number of physical memory needed The parameter N typically dominates the memory size requisite and the Ncpr parameter the complexity of the compression process. Any architecture will be constrained to consume no more clock cycles ( Nclk ) than Avclk. The RAM requisite Msize provides the indicator of the efficiency of the processing structure. Two scenarios have been investigated: the «ATM» and the «IP» . Both scenarios have been tested by supposing a 622 Mbit/s (STM-4) full throughput. Obviously, other speed assumptions (e.g 155 Mbit/s or 1.3 Gbit/s) will imply a fully different comparison results. A 622 Mbit/s throughput has been chosen in order to be in line with present trends in ATM switches and IP router technology. The «ATM» scenario implies N=24 bits. Assuming 53 bytes/cell, to prove these architectures at 622 Mbit/s it means Avclk=26. The «IP» scenario implies N=32 bits. Assuming 64 bytes for the shortest packet, to prove these architectures at 622 Mbit/s it means AVclk= 32. Input parameter for benchmarking Scenario N AVclk «ATM» 24 26 «IP» 32 32 Each architecture will be tested, for each scenario, for any Ncpr value between 2 and 16: this means examining the performance over a very wide range of possible applications. By writing the performance as an equation and the constraint as a disequation, it is possible to state: Msize = F(N, Ncpr, P1, P2, ...) for Ncpr ∈ (2..16) Nclk = G(N, Ncpr, P1, P2, ...) ≤ A Vclk for Ncpr ∈ (2..16) P1, P2, etc are «technique dependent free parameters». For example, when dealing with a Binary Tree Algorithm the free parameter is the number of stages Nst ; when using a Clustered Sequential Search Algorithm the free parameter is the cluster size, SSLL . In order to arrive at an objective performance evaluation, for each technique, the analysis has been performed using the «good designer approach»: for each technique, for each W, for each Ncpr, the best value of the free parameter (the value that minimizes Msize) has been identified and applied. Figure 24 shows this concept. As far as the dis-equation Nclk ≤ Avclk is concerned, it is possible to argue that, if the clock that reads the memories M 1 ..M Nmem is faster (e.g. double) than the clock of the incoming serial stream (address) the performance of the system can be improved. This is true, but, because the same «trick» could be applied with the same benefits to any technique, a «common reference clock» has been defined in order to perform a real comparison. The applied«reference clock» is the clock related to the incoming address. 3.3.1 CAM PERFORMANCE The analysis of CAM is really fast. The number of requested bits is Msize = N*2 Ncpr (bits) There are no free parameters, and the Nclk will be, in any case, less then Avclk. Nmem obviously is 1 With Ncpr= 16 (2^16=64K compressed identifiers) around 1.5 and 2 Mbits of CAM are needed. There is to point out that CAM cell is more complex respect to conventional RAM, and that serious technology problems arise increasing its size. 3.3.2 PURE SEQUENTIAL SEARCH ALGORITHM PERFORMANCE An analysis of the efficiency of a sequential search algorithm is rather immediate. The Add vector scans the memory M and, if a data in the memory matches the incoming address value, the compressed identifier is set equal to the memory Add. The process is summarized in Figure 25. The number of bits requested is (1) Msize = N*2 Ncpr (bits) and the clock cycles needed are (2) Nclk = 2 Ncpr Obviously, this technique can be applied only with small Ncpr (2 to 4,5) values. Nmem is 1. The following tables describe the requisites for the two considered scenarios. 3.3.3 EXTENDED SEQUENTIAL SEARCH ALGORITHM PERFORMANCE In this case a free parameter exist. It is the number of memories where it is possible to perform simultaneously a sequential search (Nmem). For each memory, an Add(i) vector scan M(i) and, if a data in a memory (i) matches the incoming address value, the compressed identifier is set equal to the memory (i) concatenated to Add.. The process is summarized in The number of bits requested is (1) Msize = N*2 Ncpr (bits) and the clock cycles needed are (2) Nclk = (2 Ncpr /Nmem) Unfortunately, the number of memories that is possible to put in place is limited, and 8 (at most 16!) may be regarded as the largest possible value for Nmem. This limit 2 Ncpr to 256, 512. The following tables show the requisite for the two scenarios. 3.3.4 BINARY TREE ALGORITHM PERFORMANCE Figure 27 shows the structure for a binary tree search. The N-bit wide incoming address is split into different vectors of size W0, W1, W2, W(Nst- 1), obviously providing for (1) N=ΣWi , for i=0, (Nst-1) These addresses are sent to Nst different memory banks (these banks may be organized in a single physical memory array: Nmem=1). The output data belonging to bank i is used, concatenated with W(i+1), to address the bank (i+1). In this way any bank is Ncpr bit wide and the number of address bits needed is (2) Add(DAT) = W0 (3) Add(RTi) = Wi+Ncpr Because there is no gain in having different values for Add(RTi), it may be set (4) Wi = W^ , for i=1, Nst-1 By applying the (4) in the (1): (5) N = W0 + (Nst-1)*W^ To minimize the global needed memory, the depth of the DAT must be less or equal to the depth of the other memories (6) W0 ≤ W^+Ncpr By combining the (5) and the (6): (7) W^ ≥ (N - Ncpr) / Nst therefore, the following is implemented (8) W^ = ceil((N - Ncpr) / Nst) The equation (8) will be used to size any memory applied in the technique using Nst as a free parameter. The number of clock cycles needed is (8) Nclk = 2 * Nst The «2» factor appears because the address used to access the «next» memory bank is written in the «actual»: a clock cycle is needed to read the «actual» and another to prepare the address for the «next». This shows that the technique remains valid in any scenario. The performance is (9) Msize = (Ncpr+1)*2 W0 + (Nst -1) * (Ncpr+1)*2 (W^+Ncpr) Any bank is considered (Ncpr+1) bits wide because an «active» bit is needed, for each address. As an example of the work performed to evaluate the technology, table 9 shows the W^ parameter, calculated by applying equation (7) in «ATM» scenario. table 10 and table 11 show the equation Msize = F(N, Ncpr, Nst). In the last two columns the best performance value in terms of a lowest value of Msize(N, Ncpr) is pointed out, together with the related value of Nst. In the tables are reported the overall performances for a binary tree search technique, which can be applied with any Ncpr value. It is evident the fact that implementation of a binary tree search algorithm is almost 10 lines more burdensome than the implementation of a CAM technique 3.3.5 CLUSTERED SEQUENTIAL SEARCH ALGORITHM PERFORMANCE Figure 28 shows the structure that implements a Clustered Sequential search algorithm of the invention. Let Cs be the size of the clusters, formerly addressed as SSLL . For each cluster, the number of locations is 2 Cs . Let 2 Cn be the number of clusters, formerly addressed as Ncluster. Moreover, let C j be the j-th cluster. The N bit wide incoming address is split into different vectors of size W0, W1, W(Nst-1), obviously verifying that: (1) W=ΣWi , for i=0, (Nst-1) These addresses are sent to Nst different memory banks, called DAT and RTi respectively. These banks may be organized in the same physical memory. The output data belonging to Rti, concatenated with W(i+1) is used to address RT(i+1). The last pointer, read from RT(Nst-1), is used to address a cluster Cj within another memory, called SST. The SST stores the «active» incoming address values (i.e. the addresses handled by the structure), spread in the right cluster. Normally, the SST memory has a size different from the one that hosts the DAT and the RTi. The Clustered Sequential Search Algorithm has Nmem=2. A sequential search, from the first to the last location belonging to cluster Cj, is performed. If the incoming address is equal to the data stored in the SST, the address of the SST itself is validated as the corresponding Compressed Identifier. As far as the depth of the SST is concerned, there are 2 Cn clusters, each 2 Cs deep. The overall depth SST is 2 Ncpr . Therefore, it may be stated that: (2) 2 Cn *2 Cs = 2 Ncpr and (4) Ncpr = Cn + Cs These relationships give the size of SST: (5) SSTsize = N*2 Ncpr Of course the rules stemming from the «maximum spread» approach and identified in paragraph 4, must be applied to RTi. In RT i (i∈ 1, Nst-1) Cn «pages» are addressed by the value stored in RTM i-1 . Within a «page», Cs locations are needed, in order to prevent a blocking condition. The stored value is Cn bit wide. This give the RTM i size. (6) RT i size = Cn*2 Ncpr with (i∈ 1, Nst-1) The first bank, DAT, performs a flat addressing function between the W0 vector and the first pointer which is Cn bits wide. To minimize the total needed memory, the depth of DAT must be less or equal to the depth of the other memories constituting the RT i . In fact, (7) W0 ≤ (Cn+Cs) = Ncpr moreover (8) N = W0 + (Nst-1)*Cs Combining the (5) and the (6) we have (9) Nst ≥ (N - Ncpr + Cs) / Cs thus verifying (10) Nst = ceil((N - Ncpr + Cs) / Cs) The equation (10) is used to determine Msize by using Cs as a free parameter. In the following tables the relative values of Cs and Ncpr are shown. The shaded values reflect a situation where Ncpr ≤ Cs The number of clock cycles needed is (11) Nclk = 2 * Nst + 2 Cs The «2» factor appears because the address used to access the «next» memory bank is written in the «actual»: a clock cycle is needed to read the «actual» and another to prepare the address for the «next». During SST search only a clock cycle per address is needed. The following tables show the relation values of Cs and Ncpr.. The two tables show that the CSS technique can be applied only with small Cs values, 3 or 4. (this means clusters with 8, 16 locations) The performance is (12) Msize = Cn*2 W0 +(Nst-1)*Cn*2 Ncpr + W*2 Ncpr Table 18 and Table 19 show the results of the above equation. Msize = F(N, Ncpr, Cs). In the last two columns the best performance value for Msize(N, Cs) is pointed out, together with the related value of Cs. These are the overall performance values of the Clustered Sequential Search Algorithm of the invention. Two physical memories are needed (Nmem=2): the first hosting the DAT and the plurality of RTi banks, the second the SST. The method of the invention can be implemented with different Ncpr values. The method remains valid as long as Ncpr is extremely small (2,3). In the range Ncpr ∈ (8,16) the addressed cluster size is 4 (that means a cluster with 16 positions). The practicable conditions are resumed in the following tables. Of course, performing the sequential search on different SSMs, in parallel, (as in an Extended Sequential Search), it is possible to accept larger Cs values without increasing Nclk. In an embodiment of that kind, Msize can be reduced further. 3.3.6 OVERALL PERFORMANCE COMPARISON Table 22 and Table 23 shows a comparison between the various known techniques and the CSSA technique of the invention for the «ATM» scenario, table 23 shows the same comparison for « IP » scenario. The technique that covers the entire Ncpr field with the smallest Msize is obviously the CAM, but in this case there are serious problems of implementation, especially for relatively large Ncpr values; moreover it must be remember that Msize is given in terms of «CAM» bits, which are memory structures for more complex than ordinary «RAM» structures. The areas applicability of a sequential search algorithm (pure or extended) cover only relatively small Ncpr values. On the other hand, the Msize requisite is minimum. This approach may remain a candidate in equipment that needs a limited number of channels (up to 512). The classical Binary Tree search and the Clustered Sequential Search of the present invention appear to be the only two techniques capable of covering the entire spectrum of applications. However, by looking to the proceeding tables, it is clear that the memory needed for implementing the CSS is far less than the memory needed for a classical Binary Tree search. In the previous tables, the Msize value for the CSS and for the Binary Tree is normalized in respect to a CAM Msize. Then the normalized BT value is divided by the correct normalized CSS value. This produces an indication of the gain obtained in applying the CSS technique instead of the BT.As can be readily appreciated, the gain ranges from nine to five times in an ATM scenario, and from 15 to six in an IP scenario. This means that, for Ncpr greater than 8 or 9, the Clustered Sequential Search technique of the invention is the technique that gives by far the best overall performance. Moreover, with the CSS it is possible to markedly the reduce cost of implementation. For example, in the ATM scenario, with Ncpr=12 (4096 entries), the needed memory for a Binary Tree is 1491 Kbits and for the CSS is 229 Kbits. If the address compression function is implemented by way of an ASIC, if the Binary Tree technique is used it may be necessary to employ an external memory. This can be avoided by using the CSSA: technique of this invention, thus reducing the pin requirement.

Claims: A method of address compression for a data stream structured in packets or cells, each including a destination identifier consisting of a string of N bits (INCVECT) constituting an address space (U) of size 2 N , consisting in an algorithm, executable in a predictable time span, mapping 2 Ncpr points of said address space (U) belonging to at least a subset (S) of identifiers to be compressed to a relevant string of Ncpr bits, constituting a compressed address space (C) of size 2 Ncpr where Ncpr<N, characterized in that the method comprises the steps of: a) splitting said address space (U) of incoming N-bit identifiers into a plurality of identically sized up subspaces by the use of a direct addressing table (DAT), a row of which is pointed by a first predefined slice of the incoming N-bit identifier (INCVECT) for outputting a first pointer datum; b) clustering said subset (S) of N-bit identifiers contained in said subspaces by the use of a plurality of routing tables (RTi) having the same number of pages, the tables being coupled in a cascade, a page of the first table (RT1) being pointed by said first pointer datum and the row of the pointed page being selected by a predefined second slice of the incoming N-bit identifier (INCVECT), for outputting a second pointer datum, a page of each of the following tables of the cascade being pointed by the pointer datum output by the preceding table and the row of the pointed page being selected by a respective predefined slice of the incoming N-bit identifier (INCVECT), for outputting from the last routing table (RTn) a final pointer datum, thus identifying a series of clusters located in at least a sequential search table (SST), each cluster smaller or equal to a predefined number (SSLL) and storing only points of said subsets that belong to the said subset (S); c) performing, on a cluster of said first subset (S), having a size equivalent to said predefined number (SSLL) as defined in step b), a sequential search in at least a table (SST), said table being organized in pages, each page corresponding to a cluster, composed by a number of rows equal to said predefined number (SSLL), within a given packet or cell time slot, by pointing, with the pointer datum outputted by the last one of said routing tables (RTi) in cascade, a page on which said sequential search is performed; d) said pointer datum outputted by the last routing table, concatenated with the row index datum of the selected page of said sequential search table (SST) or plurality of tables, verifying the match with incoming N-bit identifier (INCVECT) constituting said compressed address of Ncpr bits. The method according to claim 1, wherein more then one sequential search table (SST) with the same number of pages are used, the same pointer datum output by the last one of said routing tables (RTi) in cascade, pointing a page of each sequential search table (SSTj) and the sequential search being performed in parallel on all the selected pages of the sequential search tables (SSTj), until the content of row of any of the sequential search tables, searched in parallel, verifies the match with said incoming N-bit identifier (INCVECT). The method according to claim 1, wherein each row of the sequential search table (SST) is adopted to store a predetermined number of vectors (OUTVECT) to be matched with said incoming N-bit identifier (INCVECT). The method according to one of the preceding claims, wherein the steps a) and b) are performed during a single cell or packet period, and the step c) is performed during the successive, cell or packet period, in a pipelined arrangement. The method according to claim 1, characterized in that the preceding steps further include: mapping different points or domains of said address space (U) belonging to a certain number (Nclasses) of subsets (S 1 , S 2 , S j , S Nclasses ) of identifiers to be compressed to as many strings constituting different compressed address spaces (C 1 , C 2 , C j , C Nclasses ); clustering at step b) said subsets (S1, S2, Sj, SNclasses) by the use of a plurality of routing tables (RTij), the tables being organized in a tree, a page of the first table (RT11) being pointed by said first pointer datum obtained at step a) and the row of the pointed page being selected by a predefined second slice of the incoming N-bit identifier (INCVECT), for outputting a second pointer datum, used to point a page of the following tables of the cascade (RT12) if the same subset (S1) has to be clustered or to point to at least two different tables (RT21 and RT22,...), downstream of a branching of said tree, if different subsets must be clustered to different compressed address spaces, for selecting, by means of a predefined slice of the incoming N-bit identifier (INCVECT), at least two different pointer data suitable to point to a next stage of Routing Table of said tree (RTij), and so forth until all bits of the incoming N-bit identifier (INCVECT) have been utilized, outputting from the last pointed routing tables (RTnj) a plurality of final pointer data (CLID 1 , CLID 2 , CLID j , CLID Nclasses ) identifying as many clusters in different sequential search tables (SST 1 , SST 2 , SST j , SST Nclasses ) each organized in pages composed by a number of rows equal to said predefined number (SSLL j ), each page corresponding to a cluster, and each sequential search table corresponding to points or domains or subsets (S j ) belonging to said address space (U), each cluster being smaller of or equal to said predefined number of rows (SSLL 1 , SSLL 2 , SSLL j , SSLL Nclasses ) and storing only points belonging to the said subset of N-bit identifiers (S 1 , S 2 , S j , S Nclasses ) which map to the corresponding said (C 1 , C 2 , C j , C Nclasses ) subsets of compressed addresses; performing at step c), on the clusters belonging to each sequential search table (SST 1 , SST 2 , SST j , SST Nclasses ) pointed by said final pointer data (CLID 1 , CLID 2 , CLID j , CLID Nclasses ) a sequential search by means of different address generators, one for each sequential search table; verifying at step d) the match of the data stored in said sequential search tables (OUTVECT j ) with said incoming N-bit identifier (INCVECT), identifying said compressed addresses subsets (C 1 , C 2 , C j , C Nclasses ) of compressed addresses. A data processing structure for performing address compression for a data stream structured in packets or cells, each including a destination identifier consisting of a string of N bits (INCVECT) constituting an address space (U) of 2 N size, comprising mapping means (DAT, RTi, SST, =) for mapping in a predictable time span 2 Ncpr points of said address space (U) belonging to at least a subset (S) of identifiers to be compressed to a relevant string of Ncpr bits constituting a compressed address space (C) of size 2 Ncpr where Ncpr<N, said mapping means (DAT, RTi, SST, =) receiving an incoming N-bit identifier (INCVECT) belonging to said address space (U) containing unique address information upon verifying a match of the destination information contained in the N-bit incoming identifier (INCVECT) with an outcoming N-bit vector (OUTVECT) among a plurality of 2 Ncpr elements, each one in direct relationship with a compressed address, characterized that the mapping means comprising: a) a direct addressing table (DAT) for splitting said address space (U) into a plurality of identically sized up subspaces and outputting a first pointer datum from a row to which a first predefined slice of said incoming N-bit identifier (INCVECT) is pointing for; b) a cascade of routing tables (RT1,..., RTn) organized in the same number of pages, the first of which is coupled in cascade to said direct addressing table (DAT), each organized in selectable pages that are pointed by the pointer datum of the preceding table in the cascade, the first table of the cascade (RT1) having a page pointed by said first pointer datum outputted by said direct addressing table (DAT), and a row of the thus pointed page of all routing tables of the cascade being pointed by respective slices of said incoming N-bit identifier (INCVECT), which is inputted to each routing table; c) at least a sequential search table (SST) organized in a plurality of pages, or clusters, pointed by the datum outputted by the last table (RTn) of said cascade of routing tables; d) validation means (=) verifying the coincidence of the destination information contained in said incoming N-bit identifiers (INCVECT) with the information contained in the sequentially searched rows (OUTVECT) of the pointed page of said sequential search table (SST) or plurality of tables. The data processing structure according to the preceding claim, characterized in that it includes two or more sequential search tables (SST) organized in the same number of pages pointed by the same datum outputted by the last table (RTn) of said cascade of routing tables and searched simultaneously in parallel. The data processing structure according to claim 6, characterized in that it includes a sequential search table (SST) in which each row hosts more than one vector (OUTVECT) to be matched with said incoming N-bit identifier (INCVECT). The data processing structure according to any claim from 6 to 8, characterized in that the operations performed by said direct addressing table (DAT) and the operations performed by said cascade of routing tables (RT1,..., RTn) are executed during a single cell (packet) period, and the operations performed by said at least one sequential search table (SST) are executed during the successive cell (packet) period, said direct addressing table (DAT) and said tree of routing tables (RT ij ), and said sequential search table (SST j ) are organized in a pipeline employing two first-in-first-out registers two cells at the time. The data processing structure according to claim 6, characterized in that said mapping means (DAT; RT 11 , ..., RT ij ,..., RT nNclasses , SST j ) are suitable for mapping different points or domains of said address space (U) belonging to a certain number (Nclasses) of subsets (S 1 , S 2 , S j , S Nclasses ) of identifiers to be compressed to as many strings constituting different compressed address spaces (C 1 , C 2 , C j , C Nclasses ), the mapping means further including: a tree of routing tables (RT 11 , ..., RT ij ,..., RT nNclasses ), the first of which is coupled in cascade to said direct addressing table (DAT), each routing table being organized in selectable pages that are pointed by pointer data outputted by preceding tables in the tree-like cascade, the first table of the tree-like cascade (RT11) having a page pointed by said first pointer datum outputted by said direct addressing table (DAT), and pointing to a chain of routing tables or branching to at least two chains, a row of the thus pointed page of all routing tables of the tree-like cascade being pointed by respective slices of said incoming N-bit identifier (INCVECT), which is inputted to each routing table, the last routing table (RT nj ) of each branch in said tree-like cascade generating a final pointer datum (CLID 1 , CLID 2 , CLID j , CLID Nclasses ); at least a number of sequential search tables (SST j ) equal to said certain number (Nclasses) of subsets (S 1 , S 2 , S j , S Nclasses ), each table being organized in a plurality of pages, or clusters, pointed by the datum outputted by the last table (CLID j ) of said tree-like cascade of routing tables; validation means (=) verifying the coincidence of the destination information contained in said incoming N-bit identifier (INCVECT) with the data (OUTVECT j ) contained in the pages, belonging to said sequential search table (SST j ), pointed by final pointer data (CLID 1 , CLID 2 , CLID j , CLID Nclasses ) generated by said last routing table (RT nj ) of each branch in said tree-like cascade.

Inventors: GEMELLI RICCARDO, PAVESI MARCO, GEMELLI, RICCARDO, PAVESI, MARCO
Applicants: ITALTEL SPA, ITALTEL S.P.A.
Application year: 1998
Main classification: H04L12
IPC codes: H04L12, H04L29