AFFINE TRANSFORMATION MEANS AND METHOD OF AFFINE TRANSFORMATION

Abstract: A transformation means for transforming memory cell addresses between different memory device topologies providing the use of minimum memory space and time required for storage and computing defect data and also the flexibility of approach which allows the use of a wide spectrum of mapping classes and simplification of the transforming procedure.

Description: AFFINE TRANSFORMATION MEANS AND METHOD OF AFFINE TRANSFORMATION Technical Field The present invention relates to a memory unit address transformation means and a method of transformation and may be used, for example, for address transformation from a logical address space into a topological address space in solid state memory devices, including semiconductor, ferroelectric, optical, holographic, molecular and crystalline atomic memories . The present invention is applicable in particular, though not exclusively, in test systems for engineering test analysis, for example, for processing and representation of defect data, or in memory redundancy allocation systems for establishing a relationship between memory unit addresses in different memory device topologies for the purposes of distribution of spare resources. Background of the invention In the memory industry, large electronic systems are produced having hundreds of integrated circuits called devices designed to implement a large number of logical functions. These functions are implemented by the logical design of the system. However, the actual physical structure of the system which specifies the actual physical locations of the electronic components necessary to implement the logical, i.e. electrical, functions, differs from the logical design. To test memory products after fabrication, different test methods are used, some of them being independent of the physical location of the memory cell, but most requiring knowledge of the placement of every cell. The address presented to the memory device is called the logical, or electrical, address; this may not be the same as the address used to access the physical memory cell or cells, which is called the topological, or physical address (see A.J.van de Goor "Testing Semiconductor Memories: Theory and Practice", publ. by John Wiley & Sons, 1996, pp.429-436). The translation of logical addresses into topological addresses is called address transformation, or mapping. When addresses are transformed, successive logical addresses may transform into non-successive topological addresses. One reason for this difference is that decoders are restricted in size in order to fit the topology of rows and columns of memory cells. A second reason is that, to maintain acceptable production yields, redundant cells are added during manufacture that can be used to replace faulty cells. Spare rows and columns cause a difference in the logical and topological address sequence. Lastly, different chip designs result in chip layouts in which on-chip address pads do not correspond to the standard pin numbers. The size and density of memory products has increased exponentially over time: from 2 10 bits in 1971 to more than 2 28 bits being sampled by manufacturers today. As the density of memory devices increases, the number of defects in them increases as well. To properly test a memory device, a detailed description of the internal topology and address mapping of the device is required in order to run complex redundancy schemes and optimize testing procedures. However, storing the address transformation table requires too much space. Besides, reverse transformation requires the same memory space as direct transformation and in the case of restricted memory is not possible. Therefore, means that were adequate for transformation under simpler conditions are far too slow and space consuming in the contemporary environment and often suffer from cost- inefficiency, thus creating a requirement for a system capable of transformation of the addresses using the minimum available space and in the minimum time. There are numerous mapping schemes described in the literature where a transformation is applied from a logical to a physical space. For example, US 4,774,652 describes a memory mapping scheme designed to simplify the access of pages in a cache memory system. However, these systems often make the reverse mapping very difficult, requiring a very large table with 2 n entries. There are several transformation procedures described in An Interactive Descrambler Program for RAMs with Redundancy, Kirschner,N. In Proc . IEEE Int . Test Conference, pp. 252-251 , 1982, together with a method of constructing a procedure that can perform the transformation operation to generate transformation tables. The known transformation means can scramble the address lines of a 64 Kbit memory chip using an 8-bit row address and a 8-bit column address. The equations describing the transformation operation for the row-select lines r 0 through r are given below, however in the construction of the mapping, there is no simple scheme for ensuring the reversibility of the map. r 0 = a 0 XOR a 2 XOR A 7 r 2 = a XOR A r 6 = a 6 XOR a 7 r 7 = a 7 Disclosure of Invention It is an object of the present invention to provide a configurable transformation means for memory unit address mapping, for example from logical into topological address space, with the advantages of reducing the required memory space and the time required for transformation, and also enabling the reverse mapping to be obtained easily. Furthermore, it is an object of the present invention to simplify in various applications the definition of redundancy allocation constraints by applying a user configurable transformation. The substance of the present invention is a transformation means for transforming memory unit addresses between different memory device topologies, wherein the transformation means are capable of configurable mapping represented as affine transformation in P n space, where n denotes the total number of bits in an address, and P is the modulo 2 field. The proposed system also provides the reverse transformation procedure. The present invention relates further to a method of affine transformation of memory addresses. Another aspect of the present invention is a memory device testing and analysing system comprising a fault data storing and analysing means and a testing means provided with transformation means for address transformation between logical address space and physical (topological) address space, wherein the transformation means represents transformation as affine transformation in P n space, where n denotes the total number of bits in an address, and P is the modulo 2 field. The proposed system also provides the reverse transformation procedure. The present invention relates further to a method of operation of the proposed system. Still another aspect of the present invention is a memory redundancy allocation system comprising a fault data storing and analysing means and an allocation means, which further contains a transformation means for transforming cell addresses which represents or modifies constraints between memory regions that are physically separate on the actual memory device by applying an affine transformation to map regions sharing a mutual constraint or a mutual resource into adjacent regions in a mapping space for the purpose of redundancy allocation, that space is neither the logical nor topological space, wherein transformation means represents transformation as affine mapping in P n space, where n denotes the total number of bits in an address, and P is the modulo 2 field. The invention may be implemented in a hardware system for taking the information about a memory device received, e.g. from a testing system, expressed in terms of logical addresses of faults, and computing corresponding data expressed in terms, for example, of physical layout defects, for enabling repair means to repair the memory device. Furthermore, the corresponding data may be obtained in terms of redundancy allocation procedures for enabling an allocation means to create a repair solution. Alternatively, the present invention may be implemented in a software program for performing the proposed method of address transformation. The present invention provides also the reverse transformation, sometimes called descrambling, for example, of the transformed addresses expressed in terms of topological, i.e. physical layout defects and producing the corresponding data relating to logical address space for addressing a memory device under treatment. The proposed systems requires minimum memory space and time for storing and processing defect data and allows the use of a wide spectrum of mapping classes. For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made, by way of example, without loss of generality, to the accompanying drawings in which: Fig.l shows a block scheme of the memory device testing system using the transformation means in accordance with the first embodiment of the present invention. Fig.2 shows an example illustrating in detail the transformation procedure from logical into physical address space using the transformation means according to the first embodiment of the present invention. Fig.3 shows an example flow chart of the reverse transformation procedure. Fig.4 shows an example illustrating an alternative method of operation of the transformation means showing the transformation procedure from physical into another two- component address space, e.g., address space suitable for redundancy allocation. Fig.5 illustrates one of the preferred software implementation of the method of transformation according to the present invention. Fig.6 is a fragmentary circuit illustrating one of the hardware implementation of the transformation means according to the present invention. Fig.7 shows a block scheme of a memory redundancy allocation system using the transformation means in accordance with the present invention. Fig.8 illustrates the use of the affine transformation in conjunction with memory redundancy allocation. According to the first embodiment of the present invention, the affine transformation means is adapted to perform the transformation from logical into physical address space and the reverse transformation. As shown in Fig.l, a memory test system using the transformation means according to the present invention consists of a fault data storing and analysing means 1 for storing fault data, testing means 2 for testing a memory device 3 under treatment, provided with a transformation means 4 for transformation of fault addresses from logical into topological (physical) address space and for the reverse transformation. The system operates as follows. After generating fail addresses, testing means 2 subject them to transformation in the transformation means 4. The transformed (scrambled) address data expressed in terms of topological address space are then transferred to the storing and analysing means 1 for processing and storage. The use of the affine transformation means proposed in the present invention allows subjecting the address data in the topological address space, if necessary, to the reverse transformation to obtain logical addresses. According to the present invention, the transformation means resolves the problem of assigning each input address to the corresponding output address using the formula: 'joined i » ljoined U joined "*" >-joined/ wherein U j0 in ed is an input address vector, e.g. logical address vector combined of bits of row, column and DQ addresses (where DQ is a bidirectional data pins) ; N jo in ed is an output address vector, e.g. physical address vector combined of bits of row and column addresses; M is a mapping matrix represented as an array in P" space, and t is a translation vector in P n space, where n is the total number of bits in an address, e.g. the sum of the number of bits in a row and column address in the physical address space, or the sum of the number of bits in a row, column and DQ address in the logical address space. Mapping matrices and translation vectors may be easily obtained by a specialist ordinary skilled in the art from formulas supplied by the manufacturer. It shall be also mentioned that the term "vector", as used herein to define a processor's word, is customary in the special literature and should not be considered as limiting the proposed invention. The address transformation means may be implemented in hardware by either using two stores containing the transformation tables showed below, or a set of exclusive OR gates and inverters (the transformations have the property of being able to be expressed by a network of exclusive OR gates and inverters, each carrying out a unary operation, hence their position in the logic process is not important, but only the number of inversions and the number of exclusive ORs as well as which operands are used) . The logical network is apparent from the following transformation example. The transformation means can also be implemented in a software program created in any suitable computer language, e.g. C, C++, Assembler, etc. The first method of the operation of the transformation means in accordance with the present invention is shown in Fig.2. To perform the transformation, for example, from logical into physical address space, the transformation means (called also Scrambler) starts to operate upon receipt of the following information in bit form about a memory device: a) logical row addresses, LR; b) logical column addresses, LC; and c) the number of the plane in logical address, DQ. On the basis of this information, the transformation means combines bits of row, column and DQ addresses into one (joined) input bit vector Ujoine - The vector Uoined is multiplied by mapping matrix M and then a translation vector t is added to the result to obtain the output vector Vjoined - An example of such an operation will now be presented and explained in detail with reference to Fig . 2 . Suppose, the transformation formulas are as follows: PR0=!LR0 Λ LR12 PR13=LR12 PR1=!LR1 A LR12 PC0=DQ0 PR2=!LR2 Λ LR12 PC1=DQ1 PR3=!LR3 Λ LR12 PC2=LC0 Λ DQ2 A DQ3 PR4=!LR4 A LR12 PC3=LC1 Λ DQ2 Λ DQ3 PR5=!LR5 A LR12 PC4=LC2 A DQ2 Λ DQ3 PR6=!LR6 A LR12 PC5=LC3 A DQ2 A DQ3 PR7=!LR7 A LR12 PC6=LC4 A DQ2 A DQ3 PR8=!LR8 A LR12 PC7=LC5 A DQ2 A DQ3 PR9=!LR9 A LR12 PC8=LC6 Λ DQ2 A DQ3 PR10=!LR10 A LR12 PC9=LC7 Λ DQ2 A DQ3 PR11=!LR1 1 A LR12 PC10=!DQ2 A DQ3 PR12=!LR12 A DQ3 where PRn - n-th bit in physical (topological) row address; in this case, n = 0,1...13, i.e. the total number of bits in row address is 14; PCn - n-th bit in physical (topological) column address; in this case, n = 0, 1...10, i.e. the total number of bits in column address is 11; LRn - n-th bit in logical row address; in this case, n = 0, 1...12, i.e. the total number of bits in row address is 13; LCn - n-th bit in logical column address; in this case, n = 0, 1...7, i.e. the total number of bits in column address is 8; DQn - n-th bit in logical address representing the number of the plane in logical address, in this case, n = 0, 1...3, i.e. the total number of bits in DQ address is 4. On the basis of these formulas, the following matrix of size 25 x 25 bits and the translation vector are obtained: Translation Vector t: 1000000000001111111111111 Transformation Matrix M[25:0][25:0] : 000000 000000 0000 00000001 000000000000 000000000010 000000000000 000000000100 000000000000 000000001000 000000000000 000000010000 000000000000 000000100000 000000000000 000001000000 000000000000 000010000000 000000000000 000100000000 000000000000 001000000000 000000000000 010000000000 000000000000 „100000000000 100000000000 1000000000000 000000000000 1000000000000 000100000000 0000000000000 001000000000 0000000000000 110000000001 0000000000000 110000000010 0000000000000 10000000100 0000000000000 10000001000 0Q00000000000 10000010000 0000000000000 10000100000 0000000000000 10001000000 0000000000000 _10010000000 0000000000000 110000000000 0000000000000 Let the input logical address be: DQ : 2; Row : 0201 (Hex) ; Col : 001F . (Hex) . The corresponding input address vector Uoine combined of bits of row, column and DQ address is shown in Fig.2a. After performing the transformation as described in the flow chart shown in Fig.2b, the output address vector Vj 0ined is obtained, which decomposed m row and column components as follows : Row : lDFE(Hex); Col : 007E(Hex). The flow chart of the reverse transformation procedure is shown in Fig.3. In case of the reverse transformation from physical (topological) address space into logical address spaces, the transformation means first subtracts the translation vector t from the topological address vector - om ed . and multiplies the result by the reverse matrix M "α . The result is a bit vector U-, 0 _-ned of the logical address: M joined '"joined — t 3 oιned/ = Ujoine , where the reverse matrix M "1 -, 0m ed (descrambling matrix) is as follows: 0000000000010000000000001 0000000000010000000000010 0000000000010000000000100 0000000000010000000001000 0000000000010000000010000 0000000000010000000100000 0000000000010000001000000 0000000000010000010000000 0000000000010000100000000 0000000000010001000000000 0000000000010010000000000 0000000000010100000000000 0000000000010000000000000 1000000010000000000000000 1000000100000000000000000 1000001000000000000000000 1000010000000000000000000 1000100000000000000000000 1001000000000000000000000 1010000000000000000000000 1100000000000000000000000 0000000000100000000000000 0000000001000000000000000 1000000000011000000000000 0000000000011000000000000 Both the transformation matrix and the reverse matrix are affine matrices m P n space, where n - the total number of bits m an address, and P is the modulo 2 field. The result of the transformation means operation is that logical addresses may be transformed into topological addresses for use m the storing system or laser repair means and topological addresses may be transformed into logical addresses for use by testing means. Various modifications of the transformation procedure are possible within the scope of the present invention. One of the preferred embodiments of the method of performing the transformation will now be illustrated with reference to Fig. . The characteristic feature of the method is transposing the mapping matrix. The result of this step is that each vertical line will correspond now to a single machine word. The width of such word in conventional processors equals to 32 bit, however, the address vector size is not limited to this figure. Another important feature is combining bits of address components, e.g., row and column address bits, in such a way, that they are not joined, as in the previous example, but are aligned according to the admissible word width, so as to obtain, e.g. a 32 bit word, as shown in Fig.4a. In this case, non-significant bits may be added to address bits to obtain a corresponding input address vector and to accelerate the operation. For the same transformation formulas shown above, the transformation means now performs the following operation: n Vanned [n:0] = Uaϋgned XOR [n:0][n:0], k=0 and the whole transformation procedure may be carried out in following steps (see Fig.4b): a) begin Vaϋgned [n : 0 ] = t; b) if Uaiined [i]= 0, skip the next two steps; c) take a vertical line M[i] [n:0] from matrix Maijgne d (each line consisting of a single n-bit word) , d) make XOR operation upon the output word Vaϋgned counted in a previous step and the word taken from matrix M in step (b) . The main advantages of the preferred way of performing the transformation as disclosed above are that, first, it allows transforming addresses much faster than transformation procedures conventionally used; second, the method does not require checking for being non- contradictory, i.e. checking that the incoming address is not out of space (it simply ignores the extra set bits) ; third, it is much more simple due to decreasing the number of XOR operations used for transformation. To speed up the above-disclosed procedure even more, Look Up Tables (LUT) may be used to store partial results of the calculations. Thus, to simplify the procedure of performing the transformation for a 32-bit input address, the input word may be splitted into two 16-bit parts, with the two LUT created, respectively, each LUT comprising 16 addresses and 32 bits of data. Thus, the resulting procedure will contain the following operation: VOUTPUT[31:1]= LUT_High [UI N P UT [31:15]] XOR LUT_LowUι N puτ[15:0]] The LUT size may be varied depending of the particular application and the available memory resources. For example, for some applications it is possible to create two large none cacheable tables to perform just one XOR operation but have two memory accesses. For some other applications it may be preferable to employ four comparatively small tables each of a size 256 x 32 bits, i.e. smaller than the processor's internal cache size, the total size being 4 Kbytes. As shown in the example presented in Fig.5, the input address U a ii gn ed is splitted into four parts consisting of bytes 0, 1, 2 and 3, respectively. The matrix M is sliced accordingly into a respective Slices 0, 1, 2 and 3. For each byte of the input address vector, a corresponding partial vector Vs of the output vector V AL IGN E D is pre-calculated and stored in the cache memory. For some applications, even smaller LUT size may give better results. The proposed technical solution may be implemented both in hardware and software. The hardware implementation of the transformation means may be created, e.g. using available small memory cells in a Field Programmable Gates Array (FPGA) . The size of these memory cells is family dependent. For example, to realise the above transformation means according to the preferred embodiment as discussed above, Lucent ORCA2A memory devices can be used, each memory device consisting of 16 x 4 memory cells, as shown in Fig.6. In this case, the transformation means will require 8 x 8 = 6. PFU' s (Programmable Function Units) for storing data and 32 x 1 PFU' s for calculating the XOR operation for each bit of the output vector. The result will be even greater saving of the FPGA area and the greater acceleration of the system. Another important feature of the proposed technical solution is that the transformation means may be easily pipelined at the input of the means, then at the output of each memory cell, and finally at the output of the means. The pipelining permits to have just one logic level between registers, thus maintaining the maximal frequency possible, i.e. more that 150 MHz, and therefore, increasing the accuracy and speed of processing. As the above described transformation procedure increases greatly the data flow transmitted through a SCSI bus (Small Computer System Interface, ANSI X3.131-1993, publ. 11 West 42 Street, NY, NY, 10036), to avoid the transfer rate limitations within the tester, first, the compressed data may be transferred through SCSI, and then, the transformation procedure may be carried out using the transformation means according to any of the embodiments of the present invention. A software program for performing the above described method of transformation or carrying out- functions of the above discussed transformation means can be also created in any suitable computer language, e.g. C, -C++, any kind of Assembler or another language, in a manner evident for a person skilled in the art. Another system using the affine transformation means according to the second embodiment of the present invention is illustrated in Fig.7. The memory redundancy allocation system shown in Fig.7 consists of a fault data storing and analysing means 1, an allocation means 2 for creating a repair solution for a memory device, a laser repair means 3, and a transformation means 4. During transmission from the storing system 1 to the allocation means 2 the address data are transformed (scrambled) in the transformation means 4 from logical space into the address space appropriate for redundancy allocation procedures. When the resulting addresses are transmitted to the laser repair means 3, the scrambled addresses are descrambled using the transformation means 4 into topological addresses. Fig.8 illustrates an example of how the transformation means may be used in conjunction with a memory redundancy allocation system in accordance with the second embodiment of the present invention. The object of the transformation means in this case is transforming cell addresses for representing or modifying constraints between memory tiles that are physically separate on the actual memory device. The use of the affine transformation allows the rapid mapping of physically separate regions sharing constraints into adjacent regions that fit the industry standard Domain and Region model for redundancy allocation (further RA) , while retaining the ability to convert the result back into the physical domain in order to output the redundancy allocation results. By use of an affine transformation means, it is possible to reduce considerably the complexity of the constraint set for redundancy allocation in advanced memory devices. For example, in Fig.8 a memory segment S consisting of a four tiles a,b,c,d (where tiles b and c are physically separate memory arrays) may be transformed into a segment S 1 in which tiles b and c share mutual spare resources by applying the following affine transformation. Let the first picture (segment S) represent the physical layout (bits PRO,....PR5, PCO...PC5) and the second picture represent the RA layout (bits RRO,....RR5, RCO...RC5) . The formulas would be: RRO = PRO RCO = PC0 !PC5 RR1 = PR1 RC1 = PC1 A !PC5 RR2 = PR2 RC2 = PC2 !PC5 RR3 = PR3 RC3 = PC3 A 'PC5 RR4 = PR4 RC4 = PC4 A !PC5 RR5 = PR5 A PC5 RC5 = PC5 The transformed segment S 1 may be subjected then to redundancy allocation in accordance with any suitable known procedures. The transformation is implemented by conversion of the defined constraints into an affine mapping represented by use of a vector or a succinct table. It will be appreciated that the above is example embodiments only and that various modifications may be made to the embodiments described above within the scope of the present invention.

Claims: Claims 1. A transformation means for transforming addresses between different memory device topologies, wherein the transformation means are capable of a configurable mapping represented as an affine transformation in P n space, where n denotes the total number of bits in an address, and P is the modulo 2 field. 2. A system according to claim 1, characterised in that the transformation means are adapted to perform the transformation from logical address space into physical address space and the reverse transformation. 3. A system according to claim 1, characterised in that the transformation means are adapted to perform the transformation from logical or physical address space into address space appropriate for redundancy allocation and the reverse transformation. 4. A system according to claims 1-3, characterised in that the transformation means stores the transformation map as an n x n matrix of bits and an n x 1 translation vector, where n denotes the total number of bits in an address. 5. A method for storing and transforming address data comprising the transformation of addresses between different memory device topologies, wherein the transformation is a configurable mapping represented as an affine transformation in P n space, where n denotes the total number of bits in an address, and P is the modulo 2 field. 6. A method according to claim 5, characterized in that the transformation is performed by representing the input address in the form of a vector combined of bits of address components. 7. A method according to claims 5-6, characterized in that the reverse transformation is performed by using the reverse matrix. 8. A method according to claims 5-6, characterized in that the transformation is performed by using the transposed matrix. 9. A method according to claim 8, characterized in that look-up tables containing pre-calculated values for an output address vector are used to perform the transformation. 10. A method according to claims 5-9, characterised in that the transformation map is stored in the transformation means as an n x n matrix of bits and an n x 1 translation vector, where n denotes the total number of significant bits in an address. 11. A memory device testing and analysing system comprising a fault data storing and analysing means and a testing means provided with a transformation means for transforming addresses between logical address space and topological address space, wherein the transformation means represents the transformation as an affine transformation in P n space, where n denotes the total number of bits in an address, and P is the modulo 2 field. 12. A system according to claim 11, characterised in that the transformation means stores the transformation map as a n x n matrix of bits and a n x 1 translation vector, where n denotes the total number of bits in an address. 13. A system according to claim 10, characterised in that the reverse transformation is carried out by using the reverse matrix. 14. A method of testing and analysing a memory device including a step of testing a memory device using a cell address transformation and a step of storing and analysing the fault data, wherein the cell address transformation is represented as an affine transformation in P n space, where n denotes the total number of bits in an address, and P is the modulo 2 field. 15. A method according to claim 14, characterised in that the transformation map is stored in the transformation means as an n x n matrix of bits and an n x 1 translation vector of bits, where n denotes the total number of bits in an address. 16. A method according to claim 15, characterised in that the reverse transformation is carried out by using the reverse matrix. 17. A memory redundancy allocation system comprising a fault data storing and analysing means and an allocation means, wherein the system further contains transformation means for transforming cell addresses which represents or modifies constraints between memory regions that are physically separate on the actual memory device by applying an affine transformation in P n space, where n denotes the total number of bits in an address, and P is the modulo 2 field, to map regions sharing a mutual constraint or a mutual resource into adjacent regions in a mapping space for the purpose of redundancy allocation, that is neither the logical nor topological space. 18. A system according to claim 17, characterised in that the transformation means stores the transformation map as an n x n matrix of bits and an n x 1 translation vector, where n denotes the total number of bits in an address. 19. A system according to claims 17-18, characterised in that the reverse transformation is carried out by using the reverse matrix. 20. A method of memory redundancy allocation including a step of storing and analysing fault data and a step of redundancy allocation, wherein the method further includes a step of transforming cell addresses for representing or modifying constraints between memory regions that are physically separate on the actual memory device by applying an affine transformation in P n space, where n denotes the total number of bits in an address, and P is the modulo 2 field, to the map regions sharing a mutual constraint or a mutual resource into adjacent regions in a mapping space for the purpose of redundancy allocation, that is neither the logical nor topological space. 21. A method according to claim 20, characterised in that the transformation map is stored in the transformation means as an n x n matrix of bits and an n x 1 translation vector of bits, where n denotes the total number of bits in an address. 22. A computer program for implementing or emulating or simulating the hardware functions of a system or of a method as claimed in any one of claims 1-21 when stored in electrically readable media.

Inventors: ABROSSIMOV IGOR ANATOLIEVICH, DEAS ALEXANDER ROGER, PLISS OLEG ANATOLIEVICH, VILKOV BORIS NIKOLAYEVICH, ABROSSIMOV, IGOR ANATOLIEVICH, DEAS, ALEXANDER ROGER, PLISS, OLEG ANATOLIEVICH, VILKOV, BORIS NIKOLAYEVICH
Applicants: VILKOV BORIS NIKOLAYEVICH, VILKOV, BORIS NIKOLAYEVICH
Application year: 1998
Main classification: H04N
IPC codes: G11C29