Circuit and method for reading a non-volatile memory

Abstract: A method for reading a non-volatile memory, comprising the steps of: providing a first random memory reading cycle; performing, at the end of the random reading cycle, a collective page precharge; subsequently performing a reading cycle of the page or random type, depending on whether the subsequent reading must be performed within the same page or not; and if a page reading cycle is performed, executing, when the data item is captured, a page precharge step in preparation both for page reading and for random reading.

Description: The present invention relates to a circuit and a method for reading a non-volatile memory. More particularly, the invention relates to a particular architecture of the reader circuit of a non-volatile memory and to a particular associated reader protocol. It is known that in a conventional non-volatile memory the reading method normally used is so-called random reading, in which word lines and bit lines are selected randomly and independently. This procedure entails reading times which are the sum of a sequence of events which can be summarized substantially as: propagation of the word line and bit line selection paths; precharge activity; data evaluation interval; propagation for data transfer to the output buffer and transition time of said buffer. The total reading time, given by the sum of the times of the individual operations listed above, depends not only on the dimensions and architecture of said memory but also on the kind of device that is present in the memory, i.e., on the technology that is used. The advantages of a conventional architecture lie in the fact that it is simple (a minimal number of memory structures), allows easy timing (because all reading cycles are equal), provides maximum efficiency for redundancy structures, and has significantly low consumption since the number of current-absorbing circuits is kept to the lowest possible value. However, the limitations of the conventional architecture reside indeed in the reading speed, which becomes very important in large memories. One possible approach for improving the reading speed is the use of so-called "page mode" reading, in which a plurality of words in parallel, for example eight, are read in a first cycle, storing the content of the reading operation in a suitable register and displaying externally the portion of register that relates to the selected word within the packet of read words. In this manner it is possible to scan the words contained in the packet of read words in a significantly shorter time than with random reading. However, the first reading cycle continues to be dependent on the time of a random selection. Page-mode reading is in any case affected by some drawbacks, such as: a large number of reader circuits. For example, if eight words of eight bits each are read in parallel, sixty-four sense amplifiers are required; high current absorption during parallel reading; the provision of word registers; the provision of register decoding; a reduction in the effectiveness of redundancy structures. One line at a time can be replaced with a redundant line, but in the case of multiple reading the possibilities of line fault increase yet there is still only one redundant line available; the reading protocol entails a double cycle time: random or page. The aim of the present invention is therefore to provide a circuit and a method for reading a non-volatile memory which allow to achieve performance advantages with respect to the conventional reading solution yet are simplified with respect to the page-mode solution. Within the scope of this aim, an object of the present invention is to provide a circuit and a method for reading a non-volatile memory which allow to keep the number of structures of the memory to a minimum. Another object of the present invention is to provide a circuit and a method for reading a non-volatile memory which allow to avoid reducing the effectiveness of redundancy. Another object of the present invention is to provide a circuit and a method for reading a non-volatile memory which do not require the implementation of additional reader and decoder registers. Another object of the present invention is to provide a circuit and a method for reading a non-volatile memory which allow to avoid introducing additional current consumption. Another object of the present invention is to provide a circuit and a method for reading a non-volatile memory which are highly reliable, relatively easy to provide and at competitive costs. This aim, these objects and others which will become apparent hereinafter are achieved by a method for reading a non-volatile memory, characterized in that it comprises the steps of: providing a first random memory reading cycle; performing, at the end of the random reading cycle, a collective page precharge; subsequently performing a reading cycle of the page or random type, depending on whether the subsequent reading must be performed within the same page or not; and if a page reading cycle is performed, executing, when the data item is captured, a page precharge step in preparation both for page reading and for random reading. Further characteristics and advantages of the invention will become apparent from the description of preferred but not exclusive embodiments of the circuit and of the method according to the invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein: Figure 1 is a schematic view of a first embodiment of an organizational structure of a non-volatile memory according to the present invention; Figure 2 is a schematic view of a second embodiment of an organizational structure of a non-volatile memory according to the present invention; Figure 3 is a chart of the reading timings of a non-volatile memory according to a known reading cycle, which points out the regularity of the timing events (reading cycles); Figure 4 is a chart of the read timings of a non-volatile memory according to a reading cycle provided with the circuit and the method according to the present invention; and Figure 5 is a chart of the reading timings of a non-volatile memory provided according to the invention and with continuous page changing after an initial random cycle. With reference to the above figures, the circuit for reading a non-volatile memory according to the invention receives a memory which is divided into a right half-matrix 1 and a left half-matrix 2 which are arranged on two opposite half-planes; each half-matrix has a plurality of memory cells arranged in rows and columns in addition to a plurality of redundancy memory cells. The memory cells are designated by the references ROW-MAT-R and ROW-MAT-L for the right half-matrix 2 and for the left half-matrix 1 respectively. Sense amplifiers 3 are arranged between the two half-matrices, comparison bit lines are arranged on different half-matrices, a reference word line is provided for each one of the two half-matrices, and each cell selected on the word line of one half-matrix is matched by the selection of a similar cell on the reference word line arranged on the opposite half-matrix. Column multiplexers are arranged symmetrically in each one of the two half-matrices. The two multiplexers are activated simultaneously so that each multiplexer selects, in its respective half-plane, two bit lines to be compared. Control buses YN-YM for the two multiplexers are provided to select a packet of bit lines (the bus YM) and a particular bit line within the packet (the bus YN). It is known that a reading cycle for a conventional non-volatile memory has the characteristic of restimulating, at each address transition, all the selection paths and of then continuing, as timing progresses, until external transfer of the data read from the memory is reached. This entails the fact that each reading cycle is provided over a long time period because said time period is a sum of all the events, as mentioned. The particularity of the invention is that it provides, following the model of page reading, a dual reading cycle: a random cycle; a page cycle. The expression "random cycle" is used to define every first reading cycle and every reading operation that does not act within a packet of memory locations which can be selected more quickly than locations belonging to different packets. The expression "page-type read cycle" is instead used to define any reading cycle that acts within a same packet of locations which can be selected more quickly than locations outside said packet. A random cycle is performed with the same method as in a conventional-read memory, but an immediate page precharge activity is superimposed thereon. Page precharge occurs after the data item has been captured. Each random cycle is therefore performed as follows. First of all, a specific word line and a specific bit line are activated at the beginning of a reading cycle. At this point there is reading timing progress for reading and capturing the data item, subsequently transferring and displaying the data read at the beginning of the memory. As soon as the read data has been captured, page precharge activity is initialized. A generic random access occurs only if a subsequent reading must be performed in memory locations other than those of the page, i.e., if the bit line to be selected is outside the packet of bit lines selected by page precharge. A page reading cycle is performed starting from a preceding random cycle (which, as mentioned, already performs page precharge), thus freezing the word line selection, subsequently selecting a page location and extracting the data item of the memory cell and transferring and thus displaying it externally. Finally, page precharge is initialized as soon as the read data item has been captured. A set of lines is precharged simultaneously in the time interval between the capture of the current data item and the beginning of a new read cycle. The selection operation occurs very quickly and isolates, among the selected bit lines, the one on which the cell to be read is to be identified. The selected bit line (whose precharge has already been performed in the previous reading cycle) remains under evaluation only for the time required for residual and optionally finer precharge, construction of the cell signal, and evaluation/capture of the cell data item. The above-described reading protocol allows to recover path selection time and precharge time, thus allowing to provide a faster page reading cycle, to freeze the number of necessary memory structures and to contain peak consumption, in addition to fully utilizing the effectiveness of the redundancy structures. During reading (programming), the control buses YN-YM of the two multiplexers have only one active line and can be in two conditions during page precharge; the bus YM is forced fully to logic level "1" by means of a forcing signal (PAGE) and the bus YN is set to univocal selection, indicating a page read mode; or both buses are in the univocal selection configuration but can, in the case of Figure 2, be bypassed by devices which are stimulated with the PAGE control signal, which is synchronous with the precharge signal. If passage from one bit line selection to the other occurs only by changing the configuration of the bus YM but not of the bus YN, after an initial reading activity, this means that the page is the same and can be advantageously read at the chosen location. If instead there is even just one change among the lines YN, then this means that a page change has occurred and that a random reading activity must therefore be performed. The architecture shown in Figure 1 shows the sense amplifiers 3 connected to structures of the tristate type 4, which are connected to a data bus designated by the reference sign DATA-bus. The architecture shown in Figure 2 differs from the architecture of Figure 1 in that the signal PAGE is sent directly to the gate terminals of transistors 5 which are connected to the decoding buses YM and YN. On the contrary, in the architecture of Figure 2, the page control signal PAGE is sent in input to a NOR gate 6 together with a column selection signal, i.e., a bit line selection signal (the word line WL always remains the same in the case of page reading, while the bit line BL changes every time); said signal is obtained by inputting column addresses to an AND gate 7. If the column address corresponds to the bit line group, i.e., to the packet of bit lines grouped under the PAGE control, then the control bus YM becomes entirely high and the simultaneous selection of bit lines is activated; the signal PAGE forces to 1 all the lines YM, regardless of the output of the logic gate 7; viceversa, if the signal PAGE is low, the AND gate is selected univocally and selects a single line. If even just one YN changes, then this means that the selected bit line does not belong to the packet of bit lines that are precharged together and it is therefore necessary to perform a random reading activity again and then attempt a subsequent page reading. With reference now to the timing charts of Figures 3, 4 and 5, Figure 3 plots the reading timing in the case of successive conventional random cycles, in which the random cycle is designated by the reference numeral 10 and the reference signs arranged laterally to the chart are to be interpreted as follows. In Figure 4, the reference ADD designates the address transition, i.e., the address change; the reference ATD designates address transition detection; the reference WL designates the word line; the reference YM designates the control bus described earlier, which is suitable to select a bit line packet; the reference BL designates the bit line; the reference PC designates the bit line precharge step; the reference EQ designates the equalization step; the reference LOAD designates the step for loading the data into the output buffers; the reference PAGE designates the signal for activating the page reading mode; the reference OUT designates the output of the read data from the memory. In Figure 2 the reference numeral 11 designates the bit line selection time at each random reading cycle. Figure 4 instead plots the reading cycle that uses a random reading mode followed by a page reading mode. In this case, the random cycle is again designated by the reference numeral 10, while the page-mode reading cycle is designated by the reference numeral 12. These page-mode reading cycles 12 have a shorter duration than the random reading cycles 10. The random cycle is never affected by the stimulus of the signal PAGE in the initial step; it is affected only at the end. At the references YM indicating the control buses, the portions shown in dashed lines correspond to the behavior of the bus YM if a random reading cycle were used each time instead of a page cycle after an initial random cycle. As regards the behavior of the bit line BL, Figure 4 shows that after the initial random cycle 10, which however follows a preceding page cycle 12 (not shown in the figure for the sake of convenience), all the bit lines BL that are not selected are brought to zero, while only the bit line BL that must be selected remains high. Therefore, differently from the conventional random cycle, in which a single bit line is selected, in the case of page mode reading all the bit lines that belong to a same packet are precharged in advance and then only the bit line that must actually be selected is kept high, while the remaining bit lines are discharged. This behavior is pointed out by the chart showing the development of the bit lines BL in Figure 4. In this manner it is possible to have an additional selection time, designated by the reference numeral 13, which is saved with respect to the bit line selection that occurs in the conventional random cycle. Finally, Figure 5 illustrates the case of the present invention, in which a random cycle is followed by a page cycle but in which a page precharge is performed at the end of the random cycle in order to prepare the memory for the subsequent page-mode reading. Figure 5 shows that the page cycle is performed starting from a preceding random cycle which, as mentioned, already performs a page precharge at the end. In this case, the word lines WL are frozen, since the activity occurs within a same page, and a page location is selected. In this manner, page precharging occurs collectively and simultaneously on the same number of matrix and reference lines arranged in the two opposite half-planes, while the evaluation step is also conducted symmetrically and is of course limited to its line of the data item to be read. The above-described architecture, together with the reading protocol, allows to limit the page-mode reading time to the time required for in-page selection and evaluation/capture and transfer of the data item. In-page selection time is reduced by performing selection exclusively by means of the bus lines YM (which are notoriously less capacitive than the corresponding lines YN), eliminating any resistive extra load during execution and assigning appropriate dimensions to the drivers of said lines. The reading protocol according to the invention therefore entails a succession of random and page cycles, depending on whether the selected line belongs or not to a same packet of bit lines. In practice, it has been observed that the circuit and the method for reading a non-volatile memory according to the invention fully achieve the intended aim and objects, since they allow to increase the reading speed of a non-volatile memory by utilizing a hybrid random and page reading. The circuit and the method thus conceived are susceptible of numerous modifications and variations, all of which are within the scope of the inventive concept; all the details may also be replaced with other technically equivalent elements. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.

Claims: A method for reading a non-volatile memory, characterized in that it comprises the steps of: providing a first random memory reading cycle; performing, at the end of the random reading cycle, a page precharge; subsequently performing a reading cycle of the page or random type, depending on whether the subsequent reading must be performed within the same page or not; and if a page reading cycle is performed, executing, when the data item is captured, a page precharge step in preparation both for page reading and for random reading. The method according to claim 1, characterized in that said first random read cycle comprises the steps of: selecting, in response to an address transition, a word line and a bit line which define a memory cell whose content is to be read; precharging and equalizing said bit line; reading the data item contained in the memory cell and transferring said data item outside the memory for display; and precharging a plurality of bit lines that belong to a page in the interval between data extraction and the beginning of a new cycle. The method according to claim 1, characterized in that said page read cycle comprises the steps of: starting from said first random cycle or from a subsequent random cycle in which a page precharge operation has been performed at the end, freezing the selection of the word lines by keeping selected the word line selected earlier in the random cycle; selecting a memory cell within said page; extracting the data item to be read from said memory cell; transferring and displaying outside said memory the extracted data item; and precharging said page after the capture of said data item. The method according to claim 3, characterized in that said step of selecting a memory cell within said page comprises isolating the bit line to be read within said page at the word line that is currently selected. The method according to claim 4, characterized in that the selected bit line remains in the evaluation step for the time required for residual precharge, construction of the cell signal and evaluation/capture of the data item of the memory cell. The method according to claim 1, characterized in that said memory matrix is divided into two symmetric half-matrices which lie in two opposite half-planes, said page precharge step being provided simultaneously on a plurality of bit lines of one half-matrix and on a same plurality of corresponding bit lines on the other half-matrix. The method according to one or more of the preceding claims, characterized in that each one of said memory half-matrices comprises a pair of column multiplexers, each whereof is suitable to select a bit line within the corresponding half-plane. The method according to claim 1, characterized in that said column multiplexers comprise a pair of control buses, a first one of said control buses being suitable to select a page of said memory, a second one of said control buses being suitable to select a bit line within said memory page. The method according to claim 8, characterized in that during said page precharge step the page selection control bus is simultaneously forced to the high logic level by means of a page reading indication signal. The method according to claim 8, characterized in that during said precharging step a page reading indication signal is sent for the direct selection of said word lines. The method according to one or more of the preceding claims, characterized in that a random reading cycle is executed only if the memory cell to be read does not belong to said memory page. The method according to one or more of the preceding claims, characterized in that the number of bit lines that are simultaneously precharged corresponds to the word length. The method according to one or more of the preceding claims, characterized in that during the step for the evaluation of the data item for its extraction, only one bit line is selected, said line being chosen, in page reading mode, among the previously precharged lines. The method according to one or more of the preceding claims, characterized in that if the memory reading cycle is of the random type, the page reading indication signal is produced exclusively at the end of the reading activity. The method according to one or more of the preceding claims, characterized in that said page reading indication signal is active in the time interval that directly follows a memory reading activity until a new reading cycle begins. The method according to one or more of the preceding claims, characterized in that the page reading indication signal is sent in input to a NOR gate together with a bit line signal which is obtained by inputting column addresses in an AND gate.

Inventors: PASCUCCI LUIGI, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1998
Main classification: G11C7
IPC codes: G11C16, G11C7