Vertical insulated gate field-effect transistor, method of making the same and corresponding integrated circuit

Abstract: A semiconductor device, which is characterized in that a trench (12) is formed in a silicon substrate (11), an element isolation film (1) is formed on an inner surface of said trench (12), and a drain region (7), a channel region (8) and a source region (9) are arranged vertically in a region encircled by said element isolation film (1); and that a gate insulating film (2) is formed inside of these regions (7, 8 and 9) and a gate electrode (4) is formed on an inner side portion of said gate insulating film (2), while a drain electrode (5) or source electrode (13) is formed on an outer side portion of said gate insulating film (2).

Description: BACKGROUND OF THE INVENTION This invention relates to semiconductor device, and in particular, to a vertical MOS semiconductor device where the source, channel and drain thereof are perpendicularly arranged on a semiconductor substrate. This invention also relates to a method of manufacturing such a vertical MOS semiconductor device. As a semiconductor device for realizing an increased integration and an increased high speed performance, a MOS semiconductor device which is formed on an SOI (Semiconductor On Insulator) has been known. FIG. 6 shows a MOS semiconductor device of lateral structure wherein an element substrate (P-type Si) 22 is superimposed via an SiO 2 insulating layer 21 on a supporting substrate 20 of P-type Si. A source 23, a channel 24 and a drain 25 are respectively formed in this element substrate 22, and a gate electrode 27 is formed over the channel 24 with a gate insulating layer 26 being interposed therebetween. FIG. 7 shows a semiconductor device of vertical structure which is disclosed in JP-A-5-41521 and wherein superimposed on a supporting substrate 28 is an element substrate 29 in which a drain 30, a channel 31 and a source 32 are arranged vertically, i.e. in a direction perpendicular to the element substrate 29. A gate electrode 34 is arranged beside these regions 30, 31 and 32 with a gate insulating layer 33 being interposed therebetween. The gate electrode 34, the drain 30, the channel 31 and the source 32 are electrically isolated by an insulating layer 35 formed around them. In this FIG. 7, reference numeral 36 denotes a source wiring, while 37 denotes a gate wiring and 38 denotes a drain wiring. The SOI structure shown in FIG. 6 is advantageous in the respect of achieving an increased high-speed of performance, since the electric field in the inversion layer is weakened in the direction perpendicular to the surface of substrate, thereby making it possible to enhance the mobility of carriers. However, since the source 23, channel 24 and drain 25 are arranged laterally in this MOS structure, it is accompanied with a problem that the integration degree of elements would be limited. In the case of the conventional semiconductor device of vertical structure shown in FIG. 7, there are also problems that, since the element substrate 29 is designed to be superimposed on the supporting substrate 28, the manufacturing process thereof becomes complicated thus increasing the manufacturing cost, and at the same time, a parasitic bipolar transistor of P-N-P constituted by the element substrate (P) 29, the supporting substrate (P) 28 and the drain wiring (N) 38 is caused to be formed, in addition to the essential MOS transistor constituted by the source (N) 32, the channel (P) 31 and the drain (N) 30, thus destabilizing the performance of the resultant semiconductor device. JP-A-01268172 discloses a semiconductor device in which a perpendicular arrangement of a lower source and upper drain with an epitaxial layer therebetween providing a channel, is disposed within a vertically arranged gate which shields the channel so as to stabilize the device's threshold voltage. The gate is electrically isolated by insulating layers from the source and from an adjacent source electrode, also vertically arranged in the device substrate. JP-A-03253079 also discloses a semiconductor device of vertical structure. Trenches are formed on opposite sides of a source channel and drain stack formed in the device substrate. One trench has an oxide lining and accommodates a gate disposed vertically between two insulating layers. The other trench accommodates polysilicon for interconnecting to the source, which is at the bottom of the stack. BRIEF SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a vertical semiconductor device, which makes it possible to enhance the integration degree, to simplify the manufacturing method thereof, and to obtain a stabilized performance. Another object of the present invention is to provide a method of manufacturing such a vertical semiconductor device. In the light of the above objects, the present invention provides in a first aspect a semiconductor device as set out in claim 1. In a second aspect the present invention provides in claim 2 a method of manufacturing the aforementioned semiconductor device of the first aspect. In the second aspect of the invention the fourth step may be performed as set out in dependent claim 3. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING FIG. 1 is a cross-sectional view schematically illustrating the structure of semiconductor device according to a first example; FIGS. 2A to 2J are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the first example; FIG. 3 is a cross-sectional view schematically illustrating the structure of semiconductor device according to a second example; FIGS. 4A and 4B show a plan view and a cross-sectional view taken along the line A-A of FIG. 4A, respectively illustrating the semiconductor device according to a third example; FIG. 5 is a plan view showing the structure of semiconductor device according to an embodiment; FIG. 6 is a cross-sectional view of a lateral semiconductor device of the prior art; and FIG. 7 is a cross-sectional view of a vertical semiconductor device of the prior art. The first to third examples are not embodiments of the claimed invention, but provide background to assist the understanding of the embodiment of FIG. 5, which is an embodiment of the claimed invention in its first aspect. The FIG. 2 manufacturing process provides background to assist the understanding of the claimed invention in its second aspect. DETAILED DESCRIPTION OF THE INVENTION This invention will be further explained in detail with reference to the following examples and embodiment. FIG. 1 shows a cross-sectional view of semiconductor device according to a first example. Referring to FIG. 1, a peripheral element isolation film 1 is vertically formed in a silicon substrate 11. A drain region 6, a channel region 7 and a source region 8 are successively formed one upon another in the mentioned order in a region encircled by the element isolation film 1. A drain electrode 5 and a gate electrode 4 are lead out from the level of the drain region 6 to the surface of the silicon substrate 11. An interlayer insulating film 3 is formed between the drain electrode 5 and the gate electrode 4. A source insulating film 9 is formed between the gate electrode 4 and the source region 8. A gate insulating film 2 is formed between the gate electrode 4 and the drain region 6 as well as between the gate electrode 4 and the channel region 7. Lead-out electrodes 401, 501 and 801 are formed on the gate electrode 4, drain electrode 5 and source region 8, respectively (FIG. 2J). A protective film 10 is formed covering all over the surface of the device. As a result, a vertical operation transistor having a vertical P-N-P structure is formed between the element isolation films 1. A process for manufacturing this semiconductor device of the first example will be explained with reference to FIGS. 2A to 2J. Referring to FIG. 2A, first of all, a square trench 12 is formed in the substrate 11 by means of anisotropic etching such as RIE. This trench 12 may be dimensioned such that 1 µm in width and 3 µm in depth for instance. In the step shown in FIG. 2B, an oxide film (SiO 2 film) is filled in the trench 12 thereby to form the element isolation film 1. In the step shown in FIG. 2C, a portion of the silicon substrate 11 which is encircled by the element isolation film 1 is etched by means of photolithographic technology, i.e. a plasma etcher to a depth of 1.6 µm. The region thus etched is then subjected to an ion-implantation using a P-type impurity such as boron thereby to form the drain region 6. In the step shown in FIG. 2D, a non-doped polysilicon is deposited all over the surface by means of a low pressure CVD method (LPCVD method), and then the resultant non-doped polysilicon layer is etched back so as to leave a non-doped polysilicon layer 0.6 µm in thickness only on the surface of the drain region 6. Then, an ion-implantation (an N-type impurity such as phosphorus) is selectively performed, by making use of patterning, on a region of the polysilicon layer excluding a region 5a (at least 0.5 µm in width) where the drain electrode 5 is to be formed, thereby forming the channel region 7 (60nm, = 600 angstroms). In the step shown in FIG. 2E, a non-doped polysilicon is deposited all over the surface by means of a low pressure CVD method, and then the resultant non-doped polysilicon layer is etched back so as to leave a non-doped polysilicon layer 1 µm in thickness only on the surface of the channel region 7. Then, an ion-implantation (a P-type impurity such as boron) is selectively performed, by making use of patterning, on a region of the polysilicon layer excluding a region 5b (at least 0.5 µm in width) where the drain electrode 5 is to be formed, thereby forming the source region 8. In the step shown in FIG. 2F, a patterned region formed on the source layer 8 and overlapping slightly with the regions 5a and 5b where the drain electrode 5 is to be formed is selectively etched to a depth (1.9 µm) reaching the drain region 6 by making use of an anisotropic etching such as RIE, thereby forming a trench 14 having a width of 0.47 µm. In the step shown in FIG. 2G, a gate oxide film 2 (SiO 2 film: 10nm,=100 angstroms) is formed on the inner wall of the trench 14 which has been formed in the step of FIG. 2F. Then, the space in the trench 14 is filled with polysilicon to be turned into a gate electrode by means of a low pressure CVD method, and this polysilicon is subjected to an N + doping, thereby forming the gate electrode 4. Simultaneously with this doping of gate electrode, the non-doped polysilicon of the drain regions 5a and 5b is also subjected to an N + doping, thereby forming the drain electrode 5. In the step shown in FIG. 2H, by making use of an anisotropic etching such as RIE, a trench having a depth of 1.9 µm and a width of 0.2 µm is formed between the gate electrode 4 and the drain electrode 5, and another trench having a depth of 1 µm and a width of 0.2 µm is formed between the gate electrode 4 and the source electrode 8. Subsequently, an oxide film (a thermal oxide film or an oxide film by means of CVD) is formed on the inner walls of these trenches, thereby forming the interlayer insulating film 3 and the source insulating film 9. In the step shown in FIG. 2I, an Al-Si is deposited all over the upper surface of the device by means of sputtering and then patterned thereby to form lead-out electrodes 401, 501 and 801 connected with the gate electrode 4, drain electrode 5 and source region 8, respectively. In the step shown in FIG. 2J, a protective layer 10 is deposited all over the upper surface of the device, thus completing a MOS transistor having a vertical P-N-P structure as shown in FIG. 1. By the way, the specific dimensions described in the above example are only an example, and therefore, the second aspect of the present invention is not limited by these specific dimensions. The aforementioned drain region 6 and source region 8 may be reversed in arrangement as shown in FIG. 3 illustrating a second example. Namely, in the structure shown in FIG. 3, the drain region 6 and the source region 8 shown in FIG. 1 are exchanged with each other, so that the drain region 6 is disposed at an upper portion and the source region 8 is disposed at a lower portion, thus forming an N-P-N type transistor. By the way, the drain electrode 5 of the aforementioned first example is also substituted by a source electrode 13 in this second example. FIGS. 4A and 4B show a semiconductor device according to a third example. In this third example, the element isolation film 1 is elliptically formed, and each element is formed within this elliptical region encircled by the element isolation film 1. As shown in FIGS. 4A and 4B, an element isolation film 1a is disposed at the center, around which the gate electrode 4 is formed. The gate electrode 4 is surrounded by source insulating film 9 and then by the source region 8, around which the drain electrode 5 constituting an outermost region is formed with the interlayer insulating film 3 being interposed therebetween. Namely, the drain electrode 5 is disposed along the inner wall of the element isolation film 1. According to this third example, the thickness of the interlayer insulating film 3 can be made thinner, so that the resultant semiconductor chip can be further miniaturized and at the same time, an electrical interference between the drain and gate can be eliminated, thus making it possible to stabilize the performance of semiconductor device. It is also possible to reverse the arrangement of source region 8 and drain region 6 (i.e., the drain electrode is substituted by the source electrode) in this third example. It is also possible to reverse the arrangement of the drain electrode 5 and the gate electrode 4. Furthermore, the source electrode 13 (see FIG. 3) may be disposed at the center, and the gate electrode 4 and the drain electrode 5 are disposed to surround the source electrode 13. In other words, there is no limitation regarding the arrangement of these electrodes. Since the transistor is formed around the electrode disposed at the center in this third example, the central element isolation film 1a can be omitted. FIG. 5 shows a semiconductor device according to an embodiment, in accordance with the present invention. The semiconductor device according to the embodiment is similar to that shown in FIGS. 4A and 4B except that element isolation films 15, each radially extending from the electrode disposed at the center (the gate electrode 4 in this illustrated embodiment) to the inner wall of the peripheral element isolation film 1, are formed so as to partition the semiconductor device into a plurality of transistors 16 each partitioned by the element isolation films 15. According to this embodiment, it is possible to form a plurality of transistors in a single semiconductor device of vertical structure. At the same time, a plurality of transistors can be driven simultaneously with a single central gate electrode 4 (or drain electrode or source electrode). In the third example and the embodiment, the semiconductor devices are exemplified as having an elliptical structure in plan view. However, the present invention is not limited to the elliptical structure, but the shape of the device may be optionally selected, e.g. it may be circular or polygonal. As explained above, it is possible according to the semiconductor device to realize a vertical transistor where a drain region, a channel region and a source region are vertically arranged in high integration degree on a semiconductor substrate . Furthermore, since all of the elements can be arranged on a single SOI substrate, the generation of parasitic bipolar can be prevented, thus making it possible to stabilize the performance of the device. According to the method of manufacturing a semiconductor device mentioned above, a trench is formed in a semiconductor substrate at first, and then an element isolation film is formed on the inner wall of the trench, after which a drain region, a channel region and a source region are formed in a region encircled by the element isolation film by making use of a process comprising the steps of depositing a non-doped polysilicon and implanting an impurity. Therefore, the conventional step of superimposing an element substrate on a supporting substrate can be dispensed with, thus making it possible to obtain a semiconductor device which is high in integration density and stable in performance by a simple process.

Claims: A semiconductor device comprising a semiconductor substrate (11); a drain region (6), a channel region (7) and a source region (8) arranged one above another as a vertical stack in a device region within said substrate, with the channel region between the source and drain regions, and one of said source and drain regions lowermost; a drain or source electrode (5; 13) and a gate electrode (4) extending, respectively, from the depths within said device region of said lowermost region and said channel region toward the surface of the substrate, said gate electrode being electrically isolated by a gate insulating film (2) from said channel region and said drain or source electrode being electrically connected to said lowermost region and electrically isolated by an interlayer insulating film (3) from said channel and upper most regions and from said gate electrode, wherein said device region is encircled by a first element isolation film (1) extending vertically in the semiconductor substrate, and wherein one of said drain or source and gate electrodes (5; 13, 4) is provided adjacent a centre of the device and is surrounded by the other said electrode and by said channel and upper most regions; and the device further comprises further element isolation films (15), each radially extending from said centre of the device to said first element isolation film so as to form a plurality of transistors partitioned from each other by said further element isolation films (15). A method of manufacturing a semiconductor device according to claim 1, comprising: a first step wherein a trench (12) is formed in a silicon substrate (11) so as to encircle a device region of said substrate, and then an element isolation film (1) is formed on an inner surface of said trench; a second step wherein a drain region (6), a channel region (7) and a source region (8) are formed so to be arranged vertically in the device region encircled by said trench; a third step wherein a further trench (14) is formed vertically penetrating into the drain region, channel region and source region, and then a gate insulating film (2) is formed on an inner surface of said further trench; a fourth step wherein a gate electrode (4) is formed adjacent an inner side portion of said gate insulating film within said further trench, while one of a drain and source electrode (5) is formed adjacent an outer side portion of said gate insulating film outside said further trench; and a fifth step wherein an interlayer insulating film (3) is formed between said gate electrode (4) and said one of a drain and a source electrode (5), wherein said second step comprises the steps of: formingone of a drain and a source region by etching said region encircled by the element isolation film (1) at first and then by implanting an impurity in the etched region; forming a channel region (7) by depositing a first non-doped polysilicon on said one of a drain and a source region at first and then by implanting an impurity in a first region of said first non-doped polysilicon; and forming the other of a source and a drain region by depositing a second non-doped polysilicon on said channel region at first and then by implanting an impurity in a first region of said second non-doped polysilicon located above said first region of the first non-doped polysilicon, and wherein in the fourth step said one of a drain and source electrode is formed by doping an impurity in second regions of the first and second non-doped polysilicons arranged one above another and excluding said respective first regions thereof. A method according to claim 2, wherein said fourth step is performed by the steps of: depositing a gate polysilicon on the inner side portion of said gate insulating film; and performing a doping of said gate polysilicon and, simultaneously, of said second regions of the first and second non-doped polysilicons, thereby simultaneously forming said gate electrode and said one of a drain and source electrode (5).

Inventors: DEGAWA TOSHIHIKO, DEGAWA, TOSHIHIKO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1998
Main classification: H01L29
IPC codes: H01L29, H01L27, H01L21