GROUP DELAY EQUALIZER

Abstract: Group delay equalizer (6) including at least two transmission lines (5, 5') on which the signal to be equalized in digital form and the same signal, 90 DEG phase shifted, are respectively transmitted, in which one or more real filtering cells (F1, F1', F2, F2', F3 and F3') having transfer function, with at least two poles and two real or complex conjugate zeros, are connected to each transmission line (5, 5'), and both the transmission lines (5, 5') are connected to at least one complex filtering cell (CF) having transfer function with at least one imaginary pole and zero, all said real filtering cells (F1, F1', F2, F2', F3, F3') and said complex filtering cell (CF) connected among them forming a filter having infinite impulse response.

Description: "GROUP DELAY EQUALIZER" Field of the Invention The present invention relates to a group delay equalizer, and in particular to a digital equalizer that can be used to compensate the group delay introduced by radiofrequency filters employed in high capacity radio links. It is known that radiofrequency channel filters, known also under the name of branching filters, introduce a group delay distortion in digital radio links, degrading the signal transmitted. This degradation is particularly significant in high capacity radio links, where a high spectral effectiveness is required, that is a high ratio between the frequency of bits transmitted and the band occupied by the signal. However, just digital modulation systems are particularly sensitive to the group delay distortion, so they must be fit with an equalizer to compensate this distortion. Background art Group delay analogue equalizers are known, operating both at radiofrequency, through the so-called self-equalized filters, and at intermediate frequency, through lumped parameter cells. However, these known equalizers show all the typical disadvantages of analogue circuits, that is high cost, complex manufacturing, as well as difficult calibration and suitability as the operational conditions change. To overcome these drawbacks, group delay equalizers have been implemented according to the digital technology. A first type of these digital equalizers includes a plurality of filters with finite impulse response, known as FIR (Finite Impulse Response), which are used to compensate in base band the group delay just before the modulation of the signal in radiofrequency. This kind of digital equalizer has the advantage to be comparatively simple, since the filters receive at input a word of a few bits. However, the signal at the power amplifier input is affected by a group delay distortion, caused by said previous compensation, which significantly worsens the ratio between the peak power and the average power of the signal. The amplifier shall therefore operate at a lower mean power, so that also the system gain of the radio link is necessarily worsened. An additional disadvantage of this type of digital equalizer is represented by the fact that it can compensate only group delay distortions on symmetric signals in the frequency range. To overcome these last drawbacks it was conceived a second type of digital equalizer including a FLR used to compensate the group delay in the receipt phase of the radiofrequency signal. This equalizer, implemented through a long series of filtering cells arranged in cascade, is considerably more complex of the previous one and takes a comparatively long time to perform the whole equalization, so it can cause transit delays, detrimental to the whole receiver in which the same in inserted. Object of the Invention Object of the present invention is that to obtain an equalizer not showing the drawbacks mentioned above, that is an equalizer having a comparatively simple structure, compensating the group delay in an acceptable time. Summary of the Invention Said object is attained through an equalizer whose main characteristics are specified in the first claim. Through the particular circuit structure of the equalizer according to the present invention, a complex filter is implemented having an infinite impulse response, which can be easily suited to the required utilization, showing a minimum quantization noise and above all capable to operate at high frequencies, in particular at the frequency of high capacity radio links. A further advantage of the equalizer according to the present invention is offered by the particular internal structure of biquadratic filters. The structure of said filters is similar to the structure known in the technique under the name of " direct form II", from which it differs due to the fact to include three delay cells, instead of two. The addition of the third delay cell, though delaying the direct output of the filter, enables to reduce the quantity of calculations to be made in a single clock period of the processor forming the filter itself, with resultant advantages in the reliability and accuracy of the equalizer. With this type of structure it is also possible to implement a filter not necessarily of the all-pass type, but able to possibly modify also the response in amplitude of the signal to be equalized. An additional advantage of the equalizer according to the present invention is offered by the particular implementation of fixed-point numeric signals. To avoid possible rounds- off that delay the processing, the present equalizer employs adding cells transforming the numbers at input by adding a logic one to the same on the right of the less significant bit. Although this measure requires that numbers are represented with an additional bit, its implementation in an electronic circuit involves a negligible increase in complexity, considering that said additional bit is a fixed one. However, numbers represented with this system have the advantage to be symmetrical versus the zero, since they have an equal number of positive and negative levels. The sign inversion operation is therefore simplified, for which it is sufficient to invert all the bits and maintain the one in the less significant position, also avoiding all the overflow risks deriving from the fact that in the representation in complement to two, there is no positive number corresponding to the negative number having the maximum module. This system of numeric representation retains the advantages of rounding off, but makes the implementation of a quick electronic circuit easier. An additional advantage of the equalizer according to the present invention is given by the fact that no saturation is made inside it, but immediately before the output. This is enabled by the fact that two additional dynamic bits are used during the signal processing with simultaneous limitation of the input signal level according to the coefficients of the transfer function of the equalizer itself. The features of the present invention which are believed to be novel are set forth in the appended claims. Brief description of the drawings The invention, together with further objects and advantages thereof, may be understood with reference to the following description, taken in conjunction with the accompanying drawings, in which: - figure 1 is a block diagram of a receiver including an equalizer according to the present invention; - figure 2 is a block diagram of a biquadratic filtering cell of the equalizer of fig. 1; and - figure 3 is a block diagram of the complex filtering cell of the equalizer of fig. 1. Making reference to figure 1, we see that in a receiver of radiofrequency signals, for instance 11 GHz, a signal is picked up in the known way through an antenna 1. The signal is filtered by at least a channel analogue filter AF limiting the band of the signal received filtering all undesired frequencies, for instance the frequency bands adjacent to the desired band, but introducing in the signal itself a group delay distortion, however minimum. The filtered signal is converted by a local oscillator 01 at intermediate frequency, for instance 70 MHz. Said distorted signal (that is the signal picked up by antenna 1, following the effect of filter AF suffers a group delay distortion) is withdrawn by two multipliers 4 and 4' connected in parallel and demodulated in base band through oscillators 02 and 02'. The reference signal of oscillators 02 and 02' is 90° phase shifted, in order that also the signals in base band at the output of multipliers 4 and 4' are phase shifted by 90°. With this measure, two channels in quadrature are created in the known way, known also under the name of "I" channel and "Q" channel. The signals transmitted on these channels are converted to digital form by a pair of analogue-digital converters AD and AD' and sent to two transmission lines 5 and 5' belonging to the equalizer according to the present invention 6 (shown with a dotted line). On each one of the transmission lines 5 and 5' one or more filtering cells are adequately connected in series, having a transfer function with at least two poles and two real or complex conjugate zeros. In particular, in the present embodiment of the invention six biquadratic filtering cells Fl, Fl ', F2, F2', F3 and F3' are present, connected in series, three for each transmission line, whose operation shall be described more in detail hereafter. The output of the last filtering cells F3 and F3' placed on each transmission line 5 and 5' is connected at input to a complex filtering cell CF having a transfer function with an imaginary pole and a zero. Said complex filtering cell includes in the known way, two inputs and two outputs corresponding to the real part and to the imaginary part, respectively of the signal to be equalized. The two outputs of the complex filtering cell CF are preferably connected to two saturation cells SC and SC serving to adapt, in particular at 1.9 bit, the resolution of signals coming out from the equalizer through the lines 5 and 5' to the different devices (not shown in the figure) of the receiver. Making now reference to figure 2, we see that each one of the filtering cells Fl, Fl', F2, F2', F3 and F3' receives at input a digital signal from one of the two transmission lines 5 or 5', in particular at 12 bit. In the figure, the resolution of said signal through the different transmission lines is indicated with a notation in complement to two of the m.n type, where m indicates the number of figures on the left of the point and n the number of figures on the right of the point. The resolution is therefore equal to m + n bit, where the weight of the more significant bit is 2 m" ', while that of the less significant bit is 2 "n . By extension, m and n values can also be negative, to indicate intervals of integer numbers only or decimal numbers only. For instance, a number having a 4.3 bit resolution includes all integer multiples of 0,125 included between 7,875 and -8. The 3.9 bit number, that is 12 bits, received on the line at input is processed by a first adder cell SI which sums up said number to a logic one on the right of the less significant bit, in such a way that the number at output consists of 3.10 bits. This number is summed up by an adder 7 to another number transmitted through a retroactive line 8 to 5.15 bit. The output of this adder 7 is connected to a first cutting cell Tl truncating the sum which eliminates the less significant bits and the possible more significant bits in excess compared to the 3.9 bit resolution. The output of the cell Tl is connected in series to a second adding cell S2 transforming the 3.9 bit number at input into a 3.10 bit number at output adding a logic one on the right of the less significant bit, as it takes place in cell S 1. The cell S2 is connected in series to three delay cells Dl, D2 and D3, each of them delaying the signal at Ts/2 input, where Ts/2 is the sampling period of the converters AD and AD'. The output of the first delay cell Dl is connected, in addition to the second delay cell D2, also to two multipliers 9 and 10 multiplying the number coming out from the delay cell Dl by two numbers drawn for instance from a pair of registers Rl and Rl '. In particular, registers Rl and Rl' contain a 1.5 and 2.4 bits number, respectively. Also the output of the second delay cell D2 is connected, in addition to the third delay cell D3, to two multipliers 11 and 12 multiplying the number coming out from the delay cell D2 by two numbers drawn for instance from a pair of registers R2 and R2'. In particular, registers R2 and R2' contain a 2.4 and 1.5-bit number, respectively. The products coming out from multipliers 9 and 11 are summed up by an adder 13 and the result at output is summed by an additional adder 14 with the number coming out from the third delay cell D3. The 5.15 bit value coming out from the adder 14 is taken to the output of the filtering cell after truncation in a 3.9 bit number by an additional cutting cell T2. The products coming out from multipliers 10 and 12 are on the contrary added among them by an adder 15 and the result at output is transmitted through line 8 to the adder 7. The whole of the delay cells Dl, D2 and D3 connected among them and connected to two pairs of multipliers 9, 10, 1 1 and 12 through two lines, out of which a retroactive one, duly forms a biquadratic filter having a transfer function of the H(z)=(bo+b*z "1 +z " 2 )/(l+aιz "1 +a 2 z "2 ) type, where coefficients bo, and bi correspond to the numbers at input of multipliers 9 and 11, respectively, in particular contained in registers Rl and R2, while coefficients ai and a 2 correspond to the numbers at input of multipliers 10 and 12, respectively, in particular contained in registers Rl ' and R2', sign inverted. The poles of the biquadratic filter can be calculated in the known way through the formula pι. 2 = -a-/2 ± (a* 2 /4-a 2 ) '/2 , so that if a* 2 > 4a 2 two separate real poles are obtained, if aι 2 = 4a 2 two coinciding real poles are obtained, and if a* 2 < 4a 2 two complex conjugate poles are obtained. Likewise, the zeros of the biquadratic filter can be calculated in the known way through the formula zι. 2 = (-b- ± (bι 2 -4bo) " ') / 2bo, therefore if b* > 4bo two separate real poles are obtained, if bι 2 = 4b 0 two coinciding real poles are obtained, and if bι 2 < 4bo two complex conjugate poles are obtained. The stability condition for this type of filter is given by the following relations: |a*| < l+a 2 e |a 2 | < 1. Finally, if an all-pass type filter is desired, also the following conditions shall be satisfied: ai = bi e a 2 = b 0 . Making reference to figure 3, we see that the complex filtering cell CF includes two specular series of electronic devices placed along the transmission lines 5 and 5'. In particular, at input on said lines there is a pair of adding cells S3 and S3' transforming the 3.9 bit numbers into 3.10 bit numbers at output, adding a logic one on the right of the less significant bit, as it takes place in cells SI and S2 of the biquadratic filtering cells Fl, Fl\ F2, F2\ F3 and F3\ The pair of number coming out from cells S3 and S3' is summed by a pair of adders 16, 16' to another pair of numbers transmitted through two retroactive 4.15-bit lines 17, 17'. The outputs of said adders 16, 16' are connected to a pair of cutting cells T3, T3' which truncate the sums eliminating the less significant bits and the possible more significant bits in excess versus the 3.9 bit resolution. The outputs of cells T3, T3' are connected to a second pair of adding cells S4 and S4' transforming the 3.9 bit number at input into a 3.10 bit number at output adding a logic one on the right of the less significant bit, as it happens in cells S3, S3'. Each one of the cells S4 and S4' is connected in series to a pair of delay cells D4, D5 and D4', D5', respectively, each one delaying the signal at input of Ts/2, where Ts/2 is the sampling period of AD and AD' converters. The outputs of the first delay cells D4, D4' are connected, in addition to the second delay cells D5, D5', also to two multipliers 18, 18' multiplying the number coming out from the delay cell D4 or D4' connected to one of them, by a number drawn for instance from a pair of registers R3 and R3'. In particular, registers R3 and R3' contain a 1.5 bit number each. Products at output of multipliers 18 and 18' are added by a pair of adders 19, 19' with the numbers coming out from the second pair of delay cells D5, D5'. In particular, the product coming out from multiplier 18 is summed up by adder 19' with the number coming out from the delay cell D5', and vice versa, in order to cross the lines 5 and 5'. 4.15 bit values coming out from adders 19, 19' are taken to the output of the filtering cell CF after having been truncated in a 3.9 bit number by an additional pair of cutting cells T4, T4\ To complete the structure of the filtering cell CF, the outputs of multipliers 18 and 18' are connected to adders 16, 16' through the retroactive lines 17, 17'. Also in this case the lines 5, 5' are crossed, since multiplier 18 is connected to the adder 16' through the retroactive line 17', and vice versa. The whole of the two pairs of delay cells D4, D4', D5 and D5' connected in series two by two, in which the outputs of the first delay cells D4, D4' of each pair are connected to a pair of multipliers 18, 18' whose outputs are in their turn connected to two pairs of adders 16, 16', 19 and 19' placed upstream and downstream said delay cells D4, D4', D5 and D5', respectively, duly forms a complex filter CF having a transfer function of the H(z)=(-jd+z '1 )/(l+jcz "1 ) type, where the coefficient c corresponds to the number at input of the multiplier 18', in particular contained in register R3', while the coefficient d corresponds to the number at input of the multiplier 18, in particular contained in register R3, with inverted sign. The pole of the complex filter CF is equal to jd, while the zero is equal to j/c. The stability condition for this type of filter is given by the relation |d| < 1. If an all-pass type filter is requested, also the c = d condition shall be met. For the implementation of the equalizer according to the present invention a dedicate integrated circuit can be used, preferably including one or more electronic devices suitable to improve the operation and/or accuracy of the equalizer itself, such as for instance a digital detector for the automatic control of the gain and a reception filter FIR. In particular, the integrated circuit implemented by the applicant can be planned through an appropriate interface and in the present embodiment it includes about 70000 logic ports, it can operate at a maximum frequency 80 MHz and absorbs 1,7 W at the rated frequency of 50 MHz. Though one particular embodiment of the present invention has been shown and described, it should be understood that the present invention is not limited thereto since other embodiments may be made by those skilled in the art without departing from the scope thereof. It is thus contemplated that the present invention encompasses any and all such embodiments covered by the following claims.

Claims: CLAIMS 1. Group delay equalizer (6) including at least two transmission lines (5, 5') on which the components in phase and in quadrature of the signal to be equalized converted to digital form are respectively transmitted, characterized in that one or more real filtering cells (Fl, Fl ', F2, F2\ F3 and F3') having a transfer function with at least two poles and two real or complex conjugate zeros are connected in series to each transmission line (5, 5'), the whole of said real filtering cells (Fl, Fl ', F2, F2', F3, F3') connected among them forming a filter having infinite impulse response. 2. Equalizer according to the previous claim, characterized in that both the transmission lines (5, 5') are connected to at least a complex filtering cell (CF) having a transfer function with at least an imaginary pole and a zero, the whole of said real filtering cells (Fl, Fl ', F2, F2', F3, F3') and of said complex filtering cell (CF) connected among them forming a filter having infinite impulse response. 3. Equalizer according to the previous claim, characterized in that at least one of said real filtering cells (Fl, Fl ', F2, F2\ F3, F3') and/or said complex filtering cell (CF) is of the all-pass type. 4. Equalizer according to one of the previous claims, characterized in that three filtering biquadratic cells (Fl, FT, F2, F2', F3 and F3') are connected in series on each transmission line (5, 5'), in which the output of the biquadratic filtering cells (F3, F3') placed downstream each series is connected to one of the two inputs of said complex filtering cell (CF) having a transfer function with at least one imaginary pole and a zero. 5. Equalizer according to one of the previous claims, characterized in that each one of the two outputs of the complex filtering cell (CF) is connected to a cell (SC, SC) saturating the signal received by said filtering cell. 6. Equalizer according to one of the previous claims, characterized in that at least one of the real filtering cells (Fl, Fl', F2, F2', F3 and F3') having a transfer function with at least two poles and two real or complex conjugate zeros includes at least three delay cells (Dl, D2 and D3) connected in series, the outputs of the first (Dl) and of the second (D2) delay cell being connected to two pairs of multipliers (9, 10, 11 and 12), respectively, in which the outputs of the first multiplier (9, 11) of each pair are summed up to the output of the third delay cell (D3), while the outputs of the second multiplier (10, 12) of each pair are summed up to the input of the first delay cell (Dl). 7. Equalizer according to the previous claim, characterized in that the outputs of the first (Dl) and second (D2) delay cell are multiplied by the two pairs of multipliers (9, 10, 11 and 12) with the coefficients (a- . , a 2 , bo e b*), possibly sign inverted, of the transfer function of the real filtering cell (Fl, Fl ', F2, F2', F3 and F3') they belong to. 8. Equalizer according to one of the previous claims, characterized in that the complex filtering cell (CF) having a transfer function with at least an imaginary pole and a zero including at least two pairs of delay cells (D4, D5 and D4', D5') connected in series two by two, the outputs of the first delay cells (D4, D4') of each pair being connected to a multiplier (18, 18'), where the output of the first multiplier (18) is added to the output of the second delay cell (D5') of the second pair and at the input of the first delay cell (D4') of the second pair, while the output of the second multiplier (18') is added to the output of the second delay cell (D5) of the first pair and at the input of the first delay cell (D4) of the first pair. 9. Equalizer according to the previous claim, characterized in that the outputs of the first delay cells (D4, D4') of each pair are multiplied by multipliers (18, 18') connected to the same with coefficients (c, d), of which one sign inverted, of the transfer function of the complex filtering cell (CF) they belong to. 10. Equalizer according to one of the previous claims, characterized in that on at least one of the transmission lines (5, 5') a cutting cell at least is placed (Tl, T2, T3, T3', T4, T4') truncating the signal at input eliminating the less significant bits and the possible more significant bits in excess versus a predetermined resolution. 11. Equalizer according to the previous claim, characterized in that the output of said cutting cell (Tl, T3, T3') is connected to an adding cell (S2, S4, S4') adding to the number at input a logic one on the right of the less significant bit. 12. Equalizer according to the previous claim, characterized in that the output of said adding cell (S2, S4, S4') is connected to the input of the first one (Dl, D4, D4') of a series of delay cells (Dl, D2 and D3, D4 and D5, D4' and D5').

Inventors: BIANCHI SERGIO, SCHMIDMAIER RICHARD, BIANCHI, SERGIO, SCHMIDMAIER, RICHARD
Applicants: ITALTEL SPA, ITALTEL S.P.A.
Application year: 1998
Main classification: H04L25
IPC codes: H03H17, H04B7, H04L25, H04L27