STRUCTURE FOR INCREASING THE MAXIMUM VOLTAGE OF SILICON CARBIDE POWER TRANSISTORS

Abstract: A silicon carbide insulated gate power transistor is disclosed that demonstrates increased maximum voltage. The transistor comprises a field effect or insulated gate transistor with a protective region (23, 43) adjacent the insulated gate that has the opposite conductivity type from the source (14, 34) for protecting the gate insulator material (17, 37) from the degrading or breakdown effect of a large voltage applied across the device. The device optionally includes a current-enhancing layer (67, 83) having the opposite conductivity type from the protective region and positioned between the protective region and another first conductivity-type region of the transistor.

Description: STRUCTURE FOR INCREASING THE MAXIMUM VOLTAGE OF SILICON CARBIDE POWER TRANSISTORS Field of the Invention The present invention relates to insulated gate power semiconductor devices and in particular relates to UMOS and IGBT field effect transistors formed in silicon carbide. Background of the Invention The present invention relates to power semiconductor devices and particularly power MOSFETs (metal-oxide semiconductor field-effect transistors) formed in silicon carbide. A power MOSFET is a small, reliable, electronically controllable switching device that has growing application in high voltage/high power devices and integrated circuits. Power MOSFETs have a variety of applications in numerous fields including communications, consumer applications, data processing, military, industrial, automotive and related markets. In particular, power MOSFETs have inherently higher switching speeds than bipolar transistors and are accordingly particularly useful in high frequency applications. Although silicon has been the material of choice for many semiconductor applications, its fundamental electronic structure and characteristics prevent its utilization beyond certain parameters. Thus, interest for power MOSFET devices has turned from silicon to other materials, including silicon carbide. Silicon carbide has a number of intrinsic advantages for power MOSFET applications. Silicon carbide has a high field saturation velocity which is three times larger than that of gallium arsenide (GaAs). Silicon carbide has a high intrinsic breakdown field ten times higher than gallium arsenide and a thermal conductivity ten times as high as gallium arsenide. SiC is unique among compound semiconductors in that its native oxide is SiO, the same oxide as silicon. This means that the workhorse power devices used in silicon, i.e., the power MOSFET, insulated gate bipolar transistor (IGBT), and MOS-controlled thyristor (MCT) can all be fabricated in SiC. Because of technological differences, however, power devices in SiC can be very different from silicon devices, and a direct translation of silicon concepts to SiC is not always possible. SiC has a breakdown field eight times higher than silicon, and SiC power devices can have specific on resistances 100 to 200 times lower than similar devices in silicon. Nevertheless, several practical problems must be addressed before such devices can be realized. Bipolar devices in SiC (e.g., the IGBT and MCT) suffer from short minority carrier lifetimes, which are typically in the range of 40 to 400 nanoseconds (ns). As a result, the highest current gains yet reported in SiC bipolar transistors are in the range of 10 to 12. Because the peak electric field can be eight times (8X) higher than in silicon, SiC switching devices can be fabricated with a drift region about 8X thinner than comparable silicon devices. If the drift region is 8X thinner, the doping of the drift region can be about twelve times (12X) higher. The resistance of the drift region is proportional to the thickness and inversely proportional to the doping, so the specific on-resistance of a SiC device can be from 100-200 times smaller than a comparable silicon device of equal voltage rating. This means the SiC device can be 100-200 times smaller than the comparable silicon device. Alternatively, if the SiC device has the same area as the comparable silicon device, its specific on-resistance will be 100-200 times lower. Although it offers substantial advantages over silicon, SiC is still relatively immature as a semiconductor material. Single crystal wafers of SiC have only been commercially available since 1991, and a number of technical problems need to be addressed before SiC can supplant silicon in power device applications. The main problems are related to crystal growth of SiC materials. Because of the very high melting point, single crystal boules cannot be pulled from a melt as in the Czochralski method used for silicon. Instead, the boule is grown on a seed crystal by a high temperature sublimation process. At present, the boules grown by the sublimation process are about 2 inches in diameter, much smaller than the 6 to 8 inches common in the silicon industry. In addition, the material still has a relatively large number of defects. These defects include micropipes; i.e., micron size holes which run completely through the wafer. Fortunately, the micropipe problem appears to be under control, with micropipe densities as low as 27 cm "2 in the most recent wafers, and at the current rate of improvement micropipes should eventually be completely eliminated. SiC crystallizes in the hexagonal lattice with alternating planes of silicon and carbon atoms. The Si-C plane-pairs can occur in three orientations, labeled A, B, and C. The particular stacking sequence of Si-C plane-pairs identifies the polytype of the crystal. SiC occurs in a variety of polytypes, but the most common are 3C, 4H, and 6H. At the present time, the 6H polytype is the most thoroughly characterized, but the 4H polytype is more attractive for power devices because of its higher electron mobility. Although it has a much higher breakdown field than silicon, SiC has lower hole and electron mobilities and shorter minority carrier lifetimes. The shorter lifetimes allow bipolar devices in SiC to switch much faster than comparable silicon devices, but they limit the current gain of SiC bipolar transistors to very low values, typically less than 20. For high-speed switching with low forward voltage drop, the best SiC device will be a power MOSFET. The typical power MOSFET in silicon is a DMOS (or doubly diffused MOS) structure. The short channel length is achieved by diffusing the p-type base layer and the n+ source through the same oxide window, thus removing any dependence on alignment of photomasks. The p-type base must have a sufficient number of dopant atoms per unit area (thickness times concentration) to prevent punch-through by the drain electric field in the blocking state. Unfortunately, the DMOS concept is difficult to translate to SiC because it is not feasible to thermally diffuse dopant atoms in SiC. One might artificially construct a similar structure using ion implantation, but the channel length would then be defined by a mask alignment, and it would be difficult to implant the p-type impurity to sufficient depth to prevent punch-through. For these reasons, a vertical UMOSFET structure — i.e., a combination of SiC epitaxial layers and a trench is the most practical in SiC. The theoretical potential for SiC MOSFETs has not been reached, however, because the maximum voltage in silicon carbide MOSFETs is instead limited by the breakdown field of the silicon dioxide (SiO 2 ) insulator. Although this oxide does not actually fail until fields of about 10 7 Volts per centimeter (V/cm) are reached, from a practical standpoint the low-term reliability of the oxide degrades severely under fields above about 2-3 X 10 6 V/cm. Such a field limitation is already slightly lower than the breakdown field of silicon carbide. Even more problematic, however, because of the 2.5:1 ratio of the dielectric constants of silicon dioxide and silicon carbide, Gauss' law requires that the maximum field in the silicon carbide portion of a device be limited to around 1 X 10 6 V/cm. As a result, silicon carbide power transistors are in practical terms limited to a blocking voltage much lower than that of which silicon carbide is theoretically capable. Accordingly, the need exists for power transistors, particularly power MOSFETs, in silicon carbide that are capable of taking greater advantage of silicon carbide's favorable intrinsic properties, and it is an object of the invention to provide such transistors. Summary of the Invention The invention meets this object with a silicon carbide insulated gate power transistor that demonstrates increased maximum voltage. The transistor comprises an opposite conductivity-type region adjacent the insulated gate for protecting the gate insulator material from the degrading or breakdown effects of a large voltage applied across the device. In another aspect, the invention is a method of making a silicon carbide power transistor that demonstrates such increased maximum voltage. The method comprises etching a first-opposite-first conductivity-type silicon carbide structure to define a trench, and implanting an opposite layer at the bottom of the trench that is aligned by the trench walls. Adding the appropriate oxidation layer and ohmic contacts produces the improved transistor of the present invention. Brief Description of the Drawings The foregoing and other objects, features, and advantages of the present invention will be made apparent from the following detailed description of the preferred embodiment of the invention and from the drawings, in which: Figure 1 is a cross-sectional schematic diagram of a UMOS according to the prior art accompanied by informal plots of the field along the p-n and MOS sections of such prior art devices; Figure 2 is a similar schematic cross-sectional view of a UMOS according to the present invention and again accompanied by informal plots of the resulting field along the p-n and MOS sections of the device; Figure 3 is a user-defined grid of a conventional prior art UMOS using device simulation software; Figure 4 is a grid similar to Figure 3, but expanded in the vertical direction; Figures 5 and 6 are plots of the electric field strength at various positions within a conventional prior art UMOS based on the grids of Figures 3 and 4; Figures 7 and 8 are user-defined grids for the UMOS of the present invention based on a 4 micron and a 16 micron vertical cross-section, respectively; Figures 9 and 10 are plots of the electric field strength at various positions within the UMOS of the present invention as defined in Figures 7 and 8; Figures 11 and 12 plot the same type of information as Figures 9 and 10, but at a higher applied voltage; Figure 13 is a plot under the same conditions as Figures 11 and 12, but along a different portion of the device; Figures 14 and 15 are plots similar to Figures 9-12, but taken at a lower doping level than the devices modeled in the previous figures; Figures 16-18 are similar plots for the lower doping levels of Figures 14 and 15, but under much higher applied drain voltages; Figure 19 is an IGBT according to the present invention; Figure 20 is a cross-sectional view of another UMOS according to the present invention; and Figure 21 is a cross-sectional view of another IGBT according to the present invention. Detailed Description of the Preferred Embodiments In its broadest sense, the invention is an insulated gate transistor, field-effect or bipolar, in which the gate material is an oxide, and in which the opposite conductivity semiconductor is placed adjacent the oxide to protect the oxide from high electric fields. The preferred embodiment of the invention is a silicon carbide UMOS power transistor broadly designated at 10 in Figure 2. For comparison purposes, a prior art device is illustrated in Figure 1. In a presently preferred embodiment, the UMOS 10 is formed of an n-type single-crystal silicon carbide substrate 11 , an n-type silicon carbide epitaxial layer 12 on the n-type substrate 11 and a p-type epitaxial layer 13 on the n-type epitaxial layer 12. An n-type well 14 is formed in the p-type epitaxial layer 13. A gate trench defined by the trench wall 15 and a flat trench bottom 16 extends through the n-type well 14 and the p-type epitaxial layer 13 and terminates in the n-type epitaxial layer 12. A gate oxide 17 covers the wall 15 and bottom 16 of the trench. Respective ohmic contacts define the source, gate, and drain. In particular, the gate contact 20 is on the oxide layer 17, the source contact 21 is on the p-type epitaxial layer 13 and overlaps with the n-type well 14, and the drain contact 22 is made to the n-type substrate 11 so that the three contacts define the source, gate, and drain of the UMOS 10. There are a number of metals and composite metal systems that are appropriate for these contacts, and as these are generally well understood in the art, they will not be described in detail further herein other than to note that, for example, nickel or nickel-titanium combinations are appropriate ohmic contacts to n-type silicon carbide while aluminum or aluminum-titanium combinations are useful ohmic contacts to p-type silicon carbide. More recently cobalt suicide (CoSi 2 ) has shown promise as an ohmic contact material to p-type silicon carbide. As noted in the background portion, within the last decade, silicon carbide substrates, and substrates that include appropriate epitaxial layers, have become commercially available. Thus, their formation and growth will not be discussed in detail herein, other than to note that exemplary substrate and epitaxial growth techniques are set forth in U.S. Patents Nos. 4,912,063; 4,912,064; Re. 34,861; and 5,011,549. Similarly, the oxide layer 17 can be a deposited or a thermal oxide, and some advantageous methods of forming high-quality silicon dioxide layers on silicon carbide are set forth in U.S. Patent No. 5,459,107. Appropriate ohmic contact structures are set forth for example in U.S. Patents Nos. 5,323,022 and 5,409,859. As Figure 2 indicates, in the preferred embodiment the n-type substrate 11 is somewhat more heavily doped than the n-type epitaxial layer 12 with appropriate doping concentrations being for example 2 x 10 19 cm "3 for the substrate 11 and 2 X 10 16 cm "3 for the n- epitaxial layer 12. It will be understood that the use of an n- epilayer on an n+ substrate offers certain advantages for current flow in particular situations. In other embodiments, a single n-type layer or substrate provides an appropriate drain structure. Similarly, the n-type well 14 is more heavily doped, comparatively speaking, than either the p-type epitaxial layer 13 or the n-type epitaxial layer 12. An exemplary doping level for the n-type well 14 is also 2 X 10 19 cm "3 , and for the p-type layer 13 is 5 X 10 17 cm "3 . The invention further comprises a grounded p-type protective region 23 between the oxide layer 17 and the n-type epitaxial layer 12, and which, in the embodiment illustrated in Figure 2, is under the bottom portion of the trench oxide layer 17. The p-type protective region 23 is grounded by the ohmic contact shown schematically at 24 in Figure 2. This ohmic contact is typically formed on the horizontal surface 16 at a location not covered by the gate metal and gate oxide, for example, at a point on a plane behind the view of Figure 2. The p-type region 23 is aligned with the bottom 16 of the gate trench for protecting the oxide 17 in the trench from the degrading or breakdown effects of a large positive voltage applied to the drain contact 22. Stated independently of specific polarity, the opposite type protective region (23 in Figure 2) is adjacent the insulated gate (silicon dioxide 20 in Figure 2) and protects the gate insulator material 20 from the degrading or breakdown effects of a large voltage applied to the drain. The results of this structure are informally illustrated by comparing the field strength plots of Figure 1 with those of Figure 2, and are more formally illustrated by the information presented in Figures 3-18. In both Figure 1 and Figure 2, the field strength along the p-n section is basically the same. The effect of adding the p-layer 23 of the present invention, however, is illustrated by the difference between the field along the MOS section plotted in Figure 1 versus that plotted in Figure 2. As Figure 2 illustrates, the invention keeps the peak field strength away from the oxide so that a high voltage applied to the drain (as indicated by V d »0 in Figure 2), does not affect the oxide layer 17 in the UMOS 10 of Figure 2 in the same way that a similarly high drain voltage affects the oxide layer in the prior art example of Figure 1. By essentially protecting the oxide layer 17 from the field created by the high voltage, the p-type layer 23 permits the performance of the silicon carbide device of the present invention to more closely approach its theoretical potential. In order to obtain a more formal indication of the performance of the device, the design illustrated in Figure 2 was analyzed using the MEDICI™ device simulation program. MEDICI™, which is one of a number of commercially available device-simulation programs, was used to find the e-field value of each point inside the different SiC UMOS devices with the different biases. From this the maximum bias for each UMOS could be determined with the maximum e-field in the oxide layer lower than or equal to 3 X 10 6 V/cm. For analytical purposes, this was defined as the maximum bias voltage for the device. The MEDICI™ program is available from TMA, 595 Lawrence Expressway, Sunnydale, CA 94087 (URL: http://www.tmai.com). MEDICI™ predicts the electrical characteristics of arbitrary two-dimensional structures under user-specified operating conditions. The analysis of MOSFETs is one of the typical device applications for which the MEDICI™ simulation program is useful. The MEDICI™ results are illustrated in Figures 3-18. Figures 3-6 describe a conventional prior art UMOS, while Figures 7-18 describe a UMOS according to the present invention. Figure 3 is a user-defined grid for a conventional UMOS power device such as the one illustrated in Figure 1. Using the MEDICI™ program, the number and location of the grid points were selected to define the desired device in a two-dimensional pattern. Typically, and as Figure 3 illustrates, a larger number of grid points are selected and assigned to those portions of the device that will demonstrate the greatest effects or responses to voltage, current, and electric field. For example, in Figure 3, a large number of grid points are assigned to the oxide and appear as the dark L-shaped wide lines. As the listed dimensions indicate, Figure 3 illustrates a cross-sectional portion of a conventional UMOS that is approximately 4 microns wide and 2 microns high. Figure 4 is based upon the identical data as Figure 3 except that Figure 4 is expressed along a vertical distance of approximately 16 microns. Figure 5 demonstrates the behavior of a conventional SiC UMOS as modeled by the MEDICI™ program. The plot of Figure 5 is taken along the line y = 1.2033 microns; i.e., a horizontal line between the left- and right-hand borders of Figure 3. As Figure 3 illustrates, such a horizontal line passes through the oxide portion at the bottom of the UMOS trench. In particular, Figure 5 models the behavior of the conventional UMOS at a drain voltage of 150 volts. Under such conditions, the peak electric field is approximately 3.82 X 10 10 6 V/cm and occurs along the horizontal line at an x coordinate of about 3.08 microns. Again returning to Figure 3, this corresponds to the corner of the oxide, which is generally the expected position for the highest field strength. As noted above, such a high field strength can cause the oxide to either breakdown immediately, or to degrade so rapidly as to render the device generally useless under such conditions. As also noted earlier, in order to avoid oxide degradation, the peak electric field in the oxide should desirably be kept below about 2.5-3 x 10 6 V/cm, and preferably even lower. Figure 6 illustrates the same information as Figure 5, but does so by measuring the field along a vertical line defined by an x coordinate of 3.0967 microns, and again with an applied drain voltage of 150 volts. As Figure 6 demonstrates, the peak value of the electric field is again about 3.82 X 10 6 V/cm and occurs at the corner of the oxide; i.e., a coordinate defined by x = 3.1 microns and y = 1.25 microns. Figure 7 is the user-defined MEDICI™ grid for the UMOS of the present invention with the implanted p-layer (e.g., illustrated at 23 in Figure 2) having a depth of about 0.5 microns. In a manner similar to Figure 3, the largest number of points in the grid are selected within the oxide portion, which again appears as the large L-shaped solid lines in Figure 7. Figure 7 also includes, however, a large number of grid points corresponding to the implanted p-layer just below the oxide. As with Figure 3, the cross-sectional grid of Figure 7 covers approximately 4 microns vertically and 4 microns horizontally. Figure 8 corresponds to the same structure as does Figure 7, but is plotted to show a depth of 16 microns. Figure 9 shows the behavior predicted by the MEDICI™ program for the UMOS according to the present invention under an applied drain voltage of 150 volts, and doping concentrations of 2.0 X 10 16 cm "3 (2E16) in the n- layer (e.g., 12 in Figure 7), 2 x 10 19 cm "3 in the substrate 11, and 5 X 10 17 cm "3 in both the p-type epilayer 13 and in the grounded p-type region 23. Figure 9 is taken along a horizontal line again defined by y = 1.2023 microns; i.e., the same horizontal line as Figure 5. Thus, Figures 5 and 9 provide a basis for comparison of the two devices at a structurally equivalent point. As Figure 9 demonstrates, a peak in the electric field still occurs at the corner of the oxide (x = 3 microns, y = 20 1.2 microns), but also demonstrates that the electric field at that point has been greatly reduced; i.e., about 0.278 X 10 6 V/cm; i.e., more than an order of magnitude lower than the electric field at the oxide corner without the implanted p-layer (as compared to the field of 3.82 X 10 6 V/cm at the same point in Figures 5 and 6). Figure 10 plots the same information as Figure 9, but again taken along the vertical line at x = 3.0967. Thus, Figure 10 corresponds in its geometry to Figure 6. Figure 10 shows two peaks. The largest of the two peaks falls at the coordinates x = 3.1 and y = 1.75 which, referring to Figure 7, is adjacent the p-n junction. Figure 10 also shows that the oxide peak falls at the corner of the oxide (x = 3.1 and y = 1.2), but is again greatly reduced from the prior art device; i.e., about 0.18 x l0 6 V/cm. Figure 11 plots the electric field along the same horizontal line (y = 1.2033 microns) as in the other similar figures, but at an applied drain voltage of 950 volts in the structure of the invention. Figure 11 also represents the same doping level (2E16) in the n-layer as in Figures 9 and 10. Once again the peak electric field is at the corner of the oxide (x = 3, y = 1.2 microns) but is still relatively low; i.e., about 1.32 x 106 V/cm. Stated differently, even under an applied drain voltage of 950 volts, the structure of the present invention reduces the electric field at the corner of the oxide to a fraction of the electric field at the same position under far less voltage in conventional structures. Figure 12 corresponds to Figure 11 in that it represents an applied drain voltage of 950 volts, but as in other similar plots, is taken along the vertical line x = 3.0967 microns. Figure 12 also includes two peaks. Again, the higher of the two peaks (at coordinates x = 3.1 and y = 1.9 microns) represents the field at the p-n junction and, at a strength of approximately 3.12 X 10 6 V/cm is approaching the breakdown field of silicon carbide at this doping level. The other peak again occurs at the corner of the oxide (x = 3.1 microns, y = 1.2 microns) and is about 1.82 x 10 6 V/cm, well within the desired field strength parameters. Figure 13 is taken along a slightly different vertical line (x = 1.0536 microns) than the previous plots, but also represents 950 V applied to the drain and an n-doping level of 2E16. This particular x coordinate represents a vertical slice of the structure of the invention that is somewhat removed from the oxide, and thus demonstrates the field strength through the p and n portions of the transistor and particularly the field at the p-n junction (x = 1.0536, y = about 1.1 microns). Figure 13 shows the peak field strength in the silicon carbide near the p-n junction to be on the order of about 2.33 x 10 6 V/cm, which is again within the desired limits. As noted above, Figures 5 through 13 were all calculated at doping concentrations in the n-layer of 2E16 cm "3 . Because of the effect of doping on breakdown voltage, the MEDICI™ program was again used to simulate the behavior of the structure of the invention at a reduced doping level of 2.S X 10 15 cm "3 (2.5E15) in the n- layer. The grid is the same as that originally defined in Figures 7 and 8, and thus the coordinates of Figures 14-18 correspond to those in Figures 9-13. Figure 14 is another plot of the electric field taken along the vertical line at coordinate x = 3.0967 microns, with an applied drain voltage of 950 volts at the lower doping level of 2.5E15 cm "3 . Figure 14 includes two peaks that again respectively represent field strength at the oxide and the p-n junction. The field strength at the p-n junction (x = 3.1 and y = 1.95 microns) is about 1.69 X 10 6 V/cm well within the desired limits. Similarly, the maximum field in the oxide (x = 3.1 and y = 1.25 microns) is about 0.19 X 10 6 V/cm well under the maximum field of the corresponding prior art devices. Figure 15 corresponds to Figure 14, but with the data plotted along the horizontal line y = 1.2033 microns. Taken along this line, the peak field strength again occurs at the corner of the oxide (x = 3 and y = 1.2 microns) with a value of approximately 0.25 X 10 6 V/cm once again well under the maximum field of the prior art devices. Figures 16 and 17 represent plots for the same doping levels as Figures 14 and 15, but at an applied drain voltage of 2300 volts. The peak field still falls at the corner of the oxide (x = 3 and y = 1.2 microns), and the field strength at that point is 1.15 X 10 6 V/cm; i.e., still only a fraction of the field strength experienced by conventional devices at much lower voltages. Figure 17 corresponds to Figure 16, but is taken along the vertical line of x = 3.0967 microns. As in the other plots taken along a vertical line, Figure 17 shows two peaks, the higher of which represents the p-n junction (x = 3.1 and y = 1.8 microns). At the p-n junction the electric field reaches approximately 3.1 x 10 6 V/cm; i.e., closer to the breakdown voltage of the silicon carbide at this doping level. The peak field strength in the oxide, however, remains much lower, on the order of about 1.47 X 10 6 V/cm; i.e., a fraction of the field strength that would become problematic. Finally, Figure 18 corresponds to Figure 13 (z ' .e. 4 a vertical line at x = 1.0536 microns), except at the lower doping level (2.5E15 cm "1 ) and the higher drain voltage (2300 volts). Figure 18 demonstrates that along this vertical line, the field is strong throughout the p and n portions of the device and is closer to breakdown at all such points (i.e., always above about 2.10 X 10 6 V/cm). In short summary, Figures 4 through 18 demonstrate that the UMOS of the present invention offers superior resistance to oxide degradation or breakdown at voltages that are both multiples and orders of magnitude higher than those at which conventional silicon carbide UMOS devices would experience breakdown. As a proviso, the relatively close proximity of the p-type epitaxial layer of the transistor to the implanted p-type protective region can encourage a pinching effect that may reduce the on-current of the device. Accordingly, in preferred embodiments, the grounded p-type region is spaced sufficiently from the p-type epitaxial layer to minimize any such pinching effects. In another aspect, the invention comprises a method of making the insulated gate silicon carbide power transistors according to the present invention. In such aspect, the invention comprises etching a first-opposite-first conductivity-type silicon carbide structure to define a trench with a first-opposite-first conductivity-type wall, forming an opposite conductivity type layer at the bottom of the trench and aligned by the trench walls, forming the appropriate oxidation layer on the trench walls and trench bottom, and then adding respective ohmic contacts to form the source, gate, and drain (or emitter in an IGBT). Accordingly, in producing the previously described embodiments with the n-type source and drain, the method can further comprise growing a p-type epilayer on either an n-type epilayer or n-type substrate, followed by the step of forming an n-type well in the p-type epilayer. This produces an n-p-n SiC structure that can be etched to produce an n-p-n wall. Epitaxy of SiC is normally accomplished by chemical vapor deposition (CVD). Both 4H and 6H-SiC wafers with customer specified epilayers are commercially available. These layers can be nitrogen doped (n-type) or aluminum doped (p-type) at doping levels from 10 14 cm 3 to 10 20 cm "3 . Selective-area doping is accomplished by ion implantation. This is necessary because thermal diffusion coefficients in SiC are too small for diffusion of impurities to be practical. SiC can be implanted to greater than 10 19 cm "3 with nitrogen (n-type) and with either boron or aluminum (p-type). In preferred embodiments, the implantation is conducted with the wafer at an elevated temperature, and the implants are activated at 1200 to 1500°C in argon. (Note that at 1500°C, a silicon wafer would melt). Such high temperature implantation is described in U.S. Patent No. 5,087,576. Anisotropic etching is by RIE. Any fluorinated gas can be used, including NF 3 and SF 6 . Appropriate techniques for etching silicon carbide are set forth for example in U.S. Patents Nos. 4,865,685 and 4,981 ,551. An early problem reported by several investigators was micromasking caused by aluminum particle contamination during RIE of SiC. This problem can be eliminated by adding a graphite cover plate over the aluminum cathode in the RIE chamber. Highly anisotropic profiles in 6H-SiC to a depth of tens of microns can accordingly be obtained. The surface morphology of the etched surfaces is good. With respect to thermal oxidation, MOS oxides are critical elements of most semiconductor devices, particularly power devices. The important figures of merit are the interface state density DIT, the fixed charge density QF, and the breakdown field EBOX. A difficulty exists in obtaining an accurate measurement of the interface state density DIT on SiC. Because of the wide bandgap of SiC, deeper-lying interface states at the SiO 2 /SiC interface are not in thermal equilibrium with the semiconductor at room temperature, and the occupancy of interface states cannot follow changes in the DC bias. To correctly measure the interface state density using CV techniques, it is necessary to heat the sample enough that the states can remain in quasi-steady-state as the gate voltage is changed. This has not been recognized by all SiC researchers, and several erroneous reports are present in the literature. A better approach appears to be a modified hi-lo capacitance technique and an AC conductance technique at elevated temperatures to characterize the SiO 2 /SiC interface. Thick oxides are used for field and intermediate dielectrics and as passivation layers for field termination on high-voltage devices. It is not practical to grow thick oxides by conventional thermal oxidation due to the long times and temperatures involved. Moreover, dopant redistribution (segregation) into a growing thermal oxide can be a problem. Several other techniques are preferred, depending on the circumstances: (i) deposition of thick SiO 2 by either LPCVD or PECVD, (ii) deposition of an amorphous silicon layer which is later converted to SiO 2 by thermal oxidation, or (iii) application of spin-on-glass (SOG). Ohmic contacts are formed to n- and p-type layers by annealed nickel and annealed aluminum, respectively. These procedures are quite routine, and specific contact resistivities in the 10 "6 ohm-cm 2 range can be obtained to heavily-doped n-type SiC. Ohmic contacts to p-type material are more difficult, and contact resistivities range from 10 6 ohm-cm 2 for lightly-doped material to 10 " ' ohm-cm 2 for heavily doped material. Schottky contacts are easy to fabricate, and Fermi level pinning is not observed. As a result, barrier heights are a function of the metal, and a wide range of barrier heights are attainable. Typical metals used for Schottky contacts on SiC are Au, Pt, and Ti. Metal and polysilicon deposition procedures are similar to silicon, and no unusual problems are generally encountered. Preferred techniques include boat-evaporated aluminum, molybdenum or LPCVD polysilicon as gate materials for SiC MOSFETs. In another embodiment, the invention comprises an insulated gate bipolar transistor (IGBT). As known to those familiar with such devices, an IGBT has the high input impedance and high speed characteristics of a MOSFET with the conductivity characteristic— low saturation voltage — of a bipolar transistor. In its most typical application, the IGBT is turned on by applying a positive voltage between the source and the emitter, and as in a MOSFET is turned off by making the gate signal zero or slightly negative. An IGBT has a much lower on resistance than a corresponding MOSFET. Compared to a MOSFET, an IGBT is generally smaller with the same current rating, although the bipolar action in an IGBT slows down the device so that it exhibits a much lower frequency than a corresponding MOSFET. IGBTs are discussed in some detail in Dorf, The Electrical Engineering Handbook (1993); CRC Press at pages 699-700; and related devices such as the field/controlled thyristor are discussed in Sze, Physics of Semiconductor Devices, Second Edition, 1981 at pages 238-240. Accordingly, the structure and function of the IGBT will not be discussed in detail herein other than to illustrate this embodiment of the present invention. In this embodiment, the invention comprises an insulated gate bipolar power transistor formed in silicon carbide with silicon dioxide as the gate insulator. The transistor includes a source with the first conductivity type, and a protective region beneath the gate oxide that has the opposite conductivity type from the source, for protecting the gate oxide from the degrading or breakdown effects of a large voltage applied across the transistor. An IGBT according to the present invention is illustrated in Figure 19 and is broadly designated at 30. The IGBT 30 comprises a p-type silicon carbide substrate 31, an n-type silicon carbide epitaxial layer 32 on the p-type substrate 31, a p-type silicon carbide epitaxial layer 33 on the n-type epitaxial layer 32, and an n-type well 34 in the p-type epitaxial layer 33. A gate trench illustrated by its wall 35 and bottom 36 extend through the n-type well 34 and the p-type epitaxial layer 33 and terminates in the n-type substrate 32. A gate oxide 37 is on the wall 35 and bottom 36 of the trench. Respective ohmic contacts 40, 41, and 42 to the gate oxide 37 to the n-type well 34 and to p-type substrate 31 define the gate, the source, and the emitter. As in the other embodiments, the IGBT 30 includes a p-type silicon carbide region 43 between the gate oxide 37 and the n-type epitaxial layer 32 and aligned with the bottom 36 of the gate trench for protecting the oxide 37 in the trench from the degrading or breakdown effects of a large positive voltage applied across the transistor 30. In preferred embodiments, the p-type region is grounded and is formed by implantation as discussed previously. Similarly, and as in the MOSFET embodiments of the invention, the p-type region 43 is spaced sufficiently from the p-type epitaxial layer 33 to minimize any current pinching effects between the p-type region 43 and the p-type epitaxial layer 33. As in the earlier embodiments, the ohmic contacts to the n-type regions are selected from the group consisting of nickel and nickel alloys, while the ohmic contacts to the p type material are preferably selected from the group consisting of aluminum, aluminum alloys, and cobalt suicide. As in the previous embodiments, nitrogen is typically preferred for doping the n-type material, while the p-type material is typically doped with either aluminum or boron. As in the earlier embodiments, the silicon carbide in the transistor 30 has a polytype selected from the group consisting of 4H and 6H. Reducing the On-Resistance Figure 20 illustrates another embodiment of the invention. In this regard, the MEDICI™ simulation used herein also indicates that the protection offered by the additional p-type layer at the bottom of the trench increases as the distance ("d" in Figure 20) along the trench wall between the p-type layer of the transistor and the p-type protection layer decreases. Stated in the alternative, the protective effect on the oxide is better when these two p-type portions of the device are closer to one another. As a proviso noted in the above, however, decreasing this distance between the two p-type regions tends to encourage pinch-off between them which can eventually block all current at forward bias. Basic calculations indicate that for typically useful doping concentrations in the p and n-type portions of the UMOS (e.g., p = 2 X 10 17 cm "3 , n = 2.5 X 10 15 cm "3 ), pinch off will occur when the distance between the two p-type portions is less than about 1.5 microns. Obtaining a 1.5 micron gap, however, presents some problems. First, from a processing standpoint, physically defining such a distance requires that the trench be etched to a depth of about 3 microns. Accordingly, if aluminum is used in typical fashion as a reactive ion etching (RIE) mask, at least about 6750 A of aluminum will be theoretically required. In reality, however, because of the thickness variation of aluminum deposition and etch rate variation during RIE, 8,000 A of aluminum would be typically necessary for a safe mask. The aluminum mask then would need to be removed using lift off technology in order to keep straight sidewalls in the trench. Lifting off an 8,000 A layer of aluminum is technically difficult, however, and is best avoided if at all possible. Alternatively, if the two p-type layers are spaced 1.5 microns or more apart to minimize the processing problems, the greater distance will correspondingly minimize the protective effect for which the additional p-type layer is included in the structure. Accordingly, there exists a need to tailor the geometry of the structures disclosed herein to minimize the possibility of pinching off the current and to avoid technical difficulties in masking and etching deep trenches solely for the purpose of establishing a minimum distance between the p-type layers. Accordingly, in the embodiment illustrated in Figure 20, the present invention provides an insulated gate structure that minimizes the possibility of pinching off the current while at the same time taking advantage of the full capabilities of UMOS and IGBT structures, particularly in silicon carbide. In this embodiment, the invention comprises a UMOS field-effect transistor, including a trench and a trench oxide on the walls and bottom of the trench. A protective region is beneath the bottom portion of the trench oxide of the transistor for protecting the trench oxide from the degrading or breakdown effects of a large voltage applied across the device. A current enhancing layer is between the protective region and the channel of the insulated gate structure, and the current enhancing layer is preferably more heavily doped than the remainder of the n-type drain region of the transistor. Figure 20 illustrates the present invention in the form of an upright metal oxide semiconductor p-channel enhancement type field effect transistor broadly designated at 50. Although the structure is designed to particularly take advantage of the properties of silicon carbide, the present invention offers advantages for devices in both silicon and silicon carbide. With this understanding, however, the remainder of the description of this embodiment will be made in terms of silicon carbide. Figure 20 illustrates that the UMOS 50 of the invention includes an n-type silicon carbide substrate 51 with an n-type silicon carbide epitaxial layer 52 on the n-type substrate. As Figure 20 illustrates with the n+ and n- designations, in preferred embodiments the substrate 51 that meets the drain contact is more heavily doped than the epitaxial layer 52, to enhance the current flow to the drain. It will be understood that under some circumstances, a single substrate can take the place of the substrate 51 and the epilayer 52. The n+/n- structure, however, offers certain current-flow advantages, and is thus generally preferred. A p-type epitaxial layer 53 forms the channel region of the UMOS 50 and an n-type well 54 forms the source. Figure 20 also illustrates the trench 55 and the gate oxide 56 that covers the walls 57 and bottom 60 of the trench 55. As in the previous embodiments, the invention includes the grounded p-type region 61 between the oxide 56 and the n-type epitaxial layer 52 and that is aligned with the bottom 60 of the gate trench 55 for protecting the oxide 56 in the trench 55 from the degrading or breakdown affects of a large positive voltage applied to the drain. The UMOS of this embodiment, however, further comprises the current enhancing n-type layer 62, preferably an n+-type layer, between the grounded p-type region 61 and the p-type channel region 53 of the UMOS structure 50. The current enhancing n-type layer 62 is preferably more heavily doped than the remainder of the n-type epitaxial layer 52. Figure 20 also illustrates the source contacts 63, the gate contact 64 and the drain contact 65. By placing the current enhancing n-type layer 62 underneath the p-type channel layer 53, the structure avoids current pinch off even at much smaller distances (d) between the p-type channel portion 53 and the grounded p-type region 61. For example, the same calculations that demonstrate pinch off occurring at distances (d) of 1.5 microns or less in a structure such as Figure 1 demonstrate that pinch off can be avoided using the invention for distances (d) of as little as 0.18 microns. Accordingly, if the distance d can be made somewhat smaller, the processing of the structure can be made correspondingly easier while at the same time strengthening the protective effect of the p-type layer 61. Additionally, the current enhancing layer 62 also helps to reduce the drain resistance at forward bias. In the absence of the additional n-type layer 62, the current spreading out from the bottom of the trench corner to the drain creates a large spreading resistance around the trench corner. By adding the n-type layer 62, the current can first flow laterally inside the n-type layer, and then flow down to the drain, thus minimizing or eliminating the spreading resistance under forward bias. The MEDICI™ simulation program was again used to check the behavior of the structure of the present invention. The simulation demonstrated that at a concentration of about 2 X 10 17 cm "3 in the n-type current enhancing layer 62, and a distance d of 0.18 microns between the two p-type portions 53 and 61 , no pinch off occurs and forward current increases by a factor of about 10. It will be understood that the doping concentration and the thickness of the n-type layer 62 should be designed carefully so that the n-type layer 62 can effectively strengthen the protective effect of the grounded p-type layer 61 while at the same time still providing the maximum usage of the n- region 52 to block reverse voltage drop. In summary, the addition of the n-type layer 62 serves at least two purposes. First, it prevents pinch off even for a very small d thus in turn strengthening the protective effect of the grounded p-type layer 61 at reverse bias. Second, the n-type layer 62 reduces the on-resistance at forward bias. As noted above, preliminary two-dimensional MEDICI™ simulation appears to verify these two advantages. From a processing standpoint, the addition of the n-type layer 62 is relatively straightforward in that it requires simply growing one more epitaxial layer while using the identical mask design and processes that are used to make the UMOS illustrated in Figure 2. As some additional details, in preferred embodiments, the n-type substrate 51 typically has a carrier concentration of about 2 X 10 19 cm "3 . The n-type epitaxial layer 52 generally has a carrier concentration of between about 2.5 X 10 15 cm '1 and 2 X 10 16 cm "3 . The current enhancing n-type epitaxial layer 62 preferably has a carrier concentration about 2 X 10 17 cm "3 . The p-type epitaxial layers 53 and the grounded p-type region 61 typically have carrier concentrations of between 2 X 10 17 cm "3 and 5 X 10 17 cm "3 . As discussed with regard to the earlier embodiments, when the semiconductor is silicon carbide, the grounded p-type region 61 is typically an implanted region doped with aluminum or boron. Additionally, in the silicon carbide embodiments, the preferred n-type dopant is nitrogen and the preferred dopant for the p-type epilayer 53 is also aluminum. When the structure is formed in silicon, the preferred p-type dopant is boron, and the preferred n-type dopants are phosphorous, arsenic, and antimony. In the silicon carbide embodiments, the ohmic contacts 63 and 65 to the n-type well 54 and n-type substrate 51 are generally selected from the group consisting of nickel and nickel alloys, while the p-type region 61 is grounded through an ohmic contact (not shown) selected from the group consisting of aluminum and aluminum alloys and cobalt suicide (CoSi 2 ). In another aspect, the present embodiment can be described by the structure of the trench 55. This structure comprises the trench wall 57 and the grounded p-type region 61 that forms the trench bottom 60. The trench wall 57 and trench bottom 60 are covered by the gate oxide 56 of the UMOS 50. The trench wall 57 beneath the oxide 56 in turn comprises the n+ well 54 for the source, the p-type epitaxial layer 53 for the channel positioned beneath the n+ type well 54, the current enhancing n-type type layer 62 beneath the p-type epitaxial layer 53, and the n-type drain region 52 (together with the substrate 51) beneath the current enhancing n-type layer 62. As in the other embodiments, the n-type drain region 52 is less heavily doped than the current enhancing n-type layer 62. In another embodiment, the invention comprises an insulated gate bipolar transistor (IGBT) formed in silicon carbide with silicon dioxide as the gate insulator. The transistor has a source with a first conductivity type, a protective region adjacent the gate oxide and that has the opposite conductivity type from the source for protecting the gate oxide from the degrading or breakdown effects of a large voltage applied across the transistor, and a current enhancing layer having the first conductivity type and positioned between the protective region and the source region of the transistor. Figure 21 illustrates a particularly preferred IGBT embodiment broadly designated at 70. The IGBT 70 comprises a p-type silicon carbide substrate 71, an n-type silicon carbide epitaxial layer 72 on the p-type substrate 71, a p-type silicon carbide epitaxial layer 73 on the n-type epitaxial layer 72, an n-type well 74 in the p-type epitaxial layer 73, and a gate trench broadly designated at 75 extending through the n-type well 74, the p-type epitaxial layer 73, and terminating in the n-type epitaxial layer 72. A gate oxide 76 is on the walls and bottom of the trench 75 and respective ohmic contacts 77, 80, and 81 are made to the gate oxide 76, to the n-type well 74 and to the p-type substrate 71 for respectively defining the gate, the source, and the emitter. A p-type silicon carbide protective region 82 is between the oxide 76 and the n-type epitaxial layer 72 and is aligned with the bottom of the gate trench 75 for protecting the oxide 76 in the trench 75 from the degrading or breakdown effects of a large, positive voltage applied across the IGBT 70. An n-type current enhancing layer 83 is positioned between the protective region 82 and the source 74. As in previous embodiments, the p-type protective region 82 is preferably grounded with an ohmic contact selected from the group consisting of aluminum, aluminum alloys, and cobalt suicide and is preferably formed by ion implantation. The ohmic contacts to the n-type well 74 are preferably selected from the group consisting of nickel and nickel alloys. The n-type well 74, n-type epitaxial layer 72 and n-type current enhancing layer 83 are all preferably doped with nitrogen, and the preferred dopant for the p-type epitaxial layer 73 is selected from the group consisting of aluminum and boron. As in the other embodiments, the silicon carbide preferably has a polytype selected from the group consisting of 4H and 6H. In the drawings and specification, there have been disclosed typically preferred embodiments of the invention and, although specific terms have been employed, they have been used in the generic sense and descriptive sense only, and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims: CLAIMS: 1. A silicon carbide UMOS power transistor that demonstrates increased maximum voltage, said transistor comprising: a metal oxide semiconductor, enhancement-type field effect transistor formed in silicon carbide and including a trench and a trench oxide on the walls and bottom of said trench; said transistor having a source and drain with a first conductivity type and a channel region with the opposite conductivity type; characterized by: a region beneath said trench oxide of said transistor that has the opposite conductivity type from said source and drain for protecting said trench oxide from the degrading or breakdown effects of a large voltage applied to the drain. 2. A silicon carbide UMOS power transistor according to Claim 1 wherein said source and drain are p-type and said region beneath said trench oxide is n-type. 3. A silicon carbide UMOS power transistor according to Claim 1 comprising: an n-type silicon carbide substrate; a p-type silicon carbide epitaxial layer on said n-type substrate; an n-type well in said p-type epitaxial layer; a gate trench extending through said n-type well and said p-type epitaxial layer and terminating in said n-type substrate; a gate oxide on the walls and bottom of said trench; respective ohmic contacts to said gate oxide for defining a gate, to said n-type well for defining a source, and to said substrate for defining a drain; and a p-type silicon carbide region between said oxide and said n-type substrate and aligned with the bottom of said gate trench for protecting said oxide in said trench from the degrading or breakdown effects of a large positive voltage applied to the drain. 4. A silicon carbide UMOS power transistor according to Claim 3 wherein said n-type well and said n-type substrate are both doped with nitrogen. 5. A silicon carbide UMOS power transistor according to Claim 3 wherein said n-type substrate has a carrier concentration of about 2 X 10 16 cm "3 ; and said p-type epitaxial layer has a carrier concentration of about 5 X 10 17 cm "3 . 6. A silicon carbide UMOS power transistor according to Claim 1 comprising: an n-type silicon carbide substrate; an n-type silicon carbide epitaxial layer on said n-type substrate; a p-type epitaxial layer on said n-type epitaxial layer; an n-type well in said p-type epitaxial layer; a gate trench extending through said n-type well and said p-type epitaxial layer and terminating in said n-type epitaxial layer; a gate oxide on the walls and bottom of said trench; respective ohmic contacts to said gate oxide for defining a gate, to said n-type well for defining a source, and to said substrate for defining a drain; and a p-type region between said oxide and said n-type epitaxial layer and aligned with the bottom of said gate trench for protecting said oxide in said trench from the degrading or breakdown effects of a large positive voltage applied to the drain. 7. A silicon carbide UMOS power transistor according to Claim 3 or 6 wherein said p-type region is a grounded region. 8. A silicon carbide UMOS power transistor according to Claim 6 wherein said n-type substrate is more heavily doped than said n-type epitaxial layer. 9. A silicon carbide UMOS power transistor according to Claim 6 wherein said n-type substrate has a carrier concentration of about 2 X 10 19 cm "3 and said n-type epitaxial layer has a carrier concentration of between about 2.5 X 10 15 cm " 3 and 2 X 10 16 cm "3 . 10. A silicon carbide UMOS power transistor according to Claim 1 , 3, or 6 wherein the silicon carbide has a polytype selected from the group consisting of 4H and 6H. 11. A silicon carbide UMOS power transistor according to Claim 6 wherein said p-type epitaxial layer has a carrier concentration of about 5 X 10 17 cm "3 ; and said p-type protective region has a carrier concentration of about 5 X 10 17 cm" 12. A silicon carbide UMOS power transistor according to Claim 1, 3, or 6 wherein said p-type protective region is an implanted region. 13. A silicon carbide UMOS power transistor according to Claim 6 wherein the dopant for said p-type protective region is selected from the group consisting of aluminum and boron. 14. A silicon carbide UMOS power transistor according to Claim 3 or 6 wherein said p-type region is spaced sufficiently from said p-type epitaxial layer to minimize any current pinching effects between said p-type region and said ρ-tyρe epitaxial layer. 15. A silicon carbide UMOS power transistor according to Claim 3 or 6 wherein said ohmic contacts to said n-type well and said n-type substrate are selected from the group consisting of nickel and nickel alloys. 16. A silicon carbide UMOS power transistor according to Claim 7 wherein said grounded p-type region is grounded through an ohmic contact selected from the group consisting of aluminum, aluminum alloys and cobalt suicide. 17. A silicon carbide UMOS power transistor according to Claim 6 wherein said n-type epitaxial layer is doped with nitrogen. 18. A silicon carbide UMOS power transistor according to Claim 3 or 6 wherein the dopant for said p-type epitaxial layer is selected from the group consisting of aluminum and boron. 19. A silicon carbide UMOS power transistor according to Claim 1 , 3, or 6 wherein the oxide comprises silicon dioxide. 20. A silicon carbide insulated gate bipolar power transistor (IGBT) that demonstrates increased maximum voltage, said transistor comprising: a p-type silicon carbide substrate; an n-type silicon carbide epitaxial layer on said p-type substrate; a p-type silicon carbide epitaxial layer on said n-type epitaxial layer; an n-type well in said p-type epitaxial layer; a gate trench extending through said n-type well and said p-type epitaxial layer and terminating in said n-type substrate; a gate oxide on the walls and bottom of said trench; respective ohmic contacts to said gate oxide for defining a gate, to said n-type well for defining a source, and to said substrate for defining an emitter; and a p-type silicon carbide region between said oxide and said n-type epitaxial layer and aligned with the bottom of said gate trench for protecting said oxide in said trench from the degrading or breakdown effects of a large positive voltage applied across said transistor. 21. A silicon carbide IGBT power transistor according to Claim 20 wherein said p-type region is a grounded region. 22. A silicon carbide IGBT power transistor according to Claim 20 wherein said p-type region is an implanted region. 23. A silicon carbide IGBT power transistor according to Claim 20 wherein said p-type region is spaced sufficiently from said p-type epitaxial layer to minimize any current pinching effects between said p-type region and said p-type epitaxial layer. 24. A silicon carbide IGBT power transistor according to Claim 20 wherein said ohmic contacts to said n-type well and said n-type substrate are selected from the group consisting of nickel and nickel alloys. 25. A silicon carbide IGBT power transistor according to Claim 21 wherein said grounded p-type region is grounded through an ohmic contact selected from the group consisting of aluminum, aluminum alloys, and cobalt suicide. 26. A silicon carbide IGBT power transistor according to Claim 20 wherein said n-type well and said n-type substrate are both doped with nitrogen, and wherein the dopant for said p-type epitaxial layer is selected from the group consisting of aluminum and boron. 27. A silicon carbide IGBT power transistor according to Claim 20 wherein the silicon carbide has a polytype selected from the group consisting of 4H and 6H. 28. A UMOS according to Claim 1, 3, or 6 and further comprising: a current-enhancing layer having the opposite conductivity type from said protective region and positioned between said protective region and the channel of said UMOS structure. 29. A UMOS power transistor according to Claim 28 wherein said current-enhancing layer is more heavily doped than the remainder of the drain region of said transistor. 30. A silicon carbide IGBT according to Claim 20 and further comprising an n-type current-enhancing layer positioned between said protective region and the source region of said transistor. 31. A silicon carbide insulated gate bipolar power transistor according to Claim 20 wherein said gate insulator comprises silicon dioxide.

Inventors: COOPER JAMES ALBERT JR, TAN JIAN, COOPER, JAMES, ALBERT, JR., TAN, JIAN
Applicants: COOPER JAMES ALBERT JR, TAN JIAN, COOPER, JAMES, ALBERT, JR., TAN, JIAN
Application year: 1998
Main classification: H01L29
IPC codes: H01L29