IMPROVED SUCCESSIVE APPROXIMATION A/D CONVERTER

Abstract: Apparatus and method are disclosed for successive approximation analog-to-digital conversion of a variable analog input voltage to digital form by periodic sampling thereof, using a comparator to compare the relative values of the analog input voltage amplitude in a predetermined time interval and the upper limit of a reference voltage range which is successively adjusted until it closely approximates the digital value of the sampled analog input voltage in that time interval. The successive adjustment is performed by a successive approximation register which has an odd number of multiple stages, at least three, for each digital significant bit representing the upper limit of the reference voltage range to be used in the comparison. The accuracy and reliability of this upper limit is refined by using as the value of each significant bit the majority of its value in the multiple stages. After a number of comparisons that fixes the majority value of each significant bit, the resulting succession of the significant bits becomes the digital conversion of the analog input voltage in the respective time interval.

Description: IMPROVED SUCCESSIVE APPROXIMATION A/D CONVERTER Background of the Invention The present invention relates generally to analog-to-digital (A/D) conversion techniques, and more particularly to improvements in successive approximation register A/D conversion. Generically, A/D conversion constitutes any of many available methods for converting measured analog quantities to digital form so that the digital representations of the quantities of interest may be processed by a computer, or displayed, or stored. So-called "successive approximation " is among the most popular of the many different techniques. Unlike other methods, the conversion time for successive approximation A/D conversion, i.e., the time interval in which the analog quantity is converted to digital form, is fixed. That is, conversion time is the same regardless of the value of the analog quantity being converted. Referring to the block diagram of a prior art successive approximation converter in FIG. 1, the A/D converter 10 consists of three basic components, namely, a digital-to-analog converter (DAC) 12, a successive approximation register (SAR) 15, and a comparator 16. The comparator 16 compares the output of the DAC 12, which is supplied as one of the inputs of the comparator, to an analog quantity of interest, typically an analog input signal voltage V 1N , which is supplied to the other comparator input. In operation of the prior art converter of FIG. 1, SAR 15, DAC 12, and comparator 16 operate in a closed loop system to determine the digital (binary) equivalent of an applied analog signal V IN . The system determines the value of each bit, from the most significant bit (MSB) to the least significant bit (LSB), in succession by dividing the previous range in which the analog input signal can be found, in half. For example, an analog voltage of +7.2 volts lies within a range of interest between 0 volts and 16 volts. The SAR system divides the valid range (0 to 16 volts) in half, and provides an output of 8 volts (a binary value of 1000) from the 4-bit DAC to the comparator. The comparator output indicates to the SAR that the current binary value is too high (i.e., 8 volts being greater than 7.2 volts). The MSB value is now known to be a logic 0, and the new valid range in which the analog input voltage can be found is between 0 volts and 8 volts. Next, the SAR divides the new valid range in half, and provides an output of 4 volts (a binary value of 0100) from the 4-bit DAC to the comparator. This time the comparator output indicates to the SAR that the current binary value is too low (i.e., 4 volts being less than 7.2 volts). The second most significant bit value is now known to be a logic 1 , and the new valid range in which the analog input voltage can be found is between 4 volts and 8 volts. The sequence continues for the next two bits, and the binary output of the SAR is found to be 0111. That digital value is provided as the output of the successive approximation A/D converter, and the SAR registers are cleared to 0's in preparation for the next sample conversion cycle. In practice, problems are encountered with a conventional successive approximation A/D converter in that the comparator at times may have considerable difficulty in determining whether the voltage applied from the DAC is greater than or less than the analog input voltage W w , such as when V, N is close to the DAC value, or when noise is present. An example is illustrated in the signal diagram of FIG. 2, where voltage V ΓN is wavering because of system noise, jitter, or the like. In these circumstances, the comparator may fluctuate between a high and a low output, which is likely to produce errors in the digital conversion value of the conventional SAR converter. Accordingly, it is a principal aim of the present invention to provide an improved technique of successive approximation analog-to-digital conversion. A more specific objective of the invention is to provide an improved successive approximation A/D converter for substantially better reproduction of conversions even when the difference between inputs to be compared is not readily discernible by the comparator. Summary of the Invention According to the invention, a method and a circuit are employed to attain improved repeatability and stability of the A/D conversion. In particular, each time a sampling and conversion of the analog input voltage is to be performed, rather than looking at a single sample of VΓ N at eacn interval, the analog input voltage is sampled several times per interval for comparison with the DAC output. The SAR is implemented with additional latches and shift register stages to accommodate the number of samples selected per DAC input bit, as well as with a majority vote logic circuit. The majority of the binary values among the samples, 0 or 1, for-a particular bit wins the vote as the value of the input to the DAC for that bit location. For that reason the number of samples taken for any given bit must be an odd number (to arrive at a majority), and is at a minimum three to take into account the desire for repeatability and stability without unduly reducing the speed of conversion of the successive approximation approach. If desired, the majority detect approach can be limited to only those times when the comparator output appears to be fluctuating. This may occur only once or twice during conversion of the analog signal to a 12-bit digital value. Nevertheless, the desire remains to make the conversion process more repeatable. For example, if a conversion were performed with V m at just slightly more than one-half of V DD (e.g., 2 microvolts (μV) higher than exactly one-half) — the improved SAR converter of the invention will still arrive at the same conversion value much more often than would be the case with prior art SAR A/D converters. The conversion repeatability increases asymptotically with the number of inputs to the majority vote logic circuit. In a preferred method of performing successive approximation A/D conversion of a variable analog input signal according to the invention, a reference range is selected with an upper limit to encompass the digital value of the analog input signal, the upper limit of the reference range is compared to the magnitude of the analog input signal in a predetermined time interval to obtain the most significant bit (MSB) of the digital value for the conversion, the reference range is successively divided in half for comparison to that magnitude to obtain each successive significant bit from MSB to least significant bit (LSB) of the digital value for the conversion, with the number of divisions of the reference range being dependent on the number of bits from MSB to LSB of the digital value for the conversion, and the magnitude of the analog input signal over the selected time interval is acquired by rapidly sampling the analog input signal an odd number of times over the predetermined time interval and taking the consensus of the samples as its magnitude. The odd number is at least three. The digital value from MSB to LSB is then the conversion value of the magnitude of the analog input signal over the predetermined time interval. Stated somewhat differently, the method of successive approximation A/D conversion of a variable analog input signal according to the invention includes rapidly sampling the amplitude of the analog input signal an odd number of times, at least three, during a predetermined time interval, comparing the value of each sample to a first predetermined reference value estimated to be the maximum value of a range in which the amplitude of the analog input signal lies in the predetermined time interval to obtain a binary value representing whether the sample value is above or below the first reference value, and using the majority of corresponding binary values of the odd number of samples as the binary value of the MSB for the digital conversion. The reference value is then halved and compared against the value of each sample, and the majority binary value obtained from the comparisons is used as the next most significant bit. The process of halving the reference value, comparing and taking the majority binary value as the value for each succeeding bit is continued until the LSB is obtained for the digital conversion. A successive approximation A/D converter according to the invention includes an SAR for generating a digital output in the form of a succession of binary values ranging from MSB of 2 n to LSB of 2° in response to a succession of inputs thereto, where n+1 is the number of significant bits in the conversion, a comparator for supplying an input to the SAR based on a comparison of the instantaneous magnitude of the analog input signal to the magnitude of a reference signal, means for converting a succession of binary values to analog values as the reference signal to the comparator, and means for performing a majority vote of an odd number of binary values associated with each of the succession of binary values to provide a modified succession of binary values to the converting means. Means are provided for rapidly sampling the magnitude of the analog input signal during a predetermined time interval as an input to the comparator to provide the odd number of binary values as the respective values of each of an odd number of successive ones of the samples relative to the reference signal for delivery to the SAR for use in performing the majority vote. The SAR includes means for generating an upper limit of a reference range of magnitudes in digital format as the reference signal for the comparison. The successive approximation A/D converter of the invention may also be viewed as including means for supplying samples of the magnitude of the analog input signal relative to the maximum value of a reference range over a predetermined time interval as binary inputs to the SAR, the SAR being adapted to adjust the reference range based on a succession of the binary inputs to more closely encompass the sampled magnitude of the analog input signal over the time interval for use in refining the digital output to better represent the analog input signal magnitude; and means for further adjusting the reference range by discarding samples having a binary value that differ from a norm established by a majority of the binary inputs during the time interval. The samples are supplied to provide an odd number of binary inputs of at least three in number to the SAR for each significant bit in a digital representation of the reference range, including successive adjustments of the range, for determination of the majority for each significant bit in the digital representation in the predetermined time interval. Logic means coupled to the SAR detects or determines the majority binary value for each significant bit in the digital representation. The SAR has an effective digital content, after determination of the majority binary value for each significant bit in the digital representation of the reference range in the predetermined time interval, constituting the digital output representative of the variable analog input signal in that time interval. Another aim of the invention, then, is to improve the repeatability, accuracy, and reliability of a successive approximation A/D conversion by multiple high-rate sampling of the analog signal to be converted during periods of noise on or waver of the signal. Brief Description of the Drawings The above and still further aims, objects, aspects, features and attendant advantages of the present invention will become apparent from a consideration of the following detailed description of the best mode currently contemplated for practicing the invention, encompassed by a preferred method and embodiment, taken in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram of a prior art successive approximation A/D converter, which has been discussed above; FIG. 2 is a signal diagram of analog input signals to a comparator of the successive approximation A/D converter, to be converted to digital form over a time interval including a sampling period, also discussed above; FIG. 3 is a sampling and A/D conversion diagram illustrating the outcome of an exemplary majority detect scheme according to the invention; and FIG. 4 is a block diagram of a preferred embodiment of the SAR portion and related logic of a successive approximation A/D converter according to the present invention. Detailed Description of the Preferred Methods and Embodiments Referring now to FIG. 3, in the successive approximation A/D converter of the present invention the analog input signal V ]N of FIG. 2 is sampled at a high rate multiple times over a predetermined very brief period of time closely corresponding to the typical predetermined interval at which samples are taken in the standard successive approximation A/D converter. This multiple sampling is therefore performed while the signal may be undergoing relatively rapid undulations or excursions which, in the conventional successive approximation A D converter, would produce a single sample that may not result in an accurate conversion output bit from the comparator. For example, if five samples are taken, designated SI, S2, S3, S4, and S5 in the diagram of FIG. 3, they produce outputs of 1, 0, 1, 1, and 0, respectively. The majority of these samples is a 1 (3 out of the 5 samples being a binary value of 1), so a binary 1 constitutes the value derived from this portion of the conversion process. In the conventional SAR 15 of A/D converter 10 (FIG. 1), each of a plurality of individual register stages includes individual latches and shift register to which the samples are supplied after each comparison. The same basic arrangement is provided in an exemplary embodiment of an SAR A/D converter according to the present invention, except that the sampling rate is markedly increased and rather than using each individual sample as the basis for the conversion process, multiple samples are examined to arrive at an appropriate value, based on a majority vote, or consensus. The high sampling rate takes into account changes in a rapidly varying analog input signal to accurately portray these undulations. A plurality of stages of odd number form the basic unit of the successive approximation register so as to accept numerous samples obtained within a predetermined interval, and then the binary value of the majority of these successive samples for that interval of the analog signal is used to determine the digital output of the conversion process for that interval. The samples result in output bits from the comparator in a manner similar to that illustrated in FIG. 3, except that in the preferred embodiment of the SAR of the invention, the number of repetitive samples taken for determination of the SAR content for a particular significant bit (to be applied as a given DAC input bit) is a minimum of three. These bits are fed into the three successive stages of shift register with related latches to hold the stored bits over the individual overall sampling period. It should be understood that sampling may be performed in advance of application to the comparator, or by the effect of clocking the comparator output into the SAR. In the latter arrangement, the comparator output would be undergoing change during the selected time interval if the analog input signal amplitude is varying by a sufficient amount in that interval while the reference signal value to the comparator is held constant. The differences in the comparator output are entered into the register stages of the SAR for the significant bit of interest upon each clock signal. For example, in the embodiment of a portion of a SAR 25 shown in FIG. 4, three bits constituting the result of compared values of three samples that substitute for the conventional single sample taken in a prior art SAR, have the values 1, 0, and 1. The contents of the register are detected in parallel by a majority detect logic circuit 27 which determines binary value of the majority, or a consensus value, and delivers that bit value to DAC 12 for the bit number to be used in a conversion to analog value for the next comparison by the comparator (not shown in FIG. 4). An odd number of stages for each significant bit of the SAR allows a majority binary value to be determined for that bit. In the example of FIG. 4, the contents of the first three stages of SAR 25 are detected by logic 27 as a majority binary value of 1, which provides the value of DAC bit 7. If only the content of the first sample (first stage) of the SAR had been taken as the DAC bit value, as in a conventional arrangement, it would by coincidence have been the same value as that arrived at by multiple samplings in the arrangement of FIG. 4, but the conversion process in the former case would not be as reliable as in the majority rule/digital filtering approach of the invention. The same procedure is followed for each of the multiple stages whose majority or consensus content establishes the value of the next DAC bit, and so forth. Each bit determined in that manner may be captured in a latch (not shown). The multiple stage shift register and majority detect logic may be and preferably is used by the SAR and associated logic to develop each DAC bit. Alternatively, a suitable SAR may consist of parallel shifts registers, one with multiple stages and another with single stage, and having switchable inputs to allow some compare bits to be applied to the multiple stage register with majority detect logic for determination of the next DAC bit when analog signal characteristics warrant, and other compare bits to be applied to the single stage as outputs directly to the applicable DAC bit input, and so forth. A typical application for the successive approximation A/D converter of the present invention is a 12-bit system with very high resolution, 10 volts by 4096 states, and down to one-quarter of a millivolt (250 microvolts). In such an application. a situation in which a slight difference between V+ and V- (as with the signal depicted in FIG. 2) is difficult to detect may be encountered frequently, so that the accuracy, resolution, and repeatability provided with the multi-stage SAR and majority rule of the invention is a highly desirable feature. In an application requiring monitoring of status of charge on a battery in an electronic device, such as the battery in a portable personal computer, the voltage deflection will indicate when the battery is fully charged. When the voltage on the battery begins to decrease, by as slight an amount as one-quarter of a millivolt, the appropriate state of charge has been attained. A battery charge level monitor, often referred to as a "fuel gauge," must be sufficiently accurate at these levels to assure that the battery is not being overcharged, and therefore, to shut down the charging circuit once the level of a full charge has been attained. If the A/D conversion process were not repeatable and highly accurate, the result could be an inefficient charge on the battery and a deleterious effect on the system in which the battery is installed. Although a best mode currently contemplated for practicing the invention has been described herein, in conjunction with certain preferred methods and embodiments, it will be recognized by those skilled in the art of the invention that variations and modifications of the disclosed methods and embodiments may be made without departing from the true spirit and scope of the invention. Accordingly, it is intended that the invention shall be limited only by the appended claims and the rules and principles of the applicable law.

Claims: Claims: 1. A method of performing successive approximation analog-to- digital conversion of a variable analog input signal, which comprises selecting a reference range for the digital value of said analog input signal, comparing the upper limit of said reference range to the magnitude of said analog input signal in a predetermined time interval to obtain the most significant bit (MSB) of the digital value for said conversion, successively dividing said reference range in half for comparison to said magnitude to obtain each successive significant bit from MSB to least significant bit (LSB) of the digital value for said conversion, wherein the number of divisions of said reference range depends on the number of bits from MSB to LSB of said digital value for the conversion, and acquiring said magnitude of the analog input signal over said predetermined time interval by rapidly sampling the analog input signal an odd number of times over said predetermined time interval and taking the consensus of said samples as said magnitude. 2. The method of claim 1, wherein the minimum number of said odd number of times in which the analog input signal is sampled during said predetermined time interval is three. 3. The method of claim 2, including outputting the digital value from MSB to LSB as the conversion value of the magnitude of the analog input signal over said predetermined interval. 4. A method of successive approximation analog-to-digital conversion of a variable analog input signal, which comprises rapidly sampling the amplitude of the analog input signal an odd number of times during a predetermined time interval, comparing the value of each sample to a first predetermined reference value estimated to be the maximum value of a range in which the amplitude of said analog input signal lies in said predetermined time interval to obtain a binary value representing whether said sample value is above or below the first reference value, and using the majority of corresponding binary values of the odd number of samples as the binary value of the most significant bit (MSB) for the digital conversion; halving the reference value and comparing the value of each sample to the halved reference value and using the majority binary value obtained from the comparisons as the next MSB; and continuing the process of halving the reference value, comparing and taking the majority binary value as the value for each succeeding bit until the least significant bit is obtained for the digital conversion. 5. The method of claim 4, wherein said odd number of times of rapid sampling of the analog input signal in said predetermined time interval is at least three. 6. The method of claim 5, including repeating the process of successively sampling, comparing each sample with successively halved reference value, and taking the majority binary value for each set of samples relative to the respective halved reference value for each predetermined time interval, to obtain continuing conversions of the instantaneous amplitude of the analog input signal to digital form from MSB to LSB. 7. A successive approximation analog-to-digital (A/D) converter for converting a variable analog input signal to a digital format representative of the magnitude thereof, comprising: a successive approximation register (SAR) for generating a digital output in the form of a succession of binary values ranging from a most significant bit (MSB) of 2" to a least significant bit (LSB) of 2° in response to a succession of inputs thereto, where n+1 is the number of significant bits in the conversion, a comparator for supplying an input to said SAR based on a comparison of the instantaneous magnitude of said analog input signal to the magnitude of a reference signal, means for converting a succession of binary values to analog values as said reference signal to said comparator, and means for performing a majority vote of an odd number of binary values associated with each of said succession of binary values to provide a modified succession of binary values to said converting means. 8. The A/D converter of claim 7, including: means for rapidly sampling the magnitude of said analog input signal during a predetermined time interval as an input to said comparator to provide said odd number of binary values as the respective values of each of an odd number of successive ones of said samples relative to said reference signal delivery to said SAR for use in performing said majority vote. 9. The A/D converter of claim 7, wherein: said SAR comprises means for generating an uppermost limit of a reference range of magnitudes in digital format as said reference signal for comparison with said analog input signal by said comparator. 10. A successive approximation analog-to-digital (A/D) converter for generating a digital output representative of a variable analog input signal, comprising: means for supplying samples of the magnitude of an analog input signal relative to the maximum value of a reference range over a predetermined time interval as binary inputs to a successive approximation register (SAR); said SAR being adapted to adjust the reference range based on a succession of said binary inputs to more closely encompass the sampled magnitude of the analog input signal over said time interval for use in refining said digital output to better represent said analog input signal; and means for further adjusting said reference range by discarding samples having a binary value that differ from a norm established by a majority of the binary inputs during said time interval. 11. The A/D converter of claim 10, wherein said samples are supplied to provide an odd number of binary inputs of at least three in number to said SAR for each significant bit in a digital representation of the reference range, including successive adjustments of said range, for determination of said majority for each significant bit in said digital representation in said predetermined time interval. 12. The A/D converter of claim 11, including logic means coupled to said SAR for the determination of the majority binary value for each significant bit in the digital representation of the reference range in said predetermined time interval. 13. The A/D converter of claim 12, wherein said SAR has an effective digital content, after determination of the majority binary value for each significant bit in the digital representation of the reference range in said predetermined time interval, constituting said digital output representative of the variable analog input signal in that time interval.

Inventors: COOPER RUSSELL E, COOPER, RUSSELL, E.
Applicants: MICROCHIP TECH INC, MICROCHIP TECHNOLOGY INCORPORATED
Application year: 1998
Main classification: H03M1
IPC codes: H03M1