Improved differential amplifier constituted of bipolar transistors

Abstract: In a differential amplifier comprising a non-linear distortion compensating circuit including a differential emitter follower, and a first group of current sources having a first differential pair of transistors having bases receiving a pair of emitter currents of the differential emitter follower, respectively, so that the first group of current sources are controlled by the pair of emitter currents of the differential emitter follower, and a differential buffer including a second differential pair of transistors having bases receiving signals outputted from the non-linear distortion compensating circuit, respectively, there is provided a base current compensating circuit for supplying to emitter nodes of the differential emitter follower, a current for reducing a non-linear distortion caused by base currents of the transistors of the second differential pair in the differential buffer and the transistors of the first differential pair in the first group of current sources.

Description: Background of the Invention Field of the invention The present invention relates to a differential amplifier, and more specifically to a differential amplifier constituted of bipolar transistors. Description of related art Referring to Fig. 8, there is shown a circuit diagram illustrating one example of a prior art differential amplifier constituted of bipolar transistors. In brief, the shown differential amplifier includes a pair of NPN bipolar transistors Q 1 and Q 2 having bases connected to a pair of input terminals IN1 and IN2, respectively, between which a differential input voltage V IN is applied. Collectors of the transistors Q 1 and Q 2 are connected to a power supply voltage V CC through load resistors R 1 and R 2 , respectively. In addition, the collectors of the transistors Q 1 and Q 2 are connected to a pair of output terminals OUT1 and OUT2, respectively, from which a differential output voltage V OUT is obtained. Emitters of the transistors Q 1 and Q 2 are connected to ground through current sources I 1 and I 2 having a constant current I 0 , respectively. The emitters of the transistors Q 1 and Q 2 are connected to each other through an emitter feedback resistor R 3 . The differential amplifier as shown in Fig. 8, constituted of bipolar transistors and including the emitter feedback resistor, is used as a differential amplifier having a relatively wide input voltage range which can be approximately deemed to operate linearly. In addition, the shown differential amplifier also has another advantage that a gain precision can be easily obtained since a nominal gain is given by a ratio between the emitter feedback resistor and the load resistors. However, when the differential amplifier as shown in Fig. 8 is used as an input buffer in an analog-to-digital converter, since a high linearity is required, it is an ordinary practice to make improvement in order to elevate the linearity. Now, assuming R 1 =R 2 =1000Ω, R 3 =2000Ω and I 0 =0.25mA in the differential amplifier as shown in Fig. 8, the result of a "SPICE" (Simulation Program with Integrated Circuit Emphasis) simulation will be described in the following: Fig. 9 is a graph illustrating a relation between a differential input voltage V IN and a non-linear error V D in the differential amplifier as shown in Fig. 8. Here, V D is a difference between a differential output voltage V OUT =V OUT (V IN ) and a tangential line V L = V L (V IN ) in differential output voltage V OUT (V IN ) at the time of V IN = 0V. V D = V OUT (V IN ) - V L (V IN ) Accordingly, V D is indicative of the non-linearity in the differential output voltage V OUT . In the following, for purposes of convenience, this VD will be called a non-linear error. If the differential output voltage V OUT has a complete linearity in relation to the differential input voltage V IN , the non-linear error V D ceaselessly becomes zero. For purposes of convenience, assume that if the non-linear error V D is within the range of ±1mV, it can be deemed to be linear. In this case shown in Fig. 9, the range of the differential input voltage V IN permitting the linear operation becomes ±220mV. On the other hand, since the differential output voltage V OUT of the shown differential amplifier is cramped at ±500mV, and since the nominal gain is 1 (=2×R 1 /R 3 ), a maximum operable range of the differential input voltage V IN is also ±500mV. However, the shown differential amplifier can operate in a linear operating mode in only a range which is a half of the maximum operable range In addition, the gain at the differential input voltage V IN = 0V, namely, the inclination of the tangential line V L , is 0.86, which is smaller than the nominal gain 1 at some degree. The non-linear operation of the differential amplifier shown in Fig. 8 is mainly attributable to the circumstances that a base-emitter voltage (V BE ) of the bipolar transistors Q 1 and Q 2 non-linearly changes in relation to a collector current (I C ). Now, one prior art example for improving the linearity will be described with reference to Fig. 10, which is a circuit diagram illustrating another prior art example of the differential amplifier, which is constituted to improve the linearity of the differential amplifier shown in Fig. 8 and which is shown in Fig. 7(a) of T. Kumamoto et at, "A 10-bit 50MS/s 500mW A/D Converter with Differential-Voltage Subconverter", Technical Report of IEICE (The Institute of Electronics, Information and Communication Engineers (in Japan)), ED93-47, ICD93-46 (1994-06), pp17-22. In Fig. 10, elements corresponding to those shown in Fig. 8 are given the same Reference Numerals, and explanation will be omitted. In the differential amplifier shown in Fig. 10, diodes D 1 and D 2 are inserted between the power supply voltage V CC and the load resistors R 1 and R 2 , respectively. In this example, the non-linearity is compensated by the diodes D 1 and D 2 , so that a linear differential output voltage is obtained. Actually, assuming R 1 = R 2 = R 3 /2, the differential output voltage V OUT is expressed as follows: V OUT = (2 × R 1 / R 3 ) × (V IN - V BE1 + V BE2 ) + V D1 - V D2 = V IN - V BE1 + V BE2 + V D1 - V D2 = V IN where V BE1 , V BE2 , V D1 and V D2 are a base-emitter voltage of the bipolar transistors Q 1 and Q 2 , and a forward-direction voltage drop of the diodes D 1 and D 2 , respectively. In addition, V BE1 is substantially equal to V D1 (since a current flowing through Q 1 is substantially equal to a current flowing through D 1 ), and also V BE2 is substantially equal to V D2 . Thus, the result expressed by the above equation is obtained. Now, assuming R 1 =R 2 =1000Ω, R 3 =2000Ω and I 0 =0.25mA in the differential amplifier as shown in Fig. 10, the result of the SPICE simulation will be described in the following: Fig. 11 is a graph illustrating a relation between a differential input voltage V IN and a non-linear error V D in the differential amplifier as shown in Fig. 10. As seen from comparison between Fig. 9 and Fig. 11, the differential amplifier shown in Fig. 10 has a linearly operating range wider than that of the differential amplifier shown in Fig. 8. Namely, the differential amplifier shown in Fig. 10 has an improved linearity. In addition, the gain at the differential input voltage V IN = 0V, namely, the inclination of the tangential line V L , is 0.9808. which is slightly than the nominal gain 1 but is nearer to 1, in comparison with the differential amplifier shown in Fig. 8. However, since the differential amplifier shown in Fig. 10 includes the diode connected in series with the load resistor, a common-mode output potential drops by the forward-direction voltage drop (about 0.8V) of the diode, and therefore, when the power supply voltage is low, a next-stage circuit directly receiving the output of the differential amplifier becomes difficult to properly operate at a low power supply voltage. Referring to Fig. 12, there is shown a circuit diagram illustrating still another prior art example of the differential amplifier, which is shown in Japanese Patent Application Pre-examination Publication No. JP-A-57-160207, which corresponds to U.S. Patent 4,496,860. Also in EP 0 637 128 such a circuit is disclosed. In Fig. 12, elements corresponding to those shown in Fig. 8 are given the same Reference Numerals, and explanation will be omitted. The differential amplifier shown in Fig. 12 includes a non-linear distortion compensating circuit 101 provided as an input stage receiving a differential input voltage, and a differential buffer 102 constructed completely similarly to the differential amplifier shown in Fig. 8. The non-linear distortion compensating circuit 101 includes a pair of NPN bipolar transistors Q 3 and Q 4 having collectors connected directly to a power supply voltage V CC . Bases of the transistors Q 3 and Q 4 are connected to a pair of input terminals IN1 and IN2, respectively, between which a differential input voltage V IN is applied. Emitters of the transistors Q 3 and Q 4 are connected to the bases of the transistors Q 1 and Q 2 , respectively. The non-linear distortion compensating circuit 101 also includes another pair of NPN bipolar transistors Q 5 and Q 6 each having a base cross-connected to a collector of the other of the pair of NPN bipolar transistors Q 5 and Q 6 . The collectors of the NPN bipolar transistors Q 5 and Q 6 are connected to the emitters of the transistors Q 3 and Q 4 , respectively. Emitters of the transistors Q 5 and Q 6 are connected to ground through current sources I 3 and I 4 , respectively. The emitters of the transistors Q 5 and Q 6 are connected to each other through an emitter feedback resistor R 4 . In the differential amplifier shown in Fig. 12, a current of an emitter follower (the bipolar transistors Q 3 and Q 4 ) in the non-linear distortion compensating circuit 101 changes dependently upon the input differential voltage V IN (input signal), and a base-emitter voltage V BE of the bipolar transistors Q 3 and Q 4 changes dependently upon the change of the current of the emitter follower, with the result that the change of the base-emitter voltage V BE of the bipolar transistors Q 1 and Q 2 in the differential buffer 102 is canceled, so that a linear differential output voltage can be obtained. Actually, assuming R 1 = R 2 = R 3 /2 = R 4 /2, the differential output voltage V OUT of the differential amplifier shown in Fig. 12 is expressed as follows: V OUT = (2 × R 1 / R 3 ) × (V IN - V BE3 - V BE1 + V BE4 + V BE2 ) = V IN - V BE3 - V BE1 + V BE4 + V BE2 = V IN where V BE1 , V BE2 , V BE3 and V BE4 are a base-emitter voltage of the bipolar transistors Q 1 , Q 2 , Q 3 and Q 4 , respectively. In addition. V BE1 is substantially equal to V BE4 (since a current flowing through Q 1 is substantially equal to a current flowing through Q 4 ), and also V BE2 is substantially equal to V BE3 . Thus, the result expressed by the above equation is obtained. Differently from the differential amplifier shown in Fig. 10, since the differential amplifier shown in Fig. 12 has no drop in the common-mode output voltage, a next-stage circuit directly receiving the output of the differential amplifier becomes can properly operate at a low power supply voltage. In addition, the nominal gain is not necessarily required to be 1. For reference, the gain at the differential input voltage V IN = 0V, namely, the inclination of the tangential line V L , is 0.9718, which is slightly than the nominal gain 1. Actually, however, because of a base current of the bipolar transistors Q 1 , Q 2 , Q 3 and Q 4 which was ignored in the above mentioned equation, improvement of the linearity is not so good, and therefore, it has a disadvantage that the linearly operating range is narrow. Now, assuming R 1 =R 2 =1000Ω, R 3 =2000Ω and I 0 =0.25mA in the differential amplifier as shown in Fig. 12, the result of the SPICE simulation will be described in the following: Fig. 13 is a graph illustrating a relation between a differential input voltage V IN and a non-linear error V D in the differential amplifier as shown in Fig. 12. As shown in Fig. 13, the linearly operating range is about ±300mV, which cannot be said to be sufficiently wide. Next, influence of the base current will be described. V BE1 and V BE4 in this prior art differential amplifier shown in Fig. 12 are given by the following equations: V BE1 = V T × In (I C1 / I S ) V BE4 = V T × In [{(β / (β+1)} × (I C6 + I B2 + I B5 ) / I S ] = V T × In [{(β / (β+1)} × (I C1 + (2/β) × I C2 } / I S ] where V T is a thermal voltage (V T = kT/q; k = Boltzmann constant, T = absolute temperature, q = elementary charge), I S is a saturation current, I C1 to I C6 and I B1 to I B6 are a collector current and a base current of the transistors Q 1 to Q 6 , and β is a current gain. IN addition, since the differential amplifier shown in Fig. 12 has a current mirror structure, a relation of I C6 = I C1 and I B2 = I B5 holds. By using this relation, the equation was modified. The currents I C1 to I C6 change upon the change of the differential input voltage V IN , but if the change of V BE1 is equal to the change of V BE4 , the linear operation of the circuit is obtained. Actually, however, since the base currents exist, it would be understood from the above equation that the change of V BE1 never becomes equal to the change of V BE4 . Summary of the Invention Accordingly, it is an object of the present invention to provide a differential amplifier which has overcome the above mentioned defects of the conventional ones. Another object of the present invention is to provide a differential amplifier having a widened linearly operating range and having a high common-phase output potential to permit a next-stage circuit to operate at a low power supply voltage. The above and other objects of the present invention are achieved in accordance with the present invention by a differential amplifier as defined in claim 1. Further embodiments of the invention are claimed in the dependent claims. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Fig. 1 is a circuit diagram illustrating a basic construction of the differential amplifier in accordance with the present invention; Fig. 2 is a circuit diagram of a first embodiment of the differential amplifier shown in Fig. 1; Fig. 3 is a graph illustrating a relation between a differential input voltage V IN and a non-linear error V D in the differential amplifier shown in Fig. 2, based on the SPICE simulation; Fig. 4 is a circuit diagram of a second embodiment of the differential amplifier shown in Fig. 1; Fig. 5 is a graph illustrating a relation between a differential input voltage V IN and a non-linear error V D in the differential amplifier shown in Fig. 4, based on the SPICE simulation; Fig. 6 is a circuit diagram of a third embodiment of the differential amplifier shown in Fig. 1; Fig. 7 is a graph illustrating a relation between a differential input voltage V IN and a non-linear error V D in the differential amplifier shown in Fig. 6, based on the SPICE simulation; Fig. 8 is a circuit diagram illustrating one example of the prior art differential amplifier constituted of bipolar transistors; Fig. 9 is a graph illustrating a relation between a differential input voltage V IN and a non-linear error V D in the differential amplifier shown in Fig. 8, based on the SPICE simulation; Fig. 10 is a circuit diagram illustrating another example of the prior art differential amplifier constituted of bipolar transistors; Fig. 11 is a graph illustrating a relation between a differential input voltage V IN and a non-linear error V D in the differential amplifier shown in Fig. 10, based on the SPICE simulation; Fig. 12 is a circuit diagram illustrating still another example of the prior art differential amplifier constituted of bipolar transistors; and Fig. 13 is a graph illustrating a relation between a differential input voltage V IN and a non-linear error V D in the differential amplifier shown in Fig. 12, based on the SPICE simulation. Description of the Preferred embodiments Now, embodiments of the differential amplifier in accordance with the present invention will be described with reference to the accompanying drawings. Referring to Fig. 1, there is shown a circuit diagram illustrating a basic construction of the differential amplifier in accordance with the present invention. In Fig. 1, elements corresponding to those shown in Fig. 12 are given the same Reference Numerals. The differential amplifier shown in Fig. 1 includes a non-linear distortion compensating circuit 1 including a differential emitter follower and a first group of current sources having a first differential pair of transistors having bases receiving a pair of emitter currents of the differential emitter follower, respectively, so that the first group of current sources are controlled by the pair of emitter currents of the differential emitter follower, and a differential buffer 2 including a second differential pair of transistors having bases receiving signals outputted from the non-linear distortion compensating circuit 1, respectively. Furthermore, the non-linear distortion compensating circuit 1 includes a base current compensating circuit 3 for supplying at least a portion of each of base currents of the transistors of the second differential pair in the differential buffer 2 and the transistors of the first differential pair in the first group of current sources. More specifically, the non-linear distortion compensating circuit 1 includes a differential pair of NPN bipolar transistors Q 3 and Q 4 having collectors connected directly to a power supply voltage of a predetermined potential (V CC ). Bases of the transistors Q 3 and Q 4 are connected to a pair of input terminals IN1 and IN2, respectively, between which a differential input voltage V IN is applied. The non-linear distortion compensating circuit 101 also includes an NPN bipolar transistor Q 5 having a collector connected to an emitter of the transistor Q 3 and a base connected to an emitter of the transistor Q 4 , and an NPN bipolar transistor Q 6 having a collector connected to an emitter of the transistor Q 4 and a base connected to an emitter of the transistor Q 3 , a resistor R 4 connected between an emitter of the NPN bipolar transistor Q 5 and an emitter of the NPN bipolar transistor Q 6 , a constant current source I 3 connected between the emitter of the NPN bipolar transistor Q 5 and the ground, a constant current source I 4 . connected between the emitter of the NPN bipolar transistor Q 6 and the ground, a current source I X1 connected between the emitter of the NPN bipolar transistor Q 3 and the power supply voltage V CC , and a current source I X2 connected between the emitter of the NPN bipolar transistor Q 4 and the power supply voltage V CC . The differential emitter follower is constituted of the transistors Q 3 and Q 4 . The first group of current sources are constituted of the transistors Q 5 and Q 6 and the constant current sources I 3 and I 4 . The base current compensating circuit 3 is constituted of the current sources I X1 and I X2 . On the other hand, the differential buffer 2 includes a differential pair of NPN transistors Q 1 and Q 2 having bases connected to receive emitter potentials of the transistors Q 3 an Q 4 , respectively, a pair of resistors R 1 and R 2 connected between collectors of the NPN transistors Q 1 and Q 2 and the power supply voltage V CC , respectively, a resistor R 3 connected between an emitter of the transistor Q 1 and an emitter of the transistor Q 2 , a constant current source I 1 connected between an emitter of the transistor Q 1 and the ground, and a constant current source I 2 connected between an emitter of the transistor Q 2 . Thus, the collectors of the transistors Q 1 and Q 2 are supplied through the resistors R 1 and R 2 with a predetermined potential (V CC ). Next, an operation of the differential amplifier constructed as mentioned above will be described. In brief, a differential input voltage V IN applied between the bases of the transistors Q 3 and Q 4 is supplied between the bases of the transistors Q 1 and Q 2 while the potential difference is maintained as it is, and then, is multiplied by the nominal gain of {(R 1 +R 2 )/R 3 } so that it is outputted between the collectors of the transistors Q 1 and Q 2 as the differential output voltage V OUT . Next, a linearity of the differential output voltage V OUT to the differential input voltage V IN will be described. As mentioned hereinbefore, since V OUT = {(R 1 + R 2 ) / R 3 } × (V IN - V BE3 - V BE1 + V BE4 + V BE2 ) the following equation holds as regards a change amount: ΔV OUT = A × (ΔV IN - ΔV BE3 - ΔV BE1 + ΔV BE4 + ΔV BE2 ) where A = (R 1 + R 2 ) / R 3 , and ΔV OUT , ΔV IN , ΔV BE3 , ΔV BE1 , ΔV BE4 and ΔV BE2 are a change amount of V OUT , V IN , V BE3 , V BE1 , V BE4 and V BE2 , respectively. Accordingly, in order to establish the linearity, it is sufficient if a relation of ΔV BE1 = ΔV BE4 and ΔV BE2 = ΔV BE3 holds. Since ΔV BE4 = V T × ln {I C1 + ΔI C + (2/β) × (I C2 - ΔI C ) - I X - ΔI X } - V T × In {I C1 + (2/β) × I C2 - I X } and ΔV BE1 = V T × ln (I C1 + ΔI C ) - V T × ln I C1 a linear operation is realized by giving I X which makes V BE4 equal to V BE1 . Here, it is assumed that ΔI C = ΔI C1 = -ΔI C2 . Since a similar relation holds in connection with ΔV BE2 and ΔV BE3 , explanation will be omitted. Embodiment 1 Referring to Fig. 2, there is shown a circuit diagram of a first embodiment of the differential amplifier shown in Fig. 1. In Fig. 2, elements corresponding to those shown in Fig. 1 are given the same Reference Numerals, and explanation will be omitted for simplification of description. In order to make the current sources I X1 and I X2 shown in Fig. 1 equal to a sum of base currents of the transistors Q 1 and Q 6 and a sum of base currents of the transistors Q 2 and Q 5 , respectively, the base current compensating circuit 3 in this first embodiment includes, as shown in Fig. 2, PMOS transistors MP 1 to MP 4 controlled by base currents of transistors Q 7 and Q 8 , a current control circuit composed of transistors Q 9 and Q 10 and a resistor R 5 for supplying currents to the transistors Q 7 and Q 8 , and emitter follower transistors Q 11 and Q 12 receiving the differential input voltage, for controlling the current control circuit composed of the transistors Q 9 and Q 10 and the resistor R 5 . Specifically, the input terminal IN1 is connected to a base of the transistor Q 11 , and the input terminal IN2 is connected to a base of the transistor Q 12 . Collectors of the transistors Q 11 and Q 12 are connected to the power supply voltage V CC . An emitter of the transistor Q 11 is connected to a base of the transistor Q 9 and also connected to the ground through a constant current source I 7 . An emitter of the transistor Q 12 is connected to a base of the transistor Q 10 and also connected through a constant current source I 8 to the ground. A collector of the transistor Q 9 is connected to an emitter of the transistor Q 7 , and an emitter of the transistor Q 9 is connected through a constant current source I 5 to the ground. A collector of the transistor Q 10 is connected to an emitter of the transistor Q 8 , and an emitter of the transistor Q 10 is connected through a constant current source I 6 to the ground, and also connected through the resistor R 5 to the emitter of the transistor Q 9 . Collectors of the transistors Q 7 and Q 8 are connected to the power supply voltage V CC . A base of the transistor Q 7 is connected to a drain and a gate of the PMOS transistor MP 1 and a gate of the PMOS transistor MP 2 . Sources of the PMOS transistors MP 1 and MP 2 are connected to the power supply voltage V CC . A drain of the PMOS transistor MP 2 is connected to the bases of the transistors Q 1 and Q 6 . Therefore, the PMOS transistors MP 1 and MP 2 constitute a current mirror circuit. A base of the transistor Q 8 is connected to a drain and a gate of the PMOS transistor MP 3 and a gate of the PMOS transistor MP 4 . Sources of the PMOS transistors MP 3 and MP 4 are connected to the power supply voltage V CC . A drain of the PMOS transistor MP 4 is connected to the bases of the transistors Q 2 and Q 5 . Therefore, the PMOS transistors MP 3 and MP 4 constitute a current mirror circuit. Here, all the constant current sources I 1 to I 8 have the same current value I 0 . For example, I 0 = 0,25mA, R 1 =R 2 =1kΩ, and R 3 =R 4 =R 5 =2kΩ. Now, an operation of the differential amplifier constructed as mentioned above will be described. Since the base current of the transistor Q 8 is substantially equal to the base current of the transistor Q 2 , if the current mirror circuit formed of the PMOS transistors MP 3 and MP 4 is so designed that a current equal to a double of the current flowing through the PMOS transistor MP 3 , flows through the PMOS transistor MP 4 (magnifying power of 2), the PMOS transistor MP 4 can supply the base currents of the transistors Q 2 and Q 5 , so that the current flowing through the transistor Q 4 is no longer required to supply the base currents of the transistors Q 2 and Q 5 . Accordingly, ΔV BE4 is expressed by the following equation: ΔV BE4 = V T × ln {I C1 + ΔI C + (2/β) × (I C2 - ΔI C ) - I X - ΔI X ) - V T × ln {I C1 + (2/β) × I C2 - I X } = V T × ln (I C1 + ΔI C ) - V T × ln I C1 = ΔV BE1 Similarly, it becomes ΔV BE3 = ΔV BE2 . Thus, a linear operation is realized. Referring to Fig. 3, there is shown a graph illustrating a relation between a differential input voltage V IN and a non-linear error V D in the differential amplifier shown in Fig. 2, based on the SPICE simulation. As shown in Fig. 3, the linearly operating range was extended to ±450mV. In addition, the gain was 0.9789, which is larger than that obtained in the prior art differential amplifier shown in Fig. 12. Incidentally, if the current value of the constant current sources I 5 and I 6 is halved (to I 0 /2), and furthermore, if the PMOS transistor current mirror circuits are so designed that the output current is four times the input current (magnifying power of 4), a similar effect can be obtained. In addition, if the current value of the constant current sources I 3 and I 4 are made to I 0 /k, and also if the resistance of the resistor R 4 is made to k times, and if the magnifying power of the PMOS transistor current mirror circuits is suitably set so as to supply necessary base currents, a similar effect can be obtained. Furthermore, the current value of the constant current sources I 7 and I 8 can be changed from I 0 . In this case, it is sufficient if the size ratio of the bipolar transistors is suitably changed if necessary. Moreover, it would be apparent that the transistors Q 11 and Q12 of the emitter follower can be constructed similarly to the non-linear distortion compensating circuit shown in Fig. 12, so as to realize the matching of the base currents. Since modifications in the size of the constituents and in the ratio of the currents are a matter of design to persons skilled in the art, a further explanation will be omitted. In the above mentioned equation, the output resistance of the current sources I X1 and I X2 was deemed to be infinite. However, in this embodiment, the current sources I X1 and I X2 have a non-negligible finite output resistance. When the current gain β is actually not the constant but varies upon the current value and the collector-emitter voltage, it is in some cases that a more excellent linearity can be obtained when the current sources I X1 and I X2 have a finite output resistance, than when the current sources I X1 and I X2 have an infinite output resistance. However, if it is desired to cause the current sources I X1 and I X2 to have a large output resistance enough to be deemed to be infinite, it is possible to use a well-known manner in which a drain of each of the PMOS transistors MP 2 and MP 4 is cascade-connected with a PMOS transistor having a gate suitably biased, so that the output resistance of the current sources I X1 and I X2 is enlarged. This is true in embodiments which will be described hereinafter. Embodiment 2 Referring to Fig. 4, there is shown a circuit diagram of a second embodiment of the differential amplifier shown in Fig. 1. In Fig. 4, elements corresponding to those shown in Fig. 1 are given the same Reference Numerals, and explanation will be omitted for simplification of description. The base current compensating circuit 3 in this second embodiment, namely, the current sources I X1 and I X2 shown in Fig. 1, include an NPN transistor Q 13 having a collector connected to the power supply voltage V CC and an emitter connected through a constant current source I 9 to the ground, and a current mirror circuit composed of three PMOS transistors MP 5 to MP 7 having sources connected to the power supply voltage V CC . A base of the NPN transistor Q 13 is connected to a gate and a drain of the PMOS transistor MP 5 and a gate of each of the PMOS transistors MP 6 and MP 7 . A drain of the PMOS transistor MP 6 is connected to the bases of the transistors Q 1 and Q 6 , and a drain of the PMOS transistor MP 7 is connected to the bases of the transistors Q 2 and Q 5 . Since a base current of the transistor Q 13 is substantially equal to the base current of the transistor Q 2 when the different input voltage V IN is 0 (zero), if the current mirror circuit of the PMOS transistors MP 5 to MP 7 is designed to have the magnifying power of 4 so that the current flowing through each of PMOS transistors MP 6 and MP 7 is equal to a double of the current flowing through PMOS transistor MP 5 , it is possible to supply a constant amount portion of the base currents of the transistors Q 2 and Q 5 and a constant amount portion of the base currents of the transistors Q 1 and Q 6 from the base current compensating circuit 3 of the second embodiment. Accordingly, ΔV BE4 is expressed by the following equation: ΔV BE4 = V T × In {I C1_0 + ΔI C + (2/β) × (I C2_0 - ΔI C ) - I X - ΔI X - V T × ln {I C1_0 + (2/β) × I C2_0 - I X } = V T × In {I C1_0 + ΔI C + (2/β) × (I C2_0 - ΔI C )} - V T × ln {I C1_0 + (2/β) × I C2_0 } = V T × In (I C1_0 + ΔI C ) - V T × ln I C1_0 = ΔV BE1 where I C1_0 is I C1 when V IN is zero and I C2_0 is I C2 when V IN is zero, and it is deemed to be ΔI X =0 under assumption that I X =(4/β) × I C1_0 , I C2_0 = I C1_0 , and the output resistance is infinite. Similarly, it becomes ΔV BE3 = ΔV BE2 . Thus, a linear operation is realized. Referring to Fig. 5, there is shown a graph illustrating a relation between a differential input voltage V IN and a non-linear error V D in the differential amplifier shown in Fig. 4, based on the SPICE simulation. As shown in Fig. 5, the linearly operating range was extended to ±480mV. In addition, the gain was 0.9783, which is larger than that obtained in the prior art differential amplifier shown in Fig. 12. In this second embodiment, the number of the constant current sources required to construct the current sources I X1 and I X2 is reduced to one from four required in the first embodiment. Therefore, the second embodiment can realize a low power consumption in comparison with the first embodiment. Embodiment 3 Referring to Fig. 6, there is shown a circuit diagram of a third embodiment of the differential amplifier shown in Fig. 1. In Fig. 6, elements corresponding to those shown in Fig. 1 are given the same Reference Numerals, and explanation will be omitted for simplification of description. The current sources I X1 and I X2 of the base current compensating circuit 3 in this third embodiment are constituted of only resistors R X1 and R X2 , respectively. Accordingly, since the base current compensating circuit 3 in the third embodiment has no constant current source, the third embodiment can realize a low power consumption in comparison with the first and second embodiments. Now, an operation of the third embodiment will be described. Each of the resistors R X1 and R X2 can be deemed to be a current source which supplies a current I X_0 when the differential input voltage V IN is 0 (zero) and which has an output resistance R X . Here, R X is a resistance of the resistors R X1 and R X2 . Therefore, in the above mentioned equation giving ΔV BE4 , if the situation when the differential input voltage V IN is 0 (zero) is considered to be as a reference condition, ΔI X is approximately expressed as follows: ΔI X = V IN / (2 × R X ) In addition, since the differential input voltage V IN is approximately equal to R 3 × ΔI C , it becomes ΔI X = (R 3 × ΔI C ) / (2 × R X ) Accordingly, if the resistance value R X is determined to fulfill the following relation: I X_0 = {4/β + R 3 / (2 × R X )}} × I C1_0 it becomes ΔV BE4 = ΔV BE1 Referring to Fig. 7, there is shown a graph illustrating a relation between a differential input voltage V IN and a non-linear error V D in the differential amplifier shown in Fig. 6, based on the SPICE simulation. As shown in Fig. 7, the linearly operating range was extended to ±470mV. In addition, the gain was 0.9780, which is larger than that obtained in the prior art differential amplifier shown in Fig. 12. As mentioned above, the differential amplifier in accordance with the present invention includes the base current compensating circuit for supplying at least a portion of each of base currents of the transistors of the second differential pair in the differential buffer and the transistors of the first differential pair in the first group of current sources. With this arrangement, a current for reducing a non-linear distortion caused by base currents of said transistors of said second differential pair in said differential buffer and said transistors of said first differential pair in said first group of current sources, is supplied from the base current compensating circuit to said transistors of said second differential pair in said differential buffer and said transistors of said first differential pair in said first group of current sources, as a base current. Therefore, the differential amplifier operates linearly, and a widened linearly operating range and a high common-mode output potential are simultaneously realized. The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made,

Claims: A differential amplifier comprising a non-linear distortion compensating circuit (1) and a differential buffer (2), said non-linear distortion compensating circuit (1) including: a differential pair constituted of first and second transistors (Q3 and Q4) having collectors connected to a predetermined potential (VCC) and bases connected to a pair of input terminals (IN1 and IN2), respectively, for receiving a differential input voltage (VIN); a third transistor (Q5) having a collector connected to an emitter of said first transistor (Q3), a base connected to an emitter of said second transistor (Q4), and an emitter connected through a first constant current source (I3) to the ground; a fourth transistor (Q6) having a collector connected to the emitter of said second transistor (Q4), a base connected to the emitter of said first transistor (Q3), and an emitter connected through a second constant current source (I4) to the ground; and a first resistor (R4) connected between an emitter of said third transistor (Q5) and an emitter of said fourth transistor (Q6), and said differential buffer (2) including a second differential pair constituted of fifth and sixth transistors (Q1 and Q2) having bases connected to the emitter of said first and second transistors (Q3 and Q4) of said non-linear distortion compensating circuit (1), respectively, a collector of said fifth and sixth transistors (Q1 and Q2) constituting a differential output of the differential amplifier, and characterized in that the differential amplifier further includes a base current compensating circuit (3) including: a third current source (IX1) connected between the emitter of said first transistor (Q3) and said predetermined potential (VCC), for supplying a portion of base currents of said fifth and fourth transistors (Q1 and Q6); and a fourth current source (IX2) connected between the emitter of said second transistor (Q4) and said predetermined potential (VCC), for supplying a portion of base currents of said sixth and third transistors (Q2 and Q5). A differential amplifier claimed in Claim 1 wherein said differential buffer (2) further includes: a second resistor (R1) connected between the collector of said fifth transistor (Q1) and said predetermined potential (VCC), a third resistor (R2) connected between the collector of said sixth transistor (Q2) and said predetermined potential (VCC), a fifth constant current source (I1) connected between the emitter of said fifth transistor (Q1) and the ground; a sixth constant current source (I2) connected between the emitter of said sixth transistor (Q2) and the ground; and a fourth resistor (R3) connected between the emitter of said fifth transistor (Q1) and the emitter of said sixth transistor (Q2). A differential amplifier claimed in Claim 1 or 2 wherein said base current compensating circuit (3) is internally provided in said non-linear distortion compensating circuit (1). A differential amplifier claimed in any of Claim 1 to 3 wherein said base current compensating circuit includes: a differential pair constituted of seventh and eighth transistors (Q11 and Q12) having collectors connected to said predetermined potential (VCC) and bases connected to said pair of input terminals (IN1 and IN2), respectively, an emitter of said seventh and eighth transistors (Q11 and Q12) being connected through seventh and eighth current sources (I7 and I8) to the ground, respectively; a ninth transistor (Q9) having a base connected to the emitter of said seventh transistor (Q11) and an emitter connected through a ninth current source (I5) to the ground; a tenth transistor (Q10) having a base connected to the emitter of said eighth transistor (Q12) and an emitter connected through a tenth current source (I6) to the ground; a fifth resistor (R5) connected between the emitter of said ninth transistor (Q9) and the emitter of said tenth transistor (Q10); an eleventh transistor (Q7) having an emitter connected to a collector of said ninth transistor (Q9) and a collector connected to said predetermined potential (VCC); a twelfth transistor (Q8) having an emitter connected to a collector of said tenth transistor (Q10) and a collector connected to said predetermined potential (VCC); a first current mirror circuit constituted of first and second PMOS transistors (MP1 and MP2) having sources connected to said predetermined potential (VCC), a drain and a gate of said first PMOS transistor (MP1) and a gate of said second PMOS transistor (MP2) being connected to a base of said eleventh transistor (Q7), and a drain of said second PMOS transistor (MP2) being connected to the emitter of said first transistor (Q3), so that said second PMOS transistor (MP2) constitutes said third current source (IX1); and a second current mirror circuit constituted of third and fourth PMOS transistors (MP3 and MP4) having sources connected to said predetermined potential (VCC), a drain and a gate of said third PMOS transistor (MP3) and a gate of said fourth PMOS transistor (MP4) being connected to a base of said twelfth transistor (Q8), and a drain of said fourth PMOS transistor (MP4) being connected to the emitter of said second transistor (Q4), so that said fourth PMOS transistor (MP4) constitutes said fourth current source (IX2), whereby currents supplied from said third and fourth current sources (IX1 and IX2) become equal to a sum of base currents of said fifth and fourth transistors (Q1 and Q6) and a sum of base currents of said sixth and third transistors (Q2 and Q5), respectively. A differential amplifier claimed in any of Claim 1 to 3 wherein said base current compensating circuit includes: a seventh transistor (Q13) having a collector connected to said predetermined potential (VCC) and an emitter connected through a seventh current source (I9) to the ground; and a current mirror circuit constituted of first, second and third PMOS transistors (MP5, MP6 and MP7) having sources connected to said predetermined potential (VCC), a drain and a gate of said first PMOS transistor (MP5) and a gate of said second and third PMOS transistors (MP6 and MP7) being connected to a base of said seventh transistor (Q13), and a drain of said second PMOS transistor (MP6) being connected to the emitter of said first transistor (Q3) so that said second PMOS transistor (MP6) constituting said third current source (IX1), and a drain of said third PMOS transistor (MP7) being connected to the emitter of said second transistor (Q4), so that said third PMOS transistor (MP7) constitutes said fourth current source (IX2). A differential amplifier claimed in any of Claim 1 to 3 wherein said third current source (IX1) in said base current compensating circuit is a fifth resistor (Rx1) connected between the emitter of said first transistor (Q3) and said predetermined potential (VCC), and said fourth current source (IX2) in said base current compensating circuit is a sixth resistor (Rx2) connected between the emitter of said second transistor (Q4) and said predetermined potential (VCC). A differential amplifier claimed in Claim 1 or 2 wherein said base current compensating circuit includes a pair of resistors provided to comply with said differential emitter follower in said non-linear distortion compensating circuit. A differential amplifier comprising: a non-linear distortion compensating circuit including a differential emitter follower, and a first group of current sources having a first differential pair of transistors having bases receiving a pair of emitter currents of said differential emitter follower, respectively, so that said first group of current sources are controlled by said pair of emitter currents of said differential emitter follower; a differential buffer including a second differential pair of transistors having bases receiving signals outputted from said non-linear distortion compensating circuit, respectively, and a base current compensating circuit for supplying to emitter nodes of said differential emitter follower a current for reducing a non-linear distortion caused by base currents of said transistors of said second differential pair in said differential buffer and said transistors of said first differential pair in said first group of current sources. A differential amplifier claimed in Claim 8 wherein said base current compensating circuit is internally provided in said non-linear distortion compensating circuit. A differential amplifier claimed in Claim 8 or 9 wherein said non-linear distortion compensating circuit includes a second group of current sources controlled to be ceaselessly equal to said base currents of said transistors of said second differential pair in said differential buffer. A differential amplifier claimed in Claim 8 or 9 wherein said base current compensating circuit includes a current mirror circuit for supplying a predetermined base current to said transistors of said second differential pair in said differential buffer. A differential amplifier claimed in Claim 11 wherein said current mirror circuit has a magnifying power predetermined for eliminating a non-linear distortion caused by said base current. A differential amplifier claimed in Claim 8 or 9 wherein said base current compensating circuit supplies a constant current for eliminating a non-linear distortion caused by said base currents of said transistors of said second differential pair in said differential buffer and said transistors of said first differential pair in said first group of current sources. A differential amplifier claimed in Claim 8 or 9 wherein said base current compensating circuit includes a pair of resistors provided to comply with said differential emitter follower in said non-linear distortion compensating circuit.

Inventors: SUGAWARA MICHINORI, SUGAWARA, MICHINORI, SUGAWARA, MICHINORI, C/O NEC CORPORATION
Applicants: NEC ELECTRONICS CORP, NEC ELECTRONICS CORPORATION
Application year: 1998
Main classification: H03F1
IPC codes: H03F1, H03F3