Sensor with thermal compensation network

Abstract: A capacitive transducer (10) which provides an output voltage in response to the application of a mechanical stimulus such as pressure or acceleration includes a signal conditioning integrated circuit (12) to which are connected a variable capacitor (C VAR ), a reference capacitor (C REF ), a linear correction capacitor (C LIN ) as well as an integrating capacitor (C INT ) and associated filtering components. The linear correction capacitor (C LIN ) is used to offset a fixed parasitic charge associated with the variable capacitor. Any net error charge appearing on a detect, common node (pin 4) between the variable capacitor and the reference capacitor is cancelled out by means of an analog feedback network (22). In a modified embodiment a thermal compensation network (40) allows for correction for thermal error at a second temperature without having any affect at a first temperature.

Description: Background of the Invention This invention relates generally to sensors having variable capacitors as sensing elements and more particularly to signal conditioning electronics for providing an improved linear output voltage versus the application of a mechanical stimulus such as pressure or acceleration. A signal conditioning circuit of this type is shown and described in U.S. Patent No. 4,982,351, assigned to the assignee of the present invention. In that patent, a condition responsive element such as a capacitive pressure transducer having a pressure responsive diaphragm for varying transducer capacitance within a selected range in response to variations in pressure forces applied to the diaphragm is shown connected to a reference capacitor in a charge locked loop relation having a common node for forming a capacitance to voltage converter circuit which is ratiometric with respect to supply voltage to vary output voltage within a selected range in response to variation in transducer capacitance in a corresponding range. An array of switches cycles the voltage across the transducer and reference capacitors with opposite transitions with a predetermined frequency so that change in transducer capacitance results in a differential voltage at the common node. That voltage is then amplified to drive a current source-sink network to adjust the sensor output voltage and, by a feedback path, to restore a balanced condition at the node, thereby to maintain the sensor output voltage as a function of the transducer capacitance. The above circuit has been widely used with various capacitive transducers including pressure and acceleration responsive transducers and provides a nearly linear output voltage. Sensors of this type typically have a total accuracy within a few percent of full scale output voltage. As usage of such sensors increase, higher accuracy as well as lower cost are continuously sought after. Some error in the circuit is related to the feedback circuit which uses a flip flop latch in which a specified voltage change, positive or negative, is applied to the variable capacitor to offset any error change in the common node. Using this digital approach allows minimization but not elimination of the error charge since it is limited by the incremental charge applied by the digital system. Additionally, a certain amount of non-linearity is found and evidences itself as a parasitic capacitor in parallel with the variable capacitor. US 5,241,850 discloses a temperature-compensating offset calibration means comprising two opposite bridge junctions, each having a thermistor and a temperature independent resistor, the bridge elements being connected by a potentiometer. The potentiometer output changes as the balance of the bridge changes with temperature. The setting of the potentiometer can be adjusted so that an appropriate temperature dependent signal is obtained, that signal being used to compensate for changes in offset in the output signal which result from changes in sensor temperature. Summary of the Invention The present invention provides a sensor according to claim 1. The present invention also provides a method according to claim 5. According to a feature of the present invention, compensation for capacitive sensor error over temperature is provided comprising a thermal compensation circuit utilizing a resistive bridge sensor network which is calibrated at a first temperature, such as room temperature, so that thermal compensation adjustment produces no sensor output change. Thermal compensation adjustments at a second temperature can then correct output error caused by temperature change without affecting the output at the first temperature. Description of the Drawings Other objects, advantages and details of the novel and improved sensor appears in the following detailed description of a preferred embodiment of the invention, the detailed description referring to the drawings in which: Fig. 1 is a block diagram of a sensor comprising a variable capacitor, integrated circuit and associated components shown for illustrative purposes; Fig. 2 is a timing diagram for the integrated circuit of Fig. 1; Fig. 3 is a simplified block diagram illustrating a linearity improvement feature and Fig. 4 is a simplified block diagram illustrating a thermal error compensation feature of an embodiment of the invention. Description of the Preferred Embodiment Referring to Fig. 1, numeral 10 indicates a sensor which is shown to include a condition or mechanical stimulus responsive means 11 such as an accelerometer, a pressure sensor, a position sensor or the like, which includes a variable capacitor C VAR . Variable capacitor C VAR , along with a reference capacitor C REF , are connected to signal conditioning circuit means in the form of a calibrated capacitive conditioner integrated circuit 12. With regard to integrated circuit 12, for the purpose of the following description. the resistor value for R is 10K ohms nominal. More specifically, one side of the variable capacitor is connected to variable (VAR) pin 6 of circuit 12 and one side of reference capacitor C REF is connected to reference (REF) pin 2 of circuit 12. The other sides of the capacitors are connected to a detect (DET) pin 4. Internally of circuit 12, pin 4 is connected through a 0.1R resistor to a charge comparator 14 with a phase switch A connected across comparator 14. The output of comparator 14 is connected to a voltage to current stage 16 through a D-latch flip-flop 18 via a switch SW3 or directly via switch SW3. Switches SW3, SW3 , along with SW1, SW1 and SW2, SW2 to be discussed below. are one time programmable switches. The output of the voltage to current stage 16 is connected through a phase switch C to the integrator buffer 20 and to integrator (INT) pin 8 which in turn is connected to an external integrating capacitor C INT . Buffer 20 output is connected to feedback network 22 comprising feedback resistors RF3. RF2. RF1 and switches SW1 . SW1 to pin VAR (pin 6) through a phase switch B . Switch SW1 or SW1 is programmed to be closed depending on the level of sensitivity desired. Another programmable option is provided utilizing switches SW2. SW2 . In the default or normal operational, mode switch SW2 is closed connecting the output of integrator buffer 20. through a 2.0R resistor to the positive input of output amplifier 24 whose output is connected to (OUT) pin 10 and to (FLT) pin 9 which in turn is connected to an external filter capacitor C FLT1 . The negative input of output amplifier 24 is connected through a 2.0R resistor to an attenuated supply voltage VDD/3 and through a 2.0R resistor to the output of amplifier 24. This arrangement provides an output voltage which is related to capacitor C VAR as described infra. If desired. the change in output voltage can be inverted by programming switch SW2 to be closed instead of switch SW2 . In this arrangement the output of buffer 20 is connected through a 2.0R resistor to the negative input of amplifier 26 whose positive input is connected to an attenuated supply voltage V DD 5/12. The output is also fed back to the negative input through a 2.0R resistor. Reference pin 2 is connected through a phase B switch to a programmable voltage divider in the form of an 10 bit gain DAC between 0.8 V DD and V SS (where Vss is defined as 0 volts) and through a phase B switch to a reference voltage, i.e., through a 0.33R resistor to supply voltage V DD . Variable pin 6 is connected though a phase B switch to another programmable voltage in the form of an 11 bit bias DAC between V DD and 0.2 V DD and through a phase B switch to the feedback network as described above. Timing signals A, B, B , C are generated internally utilizing oscillator 28 and phase logic 30. In their high and low states. as shown in Fig. 2, these signals will close and open their respective switches. Switches SW1, SW1 , SW2, SW2 , SW3, SW3 and the gain and bias DAC's are coupled to volatile - non-volatile memory 34. These functions are calibrated utilizing (DAT) pin 11, (CLK) pin 12 and (PGM) pin 13. Calibration consists of setting on-chip switches, testing circuit performance, iterating the first two steps and finally storing the final switch settings in a reliable, non-volatile memory. A shield generator is connected to shield pins 3 and 5 and provides a voltage source equal to the threshold voltage present at the (DET) pin 4 during the charge reference phase (approximately V DD/2 ) to be discussed. The shield voltage guards the conductor runs connected to pin 4 in a known manner. Pin 7 (VSS) provides both an analog ground and digital ground while pin 14 (VDD) is for connection to a voltage source. Pin 14 is connected to terminal VDD of connector 36 with a filter capacitor C1 connected across terminals VDD and VSS. Terminal OUT of connector 36 is connected to pin 10 through resistor R1 of greater than 10 ohms, filter capacitor C2 and a voltage divider comprising a pull-up resistor R2 of greater than 1.8K ohms and a pull-down resistor R3 of greater than 1.8K ohms. Capacitor C FLT2 is connected across (VDD) pin 14 and (FLT) pin 9. According to a feature to be described, an external capacitor C LIN is connected externally to (LIN) pin 1 and internally through a phase B switch to voltage VF of the feedback network and through a phase B switch to the voltage V BIAS . With the addition of the external components described, IC 12 converts small capacitance changes to large changes in output voltage. The input capacitance varies in response to the application of the mechanical stimulus, e.g., pressure, acceleration. and the like. Operation of circuit 12 can be broken down into three phases. The first phase is a charge reference phase in which the phase logic of the phase switches is reflected in Fig. 1. During this phase a known quantity of charge is stored on the plates of reference capacitor C REF and transducer capacitor C VAR . This is accomplished by closing the phase A and B switches which cause the known selected voltages V DET - V GAIN to be impressed upon capacitor C REF and the voltage V DET - V BIAS upon capacitor C VAR . A known selected voltage V DET - V F is also impressed upon capacitor C LIN . The charge reference phase is selected to be long enough for capacitor C REF and C VAR voltages to settle before entering the next phase, the charge redistribution phase. At the end of the first phase the phase A switch opens, then the phase B switch opens switching out the DAC voltages and the B switch then closes to switch in the supply voltage V DD and the feedback voltage V F . This causes the output of the charge comparator to go to a logic one, a logic zero or somewhere in-between depending on the error voltage at common detect pin 4. The phase B switches are selected to be closed long enough to allow the comparator and the voltages across C REF , C VAR to settle before entering the third sample phase. During the third phase, according to a feature of the invention, switch SW3 is programmed during calibration to be closed (switch SW3 open, the opposite modes being shown in Fig. 1). The charge comparator 14 output is sampled through phase switch C and will then accordingly charge or discharge integrating capacitor C INT . The voltage across comparator C INT is buffered by integrator buffer 20 and fed back to the input capacitor network through the resistor feedback network 22. In the steady state, when capacitor C VAR is unchanging, the voltage of pin 4 does not change when switching between the reference phase and the charge redistribution or sample phase. The change in the charge on capacitor C REF , C VAR and C LIN , when switching from the reference phase to the comparator phase, can be calculated and the general form of a transfer function relating the output voltage to the change in the voltage of capacitor C VAR can be written F OUT = G*(F BIAS - (1 - F GAIN ) * C REF /(C VAR - C LIN )) - 1/3 with switch SW2 closed and where F OUT = V OUT/ V DD and G is a known constant. A similar transfer function can be written with switch SW2 closed. The transfer function shows that the output voltage V OUT at terminal OUT is a linear function of mechanical stimulus if capacitance C VAR -C LIN is inversely proportional to a linear function of mechanical stimulus (e.g., pressure, acceleration) however. However, capacitance C VAR inherently includes a parasitic capacitance C PAR which is independent of the mechanical stimulus and produces a non-linear output voltage. According to a feature of the invention, capacitor C LIN is used to neutralize the effect of this parasitic capacitance. Although switch SW3 in Fig. 1 is shown to be closed thereby connecting D-latch 18 in the circuit and providing a digital feedback loop, preferably switch SW3 is programmed to be closed with SW3 open to bypass the D-latch. This results in an analog feedback loop which reduces noise by enabling the circuit to null out any error charge on the common node, pin 4. Use of D-latch 18 results in applying a specific positive or negative charge to capacitor C VAR so that some error charge inherently remains on the common node. That is. this type of feedback results in a predetermined small amount of sensor output noise. Although the integrating time constant in prior art circuit approaches utilizing a flip-flop, whether in a switch voltage approach described or in a switched current approach, can be increased in order to reduce this noise, the frequency response of the sensor is concomitantly degraded. By eliminating the flip-flop, i.e., D-latch 18, with a switch that allows an analog feedback. the net error charge can be cancelled by the provision of an equal feedback charge thereby significantly reducing noise. For example, in a sensor built in accordance with the invention. output noise of 1% fso (full scale output) was reduced to 0.1% fso without degrading the frequency response. As referenced above, another feature relates to the provision of means to correct for output non-linearity. Typically, non-linearity on the order of 1.0% fso occurs on pressure and acceleration sensors. This non-linearity is caused by various factors, such as the non-uniform movement of the movable capacitor plate on a diaphragm which is placed in communication with a pressure source wherein movement of the diaphragm decreases as one goes in a direction from the center out to the fixed perimeter of the diaphragm. This non-linearity can be modeled by adding a parasitic capacitor C PAR in parallel with the variable capacitor C VAR as shown in Fig. 3. The electronic transfer function for the switched voltage approach as described above results in a sensor output voltage that is a linear function of C REF /(C VAR + C PAR - C LIN ). The inverse C VAR is ideally a linear function of the sensed stimulus therefore the sensor output voltage is also a linear function of the sensed stimulus as long as C LIN is equal to C PAR . As shown in Fig. 3, one end of capacitor C LIN is connected to-pin 4, the common node between capacitor C REF and C VAR while the other end is connected to a switch voltage signal that is opposite in phase to the signal applied to capacitors C VAR . The amount of linearity correction can be adjusted by adjusting the capacitance of C LIN or by adjusting the magnitude of the signal applied to capacitor C LIN . A transducer made in accordance with the invention comprised the following components in addition to integrated circuit 12: C VAR 20pF to 25pF C1 0.1uF C REF 20pF C FLT2 0.1 uF C LIN 2.0pF C FLT1 0.1uF R1 >10K ohm C LOAD 0.1uF R2 > 1.8K ohm C INT 0.047uF R3 > 1.8 ohm In an embodiment of the invention, a network feature shown in Fig. 4 provides thermal error compensation for the sensor. The network comprises a temperature dependent resistor R4 serially connected to a calibration resistor R5 between supply voltage V DD and ground V SS . A thermal compensation potentiometer R6 is connected between a reference voltage V DD /2 and the junction of resistors R4, R5. Calibration resistor R5 is adjusted such that adjustment of potentiometer R6 does not affect the offset compensation voltage connected to the sensor output stage at a first temperature, e.g., room temperature. Since the resistance value of resistor R4 changes with temperature, sensor output error caused by a change at a second temperature can be compensated by adjusting potentiometer R6 without affecting the sensor output at the first temperature. This embodiment simplifies thermal compensation by eliminating the need to make a second adjustment at the first temperature due to compensation at the second temperature. A further advantage is that with respect to the manufacturing process, the sensor data obtained in going from the first to the second temperatures and vice versa need not be remembered. A similar temperature compensation calibrating bridge is shown in coassigned U.S. Patent No. 5.241,850. It should be understood that although a particular embodiment of the invention has been described by way of illustrating the invention, other embodiments and variations of the invention are possible. The invention includes all modifications of the disclosed embodiment falling within the scope of the claims.

Claims: A sensor transducer comprising means for developing an electrical output signal responsive to a stimulus, including a thermal compensation network, the thermal compensation network comprising means for providing a reference voltage, a temperature dependent resistor (R4) and a calibration resistor (R5) serially connected between a supply voltage and ground forming a junction therebetween, and a thermal compensation potentiometer (R6) connected between the reference voltage and the junction, the potentiometer (R6) having an output signal which is added to the electrical output signal responsive to the stimulus, wherein adjustment of the calibration resistor (R5) can eliminate any effect of potentiometer setting upon the combined electrical output voltage at a first temperature, and wherein the potentiometer (R6) can be adjusted at a second temperature to provide compensation for offset error at a second temperature without affecting the combined electrical output signal at the first temperature. A sensor as claimed in claim 1, wherein the calibration resistor (R5) has been adjusted to eliminate any effect of potentiometer setting upon the combined electrical output signal at the first temperature and the potentiometer (R6) is adjustable at a second temperature to provide compensation for offset error at that second temperature without affecting the combined electrical output signal at the first temperature. A sensor as claimed in claim 1 or claim 2, wherein the first temperature is room temperature. A sensor as claimed in any preceding claim, wherein the stimulus is a mechanical stimulus A method of thermal compensation comprising the steps of providing a sensor transducer comprising means for developing an electrical output signal responsive to a stunulus and a thermal compensation network having means for providing a reference voltage, a temperature dependent resistor (R4) and a calibration resistor (R5) serially connected between a supply voltage and ground forming a junction therebetween and a thermal compensation potentiometer (R6) connected between the reference voltage and the junction, the potentiometer (R6) having an signal which is added to the electrical output signal responsive to the stimulus, the method futher comprising the steps of adjusting the calibration resistor (R5) to eliminate any effect of potentiometer setting upon the combined electrical output signal at a first temperature and adjusting the potentiometer (R6) at a second temperature to provide compensation for offset error at the second temperature without affecting the combined electrical output signal at the first temperature. A method as claimed in claim 5, wherein the stimulus is a mechanical stimulus.

Inventors: BERTHOLD JAMES P, KAWATE KEITH W, BERTHOLD, JAMES P., KAWATE, KEITH W.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1998
Main classification: G01D5
IPC codes: G01L1, G01P15, G01L9