Digital automatic gain control (AGC) circuit

Abstract: A digital AGC circuit, comprising an A/D converter (20), an AGC gate pulse generator (10) and a TOP voltage converter (30), is provided. The A/D converter (20) converts a video signal clamped to a reference level into digital data having a voltage between a predetermined reference voltage and a TOP voltage. The AGC gate pulse generator (10) generates an AGC gate pulse for detecting a pedestal level region of the video signal, according to vertical and horizontal synchronous signals. The TOP voltage controller (30) controls the TOP voltage of the A/D converter on the basis of a sample value extracted from the output of the A/D converter (20) and a sync tip value of a standard signal, while the AGC gate pulse generated by the AGC gate pulse generator (10) is enabled. All circuits but the low pass filter are digital circuits, so a special analog AGC IC is not needed. AGC is performed by controlling the TOP voltage of the A/D converter, thereby accomplishing an accurate AGC.

Description: The present invention relates to an automatic gain control (AGC) circuit, and more particularly, to a digital AGC circuit which performs AGC using an A/D converter. An AGC circuit automatically controls gain to give a constant output value at any time in spite of changes in an input value. An existing AGC circuit is made using an analog device. The AGC circuit having an analog device has no specific problem when used in an analog system, but is inconvenient to use in a digital system. Also, it is desired to provide an AGC circuit which can perform a more accurate automatic gain control. US 4628362 discloses an automatic gain control and digitizing circuit, comprising an A/D converter which converts a video signal into a digital signal. This document forms the pre-characterising portion of the independent claim 1 appended hereto. It is an aim of at least preferred embodiments of the present invention to provide an accurate digital automatic gain control (AGC) circuit. According to the present invention, there is provided a digital AGC circuit comprising an A/D converter, an AGC gate pulse generator and a TOP voltage converter. The A/D converter converts a video signal clamped to a reference level into a digital signal having a voltage between a predetermined reference voltage and a TOP voltage. The AGC gate pulse generator generates an AGC gate pulse according to vertical and horizontal synchronous signals. The TOP voltage controller controls the TOP voltage of the A/D converter on the basis of a sample value extracted from the output of the A/D converter, while the AGC gate pulse generated by the AGC gate pulse generator has an enabling value. The invention is characterised in that the AGC gate pulse generator generates the AGC gate pulse for detecting a pedestal level region of said video signal and the TOP voltage controller further controls the TOP voltage of the A/D converter on the basis of a sync tip value (K) of a standard signal. In the preferred embodiment, the TOP voltage controller comprises an AGC comparator, a PWM pulse generator and a low pass filter. The AGC comparator compares a mean value (M) of a predetermined number of samples extracted from the digital data output by the A/D converter with the sync tip value (K) of the standard signal, while the AGC gate pulse has an enabling value. The PWM pulse generator generates a PWM pulse signal corresponding to the output of the AGC comparator. The low pass filter integrates the PWM pulse signal output by the PWM pulse generator and transforms the result into a direct current voltage to be used as the TOP voltage of the A/D converter. Preferably, the AGC comparator comprises a sample mean value unit, a 1/K value setting unit and a multiplier. The sample mean value unit calculates the mean value (M) of N samples extracted from the output of the A/D converter, while the AGC gate pulse has an enabling value. The 1/K value setting unit obtains a sync tip value (K) of a standard signal and outputs the reciprocal value (1/K) of the sync tip value (K). The multiplier multiplies the mean value (K) output by the sample mean value unit by the value (1/K) set by the 1/K value setting unit and outputs the product (M/K) to the PWM pulse generator. For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figure 1 is a block diagram of a digital AGC circuit according to an embodiment of the present invention; Figure 2 is a detailed block diagram of an AGC comparator shown in Figure 1; Figure 3 is a waveform illustrating a process for obtaining a sync tip value (K) with respect to a standard signal; Figures 4A and 4B are waveforms illustrating a relationship between a multiplier output value (M/K) and a PWM pulse signal; Figure 5 is a waveform of a video signal and an AGC gate pulse; and Figure 6 is a waveform for illustrating a relationship between a multiplier output value (M/K) and an A/D converter TOP value. Referring to Figures 1 and 2, a digital AGC circuit according to an embodiment of the present invention is shown, comprising an AGC gate pulse generator 10, an A/D converter 20 and a TOP voltage controller 30. The TOP voltage controller 30 includes an AGC comparator 12, a PWM pulse generator 14 and a low pass filter 16. Referring also to Figure 2, the AGC comparator 12 includes a sample mean value unit 122, a 1/K value setting unit 124 and a multiplier 126. The AGC gate pulse generator 10 receives horizontal and vertical synchronous signals and generates an AGC gate pulse for detecting a pedestal level region of a video signal clamped to a reference level. Here, the vertical synchronous signal is necessary to generate an AGC gate pulse, to prevent the AGC gate pulse from being enabled within a vertical synchronization signal. The AGC gate pulse (shown in Figure 5) can be generated in plural. The A/D converter 20 performs an A/D conversion on the video signal clamped to a reference level between a reference voltage (usually, a ground voltage) and an initially-set TOP voltage (hereinbelow, called a reference TOP voltage) . The AGC comparator 12 compares a mean value (M) with a synctip value(K) with respect to a standard video signal. A standard video signal (hereinbelow, called a standard signal) represents a distance between a sync tip and a white peak (100% white) as 140IRE, and is comprised of a video signal 100 IRE, a sync signal 40 IRE, and a colour burst signal 40 IRE as the basis of a colour signal, with reference to a sync pedestal level (0 IRE). This is shown in Figure 3. In Figures 3, 5 and 6, reference numerals 32, 34 and 36 denote a colour burst signal, a sync tip, and a video signal, respectively. The mean value (M) is the mean of N samples extracted from digital data (data in a pedestal region of a video signal) output by the A/D converter 20, while the AGC gate pulse is enabled. Here, the sync tip value (K) of the standard signal denotes a value between a sync tip and a pedestal level of the standard signal, i.e., a pedestal value of the standard signal. The operation of the AGC comparator 12 will now be described in detail referring to Figure 2. The sample mean value unit 122 calculates the mean value (M) of N samples extracted from the output of the A/D converter 20 while the AGC gate pulse is enabled. At this time, the N samples which are used to calculate the mean value (M) can be obtained in one of two ways. First, the N samples can all be extracted from the output of the A/D converter 20 while one AGC gate pulse is enabled. Or, only one sample can be extracted during each AGC gate pulse, so that the N samples are gathered over the period of N AGC gate pulses. The sample mean value unit 122 can be easily realized using an M-bit shift register, an adder or a multiplier. The 1/K value setting unit 124 obtains a sync tip value (K) with respect to a standard signal and outputs the reciprocal (1/K) of the sync tip value (K). The multiplier 126 multiplies the mean value (M), output by the sample mean value unit 122, by the value (1/K) set by the 1/K value setting value 124, and outputs the multiplied value (M/K) to the PWM pulse generator 14. The AGC comparator 12 shown in FIG. 2 can also be comprised of a sample mean value unit 122 and a comparator (not shown). In that case, the comparator (not shown) outputs the difference between the mean value (M), output by the sample mean value unit 122, and the sync tip value (K) of the standard signal. The cases when the output of the comparator (not shown) is negative or positive correspond to the cases when the output value (M/K) (to be described later) of the multiplier 126 is smaller or larger than 1. The case when the output of the comparator is 0 corresponds to the case when M/K is 1. The method of obtaining a sync tip value (K) with respect to a standard signal will now be described referring to Figure 3. For an example, an 8-bit analog-to-digital conversion of an NTSC signal will be used. In this case, the sync tip value (K) of the standard signal becomes 72.85 by calculating a proportional expression, i.e., 255:140IRE = K:40IRE. In this example, the value K is set as 72 to simplify calculation. When an n-bit analog-to-digital conversion is performed, the sync tip value (K) with respect to the standard signal is given as (40IRE/140IRE) * (2 n -1). In the PAL or SECAM systems, K is given as (42IRE/137IRE) * (2 n -1). The multiplier 126 multiplies the mean value (M), output by the sample mean value unit 122, by the value (1/K) set by the 1/K value setting unit 124, and outputs the product (M/K) to the PWM pulse generator 14. The PWM pulse generator 14 generates a PWM pulse signal corresponding to the output of the AGC comparator 12. The low pass filter 16 integrates the PWM pulse signal output by the PWM pulse generator 14, and transforms the result into a direct current voltage to be used as a TOP voltage of the A/D converter 20. The operation of the AGC will be described referring to Figures 4 and 6. First, a description will be given of the case (Figure 4A) when the output value (M/K) of the multiplier 126 is larger than 1. The above case corresponds to the case when the mean value (M) of N samples is greater than the sync tip value (K) of the standard signal. Thus, the value (M) must be reduced thereby performing the AGC. For this, the gain of the A/D converter 20 must be reduced by making the TOP voltage larger than a reference TOP voltage. The PWM pulse generator 14, having received a value (M/K) smaller than 1 from the multiplier 126, increases the width of high pulses from an initially-set PWM pulse width, and provides the result to the low pass filter 16. The low pass filter 16 integrates the PWM pulse signal having increased pulse width, and inputs a first TOP voltage (shown in Figure 6), that is higher than the reference TOP voltage, to the A/D converter 20. Since the peak-peak value of the input video signal (analog signal) is fixed, then if the TOP voltage initially set in the A/D converter 20 increases to the first TOP voltage, the level of data converted by the A/D converter 20 decreases from the level when the reference TOP voltage is used. Consequently, the gain of the A/D converter 20 decreases, and finally automatic-gain-controlled digital data is output by the A/D converter 20. Next, a description will be given of the case (FIG. 4B) when the output value (M/K) of the multiplier is smaller than 1. This occurs when the mean value (M) of N samples is smaller than the sync tip value (K) of the standard signal. Thus, the value (M) must be increased, thereby performing the AGC. This is performed in the same way as when M/K >1, but by making change in the opposite direction. For this, the gain of the A/D converter 20 must be increased by making the TOP voltage smaller than the reference TOP voltage. The PWM pulse generator 14, having received a value (M/K) smaller than 1 from the multiplier 126, increases the width of the low pulses, and provides the result to the low pass filter 16. The low pass filter 16 integrates the PWM pulse signal having increased low pulse width, and provides a second TOP voltage (shown in Figure 6) lower than the reference TOP voltage to the A/D converter 20. Then, when the TOP voltage initially set by the A/D converter 20 decreases to the second TOP voltage, the level of data converted by the A/D converter 20 increases from the level when the reference TOP voltage is used. Consequently, the gain of the A/D converter 20 increases, and finally automatic-gain-controlled digital data is output by the A/D converter 20. When the output value (M/K) of the multiplier 126 is 1, since the pulse width of a PWM pulse signal initially-set by the PWM pulse generator 14 is maintained, the TOP voltage input to the A/D converter 20 remains the same as the initially-set reference TOP voltage. The AGC is performed by continuously performing the above processes. In the preferred embodiment of the present invention, the 8-bit analog-to-digital conversion is used only as an example. The present invention is applicable to the general case of an n-bit A/D conversion, such as 10-bit, 12- bit, 18-bit, 20-bit, etc. Also, the present invention can be applied not only to the NTSC broadcasting method but also to other broadcasting methods such as PAL, SECAM, etc. Advantageously, all circuits but the low pass filter are digital circuits, so that a special analog AGC IC is not needed. AGC is performed by controlling the TOP voltage of the A/D converter, thereby accomplishing an accurate AGC.

Claims: A digital AGC circuit comprising: an A/D converter (20) which converts a video signal clamped to a reference level into a digital signal having a voltage between a predetermined reference voltage and a TOP voltage; an AGC gate pulse generator (10) which generates an AGC gate pulse according to vertical and horizontal synchronous signals; and a TOP voltage controller (30) which controls the TOP voltage of said A/D converter on the basis of a sample value extracted from the output of said A/D converter, while said AGC gate pulse generated by said AGC gate pulse generator has an enabling value; characterised in that : the AGC gate pulse generator (10) generates the AGC gate pulse for detecting a pedestal level region of said video signal; and the TOP voltage controller (30) further controls the TOP voltage of the A/D converter (20) on the basis of a sync tip value (K) of a standard signal. The digital AGC circuit as claimed in claim 1, wherein said TOP voltage controller (30) comprises: an AGC comparator (12) which compares a mean value (M) of N samples extracted from the digital data output by said A/D converter with said sync tip value (K) of the standard signal, while said AGC gate pulse has an enabling value; a PWM pulse generator (14) which generates a PWM pulse signal corresponding to the output of said AGC comparator; and a low pass filter (16) which integrates said PWM pulse signal output by said PWM pulse generator and transforms the result into a direct current voltage to be used as the TOP voltage of said A/D converter. The digital AGC circuit as claimed in claim 2, wherein said AGC comparator (12) comprises: a sample mean value unit (122) which calculates said mean value (M) of N samples extracted from the output of said A/D converter, while said AGC gate pulse has an enabling value; a 1/K value setting unit (124) which obtains a sync tip value (K) of a standard signal and outputs the reciprocal value (1/K) of said sync tip value (K); and a multiplier (126) which multiplies said mean value (K) output by said sample mean value unit by said value (1/K) set by said 1/K value setting unit and outputs the product (M/K) to said PWM pulse generator. The digital AGC circuit as claimed in claim 2, wherein said AGC comparator (12) comprises: a sample mean value unit (122) which calculates said mean value (M) of N samples extracted from the output of said A/D converter, while said AGC gate pulse has an enabling value; and a comparator which outputs the difference between said mean value (M), output by said sample mean value unit (122), and said sync tip value (K) of the standard signal. The digital AGC circuit as claimed in claim 3 or 4, wherein said sample mean value unit (122) calculates the mean value (M) of N samples extracted from the output of said A/D converter (20) during the period in which one AGC gate pulse has an enabling value. The digital AGC circuit as claimed in claim 3 or 4, wherein said sample mean value unit (122) calculates the mean value (M) of N samples which are gathered over the period of N AGC gate pulses by extracting one sample during each AGC gate pulse.

Inventors: BAE JUM-HAN, BAE, JUM-HAN
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1998
Main classification: H04N5
IPC codes: H04N5, H03K7