Symbol synchronization in multicarrier receivers

Abstract: Improved synchronization of OFDM signals is achieved. A controlled oscillator (8) provides clock pulses to derive complex samples of an input signal which are applied both to a fast Fourier transform (5) for data recovery and to a synchronization unit (9). The synchronization unit generates the complex product XY* of the input and the delayed input, which is applied to a high-pass filter (30) to suppress frequencies below the symbol frequency. The filter output is applied through a symbol comb filter (40) to an adaptive slicer (50) which determines the larger magnitude of the real and imaginary components of the signal. A pulse processor (60) generates a single pulse at the leading edge of the symbol pulse which is applied to a symbol counter (70). The symbol counter includes two count stages arranged to lock in quickly and yet be variable to accommodate different guard intervals in the OFDM signal.

Description: Background of the Invention This invention relates to apparatus for extracting information from a signal which consists of a succession of symbol periods each consisting of an active symbol period and a guard interval. In particular the invention is applicable to the synchronization of Orthogonal Frequency Division Multiplex (OFDM) signals, such as may be used for broadcasting digital television signals in the uhf (ultra high frequency) bands, or for digital audio broadcasting (DAB). The form of OFDM signal proposed for this purpose consists of data signals and reference information modulated as QPSK (quadrature phase shift keying) or QAM (quadrature amplitude modulation) on to several thousand individual carriers, evenly spaced in frequency and occupying a total bandwidth of several Megahertz in the uhf spectrum. The data signal on each carrier has a relatively long symbol period and this, in part, gives the signal its good performance in conditions of multipath propagation. The multipath performance is further enhanced by the inclusion of a guard interval in which a portion of the modulated signal waveform taken from the end of each symbol is also included at the beginning of the same symbol period. Different fractions of the basic symbol period, such as 1/32, 1/16, 1/8 or 1/4, can be used in this way to provide immunity to multipath distortion of increasingly long delays. More specifically, each symbol is extended by a period T G (the guard interval) which precedes the "useful" or "active" symbol period T S , so that the whole symbol now lasts T T in total. T S is the reciprocal of the carrier spacing f S , and is the duration of the time domain signal produced or analysed by the FFT (fast Fourier transform) in the transmitter and receiver respectively. Each carrier is continuous over the boundary between the guard interval and the active part of the same symbol, keeping the same amplitude and phase. If the signal at complex baseband is considered, with all the carrier frequencies not only spaced f S , but also equal to multiples of f S , then the signal in the guard interval is effectively a copy of the segment of the signal occupying the last T G 's worth of the active part, as shown in Figure 4 of the accompanying drawings. It follows that the signal has the same value at any two instants which are separated by T S but lie within the same symbol. Specific proposals for synchronization of OFDM receiving apparatus have been published for example in European Patent Applications EP-A-0 653 858 and 0 608 024, and International Patent Applications WO95/07581, WO95/05042 and WO95/03656. The principal requirement for synchronization in a receiver is to obtain from the signal waveform a reliable time synchronization pulse related to the start of the symbol period. Such a pulse could then be used to start, at the correct position in the waveform, the process of Fourier transformation which accomplishes a major portion of the demodulation process. A second requirement for synchronization is to lock the digital sampling clock in the receiver to an appropriately chosen harmonic of the symbol period. However, the modulated OFDM waveform produced by adding together all the modulated carriers is essentially noise-like in nature and contains no obvious features such as regular pulses which could be used to synchronize the circuitry of a receiver. Because of this, we have previously proposed techniques for synchronization which are based on correlation of the signal with a version of itself delayed by the basic symbol period. The similarity between the portion included to form the guard interval and the final part of the basic symbol is then shown as a region of net correlation, while the remainder of the symbol period shows no correlation. Even so, the correlated waveform still reflects the noise-like nature of the signal waveform and can be impaired by signal distortions, so it is necessary to process the signal further to obtain reliable synchronization. Our European patent application No. 96307964.5, publication No. 0 772 332 (publication date 7 May 1997), describes the use of a correlator with a filter which exploits the periodicity of the waveform to form a complex symbol pulse and then uses the argument of the pulse to obtain frequency control for a local oscillator. In addition, the modulus of the pulse signal is used to derive a pulse related to the start of the symbol period and to derive a signal to control the clock frequency in the demodulator. A complex integrate-and-dump technique is included in the clock loop to suppress interference. The application also discloses (page 16 lines 13 to 15 of EP-A-0 772 332) the use of a high-pass filter for the purposes of AFC extraction. Summary of the Invention The present invention is defined in Claim 1 below, to which reference should now be made. Advantageous features of the invention will be described in more detail by way of example with reference to the drawings. A preferred embodiment of the invention is described in more detail below. The preferred embodiment also uses correlation and a filter which exploits the periodicity of the waveform to form a symbol pulse, but additionally includes a high-pass filter in order to counteract the effects of interference. This is achieved by suppressing frequencies substantially below the symbol frequency, prior to the determination of the position of the start of the symbol (by adaptive slicing, as described below, or otherwise). The preferred embodiment also incorporates two additional improvements: 1. An adaptive slicing technique based on the modulus and the argument of the symbol pulse waveform is employed in order to extract timing information from the pulse. Thus, the magnitude alone is not used, as this would give inferior results. As a further development of this, we have recognised that an approximation to the correct phase can be used initially, as once the system has locked correctly to the incoming signal, the desired phase will become aligned with the real axis, and this can thereafter be assumed to be the correct phase or argument. 2. A symbol period counter is used to provide stable and correctly timed pulses to start the process of Fourier transformation and to provide a control signal to lock the sampling clock in the demodulator. The symbol period counter is of particularly ingenious construction which does not require the counter to rephase itself through a full symbol period. Instead we have appreciated that the counter can be split into two parts, in such a way as to lock in much more quickly. These two additional improvements are described in EP-A-0 876 031 and form the subject of divisional applications Nos. 02078145.6 (EP-A-1 267 539) and 02078144.9 (EP-A-1 267 538) respectively. The three improvements, namely of the present and the divisional applications, can with advantage be used together. Brief Description of the Drawings The invention will now be described in more detail, be way of example, with reference to the accompanying drawings, in which: Figure 1 is a block circuit diagram of the relevant part of an OFDM receiver embodying the invention; Figure 2 is a block circuit diagram of the synchronization unit of the receiver of Figure 1; Figure 3 is a block circuit diagram of the high-pass filter circuit of the synchronization circuit in the receiver of Figure 1; and Figure 4 (described above) is a diagram showing how each symbol comprises an active symbol and a guard interval, and illustrates the relationship between them. Detailed Description of the Preferred Embodiment The system will be described using parameter values from a particular system of digital OFDM signal transmission by way of example. More details of this system are contained in ETSI draft document prETS 300 744, November 1996, now document ETS 300 744 dated March 1997. The relevant parts of an OFDM receiver embodying the invention are shown in block diagram form in Figure 1. The receiver has a uhf input 1 which applies a received signal to a down-converter 2. The output of the down-converter is applied to an a-d (analog-to-digital) converter 3 which receives a clock input from a voltage-controlled crystal oscillator 8 and supplies an output to a real-to-complex converter 4. The output of the real-to-complex converter 4 is applied first to a Fourier transform circuit, such as a well-known FFT (fast Fourier transform), and also to a synchronization unit 9. The output of the Fourier transform circuit is applied to data recovery circuitry 6, based on that in a known OFDM receiver, to provide a data output at 7. The synchronization unit 9 has two outputs, namely an output 10 which is coupled to the Fourier transform circuit 5, and an output 11 which is applied to the controlled oscillator 8. Finally, the synchronization unit 9 receives the clock signal from the controlled oscillator 8. The operation of the circuit of Figure 1 is as follows. A received uhf OFDM input signal at the input 1 is down-converted by frequency shifting in the down-converter 2 to occupy a bandwidth of nominally 8MHz in the region 0-9MHz. It is then sampled by the a-d converter 3, operating with a sampling frequency of 18·285714 MHz from the voltage-controlled crystal oscillator 8. The real samples from the a-d converter are converted by the real-to-complex converter 4 into the form of complex samples at 9·142857 MHz required for Fourier transformation in the Fourier transform circuit 5. As each complex sample consists of real (R) and imaginary (I) components, it is convenient to multiplex the two together in a sequence R 1 I 1 R 2 I 2 ... thus retaining the 18·285714 MHz rate of the data stream. Accordingly, the synchronization unit 9 accepts the OFDM signal waveform as a series of complex samples which are then processed to produce a series of regular symbol pulses at output 10 to start the transform at the appropriate time in the symbol. Additionally, the synchronization unit can provide a signal at output 11 to lock the controlled oscillator 8. This is achieved by comparing the timing of regular symbol pulses which are produced by dividing the sampling clock by an appropriate ratio, with the timing of the symbol pulses extracted from the incoming signal waveform. The main elements of the synchronization unit 9 are shown in Figure 2. Referring to Figure 2, the complex input from the real-to-complex circuit 4 is applied to an input terminal 21 and thence to a delay 20 with a duration equal to the basic symbol period T S and to a conjugating circuit 24. The conjugating circuit 24 forms the complex conjugate of each sample by inverting the imaginary part. The outputs of the delay 20 and conjugating circuit 24 are both applied to a full four-component complex multiplier 22. Thus, the multiplier provides an output XY*, where Y is the input signal, X is the signal Y after the delay 20, and the asterisk (*) indicates the complex conjugate. The delay 20, conjugating circuit 24 and multiplier 22 operate as a correlator, as described in our above-mentioned European patent application No. 96307964.5. The output of the multiplier 22 is applied to a high-pass filter circuit 30, the output of which is applied to a symbol-period comb filter 40. The output of the filter is then applied to an adaptive slicing circuit 50 the output of which in turn is applied to a pulse processing circuit 60. The output of the pulse processing circuit 60 is then applied to a symbol counter 70. The operation of the synchronization circuit shown in Figure 2 is as follows. The noise-like OFDM signal in complex form is applied to the delay 20 with a duration equal to the basic symbol period, and to the conjugating circuit 24 which forms the complex conjugate of each sample by inverting the imaginary part. The correlation between the two signals is produced by the complex multiplier 22 and appears as a noisy pulse waveform at symbol rate. It should be recognised that the conjugation process 24 can alternatively be placed in the delayed signal, that is in series with the delay 20, with equal effectiveness. That is, the signal YX* is generated rather than XY*. The high-pass filter circuit 30 is included to remove complex-valued offsets introduced by interference. This is followed by the symbol-period comb filter 40, which exploits the periodic nature of the waveform to suppress noise and other impairments so as to produce a rectangular pulse, the duration of which is related to the guard interval. It should be noted that the comb filter 40 could be placed before the high-pass filter 30 with similar effectiveness. The adaptive slicing circuit 50 is used to prepare the complex waveform for slicing at the most advantageous point, taking account of the effects of local oscillator frequency errors, amplitude variations, and distortions arising from multipath propagation. This circuit 50 is followed by the pulse processing circuit 60, which generates a single pulse at the leading edge of the symbol pulse, and prevents the generation of spurious pulses which might arise from multiple crossings of the slicing level in a noisy signal. The timing of the pulses produced by the pulse processing circuit 60 is compared with the timing of pulses produced by dividing the sampling clock frequency down to symbol rate in the symbol counter 70. The comparison produces a signal at output 11, which is used to control the clock oscillator 8. Regular appropriately-timed symbol rate pulses at output 10 are derived from the symbol counter 70 and are used to start the Fourier transform processing on each symbol. The pulses from the pulse processing circuit 60 are also used for initial resetting of the symbol counter 70 during lock-up; but after the initial period, adjustment of the position of the pulses at output 10 is obtained only by controlling the sampling clock frequency. This ensures that the number of clock periods between symbol pulses remains constant, which is necessary for simplifying the operation of subsequent processing in the data recovery circuitry 6 in Figure 1. The operation of the high-pass filter circuit 30 of Figure 2 will now be described in more detail. For a description of the circuits 40, 50, 60 and 70, see EP-A-0 876 031. Because an OFDM signal is made up of a large number of carriers, if in-band sinusoidal interference is present, then only a few carriers will be affected and the resulting errors will be within the capacity of the error correcting codes of the system. However, such signals can cause premature synchronization failure by introducing a complex offset signal into the output of the correlator multiplier 22 in Figure 2, so that the slicer 50 fails to detect the symbol pulses. We have appreciated that the offset introduced by interference can be substantially removed by incorporating a high-pass filter which cuts out frequencies substantially below the symbol frequency. This filter is located before rather than after the adaptive slicing or other means for determining the phase or argument of the complex signal. Figure 3 shows the details of the high-pass filter arrangement 30 used, consisting of a recursive low-pass filter 32 connected to the output of the multiplier 22 (Figure 2) and which extracts the average level of the signal, and a subtractor 34 also connected to the output of the multiplier 22, and which subtracts the filter output from the input signal and thus has its non-inverting input connected to the output of the multiplier 22 and its inverting input connected to the output of the filter 32. The recursive low-pass filter 32 comprises a subtractor 36 the non-inverting input of which is connected to receive the complex input from the multiplier 22 and the output of which is connected to a divider or binary shift circuit 37, which divides by 4096 by shifting the binary values by 12 places. The output of the circuit 37 is applied to an adder 38, the output of which is applied to a register or delay device 39 providing two clock periods of delay. The output of the delay device 39 constitutes the output of the filter 32 and is applied to the inverting input of the subtractor 34, and is also applied both to the other input of the adder 38 and to the inverting input of the subtractor 36. The arrangement of the subtractor 36, the binary shift circuit 37, the adder 38, and the delay device 39 constitutes a recursive loop which causes 1/4096th of the input to be added to 4095/4096ths of the previously accumulated total, thereby producing a long-term average of the input signal. The value of the shift factor 37 is chosen, on the one hand, so that the change of average value during the symbol period is small and, on the other hand, so that the acquisition time is not significantly lengthened. Since the signal is in the form of time-multiplexed real and imaginary samples, the low-pass filter includes two clock periods of delay 39 so that the real and imaginary signals are processed at separate time instants. An alternative method of producing an average as the output of the low-pass filter described is to accumulate the input signal for a period, store the accumulated total, and divide by the number of samples. Such an arrangement is less preferred because there is the possibility of introducing abrupt changes as new accumulated values are applied to the subtractor. Whereas Figure 3 shows the high-pass filter arranged as a low-pass filter and a subtractor, it should be noted that the output can alternatively be taken more simply from subtractor 36, since subtractors 34 and 36 share common inputs. This is indicated in dashed lines at 31. Thus the filter does not have to operate by subtraction of the low-frequency components from the signal in order to provide a high-pass function; other filter designs may be used. Equally the filter does not have to be a recursive filter. The cut-off characteristic of the filter need not be particularly steep; there should not however be significant attenuation at the symbol frequency. Because of the noise-like nature of the correlated signal, it is desirable to filter the signal so as to reduce the noise before slicing to detect the symbol pulse. However, conventional low-pass filtering would distort the pulse, degrading the sharpness of the edges. This is undesirable, because the position of the start of the pulse is of particular interest for synchronization. It is therefore greatly preferred to follow the high-pass filter with a comb filter arrangement 40 which combines signal values at corresponding positions from one symbol to another. This suppresses the noise components, but retains the underlying shape of the pulse. Moreover it is necessary to filter the signal in this way to suppress product terms arising from the multiplication of interference with the signal in the correlation multiplier 22, which are not suppressed by the high-pass filter 30. While one example of the invention has been described, it will be appreciated that many variations may be made in the implementation of the invention.

Claims: Claims for the following Contracting States : BE, DE, FR, IT Apparatus for extracting synchronizing information from a signal which comprises a succession of symbol periods T T each consisting of an active symbol period T S and a guard interval T G , the apparatus comprising: means (21) for receiving an input signal Y; means (20) for providing a signal X delayed by a time period equal to the active symbol period T S ; means (22,24) for forming a signal related to the complex product XY* or X*Y of the input signal and the delayed signal to provide a succession of pulses, one for each symbol period; means (30) for high-pass filtering the complex product signal to suppress frequencies substantially below the symbol frequency; clock means (8) for generating clock signals for use in extracting the information from the input signal; and means (40,50,60,70,11) coupled to the output of the high-pass filtering means for controlling the clock means to be in synchronism with the input signal. Apparatus according to claim 1, in which the high-pass filtering means (30) comprises a recursive filter. Apparatus according to claim 1, in which the high-pass filtering means comprises low-pass filtering means (32), and combining means (34) arranged to subtract the output of the low-pass filtering means from the input signal. Apparatus according to claim 3, in which the low-pass filtering means comprises averaging means (36-38) for forming a time average of the input signal. Claims for the following Contracting State : SP Apparatus for extracting information from a signal which comprises a succession of symbol periods T T each consisting of an active symbol period T S and a guard interval T G , the apparatus comprising: means (21) for receiving an input signal Y; means (20) for providing a signal X delayed by a time period equal to the active symbol period T S ;and means (22,24) for forming a signal related to the complex product XY* or X*Y of the input signal and the delayed signal to provide a succession of pulses, one for each symbol period; characterized by means (30) for high-pass filtering the complex product signal to suppress frequencies substantially below the symbol frequency. Apparatus according to claim 1, further comprising clock means (8) for generating clock signals for use in extracting the information from the input signal; and means (40,50,60,70,11) coupled to the output of the high-pass filtering means for controlling the clock means to be in synchronism with the input signal. Apparatus according to claim 1, in which the high-pass filtering means (30) comprises a recursive filter. Apparatus according to claim 1, in which the high-pass filtering means comprises low-pass filtering means (32), and combining means (34) arranged to subtract the output of the low-pass filtering means from the input signal. Apparatus according to claim 4, in which the low-pass filtering means comprises averaging means (36-38) for forming a time average of the input signal.

Inventors: CLARKE CHRISTOPHER K P, ROBINSON ADRIAN PAUL, STOTT JONATHAN HIGHTON, CLARKE, CHRISTOPHER K.P., ROBINSON, ADRIAN PAUL, STOTT, JONATHAN HIGHTON, Clarke, Christopher K.P. British Broadcasting Corp, Robinson, Adrian Paul, British Broadcasting Corp., Stott, Jonathan Highton, British Broadcasting Corp
Applicants: BRITISH BROADCASTING CORP, BRITISH BROADCASTING CORPORATION
Application year: 1998
Main classification: H04L27
IPC codes: H04L25, H04L1, H04N7, H04N5, H04L27