SWITCHED-CURRENT MEMORY

Abstract: A switched current memory circuit has an input to which an input current (i) is applied and which is connected via a switch (S1) to the drain electrode of a memory transistor (M). A second switch (S3) is connected between the memory circuit input and the source electrode of a grounded gate transistor (G) whose drain electrode is connected to the gate electrode of the memory transistor (M). The drain electrode of the memory transistor (M) is connected via switch (S2) to an output at which an output current (iOr) is produced. The second switch (S3) provides zero-voltage switching which reduces the effects of charge injection on the current stored.

Description: DESCRIPTION SWITCHED-CURRENT MEMORY The invention relates to a switched-current memory circuit. Figure 1 shows two known switched-current memory circuits or cells, the grounded-gate memory and the zero-voltage switching memory. The grounded-gate memory shown in Figure 1a has been disclosed in a paper entitled "Switched-Current Signal Processing for Video Frequencies and Beyond" by J B Hughes and K W Moulding and published in IEEE Journal of Solid-State Circuits, Vol 28, No 3, March 1993, pp 314-322 and uses a non- inverting voltage amplifier G to reduce non-ideal behaviour resulting from finite memory transistor g m /g 0 . However, the charge injection from switch S3 is unchanged and becomes the dominant sampling error. It is signal-dependent and so causes harmonic distortion as well as offset and gain errors. The zero-voltage switching memory shown in Figure 1b has been disclosed in a paper entitled "Zero-Voltage Switching in Switched-Current Circuits" by D G Nairn published in the Digest of papers of IEEE International Symposium on Circuits and Systems, 1994, pp 289-292 and uses a virtual-earth inverting amplifier A to reduce g m /g 0 errors. Further, as the memory switch is placed at the amplifier's virtual earth the charge injection from the switch S3 is dumped onto capacitor C m to product a signal-independent sampling error. This is less troublesome because it is only an offset error. However, the cell consumes more power, generates more noise and the more complex loop gives higher order settling behaviour which limits the cell's effective bandwidth. It is an object of the invention to enable the provision of a switched- current memory cell in which the effects of one or more of the disadvantages of the prior art circuits referred to above can be mitigated. The invention provides a switched-current memory circuit comprising an input which is connected via a first switch to the drain electrode of a field effect transistor and via a second switch to the gate electrode of the transistor, the path between the input and the gate electrode of the transistor further including a grounded gate amplifier, and an output connected via third switch to the drain electrode of the transistor, in which the first and second switches are closed during a first portion of a clock period and the third switch is closed during a second non-overlapping portion of the clock period or a subsequent clock period and the second switch is connected between the input of the memory circuit and the input of the amplifier. Such memory cell effects both charge injection and g m /g 0 error reduction through zero-voltage switching in the grounded-gate memory. The second switch may comprise a first field effect transistor connected in series with a second field effect transistor whose source and drain electrodes are shorted together and whose drain electrode is driven during the second portion of the clock period. This enables a further reduction in charge injection as the action of the second transistor is such as to cancel injected charge from the first transistor. A further field effect transistor may be connected in between the first switch and the drain electrode of the first mentioned transistor, the drain electrode of the further transistor being connected to a potential source which causes it to be conductive. The further field effect transistor serves to compensate for the voltage drop on the output transistor. This is explained in greater detail in EP-A-0789920 (PHB34007). A memory circuit for storing balanced currents may be formed by two current memory circuits as set forth above. This will produce a more constant differential transconductances so that any residual error at the gate of the memory transistor of each of the current memory circuits translates to an offset error in the differential output. This invention further provides a differential current memory circuit comprising first and second field effect transistors connected as a differential pair, first and second inputs which are connected via respective first switches to the drain electrodes of the first and second transistors and via respective second switches and respective grounded gate amplifiers to the gate electrodes of the first and second transistors, and first and second outputs connected via respective third switches to the drain electrodes of the first and second transistors, wherein the first and second respective switches are closed during a first portion of a clock period and the third respective switches are closed during a second non-overlapping portion of the clock period or a subsequent clock period. The voltage at the junction of the first and second transistors may be arranged to control the bias currents to the grounded gate amplifiers. This reduces the effect of both common mode input signals and charge injection errors from the respective second switches. The above and other features and advantages of the present invention will be apparent from the following description, by way of example, of embodiments of current memory cells with reference to the accompanying drawings, in which: Figures 1a and 1b show circuit diagrams of prior art current memory cells; Figure 1c shows switching waveforms for the switches in the current memory cells of both the prior art memory cells and the embodiments shown in Figures 2a, 2b, 2c and 3 hereof; Figure 2a shows a first embodiment of a current memory cell according to the invention; Figure 2b shows a second embodiment of a current memory cell according to the invention; Figure 2c shows a third embodiment of a current memory cell according to the invention; and Figure 3 shows a fourth embodiment of a current memory cell according to the invention. Referring to Figure 2a, the cell is similar to the grounded-gate memory (Figure 1a) except that there is no switch in the gate of the memory transistor M and the input switch S1 connects to the memory transistor drain and via switch S3 to the input of the grounded gate amplifier. Its operation is as follows. On phase φ1 , the memory transistor M is connected in a closed-loop configuration with the grounded-gate amplifier G. The memory transistor's drain current settles to J+i and the gate voltage to sustain this is applied to C m . The high voltage gain of the grounded gate amplifier G ensures that the voltage at the input is held nearly constant, i.e nearly independent of the signal i. Besides ensuring low g m /g 0 error, this also produces a constant voltage at switch S3. At the end of phase φ'1 , switch S3 opens and the voltage stored on the capacitor C m is disturbed by the switch's channel charge flowing via the amplifier G onto capicitor C m . As switch S3 is held at nearly constant voltage, it will produce a nearly constant voltage error at the gate of the memory transistor M. This, however, still produces a signal-dependent error in the output current. Either or both of the techniques shown in Figures 2b and 2c can reduce this signal dependent error. First, because switch S3 operates at nearly constant voltage, its injected charge can be effectively cancelled by a dummy switch of approximately half width connected with both source and drain to the amplifier's input and with its gate driven by phase φ2 (Figure 2b). Note also the optional dummy switch which connects the input switch to the drain of the memory transistor M with its gate tied permanently to the supply rail V dd . This has the same dimensions as the output switch S2 and compensates for the voltage drop on the output switch on phase φ2. Secondly, a balanced pair or cells (Figure 2c) may be used to give a more constant differential transconductance so that any residual error voltage at the gate of the memory transistors M translates to an offset error in the differential output current. Figure 3 shows a fully differential version of the current memory circuit. It is derived from the single-ended circuit shown in Figure 2b. It has the advantage over the balanced arrangement shown in Figure 2c that it does not rely on transistor matching to balance the grounded gate amplifier bias currents l N and l P . Instead, the cascoded l N current sources form a common-mode feedback loop with the memory transistor pair M a and M b . On phase φ1 , if say l P is greater than l N , then the excess current l P - l N flows via the memory transistors into node X causing its voltage to rise. This increases l N until it matches l P . Now consider the effect of charge injection from switches S3a and S3b. At the end of phase φ'1 , the channel charges are routed via the grounded-gate amplifiers Ga and Gb onto the memory capacitors Cma and Cmb. As this causes a constant signal-independent voltage error at the memory transistor gates, this corresponds to a common-mode voltage error which disturbs node X. During phase φ2, the common-mode feedback loop remains closed and adjusts the value of l N so that momentarily it mismatches l P flowing in the amplifiers Ga and Gb. The error currents l P - l N flow into the gates of the memory transistors Ma and Mb causing node X to return to its earlier value. This can only be achieved when the voltages on the gates of the memory transistors have returned to the values on phase φ1. In other words, the common-mode loop acts to cancel the charge injection errors from switches S3a and S3b. When the input signals contain a common-mode component l cm , this flows initially with the differential input signal into the memory transistors Ma and Mb. The consequent imbalance in the currents summing at node X causes the common-mode feedback loop to act as before, increasing l N until it matches the sum of l P and l cm and leaving the memory transistors Ma and Mb biased correctly. On phase φ2, the common-mode signal is disconnected from the input and the common-mode feedback loop re-adjusts the value of l N until it matches l P without affecting the currents at the output. In other words, the memory cell rejects common-mode input signals. From reading the present disclosure, other modifications and variations will be apparent to persons skilled in the art. Such modifications and variations may involve equivalent features and other features which are already known in the art and which may be used instead of or in addition to features already disclosed herein. Although claims have been formulated in this Application to particular combinations of features, it should be understood that the scope of the disclosure of the present application includes any and every novel feature or any novel combination of features disclosed herein either explicitly or implicitly and any generalisation thereof, whether or not it relates to the same invention as presently claimed in any Claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The Applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during prosecution of the present application or of any further application derived therefrom.

Claims: CLAIMS 1. A switched-current memory circuit comprising an input which is connected via a first switch to the drain electrode of a field effect transistor and via a second switch to the gate electrode of the transistor, the path between the input and the gate electrode of the transistor further including a grounded gate amplifier, and an output connected via a third switch to the drain electrode of the transistors, in which the first and second switches are closed during a first portion of a clock period and the third switch is closed during a second non- overlapping portion of the clock period or a subsequent clock period and the second switch is connected between the input of the memory circuit and the input of the amplifier. 2. A memory circuit as claimed in Claim 1 in which the second switch comprises a first field effect transistor connected in series with a second field effect transistor whose source and drain electrodes are shorted together and whose drain electrode is driven during the second portion of the clock period. 3. A memory circuit as claimed in Claim 1 or Claim 2 in which a further field effect transistor is connected between the first switch and the drain electrode of the first mentioned transistor, the drain electrode of the further transistor being connected to a potential source which causes it to be conductive. 4. A memory circuit for storing balanced currents comprising first and second identical current memory circuits as claimed in any of Claims 1 to 3. 5. A differential current memory circuit comprising first and second field effect transistors connected as a differential pair, first and second inputs which are connected via respective first switches to the drain electrodes of the first and second transistors and via respective second switches and respective grounded gate amplifiers to the gate electrodes of the first and second transistors, and first and second outputs connected via respective third switches to the drain electrodes of the first and second transistors, wherein the first and second respective switches are closed during a first portion of a clock period and the third respective switches are closed during a second non-overlapping portion of the clock period or a subsequent clock period. 6. A memory circuit as claimed in Claim 5 in which each of the respective second switches comprises a first field effect transistor connected in series with a second field effect transistor whose source and drain electrodes are shorted together and whose drain electrode is driven during the second portion of the clock period. 7. A memory circuit as claimed in Claim 5 or Claim 6 in which respective further field effect transistors are connected between the respective first switches and the drain electrodes of the first and second transistors, the drain electrodes of the respective further transistors being connected to a potential source which causes them to be conductive. 8. A memory circuit as claimed in any of Claims 5 to 7 in which the voltage at the junction of the first and second transistors is arranged to control the bias currents to the grounded gate amplifiers.

Inventors: HUGHES JOHN BARRY, HUGHES, JOHN, BARRY
Applicants: KONINKL PHILIPS ELECTRONICS NV, PHILIPS SVENSKA AB, KONINKLIJKE PHILIPS ELECTRONICS N.V., PHILIPS AB
Application year: 1998
Main classification: G11C27
IPC codes: G11C27