Reference circuit

Abstract: A reference circuit (200') has bipolar transistors (216, 226) providing a voltage difference ΔV of base-emitter voltages | V BE | and has resistors (210/R 1 , 220/R 2 ) for adding a current I R1 resulting from ΔV and a current I R2 resulting from of base-emitter voltage | V BE | of one bipolar transistor (216 or 226) so that a resulting temperature coefficient TC TOTAL of said currents I R1 and I R2 is compensated. The circuit (200') has voltage transfer units (260, 270) which transfer ΔV to the resistors (210/R 1 , 220/R 2 ) so that the resistors (210/R 1 , 220/R 2 ) do not substantially load the bipolar transistors (216, 226). The voltage transfer units (260, 270) have input stages with n-channel FETs. A control unit (241) which is coupled to the bipolar transistors (216, 226) adjusts input voltages ( | V CE | ) at the voltage transfer units (260, 270) to temperature changes, so that the n-channel FETs operate in an active region. The control unit (241) has a voltage source (290) providing a voltage V DS REF which is similary temperature and process depending as a drain-source voltage of the n-FETs.

Description: Field of the invention The present invention generally relates to electronic circuits, and more specifically to circuits providing temperature independent reference voltages. Background of the Invention It is common in the electronic art to use reference voltage in connection with complex circuits and systems. Various circuits for generating reference voltages are well known, including those which employ temperature compensation so that the reference voltage is substantially independent of the temperature over a significant range. Bandgap reference circuits are known, for example, from: [1] Horowitz, P., Hill, W.: The art of electronics, Second Edition, Cambridge University Press, chapter 6.15: Bandgap (V BE ) reference, pages 335 - 341; [2] Ahuja, B. et. al.: A programmable CMOS Dual Channel Interface Processor for Telecommunications Applications, IEEE Journal of Solid State Circuits, vol. SC-19, no. 6, December 1984; [3] Song, B. S., Gray, P. R.: A Precision Curvature-Compensated CMOS Bandgap Reference, IEEE Journal of Solid-State Circuits, vol. SC-18, No. 6, December 1983, pages 634-643; [4] US patent 4,375,595 to Ulmer et. al.; and [5] Ruszynak, A.: CMOS Bandgap Circuit, Motorola Technical Developments, volume 30, March 1997, published by Motorola Inc., Schaumburg, Illinois 60196, pages 101-103. The principle used in the circuits described in [1] and [2], as with many other similar circuits, is based on adding two voltages whose temperature coefficients have opposite signs. One voltage is generated by a current of a given amount flowing through a diode or bipolar transistor resulting in a negative temperature coefficient and the other voltage is obtained across a resistor and has a positive temperature coefficient. FIG. 1 is a simplified circuit diagram of reference circuit 100 known in the art. Circuit 100 receives a supply voltage between lines 101 and 102. Circuit 100 comprises resistors R a and R b , operational amplifier OA, bipolar transistors Q 1 and Q 2 , and current sources I 1 and I 2 , coupled, for example, as illustrated in FIG. 1. A variety of publications, such as e.g., [1], [2], or [4], explain how circuit 100 provides substantially temperature independent voltage V out at line 110. Arrow 105 pointing to resistors R a and R b symbolizes spikes or other noise penetrating into circuit 100 via, e.g., a silicon substrate. Such spikes occur especially in integrated circuits which have analog portions (e.g., circuit 1.00) in the vicinity of digital portions. The sensitivity to accept spikes increases with the geometrical size of resistors R a and R b . Also, spikes can be rectified by transistors Q 1 and Q 2 or by other, including parasitic components with pn-junctions. The spikes are not the only problem. The trend in modem integrated circuits goes to small supply voltages, such as 0.8-0.9 volts or even less. Output voltages of e.g., 1.1 to 1.2 volts are generated by switched capacitors, which are very sensitive to spikes. In prior art circuits, such as in circuit 100, currents I 1 , I 2 flow through transistors Q 1 and Q 2 and through resistors R a and R b , thus loading the transistors Q 1 and Q 2 . Resistors R a and R b should have large resistance values (in e.g., megaohms) to provide necessary voltage drops. Also, they should have enough chip area to carry currents I 1 and I 2 . However, chip area is expensive and causes parasitic capacities making the circuit more sensitive to the above-mentioned spikes. Accordingly, there is on ongoing need to have reference circuits which overcome these and other deficiencies well known in the art. From patent publication EP 0321226 Al there is known a circuit for generating a potential intermediate between a power source potential and ground potential in a semiconductor chip. From patent publication WO 93/16427 Al there is known a voltage regulator adaptable for use with a filed programmable gate array. From US patent 5,352,973 there is known a temperature compensation bandgap voltage reference circuit. Statement of Invention In accordance with the invention there is provided a reference circuit according to claim 1. Brief Description of the Drawings FIG. 1 is a simplified circuit diagram of a reference circuit known in the art; FIG. 2 is a simplified block diagram of a reference circuit according to the present invention; FIG. 3 is a simplified circuit diagram of the reference circuit of FIG. 2 in a preferred embodiment of the present invention; FIG. 4 is a simplified circuit diagram of an input stage used in the reference circuit of FIG. 3; and FIG. 5 is a simplified circuit diagram of a voltage source used in the reference circuit of FIG. 3. Detailed Description of a Preferred Embodiment FIG. 2 is a simplified block diagram of reference circuit 200 according to the present invention. Reference circuit 200 comprises current sources 215 and 225 generating currents I 1 and I 2 , respectively, bipolar transistors 216 and 226, voltage transfer units 260 and 270, resistor 210 with value R 1 , resistor 220 with value R 2 , and node 205. Arrows in FIG. 2 and other FIGS. indicate voltages or currents. The direction of these arrows was only chosen for convenience of explanation. A person of skill in the art is able to define currents and voltages in opposite senses. To have the following description applicable for different types of semiconductor devices (e.g., diodes, pnp-, npn-transistors), voltages across one or more pn-junctions (e.g., V BE ) are given in | | symbols for absolute values. Currents I 1 and I 2 flow through bipolar transistors 216 and 226, respectively. Assuming different current densities J 1 in transistor 216 and J 2 in transistor 226, base-emitter voltages |V BE 1 | and |V BE 2 | are different and provide a voltage difference: ΔV = |V BE 1 | - |V BE 2 | ΔV is applied to resistor 210 by voltage transfer units 260 and 270 at both terminals of resistor 210, respectively. Now, with ΔV being applied across resistor 210, a current I R1 is generated: I R1 = ΔV/R 1 with the slash for division. I R1 does significantly not interfere with I 1 and I 2 . Hence, bipolar transistors 216 and 226 do not carry the load current I R1 of resistor 210. Assuming, for simplicity a zero voltage drop across transfer unit 260, V BE 1 of bipolar transistor 216 is applied across resistor 220. Similarly, a current I R2 is generated: I R2 = |V BE 1 |/R 2 I R2 is not significantly derived from I 1 or I 2 . Current I R2 and I R2 are summed up in node 205 to reference current I M ("output current I M "): I M = I R1 + I R2 I M = ΔV/R 1 + |V BE 1 |/R 2 I M = k*T/e 0 * R 1 * In(J 1 /J 2 ) + |V BE 1 |/R 2 with k = 1.38 * 10 -23 Joule / Kelvin, e 0 = 1.60 * 10 -19 Coulomb, and T the actual operating temperature of circuit 200 in Kelvin. The term "k * T/e 0 " is the temperature voltage V T . At room temperature (T=300K), V T is around 26mV (milli volts). The first and the second term in equations (4) to (6) have temperature coefficients TC 1 and TC 2 , respectively, which are, approximately related as |TC 1 | ≈ - |TC 2 | with TC 1 = dT I R1 /dT and TC 2 = dT I R2 /dT being deviations to the temperature T. A resulting temperature coefficient TC total of I M can be neglected and I M can be used as reference. A preferred embodiment of the present invention will be explained in connection with FIGS. 3-5. The operation of the embodiment will be explained after having described the figures. FIG. 3 is a simplified circuit diagram of the reference circuit of FIG. 2 in a preferred embodiment of the present invention. Reference circuit 200' (hereinafter circuit 200') has supply lines 201 and 202 for receiving a supply voltage V supply . Circuit 200' provides a reference voltage V BG ("BG" for "bandgap") preferably, at output line 203. Circuit 200' comprises current sources 215, 225 and 235, bipolar transistors 216 and 226, voltage transfer units 260 and 270 ("transfer units" or "op amps"), resistors 210, 220, and 230 having values R 1 , R 2 , and R 3 , respectively, transistors 217, 227 and 237 (e.g., also "FETs"), comparator 280, node 205, and voltage source 290. Elements 205, 210, 215, 220, 225, 216, 226, 260, and 270 have already been introduced in connection with FIG. 2. Elements, such as transistor 237, current source 235, voltage source 290, and comparator 280 form control unit 241 (enclosed by dashed frame). Control unit 241 provides countermeasures to a common mode drift of ΔV. Transistors 217 and 227 have the function of a current mirror 240 (enclosed by dashed lines). Convenient implementations of transfer units 260 and 270 are illustrated by example in FIG. 4; and voltage source 290 is illustrated in FIG. 5. Before explaining how the elements of circuit 200' are coupled, elements 215, 216, 217, 225, 226, 227, 237, 260, 270, and 280 are introduced. Current sources 215 and 225 can be implemented in may ways, for example, by resistors or transistor. Bipolar transistors 216 and 226 are, preferably, pnp-transistors having emitter electrodes ("emitters" or "E"), collector electrodes ("collectors" or "C") and base electrodes ("bases" or "B"). However, a person of skill in the art is able, based on the description herein, to use other components such as npn-transistors or diodes having pn-junctions. The term "bipolar transistor" as used here is intended to include any other device providing temperature dependent voltages. Transfer units 260 and 270 are, preferably, operational amplifiers configured as voltage followers. But this is not essential. The term "transfer unit" is intended to include any device measuring a first voltage at a first node and providing a second voltage to a second node, wherein the second voltage is the first voltage multiplied with a gain factor. For simplicity of explanation, it is assumed that the gain factor is equal to 1, but other values can also be used. The second node at the transfer unit does not consume power from the first node. At transfer unit 260, input 261 is preferably an inverting input ("-") and input 262 is, preferably, a non-inverting input ("+"). At transfer unit 270, input 271 is, preferably, an non-inverting input ("+") and input 272 is, preferably, an inverting input ("-"). Comparator 280 is, preferablyimplemented as operational amplifier having non-inverting input 281 ("+") and inverting input 282 ("-"). Transistors 217 and 227 are, preferably, field effect transistors (FETs) of the p-channel type (p-FET). Transistor 237 is, preferably, a FET of the n-channel type (n-FET). To use p-FETs and n-FETS is convenient, but not essential. FETs have gate electrodes ("gates" or "G"), and drain and source electrodes ("D" and "S"). Which electrode is the drain D and which is the source S, depends on the applied voltages, so D and S are distinguished here only for the convenience of explanation. As it will be explained later in connection with FIG. 3, transistor 237 is preferably, of the same type (n or p) as FETs at inputs 261, 262, 271, and 272 of transfer units 260 and 270. Current sources 215 and 225 are coupled between supply line 201 and emitters E of bipolar transistors 216 and 226, respectively. Collectors C of bipolar transistors 216 and 226 are coupled to supply line 202. Bases of transistors 216 and 226 are coupled together. Input 261 of transfer unit 260 is coupled to E of bipolar transistor 216; and input 271 of transfer unit 270 is coupled to E of bipolar transistor 226. Input 262 of transfer unit 260 is coupled to node 205. Output 263 of transfer gate 260 is coupled to gates G of FETs 217 and 227. Input 272 of transfer gate 270 is coupled to output 273 of transfer gate 270 which is coupled to resistor 210. Resistor 210 is further coupled to resistor 220 via node 205. Resistor 220 is further coupled to the bases of bipolar transistors 216 and 226. The source-drain (S-D) path of FET 217 is coupled between supply line 201 and node 205. FET 227 has its S coupled to supply line 201 and its D coupled to output line 203. Output line 203 is also coupled to supply line 202 via resistor 230. FET 237 has its D coupled to supply line 201 and its S coupled to current source 235 which is further coupled to supply line 202. The gate G of FET 237 is coupled to input 271 of transfer unit 270. Input 282 of comparator 280 is coupled to the S of FET 237. Input 281 of comparator 280 is coupled to output 291 of voltage source 290. Output 283 of comparator 280 is coupled to the bases B of bipolar transistors 216 and 226. It is convenient to introduce voltages and currents. Voltage difference ΔV is measured between the Es of bipolar transistors 216 and 226, that is between input 261 of transfer unit 260 and input 271 of transfer unit 270. Currents I 1 and I 2 generated by current sources 215 and 225, respectively, flow by definition into the Es of transistors 216 and 226, respectively. Current I M comes from p-FET 217 and is split at node 205 into current I R1 through resistor 210 and into current I R2 through resistor 220. A current between node 205 and input 262 is neglected. Mirror current I out originating by mirroring I M in current mirror 240 flows through transistor 227 and resistor 230. Output voltage (or reference voltage) V BG is defined across resistor 230 between output line 203 and supply line 202. Voltage V 3 is the voltage at the source S of n-FET 237 referred to line 202 and also applied to input 282 of comparator 280. V DS REF is provided by voltage source 290 at its output 291 and available at input 281 of comparator 280. V B ("B" for "base") is the base voltage of bipolar transistors 216 and 226 referred to line 202. Voltages at emitters E of bipolar transistors 216 and 226 referred to supply line 202 (here, coupled to collectors C) are |V EC 1 | and |V EC 2 | or, in general |V EC |. |V EC 1 | and |V EC 2 | are also present at inputs 261 and 271, respectively. FIG. 4 is a simplified circuit diagram of input stage 250 conveniently used in transfer units 260 and 270 of circuit 200' of FIG. 3. Input stage 250 comprises n-FETs 251, 252, and 253. As illustrated by lines 201' and 202' with primed reference numbers, input stage 250 is, preferably, coupled to supply lines 201 and 202 of FIG. 3. It is not essential, but understood by those of skill in the art, that other components can eventually be coupled between lines 201' / 201 and 202' / 202. As illustrated by arrows pointing to line 201', drains D of n-FETs 251 and 252 provide currents to subsequent stages of transfer unit 260 and 270. The sources S are coupled together to the drain D of n-FET 253. The source S of n-FET 253 is coupled to line 202'. Gate G of n-FET 251 is input 261 or input 271; and G of n-FET 252 is input 262 or input 272. G of n-FET 253 receives a bias voltage which is not essential to be described here and left out for simplicity. Preferably, n-FETs 251, 252, and 253 should operate in the saturation region ("active region"). Therefore, the gate-source voltages V GS 1 of n-FET 251 and V GS 2 of n-FET 252 are larger or substantially equal than the sum of threshold voltage V th and the drain-source saturation voltage V DS SAT of n-FETs: V GS 1 ≥ V th + V DS SAT and V GS 2 ≥ V th + V DS SAT . By biasing n-FET 253, its drain-source voltage V DS 3 is larger or substantially equal to the drain-source saturation voltage V DS 3 ≥ V DS SAT The input voltages of transfer units 260 and 270 at their inputs 261, 262, 271, and 272 are the emitter - collector voltages |V EC 1 | and |V EC 2 | across bipolar transistors 216 and 226. Here, |V EC | are: |V EC | ≥ 2 * V DS SAT + V th (twice saturation voltage and threshold voltage). The saturation voltage V DS SAT depends on the temperature. Therefore, it must be adjusted when the temperature changes. This is accomplished in the circuit of FIG. 5. FIG. 5 is a simplified circuit diagram of voltage source 290 used in the reference circuit 200' of FIG. 3. Voltage source 290 provides a voltage V DS REF at output 291. V DS REF (FIG. 5) and V DS SAT (see FIG. 4) depend on the temperature T and on a manufacturing process in the same way. Preferably, voltage source 290 comprises current source 296 and n-FETs 293 and 295 serially coupled between lines 201' and 202' (see FIG. 4). In detail, current source is coupled to line 201' and to the drain D of n-FET 293; the source S of n-FET 293 is coupled to the drain D of n-FET 295 at output 291; and the source S of n-FET 295 is coupled to line 202'. Gates G of n-FETs 293 and 295 are coupled together to D of n-FET 293. A person of skill in the art is able to provide a similar voltage source by other components and, based on the description herein, to use the voltage source in the same or similar function within circuit 200. As it will be explained later, V DS REF is used to control the common base voltage |V B | (see FIG. 3) of bipolar transistors 216 and 226. This voltage |V B | influences the voltage |V EC | at n-FETs 251 and 252 of input stages 260 and 270. It is an important feature of the embodiment of the present invention, that V DS REF is derived from the parameters of the FETs and not derived from bipolar transistors. Circuits 200 (FIG. 2) and circuit 200' provide reference current I M , which is substantially independent from temperature changes. Current sources 215 and 225, bipolar transistors 216 and 226, transfer units 260 and 270, resistors 210 and 220 operates as described in connection with FIG. 2. Current mirror 240 transfers reference current I M to I out through resistor 230. The output voltage V BG = I out * R 3 across resistor 230 at output line 203 does not significantly influence reference current I M . Voltage differences ΔV and |V BE | are subject to temperature changes. Also, input voltages V EC 1 and V EC 2 at transfer units 260 and 270 should depend on the threshold voltages V th of e.g., transistor 237 and the transistors within transfer units 260 and 270 (such as e.g., transistors 251 and 252). Hence, common mode drift of ΔV acts on input stages 250 of transfer units 260 and 270 which require certain input voltages (e.g., |V EC | ≥ 2 * V DS SAT + V th ). The voltage drift expresses itself by, for example, a simultaneous increase or decrease of |V BE 1 | and |V BE 2 |. Control unit 241 (transistor 237, current source 235, voltage source 290 and comparator 280) compensates common mode drift according to a method of the present invention with the following steps: measuring a first voltage (|V EC 1 | or |V EC 2 |) at one electrode (e.g., E of 226) of one of bipolar transistors 216 or 226; linearly converting (e.g., by current source 235 and n-FET 237) the first voltage (|V EC 1 | or |V EC 2 |) to a second voltage V 3 which does not significantly influence the first voltage (|V EC 1 | or |V EC 2 |); providing a reference voltage (e.g., V DS REF by voltage source 290) which is related to the required input voltage (e.g., ≥ 2 * V DS SAT + V th ); and comparing the second voltage (e.g., V 3 ) to the reference voltage (e.g., V DS REF ) and changing the common voltage (e.g., |V B |) which controls bipolar transistors 216 and 226. In other words, control unit 241 shifts base-emitter voltages |V BE 1 | and |V BE 2 | without changing their values so that the input voltage at voltage transfer units 260 and 270 is substantially more than a saturation voltage V DS SAT and a threshold voltage V th of n-FETs so that the FETs operate in a saturation region. It is an advantage of the present invention that in the step of providing the reference voltage, the reference voltage is derived from the threshold voltage V th of field effect transistors (e.g., n-FETs 293 and 295 of voltage source 290). It is a further advantage of the present invention that the supply voltage V supply can be as low as 0.7 volts to 0.8 volts. Spikes, for example, common mode signals coupled through the bipolar transistors (or otherwise) do not significantly influence the reference voltage V BG . When comparing a reference circuit of the present invention to prior art solutions, the following advantages of the present invention are apparent: (a) Resistors (such as R 1 and R 2 ) are located at the outputs of operational amplifiers. The bipolar transistors are de-coupled from the resistors and carry lower current loads. (b) The bipolar transistors can be implemented with smaller dimensions, thus saving chip space and, due to smaller capacitances, substantially preventing spikes from penetrating. (c) The supply voltage can be reduced to e.g., 0.7-0.8 volts. (d) The reference circuit can be used for modem low-voltage applications (e.g., CMOS circuits).

Claims: A reference circuit (200) characterized by : a first transistor (216) with a first current I 1 and a first current density J 1 , providing a first base-emitter voltage |V BE 1 |; a second transistor (226) with a second current I 2 and a second current density J 2 , providing a second base-emitter voltage |V BE 2 |; a first voltage transfer unit (260) coupled to said first transistor (216); a second voltage transfer unit (270) coupled to said second transistor (226); a first resistor (210) having value R 1 coupled to an output of said first voltage transfer unit (260) and to an output of said second voltage transfer unit (270) so that a third current I R1 = (|V BE 1 | - |V BE 2 |)/R 1 flows through said first resistor (210) without substantially being derived from said first current I 1 or from said second current I 2 ; and a second resistor (220) having value R 2 coupled to the output of said first voltage transfer unit (260) so that a fourth current I R2 flows through said second resistor (220) without substantially being derived from said first current I 1 , in said reference circuit (200), said third current I R1 and said fourth current I R2 being added and provided as reference current I M . The reference circuit (200) of claim 1 wherein said values R 1 , R 2 , J 1 , and J 2 being selected in such a way that said third current I R1 and said fourth current I R2 have substantially equal, but inverted temperature coefficients: dT I R1 / dT ≈ - dT I R2 / dT. The reference circuit (200) of claim 1 further having a current mirror (240) and a third resistor (230) having value R 3 wherein said reference current I M is mirrored to said third resistor (230) so that an output voltage is available across said third resistor (230), said output voltage substantially not influencing said reference current I M . The reference circuit (200) of claim 1 wherein said first voltage transfer unit (260) and said second voltage transfer unit (270) both comprise n-channel field effect transistors (251, 252, n-FETs) coupled to said first transistor (216) and to said second transistor (226) by gate electrodes, respectively, said n-FETs (251, 252) operating in an active region with V GS > V th + V DS SAT with V GS being gate-source voltages, V th being a threshold voltage, and V DS SAT being a saturation voltage. The reference circuit (200) of claim 1 wherein said first and second voltage transfer units (260, 270) have input stages with n-channel field effect transistors (251, 252, n-FETs), and wherein at least one of said first or second voltage transfer units (260, 270) receives a control voltage which is substantially equal to a saturation voltage V DS SAT of said n-FETs. The reference circuit (200) of claim 1 wherein said first and second voltage transfer units (260, 270) comprise n-channel field effect transistors (251, 252, n-FETs) and wherein said reference circuit (200) further comprises a control unit (241) coupled to one of said first and second voltage transfer units (260, 270) and so said first and second transistors (216, 226), said control unit (241) shifting said first and second base-emitter voltage |V BE 1 | and |V BE 2 | without changing their values so that the input voltage at said first and second voltage transfer units (260, 270) is substantially more than a saturation voltage V DS SAT and a threshold voltage V th of n-FETs so that said FETs operate in a saturation region.

Inventors: AFEK YACHIN, KOIFMAN VLADIMIR, AFEK, YACHIN, KOIFMAN, VLADIMIR
Applicants: FREESCALE SEMICONDUCTOR INC, FREESCALE SEMICONDUCTOR, INC.
Application year: 1998
Main classification: G05F3
IPC codes: G05F3