Symbol synchronization in multicarrier receivers

Abstract: Improved synchronization of OFDM signals is achieved. A controlled oscillator (8) provides clock pulses to derive complex samples of an input signal which are applied both to a fast Fourier transform (5) for data recovery and to a synchronization unit (9). The synchronization unit generates the complex product XY* of the input and the delayed input, which is applied to a high-pass filter (30) to suppress frequencies below the symbol frequency. The filter output is applied through a symbol comb filter (40) to an adaptive slicer (50) which determines the larger magnitude of the real and imaginary components of the signal. A pulse processor (60) generates a single pulse at the leading edge of the symbol pulse which is applied to a symbol counter (70). The symbol counter includes two count stages arranged to lock in quickly and yet be variable to accommodate different guard intervals in the OFDM signal.

Description: Background of the Invention This invention relates to apparatus for extracting information from a signal which consists of a succession of symbol periods each consisting of an active symbol period and a guard interval. In particular the invention is applicable to Orthogonal Frequency Division Multiplex (OFDM) signals, such as may be used for broadcasting digital television signals in the uhf (ultra high frequency) bands, or for digital audio broadcasting (DAB). The form of OFDM signal proposed for this purpose consists of data signals and reference information modulated as QPSK (quadrature phase shift keying) or QAM (quadrature amplitude modulation) on to several thousand individual carriers, evenly spaced in frequency and occupying a total bandwidth of several Megahertz in the uhf spectrum. The data signal on each carrier has a relatively long symbol period and this, in part, gives the signal its good performance in conditions of multipath propagation. The multipath performance is further enhanced by the inclusion of a guard interval in which a portion of the modulated signal waveform taken from the end of each symbol is also included at the beginning of the same symbol period. Different fractions of the basic symbol period, such as 1/32, 1/16, 1/8 or 1/4, can be used in this way to provide immunity to multipath distortion of increasingly long delays. More specifically, each symbol is extended by a period T G (the guard interval) which precedes the "useful" or "active" symbol period T S , so that the whole symbol now lasts T T in total. T S is the reciprocal of the carrier spacing f s , and is the duration of the time domain signal produced or analysed by the FFT (fast Fourier transform) in the transmitter and receiver respectively. Each carrier is continuous over the boundary between the guard interval and the active part of the same symbol, keeping the same amplitude and phase. If the signal at complex baseband is considered, with all the carrier frequencies not only spaced f s , but also equal to multiples of f s , then the signal in the guard interval is effectively a copy of the segment of the signal occupying the last T G 's worth of the active part, as shown in Figure 4 of the accompanying drawings. It follows that the signal has the same value at any two instants which are separated by T S but lie within the same symbol. Specific proposals for synchronization of OFDM receiving apparatus have been published for example in European Patent Applications EP-A-0 653 858 and 0 608 024, and International Patent Applications WO95/07581, WO95/05042 and WO95/03656. The principal requirement for synchronization in a receiver is to obtain from the signal waveform a reliable time synchronization pulse related to the start of the symbol period. Such a pulse could then be used to start, at the correct position in the waveform, the process of Fourier transformation which accomplishes a major portion of the demodulation process. A second requirement for synchronization is to lock the digital sampling clock in the receiver to an appropriately chosen harmonic of the symbol period. However, the modulated OFDM waveform produced by adding together all the modulated carriers is essentially noise-like in nature and contains no obvious features such as regular pulses which could be used to synchronize the circuitry of a receiver. Because of this, we have previously proposed techniques for synchronization which are based on correlation of the signal with a version of itself delayed by the basic symbol period. The similarity between the portion included to form the guard interval and the final part of the basic symbol is then shown as a region of net correlation, while the remainder of the symbol period shows no correlation. Even so, the correlated waveform still reflects the noise-like nature of the signal waveform and can be impaired by signal distortions, so it is necessary to process the signal further to obtain reliable synchronization. Our European patent application No. 96307964.5, publication No. 0 772 332 (publication date 7 May 1997), describes the use of a correlator with a filter which exploits the periodicity of the waveform to form a complex symbol pulse and then uses the argument of the pulse to obtain frequency control for a local oscillator. In addition, the modulus of the pulse signal is used to derive a pulse related to the start of the symbol period and to derive a signal to control the clock frequency in the demodulator. A complex integrate-and-dump technique is included in the clock loop to suppress interference. Attention is also drawn to a paper by T. Keller and L. Hanzo "Orthogonal Frequency Division Multiplex Synchronisation Techniques for Wireless Local Area Networks", IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, Taiwan, October 1996, XX, Vol. 3, pages 963-967. Summary of the Invention The present invention is defined in claim 1 below, to which reference should now be made. Advantageous features of the invention will be described in more detail by way of example with reference to the drawings. A preferred embodiment of the invention is described in more detail below. The preferred embodiment also uses correlation and a filter which exploits the periodicity of the waveform to form a symbol pulse, but additionally employs an adaptive slicing technique based on the modulus and the argument of the symbol pulse waveform in order to extract timing information from the pulse. Thus, the magnitude alone is not used, as this would give inferior results. As a further development of this, we have recognised that an approximation to the correct phase can be used initially, as once the system has locked correctly to the incoming signal, the desired phase will become aligned with the real axis, and this can thereafter be assumed to be the correct phase or argument. The present improvement can with advantage be used together with the improvements of the parent application EP-A-0 876 031 and sister application EP-A-1 267 539. Brief Description of the Drawings The invention will now be described in more detail, be way of example, with reference to the accompanying drawings, in which: Figure 1 is a block circuit diagram of the relevant part of an OFDM receiver embodying the invention; Figure 2 is a block circuit diagram of the synchronization unit of the receiver of Figure 1; Figure 3 is a block circuit diagram of the adaptive slicing circuit of the synchronization circuit in the receiver of Figure 1; and Figure 4 (described above) is a diagram showing how each symbol comprises an active symbol and a guard interval, and illustrates the relationship between them. Detailed Description of the Preferred Embodiment The system will be described using parameter values from a particular system of digital OFDM signal transmission by way of example. More details of this system are contained in ETSI draft document prETS 300 744, November 1996, now document ETS 300 744 dated March 1997. The relevant parts of an OFDM receiver embodying the invention are shown in block diagram form in Figure 1. The receiver has a uhf input 1 which applies a received signal to a down-converter 2. The output of the down-converter is applied to an a-d (analog-to-digital) converter 3 which receives a clock input from a voltage-controlled crystal oscillator 8 and supplies an output to a real-to-complex converter 4. The output of the real-to-complex converter 4 is applied first to a Fourier transform circuit, such as a well-known FFT (fast Fourier transform), and also to a synchronization unit 9. The output of the Fourier transform circuit is applied to data recovery circuitry 6, based on that in a known OFDM receiver, to provide a data output at 7. The synchronization unit 9 has two outputs, namely an output 10 which is coupled to the Fourier transform circuit 5, and an output 11 which is applied to the controlled oscillator 8. Finally, the synchronization unit 9 receives the clock signal from the controlled oscillator 8. The operation of the circuit of Figure 1 is as follows. A received uhf OFDM input signal at the input 1 is down-converted by frequency shifting in the down-converter 2 to occupy a bandwidth of nominally 8MHz in the region 0-9MHz. It is then sampled by the a-d converter 3, operating with a sampling frequency of 18·285714 MHz from the voltage-controlled crystal oscillator 8. The real samples from the a-d converter are converted by the real-to-complex converter 4 into the form of complex samples at 9·142857 MHz required for Fourier transformation in the Fourier transform circuit 5. As each complex sample consists of real (R) and imaginary (I) components, it is convenient to multiplex the two together in a sequence R 1 I 1 R 2 I 2 ... thus retaining the 18·285714 MHz rate of the data stream. Accordingly, the synchronization unit 9 accepts the OFDM signal waveform as a series of complex samples which are then processed to produce a series of regular symbol pulses at output 10 to start the transform at the appropriate time in the symbol. Additionally, the synchronization unit can provide a signal at output 11 to lock the controlled oscillator 8. This is achieved by comparing the timing of regular symbol pulses which are produced by dividing the sampling clock by an appropriate ratio, with the timing of the symbol pulses extracted from the incoming signal waveform. The main elements of the synchronization unit 9 are shown in Figure 2. Referring to Figure 2, the complex input from the real-to-complex circuit 4 is applied to an input terminal 21 and thence to a delay 20 with a duration equal to the basic symbol period T S and to a conjugating circuit 24. The conjugating circuit 24 forms the complex conjugate of each sample by inverting the imaginary part. The outputs of the delay 20 and conjugating circuit 24 are both applied to a full four-component complex multiplier 22. Thus, the multiplier provides an output XY*, where Y is the input signal, X is the signal Y after the delay 20, and the asterisk (*) indicates the complex conjugate. The delay 20, conjugating circuit 24 and multiplier 22 operate as a correlator, as described in our above-mentioned European patent application No. 96307964.5. The output of the multiplier 22 is applied to a high-pass filter circuit 30, the output of which is applied to a symbol-period comb filter 40. The output of the filter is then applied to an adaptive slicing circuit 50 the output of which in turn is applied to a pulse processing circuit 60. The output of the pulse processing circuit 60 is then applied to a symbol counter 70. The operation of the synchronization circuit shown in Figure 2 is as follows. The noise-like OFDM signal in complex form is applied to the delay 20 with a duration equal to the basic symbol period, and to the conjugating circuit 24 which forms the complex conjugate of each sample by inverting the imaginary part. The correlation between the two signals is produced by the complex multiplier 22 and appears as a noisy pulse waveform at symbol rate. It should be recognised that the conjugation process 24 can alternatively be placed in the delayed signal, that is in series with the delay 20, with equal effectiveness. That is, the signal YX* is generated rather than XY*. The high-pass filter circuit 30 is included to remove complex-valued offsets introduced by interference. This is followed by the symbol-period comb filter 40, which exploits the periodic nature of the waveform to suppress noise and other impairments so as to produce a rectangular pulse, the duration of which is related to the guard interval. It should be noted that the comb filter 40 could be placed before the high-pass filter 30 with similar effectiveness. The adaptive slicing circuit 50 is used to prepare the complex waveform for slicing at the most advantageous point, taking account of the effects of local oscillator frequency errors, amplitude variations, and distortions arising from multipath propagation. This circuit 50 is followed by the pulse processing circuit 60, which generates a single pulse at the leading edge of the symbol pulse, and prevents the generation of spurious pulses which might arise from multiple crossings of the slicing level in a noisy signal. The timing of the pulses produced by the pulse processing circuit 60 is compared with the timing of pulses produced by dividing the sampling clock frequency down to symbol rate in the symbol counter 70. The comparison produces a signal at output 11, which is used to control the clock oscillator 8. Regular appropriately-timed symbol rate pulses at output 10 are derived from the symbol counter 70 and are used to start the Fourier transform processing on each symbol. The pulses from the pulse processing circuit 60 are also used for initial resetting of the symbol counter 70 during lock-up; but after the initial period, adjustment of the position of the pulses at output 10 is obtained only by controlling the sampling clock frequency. This ensures that the number of clock periods between symbol pulses remains constant, which is necessary for simplifying the operation of subsequent processing in the data recovery circuitry 6 in Figure 1. The operation of the adaptive slicer 50 of Figure 2 will now be described in more detail. For a description of the circuits 30, 40, 60 and 70, see EP 876 031A. The basis of the adaptive slicer 50 shown in Figure 3 is the recognition that, if the plane of the argument of the symbol pulse is close to either the real axis or the imaginary axis, then that signal component represents a good approximation to the signal in the plane of the pulse. The method then consists of determining which axis is closer to the required plane and selecting the corresponding signal component. Initially this constitutes only an approximation to the correct value, but it is good enough to start the lock-in process. Furthermore, it is recognised that, after the initial lock-up period, the plane of the symbol pulse will lie along the real axis, so that the simplified method then becomes equivalent in performance to the optimum approach. In more detail, the method is as follows. After a small degree of low-pass filtering of the signal from the symbol comb filter 40 in a filter 510 to smooth off peaks in the top of the pulse waveform, the components of the complex signal time-multiplexed real and imaginary samples are converted to sign-and-magnitude representation in a circuit 51. The magnitudes of the real and imaginary values are then individually compared by a subtractor 52 with real and imaginary values previously stored in a pair of registers 57 acting as a store. The sign bit resulting from the subtraction in subtractor 52 is used to control a selector 56 having two inputs A and B respectively. The control is such that, if the input is less than the stored value from registers 57, input B is selected, while if the input is greater than or equal to the stored value, input A is selected. Input B selects the stored value through a decrementing circuit 55, which is connected to the output of the registers 57. The decrementing circuit 55 occasionally subtracts 1 from the stored magnitude so that, if input B remains selected, the stored values are gradually reduced. The input A of the selector receives the output of the subtractor 52 after division by four in a shift circuit 53 and addition in an adder 54 to the output of the registers 57. If input A is selected, adder 54 adds one-quarter of the amount by which the input exceeds the stored value produced by subtractor 52 and shifter 53 to the stored value, thus rapidly acquiring a value near to the peak value without completely following individual noise spikes. In each case, the sign associated with the individual real and imaginary samples is also selected by selector 56 and stored in registers 57. Thus, registers 57 contains values that are representative of the peak real and imaginary values of the symbol pulse. These values are compared in a comparator and selection circuit 58, which determines whether the real or the imaginary component has the greater peak magnitude, and controls the enabling of a register 511 which is connected to the output of the filter 510 so as to select either all the real samples from the input or all the imaginary samples, as appropriate. Also, circuit 58 selects the sign of the stored value with the greater magnitude and uses this to control the inversion of the input signal samples in a true/invert unit 512. The output of unit 512 thus always provides the larger of the real and imaginary signal components, with a positive-going excursion for the symbol pulse. A further output of circuit 58 provides the larger of the two stored magnitudes, which is multiplied by a factor of one-quarter by a shifter 59, to be subtracted from the pulse waveform produced by unit 512 in a subtractor 513. A factor of one-quarter is used, rather than one-half, so that if the pulse is distorted by the presence of a large echo so as to have a step in the rising edge, the slicing process still reliably detects the earliest part of the edge. The slicing process then consists simply of taking the sign of the output signal 514 to provide the separated two-level symbol pulse waveform. Thus, the adaptive slicer operates by initially selecting whichever has the greater magnitude of the real and imaginary parts of the complex signal, and using this as an approximation to the correct argument or phase, which will typically be somewhere in-between the two. After a while, the rest of the circuitry will lock in to the incoming signal so that the desired phase becomes aligned with the real axis. Thus after a time the detected signal will be essentially exactly what is desired and not just an approximation to it. It should be noted that if frequency correction of the received signal (AFC) is accomplished by digital circuitry placed after the time synchronisation circuitry, then the approximate value will always be used, but adequate performance can still be achieved. In a modification, indicated in dashed lines on Figure 3, the magnitudes of the real and imaginary values are compared in subtractor 52 with positive or negative real and imaginary values previously stored in a set of four registers 57. The sign of each incoming sample, positive or negative, is used to select either a positive stored magnitude or a negative stored magnitude, respectively, for comparison. The registers 57 then contain values that are representative of the positive and negative peak real and imaginary values of the symbol pulse. In this case the circuit 58 detects whether the positive or negative stored value of the larger of the real and imaginary values has the greater magnitude, and controls the true/invert unit 512 accordingly. The output of circuit 58 which is applied to shifter now provides the difference between the positive and negative stored values for the larger of the real and imaginary magnitudes. While one example of the invention has been described, it will be appreciated that many variations may be made in the implementation of the invention.

Claims: Apparatus for extracting information from a signal which comprises a succession of symbol periods T T each consisting of an active symbol period T S and a guard interval T G , the apparatus comprising: means (21) for receiving an input signal Y; means (20) for providing a signal X delayed by a time period equal to the active symbol period T S ; and means (22,24) for forming a signal related to the complex product XY* or X*Y of the input signal and the delayed signal to provide a succession of pulses, one for each symbol period; characterized by means (50) for determining the larger magnitude of the real and imaginary components of the signal related to the complex product and selecting the larger one as an output. Apparatus according to claim 1, including clock means (8) for generating clock signals for use in extracting the information from the input signal, and in which the output of the magnitude determining means (50) is applied to the clock means to control the synchronization of the clock means. Apparatus according to claim 1, including Fourier transform means (5) operating on a signal derived from the input signal, and in which the output of the magnitude determining means (50) is applied to the Fourier transform means to control the timing of the Fourier transform operation. Apparatus according to claim 1, in which the magnitude determining means comprises storage means (57) and selector means (56) arranged as part of a recursive loop, the loop selectively combining the value held in the storage means and an input value in predetermined proportions, or recirculating the value held in the storage means, in dependance upon whether the input value or the value held in the storage means is the greater. Apparatus according to claim 1, including, coupled between the signal forming means and the determining means, means (30) for high-pass filtering the signal related to the complex product to suppress frequencies below the symbol frequency.

Inventors: CLARKE CHRISTOPHER K P, ROBINSON ADRIAN P, STOTT JONATHAN H, CLARKE, CHRISTOPHER K.P., ROBINSON, ADRIAN P., STOTT, JONATHAN H., Clarke, Christopher K.P., British Broadcasting Cor, Robinson, Adrian P., c/o British Broadcasting Corp, Stott, Jonathan H., c/o British Broadcasting Corp.
Applicants: BRITISH BROADCASTING CORP, BRITISH BROADCASTING CORPORATION
Application year: 1998
Main classification: H04L27
IPC codes: H04N5, H04N7, H04L27