METHOD AND APPARATUS FOR LOGICAL ADDRESSING IN A MODULAR PATIENT CARE SYSTEM

Abstract: A modular patient care system is described having unique mechanical, electrical, and logical features. An apparatus is described for allowing a modular connecting arrangement wherein modules (102, 104A - 104D) are detachably connected to each other in a convenient, flexible, interchangeable, secure manner by providing a hinge connector pair, a specially located latch mechanism, and a guide means between any pair of modules. Additionally, an apparatus, and method is described for automatic, sequential, and dynamic logical address assignment of functional units attached to the central management unit according to their respective position in a linear array of units. Logical address assignment is designed to occur automatically upon a physical reconfiguration of the functional units, without requiring external input, or a prearranged scheme for determining the relative physical positions of the functional units.

Description: METHOD AND APPARATUS FOR LOGICAL ADDRESSING IN A MODULAR PATIENT CARE SYSTEM CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation-in-part of U.S. Pat. App. Ser. No. 08/403,503, entitled "Modular Patient Monitoring and Infusion System," filed March 13, 1995 and assigned to the assignee of the present invention. The subject matter of U.S. Patent Application Serial No. 08/403,503 is incorporated herein by reference. This application also contains subject matter related to copending U.S. Pat. App. Ser. No. 08/871,307 filed concurrently herewith entitled "Method and Apparatus for Power Connection in a Modular Patient Care System, " both assigned to the assignee of the present invention. The subject matter of this application is also incorporated herein by reference. FIELD OF THE INVENTION The present invention relates generally to modular patient care systems. More specifically, the present invention relates to modular connection arrangement wherein modules are detachably connected to each other in a convenient, flexible, interchangeable, and secure manner. Additionally, the present invention relates to a scheme for automatic, sequential, and dynamic logical address assignment of peripheral units attached to the central management unit. BACKGROUND OF THE INVENTION Systems containing multiple infusion pumping units, sensing units such as blood pressure monitors and pulse oximeters, and other patient-care units are known in the medical field. For example, Kerns et al (U.S. Pat. No. 4,756,706; "Kerns") discloses a centrally managed pump system in which pump and monitoring modules are selectively attached to a central management unit . The central management unit controls the internal setup and programming of the attached modules, and receives and displays information from them. Each module is capable of being detached from the central management unit except for the first module, which is permanently attached. Once attached and programmed, a module which is subsequently detached is still capable of operating independently of the management unit . Kerns provides for each module having its own separate cable leading to the central management unit, this cable comprising Incoming Communication and Outgoing Communication connections (Kerns col. 5, lines 11-19) . The cable for each unit achieves separate contact with the central management unit by means of pass-through structures built in to each module (Kerns Fig. 4f) . Thus, the central management unit is automatically aware of the relative position of a given module in the stack by virtue of the physical port to which it is connected (Kerns col. 5, lines 32-36) . Kerns has several disadvantages. Because each module requires its own set of electrical paths to the central unit, the total number of modules which may be stacked is only one greater than the number of pass-through cables in each module. For example, for the pass-through structure shown in Kerns Fig. 4f , only four modules total may be accommodated by a system which uses these modules. Also, there is added weight, cost, and complexity due to the multiple cabling structure. For example, each signal of each cable must have its own contact pin in among the pins 122 of the contact structure of Kerns Fig. 3. Rubalcaba (U.S. Pat. No. 4,898,578) also discloses a drug infusion system which includes a plurality of infusion pump modules selectively attached to a central management unit so as to provide for centralized control. In particular, the central management unit obtains infusion parameters from the user and then performs calculations with the parameters to establish the desired infusion rate. Once this rate is determined, the central management unit may control the infusion accordingly. Rubalcaba, however, provides no solution for the problems related to electrical and mechanical connectivity of units described above with respect to Kerns . It has been found that a common communications bus scheme provides for lesser complexity of the modular patient care system. At the same time, however, in a system not having separate communications connections from the central unit to each peripheral module, a logical addressing scheme is necessary for identification of the peripheral units according to their physical location in the system. It is desirable that external user input not be required to achieve this identification and logical addressing. Barbour et al (U.S. Pat. No. 3,949,380) discloses a peripheral device reassignment control technique, wherein a plurality of peripheral devices having physical addresses are accessed by a host processor by use of logical addresses which are utilized by the various programs in a multiprocessing environment. This disclosure, however, is simply related to the mapping of logical addresses into physical addresses to access peripheral devices. The disclosure presumes the existence of physical addresses for each of the peripheral devices, and therefor obviates the need for detecting the physical location of the peripheral devices for sequential logical address assignment. Accordingly, it an object of the present invention to provide a modular patient care system wherein modules are detachably connected to each other in a convenient, flexible, interchangeable, and secure manner. It is another object of the present invention to provide a scheme for sequential and dynamic logical address assignment of peripheral units attached to the central management unit in a modular patient care system having a common communications bus arrangement. It is yet another object of the present invention to provide for automatic address assignment of peripheral units without the need for external user input or a predetermination regarding the relative physical location of the peripheral devices. SUMMARY OF THE INVENTION These and other objects of the present invention are provided for in a modular patient care system having an interface unit for providing a user interface to said system and at least one functional unit, the functional unit being capable of removable connection to the interface unit for providing patient therapies or monitoring the condition of the patient, the functional unit being for removable attachment to the interface unit or other functional units so as to form a linear array of units. The linear array of units forms a common communications bus for allowing high level communication between each functional unit and the interface unit according to a unique sequential logical ID assigned to each functional unit. The linear array of units comprises an originating end and a terminating end, and each unit has an originating side and a terminating side, the originating side of any unit being capable of removable connection to the terminating side of any other unit. In one embodiment, the originating end is the left end, and the terminating end is the right end of the linear array. In accordance with the present invention, a method and apparatus is provided wherein the modular patient care system is capable of having the interface unit automatically and dynamically assign sequential logical ID'S to the attached functional units according to their respective positions in the linear array of units. The assignment is automatic in that it does not require instructions by a user as to the relative positions of the units in the linear array. The interface unit and functional units are configured and dimensioned so as to be capable of performing a series of steps to automatically and dynamically assign the sequential logical ID'S. Generally, each functional unit has a unit detect bus portion for forming a unit detect bus. In particular, the unit detect bus portion forms a left unit detect bus, terminating at a left unit detect lead of the interface unit, for functional units attached to the left of the interface unit. However, the unit detect bus portion is bidirectional in that when the functional unit is attached to the right of the interface unit, a right unit detect bus is formed, terminating at a right unit detect lead of the interface unit. Each functional unit is capable of pulling its respective unit detect bus logically low, the unit detect bus being coupled to a pullup resistor at the interface unit, the pullup resistor in turn being connected to a constant voltage source. Each functional unit also has an ID enable in lead at its left side and an ID enable out lead at its right side. The value of signals contained on these leads may be ENABLE or DISABLE. In one embodiment, ENABLE corresponds to a logic high value, whereas DISABLE corresponds to a logic low value. The interface unit also comprises an ID enable out lead at its right side. A key feature of each functional module is that it is designed and configured such that the ID enable in lead takes on the value of the ID enable out lead of a left adjacent unit, unless the functional unit is at the left end of the array. If the unit is at the left end of the array, the ID enable in lead automatically takes on the value ENABLE, by means of a pullup resistor connected between the ID enable in lead and a constant voltage source at the level ENABLE. Upon receiving a first command from the interface unit over the common communications bus, all functional units set ID enable out to DISABLE and pull their respective unit detect buses low. At this point, the leftmost unit is the only functional unit which (1) detects a value ENABLE at its ID enable in lead, and (2) has not yet been assigned a logical ID after receiving the first command. The leftmost unit sends a ready-for-ID message to the interface unit over the common communications bus. In response, the interface unit sends out a sequential logical address over the common communications bus, this address being received by the leftmost unit. After receiving the logical ID, the leftmost functional unit releases its respective unit detect bus and sets its ID enable out lead to ENABLE. At this point, the next adjacent functional unit is the only functional unit which (1) detects a value ENABLE at its ID enable in lead, and (2) has not yet been assigned a logical ID after receiving the first command. The next adjacent functional unit sends a ready-for-ID message to the interface unit over the common communications bus, the interface unit sends out a sequential logical address, and the next adjacent functional unit releases its respective unit detect bus and sets its ID enable out lead to ENABLE. When all functional units on the left side of the interface unit have been assigned logical ID'S, the interface unit is so notified by detecting the releasing of the left unit detect bus. At this point, the ID enable out lead at the right side of the interface unit is set to enable. In response, the adjacent functional unit on the right side of the interface unit, if any, sends a ready-for-ID message to the interface unit over the common communications bus. The logical ID'S continue to be sequentially assigned in this manner until the rightmost unit has received its logical ID and releases the right unit detect bus. The interface unit is notified that the assignment of logical ID'S is complete when the right unit detect bus is so released. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a front view of a multi-module electronic system wherein the individual modules are interconnected electrically and structurally in accordance with the present invention; FIG. 2 shows an oblique view of two modules showing structural and electrical features for module connection in accordance with the present invention; FIG. 3 shows a functional diagram of the unit identification and logical address provision features of the interface unit according to the present invention; FIG. 4 discloses a functional circuit diagram of the unit identification and logical address provision features of a functional unit in accordance with the present invention; FIG. 5 shows a high-level functional block diagram of the inter-unit communications features of a modular patient care system according to the present invention; FIGS. 6A and 6B show a functional schematic diagram of the unit detection and unit identification features of a modular patient care system in accordance with the present invention; FIGS. 7, 8, 9A and 9B, and 10 illustrate steps performed by the interface unit for unit identification and logical ID assignment in accordance with the present invention; FIGS. 11 and 12 illustrate steps performed by a functional unit of a modular patient care system in accordance with the present invention. DETAILED DESCRIPTION OF THE INVENTION The following embodiments of the present invention will be described in the context of a modular patient care system, although those skilled in the art would recognize that the disclosed methods and structures are readily adaptable for broader application. Note that whenever the same reference numeral is repeated with respect to different figures, it refers to the corresponding structure in each figure. FIG. 1 discloses a modular patient care system 100 in accordance with the present invention. Modular patient care system 100 comprises a plurality of modules or units, including interface unit 102 and functional units 104, detachably coupled to each other to form a linear array. Shown in FIG. 1 are exemplary functional units 104A, 104B, 104C, and 104D coupled to interface unit 102. While four functional units are shown in FIG. 1, a modular patient care system in accordance with the present invention may comprise interface unit 102 coupled to only a single functional unit 104, or may comprise interface unit 102 coupled to as many as "N" functional units 104. Interface unit 102 generally performs the functions of (1) providing a physical attachment of the system to structures such as IV poles and bedrails, (2) providing electrical power to the system, (3) providing an interface between the system and external devices, (4) providing a user interface to the system, and (5) providing overall system control, which includes providing information to and receiving information from functional units 104. Shown in FIG. 1 are certain user interface aspects of interface unit 102, which may include an information display 106, numerical hardkeys 108, and softkeys 110. Functional units 104 are generally for providing patient therapies or monitoring responsive to information, at least some of which may be received from interface unit 102. In many cases, functional units 104 are also for communicating information to interface unit 102. For example, functional unit 104A may be an infusion pump unit for delivering fluids to a patient responsive to certain commands received from interface unit 102, while functional unit 104B may be a blood pressure monitoring unit for providing patient blood pressure information to the interface unit 102. The scope of the invention is not so limited, however. For the purposes of the present invention, the specific function of each individual functional unit 104 is not critical. Rather, the present invention is directed toward (1) the mechanical and electromechanical coupling of the functional units 104 to each other and to interface unit 102, and (2) the inter-unit detection and communications scheme of the modular patient care system 100. Thus, for purposes of understanding the present invention, it is important only to recognize that functional units 104 (1) require means for detachably coupling to each other and to interface unit 102, and (2) require means for communicating with interface unit 102. In a preferred embodiment of the present invention, interface unit 102 and functional units 104 are laterally interchangeable. By laterally interchangeable, it is meant that the modules may be placed in any order in forming a linear array of modules. Thus, in FIG. 1, the modular patient care system 100 may instead have its modules ordered left-to-right in the sequence 104C, 102, 104B, 104D, 104A without affecting its functionality. In order to be laterally interchangeable, the units 102 and 104 of FIG. 1 should have substantially identical interconnection features on their respective left sides, and should have corresponding substantially identical interconnection features on their right sides. If the units were instead for coupling in a vertical linear array, which is within the scope of the present invention, the interconnection features would have substantially identical interconnection features on their respective top sides, and would have corresponding substantially identical interconnection features on their bottom sides. For clarity of explanation, however, only a left-to-right physical arrangement is described. To achieve the lateral interchangeability described above, each of the units 102 and 104 should also have power, unit detection, and communication circuitry which is complementary. By complementary, it is meant that the units 102 and 104 generally have power, unit detection, and communications circuit contacts on a first side and on a second side, and that the first side contacts of one unit may be connected to corresponding second side contacts of any other unit, with the overall linear array of units comprising modular patient care system 100 being fully operational. In FIG. 1, for example, the first side of a unit is the left side, and the second side of a unit is the right side. Further to this example, and as further explained later, functional unit 104C must be capable of receiving electrical power from interface unit 102 to its left and transferring it to unit 104D to its right; yet, if physically interchanged with functional unit 104B, unit 104C must be capable of receiving electrical power from interface unit 102 to its right and transferring it to unit 104A to its left, and so on. As shown in FIG. 1, each functional unit 104 may include a unit ID indicator 112 which identifies a logical address of the functional unit within the linear array. The logical address of a functional unit 104 indicates its position in the linear array relative to other functional units 104. The logical address of a functional unit 104, such as unit 104B, is used by the interface unit 102 to identify and uniquely communicate with functional unit 104B in a common communications bus environment to be described later. In a preferred embodiment of the invention, the logical address of a functional unit corresponds to its sequential position in the linear array of functional units. Thus, the system shown in FIG. 1 may illustratively contain functional units 104A- 104D with logical addresses A, B, C, and D, ordered left to right. In this embodiment, the left side of the leftmost unit forms an originating end of the linear array, while the right side of the rightmost unit forms a terminating end of the linear array. Also in a preferred embodiment of the invention, the logical address of a functional unit 104 is position- dependent, not unit-dependent . Thus, for example, in FIG. 1, if the positions of functional units 104B and 104C were physically interchanged in the linear array, the logical address of unit 104B would be changed to C, and the logical address of unit 104C would be changed to B, such that the left-to-right order of logical addresses would remain A, B, C, and D. FIG. 2 illustrates mechanical and electromechanical aspects of interface unit 102 and functional units 104 in accordance with the present invention. For purposes of the mechanical and electromechanical aspects of the invention, 5 interconnection features of interface unit 102 are similar to interconnection features of functional units 104 and thus only an exemplary unit 104A will be described. Also, an exemplary unit 104B, substantially identical to unit 104A and for connecting thereto, will be described when needed for 10 clarity. FIG. 2 shows an oblique representation of exemplary units 104A and 104B positioned before being matably connected. As shown in FIG. 2, unit 104A comprises a chassis 200 having a left side 202, a front 204, and a right side 15 206. It is to be appreciated that although Fig. 2 shows numbered components on units 104A and 104B according to their visibility in the oblique drawing, the units 104A and 104B contain substantially identical numbered components. Unit 104A further comprises a male connector portion 208 on right 20 side 206, a female connector portion 210 on left side 202, a male elevation feature 212 formed on right side 206, a female recess feature 214 formed in left side 202, a catch feature 216 formed near on right side 206, and a latch 218 near left side 202. Unit 104A further comprises cover 220 tethered to 25 male connector portion 208 for covering the male connector portion 208 during periods of non-use, and pocket 222 formed in right side 206 near male connector portion 208 for receiving cover 220 otherwise. Unit 104A further comprises cover 224 tethered to female connector portion 210 for 30 covering female connector portion 210 during periods of non- use, and pocket 226 formed in left side 202 near female connector portion 210 for receiving cover 220 otherwise. Male connector portion 208 of unit 104A is positioned and formed for hingeable connection with female connector 35 portion 210 of unit 104B for achieving mechanical and electrical coupling of units 104 and 105. In a preferred embodiment of the invention, male connector portion 208 and female connector portion 210 also form a 15-pin electrical connector pair for electrically coupling. This electrical connector pair is for electrically coupling electronic components contained in units 104A and 104B. In accordance with the present invention, functional units 104 and interface unit 102 of FIG. 1 are provided with hardware and software components for allowing (1) automatic detection of attached functional units, (2) automatic assignment of unique logical addresses of attached functional units according to their sequential position in the linear array of units, and (3) automatic detection of detachment of functional units from the system. By automatic, it is meant that associated user input is not required. Thus, for example, in the system 100 shown in FIG. 1 which has been designed in accordance with the present invention, system 100 is capable of automatically assigning the logical addresses of A, B, C, and D to units 104A, 104B, 104C, and 104D, respectively, at initial power-up. Further, if an additional unit 104E (not shown) is later added to the right of unit 104D in the linear array while system 100 is operating, system 100 is capable of automatically assigning the logical address of E to the added unit 104E. If the additional unit 104E were instead added to the left of unit 104A, system 100 is capable of assigning a logical address of A to the added unit 104E, and capable of reassigning units 104A through 104D with the logical addresses B, C, D, and E, respectively. Finally, if one of the operating functional units 104 of FIG. 1 is removed inappropriately, system 100 is capable of sounding an alarm or entering an alarm state. By inappropriately, it is meant that interface unit 102 has not authorized removal of the removed unit responsive to a signal from the user or responsive to some other input, algorithm, or condition. Referring now to FIG. 3, interface unit 102 is shown comprising a microprocessor 600, a transmitter 902, a first communications bus portion 904, a receiver 906, a second communications bus portion 908, a unit detect pullup source 910, a left unit detect lead 912, a right unit detect lead 914, an ID enable in lead 916, an ID enable out lead 918, and pullup resistors 920 and 922. These elements will be described below along with the elements of exemplary 5 functional unit 104A as shown in FIG. 4, which comprises a microprocessor 700, a receiver 1002, a first communications bus portion 1004A, a transmitter 1006, a second communications bus portion 1008A, a unit detect bus portion 1010A, a pull-down transistor 1011, an internal pullup source 10 1012, and AND gate 1014, an ID enable in lead 1016, an ID enable out lead 1018, and a pullup resistor 1020. FIG. 5 shows a symbolic diagram of the inter-unit communications scheme of system 100 in accordance with the present invention. First communications bus portions 904, 15 1004A, 1004B, 1004C, and 1004D of units 102 and 104 form a transmit communications bus 1004 when all units are coupled together as shown in FIG. 1. Transmit communications bus 1004 originates at transmitter 904 of interface unit 102 and couples to receivers 1002 in functional units 104, and serves 20 as a path for information to travel from interface unit 102 to functional units 104. Second communications bus portions 908, 1008A, 1008B, 1008C, and 1008D of units 102 and 104 likewise form a receive communications bus 1008. Receive communications bus 1008 terminates at receiver 906 of unit 25 102 and couples to transmitters 1006 in functional units 104, and serves as a path for information to travel from each functional unit 104 to interface unit 102. The transmitters and receivers are each coupled to the microprocessor contained in their unit, as shown in FIG. 5. In general, the 30 inter-unit communications configuration described forms a multi-drop communications connection without collision detection, as is well known in the art. In a preferred embodiment of the invention, the transmitters and receivers conform to the RS485 protocol. Also in a preferred 35 embodiment, communications buses 1004 and 1008 are each a differential pair which allows rejection of common mode noise appearing on the signal pair. Further in a preferred embodiment of the invention, for single-fault mitigation, the transceivers and receivers on the interface unit 102 and functional units 104 are capable of switching from full- duplex operation, wherein communication on a single bus is unidirectional, to half-duplex operation, wherein communication on a single bus is bidirectional. While the communications buses 1004 and 1008 provide the general means for high-level communications among units, further circuitry and software to provide logical address assignments to the functional units because the communications buses are incapable of detecting the relative positions of the functional units 104 and interface unit 102 in the array of units. Means for achieving this result are described with reference to FIGS. 3, 4, 6A and 6B. Shown in FIG. 4 is a unit detect bus portion 1010A for coupling to the unit detect bus portions of other functional units 104 and for coupling to left unit detect lead 912 or right unit detect lead 914 of interface unit 102 (FIG. 3) . This coupling forms left and right unit detect buses 1200L and 1200R, as shown in FIGS. 6A and 6B . FIG. 3, in turn, shows unit detect pullup source 910 coupled through pullup resistors 920 and 922 to unit detect leads 912 and 914, respectively, for pulling up buses 1200L and 1200R, respectively (FIGS. 6A and 6B) . Finally, FIG. 4 shows pulldown transistor 1011 in exemplary functional unit 104A coupled to unit detect bus portion 1010A, and thus to unit detect bus 1200L. As shown, transistor 1011 is capable of pulling down unit detect bus 1200L or 1200R (FIGS. 6A and 6B) , depending on which side of interface unit 102 the functional unit 104 is on, responsive to a positive signal from a PULLDOWN lead of microprocessor 700, to which it is coupled. Operationally, then, any functional unit 104 is capable of pulling down unit detect bus 1200L or 1200R responsive to software instructions executed by its microprocessor 700. As shown in FIG. 3, interface unit comprises an ID enable in lead 916 and an ID enable out lead 918. ID enable out lead 918 is coupled to a UNIT_ID_ENABLE_R pin of a microprocessor 600 and is capable of going high or low according to instructions carried out within microprocessor 600. As shown in FIG. 4, exemplary functional unit 104A comprises ID enable in lead 1016 which is coupled to a CONNECT_SENSE pin of microprocessor 700 and to a first input of AND gate 1014. The AND gate 1014 also has a second input coupled to a UNIT_ID_ENABLE pin of microprocessor 700, which is capable of setting UNIT_ID_ENABLE high or low responsive to instructions carried out within microprocessor 700. The AND gate 1014 has an output coupled to ID enable out lead 1018, which is high only if both the ID enable in lead 1016 is high and UNIT_ID_ENABLE are high. ID enable in lead 1016 is also coupled to internal pullup source 1012 through pullup resistor 1020. A key feature of the present invention is that the resulting voltage at CONNECT_SENSE , and thus the first input of AND gate 1014, is in a high state and remains pulled up unless it is brought down by an external ground or "low" signal placed on ID enable in lead 1016. FIGS. 6A and 6B show the interconnections of the above signals and leads of the units 104 and 102 when attached in a linear array according to the present invention. As described above, left and right unit detect buses 1200L and 1200R are formed by the respective unit detect bus portions 1010 of functional units 104 and the unit detect leads 912 and 914 of interface unit 102. Further, for any adjacent pair of units, the ID enable in lead 1016 or 916 of the unit on the right is coupled to the ID enable out lead 1018 or 918 of the unit on the left. Importantly, the ID enable in lead 1016 or 916 of the leftmost (or originating) unit is left disconnected. The ID enable out lead 1018 or 918 of the rightmost (or terminating) unit is also left disconnected. Generally, a key to the present invention is that upon a change in configuration, a logical address is only assigned to a functional unit 104 if the microprocessor of that unit detects CONNECT_SENSE to be high. CONNECT_SENSE will only be high for (1) the leftmost unit, and (2) any unit whose ID enable in lead 1016 is not pulled down by the ID enable out lead 1018 or 916 of the unit to its left. In this way, and in a general sense, each functional unit 104 is assigned a sequential logical address by setting UNIT_ID_ENABLE to low, waiting for CONNECT_SENSE to go high, sending a ready-for-ID message to the interface unit 102 and receiving a logical address from the interface unit 102 by communicating over buses 1004 and 1008, and then setting UNIT_ID_ENABLE to high. A description of the sequence of steps carried out by microprocessor 600 of interface unit 102 and microprocessors 700 of functional units 104 follows. It is to be recognized in the following disclosure that microprocessor 600 of interface unit 102 is capable of sending commands to microprocessors 700 of functional units 104, and receiving responses from microprocessors 700, by means of the inter- unit communications circuitry described previously. Also, it is to be recognized that microprocessor 600 of interface unit 102 is capable of sensing the following signals: UNIT_DETECT_L corresponding to the voltage on left unit detect lead 912; UNIT_DETECT_R corresponding to the voltage on right unit detect lead 914; MODDETL corresponding to the voltage on left module detect lead 614; and MODDETR corresponding to the voltage on right unit detect lead 616. It is also to be recognized that microprocessor 600 is capable of creating a signal UNIT_ID_ENABLE_R and driving the voltage on ID enable out lead 918 according to this signal. Further, it is to be recognized in the following disclosure that microprocessor 700 of exemplary functional module 104A is capable of receiving commands and sending responses to microprocessor 600 of interface unit 102 by means of the inter-unit communications circuitry described previously. Also, it is to be recognized that microprocessor 700 is capable of sensing: the CONNECT_SENSE signal which corresponds to the voltage at ID enable in lead 1016 and at the first input of AND gate 1014; the signal MODDETL corresponding to the voltage at left module detect lead 714; and the signal MODDETR corresponding to the voltage at right module detect lead 716. Also, it is to be recognized that microprocessor 700 is capable of the following: driving the gate of transistor 1011 to low by means of a signal PULLDOWN, therefore pulling down unit one of unit detect buses 1200L or 5 1200R depending on which side of interface unit 102 the functional unit 104A is positioned; and generating the second input to AND gate 104 by means of a signal UNIT_ID_ENABLE. FIG. 7 illustrates steps carried out by microprocessor 600 of interface unit 102 in accordance with the present 0 invention. Beginning at step 1300, step 1302 is first performed. Step 1302 comprises steps, beyond the scope of the present disclosure but capable of being programmed by a person of ordinary skill in the art, wherein microprocessor 600 detects if the system 100 is in an initial power-up 5 state. Step 1302 further comprises steps wherein microprocessor 600 detects whether two functional modules 104 have been simultaneously added, one to each side of the linear array of units. This may be achieved, for example, by detecting simultaneous low values of UNIT_DETECT_L and 0 UNIT_DETECT_R, which are driven low by the added units as described later. If the system is at initial power-up or two functional units have been simultaneously added, step 1400, as described in FIG. 8, is performed, followed by a repeating of step 1302 according to FIG. 7. Otherwise, step 1304 is 5 performed. Step 1304 comprises the step of detecting whether a new functional unit has been added to the left side of the linear array of system 100. This is performed by detecting a low value for UNIT_DETECT_L, which is driven low by the added 0 unit as described later. If a unit has been added to the left, step 1500, as shown in FIGS. 9A and 9B, is performed, followed by a repeating of step 1302 according to FIG. 7. Otherwise, step 1306 is performed. Step 1306 comprises the step of detecting whether a new 5 functional unit has been added to the right side of the linear array of system 100. This is performed by detecting a low value for UNIT_DETECT_R, which is driven low by the added unit as described later. If a unit has been added to the right, step 1600, as described in FIG. 19, is performed, followed by a repeating of step 1302 according to FIG. 7. Otherwise, step 1308 is performed. Step 1308 comprises the step of detecting whether a functional unit has been detached from the left or right sides. The detachment of a unit may be detected by one or more of three methods. First, a communications time-out with a detached module over the inter-unit communications circuitry may be detected. Second, a change of state of MODDETL or MODDETL may be detected. Third, a high-level communications signal sent by the unit adjacent to the detached unit may be detected, in response to its own detection of a change of state of MODDETL or MODDETR. If a detachment of a functional unit has taken place, step 1310 is performed. Otherwise, step 1302 is performed again in accordance with FIG. 7. Step 1310 generally comprises the step of determining whether the system is currently in an operational state. If so, the system is placed in an alarm state by step 1312, wherein audio and/or visual alarms may be activated. Otherwise, if the system is not in an operational state, step 1314 is performed, wherein verification by a user is requested by means of visual and audible indications to the user. If verification is not received, the step 1312 alarm steps are followed. If verification is received, step 1314 is performed, wherein it is determined if the unit has been detached from the left. This information may already have been determined at step 1308. If a unit was detached from the left, step 1500, as shown in FIGS. 9A and 9B, is performed, followed by step 1302 according to FIG. 7. Otherwise, a unit has been detached from the right, wherein step 1318, comprising the step of dropping the ID'S of the detached unit or units, is performed, followed by step 1302 according to FIG. 7. FIG. 8 illustrates steps carried out by step 1400, which first comprises the step of executing a Power-On-Self-Test (POST) at step 1402. This is followed by step 1404, wherein microprocessor 600 detects whether signals UNIT_DETECT_L and UNIT_DETECT_R are both high. This will be the case, as described below, when all functional units 104 have completed 5 an analogous POST of their own. Step 1404 repeats until this until both UNIT_DETECT_L and UNIT_DETECT_R are high, wherein step 1406 is performed. At step 1406, a global command is issued by microprocessor 600 instructing all functional unit microprocessors to pull down the unit detect buses 1200L or 10 1200R by setting their signals PULLDOWN to low. Following step 1406, steps 1408 and 1410 are executed, wherein UNIT_ID_ENABLE_R is set to low, and an internal variable such as IDVAL is set to "A" . Following step 1410, step 1412 is performed, wherein it 15 is determined whether UNIT_DETECT_L is high. If yes, step 1420 is performed. If not, steps 1414, 1416, and 1418 are performed, wherein a global ASSIGN_UNIT_ID command is sent over communications bus 1004, the logical address IDVAL is assigned to the responding unit, and the value of IDVAL is 20 incremented. It is to be noted that at step 1416, the responding unit is that functional unit which sends a ready- for-ID message across the communications bus 1008. Step 1412 is again performed after step 1418. Thus, sequential logical addresses are assigned to the left units, beginning at the 25 leftmost unit, until all left units have released the left unit detect bus 1200L after receiving their logical ID, thus letting UNIT_DETECT_L be pulled up by pullup source 910. Step 1420 is entered after UNIT_DETECT_L is pulled up, and comprises the step setting UNIT_ID_ENABLE_R to high to 30 allow units to the right to start receiving logical addresses. Following step 1422, step 1424 is performed, comprising the step of determining whether UNIT_DETECT_R is high. If yes, all functional units to the right, if there are any, have been assigned logical addresses and have 35 released right unit detect bus 1200R, and thus step 1430, which comprises the step of returning to step 1302 according to FIG. 7, is performed. If not, steps 1424, 1426, and 1428 are performed, which are substantially identical to steps 1414, 1416, and 1418 described above. Following these steps, step 1422 is repeated to see if any functional units are still pulling unit detect bus 1200R low. If so, steps 1424, 5 1426, and 1428 are repeated. If not, step 1430, which comprises the step of returning to step 1302 according to FIG. 7, is performed. FIGS. 9A and 9B illustrate steps carried out at step 1500 and comprises the step 1502 of determining whether 0 UNIT_DETECT_L is high. As described previously, UNIT_DETECT_L will be high after the unit attached to the left has performed its POST and released unit detect bus 1200L. After UNIT_DETECT_L goes high, steps 1504, 1506, and 1508 are performed, wherein a global command is sent 5 instructing all functional units to pull down unit detect buses 1200L or 120OR, wherein UNIT_ID_ENABLE_R is set to low, and wherein an internal variable such as IDVAL is set to "A" . Following these steps, step 1510 is performed, wherein it is determined whether UNIT_DETECT_L is high. If not, 0 assignment steps 1512, 1514, and 1516, substantially identical to steps 1414, 1416, and 1418 above, are performed. Subsequent to step 1516, step 1518 is performed, which comprises the step of determining whether the unit which has been assigned was an existing unit or is a newly attached 5 unit. This step is performed by simply communicating with the assigned unit and receiving an indicator flag. If the unit is an "old", i.e. existing, unit, step 1520 is carried out in which existing operational data within system 100 corresponding to the old logical address of the unit are 0 reassigned to the new logical address. Otherwise, step 1510 is repeated. When UNIT_DETECT_L is finally released after assignment of logical units to the left, steps 1520 and 1522, substantially similar in purpose and effect to steps 1420 and 5 1422 described above, are performed. While the value of UNIT_DETECT_R is low, steps 1524, 1526, 1528, 1530, and 1532 are performed in a manner substantially reflexive to the performance of steps 1510, 1512, 1514, 1516, 1518, and 1520 described above, and according to FIGS. 9A and 9B . When UNIT_DETECT_R finally goes high, step 1534, which comprises the step of returning to step 1302 according to FIG. 7, is performed. FIG. 10 illustrates steps carried out in step 1600 and comprises the step 1602 of determining whether UNIT_DETECT_R is high. If so, all units attached to the right have completed their POST as described above. After UNIT_DETECT_R is detected to be high, steps 1604 and 1606 are performed, wherein a command instructing any unassigned units to pull down unit detect bus 1200R is sent, and a variable IDVAL is assigned to the value of the next logical unit beyond those already assigned. Since step 1600 is entered only if a new unit is attached to the right, only the new units need to be assigned, starting the next logical unit address, and existing units do not need to be reassigned. Following step 1606, steps 1608, 1610, 1612, and 1614 are performed, which are substantially identical in purpose and effect to steps 1422, 1424, 1426, and 1428 described above and which are performed according to FIG. 10. After UNIT_DETECT_R is released by all the right functional units, the logical address assignment process is complete, and step 1616, comprising the step of returning to step 1302 of FIG. 7, is performed. FIG. 11 illustrates steps taken by exemplary functional unit 104A according to the present invention. Beginning at step 1700, step 1702 is entered, wherein it is determined if power has been newly applied to the functional unit, i.e. whether the system 100 is at power-up or whether the functional unit 104A has been newly attached. If not, step 1712 is performed. If so, steps 1704, 1706, 1708, and 1710 are performed, wherein the functional unit pulls down unit detect bus 1200L or 1200R, sets UNIT_ID_ENABLE to low, performs a POST, and then releases unit detect bus 1200L or 1200R. In this manner, interface unit 102 will detect, according to the method described above with reference to FIGS. 7 through 10, either the system initial power-up state or the addition of new functional units. Step 1712 is then performed. Step 1712 comprises the general step of receiving a command from interface unit 102 according to the general operation of the present invention. Steps 1714 and 1716, which follow step 1712, comprise the steps of combing the incoming commands for certain commands which indicate that a new logical unit address is to be assigned. At step 1714, it is determined whether a global command instructing the unit to pull down unit detect bus 1200L or 1200R has been received. If so, an assignment procedure beginning at step 1720 is performed. If not, step 1716 is performed, wherein it is determined whether a command instructing unassigned units to pull down the unit detect bus 1200L or 1200R has been received. If so, step 1718 is performed. If not, then the incoming command is, at step 1717, either performed or not performed, depending on a variety of factors corresponding to aspects of the system 100 which are beyond the scope of the present disclosure. Following step 1717, the step 1712 of receiving another command is performed. At step 1718, microprocessor 700 of exemplary functional unit 104A determines whether or not it already has been assigned a logical address. As an example, the exemplary function unit 104A may already have an assigned address where it exists on the right side of interface unit 102 in the linear array of modules, and where an additional functional unit has been added to the right of the linear array. In this case, the interface unit 102 will be assigning logical addresses to the added functional unit but not to the exemplary functional unit 104A. Therefore, the exemplary functional unit 104A will simply proceed with step 1717 as shown in FIG. 11. If the exemplary functional unit 104A has not been assigned a logical address, assignment steps beginning at step 1720 are performed. At step 1720, the unit detect bus 1200L or 1200R is pulled down by microprocessor 700 by means of signal PULLDOWN as described above. Following this step, step 1800 is performed, followed by a repeating of the step 1702 according to FIG. 11. FIG. 12 illustrates steps comprising step 1800 according to the present invention. At step 1802, functional unit 104A receives a command from interface unit 102. Steps 1804, 1806. and 1808 are then performed. As shown in FIG. 12, steps 1804, 1806, and 1808 collectively comprise the steps of determining whether (1) the received command is an ASSIGN_UNIT_ID command, with (2) CONNECT_SENSE being high, (3) at a time when the functional unit has not yet been assigned a logical address after pulling down unit detect bus 1200L or 1200R at step 1720. As described previously with reference to FIGS. 6A and 6B, the CONNECT_SENSE signal will only be high if the functional unit is either the leftmost unit, or if the unit immediately to the left of the functional unit has already been assigned a logical ID. Therefore, the presence of all of conditions (l)-(3) above signifies that the functional unit 104A is the leftmost unit which has not yet received a logical address, and furthermore has just received an ASSIGN_UNIT_ID command from the interface unit 102. Responsive to this condition, step 1809 is performed. Step 1809 comprises the step of sending a ready-for-ID message to the interface unit 102 over the communications bus 1008. Step 1809 is followed by step 1810, which comprises the step of receiving the appropriate logical address IDVAL from interface unit 1810. Following this step, step 1812 is performed, which comprises the step of sending an ID_COMPLETE message to interface unit 102, to indicate that interface unit 102 may proceed with the next unit. Following this, the steps 1814 and 1816 are performed, wherein the unit detect bus 1200L or 1200R is released by the functional unit in question, and wherein UNIT_ID_ENABLE is set to high. Step 1816 is followed by step 1818, which comprises the step of returning to the step 1702 according to FIG. 11. If the unit in question is not the terminating (i.e. rightmost) functional unit, the setting of UNIT_ID_ENABLE to high causes AND gate 104 to set the ID enable out lead 1018 to high which, in turn, will cause an adjacent functional unit to the right to detect a high state of CONNECT_SENSE . This will thus enable the next functional unit in line to receive the next logical address from the interface unit 102. It is noted that by releasing the unit detect line 1200L or 1200R, the functional unit 104A would cause the UNIT_DETECT_L or UNIT_DETECT_R signals of interface unit 102 to be pulled up only if all functional units on a given side have released the unit detect line 1200L or 1200R. As described earlier, this is the desired result in order to allow interface unit 102 to assign logical addresses in accordance with the present invention. Various embodiments of the invention have been described. The descriptions are intended to be illustrative, not limitative. Thus, it will be apparent to those skilled in the art that modifications may be made to the invention as described without departing from the scope of the claims set out below.

Claims: CD d rr CQ CD rt CD Φ CD d to TJ TJ CD Hi SD O d tr CD CD rt CO φ CD d H ≤ SD ø SD Φ < Φ SD ø SD P rr Hi SD d d SD ø SD Φ • Φ SD 0 SD ø . tr μ- μ- < μQ CQ Hi μ- Si μ- μ- ^ Φ μ- 0 rt μ- μ- <; Λ CD Hi μ- i μ- μ- (D rt μ- d ft 3 α ** fi rt CQ SD Si Ω 0 Si rt μ- d rt CQ ø Φ Φ μ- CD μ- Hi ft 3 α rt rt 3 CQ ø Φ Φ μ- CQ μ- SD CQ SD ø 3 SD ø 0 Φ o Hi μ- SD s; μ- SD CQ SD ø 3 SD ø 0 φ μ- P Hi rt 0 SD H. SD μ- Si SD SD μ- o ft tr ø Hh rt ø fD Hj SD μ- i CQ rt 0 Ω SD TJ μ- rt μ- Ω ø Φ 0 P 0 μ- Φ rt 0 Ω SD TJ μ- rt μ- Ω ø Φ φ Hi 0 CD CQ μ- μ- CQ ø J φ rt CQ φ SD Ω Hi Φ Hi 0 J CQ μ- μ- CQ ø- φ rt Ω H. 3 d d SD ø ø μ- SD SD T Φ SD SD Φ Hi 3 d d SD ø ø μ- SD SD Hi SD 3 ø Hi μ- rt Q ø 0 Hi Ω 0 i Hi μ- Hi SD 3 ø Hj μ- rt CQ ø 0 Hi Ω SD SD d μ- SD φ SD Hi tr CD d ø (D d μ- SD ϋ φ SD Hi ø' μ- Ω ø Λ 0 Hi φ rt SD SD 3 μ- SD 0 ^ Ω - y ø μQ 0 Hi Φ rt SD SD 3 3 Φ 0 μ- d μ- CQ μ- Hi ø μ- CD Hi tr 0 rr 0 H{ μ- CD Φ 0 μ- d μ- CQ μ- Hh 0 μ- CQ Hi tr 0 Φ Z Ω Φ rt μ- ø SD ø SD Hi i μ- Ω Hi rt SD SD $. Ω Φ ft μ- ø SD ϋ ø SD Hi μ j Si Si d μ- SD • < Ω rt Ω ^ CQ μ- SD ^ c 0 SD SD CQ CD μ- 0 μ- SD • y, Ω rt Ω - CQ μ- SD ^ d P ø rt Hi SD φ Φ Si K. P ft CQ 0 ø rt Hi SD φ Φ ϋ • ; μ- μ- CQ μ- φ 0 Hi CQ Φ Ω SD μ- SD μ- μ- CQ μ- Φ 0 Hi CO Φ Ω SD O rt 0 CD Hi Hi d SD ø d rr 0 Hi 0 0 £ Ω Q TJ rt 0 CO Hh Hi d SD 0 d ø J 0 Hj • • Φ 0 Φ H SD ø μ- α ø SD d H ø μ- Ω 0 SD Φ ø φ H SD ø μ- ø SD d SD SD CD ft Hi ϋ Ω μ- i μ- < TJ TJ SD rt 0 μ- rt PJ SD CD rt Hh O Ω μ- (i μ- <! TJ TJ ø Ω rt d Φ rt SD rt μ- SD SD & Hi ø μ- ø Ω rt d φ rt SD rt μ- μ- 1 SD ø J tr (D 0 CQ TJ ø O P Φ ft 0 CQ Φ α ø- tr SD ø CD TJ ø CD 0 φ rt d tr Ω ~. d Hi CQ μ- Hi CD d μ- ø d tr Ω »• d Hi CQ ϋ μ- Hi Hi CD μ j rt ø 0 d rr Φ d Ω rt 0 CD rt Hi Hi CQ i- y ft 0 0 d tr Φ φ d φ μ- μ- Hi Hi SD SD (D rt ø 0 tr CQ SD φ d φ μ- μ- Hi H{ SD SD SD rt ø Ω ø Hi 0 rt SD < 0 rt Ω φ H. μ- Ω Ω 0 Hi 0 rt (D <! 0 rt φ Ω 0 0 TJ rt μ- 0 rt 3 Φ rt fD φ Ω 0 ø TJ rt μ- o μ- ft Hi 0 (D tr Hi μ- φ ø Hi H, Ω μ- Φ Q 0 Hi μ- ft Hi 0 SD tr Hi μ- Φ ø Hi Hi Ω <! μ- 3 CQ Φ 0 rt Hi CQ μ- 0 SD 0 d CD Φ < μ- 3 CQ Y- 1 φ 0 rt Hi CQ μ- 0 SD Φ 0 φ μ- μ- < 3 Q Hi Hi 0 Hi μ- rt φ Φ 0 Φ μ- μ- < • y, 3 CQ Hi Hj ø (i Ω c 0 μ- μ- SD μ- 3 Φ SD 0 Hi rr μQ CQ 0 Ω ø ø μ- μ- SD μ- 3 Φ Ω SD SD 0 CQ 0 0 ø P Hi μ- Φ d *<. Ω SD SD ø CQ (i 0 ø ø ø 0 tr μ- μ- Hi SD SD fu CQ ø μ- φ CQ 0 tr μ- μ- Hi SD SD SD CQ 3 ^ rt Ω ø rt 0 rt ^ d μ- CQ Hi ø ft 3 ■ y, rt Ω ø rt 0 rt "< 3 d H CQ SD CQ d μ- Hi μ- CD ø P rt Φ 3 d H CD SD CQ d μ- Hj μ- CD SD ø CD O ~ TJ 0 ø μ- P μ- rt μ- α Φ CQ μ- 3 PJ 0 CO D * TJ 0 ø μ- ø μ- ft 0 μ- SD ~. SD SD μ- CQ CQ CQ ø Φ rt μ- X Φ PJ 0 μ- SD ~. SD SD μ- Q CQ CQ ø Φ Si rt μ- φ tr rt μ- φ 3 • Ω rt μQ μ- rt μ- Φ tr rt μ- φ 3 CD ϋ SD SD d CD CD ø Φ SD SD Φ d CQ co Si SD SD d CD CQ ø Φ SD rt 0 Ω Φ CD μ- SD P Hi rr ft Hi φ rt 0 Ω Φ CO μ- SD ø Hi tr rt 0 rT Φ Ω ϋ rt Si SD μ- 0 0 0 Ω rt 0 Si rr φ Ω (i rt SD tr μ- 0 Hi 0 φ μ- SD < P (D rt CQ (D ø J μ- 0 Hi 0 φ μ- SD <: Φ Ω ø Hi Hi 3 ø SD H{ μ- CQ μ- μ- TJ Φ Ω ø Hi Hi 3 ø SD Hi μ- Hi 0 Φ d μ- TJ Hi CQ P Hi ø SD Ω SD Hi 0 Φ d μ- TJ Hi CQ 0 Hi ø Φ 3 SD 0 TJ ø H{ SD SD CQ SD d SD tr Φ 3 SD ø TJ ø Hi SD i SD ω Hi 3 Hi Ω Hi rt μ- Ω ω ^ CD y- y Hi 3 Hi Ω Hi rt μ- Ω CQ ^ Hi d ft 0 Φ CD μ- μ- SD SD Hi Φ TJ Φ Hi d ft 0 Φ CD μ- μ- SD PJ o ø SD μ- < Hi μ- 0 α 0 Φ Hi 0 H 0 ø SD μ- <! Hi μ- 0 Si 0 3 μ- Hi o μ- Hi ø CQ φ rt Hi TJ CQ O 0 3 μ- Hi 0 μ- Hh ø CQ φ rt Hi TJ Ω Hi 0 ϋ SD CQ Φ SD μ- μ- ^« l-h Ω Hi 0 ϋ SD CQ Φ SD SD SD μ- Ω .. CD Hi Hi d d ft ø rt ra SD SD SD μ- Ω .. CQ Hi Hi d d ft ^ ø Φ SD SD 3 ø Hi μ- TJ μ- ft ^ rt ø Φ SD SD 3 ø Hi Φ CQ μ- Ω μ- μ- SD <! d 0 Φ CQ μ- Ω μ- μ- PJ o d rt i μ- P rt φ rt ø 0 0 d rt Si μ- ø rt ≤ Hi ø 0 ø SD CD μ- CD ≤ Hi ø O rt ^ ø SD CQ μ- μ- μ- CQ rt 0 D μ- μ- CQ rt - (t rt rt CQ μ- ^ Hi μ- SD rt rt CD μ- ; ø J SD P ø μ- 1 SD ø μ- CQ 0 SD μ- CQ o Hi Si Hh wherein each functional unit further comprises: means for detecting a first signal provided by an adjacent originating side unit, said first signal having a first value or a second value different from said first value; means for providing said first signal to an adjacent terminating side unit; means for generating a second signal, said second signal being equal to (a) said first value if the functional unit is at said originating end of the linear array, or (b) the value of said first signal provided by said adjacent originating side unit if the functional unit is not at the originating end of the linear array; means for setting said first signal to said second value upon receiving a first command from said interface unit ; means for receiving one of said sequential logical ID'S from said interface unit upon detecting said second signal to be equal to said first value after having received said first command; means for setting said first signal equal to said first value after having received said logical ID; whereby said patient care system is capable of assigning said sequential logical ID'S to said functional units according to their sequential positions in said linear array. 3. The modular patient care system according to claim 2, said system further comprising a unit detect bus formed by said plurality of functional units and said interface unit, said unit detect bus having a first state and a second state different from said first state, each of said functional units further comprising pulling means coupled to said unit detect bus for pulling said unit detect bus to said second state, ω w to to H I- 1 in o Ul o U1 o in 0 0 CO cn 01 Hh CO rt 0 rt 0 SD 0 CD . SD ft CD d SD d Ω SD 3 TJ CD 3 Hj Hi φ SD SD d φ Φ Hh ø J Hi P Hj ^ • Si ø J Φ ø 0 Φ 0 0 0 Φ d ft Φ μ- μ- Ω μ- μ- 0 Ω Hi Φ μ- ϋ μ- CD ϋ Φ μQ μ- rt μ- ø Q x SD SD fD CQ CQ 0 Si Ω 0 3 CD Q CQ ft μ- μ- d rt Φ rt ø ø H 1 rt 0 μ- μ- 0 ft 0 μ- SD CD μ- μ- φ rt Hj Φ CO 3 Ω CD Φ ft CD μ- Φ 0_ P ø s- Si 0 0 μ- Si ø μ- φ ø SD P SD 3 μ- 0 co s; Φ rt s; - Ω ø J S ø $, SD SD tr Hi Hi 0 SD ϋ ft SD SD 0 0 CD ft SD tr Hi SD μ- tr ft φ Hi tr CQ ≤ Ω tr rt rt Φ CD μ- μ- ø CD rt rt ft rt l-h 0 Φ μ- μ- Φ Φ ø 0 Φ SD μ- Hi 0 Φ tr SD Φ μ- μ- Hi ft cQ CQ (D rt μ- μ- 0 μ- Φ μ- 0 d μQ SD P. hj CD CD CQ Hi 0 0 Φ Hi Hj CD Φ TJ Hi P 0 Φ (D μ- μ- SD ø 0 Hi ø Hi ø Hi Hi 0 d φ TJ Φ 0 SD Φ SD ø SD Φ CQ CQ μ- rt ø ø rt CQ ft CQ 3 CQ μ- rt H Hi φ Tj tr 0 Hh O μ- Hi TJ μ- μ- tr μ- ø φ SD SD d Φ φ Hi μ- CQ 0" tr 0 S * ; 0 0 SD ø 0 rt d ø ti ø ø d CO ^ rt rt ø d Hi d d ø CD μ- φ Φ (D ft O rt CD Hi μ- Hi φ 0 Φ ø μ- CD μ- μ- μ- ø Hi 0 ø SD μ- ø Hi 0 μ- CQ μ- μ- ϋ CD Hi Φ d 0 tn μ- SD Hi ø ø r μ- μ- SD Ω μ- rt SD 3 SD μ- Φ <! CD SD CD μ- fD ø φ 0 SD rt Φ μ- φ CQ CQ CO Hh rt Ω rt rt μ- φ rt Ω 0 SD Ω ø φ Φ TJ μ- SD Hi ø Ω μ- Hi μ- CD Hh φ μ- ø μ- 0 α SD rt 0 d μ- Φ CQ ø' rt 0 ti i TJ TJ 0 0 Hi Φ i 0 fi CQ Hi ø 3 d TJ rt i- y ϋ Hi TJ Φ d μ- Φ Hi Hi d Hi Φ d ø Φ d CQ TJ Φ 0 Ω tr μ- μ- Φ CD 0 fi d μ- rt ø Ω Hi φ rt 0 SD rt d ø Hj SD CQ M SD Φ ø μ- ø Hh SD SD Hh Φ CD ø Φ rt ft rt rt ft 0 Φ μ- Φ P Ω d μ- Hi μ- d Hj Hj CQ ø rt d CD μ- rt SD rt Ω μ- φ μ- Φ Φ ø 1 rt Ω rt Ω μ- ft ø CD Hi rt ^ φ Φ CQ φ ø μ- ϋ CD Φ μ- μ- φ rt ø H{ < Hi Hi Φ ft •« d ft rt μ- μ- μ- TJ d μ- CD rt CQ Hi Ω ø SD Ω fi ø Hj CQ Hi Φ 3 3 Hi Hi 0 0 rr ø SD ø 0 CD 0 SD SD Hi rt CQ d μ- rt CQ Hh tr PJ μ- μ- Hi tr φ μ- tr Si 0 CQ rt Ω 0 rt ^ - μ- ø SD μ- ø Si Hi SD d 3 Ω ø ø Ω 0 d SD rt d Φ SD Si • • μ- rt CQ 0 CO α Ω 0 CD μ- tr d CD Ω CD Φ Φ ~. SD SD 0 3 CD Ω CD CD rt Φ Φ μ- ft Φ 0 SD rt Hh d 0 SD Φ SD rt rt 3 Φ ø J Φ rt 0 0 μ- C0 φ Hi Hj SD μ- d en Ω μ- ι ft 0 d μ- μ- TJ CD CD Hh Ω d Φ rt 0 ø SD 3 μ- φ d ϋ ø ft ϋ d 0 CD ø 0 ø Hj SD 0 0 0 rt ø Ω SD μ- Hj - y ø Φ Ω rt μ- to ø μ- CQ CQ μ- μ- tr Hi Ω Hi μ- rt Ω CD & μ- CQ Φ μ- ø ø et rt 0 0 d μ- -J CD Ω rt CD fi fD SD 3 tr rt P) SD CQ ft SD rt 0 ø Φ μ- 0 ø rt SD SD ø μ- <! CD ft φ d CD tr Hj 3 μ- Hi CQ μ- μ- Ω 0 tn SD μ- | μ- TJ Hi ø ø ø Hi μ- SD φ (i CD d Φ 0 Si d Ω Ω μ- Hi rt rt ft 0 SD rt Hi α SD ø μ- μ- CQ μ- ø μ- i SD α_ 0 (D 0 ø d SD μ- d tr Hj rt rt Hi CQ ϋ tr CD ø CD d Ω TJ 3 CQ Hi rt ti tr - y ϋ d i Hi Hh rt TJ CD 0 ^ Φ α Hi ^ μ- rt SD 3 rt 0 Φ d 0 Φ rt μ- Φ ø J ϋ ϋ d ft SD 0 0 TJ 0 CQ φ ø μ- tr SD 0 tr rt CD d ω μ- rt tr Hj Φ Φ Φ Hj CD SD CD Hi ft φ 0 0 Hι Φ CO Φ 0 Φ rt Φ Φ CD 0 Hj rt rt CQ Hh μ- rt SD Hi SD 3 Φ ft SD 0 φ ϋ Hi SD Ω ft μ- Ω Ω Hi r Hh Φ Φ μ- ft μ- Q rr μ- SD μ- φ 3 0 Hi SD CQ μ- rt 0 rt 0 TJ rt Ω Ω Ω ø SD Hi μ- Φ rt α ϋ 0 rt SD Ω Si CD 0 d Ω CD TJ 0 rt rt CQ rt CQ ø Φ 0 CO SD Hi 0 μ- 0 tr CD fi tr 0 rt d 3 Φ rt SD rt μ- μ- tr Hi SD Hi d ϋ 3 d SD l-h d 3 SD TJ tr tr 3 ~ rt φ ø Hh ø ^ μ- Hi 0 SD CO TJ μ- D μ- ø CD μ- CD J rt Hi d d Φ CD μ- Hi rt Hi rt Ω Si SD μ- CD SD d Hi ø •> Hi ft ø Hi Φ μ- μ- CD CD SD Φ ft ø 3 φ 0 φ CD ^ rt CD μ- ø μ- Φ rt SD CQ ft μ- ø CO 0 SD SD CQ μ- Hi 3 Hi SD SD CD μ- μ- ω SD d CD ø- ft 0 CQ £ CQ Φ ft Hi CD Ω rt ø Hi Hi μ- μ- μ- d CQ rt φ H{ TJ Φ Φ Φ 3 φ tr CD 0 0 tr φ SD SD SD CO (D 3 ø TJ (D 0 Hh CD 0 Ω Hi φ CQ CQ Φ CD Hi Ω ø rt Ω SD Ω φ 0 Ω μ- d SD ø 0 SD SD P SD CD 0 0 SD Si μ- Φ μ- Φ to SD 0 Ω ø 0 Φ 3 Hi 0 Ω ø μ- TJ μ- SD TJ d Hi 0 ø Si - Hi 0 CQ Ω rt φ Hi μ- i 0 CD fi d P Si μ- d TJ Si CQ d d ft Hi ft Φ SD SD ø 3 0 CQ ø ø CD SD ø' ϋ μ- Ω 0 ^ μ- CO TJ (D Hh μ- 1 P Φ SD PJ CD μ- μ- SD Hi Φ μ- o rt CQ rt ft Hj Hj μ- μ- φ μ- Si μ- μ- rt rt μ- Hj ø 0 0 μ- SD μ- Φ Hi ø ø Si CQ SD tr Hi Hι PJ ft ω CD Q 0 CQ rt φ SD ^ d 0 - Φ φ ft Hi 0 0 ft CO Hj CD i 0 said forcing means are pulling said originating unit detect bus to said second state, wherein said interface unit further comprises terminating side pulling means capable of pulling said terminating unit detect bus to said first state when none of said forcing means are pulling said terminating unit detect bus to said second state, wherein each of said functional units further comprises means for pulling said originating or terminating unit detect bus to said second state, and thereafter releasing said originating or terminating side unit detect bus, upon initial connection of said functional unit to said originating or terminating end, respectively, of said linear array of units, and wherein said interface unit further comprises means for detecting said pulling and releasing of said originating or terminating unit detect bus, and means for sending said first command to said functional units responsive to a pulling and releasing of said originating bus and means for sending a second command responsive to said pulling and releasing of said terminating unit detect bus, whereby said patient care system is capable of initiating a logical address assignment procedure upon the addition of a new functional unit to said linear array of units. 5. The modular patient care system of claim 4, wherein said functional units further comprise means for pulling said originating or terminating unit detect bus to said second state upon receiving said first command from said interface unit, wherein said functional units further comprise means for releasing said originating or terminating unit detect bus upon receiving said logical ID and setting said second signal equal to said first value, wherein said interface unit comprises means for detecting the releasing of said originating unit detect bus to said first state after all originating side functional units have released said originating unit detect bus, and means for providing said first signal to an adjacent terminating side unit, said first signal being equal to said first value upon said detection of the releasing of said originating unit detect bus; whereby said patient care system is capable of assigning sequential logical ID's to said all of said functional units according to their sequential positions in said linear array upon the addition of an added functional module to said originating side of said linear array. 6. The modular patient care system of claim 5, wherein said functional units further comprise means for pulling said originating or terminating unit detect bus to said second state upon both (a) receiving said second command from said interface unit while (b) not yet having an ID assigned, wherein said interface unit further comprises a means for storing the number of functional units already having logical ID's, whereby said modular patient care system is capable of assigning sequential logical ID's to functional modules added to the terminating end of the linear array without reassigning logical ID's to those functional modules already in the linear array. 7. The modular patient care system of claim 6, said interface unit further comprising: a memory for storing functional unit specific information for at least one of said functional modules indexed according to the logical ID of said at least one functional unit; means for transferring the functional unit specific information corresponding to said at least one functional ω ω to t H H in o in o in O in fD d μ» tr tr 0 Ω CQ CQ 0 tr tr Ω D ø J ϊg tr CQ CD SD CQ CD 0 CD ø Hj ø o d Hi 0 fD Hi 0 0 Φ Φ 0 • Φ μ- ø- Φ fD μ- 0 μ- • Hi d ø H μ- • CO μ- 3 μ- 0 μ- ≤ μ- μ- 3 fD cQ φ rt μ- CQ ≤ CQ μ- tr μ- SD rt CD CQ TJ fi d rt ø ø 3 fi rr Hi $. fi ø 0 ø cQ D rt . CD tr fD μ- Hj ø CD < CQ CQ fD Φ Φ fD <; CQ fD μ- Φ ^ μ- ≤ tn o CQ ø μ- Hj fi 0 0 H 0 <! μ- Φ CQ 0 μ- H ø μQ μ- fi ø J 0 Hj SD SD Q φ Ω i- y SD fD ϋ tr Hi 0 ø ø Φ Ω rr SD d ø CD Φ SD Φ d μ- μ- rt μ- fD 0 ft ø Φ t- y Ω σ rr tr Φ rt Φ fD ft Hj Hi CQ fi μ- ø φ ø 3 SD tr SD rt CO CD 0 Φ SD rr φ μ- ø CQ μ- fD Φ Φ Ω μ- ø CQ fD ϋ TJ CQ 0 d Φ 3 0 SD SD fD 0 μ- CQ μ- μ- 3 ø rt SD ti Ω Hh μ- Φ ø SD 0 SD CQ CQ Hi φ CQ ø μ- 0 CQ μ- μ- ϋ ø Φ CQ ø 0 CQ μ- rr 0 ft ø -. pj Hi 0 CD μ- CD μ- μ- SD ø fi SD Φ fi fi CQ rr CQ fi rt ϋ fD 3 Hi rt μ- CO SD ø SD CQ Ω CO CQ d CQ CQ d CD 0 μ- tr 0 TJ CD μ- Φ Q 0 μ- μ- CQ μ- μ- CD CD O H H μ- fD μ- < JD μ- 3 ø fi CD d SD ø Hi μ- Hi fi fi α ø SD ø J μ- SD SD SD μ- α D Q ø Q 0 ø SD fi rt φ Φ ^ 0 SD μ- CQ ft ø μ- φ 3 iQ μ- μ- cQ Hi Ω CQ ø ø Hi Φ ø J 3 SD μ- fi SD CQ CQ φ 0 CQ ø CQ Φ P Φ φ SD fD rt M • Φ 0 Hj Ω SD O d 0 TJ rt μ- TJ Hi fD Hi SD ø' Φ TJ 0 SD ø 0 o fD α TJ Hj 0 Hi TJ 0 ø d μ- ø d 0 0 μ- TJ i 0 fD ft SD fD CQ SD fD > SD d Hi Hj μ- ø SD d CD CQ CQ d <! tr ft tr tr Ω φ Φ Φ ft ϋ Hj TJ TJ φ Hi μ- rt CQ rt ø μ- Hi 0 d fD μ- 0 s; - y 0 0 CQ ø μ- SD -> Φ α ft Hj CQ d μ- μ- ti 0 ø 0 ø φ Hi P J Φ φ 3 fD SD CD SD φ μ- 0 SD φ ft φ CD μ- fi TJ d ø ø μ- Hh fD d μ- rt μ- ø μ- Φ TJ σ μ- μ- σ 0 rt ^ fi μ- SD μ- ø Φ ø CQ CQ ø rt ø ø SD rt CQ rt Q P μ- μ- Hi - y cQ rt μ- fD φ CD co fD rt Hi μ- CQ Φ μ- fD α CQ CQ Φ μ- ø ø μ- φ ø Φ 0 rr ft 0 μ- rt rt Φ Φ rt ø 3 ø μ- Φ CD ft Ω ø P Q 3 SD Ω ø 0 SD 0 rt 0 0 μ- Ω cn 0 Φ rt Ω CQ ø 3 ~ Φ SD SD 0 h- μ- μ- Φ 0 fD Φ <! CQ Hi ø rt μ- ti μ- SD Hi 0 CQ φ rt H Hi rt ft Φ Φ ø ø fD - 0 Hi 0 X i μ- φ Ω CQ D Φ rt ø SD 0 SD tn ϋ Φ μ- fD fD CQ 0 ft Φ Hh ft ø fD SD 3 d rt rt CD 0 0 Hi rt 0 fD H ø Ω fi fi CD CD ω LQ Ω Hi Φ TJ ø Φ 0 Φ fi CO Hh Hi O μ- σ Ω CQ CQ 0 SD φ SD CO CD CQ CQ o tr Φ SD 0 ø (D Hj Ω Φ Ω μ- rt SD fi 0 • y, P μ- fD fD Hi μ- μ- ^ SD Φ SD 0 ø μ- ϋ rt r 0 co CO Φ 0 0 Ω 3 CD CD P CD 0 TJ fi O ϋ CQ CO μ- μQ 1 0 CD CD rt Ω Φ 3 rt SD Hi CQ Hi tn 0 3 ft μ- φ fi d Hi ø ft Si d 0 rt > <. • Hj SD 0 tr Ω TJ 0 μ- 3 μ- φ 3 SD Φ ϋ Ω TJ CQ (D φ φ Hj ø- CD Φ 0 d d rt Hi Hi fi μ- O Φ Ω 3 0 3 Φ ft 0 fD CD α φ 3 SD 0 μ- Φ ft Φ ϋ TJ CO μ- ^ ø ft SD 0 fD & φ d SD Φ Ω " fi ft CQ Hj Φ Φ rt ~. CQ Hi SD 0 Ω 0 0 0 d fi Ω TJ μ- rt 0 0 u μ- μ- 3 fD Φ SD Φ Φ μ- CD 0 rt Hj ø J fi fi Hi ø Φ 0 ϋ Φ 0 CD Hi φ SD ø rt CD Ω ϋ SD SD ø SD 0 μ- - CQ μ- rt fi 0 Hi Ω fi SD ϋ fD 0 t Φ rt Ω 0 fi CQ μ- Ω 0 Ω 0 CQ SD Ω rt 0 CD φ 3 rt μ- Ω rt SD 0 tr ϋ fi ft CQ 0 Hi ft CQ μ- • ø ft CD φ μ- <; Si " 0 μ- Hi <. 0 0 Φ Hi μ- d fD fD SD fD TJ SD μ- SD ø fD SD 0 0 ø 0 μ- Hi Φ CD rt 0 μ- 0 d TJ CQ rt μ- μ- P 0 CD 0 CQ Hi μ- μ- CQ CQ Hi ø SD ft K Hi ø ø 0 SD φ fi CQ 3 rt rt rt CQ 0 μ- 3 rt μ- 3 CQ O ϋ SD φ rt fD μ- φ μ- φ μ. 0 0 CD Φ Hj Ω Φ SD 0 φ Ω Φ rt fi α tr Hi Ω oo O < Hi Hi fD CQ cr. rt SD ø SD SD μ- μ- rt 0 0 Hj φ μ- 0 tn 0 O μ- tr ft - 0 fi ϋ CD 0 Hi d tr Hi μ- Hi 0 Φ SD Ω Hi ϋ Φ TJ < CQ TJ fD ø φ φ 0 ø CQ fi CD P μ- ft 0 μ- < CQ CQ H SD μ- d TJ 0 SD t- 1 Ω μ- rt ft 0 CQ rt SD SD ϋ SD d CQ Hi ø SD fD SD d ø ø 0 ø ø μ- μ- Φ tt Φ s: Ω Ω μ- tr CQ TJ Φ μ- CQ μ- 1 μ- μ- fi φ Hi μ- rt fi ø CD Ω φ rt fD CD 0 ϋ φ 0 Hj 0 Si (i SD SD rt SD CQ d rt φ μ- ft 3 Φ 0 Φ Φ CD fD Φ fD Hi h- 1 Φ CQ ø 0 0 SD 3 Hi CQ CQ fi Hj ft Hi μ- fi ϋ Φ rt μ- tr 0 0 ft SD μ- 0 μ- 0 SD σ μ- rt Φ 0 rt ø SD fD CQ Φ 0 Hi 0 Ω 0 ft 0 Φ Hj ■ : rt ø- CD μ- fi CD ft Hi μ- CQ μ- 0- Φ μ- Φ Ω ft Ω ø μ- ø rt 0 Ω CQ CD Φ CQ Ω CQ Hi rt ø J - terminating end, said units each having an originating side facing said originating end and a terminating side facing said terminating end, said linear array comprising: an interface unit for providing a user interface to said system; a plurality of functional units, each functional unit being capable of providing patient therapies or monitoring, each functional unit having a unique resettable logical ID, each functional unit comprising: a communications bus portion for forming a common communications bus; a unit detect bus portion for forming a unit detect bus; means for providing an id_enable_out signal to a unit abutting said terminating side, said id_enable_out signal having a value ENABLE or DISABLE; means for generating an id_enable_in signal, wherein said id_enable_in signal is equal to (a) ENABLE if the functional unit is at said originating end of said linear array, or (b) the id_enable_out signal of a unit abutting said originating side otherwise; means for receiving commands from said interface unit over said communications bus; means for pulling down said unit detect bus to a LOW state and setting said id_enable_out signal to DISABLE responsive to a first command from said interface unit; means for detecting the state of said id_enable_in signal; means for receiving a unique logical address from said interface unit upon (1) having received said first command, and (2) detecting the state of id_enable_in to equal ENABLE; means for setting said logical ID equal to said unique logical address; and means for setting said id_enable_out signal to ENABLE and for releasing said unit detect bus upon setting said logical ID; whereby said patient care system is capable of assigning sequential logical ID's to said functional modules according to their respective positions in said linear array. 11. The modular patient care system of claim 10, wherein said interface unit comprises: means for pulling said unit detect bus to a high logic state; a communications bus portion for forming said common communications bus among said units; means for detecting said LOW state of said unit detect bus upon initial power-up or upon the addition of a new functional unit; means for detecting the releasing of said unit detect bus; means for transmitting a PULL_UNIT_ID_LOW command over said communications bus responsive to said LOW state and said releasing of said unit detect bus; means for assigning sequential logical addresses to said functional units during a period in which said unit detect bus is pulled LOW. 12. In a modular patient care system having a plurality of units detachably coupled to form a linear array of units having an originating end and a terminating end, each unit having an originating side facing said originating end and a terminating side opposite said originating end, the linear array of units comprising an interface unit for providing sequential logical ID's and a plurality of functional units requiring an assignment of a one of said sequential logical ID's, a method comprising the steps of: generating a value ENABLE or DISABLE at an ID enable in lead of each functional unit; transmitting a sequential logical ID to all functional units over a common communications bus formed by functional units and the interface unit; receiving the sequential logical ID at that functional unit which (1) detects a value ENABLE at its ID enable in lead, and (2) has not yet been assigned a logical ID; setting an ID enable out lead of that functional unit to the value ENABLE after receiving the sequential logical ID, for generating the value ENABLE at the ID enable in lead of an adjacent terminating side unit. 13. The method of claim 12, each functional unit having a pullup resistor connected between the ID enable lead and a constant voltage source with the value ENABLE, the step of generating the value ENABLE or DISABLE at the ID enable in lead comprising the step of (1) if the functional unit is at the originating end of the linear array, pulling up the value at the ID enable in lead to ENABLE, and (2) otherwise, connecting the ID enable in lead to the ID enable out lead of the originating side adjacent unit to assume the value of the ID enable out lead of the originating side adjacent unit. 14. The method of claim 13, further comprising the steps of : determining whether an additional unit has been added to the originating end of the linear array; determining whether an additional unit has been added to the terminating end of the linear array; if an additional unit has been added to the originating end of said linear array, assigning sequential logical ID's to all functional units; if the additional unit has been added to the terminating side of said linear array, assigning a sequential logical ID only to the additional unit . 15. The method of claim 14, said step of determining whether an additional unit has been added to the originating ω u> to to H H in o ϋi o U1 O U1 rt d tr 0 μ- fi TJ Φ ≤ H tr TJ Hi tr 0 d μ- fi TJ φ φ ø ^ Hi ø φ d ø 0" n d d 0 ■ y, Hi ø ø Φ d ø Hi μ- rt rt fi Φ • CD 0 μ- μ- rt ft Si 3 rt fD tr Φ φ rt Ω ft CQ rt Φ Φ μ- Φ Hi Ω μ- 0 tr 0 μ- rt tr μ- CD Hi Ω μ- 0 CD 0 tr μ- Hh rt ø Hi Φ ø ø μ- Φ 0 Hi rt ø Hi Φ SD Φ ø SD CQ Hj CQ 0 PJ 0 fD CQ rt rt μ- rt CQ Ω tr rt TJ ø μ- rt ø Ω tr rt rt μ- ø Φ Φ 0 fi ø' fD 0 fi fD ø μ- Φ ø ti tr μ- ø CQ Hi TJ CO 0 Φ 0 ≤ 0 rr ø rt CD 0 Φ 0 CQ 3 d 0 ■ Z H φ s; φ CQ tr 0 Z CQ Ω μ- 0 Hi 0 fD rr Hi ø 0 Hj Φ 0 Hi ø d SD ø μ- 1 μ- 0 - μ- fi Φ 1 0 Hi d μ- 0 μ- rt 0 TJ fD φ rt Hi ø fi d SD μ- SD ø 0 rt Hi ø tr μ- (D rt Si - 3 Hi φ μ- 3 TJ 0 rt Ω μ- Hj - 3 Hi Φ Φ rt tr μ- Φ 0 fD rt φ • Si CD Φ rt μ- φ 0 SD 0 d rt fi - y Hi μ- rt •- CQ rt fi Hi μ- fi Φ CQ TJ tr 0 rr ft d ϋ μ- t ø Φ Φ tr 0 fD 0 0 tr rt ø Φ ø Φ tr 0 SD rt rt 0 Hh tr ^ s; Hi SD fi Φ tr μ- rt SD ^ s > Hi Φ Φ Hι d •^ rt Φ Hi ø Φ rt Φ rt 0 φ Hi Hi Ω ø φ rt ti SD 0 Ω μ- Hj rt fi SD Hi rt TJ Ω rt Hi tr ^ 0 Hi Hi SD d rt ø μ- tr ^ SD ø rt rr 3 Φ tr 0 Φ TJ CQ CQ Φ tr Ω tr μ- Φ μ- ^ Ω μ- Ω o tr μ- ^ Ω Φ d 0 ø rt 0 rt Φ Φ 0 d CD ø 0 0 CQ μ- 0 μ- SD Φ (D 3 SD SD CO μ- SD Hi fD 3 d ø fD ø rt Hi TJ tr μ- CD tr fi rt μ- TJ 1 0 0 CQ μ j rt μ- 3 Hi Hi SD 3 μ- Hi Φ tr Φ μ- cQ Hj Hi μ- 0 Φ 0 μ- φ μ- CD 0 d μ- Φ ø μ- Φ μ- > <-r fi ø Hj CQ P μ j tn - y CQ ø ø μ- 0 CQ P CQ μt> TJ 0 ø Hh SD φ μ- tr in Ω CQ ø Hi SD Φ μ- H 0 Ξ μ- SD d rt SD ø Φ * rt rt CQ Hi rt fD ø ' d £. ø rt Ω ø μ- CQ CQ Φ tr μ- Hi ft d μ- CQ CQ φ CQ Φ μ- P μ- ø CD Φ 0 φ Ω tr ø P μ- Φ Hj fD - rt CQ ø rt SD ø fD Φ Ω CQ ø rt 0 1 0 d CQ rr fD μ- 0 fD Φ TJ rt CQ tr fD d fi ft ø ϋ Hi ^ Φ fi Hj SD SD μ- μ- Hi ^ Φ tr TJ tr μ- Φ d fi μ- CO tr ø 0 d • ft Φ rt rt P 0 CD φ CD CQ 0 Φ rt 0 P 0 CQ Φ tr Φ Ω Hi rt ϋ ft μ- 0 fi Φ Φ fD Ω Hh rt Φ SD d Ω ft φ φ ø μ- H{ ft Φ 0 ø fi TJ rt μ- SD TJ ft TJ fD rt tr 0 Hi μ- SD TJ 0 α 0 0 0 0 rt "< Hι SD 0 0 0 ft Hj Φ 0 r P 0 0 μ- tr Ω 0 P 0 Φ fi 0 SD ft Hi rt Hi 0 φ fD tr Φ μ- SD 0 Hh tr CQ Φ tr CQ μ- Φ rt μ- 1 Hi Φ Φ Hi Φ Hi fi Φ fi ø μ- d CD μ- ti fϋ fD d μ- tr d 3 Φ φ d CQ ø 0 ø LQ Φ fi CQ ø ø Φ P μ- ft rt ft ø 0 CQ μ- tr ø μ- ft μ- Ω Q μ- μ- ø Φ Φ φ μ- Ω Hi rt Φ μ- ø Φ rt ø rt ø rt fD Ω Hj rt (D μ- TJ • » μ- rt SD Ω 0 CQ μ- Hi CQ CD rt rt 3 3 TJ CQ ø ø CO rt rt 0 φ μ- μ- μ- μ- fi fD μ- rt CQ μ- μ- M rt 0 Ω SD ø ø ø ø Φ tr ø tr SD ø ø 3 t SD Φ SD P Q CQ SD μ- rt SD Φ Φ rt ø CQ iQ Φ SD TJ ϋ rt ø Φ φ rt fi rr ϋ ω CD fD 0 SD μ- CQ Ω μ- 0 d fD -> Φ tr rt ø ø rt 0 ø 0 CD rt ø M fi tr μ- CQ Hi CQ TJ Φ tr μ- φ Φ rt Φ rr > OJ to to H H> on O u. o ϋl O Ul SD Hj Φ SD ^ - ^ Hi Ω CO SD Hι TJ 0 Hi fD Ω fD Φ rt SD Hh SD fi h- y ft tr fi Ω Ω h- y Hi H Φ 0 fi t d 0 φ 0 0 0 0 0 0 0 fD Φ d CD μ- o tr Φ Φ 0 fD 03 d Ω fi l_J. * — ø 3 μQ - y Hj £ μ- HJ ϋ 3 fi Ω Hi h- 1 ø CO H! • Φ Φ rt 0 TJ . ø φ fD Ω 3 d φ rr 3 TJ rr 3 μ- Ω μ- Φ ø Φ 0 (D Ω 0 μ- Ω Hj rt 0 Φ fD fi Hj CQ Φ Hj d £D μ- ø ft CQ Ω Hi Ω φ tr ft Hj 3 < fD Φ Φ μ- 0 ø 3 rt μ- 1 3 - Φ 3 rt rr ø Φ μ- ø rt Φ SD rt Ω μ- SD μ- φ μ- 0 0 Ω 0 rt φ rt Hj d φ Ω φ Φ ft fD fD SD 0 CD μ- ft Φ 0 CQ Q SD ø ti ft Φ 0 Ω μ- SD SD φ T fD tr Φ SD Hj Φ < rt Hj 0 CO fD φ CO ø Φ 0 CQ μ- 0 CQ μ- (D 0 fD 0 Ω Ω 0 ^ μ- 0 1 Hj μ- μ- SD φ 0 fD μ- CQ fi 0 SD μ- P CD .— ». 0 <; 3 CD rr ft 0 CQ < CD Hi 3 ø ø SD μQ CO CQ Hh - y CQ fD rt OJ 0 φ 3 Φ μ- Hi rt φ Φ μ- CQ iQ Hi d μ- μ- 0 Ξ d ι-3 0 rt Hh tr — μ- fi 3 d Hh α 0 Hi tr Hi SD ø Hj d Φ ø ø Φ tr TJ Hi rr d μ- μ- 0 Φ rt 0 ø 0 0 CQ ft 0 Φ μ- 0 fD SD φ SD ø ø rt Ω CQ fi Φ 0 Φ Φ ø P P Hi rr fD (i μ- CQ Hi Hi rr Hi ø Hi SD rt ø ø ^ μ- rt Φ 0 ø ø H μ- CQ CQ Hi fD 0 0 ø Ω μ- 0 rt Φ μ- Hi tr μ- fi rt μ- Hi 3 0 Φ 3 rt Si μ- CO Hj fD Ω fi 0 0" fi ø 0 fi ø 0 - 0 CQ fD Hi TJ Hi 0 SD Hi fD φ CQ CQ CO μ- H φ Φ ft SD μ- Ω Φ fD μ- rt Hj μ- Φ CQ Hi Hi fD d CQ Φ CD rt . φ μ- Hj CD ø μ- 0 μ- h- y H{ rt rt Hj Φ 3 Hj μ- rt fD Ω rt ft μ- Ω μ- rr μQ ti φ ft 0 co SD 0 φ μ- μ- rt φ Hj fD φ 3 CO CQ tr d ft Φ φ tr Ω Φ ø 0 d Φ Ω rt tr tr 0 H Ω 0 ø fD Ω Hi ft Ω φ μ- μ- Φ ø ft 0 Hi Φ fϋ 0 μ- iQ ti φ ft Ω rt μ- CD d ft 0 rt Ω rt SD μ- ft fi (i ø μ- fD CQ 0 1 Hi <! P Hi μ- 0 ^ tr μ- Ω ^ μ- fD Φ rr μ- Ω 0 μ- μ- Φ SD μ- rt Ω μ- 0 Hi 0 μ- μ- rt 0 rt d ø 3 Φ Φ ø rr tr CD ø Hj 3 ø Φ ø ø d rt ø CO rr Ω μ- Φ Hj H CQ ø tr Hh μ- P CQ 3 rt CQ d CQ Hi Φ CQ CQ 3 0 μ- rt Φ fD rt SD μ- d μ- CQ Φ fD Ω fD Hi rr CD ft 0 SD ø d 0 TJ ø Φ tr Si CQ - ø Ω rt rt ø Hi d CD fD ^ 0 rt 0 Ω rt rt 0 <! rt Ω TJ CQ Hi SD 0 SD μ- CD fD SD 0 h- 1 μ- rr fi Φ ø μ- CD tr μ- Φ tr μ- Φ tr 0 0 Hi <. rt 0 Hi tr ø rt ø fD H O Φ Ω Ω CQ Hi fD Φ rt 0 Φ rt Hj Φ 3 tn CO fD μ- 0 0 SD Ω μ- CD μ- μ- d P Φ rt ø 0 CD d Hi TJ μ- μ- Ω ø μ- fD Φ rt 0 ø Φ rt 3 SD μ- μ- μ- SD μ> Hj μ- 0 μ- fD SD μ- Hj rt ϋ Φ CQ rt rt μ- 3 CQ μQ CQ ø < 0 — ø Hj μ- SD ø 0 ø μ- Φ φ tr 3 3 ø TJ d fi rt φ 0 Hi Hh rt φ rt fi rt fi Ω rt co d SD Φ H 0 φ CQ Hj CD Φ Φ ft d Φ fi SD Hi Hj Φ d Φ CQ fi Φ 0 Φ μ- rt Hi ø 0 d Si fi μ- μ- 0 rt •» 0 P Hi Hi Φ Ω ø Hi TJ rt μ- Hi rt 3 Hi ø tr SD μ- μ- ø μ- ø co fi ft Φ μ- Hh SD 0 Ω Φ Ω Hi 0 0 rt Hh tr 3 Hi CQ Φ Ω rt 0 ø CD d ø μ- Φ μ- Ω Φ SD rt SD d 3 Φ μ- ft fD 0 μ- SD φ 0 fD • • μ- Hi rt SD 3 μ- ø SD rt SD h- y CD Ω μ ø μ- < μ- Ω CQ CQ 0 Ω 0 Ω 0 0 fD μ- Φ ft Hi rt CQ Hi Ω Φ 0 μ- SD < μ- 0 Φ μ- φ ø φ fD Φ Hi CQ ø CQ Hi 0 d σ tr tr CQ rt 0 φ ø 0 <! 0 fD rt Ω μ- fi μ- Hi TJ tr Si rt ø h- y d rt SD d μ- CQ SD 0 φ ϋ 0 rt 0 d CQ rt ø SD fD SD μ- Φ tr Ω 0 CD Hi Φ < ø Ω fD 0 0 0 SD 3 ø μ- tr rt SD Ω ft Ω rt Φ ft CQ 0 Hj Φ μ- SD rt Hj r tr μ- rt SD Hi μ- Ω 3 μ- P Φ * rt Φ TJ μ- tr Φ μ- μ- rt 0 3 rt μ- rr ^ d rt 0" d rt ø' ø rt fD Φ μ- φ Ω n 0 Ω 0 Ω μ- Hi rt Q Φ 0 Φ Hi 0 Φ ø rt 0 ø d ø ø Ω rt rt ø SD ft ø Φ rt M * μ- (D μ- rt Hi μ- Ω rt fi μ- rt μ- Hi Hi CQ ø Hi rt SD Φ fD H-" μ- fD Ω 0 d Φ ø Hi rt 0 Φ Hi rt 0 Ω 0 P μ- 0 μ- fD 0 tr TJ ø' 0 rt Φ SD μ- CQ CD ft CQ μ- Hh SD CQ Q 0 Φ rt Ω d μ- ø μ- μ- fi fD 0 rt Hi μ- rt 0 ft 0 Si 0 ft CO μ- Ω ø μ- SD tr CO 0 0 d Ω SD ø <! Φ l-h Hi μ- CD ø 0 Hi ~. 0 Φ 0 μ- Φ CD ø rt fi CO rt Hi Φ • Hi 0 rr CQ Φ rt ft μ- ø ft CQ < fD Ω SD rt Ω 0 ø μ- SD μ- 0 > < Φ μ- fi Φ Φ Q CQ φ 0 0 Φ rt ø fi fi rt O SD ø fi rt rt μ- 0 O Ω Hj μ- Ω Φ Hj CD 3 Ω μ- CQ φ μ- 0 ø fD 0 CD CD Φ CD 0" rt 0 μ- μ j rt ø CO 0 3 3 d rt 0 Ω *• ø SD ϋ CD Hi ^ Φ ft Φ μ- ϋ 0 fD μ- 3 ft μ- fD 0 0 tr 0 CQ CD fi Φ tr μ- rt φ Q rt fi 3 rr rt 0 μ- tn fD d 3 rt fD ft ft Ω SD CD CQ μ- tr μ- φ SD Φ fi rt > < CD 3 rr φ ø 0 Φ rt rt < ft σ Ω Φ ø 0 co CO SD Φ ø 0 3 0 μ- φ Φ Φ (D ø CQ fi ft rt 0 α μ- Hi ø TJ μ- 0 SD φ fi rt 0 rt CQ ø 0 3 CD CD Hj 0 o CQ fi 3 Hi ID's and for directing the interface unit to transmit an enabling signal to a terminating side adjacent functional unit responsive thereto. 20. The computer-readable medium of claim 19, the means for directing the interface unit to detect the attachment of additional functional units further comprising: means for directing the interface unit to detect a pulling and releasing of a voltage signal present at an originating unit detect bus lead, the originating unit detect bus lead for contacting an originating unit detect bus formed by the originating side functional units, each functional unit being capable of pulling the originating unit detect bus to a second voltage, each functional unit also being capable of releasing the originating unit detect bus, the originating unit detect bus lead being connected to a constant first voltage through a pullup resistor in the interface unit, whereby the first voltage is present at the originating unit detect bus lead only when no originating side functional module is pulling the originating unit detect bus to the second voltage, wherein each functional unit is capable of pulling and then releasing said originating unit detect bus upon initial attachment to the originating end of the linear array; and means for directing the interface unit to detect a pulling and releasing of a voltage signal present at a terminating unit detect bus lead, the terminating unit detect bus lead for contacting a terminating unit detect bus formed by the terminating side functional units, each functional unit being capable of pulling the terminating unit detect bus to a second voltage, each functional unit also being capable of releasing the terminating unit detect bus, the terminating unit detect bus lead being connected to a constant first voltage through a pullup resistor in the interface unit, whereby the first voltage is present at the terminating unit detect bus lead only when no terminating side functional module is pulling the terminating unit detect bus to the second voltage, wherein each functional unit is capable of pulling and then releasing said terminating unit detect bus upon initial attachment to the linear array. 21. The computer-readable medium according to claim 20, the means for directing the interface unit to detect when all originating side functional units have received logical ID's comprising: means for directing the interface unit to transmit as the first command a command directing all functional units to pull the originating or terminating unit detect bus to the second value; and means for directing the interface unit to detect the state of the originating unit detect lead subsequent to transmitting the first command, said functional modules being capable of releasing the originating or terminating unit detect bus upon being assigned a logical ID, whereby the originating unit detect lead will contain the first voltage after all originating side units have been assigned logical ID'S. 22. A computer-readable medium which can be used to direct a functional unit of a modular patient care system in receiving a sequential logical unit ID from an interface unit, the modular patient care system having a plurality of functional units attached to the interface unit so as to form a linear array of units having an originating end and a terminating end, the interface unit and the functional units each having an originating side facing the originating end and a terminating side opposite the originating side, the computer-readable medium comprising: means for directing the functional unit to pull and then release a unit detect bus upon initial power-up of the functional module, the unit detect bus formed by the functional unit and other functional units, each of the functional units being capable of pulling the unit detect bus to to h-» H o in o in O in o d H < tr ø CQ Ω Hi ft μ- SD rt a <; 0 ft 0 Hi P d 0 0 fD 0 Φ 0 μ- 0" ø fi 0 2. 0 Hi 0 CQ μ- -. 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Inventors: DOMITRZ CASIMER, DUFFY ROBERT J, RICHARDS EDWARD M, SEVERE LON M, STONE BENSON C, DOMITRZ, CASIMER, DUFFY, ROBERT, J., RICHARDS, EDWARD, M., SEVERE, LON, M., STONE, BENSON, C.
Applicants: ALARIS MEDICAL SYST INC, ALARIS MEDICAL SYSTEMS, INC.
Application year: 1998
Main classification: A61M31
IPC codes: A61B5, A61M5, G06F19, G06Q50