A screened EEPROM cell

Abstract: An EEPROM cell is described as having a screening metal structure (50) formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal (30). This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

Description: TECHNICAL FIELD This invention relates to a memory cell of the EEPROM type. BACKGROUND OF THE INVENTION The circuit and construction of an EEPROM cell is known, for example, from US Patent 5,107,461, and a process for manufacturing such cells is known from US Patent 5,132,239. Furthermore document GB-A-2 308 738 discloses an EEPROM memory cell, comprising: a floating gate transistor formed on a semiconductor substrate with a floating gate terminal, a conducting layer overlapping the semiconductor substrate, and a metal layer positioned further from the substrate than the conducting layer, wherein a screening structure is formed in the conducting layer and is arranged to substantially overlie the floating gate terminal. A typical field of application for EEPROMs is that of chip cards, better known as smart cards. In such applications, it is highly important to prevent the data contained in the memory from being read in an anomalous way, that is by unsealing the package and reading directly from the die through the terminals of the cell matrix, rather than through the terminals of the memory device. It is common practice, in manufacturing the integrated circuit, to cover the memory device, and hence the matrix, with a metal structure. Accordingly, a direct reading can only be effected by first removing this metal structure, which represents a difficult and critical operation susceptible to result in the memory contents being destroyed. SUMMARY OF THE INVENTION An embodiment of this invention provides a memory with improved protection against anomalous readings. The embodiment includes a memory cell of the EEPROM type having a floating gate terminal of the cell substantially overlaid by a screening metal structure. According to another aspect of the invention, a memory device and a smart card are also provided wherein a cell so constructed can be used to advantage. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a circuit diagram of an EEPROM cell according to the prior art. Figure 2 shows a layout of the memory cell in Figure 1, incorporating no metal layers. Figure 3 shows a layout of the memory cell in Figure 1 which incorporates metal layers. Figure 4 shows a layout of a memory cell incorporating metal layers in accordance with this invention. Figure 5 shows a smart card with an EEPROM memory matrix of memory cells according to Figure 4. DETAILED DESCRIPTION Referring to Figure 1, an EEPROM cell according to the prior art comprises a memory element consisting of a tunnel element 10, a transistor 12, and a capacitor 18. A terminal 301 of the element 10, the control terminal 302 of the transistor 12, and a terminal 303 of the capacitor 18 are all connected together to form the floating gate terminal 30 of the cell. The element 10 is the circuit component that allows charges to be injected into and extracted from the floating gate terminal 30 of the cell. The other terminal of the element 10 and the main (drain-source) conduction path of the transistor 12 are connected in series between a bit line 14 and a common line 16. A primary selection transistor 22 is connected between the line 14 and the element 10, and an auxiliary selection transistor 40 is connected between the source terminal of the transistor 12 and the line 16. By measuring the current flowing through the lines 14 and 16, the charged condition of the floating gate terminal 30 of the cell can be determined, and accordingly, these lines can be regarded as the read terminals of the cells. The control terminals of the transistors 22 and 40 are connected together and to a word line 24 forming the selection terminal 24 of the cell. The other terminal of the capacitor 18 is connected to a local line 20 forming the control terminal 20 of the cell. Depicted in Figure 2 is a conventional layout (having no metal layers) of the cell shown in Figure 1, wherein corresponding elements are denoted by the same references as in Figure 1. The line 24 and terminal 30 are formed in a polysilicon layer overlying an oxide layer; the thickness of this oxide is provided considerably small, so as to trigger the tunnel effect. Figure 3 shows the same layout as Figure 2, but with metal layers included. In particular, the lines 14 and 16 are formed in a first metal layer METAL1 Today's fabrication technology of integrated circuits can provide processes with a large number of metal layers, e.g., 4 or 5. Of course, the larger the number of layers, the greater becomes the process complexity and cost. It is customary to reference the layers as METAL1, METAL2, METAL3, etc., proceeding from the layer closest to the substrate toward the farthest layer from the substrate. Figure 4 shows a layout (incorporating metal layers) of a memory cell according to the invention, which reflects the layouts of Figures 2, 3, for the cell of Figure 1 as modified in conformity with the teachings of this invention. In a memory cell according to the invention, a screening metal structure 50 is arranged to overlie the floating gate terminal 30. Preferably, the structure 50 will fully cover the terminal 30 only. The screening metal structure 50 is formed in the first metal layer METAL 1. To reduce the resistivity of the word line 24, the selection terminal is provided by a polysilicon structure 241 contacting a metal structure 242 formed in the first metal layer METAL 1 in overlapped relationship. To obtain a compact cell layout, one or each read terminal 14, 16 may advantageously be provided by a metal structure formed in a metal layer following the first, specifically the second metal layer METAL2. For an anomalous reading from a memory device having a cell matrix as described above to be effected, it would be necessary to remove everything from above the first metal layer METAL 1. However, such an operation would eliminate the main connections (bit lines 14 and common lines 16) of the cell matrix, and then the anomalous reading could no longer be made by direct reading at the matrix terminals but only by directly measuring the amount of charge existing on the floating gate terminals 30 of the individual cells, which operation is made impracticable by the metal screen 50. Moreover, this screen 50 prevents the memory cell from being erased and programmed by radiation, e.g., UV radiation. Should the screen 50 be taken away by removing the metal layer METAL 1, there remains to be made the direct measurement of the charge on the terminals 30, an operation at once difficult and critical to perform. In addition, since the polysilicon layer that provides the terminals 30 locates very near the layer METAL1, an alteration of its charged state during the removal is most likely to occur. It could be arranged for a metal structure (not shown in Figure 4) formed in the third or following metal layers METAL3, METAL4, etc. to overlie the whole cell, thereby providing additional protection. The screening metal structure 50 may be connected electrically to a fixed reference of potential, preferably to ground. In this way, it would become impossible to measure the amount of charge on the terminal 30, even when using a potential-sensing electron microscope, because the structure 50 also functions as an electrostatic screen. Alternatively, the screening metal structure 50 could be connected electrically to the control terminal 20. This would increase the capacitive coupling between the control terminal and the floating gate terminal of the cell, and assist in the programming and erasing operations. It will be appreciated that such a cell may be used to advantage as a basic element for an EEPROM matrix, within memory devices, including smart cards. A smart card 60 including an EEPROM matrix 62 of memory cells of Figure 4 is shown in Figure 5.

Claims: An EEPROM memory cell, comprising: a floating gate transistor (12) formed on a semiconductor substrate with a floating gate terminal, a primary selection transistor (22) coupled to said floating gate transistor (12) and having a selection terminal (24), a first metal layer (METAL1) overlapping the semiconductor substrate, a second metal layer (METAL2) positioned further from the substrate than the first metal layer, wherein a screening metal structure (50) is formed in the first metal layer (METAL1) and is arranged to substantially overlie the floating gate terminal and the selection terminal (24) is formed by providing a polysilicon structure and a metal structure (242) formed in the first metal layer (METAL1) which contact each other in an overlapped relationship. A cell according to Claim 1, characterised in that it comprises a single polysilicon layer. A cell according to Claim 1, characterised in that it comprises a read terminal (14, 16) formed by a metal structure formed in a second metal (METAL2) layer or following metal layers. A cell according to Claim 3, characterised in that it comprises a metal structure formed in a third or following metal layers (METAL3, METAL4) is arranged to substantially overlie the whole cell. A cell according to Claim 1, characterised in that said screening metal structure (50) is connected electrically to a fixed reference of potential. A cell according to Claim 1, characterised in that it comprises a control terminal (20) connected electrically to said screening metal structure. An EEPROM memory device, comprising an EEPROM matrix formed of cells according to claim 1. A smart card, including an EEPROM matrix according to claim 7.

Inventors: LISART MATHIEU, PIO FEDERICO, SOURGEN LAURENT, ZATELLI NICOLA, LISART, MATHIEU, PIO, FEDERICO, SOURGEN, LAURENT, ZATELLI, NICOLA, Lisart, Mathieu c/o STMicroelectronics S.A., Sourgen, Laurent c/o STMicroelctronics S.A., Zatelli, Nicola STMicroelectronics Srl
Applicants: ST MICROELECTRONICS SA, ST MICROELECTRONICS SRL, STMICROELECTRONICS S.A., STMICROELECTRONICS S.R.L.
Application year: 1998
Main classification: H01L23
IPC codes: H01L21, H01L29, H01L27, G11C16