Phase locked loop

Abstract: A phase locked loop ("PLL") 28 containing apparatus for automatically causing the PLL to achieve phase lock when first energized or after having lost phase lock. In addition to a phase detector (4), loop filter (13), voltage controlled oscillator ("VCO") (14) and feedback from the VCO to the phase detector (16), the PLL has a sweep circuit (30). The sweep circuit cooperates with the loop filter when the PLL is not in phase lock to automatically generate a control voltage for the VCO which control voltage increases linearly with time until the PLL achieves phase lock or until the control voltage has reached the largest voltage in the dynamic input range of the VCO. In the event that phase lock is not achieved during the period of the increasing voltage, the control voltage decreases linearly with time to drive the PLL into phase lock. A network comprising at least a resistor (70,72) and a temperature sensitive resistor (74) is provided for compensating for temperature induced variations in the transfer function of the phase detector.

Description: FIELD OF THE INVENTION This invention relates generally to frequency control systems of the form commonly referred to as phase locked loops, and in the preferred embodiment, to analog phase locked loops. BACKGROUND OF THE INVENTION The phase locked loop ("PLL") is a widely used frequency control system commonly found in various types of electronic apparatus. The PLL can be used for a variety of applications and utilizes a voltage controlled oscillator ("VCO"). The PLL serves to slave the frequency output of the VCO to an input reference signal such that the VCO frequency tracks variations in the input reference signal. One problem common to many of the applications is the necessity for a search action to initially direct the VCO to the correct frequency required for the PLL to begin to function. This process is often referred to as achieving "lock". At the beginning of operation, absent such a search action, the VCO frequency may wander aimlessly and never achieve lock. A second problem is the requirement that this search action cease when the correct frequency is found and the PLL achieves lock. The search and lock scenario is an action that may occur many times during the time a PLL circuit is active. The requirement for PLL search is not new. Various approaches to achieve lock have been known in the past. Other known systems for the purpose of sweeping a VCO in an analog PLL fall into two categories: 1) self starting sine wave oscillators, and 2) search circuits requiring outside start/stop commands. Each of these two types has certain disadvantages associated with it. Self starting sine wave search circuits are usually very complicated and the search portion of the circuitry may represent an unacceptably high portion of the system. A typical prior art circuit of this type is illustrated in Figure 1. A phase detector 4 processes an input signal 2 to provide an output error signal. This error signal is an input to a bandlimiting loop filter 13 comprised of operational amplifier ("op-amp") 8, input resistor 6, feedback resistor 10 and feedback capacitor 12. The output of the loop filter drives VCO 14 which in turn generates the PLL output signal 18. The PLL output signal 18 is also fed back via divide-by-N circuit 16 to provide a second input to phase detector 4. The circuit described to this point is a well known type 2 second order PLL. As previously mentioned, at the beginning of operation the output signal 18 may not be at the correct frequency corresponding to the value of input signal 2. Absent additional intervention, the frequency may never reach the correct value so that lock can be achieved. The addition of feedback network 20 results in a search action which directs the VCO output frequency to the correct value. Feedback network 20 may be a Wien bridge or a shunt T network. It is connected to the non-inverting input of op-amp 8 so as to provide positive feedback around the op-amp. This positive feedback network cooperates with the characteristics of the loop filter to function as a sinewave oscillator, that is to generate a low frequency sinewave to sweep the VCO. When the VCO is driven to the correct frequency and the PLL achieves lock, the feedback with the PLL in lock is enough to overcome the positive feedback of the loop filter oscillator circuit and it stops oscillating. While the circuit appears straightforward, its applications are limited. The sine wave sweep is inefficient and the circuit elements are very critical. The loop filter design goals may have to be compromised to satisfy the additional oscillator requirements. The second category of prior art search circuits is illustrated in Figure 2. Again, the PLL used in this illustration is of type 2, second order, and its components are the same as those described in connection with Figure 1. In this case, the sweep action is provided by current injected into the feedback circuit of the loop filter by a switched constant current source 24. Current source 24 operates under the control of a search control signal 22 which in turn is generated by a search control circuit (not shown). The loop filter again does double duty. During search it acts as an integrator. A constant current input provided by current source 24 results in a ramp voltage provided to the VCO so as to drive it to the correct frequency and achieve lock. This type of search operation requires the additional circuitry to recognize when the PLL is not in lock and to generate the start and stop commands for the constant source 24. In addition to ensuring PLL lock, there can be problems with temperature variation. In particular phase detector output may not be symmetrical about ground, but offset by a value which changes with temperature. As described in Japanese Patent 07297707 and Patent Abstracts of Japan Vol. 096, no 003 temperature compensation of phase detector output is known but not in the context of providing acquisition of lock. The present invention seeks to address both issues and provides a phase locked loop and method as defined in the claims. An aspect of the invention with particular reference to the locking aspect thereof will be disclosed in the context of a type 2, second order PLL similar to that shown in Figures 1 and 2. The present invention provides a phase locked loop comprising: a phase detector having a first input for receiving an input reference signal, the transfer function of said phase detector being temperature dependent; a voltage controlled oscillator having an input coupled to the output of said phase detector; a feedback circuit for coupling the output of said voltage controlled oscillator to a second input of said phase detector; and a sweep circuit responsive to the signal level at the input of said voltage controlled oscillator for detecting the absence of lock in said phase locked loop and, in the absence of lock, being adapted to apply a sweep voltage to the input of said voltage controlled oscillator, said sweep voltage being terminated when phase lock is acquired, characterized in that said sweep circuit includes: a network comprising at least a resistor and a temperature sensitive resistor, said network being adapted to compensate for temperature induced variations in the transfer function of said phase detector; whereby said sweep voltage increases linearly with time until a predetermined maximum voltage is reached and then decreases linearly with time until a predetermined minimum voltage is reached, and the duration of said linearly increasing sweep voltage differs from the duration of said linearly decreasing sweep voltage. According to a second aspect of the invention there is provided a method for driving a phase locked loop into the locked condition, said phase locked loop including a phase detector, having a first input terminal for receiving an input signal, a loop filter having a first input terminal for receiving an output signal from the phase detector and a second input terminal, a voltage controlled oscillator having an input for receiving the output of the loop filter, a feedback circuit for coupling the output of said voltage controlled oscillator to a second input terminal of said phase detector, and a sweep circuit cooperating with said loop filter to provide a varying sweep voltage to said voltage controlled oscillator when said phase locked loop is not in a locked condition, the sweep circuit including a network comprising at least a resistor and a temperature sensitive resistor, said network being adapted to compensate for temperature induced variations in the transfer function of said phase detector, said method comprising the steps of: monitoring the signal level at the input of said voltage controlled oscillator to detect the absence of lock in said phase locked loop; in the absence of lock, applying a sweep voltage to the input of the voltage controlled oscillator by, providing a first constant level voltage from said sweep circuit to one terminal of the network for compensating for the temperature dependence of said phase detector, the other terminal of said network being coupled to said second input terminal of said loop filter, monitoring the output voltage of said loop filter, and in the event that said output voltage reaches a first predetermined level, changing said first constant level voltage to a second constant level voltage; terminating said sweep voltage when lock is acquired; and generating a temperature dependent signal level to compensate for temperature dependent variations in the transfer function of the phase detector, whereby said sweep voltage increases linearly with time until a predetermined maximum voltage is reached and then decreases linearly with time until a predetermined minimum voltage is reached, and the duration of said linearly increasing sweep voltage differs from the duration of said linearly decreasing sweep voltage. More specifically, the non-inverting input of the additional op-amp is coupled through an input resistor to the output of the loop filter, that is the input of the VCO. A second resistor is connected between this non-inverting input and the output terminal of the op-amp. As such, the op-amp, together with its associated resistors, functions as a well known Schmitt-trigger circuit. It's output voltage will always be a constant voltage at one of two levels. This output is coupled by a current limiting resistor to the inverting input of the op-amp used in filter 13. Assuming that the PLL is not in the locked condition, and if the Schmitt-trigger output voltage is at its high level, this output voltage is coupled through the current limiting resistor to the inverting input of the filter op-amp. Since, in the absence of lock, there will be no countervailing input from the phase detector, the current flowing through the current limiting resistor charges the capacitor in the feedback loop of the filter op-amp causing the VCO input voltage to decrease at a constant rate. If, during this period when its input voltage is decreasing, the VCO fails to reach an output frequency corresponding to the frequency of the reference signal, lock will not be achieved. Ultimately, the VCO input voltage will reach a value sufficiently low that it will cause the Schmitt-trigger circuit to switch to a new output voltage at a constant low level. Now the current flowing through the current limiting resistor flows in the opposite direction thereby charging the feedback capacitor of the filter op-amp in the opposite direction and the VCO input voltage begins to increase. In this way, the VCO input voltage takes the form of a triangular wave. (There will also be described an alternative embodiment wherein the VCO input voltage takes the form of a sawtooth). At some point during a period of this triangular wave, the VCO output frequency will correspond to the reference signal frequency, and lock will be achieved. When this happens, the output voltage of the Schmitt-trigger circuit will be at either the constant high or low voltage. If properly designed, the Schmitt-trigger will have sufficient hysteresis that it will only switch when the VCO input voltage is at its positive or negative extremity. If the PLL is operating normally, that is in lock, the VCO input voltage never reaches either of these extremities and the operation of the sweep circuit is inhibited. In contrast with the sinewave sweep circuits, it is not necessary to compromise the operation of the PLL with the needs of the sweep circuit. Further in connection with the second category of prior art sweep circuits described above, there is no need for additional circuits to generate start and stop commands. BRIEF DESCRIPTION OF THE DRAWINGS: The present invention will now be further described by way of example, with reference to the accompanying drawings in which: Figure 1 is a diagram of a prior art PLL using positive feedback to generate a sinewave search. Figure 2 is a diagram of a prior art PLL using a switched constant current source to generate a search voltage. Figure 3 is a block diagram of a PLL using the automatic sweep circuit of this invention. Figure 4 is a partial schematic diagram of the PLL with the automatic sweep circuit. Figure 5 shows representative voltage waveforms for the automatic sweep circuit. Figure 6 illustrates another embodiment of the invention along with a resultant waveform. Figure 7 illustrates additional circuit details of the automatic sweep circuit. Figure 8 illustrates an embodiment wherein a resistive network is added to compensate for temperature induced variations in the transfer function of the phase detector. DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION PLL 28 is depicted in block diagram form in Figure 3. Common reference designators are used for elements of Figure 3 which also appear in Figure 1. A reference input 2 is in the form of an analog signal having a certain frequency or containing a signal having a certain frequency. The function of PLL 28 is commonly to cause VCO 18 to produce an output signal 18 at the frequency of reference input 2 or at some multiple (not necessarily integral) of the frequency of reference input 2. Reference input 2 provides a first input signal to phase detector 4. A second input to the phase detector is the VCO output signal 18 after conditioning by frequency divider 16. In an application where the requirement is that the VCO provide an output frequency which is the same as the frequency of the reference input, the divide ratio of frequency divider 16 would be one and the output of VCO 14 could be coupled directly to the second input of phase detector 4. When the term frequency divider is used herein, it will be intended to embrace this condition of unity divide ratio. In the embodiment which will be described in greater detail here, the divide ratio is sixty-four. Phase detector 4 generates an error signal representing the difference between its two inputs and provides this error signal via line 5 to loop filter 13. Loop filter 13 conditions the error signal, typically by amplifying and bandpass filtering. The output of loop filter 13 is coupled to VCO 14 by line 7. The output of VCO 14 represents the output of the PLL and is also coupled to frequency divider 16 by line 11. Finally, the output of frequency divider 16 is coupled by line 15 to the second input of phase detector 4. The output of loop filter 13 is coupled by lines 7 and 9 to the input of sweep circuit 30. The input signal level on line 9 is used by sweep circuit 30 to generate voltages which control the sweep search when the PLL is not in lock, and serves to prevent action by the sweep circuit 30 when lock has been achieved. The output of sweep circuit 30 is coupled by line 17 to loop filter 13 so as to drive VCO 14 to the frequency where lock can be achieved. Figure 4 is a simplified schematic diagram of the PLL in sufficient level of detail to illustrate the principles of the invention. In the preferred embodiment, reference signal 2 has a nominal frequency of 15 Mhz. Phase detector 4 may be a model SYPD-1 available from Mini Circuits. The output of phase detector 4 is coupled by line 19 to the input of level shift circuit 32. The need for level shift circuit 32 is dictated by the desire to operate the PLL from a single power supply, having a nominal supply voltage of 8 volts. Phase detectors such as the SYPD-1 provide output voltages which vary in both the positive and negative directions from a DC voltage of zero volts. Given the single 8-volt supply voltage, the op-amps utilized in the PLL can only operate between voltage levels of zero and eight volts. Therefore, level shift circuit 32 is used to translate the output voltage of phase detector 4 from the level centered about zero volts to a level centered about some positive voltage, for example, four volts in the preferred embodiment. Level shift circuit 32 will be shown in greater detail in a later figure. Whilst a positive eight volt power supply is used in the preferred embodiment, the system will work equally well with negative supply voltages. The output of level shift circuit 32 is coupled to the input of the loop filter, comprised again of op-amp 8, input resistor 6, feedback resistor 10 and feedback capacitor 12. The non-inverting input of op-amp 8 is coupled to a four volt reference level. Op-amps 8 and 34 may be the two sections of an AD822 operational amplifier available from Analog Devices, Inc. The output of the loop filter is coupled by line 7 to VCO 14 which has its output on line 18. The output of VCO 14 has a nominal frequency of 960 Mhz and will vary over a small range on either side of this nominal frequency under control of input reference signal 2. VCO 14 may be a model POS-1060 available from Mini Circuits. The output of VCO 14 is also coupled by line 11 to frequency divider 16. Frequency divider 16, in the disclosed embodiment, has a divide ratio of sixty-four and is available in the form of a MC12022 integrated circuit from Motorola Inc. The divided down output of frequency divider 16, nominally at 15 Mhz, is coupled by line 15 to phase detector 4. The output of the loop filter is also provided by lines 7 and 9 to the input of sweep circuit 35. Sweep circuit 35 is comprised of input resistor 36, op-amp 34, feedback resistor 38 connected around op-amp 34, and a third resistor 40. The junction between resistors 36 and 38 is connected to the non-inverting input of op-amp 34 while the inverting input is connected to a four-volt reference. Finally, the output of op-amp 34 is coupled by resistor 40 to the inverting input of op-amp 8. Selection of the resistor and capacitor values for the components shown in Figure 4 is straightforward. Equations used for calculating these values with respect to the loop filter are well known and are summarized in an article entitled "Design of a Search Based PLL". This article was published in the Texas Instruments Technical Journal, Vol. 11, No. 2, March-April 1994, pp 112-120, Dallas Texas and also in the conference proceedings of RF Expo East, October 19, 1993, p.275, Tampa, Florida. The relevant equations are: (1) R fb = δ π * f n * C fp (2) R input = K vco * K pd 2π * f n 2 * C fb * N where: R fb is the feedback resistor 10 of Figure 4; δ is the desired damping ratio; f n is the desired natural frequency; C fb is the feedback capacitor 12; R input is the input resistor 6; K vco is the VCO gain, a known quantity for a given VCO; K pd is the phase detector gain, also a known for a given phase detector; and N is the divide ratio. In this design example, a standard value of one microfarad will be selected for C fb . Then with a target natural frequency of 212 Hz and target damping ratio of 4.14, the value of R fb is found from equation (1) to be 6,200 ohms. Other known parameters include the tuning rate of VCO 14, 2.239 Mhz/volt; the divide ratio of frequency divider 16, 64; and the conversion slope of phase detector 4, 0.81 volts/radian. With these parameters, the value of input resistor 6, R input , is found from equation (2) to be 100,000 ohms. With these parameters, the system has a resultant closed loop 3db frequency of 1886 Hz and a phase margin of 85.9 degrees. It remains to select the values of resistance associated with the Schmitt trigger circuit. The inverting input of op-amp 34 is referenced to +4 volts. As a result, whenever the non-inverting input is at a voltage greater than four volts, the output of this op-amp will be at the positive supply voltage, eight volts, and whenever the non-inverting input is at a voltage less than four volts, the output will be at ground or zero volts. As the non-inverting input passes through four volts, the output rapidly switches between these two voltage levels. The non-inverting input will be at four volts only during the very brief instants when the Schmitt trigger circuit is switching in one direction or the other. As a result, the non-inverting input is not constrained to any particular voltage, and input resistor 36 combines with resistor 38 to form a voltage divider between the output voltage of loop filter op-amp 8 (hereinafter the "sweep voltage") and the output voltage of the Schmitt trigger op-amp 34. Figure 5 illustrates the voltages at the outputs of these two op-amps during the search operation. In the instance illustrated here, it is desired that the sweep voltage be in the form of a triangular wave that varies between the one volt and seven volt levels. At the instant that an already operating PLL should lose phase lock, the output of op-amp 34 will be either at zero or at eight volts. For ease of illustration, assume that a this instant, t 1 , it is at zero volts and the sweep voltage is at one volt. Since the voltage divider consisting of resistors 36 and 38 is coupled between the zero and one volt levels, the non-inverting input of op-amp 34 will be at a voltage less than four volts. Given these conditions, feedback capacitor 12 will charge through resistors 40 and 10 and the sweep voltage will increase linearly. In this description this type of constant slope increasing (or conversely decreasing) sweep voltage will be referred to as varying linearly (or a linear variation) with time. This constantly increasing sweep voltage will continue until such time as the non-inverting input of op-amp 34 reaches the four volt level. It is desired that this happen at the instant that the sweep voltage reaches the seven volt level, designated as t 2 in Figure 5. At this instant, the voltage divider consisting of resistors 36 and 38 will be coupled between the seven volt level of the sweep voltage and the zero volt level at the output of op-amp 34. The voltage at the non-inverting input of op-amp 36, V ni is given by the following expression. V ni = (7V - 0V) * R 38 R 36+ R 38 A standard value such as 10,000 ohms may be selected for the value of resistor 38. Then, letting V ni be equal to four volts, this equation can be solved for the value of R36 which turns out to be 7,500 ohms. With these values for resistors 36 and 38, the sweep voltage will reach its. maximum positive value at t 2 . At this instant, the Schmitt trigger flips, its output goes to the eight volt level, and capacitor 12 begins to charge in the opposite direction with the result that the sweep voltage begins to decrease at a linear rate with time. It remains to determine the value of resistor 40. The value of this resistor along with the value of capacitor 12 determine the time required for the sweep voltage to cover the upsweep or downsweep. Let it be assumed that, in either case, it is desired that the sweep occupy a period of 1.5 seconds. During either of these sweeps, the voltage across capacitor 12 will undergo a change of seven - one = six volts. Given the well known relationship between the voltage, V, and charge,q, on a capacitor, C, q = VC, and with a one microfarad capacitor, the change in charge, dq, corresponding to a six volt change, dV, is 6/10 6 . The current which provides this charge flows through resistor 40 is constant since the voltage at one end of the resistor, the output of op-amp 34, will be constant at either zero volts or eight volts, and the voltage at the other end, the inverting input of op-amp 8, will be constant at four volts. The value of this current then is 4/R where R is the resistance of resistor 40. In calculating voltage changes, the voltage drop across feedback resistor R10 can be ignored since, with constant current flowing through it, .this voltage drop will be constant. The change in capacitor charge, dq, is simply the product of this current and the time of the sweep, 1.5 seconds. Therefore: dq = 6/10 6 = (4/R) * T = (4/R) * 1.5 The solution of this equation gives 1 megohm as the value of resistor 40. Assuming the presence of a valid reference input frequency 2, at some point during the sweep the VCO will be driven to this frequency and the PLL will achieve lock. (In the absence of a valid reference input frequency, the sweep action will simply continue until a valid input is applied to the system.) As the time lock is achieved, depending on whether lock was achieved during an upsweep half cycle or a downsweep half cycle, the output of the Schmitt trigger will be at either zero volts or eight volts. As long as lock continues, the voltage will remain at that level. The inverting input of op-amp 8 will continue to be constrained to the four volt level, so there will be a constant four volt drop across resistor 40 and a corresponding current in the resistor. In the locked condition, this current can not flow into capacitor 12 as was the case during the sweep operation, and flows instead through resistor 6. Since resistor 6 has a resistance of only 100,000 ohms, the result will be an error voltage of 0.4 volts at the output of level shift circuit 32. The only effect of this is a shift in the phase of the VCO output signal. In many applications this is of no consequence, and in such applications the sweep circuit has, in effect, automatically terminated its sweep action during the period that the PLL is in lock. In the foregoing discussion of the sweep circuit, it was assumed that the sweep voltage was at one volt at the instant that the sweep process began. In fact, the sweep voltage will normally be at some voltage between the one and seven volt levels. The sweep operation will begin somewhere between the one and seven volt levels of one half cycle of the triangular sweep and proceed as described above. In summary, the sweep circuit of this invention automatically initiates the search operation whenever there is an absence of lock in the PLL. Normally, within one full cycle of the triangular sweep waveform, lock will be achieved. When this occurs, the sweep circuit effectively and automatically terminates the sweep action. Figure 6(a) is a schematic diagram of an alternative embodiment of the invention. As a result of this modification, the sweep voltage waveform takes the form of a sawtooth as illustrated in Figure 6(b). This is achieved by placing the series combination of a diode 44 and a relatively small resistor 42 in parallel with resistor 40. The diode is oriented to conduct current in the direction of the inverting input of op-amp 8. When the output of op-amp 34 is at the eight volt level the diode conducts, charging capacitor 12 very rapidly with the result that downsweep of the sweep voltage is almost instantaneous. If, for example, resistor 42 is a 10,000 ohm resistor (1/100 of the resistance of resistor 40), then the positive to negative "flyback" of the sweep voltage waveform will occupy a time period of approximately 0.015 seconds. As shown in Figure 6(b), this is virtually instantaneous in comparison with the period of the upsweep. When the sweep voltage reaches the lower end of its range (one volt in the example above), the Schmitt trigger switches its output low, diode 44 becomes back biased, and the circuit proceeds through an upsweep as above described. The sweep voltage flyback is sufficiently rapid that the system will not achieve lock during this flyback period. It is a certainty, then, that lock will be achieved only during the relative slower upsweep. The output of op-amp 34 is low during the upsweep and, assuming that lock is achieved during an upsweep, will remain low during the time period while lock is maintained, that is during the time of normal operation of the PLL. Thus, when the PLL is in lock, the diode will be back biased, and will have no impact on the normal operation of the PLL. In another variation, the direction of the diode may be reversed. In this event, a sawtooth sweep signal will again be produced, but the flyback will occur at the end of the downsweep. Figure 7 illustrates additional details of the invention. Frequency divider 16 is seen to be the MC12022SLA integrated circuit. Transistors 50 and 52 may typically be 2N2222 transistors and, as is well understood in the art, are used to amplify the divided VCO output signal and provide impedance matching to phase detector 4. Resistors 54, 56 and 58 divide down the eight volt supply voltage so as to provide the correct reference voltages for the op-amps. Since there is virtually no loading of these reference voltages by the high input impedances of the op-amps, it is a simple matter to select the correct resistor values. In the preferred embodiment, resistor 54 is equal to the sum of resistors 56 and 58 with the result that the inverting input of op-amp 34 and the non-inverting input of op-amp 8 are referenced to four volts. Resistors 56 and 58 are of equal value so that the non-inverting input of op-amp 60 is referenced to two volts. The precise resistance of these two resistors is a matter of design choice. Let it be represented by the symbol R. Op-amp 60 may also be one section of an AD822, or any comparable op-amp. Resistors 62 and 66 are each chosen to have a resistance of 0.5R and resistor 68 a resistance of R. As a result, the gain of op-amp 60 with the feedback around it is unity, and the op-amp simply serves to shift the level of the signal coming from phase detector 4 to being centered about four volts. Capacitor 64 is chosen to cooperate with the resistances in the circuit to provide low pass filter action with a cutoff frequency near 300 Khz. As is well known, the output of phase detector 4 will have components representing both the sum and difference of the reference input and feedback signals. This low pass filtering action serves to prevent the sum of these two signals from distorting the operation of the op-amps. Another alternative embodiment of the invention is shown in Figure 8. The modification here consists of the replacement of resistor 40 by a network consisting of resistors 70 and 72 along with a temperature sensitive resistor or thermistor 74. In this context the term "thermistor" should be understood to contemplate a resistive element which has either a positive or a negative variation in resistivity with temperature. The functionality of op-amps 8, 34 and 60, resistors 6, 10 and 42, capacitor 12 and diode 40 have been discussed above. Just as in the case of the modification illustrated in Figure 6 (a), the portion of the circuit shown in Figure 8 utilizes resistor 42 and diode 44 to ensure that lock is achieved only when the sweep is moving in a desired direction. With diode 44 in the orientation shown, once lock has occurred, the output voltage of the Schmitt trigger will be at its low value. While the resistive network provides the same functionality as does resistor 40 in the earlier disclosed embodiment, that is to cooperate with the value of feedback capacitor 12 to determine the rate of sweep, its particular characteristics serve to compensate for temperate variations which may occur in the transfer function of phase detector 4. In some cases, available phase detectors may depart from the ideal in the sense that their outputs may not be symmetrical about ground, but are offset by some value which changes with temperature. Such is the case with a phase detector such as that available from Alpha Industries under the product designator SPD3456-18. When the phrase "temperature dependent variations in the transfer function of the phase detector" or like expressions are used in this description and the claims appended hereto, such references shall be intended to include and be descriptive of this temperature dependent offset. The variation in offset caused by temperature variations is often not acceptable, but can be resolved with the modified circuit of Figure 8. This is achieved as follows: Let it be assumed for the purposes of illustration that the D.C. output of phase detector 4 is not at zero volts, but is, instead, offset by some positive voltage which offset voltage increases as the temperature increases. In the PLL which has been disclosed above, there will be a certain offset voltage at the output of level shifting op-amp 60. As has been previously noted, this offset comes about as follows. With diode 40 oriented in the direction shown, it is certain that lock will be achieved only when the output of Schmitt trigger op-amp 34 is at its low level. Therefore, once lock is achieved, the current flowing through resistor 42, or through the resistive network comprised of resistors 70 and 72 along with thermistor 74, must flow in the direction of the output of op-amp 34. While this current flows through feedback resistor 10 during the sweep process, it is forced to flow through input resistor 6 once lock is achieved. This current causes a voltage drop across input resistor 6 and, since the inverting input terminal of op-amp 8 is slaved to the four volt reference at its non-inverting terminal, there will result a positive offset voltage at the output of op-amp 60. It is desired that, as the ambient temperature of the circuit varies, this offset be caused to vary in the same way as does the D.C. offset voltage of phase detector 4, that is to increase with temperature. This can be accomplished if thermistor 74 is chosen to be a device having a negative temperature characteristic, that is one wherein the resistance decreases with increasing temperature. Such devices are available from Texas Instrument Incorporated under the name Senistor™. While the overall resistance of the resistive network should be nominally one megohm to ensure the proper sweep speed, it will decrease slightly as the temperature increases because of the operation of thermistor 74. As this overall resistance decreases, the current flowing through the network will increase slightly because the voltage across the network remains constant. This increased current, flowing through input resistor 6, will cause the offset voltage at the output of op-amp 60 to increase. By proper selection of resistors 70,72 and thermistor 74, this increase in offset can be designed to very closely track the temperature generated increase in the offset of phase detector 4.

Claims: A phase locked loop comprising : a phase detector (4) having a first input for receiving an input reference signal, the transfer function of said phase detector being temperature dependent; a voltage controlled oscillator (14) having an input coupled to the output of said phase detector; a feedback circuit for coupling the output of said voltage controlled oscillator to a second input of said phase detector; and a sweep circuit (30) responsive to the signal level at the input of said voltage controlled oscillator for detecting the absence of lock in said phase locked loop and, in the absence of lock, being adapted to apply a sweep voltage to the input of said voltage controlled oscillator, said sweep voltage being terminated when phase lock is acquired, characterized in that said sweep circuit includes: a network comprising at least a resistor (70, 72) and a temperature sensitive resistor (74), said network being adapted to compensate for temperature induced variations in the transfer function of said phase detector; whereby said sweep voltage increases linearly with time until a predetermined maximum voltage is reached and then decreases linearly with time until a predetermined minimum voltage is reached, and the duration of said linearly increasing sweep voltage differs from the duration of said linearly decreasing sweep voltage. A phase locked loop as claimed in Claim 1 comprising: a loop filter having an input coupled to the output of said phase detector. The phase locked loop of Claim 2, wherein said sweep circuit is arranged such that during those periods when the phase locked loop has not acquired lock, it alternately applies two different constant level currents to said loop filter. The phase locked loop of Claim 2 or 3, wherein said loop filter comprises an operational amplifier having an input resistor coupled to its inverting input and a resistor-capacitor network coupled between the output of said operational amplifier and said inverting input, and wherein said sweep circuit comprises a Schmitt trigger circuit responsive to the output voltage of said loop filter to provide alternatively a first fixed voltage level and a second fixed voltage level. A phase locked loop as claimed in any preceding claim, wherein, when said phase locked loop is not in lock, the input voltage of said voltage controlled oscillator is swept to drive its output frequency to a frequency corresponding to the frequency of said input reference signal. A method for driving a phase locked loop into the locked condition, said phase locked loop including a phase detector, having a first input terminal for receiving an input signal, a loop filter having a first input terminal for receiving an output signal from the phase detector and a second input terminal, a voltage controlled oscillator having an input for, receiving the output of the loop filter, a feedback circuit for coupling the output of said voltage controlled oscillator to a second input terminal of said phase detector, and a sweep circuit cooperating with said loop filter to provide a varying sweep voltage to said voltage controlled oscillator when said phase locked loop is not in a locked condition, the sweep circuit including a network comprising at least a resistor (70, 72) and a temperature sensitive resistor (74), said network being adapted to compensate for temperature induced variations in the transfer function of said phase detector, said method comprising the steps of: monitoring the signal level at the input of said voltage controlled oscillator to detect the absence of lock in said phase locked loop; in the absence of lock, applying a sweep voltage to the input of the voltage controlled oscillator by, providing a first constant level voltage from said sweep circuit to one terminal of the network for compensating for the temperature dependence of said phase detector, the other terminal of said network being coupled to said second input terminal of said loop filter, monitoring the output voltage of said loop filter, and in the event that said output voltage reaches a first predetermined level, changing said first constant level voltage to a second constant level voltage; terminating said sweep voltage when lock is acquired; and generating a temperature dependent signal level to compensate for temperature dependent variations in the transfer function of the phase detector, whereby said sweep voltage increases linearly with time until a predetermined maximum voltage is reached and then decreases linearly with time until a predetermined minimum voltage is reached, and the duration of said linearly increasing sweep voltage differs from the duration of said linearly decreasing sweep voltage. The method of Claim 6, further comprising the step of: in the event that the phase locked loop does not acquire lock during the time when said second constant level voltage is applied to said one terminal of said current limiting resistor, changing said second constant level voltage to said first constant level voltage. The method of Claim 6 or 7 further comprising the step of: providing a second current path coupling said first and second constant level voltages to said second input terminal of said loop filter, said second path comprising the series combination of a diode and a second resistor, said series combination being placed in parallel with said current limiting resistor.

Inventors: BLACK MICHAEL F, BLACK, MICHAEL F.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1998
Main classification: H03L7
IPC codes: H03L7, H03L1