LOW TEMPERATURE METAL FILL REGIONS FOR OHMIC CONTACTS AND VIA OPENINGS

Abstract: A relatively low temperature metal deposition method is disclosed for reliably and completely filling with metal ohmic contact openings and/or via holes or openings between spaced apart metalization layers in a semiconductor structure. The method incorporates several process steps including depositing a layer of Titanium or Titanium based metal into the ohmic contact opening and/or via hole followed by successive depositions of a metal seed layer of an Aluminum based metal such as Aluminum Silicon Copper to partially fill the ohmic contact opening and/or via hole and a metal covering layer of an Aluminum based metal such as Aluminum Silicon Copper to completely fill the ohmic contact opening.

Description: OW TEMPERATURE METAL FILL REGIONS FOR OHMIC CONTACTS AND VIA OPENINGS Field Of The Invention This invention relates to methods for fabricating semiconductor structures and semiconductor structures resulting therefrom and. more particularly, to a method of forming low temperature metal fill regions for ohmic contacts and for via openings between spaced apart metal layers and semiconductor structures resulting therefrom. Background Of The Prior Art In the past, various methods were developed to deposit metal layers onto insulating layers as part of the process of fabricating semiconductor device structures in making a semiconductor integrated circuit. For example, metal evaporation techniques were used to deposit metal layers onto insulating layers as part of the process of making a semiconductor integrated circuit. Other metal deposition techniques included either D.C. or A.C. metal sputtering operations. A critical and important process consideration was to avoid semiconductor device and, subsequently, semiconductor integrated circuit failures resulting from a process inability to completely and reliably fill with metal the ohmic contact openings and/or via holes or openings between spaced apart metal layers. The failure to completely and reliably fill with metal each ohmic contact opening and/or each via hole or opening between spaced apart metal layers would create a "void" or an electrical "open" in the desired electrical connection thereby causing both device and circuit failure. Consequently, an "open" or "void" in the metal fill for an ohmic contact opening or the via hole or opening became a very serious problem for semiconductor device or semiconductor integrated circuit manufacturers. Since the metal fill operation or process step occurs later in the semiconductor device or semiconductor integrated circuit manufacturing process after the formation of P and/or N regions in the semiconductor substrate, an undesired "void" or "open" created in the metal fill process step meant that all of the expense and time that was expended in the earlier steps of the semiconductor device or semiconductor integrated circuit manufacturing process was wasted. Correspondingly, since an "open" or "void" in the metal fill operation was not easily ascertained, then the costs and time associated with the remaining semiconductor process steps in completing the semiconductor device or semiconductor integrated circuit was also lost. As a result, it became extremely important in the process or method of forming semiconductor devices or semiconductor integrated circuits to develop a reliable metal fill process step. However, solving the problem of avoiding "voids" or "opens" in a metal fill operation or process step in fabricating semiconductor devices or semiconductor integrated circuits was not enough because any possible solution to this problem that used relatively high temperatures in the metal deposition process step destroyed or severely damaged certain low k dielectric materials that were used or deposited prior to the metal fill process step. Therefore a critical need existed for a method of forming low temperature metal fill regions that would be extremely reliable and that would avoid "shorts" or "opens" in the formation of metal filled ohmic contacts and/or metal filled via holes. Summary Of The Invention It is an object of this invention to provide an improved method of forming reliable metal fill regions for ohmic contact openings and/or via holes and a resulting semiconductor structure fabricated therefrom. It is a further object of this invention to provide an improved method of forming, at low temperatures, reliable metal fill regions for ohmic contact openings and/or via holes and a resulting semiconductor structure fabricated therefrom. It is a still another object of this invention to provide an improved method of forming, at low temperatures, reliable metal fill regions for ohmic contact openings and/or via holes which uses the deposition of an initial metal seed layer which partially fills the ohmic contact openings and/or via holes followed by the deposition of another metal covering layer which completely fills the ohmic contact openings and/or via holes as well as covers the edges of the portions of the insulating layers defining the ohmic contact openings and/or via holes and a resulting semiconductor structure fabricated therefrom. Brief Description Of The Preferred Embodiments In accordance with one embodiment of this invention, a method is disclosed of filling with metal an ohmic contact opening located within an insulating layer formed on a semiconductor substrate which comprises the steps of: forming an ohmic contact to an exposed surface portion of the semiconductor substrate within an opening in the insulating layer; depositing a layer comprising a Titanium based metal on the metal ohmic contact, on side portions of the opening and on a top surface of the insulating layer; depositing a seed layer of an Aluminum based metal onto the layer of Titanium based metal partially filling the opening; and depositing an Aluminum based metal layer onto the seed layer of an Aluminum based metal to completely fill the opening with metal and to cover with metal top edge portions of the opening. In accordance with another embodiment of this invention, a method is disclosed of filling with metal an ohmic contact opening located within an insulating layer formed on a semiconductor substrate which comprises the steps of: forming an ohmic contact to an exposed surface portion of the semiconductor substrate within an opening in the insulating layer; depositing a reaction induced creep enhancing layer on the metal ohmic contact, on side portions of the opening and on a top surface of the insulating layer; depositing a seed layer of an Aluminum based metal onto the reaction induced creep enhancing layer partially filling the opening; and depositing an Aluminum based metal onto the seed layer to completely fill the opening with metal and to cover with metal top edge portions of the opening. In accordance with a further embodiment of this invention, a method is disclosed of filling with metal a via hole located within at least one insulating layer and above an exposed metal land portion formed above a semiconductor substrate which comprises the steps of: depositing a layer of Titanium on the exposed metal land portion, on side portions of the at least one insulating layer defining the via hole and on a top surface of the at least one insulating layer; depositing an Aluminum based metal on the layer of Titanium partially filling the via hole; and depositing an Aluminum based metal layer on the seed layer of an Aluminum based metal to completely fill the via hole and to cover with metal top edge portions of the via hole. In accordance with a still further embodiment of this invention, a method is disclosed of filling with metal both an ohmic contact opening located within an insulating layer on a semiconductor substrate and a via hole located within at least one insulating layer and above an exposed metal land portion formed above the semiconductor substrate which comprises the steps of: forming an ohmic contact to an exposed surface portion of the semiconductor substrate within an opening in the insulating layer; depositing a layer comprising a Titanium based metal on the metal ohmic contact, and on side portions of the opening and on a top surface of the insulating layer; depositing a seed layer of an Aluminum based metal onto the layer of Titanium based metal partially filling the opening; depositing an Aluminum based metal layer onto the seed layer of an Aluminum based metal to completely fill the opening with metal and to cover with metal top edge portions of the opening; depositing a layer of Titanium on the exposed metal land portion, on side portions of the at least one insulating layer defining the via hole and on a top surface of the at least one insulating layer; depositing a seed layer of an Aluminum based metal on the layer of Titanium partially filling the via hole; and depositing an Aluminum based metal layer on the seed layer of an Aluminum based metal to completely fill the via hole and to cover with metal top edge portions of the via hole. The foregoing and other objects, features and advantages of this invention will be apparent from the following more particular description of the preferred embodiments of the invention as illustrated in the accompanying drawings. Brief Description Of The Drawings Figure 1 is a side elevational sectional type view depicting a starting semiconductor substrate of one conductivity type having a region therein of opposite type conductivity and an insulating layer on one surface thereof with an opening therein exposing a surface portion of the region of opposite type conductivity. Figure 2 is a side elevational sectional type view showing a layer of Titanium deposited on the insulating layer and in the opening therein of the structure of Figure 1. Figure 3 is a side elevational sectional type view showing a layer of Titanium Nitride deposited on the Titanium layer of the structure of Figure 2. Figure 4 is a side elevational sectional type view showing the formation of a Titanium Suicide ohmic contact to the region of opposite type conductivity created by a heat treatment of the structure of Figure 3. Figure 5 is a side elevational sectional type view of the structure of Figure 4 after the deposition of a Titanium layer on the top surface thereof. Figure 6 is a side elevational sectional type view of the structure of Figure 5 after the deposition of an Aluminum Silicon Copper seed layer on the top surface thereof partially filling the opening. Figure 7 is a side elevational sectional type view of the structure of Figure 6 after the deposition of an Aluminum Silicon Copper layer on the top surface thereof completely filling the opening and also covering the top edge portions of the opening. Figure 8 is a side elevational sectional type view of the structure of Figure 7 showing a portion of the metal (Aluminum Silicon Copper) formed as the first metal stripe for the structure of Figure 7 spaced from the region of opposite type conductivity (not shown) in the semiconductor substrate. Figure 9 is a side elevational sectional type view of the structure of Figure 8 after the deposition of a Silicon Dioxide layer thereon. Figure 10 is a side elevational sectional type view of the structure of Figure 9 after the deposition of a Spin On Glass/low k Dielectric (SOG) on the top surface thereof to fill in and planarize the top surface of the structure. Figure 11 is a side elevational sectional type view of the structure of Figure 10 after the deposition of a Silicon Dioxide layer on the top surface thereof and after the formation of a via hole or opening through the Silicon Dioxide layers above the metal land portion to expose a surface portion thereof. Figure 12 is a side elevational sectional type view of the structure of Figure 11 after the deposition of a layer of Titanium over the top surface of the structure and on the side walls and bottom portions of the via hole or opening. Figure 13 is a side elevational sectional type view of the structure of Figure 12 after the deposition of an Aluminum Silicon Copper seed layer on the top surface of the structure partially filling the via hole or opening. Figure 14 is a side elevational sectional type view of the structure of Figure 13 after the deposition of an Aluminum Silicon Copper layer on the top surface of the structure completely filling the via hole or opening and covering the top edge portions of the Silicon Dioxide layer defining the via hole or opening. Description Of The Specification Referring to Figure 1, a silicon semiconductor substrate 10 is shown formed of, for example, a P-type conductivity (if desired, the substrate 10 can be of the opposite N- type conductivity and thus the conductivity of N region 12 shown in the substrate 10 would be opposite (or P-type) to the N conductivity region shown in Figures 1-7). The substrate 10 of Figure 1 is a portion of a semiconductor chip containing various regions of selected N or P type conductivity (not shown). The N type region 12 is formed using diffusion or ion implantation techniques preferably in an opening formed by photolithographic masking and etching operations in an insulating layer that exposes a surface portion of the semiconductor substrate 10. In the embodiment depicted in Figure 1, an insulating layer 14 is formed on the top surface of the semiconductor substrate 10. Preferably, the insulating layer 14 comprises a bottom portion of Silicon Dioxide (not shown) which is in contact with the top surface of the semiconductor substrate 10 and the predominant portion of the insulating layer 14 comprises Boron Phosphorous Silicate Glass (BPSG)/low k Dielectric which can be created during the process of forming P type regions (not shown) in the semiconductor substrate 10 using a Boron (P type) impurity and N type regions in the semiconductor substrate such as the N type region 12 using a Phosphorous (N type) impurity. The thickness of the semiconductor substrate 10, the depth of the N type region 12 and the thickness of the BPSG insulating layer 14 can be varied as desired. Preferably, the BPSG insulating layer 14 has a thickness of several thousand Angstroms. An opening 16 is formed in the insulating layer 14 preferably by photolithographic masking and etching techniques using Photoresist (not shown) to etch away the portion of the insulating layer 14 to form the opening 16 and to expose a surface portion of the semiconductor substrate to create the N type region 12 by either diffusion or ion implantation. Referring to Figure 2, a layer 18 of Titanium is deposited on the top surface of the semiconductor structure of Figure 1. The layer 18 of Titanium preferably has a thickness of about 500 Angstroms and this layer 18 coats the side wall portions of the opening 16, the bottom portion of the opening 16 and the top surface portion of the insulating layer 14 as shown in Figure 2. Referring to Figure 3, a Titanium Nitride layer 20 is deposited on the Titanium layer 18 and this Titanium Nitride layer coats the side wall portions of the opening 16, the bottom portion of the opening 16 and the top surface portion of the Titanium layer 18. Referring to Figure 4, the semiconductor structure of Figure 3 is heat treated or annealed in a furnace preferably at a temperature of about 450-600 degrees C. for a sufficient period of time to form a Titanium Suicide (TiSi 2 ) relatively shallow ohmic contact 22 to the N type region 12. The top two surface layers, namely, the Titanium Nitride (TiN) layer 20 and the underlying Titanium layer 18 together provide a barrier layer to permit the formation of the relatively shallow ohmic contact 22 to the N type region 12. This barrier layer prevents spike through of Aluminum from the Aluminum based metal layer subsequently deposited on the barrier layer as described below. Referring to Figure 5. a second titanium layer 24 is deposited on a top surface of the semiconductor structure of Figure 4. After the heat treatment used to form the ohmic contact 22, the two separate layers 20 and 18, (layer 18 merges with Doped Silicon Region) merge together to form, in effect, a single barrier layer 19 comprising both Titanium Nitride and Titanium and Titanium Silicide 22 as shown in Figure 5. The deposited Titanium layer 34 preferably has a thickness of about 500 Angstroms and serves to cover the top surface of the barrier layer 19 and the side and bottom portions of the opening 16. The layer 34 can be another refractory metal such as Tungsten Molybdenum, Platinum or Cobalt, however, Titanium is preferred for the disclosed embodiment. The Titanium is a Reaction Induced Creep Enhancing layer which synergistically reacts with a subsequently deposited Aluminum Silicon Copper layer because of the presence of Silicon therein which is a Reaction Enhancing Metalization Impurity to permit the low temperature metal fill for the ohmic contact opening 16 and for the subsequently described metal fill for the via hole or opening. This reaction between the Titanium and Silicon facilitates and enhances drawing the metal fill into the ohmic contact and via openings. Referring to Figure 6, a metal seed layer 26 of an Aluminum based metal and preferably Aluminum Silicon Copper is deposited on the top surface of the semiconductor structure of Figure 5. As shown in Figure 6, the seed layer 26 partially fills the opening 16 and coats the side and bottom portions thereof as well as the top surface of the Titanium layer 24. Preferably, this metal seed layer 26 is deposited at a high deposition rate (i.e. a thickness of 1200 Angstroms is achieved at a deposition rate of 150 Angstroms per second. The temperature of the cold deposition ranges from ambient to about 250 degrees Centigrade. If desired, the metal seed layer 26 can have a thickness of from about 500-2000 Angstroms. Referring to Figure 7, a metal covering layer 28 of Aluminum Silicon Copper is deposited on the top surface of the semiconductor structure of Figure 6. This metal covering layer 28 is preferably deposited at a relatively low deposition rate (i.e. 20 Angstroms per second) and at a low temperature in the range of from about 240 decrees C to about 380 C. The thickness of the Aluminum Silicon Copper metal covering layer 28 is selected to completely fill the opening 16 of the semiconductor structure of Figure 6 and to thereby cover the top edge portions of the opening 16 to prevent the possibility of an "open" or "short" from being created in the formation of the Aluminum Silicon Copper metal covering layer 28 that serves as the first level of metalization (Metal 1 ) layer. As can be seen with reference to Figure 7, the metal covering layer 28 of Aluminum Silicon Copper merges with underlying layer 30 which is a combination metal layer of a Titanium Silicide (TiSi x ) plus a Titanium Aluminum Silicide (TiAl x Si y ) because of the reaction of Titanium in prior layer 24 (see Figure 6) with the seed layer 26 (Figure 6). Referring to Figure 8, a portion of the metal covering layer 28 which is the first level of metalization (Metal 1 ) of Aluminum Silicon Copper is shown as part of the metal land or metal stripe to carry electrical current to or carry electrical current away from the N region 12 (see Figure 7). After a suitable metal etching operation (not shown) using, for example, a photoresist mask (not shown), the remaining portion of the Metal 1 layer 28 is provided or formed as shown in Figure 8. For ease in illustration, the semiconductor structure depicted in Figure 8 is shown as spaced away from the N type region 12 to more simply show how the method of reliably and completely filling a via hole from a second level of metalization (not shown in Figure 8) is carried out to make electrical contact between the second level of metalization to the first level of metalization as shown by the metal land or metal stripe portion 28 in Figure 8. Referring to Figure 9, a Silicon Dioxide layer 32 is deposited onto the top surface of the semiconductor structure of Figure 8. This Silicon Dioxide layer 32 covers the exposed top surface portion of the BPSG layer 14 and the metal land portion 28. Referring to Figure 10, an insulating layer 34, which is preferably a Spin On Glass layer, is deposited on the top surface portions of the semiconductor structure of Figure 9 and then etched back to provide the substantially planar top surface configuration shown in Figure 10. Thus, the Spin On Glass layer 34 which is a low k dielectric insulating layer serves, in effect, as a filler layer and support layer for subsequent depositions as described below. The advantages of the Spin On Glass layer 34 is its ease of use and deposition, however, since it is made of a low k dielectric material, it cannot withstand high temperatures associated with prior art metal deposition techniques. Referring to Figure 11, this Figure depicts the resulting semiconductor structure after the deposition of a relatively thick Silicon Dioxide layer 36 and the formation of a via hole or opening 38 therein by, for example, photolithographic masking and etching techniques using photoresist (not shown) as a mask. This via hole or opening 38 is used to permit electrical connection between a second level of metalization (not shown in Figure 11) and the first level of metalization (Metal 1) which is the portion of the metal land 28. Referring to Figure 12, a layer of Titanium 40 (preferably having a thickness of about 500 Angstroms) is deposited on the top surface of the semiconductor structure of Figure 11. This layer 40 of Titanium covers the side and bottom portions of the via hole or opening 38 as well as the top surface of the Silicon Dioxide layer 36. The Titanium layer 40 functions as a Reaction Induced Creep Enhancing layer as described below with reference to the Titanium layer 34 used in the metal fill operation for the ohmic contact opening 16. Referring to Figure 13, a metal seed layer 42 of an Aluminum based letter such as Aluminum Silicon Copper is deposited on the top surface of the semiconductor structure of Figure 12. This metal seed layer 42 has a thickness sufficient to partially fill the via hole or opening 38 and coats or covers the side and bottom portions of the via hole or opening 38 and also coats the top surface of the Titanium layer 40. The metal seed layer 42 contains Silicon which is a Reaction Enhancing Metalization Impurity as described below with respect to the metal seed layer 26. Referring to Figure 14, a metal covering layer 44 of Aluminum Silicon Copper, which serves to create the second level of metalization (Metal 2) is deposited on the metal seed layer 42 (see Figure 13). The metal seed layer 42 of Figure 13 combines with the Titanium layer 40 (see Figure 13) to create a metal layer or region 41 that comprises Titanium Aluminum Silicide (TiAl x Si y ) and Titanium Silicide (TiSi x ) 41. This metal layer 41 is part of the metal covering layer 44 which is the Metal 2 (second level metalization) layer. Subsequent metal etching operations (not shown) can be used to define metal lands or metal stripes for the Metal 2 layer 44. As can be seen with reference to Figure 14, the Metal 2 layer 44 functions to completely fill the via hole or opening 38 (see Figure 13) as well as to cover the top edge portion of the Silicon Dioxide insulating layer 36 forming the via hole or opening 38 to insure against any "voids" or "opens" that could result if there was no such coverage. There are a number of significant advantages in the above described method or process which are as follows; 1. The method or process provides a simple and inexpensive process or method for achieving complete ohmic contact fill and/or via fill. 2. The use of the above noted Aluminum alloy in the combination of the metal fill reduces interconnect resistivity. 3. Since the ohmic contacts and vias are completely filled with this process, the mean time to fail because of electromigration will increase by one to two orders of magnitude as compared to the standard Aluminum alloy deposition process. 4. This low temperature metal fill process or method is thermally compatible with low k dielectrics that are unstable at elevated temperatures. The deposition rates, temperatures and metal layer thicknesses in carrying out the via hole metal filling process is similar to those noted above for the metal filling process for the ohmic contact opening. While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims: CLAIMS 1. A method of filling with metal an ohmic contact opening located within an insulating layer formed on a semiconductor substrate comprising the steps of: forming an ohmic contact to an exposed surface portion of said semiconductor substrate within an opening in said insulating layer; depositing a layer comprising a Titanium based metal on said metal ohmic contact, on side portions of said opening and on a top surface of said insulating layer; depositing a seed layer of an Aluminum based metal onto said layer of Titanium based metal partially filling said opening; and depositing an Aluminum based metal covering layer onto said seed layer of an Aluminum based metal to completely fill said opening with metal and to cover with metal top edge portions of said opening. 2. The method of Claim 1 wherein said seed layer of an Aluminum based metal is Aluminum Silicon Copper. 3. The method of Claim 1 wherein said Aluminum based metal covering layer deposited on said seed layer is Aluminum Silicon Copper. 4. The method of Claim 2 wherein said Aluminum based metal covering layer deposited on said seed layer is Aluminum Silicon Copper. 5. The method of Claim 1 wherein said layer of Titanium based metal having a thickness of about 500 Angstroms. 6. The method of Claim 1 including the step of depositing said seed layer of an Aluminum based metal at a relatively high deposition rate of about 150 Angstroms per second and at a temperature in the range of from about ambient to about 250 degrees C. 7. The method of Claim 6 wherein said seed layer of an Aluminum based metal has a final deposition thickness of about 1200 Angstroms. 8. The method of Claim 1 wherein said Aluminum based metal covering layer deposited onto said seed layer is deposited at a relatively low deposition rate of about 20 Angstroms per second at a temperature in the range of from about 240 degrees C to about 380 degrees C. 9. The method of Claim 1 wherein said ohmic contact is a Titanium Silicide contact. 10. The method of Claim 1 wherein said layer of Titanium based metal is Titanium Nitride. 11. The method of Claim 9 wherein said layer of Titanium based metal is Titanium Nitride. 12. The method of Claim 1 wherein both said seed layer and said metal covering layer deposited on said seed layer is Aluminum Silicon Copper, including the step of depositing said seed layer of an Aluminum based metal at a relatively high deposition rate of about 150 Angstroms per second and at a temperature in the range of from about ambient to about 250 degrees C, said seed layer of an Aluminum based metal has a final deposition thickness of about 1200 Angstroms, said Aluminum based metal covering layer deposited onto said seed layer is deposited at a relatively low deposition rate of about 20 Angstroms per second at a temperature in the range of from about 240 degrees C to about 380 degrees C. said ohmic contact is a Titanium Silicide contact, said layer of Titanium based metal is Titanium Nitride. 13. A method of filling with metal an ohmic contact opening located within an insulating layer formed on a semiconductor substrate comprising the steps of; forming an ohmic contact to an exposed surface portion of said semiconductor substrate within an opening in said insulating layer; depositing a reaction induced creep enhancing layer on said metal ohmic contact, on side portions of said opening and on a top surface of said insulating layer; depositing a seed layer of an Aluminum based metal onto said reaction induced creep enhancing layer partially filling said opening; and depositing an Aluminum based covering metal onto said seed layer to completely fill said opening with metal and to cover with metal top edge portions of said opening. 14. A method of filling with metal a via hole located within at least one insulating layer and above an exposed metal land portion formed above a semiconductor substrate comprising the steps of: depositing a layer of Titanium on said exposed metal land portion, on side portions of said at least one insulating layer defining said via hole and on a top surface of said at least one insulating layer; depositing a seed layer of an Aluminum based metal on the layer of Titanium partially filling said via hole; and depositing an Aluminum based metal covering layer on said seed layer of an Aluminum based metal to completely fill said via hole and to cover with metal top edge portions of said via hole. 15. The method of Claim 14 wherein said seed layer of an Aluminum based metal is Aluminum Silicon Copper. 16. The method of Claim 14 wherein said Aluminum based metal covering layer deposited on said seed layer is Aluminum Silicon Copper. 17. The method of Claim 15 wherein said Aluminum based metal covering layer deposited on said seed layer is Aluminum Silicon Copper. 18. The method of Claim 14 including the step of depositing said seed layer of an Aluminum based metal at a relatively high deposition rate of about 150 Angstroms per second and at a temperature in the range of from about ambient to about 250 degrees C. 19. The method of Claim 18 wherein said seed layer of an Aluminum based metal has a final deposition thickness of about 1200 Angstroms. 20. The method of Claim 14 wherein said Aluminum based metal covering layer deposited onto said seed layer is deposited at a relatively low deposition rate of about 20 Angstroms per second at a temperature in the range of from about 240 degrees C to about 380 degrees C. 21. The method of Claim 14 wherein both said seed layer and said metal covering layer deposited on said seed layer is Aluminum Silicon Copper, including the step of depositing said seed layer of an Aluminum based metal at a relatively high deposition rate of about 150 Angstroms per second and at a temperature in the range of from about ambient to about 250 degrees C, said seed layer of an Aluminum based metal has a final deposition thickness of about 1200 Angstroms, said Aluminum based metal covering layer deposited onto said seed layer is deposited at a relatively low deposition rate of about 20 Angstroms per second at a temperature in the range of from about 240 degrees C to about 380 degrees C. 22. A method of filling with metal both an ohmic contact opening located within an insulating layer on a semiconductor substrate and a via hole located within at least one insulating layer and above an exposed metal land portion formed above the semiconductor substrate comprising the steps of: forming an ohmic contact to an exposed surface portion of said semiconductor substrate within an opening in said insulating layer; depositing a layer comprising a Titanium based metal on said metal ohmic contact, and on side portions of said opening and on a top surface of said insulating layer; depositing a seed layer of an Aluminum based metal onto said layer of Titanium based metal partially filling said opening; depositing a first level Aluminum based metal covering layer onto said seed layer of an Aluminum based metal to completely fill said opening with metal and to cover with metal top edge portions of said opening; depositing a layer of Titanium on said exposed metal land portion, on side portions of said at least one insulating layer defining said via hole and on a top surface of said at least one insulating layer; depositing a seed layer of an Aluminum based metal on the layer of Titanium partially filling said via hole; and depositing a second level Aluminum based metal covering layer on said seed layer of an Aluminum based metal to completely fill said via hole and to cover with metal top edge portions of said via hole. 23. The method of Claim 22 wherein said seed layer of an Aluminum based metal is Aluminum Silicon Copper. 24. The method of Claim 22 wherein said second level Aluminum based metal covering layer deposited on said seed layer is Aluminum Silicon Copper. 25. The method of Claim 23 wherein said second level Aluminum based metal covering layer deposited on said seed layer is Aluminum Silicon Copper. 26. The method of Claim 22 including the step of depositing said seed layer of an Aluminum based metal at a relatively high deposition rate of about 150 Angstroms per second and at a temperature in the range of from about ambient to about 250 degrees C. 27. The method of Claim 26 wherein said seed layer of an Aluminum based metal has a final deposition thickness of about 1200 Angstroms. 28. The method of Claim 22 wherein said Aluminum based metal layer deposited onto said seed layer is deposited at a relatively low deposition rate of about 20 Angstroms per second at a temperature in the range of from about 240 degrees C to about 380 degrees C. 29. The method of Claim 28 including the step of depositing said seed layer of an Aluminum based metal at a relatively high deposition rate of about 150 Angstroms per second and at a temperature in the range of from about ambient to about 250 degrees C. 30. The method of Claim 29 wherein said seed layer of an Aluminum based metal has a final deposition thickness of about 1200 Angstroms. 31. The method of Claim 26 wherein said second level Aluminum based metal covering layer deposited onto said seed layer is deposited at a relatively low deposition rate of about 20 Angstroms per second at a temperature in the range of from about 240 degrees C to about 380 degrees C. 32. The method of Claim 22 wherein both said seed layer and said metal layer deposited on said seed layer is Aluminum Silicon Copper, the method of Claim 22 including the step of depositing said seed layer of an Aluminum based metal at a relatively high deposition rate of about 150 Angstroms per second and at a temperature in the range of from about ambient to about 250 degrees C, said seed layer of an Aluminum based metal has a final deposition thickness of about 1200 Angstroms, said second level Aluminum based metal covering layer deposited onto said seed layer is deposited at a relatively low deposition rate of about 20 Angstroms per second at a temperature in the range of from about 240 degrees C to about 380 degrees C. )_. A semiconductor structure made in accordance with the method of Claim 1. 34. A semiconductor structure made in accordance with the method of Claim 13. 35. A semiconductor structure made in accordance with the method of Claim 14. 36. A semiconductor device made in accordance with the method of Claim 22.

Inventors: EICHMAN ERIC C, LUNDY WALTER E, EICHMAN, ERIC, C., LUNDY, WALTER, E.
Applicants: MICROCHIP TECH INC, MICROCHIP TECHNOLOGY INCORPORATED
Application year: 1998
Main classification: H01L21
IPC codes: H01L21