Method for realizing on silicon an accurate active termination, active termination so obtained and voltage regulator comprising such an active termination

Abstract: The invention relates to an active precision termination (1) of the type incorporated in a voltage regulator for feeding the lines of an external bus, each termination comprising an impedance (R) of matching connected in series to a switch (M) formed by a MOS transistor, characterised by comprising a cell (2) formed by a plurality (n) of circuital branches (A 0 , .... ., An) provided in parallel and heading to a unique output terminal (OUT), each branch comprising an input (Ij) coupled to the series of the impedance and of the switch and receiving a signal (Bm) of control tension. The body terminal of each MOS transistor receives a corresponding signal (Bm) of control voltage via an inverter (Xj) whereas the control terminal of each MOS transistor receives a corresponding signal (Gm) of control voltage.

Description: Field of application The present invention relates to a method for creating an active precision termination onto semiconductor silicon and to a so obtained active precision termination. More in particular, the invention relates to a termination of the above mentioned type and comprising an matching impedance connected in series to a switch formed by a transistor MOS. The invention also relates to a voltage regulator incorporating an active termination of the above mentioned type. The present invention is the fruit of the development of a Bus Supplayer device, that is to say a voltage regulator for feeding a Bus which is portable with some standards: SCSI (Small Computer System Interface), SCSI-2, SCSI-3, as well as provided with at least nine active termination with high precision (110 Ω at 2 %), although the description hereinbelow is made with reference to this specific field of application with the only purpose of simplifying the illustration. Prior art A device of the above mentioned type essentially operates as a voltage regulator and feeds every line of the Bus via a so called active termination comprising an matching impedance with a switch associated thereto. A voltage regulator and the active termination (switch + resistance) are realised inside the integrated circuit. A regulator of known type is schematically illustrated in figure 1 attached hereto. In conditions of operation, the regulator feeds every line of the bus with an matching impedance of high precision; in alternative, if required by the CPU that manages the Bus, the regulator can set the terminations into a state of high impedance disconnecting itself from the Bus. Hence the output of the regulator is hence interfaced with the Bus by means of a switch that is usually realised with a MOS transistor connected in series to a respective resistor for every line of the Bus. A conclusive condition for the efficiency of the regulator is the precision of the matching impedance, that corresponds to the resistance "seen" by the output pin of the regulator connected to the line of the Bus in direction of the inside of the integrated circuit. R TERM = R DS_MOS + R as the termination "leans" on the output of the regulator, which represents a node at low impedance. The precision of the resistance R TERM must be further on maintained in presence of potential changes in the power supply, in temperature and also with respect to the fluctuations of the voltage of the bus line between V IN and GND. In the past, for SCSI applications, the regulators of this kind were always realised in integrated form interfacing them in any case with each one of the bus lines via resistors, and possible switches, external to the integrated circuit. Obviously this created serious problems of overall circuital dimensions, as well as higher costs and management fees of the regulator-Bus system. In figure 2 an example of a regulator realised according to this approach proposed by the prior art is shown. A further method for obtaining a resistive termination with high precision, internal to the integrated circuit incorporating the bus, is that of using a technique known as "Laser Trimming". Essentialy, during the EWS (Electrical Wafer Sort) test phase of the integrated circuit, the resistor connected in series to the MOS switch undergoes a trimming action by a laser beam in such a way to calibrate the resistive layer up to a desired value It is clear though that such a known solution needs an engineered system comprising the "Laser Trimming" and the technology for creating a device able to stand the trimming action. In figure 3 a schematic view of a resistive cell of termination is shown, which undergoes a trimming action by means of the "Laser trimming" technique. The technical problem which is at the basis of the present invention is that of devising a new method for realising a resistive precision termination on semiconductor silicon, thus obtaining a new type of resistive precision termination having structural and functional characteristics such to overcome the drawbacks highlighted with reference to the prior art and, in particular not to require the use of the laser trimming technique. Summary of the invention The solution idea at the basis of the present invention is that of foreseeing a cell formed by a plurality of circuital branches provided in parallel and heading to a unique output terminal, each branch comprising an input coupled to the series of an impedance and a switch and receving a signal of control voltage. The control of the various branches by means of the control voltages is such to allow the value of the termination resistance to pass from an initial value to a final desired value with a range of variation corresponding to steps of a trimming action. In this way it is possible to realise a precision resistor without using the laser trimming technique. Based on such resolutive idea, the technical problem is solved by a method of the type previously indicated and defined by the characterising part of the hereto attached claims 1 and following. The technical problem is also solved by a voltage regulator defined in claim 2. The features and the advantages of the method and of the circuit according to the invention will become clear from the following specification of an embodiment thereof, which is herein set as example for descriptive and non limiting purposes, with reference to the attached drawings. Brief description of the drawings. figure 1 shows a schematic view of a voltage regulator for a Bus line realised according to the prior art; figure 2 shows a schematic view of a further example of regulator of known type; figure 3 shows by means of example a schematic view of an active termination cell which underwent trimming by means of the "Laser Trimming" technique; figure 4 shows an example of embodiment of an active termination in accordance to the present invention; figure 5 shows a schematic view of a circuit generator of a plurality of voltage control signals applied to the termination of figure 4; figure 6 shows a schematic view of an example of embodiment of a lever shifter stage incorporated in the generator of figure 5; figure 7 respectively shows comparative diagrams of resistance-temperature characteristic patterns for a generic resistor and a MOS; figures 8A and 8B show on respective resistance-temperature diagrams two possible extreme cases of thermal drift of the impedance incorporated in the termination of figure 4; figure 9 shows a schematic view of a bandgap voltage regulator of known type; figure 10 shows a schematic view of a voltage regulator according to the present invention. Detailed description With reference to such drawings, and in particular to the example of figure 4, with 1 an active termination realised according to the present invention for a voltage regulator associated to a Bus of an integrated electronic circuit is in whole and schematically indicated. Both the voltage regulator and the Bus are not represented in the drawings as they have a conventional structure. For the comprehension of the invention it suffices to know that the Bus comprises a plurality of n connecting lines. The active termination according to the invention has a structure such to afford a great precision of the corresponding resistance of termination, but also a compensation in temperature. In the following we will examine in separate issues these features inherent to the invention. The termination 1 according to the invention comprises a cell formed by a plurality n of circuital branches A provided in parallel, each one being identified by means of a respective index from 0 to n. Each branch A comprises an input terminal I and the series of a transistor M of MOS type and of a resistance R. Each transistor MOS has a first and a second conduction terminal as well as a control gate. All the branches are heading into an output terminal OUT. A first branch A C comprises an input I 0 and the series of a transistor M 0 and of a resistance R 0 ; whereas a generic branch A j comprises an input I J and the series of a transistor M j and of a resistance R J . Each one of the inputs I is connected to a corresponding inverter X having its output connected to the body terminal, so called "bulk", of the transistor M of the respective branch A. Each inverter X is fed between a first voltage reference Vreg and a second reference of mass voltage GND. The first voltage reference Vreg is also applied to each first terminal of conduction of each transistor M. The gate terminals of the transistors M are kept at a predetermined value of control voltage Gm (with m varying from 0 to n). Respective voltages of value Bm (with m varying from o to n) are also applied to the various input terminals I. A proper generator circuit generates the control voltages Gm for piloting the gate terminals of the MOS transistors M and the control voltages Bm for controlling the bulk terminals of the transistors M themselves. The generation of the control voltages Gm is foreseen in such a way to take at the beginning the transistor M 0 only to the switch-on state ON, leaving in the switch-off state OFF all the other transistors; accordingly the resistance of the termination resistance is equal to R TERM_BEGIN = R DS_M0 + R 0 the Mos transistor M 0 and the resistor R 0 are dimensioned in such a way that in case of the maximum spread towards the minimum (referred to the resistive values) of the diffusion process, the following result is achieved: R TERM_BEGIN = R DS_M0_MIN + R 0_MIN = 110 Ω and therefore R TERM_BEGIN = R DS_M0_TYP + R 0_TYP ≥ 110 Ω The system needs therefore an operation of calibration during the EWS to decrease the resistance of the termination down to 110 Ω, as predetermined with the preset error margin. The Mos M 1 and the resistor R 1 are dimensioned in such a way that if M 1 in the ON state, the following result is achieved: 110 = 110.5 // (R DS_M1 + R 1 ) so that if R TERM_BEGIN = R DS_M0 + R 0 = 110,5 Ω introducing the branch M1-R1, the following equation is obtained: R TERM_FINAL = (R DS_M0 + R 0 ) // (R DS_M1 + R 1 ) = 110 Ω wherefrom it can be inferred that the insertion of the branch containing the Mos M 1 and the resistor R 1 , taking the Mos M 1 to the state ON, a variation in the resistance of the termination is determined equal to -0,5 Ω with respect to the initial value equal to 110,5 Ω, thus determining a trimming action of less significant weight (determined in this specific instance equal to -0,5 Ω on 110,5 Ω). The cell can be hence dimensioned in such a way that: the branch containing M 1 and R 1 (with M 1 in the ON state) introduces a variation of -0,5 Ω with respect to 110,5 Ω; the branch containing M 2 and R 2 (with M 2 in the ON state) introduces a variation of -1 Ω with respect to 111 Ω; the branch containing M 3 and R 3 (with M 3 in the ON state) introduces a variation of -2 Ω with respect to 112,5 Ω; the branch containing M 4 and R 4 (with M 4 in the ON state) introduces a variation of -4 Ω with respect to 114 Ω; the branch containing M 5 and R 5 (with M 5 in the ON state) introduces a variation of -8 Ω with respect to 118 Ω; the branch containing M 6 and R 6 (with M 6 in the ON state) introduces a variation of -16 Ω with respect to 116 Ω; the branch containing M 7 and R 7 (with M 7 in the ON state) introduces a variation of -32 Ω with respect to 132 Ω. Each parallel branch observes the following conditions (8) and (9) R BRANCH_m = R DS_m + R m R DS_m = α R BRANCH_m R m = β R BRANCH_m with α + β = 1 In this way the parallel trimming does not modify the pattern of the resistance of the termination in relation to temperature; in fact the ratio between R DS_m and R m is constant, a condition which cannot be true with the laser trimming technique. The introduction of the various branches Mos - Resistor allows therefore to decrease the initial value of the resistance of termination from the initial value to a desired value (110 Ω in the example take herein into consideration) with a range of maximum variation (equal to -63,5 Ω typ in the example herein taken into consideration) and with steps corresponding to a trimming action having a less significant weight (equal to 0,5 Ω typ in the example herein taken into consideration). The desired precision and the spread of the process determine the minimum step of trimming and the number n of branches Mos-Resistor necessary to complete with success the trimming action. The precision of the system is at its highest in case the process is shifted towards the maximum values, that is to say with higher resistances than the typical case; whereas it is at its lowest in case the process spread is shifted towards the minimum values, with lower resistances with respect to the typical case. The piloting of the bulk terminals is such to take those terminals to the value Vreg in case that the Mos operative condition herein taken into consideration is foreseen, whereas it is such to take those terminals to the value GND in the case the condition of high impedance of the termination is foreseen. This kind of piloting affords: maximum efficiency of the Mos in operative condition; bidirectionality of the transistor Mos in that the system is dimensioned in such a way to have R DS_m << R m ⇒ V DS << VR m so that, in any operative condition of the Bus lines, that may undergo rushes from GND to V IN , the junction P-N formed by the region Pwell_Bulk - N_Drain will not be directly polarised; a safe shut down in case it is wished that the system runs at high impedance. The generation of the control voltages Bm and Gm is demanded to a generator circuit 8 shown in figure 5. The action of trimming is carried out via a conventional network of firing incorporating zener diodes of zapping type ZAP. In figure 5 an example of embodiment of such network is schematically shown, whereby the network is indicated with 5. A decoding network 6 is connected in cascade to the zener ZAP network 5, network 6 which is necessary, considered that beside the trimming action ON-OFF controls are foreseen both from the outside of the integrated circuit (for example for a Power Down with high impedance of the terminations) and from the inside of the circuit in case of short-circuits on the output of the regulator. Furthermore, a proper network 7 of level shifter destined to shift the level of the decoding network 6, for example from 0V to the value of V IN in the voltage Vn generated by one stage 8 of thermal compensation that will be hereinbelow discussed. The network of level shifter 7 has the task of producing the final values of the voltages Gm and Bm. In figure 6 there is schematically shown a possible example of embodiment of a level shifter circuital block. Each one of the n zener zapping devices of the network 5 is pre-polarised in a high state that corresponds to a trimming branch ranging from the one least significant to the one of greatest weight. During the EWS test phase, to burn the m-th zener zapping means to change its logic state from 1 to 0 and this entails that the corresponding MOS M be taken into a state ON with a corresponding insertion in the termination of the branch Mos - Resistor. In the embodiment herein described by way of indicative and not limitative example, the cell 2 is repeated nine times, in order to be connected to a Bus with nine lines, which are all controlled by means of a unique network of firing, decoding and level shifter as that shown in figure 5. During the EWS test phase, the reading of the resistance of termination is carried out on one of the nine terminations, for example on the central one to better contain the spreads between a termination and the other. As already previously mentioned, the structure of termination according to the present invention is equipped with means of compensation in temperature. More in particular, deriving as function of temperature the equation (1), we obtain : dR TERM / dT = dR DS_MOS / dT + dR / DT with: dR DS_MOS / dT > 0 because the resistance of the MOS transistors is due to a layer of suitably doped semiconductor material, whereas the ratio dR/dT has a value linked to the structure from which the resistor is realised, once known the used ratio dR/dT for the resistor, it is necessary to pilot the gate of the Mos with respect to the temperature in such a way to obtain a drop of gate-source voltage V GS (it shall be noted that the source terminal of the Mos is at a fixed potential with respect to temperature corresponding to the output of the voltage regulator Vreg) that in temperature can control the R DS of the Mos transistor (which operates in a linear zone) in such a way to compensate the thermal drift of the resistor: dR TERM / dT = dR DS_MOS / dT + dR / dT ≅ 0 In a traditional application with the gate of the MOS transistor at a fixed potential in temperature, for example the potential of the power supply, a situation of the kind illustrated in figure 7 is obtained with a strong drift in temperature of the overall resistance. The innovative solution foreseen by the method according to the invention proposes to control the gate voltage in temperature in such a way to obtain a voltage drop V GS in temperature such as to force a value of R DS sufficient for compensating the thermal drift of the resistor connected in series to the transistor MOS, just as indicated by the relationship (13). In figures 8A and 8B a comparison is made between two resistance-temperature diagrams of two possible extreme cases of thermal drift of the resistor placed in series to the Mos. In other words, it is possible to state that the method according to the present invention permits to cause a gate-source voltage drop V GS able to sufficiently "open" the transistor Mos with the purpose of making it operate in a linear zone and with a pattern in temperature such as to determine a resistance R DS having a thermal drift that compensates that of the resistor in series to the transistor Mos. In fact, in linear zone and at other conditions being equal, from the output characteristics of the Mos we can derive: R DS = f(V GS ) Hence controlling the ratio dV GS /dT it is possible to control the ratio dR DS /dT and as V GS = V G - V S with V S coincident with the output of the regulator, and hence approximately: dVS / dT ≅ 0, from which: dV GS /dT = dV G /dT - dV S /dT ≅ dV G /dT follows. The complete system for controlling the gate voltage is schematically illustrated in figure 9 from which the presence can be detected of a regulator stage 10 of stable voltage value V BG , for example a Bandgap regulator of conventional type, having the output connected to a level shifter 11. The bandgap-type regulator stage 10 of reference generates a reference of voltage of about 1,25 V that is applied to the level shifter buffer stage 11 with the purpose of producing a flow of current necessary to the following stage. Such current is produced in output from the shifter 11 with a level voltage shift that takes it to a value V BLS . This value of voltage is multiplied by n by a multiplier stage 12 comprising an oscillator 13, a pair of inverters 14 and a charge pump 15. The output of the charge pump 15 produces a voltage Vn that feeds the cell of the Level-Shifter (block 7 of figure 5), the output of which, that may have a value of 0 or Vn, pilots the MOS gate in series with the resistor. In case the Level-Shifter takes its own output to the value Vn, we have: Vn = n V BLS V GS = Vn - Vreg dV GS /dT = n dV BLS /dT - 0 = n dV BG /dT Therefore, the thermal drift of the voltage V GS that pilots the transistor MOS that operates in a linear zone is n times greater than the thermal drift of the bandgap voltage V BG produced by the regulator stage 10. As the tipical feature of a bandgap regulator stage is that of being able to fix in advance the slope of the ramp of the voltage V BG with respect to the temperature T (that is to say to fix the slope dV BG /dT) for example acting on a varying resistor internal to the regulator stage 10, with a trimming action on such internal resistor it is possible to set the thermal drift of the stable voltage reference V BG . By level shifting such voltage, and by multiplying the shifted value by n, the voltage on the gate terminal of each MOS transistor inserted onto the branches A 0 , A n is obtained. The method and the device of termination according to the present invention resolve the technical problem and achieve a number of advantages, listed hereinbelow: the possibility of realizing precise resistors without the use of the laser trimming technique; the possibility of employing such method with any technology provided with Mos transistors; to keep constant the temperature coefficient of the termination resistance independently from the trimming action; the compensation of the thermal drift of a resistance with switch.

Claims: Method for realising an active precision termination on semiconductor silicon, each termination comprising an impedance (R) of matching connected in series to a switch (M), characterised by foreseeing: a cell formed by a plurality (n) of circuital branches (A 0 , ....., An) provided in parallel and heading to a unique output terminal (OUT), each branch comprising an input (Ij) coupled to the series of the impedance and of a switch formed by a MOS transistor (M 0 , ... M n ) and receiving a signal (Bm) of control tension; and a generator circuit (8) for generating control voltages for piloting the gate terminals of the MOS transistors and the control voltages (Bm) for controlling the bulk terminal of the transistors (M) themselves. Active precision termination (1) of the type incorporated in a voltage regulator interfaced with a bus of an integrated circuit for feeding the lines of such bus, each termination comprising an impedance (R) of matching connected in series to a switch (M), characterised by comprising a cell (2) formed by a plurality (n) of circuital branches (A 0 , ....., An) provided in parallel and heading to a unique output terminal (OUT), each branch comprising an input (Ij) coupled to the series of the impedance and of the switch and receiving a signal (Bm) of control tension. Termination according to claim 2, characterised in that the body terminal of each MOS transistor receives a corresponding control voltage signal (Bm) via an inverter (Xj). Termination according to claim 2, characterised in that the control terminal of each MOS transistor receives a corresponding signal (Gm) of control tension. Termination according to claim 3, characterised in that each amplifier (Xj) is fed between a first reference of voltage (Vreg) and a second reference of mass voltage (GND), the first reference of voltage (Vreg) being applied also to each first terminal of conduction of each transistor (M). Termination according to claim 4, characterised in that the generation of the control voltages (Bm, Gm) is foreseen in such a way to initially take to the switch-on state only the transistor of the first branch of the cell (2) leaving in the switch-off state all the other transistors. Termination according to claim 4, characterised in that a generator circuit (8) is in charge of the generation of the control voltages, which comprises: a network (5) of zener elements ZAP connected in cascade to a decoding network (6); a network (7) of level shifter destined to shift the level of the voltages coming out of the decoding network (6). Integrated voltage regulator for feeding the lines of an external bus by means of respective active terminations each of which comprising an matching impedance connected in series to a switch formed by a MOS transistor, characterised by comprising at least one active termination according to claim 1.

Inventors: GALLI GIOVANNI, GALLI, GIOVANNI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1998
Main classification: G06F13
IPC codes: G06F13