High storage capacity non-volatile memory

Abstract: A memory device comprising an array of memory cells (1), including at least one memory block (B0-B7) comprising multiple-level memory cells adapted for storing each one N ≥ 2 bits of information. The at least one memory block (B0-B7) also includes electrically erasable and programmable bilevel memory cells each one adapted for storing one bit of information, and means (2,5,3) are provided for either accessing and reading one of said multiple-level memory cell or simultaneously accessing and reading N of said electrically erasable and programmable bilevel memory cells, depending on address signals (A0-A21) supplied to the memory device.

Description: The present invention relates to non-volatile memories. More particularly, the invention concerns a high storage capacity non-volatile memory. The market demand for non-volatile semiconductor memory devices with higher and higher storage capacity is known. The manufacturers are therefore constantly coping with the task of finding solutions suitable for achieving the desired storage capacity at the same time keeping the production costs reasonable. A promising technique is that providing for storing in each single non-volatile memory cell more than just one bit of information. This technique is also known as multiple-level programming and sensing. While in conventional, bilevel non-volatile memory devices each memory cell can take only two distinct programming states, i.e., written and erased, in multiple-level devices each memory cell can take more than two programming states, for example four, corresponding to two bits of information. High capacity multiple-level Flash EEPROM memories have been presented by some manufacturers. However, such devices exhibit significant reliability problems. While on one hand multiple-level programming and sensing requires that the different programming levels of the memory cells be more precisely set than in the bilevel programming and sensing case, with a degree of precision increasing with the number of programming levels to be programmed and detected, Flash EEPROM devices are characterized by the feature of electrical erasing, and as a consequence the features of the memory cells vary during the life of the device. In view of the above, and according to the invention, a memory device is provided comprising an array of memory cells, including at least one memory block, said memory block comprising multiple-level memory cells adapted for storing each one N ≥ 2 bits of information, characterized in that said at least one memory block also includes electrically erasable and programmable bilevel memory cells each one adapted for storing one bit of information, and in that means are provided for either accessing and reading one of said multiple-level memory cell or simultaneously accessing and reading N of said electrically erasable and programmable bilevel memory cells, depending on address signals supplied to the memory device. Thanks to the present invention, a memory device is provided which has a high storage capacity, assured by the multiple-level memory cells, and at the same time can be electrically erased and programmed, although only in part. This situation is the most common one in several practical applications, wherein there is a large part of, e.g., a microprocessor program code that need not be changed, and only a smaller part of the code may be subject to changes. Thus, the large part of the code can be stored in the multiple-level memory cells, with a significant gain in chip area, and only the smaller, variable part of the code is stored in the bilevel electrically erasable and programmable cells. The latter, being conventional bilevel cells, are not affected by the problems previously outlined exhibited by multiple-level electrically erasable and programmable cells. The features of the present invention will be made apparent by the following detailed description of two particular embodiment thereof, illustrated by way of example only in the annexed drawings, wherein: Figure 1 is a schematic block diagram of a memory device according to the present invention; Figure 2 is a more detailed view of a memory block of the device shown in Figure 1, in a first embodiment of the invention; Figure 3 is a circuit diagram of a column selection arrangement for the memory block of Figure 2; Figure 4 is a circuit diagram of a sensing arrangement for the memory block of Figure 2; Figure 5 is a circuit diagram of an encoding circuit incorporated in the sensing arrangement shown in Figure 4; and Figure 6 is a detailed view of a memory block of the device shown in Figure 1, in a second embodiment of the present invention. Figure 1 shows a schematic block diagram of a memory device according to the present invention. The memory device comprises a matrix of memory cells 1; conventionally, the memory matrix 1 is a bidimensional array of memory cells (the latter are not shown, since they are conventional), that are arranged at the intersection of rows (word lines) WL and columns (bit lines) BL. The memory matrix includes eight memory blocks B0-B7. Each memory block B0-B7 is associated to two respective data output lines (O0,O1), (O2,O3)...(O14,O15) of the memory device. A row address decoding circuit 2 receives a subset A0-A11 (row address signals) of a set A0-A21 of address signals. The row address decoding circuit 2 decodes the digital code carried by the row address signals A0-A11 and consequently activates one out of 4096 word lines WL. The detailed structure of the row address decoding circuit 2 will not be described in detail, being considered well known to the skilled technicians. The memory device also conventionally comprises a column address decoding circuit 5 receiving a subset A12-A21 (column address signals) of the set of address signals AO-A21. The column address decoding circuit 5 decodes the digital code carried by the column address signals A12-A21, and generates column selection signals Y. The detailed structure of the column address decoding circuit 5 will not be described in detail, being considered well known to those skilled in the art. To each memory block B0-B7 there is associated a column selection and sensing circuitry 3. Each column selection and sensing circuitry 3 receives the column selection signals Y and accordingly selects a specific column or (as explained later) columns BL among those of the respective memory block B0-B7. Block 3 also performs a sensing of the addressed memory cells, i.e. those located at the intersection of the selected row and the selected columns, and controls the logic state of the two respective data output lines (O0,O1)...(O14,O15). As shown in greater detail in Figure 2, referring to a first embodiment of the present invention, each memory block B0-B7 comprises two memory sub-blocks BML and BF, each including a respective number of memory cells. Memory sub-block BML comprises multiple-level non-volatile memory cells, e.g. ROM cells or electrically programmable memory cells such as EPROM cells, fabricated by means of any one of the reliable, conventional processes already known and industrially used for the production of multiple-level non-volatile memories. Memory sub-block BF comprises conventional, bilevel electrically erasable and programmable Flash memory cells, fabricated by means of any one of the reliable, conventional processes already known and industrially used for the production of Flash EEPROM memories. Memory sub-block BML is not electrically erasable, and has a significantly higher storage capacity than memory sub-block BF, including electrically erasable cells. Memory sub-block BML includes for example 1008 columns BLA of multiple-level memory cells, e.g. four-level memory cells. Memory sub-block BF includes for example two groups BF1, BF2 each of sixteen columns BLB of conventional, bilevel Flash EEPROM cells. Columns BLA and BLB are fed to a column selection circuit 31, the structure of which will be described in detail later in connection with Figure 3. The column selection circuit 31 receives the column selection signals Y. Column selection circuit 31 selects one out of the 1008 columns BLA (the selected column of sub-block BML being connected to a first output line SBLA of circuit 31), or one column out of the sixteen columns BLB of each group BF1, BF2 of the Flash sub-block BF (the two selected columns of sub-block BF being connected to two further output lines SBLB1, SBLB2 of circuit 31). The output line SBLA of circuit 31 is supplied in parallel to three sense amplifiers SA1, SA2, SA3. The other two output lines SBLB1 (selected bit line of group BF1) and SBLB2 (selected bit line of group BF2) are respectively supplied to sense amplifiers SA2 and SA3. The outputs SO1, SO2, SO3 of sense amplifiers SA1, SA2, SA3 are supplied to an encoder circuit 4 controlling the logic state of the respective two output lines O0, O1. Figure 3 shows in detail the structure of the column selection circuit 31 shown in Figure 2. First of all, it is to be noted that column selection scheme provides for three levels of selection. Signals YN0-YN15, YM0-YM15 and YP0-YP3, all belonging to the column selection signals Y, respectively perform a first, a second and a third level of selection. The multiple-level cell block BLM comprises in this example 1008 columns BLA. These columns are grouped in packets of sixteen columns each; selection of one column BLA inside each of said packets is made by means of signals YN0-YN15. Three groups of sixteen column packets and one group of fifteen column packets are provided, for a total of 1008 columns BLA. Signals YM0-YM15 allow to select one column packet among the sixteen packets of each one of the first three groups; signals YM0-YM14 allow to select one column packet among the fifteen packets of the last group. Signals YP0-YP3 allow to select one among the groups of column packets. Similarly, signals YN0-YN15, in combination with signals YM15 and YP3, allow to select one out of the sixteen columns BLB of each group of sixteen columns BF1, BF2 of the Flash sub-block BF. Clearly, for each digital code carried by the column address signals A12-A21, only one of signals YN0-YN15, only one of signals YM0-YM15, and only one of signals YP0-YP3 is activated. Figure 4 shows in grater detail the structure of the sense amplifiers SA1, SA2, SA3. The first sense amplifier SA1 simply comprises a comparator C1 which is supplied directly by the selected column SBLA of sub-block BML and, conventionally, by a first reference column RBLA1 of multiple-level reference memory cells provided inside sub-block BML. The second sense amplifier SA2 comprises a comparator C2 and two switches SW1, SW2. Switch SW1 allows to supply one input of comparator C2 with either a second reference column RBLA2 of sub-block BML, or a first reference column RBLB1 of reference Flash EEPROM memory cells associated with group BF1 in sub-block BF. Switch SW2 allows to supply the other input of comparator C2 with either the selected column SBLA of sub-block BML, or the selected column SBLB1 of group BF1 in sub-block BF. The third sense amplifier SA3 comprises a comparator C3 and two switches SW3, SW4. Switch SW3 allows to supply one input of comparator C3 with either a third reference column RBLA3 of sub-block BML, or a reference column RBLB2 associated to group BF2 of sub-block BF. Switch SW4 allows to supply the other input of comparator C3 with either the selected column SBLA of sub-block BML, or the selected column SBLB2 of group BF2 in sub-block BF. Switches SW1, SW2, SW3 and SW4 are each composed of two CMOS pass gates (i.e., an N-channel MOSFET and a P-channel MOSFET connected in parallel to each other, controlled by complementary signals). The first pass gate of each one of the switches is controlled by a signal A which is activated when both signals YM15 and YP3 are activated; the second pass gate of each switch is controlled by a signal AN being the logic complement of signal A. Thus, while comparator C1 is always supplied with the selected column SBLA within block BML, and with the corresponding reference column RBLA1, comparators C2 and C3 are either supplied with column SBLA and reference columns RBLA2, RBLA3 when either one of signals YM15 or YP3 is deactivated, or they are supplied with columns SBLB1, RBLB1 and SBLB2, RBLB2, respectively, when signals YM15 and YP3 are both activated. Reference columns RBLA1, RBLA2, RBLA3 are columns of multiple-level reference memory cells programmed at different programming levels, so that the threshold of comparators C 1, C2 and C3 is different. In Figure 5 there is shown a detailed circuit diagram of the encoder block 4. The encoder 4 comprises an encoding circuit 6. Outputs SO2 and SO3 of sense amplifiers SA2 and SA3 are supplied to the encoding circuit 6 through respective first switches SW5 and SW6 and, through respective switches SW7 and SW8, are directly supplied to the respective output lines O0 and O1. All the switches comprise a CMOS pass gate; switches SW5 and SW6 are controlled by a signal MULTIEN which is activated (high logic level) when either one or both of signals YP3 and YM15 is deactivated, i.e. when the multiple-level cell block BML is accessed. Switches SW7 and SW8 are controlled by a signal MULTIDIS which is activated (high logic level) when both YP3 and YM15 are activated, i.e. when the Flash cell block BF is accessed. Output SO1 of sense amplifier SA1 is supplied to the decoding circuit 6 through a switch SW11. The encoding circuit 6 has two outputs O0' and O1'; substantially circuit 6 performs the following logic operation: O0' = SO3 O1' = (SO1 AND NOT(SO3)) OR SO2. The outputs O0' and O1' of circuit 6 are connected to the output lines O0, O1 through respective switches SW9, SW10, again formed by a CMOS pass gate, controlled by signal MULTIEN. In this way, the outputs O0', O1' of circuit 6 are connected to the output lines O0,O1 when the multiple-level cells block BML is accessed, while they are disconnected from the output lines O0,O1 when the Flash cell block BF is accessed; in the latter case, outputs SO2 and SO3 are directly supplied to the output lines O0,O1. In Figure 6 there is shown as in Figure 2 a more detailed structure of a memory block, in a second embodiment of the invention. In the first embodiment, a parallel sensing scheme for sensing the multiple-level memory cells was provided. In this embodiment instead, a serial sensing scheme is depicted. One of such sensing scheme, called "serial-dichotomic", is described in the European Patent Application No. EP-A-0724266, the relevant disclosure of which is herein incorporated by reference. For this reason, only a brief, schematic description is given in the following. Again, three sense amplifiers SA1, SA2 and SA3 are provided for. However, sensing of the selected multiple-level cells column SLBA is performed by using only one sense amplifier, namely SA1. A state machine 7 is supplied with the output of sense amplifier SA1. State machine 7 controls a reference column selection circuit 8 which, depending on the result of the sensing performed by sense amplifier SA1, selects which one of the three reference columns RBLA1, RBLA2, RBLA3 is to be supplied to sense amplifier SA1. Sense amplifiers SA2 and SA3 are used to sense in parallel the selected Flash memory cells of columns SBLB1 and SBLB2. State machine 7 already provides at its outputs a two-bit code carrying the result of the sensing. The two-bit code generated by the state machine 7 is supplied, together with the outputs of sense amplifiers SA2 and SA3, to a logic circuit 9, substantially a switch, allowing for transferring to the output lines O0, O1 either the outputs of state machine 7, or the outputs of sense amplifiers SA2, SA3. Other sensing schemes are possible, for example mixed parallel-serial schemes. In the present description reference has been made to the case of four-level memory cells, each capable of storing two bits of information. In this case, either one four-level cell is addressed, or two bilevel cells are simultaneously addressed. It is straightforward to generalize the description to cells capable of storing more than two bits of information. Supposing the multiple-level cells store N bits of information each, then either one multiple-level cell is addressed, or N bilevel cells are simultaneously addressed. In the case a parallel sensing approach is used, then 2 N -1 sense amplifiers have to be provided, of which (2 N -1)-N are supplied uniquely by the selected column of multiple-level cells, while the remaining N sense amplifiers are each one supplied with either the selected column of multiple-level memory cells or with a respective column of bilevel cells. If instead a serial sensing approach is used, then a serial sensing circuit plus N sense amplifiers supplied with respective columns of bilevel cells are necessary. Again, mixed parallel-serial sensing schemes are possible.

Claims: Memory device comprising an array of memory cells (1), including at least one memory block (B0-B7), said memory block (B0-B7) comprising multiple-level memory cells adapted for storing each one N ≥ 2 bits of information, characterized in that said at least one memory block (B0-B7) also includes electrically erasable and programmable bilevel memory cells each one adapted for storing one bit of information, and in that means (2,5,3) are provided for either accessing and reading one of said multiple-level memory cell or simultaneously accessing and reading N of said electrically erasable and programmable bilevel memory cells, depending on address signals (A0-A21) supplied to the memory device. Memory device according to claim 1, characterized in that said at least one memory block (B0-B7) comprises a first sub-block (BML) including a first number of columns (BLA) of multiple-level memory cells, a second sub-block (BF) including N groups (BF1,BF2) each made up of a second number of columns (BLB) of bilevel electrically erasable and programmable memory cells, and in that said means (2,5,3) comprises first column selection means for selecting one column (SBLA) out of said first number of columns of the first sub-block (BLM), and second column selection means for simultaneously selecting one column (SBLB1,SBLB2) out of said second number of columns of each of said N groups (BF1,BF2), the selection of either said one column of multiple-level cells (SBLA) or said N columns of bilevel electrically erasable and programmable cells being mutually exclusive and depending on the address signals (A0-A21). Memory device according to claim 2, characterized in that said means (2,5,3) comprises sensing means (SA1, SA2, SA3, 4; 8, SA1, 7, SA2, SA3, 9) supplied with either said selected column of multiple-level memory cells (SBLA) or said N selected columns of bilevel electrically erasable and programmable memory cells (SBLB1,SBLB2), said sensing means generating an N-bit output code (O0,O1). Memory device according to claim 3, characterized in that said sensing means comprises 2 N -1 sense amplifiers (SA1,SA2,SA3), (2 N -1)-N sense amplifiers (SA1) supplied with said selected column of multiple-level memory cells (SBLA), the remaining N sense amplifiers (SA2,SA3) each one supplied with either the selected column of multiple-level memory cells (SBLA) or a respective one of said N selected columns of bilevel electrically erasable and programmable memory cells (SBLB1,SBLB2), the sensing means further comprising an encoding circuit (4) supplied with outputs of said 2 N -1 sense amplifiers (SA1,SA2,SA3) and generating said N-bit output code (O0,O1). Memory device according to claim 3, characterized in that said sensing means comprises a serial sensing circuit (7,8,SA1) supplied with said selected column of multiple-level memory cells (SBLA) for performing a serial sensing of the multiple-level memory cells, and N sense amplifiers (SA2,SA3) each one supplied with a respective one of said N selected columns of bilevel electrically erasable and programmable memory cells. Memory device according to any one of the preceding claims, characterized in that said multiple-level memory cells form a larger part of said memory block (B0-B7). Memory device according to any one of the preceding claims, characterized by comprising a plurality of identical memory blocks (B0-B7).

Inventors: ROLANDI PAOLO, ROLANDI, PAOLO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1998
Main classification: G11C11
IPC codes: G11C11, G11C16