System for allowing a two word instruction to be executed in a single cycle and method therefor

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention: This invention relates generally to processors, and more specifically, to a system and method for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase addressable memory space without reducing performance. 2. Background of the Invention Presently, in some processor systems, all instructions are single word instructions. This means that a single word is used to inform the processor of each specific operation to be performed. A problem with single word instructions is that they limit the amount of addressable memory space since single word instructions only have a limited number of address bits. In order to increase the addressable memory space, some processor systems implement a paging scheme in the program memory. In a paging scheme, the program memory is divided into a plurality of pages. A bit or bits in a data file location will indicate which page in the program memory is currently being accessed. The problem with paging schemes is that in order to access data in a different page (i.e., a page different from the currently selected page), the bit or bits in the data file location need to be changed. This creates a lot of problems for the end user especially if a programmer did not properly change the data file bit(s) when required. Therefore, a need existed to provide a system for increasing the addressable memory space to be used by a processor. The system must increase the addressable memory space to be used by the processor without reducing the overall performance of the processor. The system must increase the addressable memory space without using a paging scheme and without reducing the overall performance of the processor. The system must increase the addressable memory space without reducing the overall performance of the processor by allowing multiple word instructions to be executed in a single cycle. Document WO 95/28677 describes a computer memory device and a processor arranged to address large memories in a computer system. This document discloses an addressing mechanism which permits a memory device to have fewer address pins than there are address bits required to address the corresponding memory space and wherein a full address is generated by concatenating the content of at least two address segment registers; however the decoding of the full memory address requires more than one cycle and a complex memory control. Document WO 97/32249 describes a digital signal processing system for performing arithmetic operations on data with either single or double precision. This document discloses a circuit that operates selectively in either a single precision mode in which it performs arithmetic operations on 16-bit data words or a double precision mode in which it performs arithmetic operations on 32-bit data words, and wherein two different memory location are retrieved in a single cycle, but using two different address pointers and two address generation units. None of these documents describes a system having the capability to solve the problems addressed by the invention. SUMMARY OF THE INVENTION In accordance with one embodiment of the present invention, it is an object of the present invention to provide a system for increasing the addressable memory space to be used by a processor. It is another object of the present invention to provide a system for increasing the addressable memory space to be used by the processor without reducing the overall performance of the processor. It is still another object of the present invention to provide a system that increases addressable memory space without using a paging scheme and without reducing the overall performance of the processor. It is still another object of the present invention to provide a system that increases the addressable memory space to be used by a processor without reducing the overall performance of the processor by allowing multiple word instructions to be executed in a single cycle. BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS In accordance with one embodiment of the present invention, a system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance is disclosed. The system utilizes a linearized program memory for storing instructions to be executed by the processor system. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be executed by the processor system to the linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to an output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction on the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows for a full address value of the two word instruction to be sent to the linearized program memory in a single cycle. In accordance with another embodiment of the present invention, a method is disclosed which allows for a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. The method comprises the steps of providing a linearized program memory for storing instructions to be executed by the processor system; providing a first address bus coupled to the linearized program memory for sending the addresses of the instructions to be executed by the processor system to the linearized program memory; providing a pointer coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of a current instruction in the linearized program memory to be fetched on the first address bus; and providing a second address bus having one end coupled to an output of the program memory and a second end coupled to the first address bus for placing an address of an operand of a second word of the two word instruction on the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus thereby providing a full address value of the two word instruction in a single cycle to the linearized program memory. The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawing. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a simplified functional block diagram of a system for allowing a two word instruction to be executed in a single cycle. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Figure 1, in order to eliminate a paging scheme in the program memory and further increase addressable address space in the program memory 12, all program jumps (program jumps are where paging becomes an important issue since a jump is from one location to another) are to be increased from a single word to a two word instruction. By providing two word jump instructions, the size of the program memory 12 may be increased. This is due to the fact that a two word instruction will be able to access a larger address space due to the increased size of the instruction. Thus, the two word jump instruction will allow the entire address base of the extended program memory 12 to be fully defined. In the preferred embodiment of the present invention, each word of the two word jump instruction is 16 bits in length. The first word will use eight bits to encode the "op-code" and the other eight bits to address memory locations within the program memory 12. The second word or operand requires only four bits to distinguish it as an operand and the other 12 bits can be used as an address. The problem with a two word instruction is that it will not execute as fast as a single word instruction. Since an instruction is being fetched while another instruction is being executed, a single word "jump" instruction generally takes two cycles to "flush out" the pipeline and execute. If the instruction to be executed is a single word "jump" instruction, the instruction that was fetched is no longer real (i.e., not the next instruction to be executed). A no operation (NOP) needs to be performed and the instruction to be "jumped" to needs to be fetched. The instruction that was pointed to by the "jump" may then be executed. For a two word "jump" instruction, three cycles would be required to load the two word instruction, flush out the pipeline and to execute. This would reduce the overall performance of the processor system since at least one additional cycle is required to perform a "jump" instruction. System 10 was designed for allowing a two word instruction to be loaded in a single cycle thereby allowing a processor system to increase memory space without reducing the overall performance of the processor system. The system 10 utilizes a program memory 12. The program memory 12 is used for storing instructions to be executed by a processor system. The program memory 12 is not divided into a plurality of pages. Instead, the entire address range of the program memory 12 is linearized. In the preferred embodiment of the present invention, the program memory 12 is a 1 megaword (where 1 word is equal to 16 bits) linearized program memory 12. A first address bus 14 is coupled to the linearized program memory 12. The first address bus 14 is used for sending the addresses of instructions to be fetched to the linearized program memory 12. A pointer 16 is coupled to the first address bus 14. The pointer 16 is used for storing an address location of the current instruction in the linearized program memory 14 to be fetched. The pointer 16 then places the address location of the current instruction to be fetched onto the first address bus 14 to indicate the address of the instruction in the linearized program memory 12 to be fetched. A program counter 18 is generally coupled to the pointer 16 for loading the pointer 16 with the address location of the current instruction in the linearized program memory 12 to be fetched. A second address bus 20 has a first end coupled to the output of the linearized program memory 12. The output of the linearized program memory is the value of the instruction that is being fetched. The second end of the second address bus 20 is coupled to the first address bus 14. The second address bus 20 is used for placing an address of an operand of the second word of the two word instruction (the one being fetched when the first word is being executed) on the first address bus 14 after the address of the operand of the first word of the two word instruction has been placed on the first address bus 14. Thus, the address of the second word does not have to be loaded into the program counter 18 and sent to the pointer 16. As stated above, in a normal system for a two word jump instruction, three cycles are required. However, the system 10 allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction. Thus, during the second cycle of the "jump" instruction, the actual "jump" instruction may be fetched. Thus the two word "jump" instruction is fetched and executed in two cycles (and therefore the two word "jump" instruction is executed in a single cycle) . The system 10 therefor allows one to expand the program memory without having to use any memory paging scheme. The expansion of the program memory further does not decrease the system performance since a two word "jump" instruction will take the same number of cycles as a single word "jump" instruction. The system 10 may further have a table pointer 22. The table pointer 22 is coupled to the pointer 16. The table pointer is used for allowing table reads and table writes to and from the linearized program memory 12. While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the invention as defined in the appended claims.

Claims: A system (10) for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance comprising, in combination: a linearized program memory (12) for storing instructions to be executed by said processor system; a first address bus (14) coupled to said linearized program memory (12) for sending said addresses of said instructions to be fetched to said linearized program memory (12); a pointer (16) coupled to said first address bus (14) for storing an address location of a current instruction in said linearized program memory (12) to be fetched and for placing said address location of a current instruction in said linearized program memory (12) to be fetched on said first address bus (14); and a second address bus (20) having one end coupled to an output of said program memory (12) and a second end coupled to said first address bus (14) for placing an address of an operand of a second word of said two word instruction on said first address bus (14) after an address of an operand of first word of said two word instruction has been placed on said first address bus (14) thereby providing a full address value of said two word instruction in a single cycle to said linearized program memory (12). A system for allowing a two word instruction to be executed in a single cycle in accordance with Claim 1 further comprising a program counter (18) coupled to said pointer (16) for loading said pointer (16) with said address location of a current instruction in said linearized program memory (12) to be fetched. A system for allowing a two word instruction to be executed in a single cycle in accordance with Claim 1 or 2 further comprising a table pointer (22) coupled to said pointer (16) for allowing table reads and table writes to and from said program memory (12). A system for allowing a two word instruction to be executed in a single cycle in accordance with Claim 1, 2 or 3 wherein said first word and said second word of said two word instruction are both 16 bit instructions. A system for allowing a two word instruction to be executed in a single cycle in accordance with Claim 1, 2, 3 or 4 wherein said program memory (12) is a one megaword (where one word is equal to 16 bits) program memory. A method for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance comprising, in combination: providing a linearized program memory (12) for storing instructions to be executed by said processor system; providing a first address bus (14) coupled to said linearized program memory (12) for sending said addresses of said instructions to be fetched to said linearized program memory (12); providing a pointer (16) coupled to said first address bus (14) for storing an address location of a current instruction in said linearized program memory (12) to be fetched and for placing said address location of a current instruction in said linearized program memory (12) to be fetched on said first address bus (14); and providing a second address bus (20) having one end coupled to an output of said program memory (12) and a second end coupled to said first address bus (14) for placing an address of an operand of a second word of said two word instruction on said first address bus (14) after an address of an operand of a first word of said two word instruction has been placed on said first address bus (14) thereby providing a full address value of said two word instruction in a single cycle to said linearized program memory (12). The method of Claim 6 further comprising the step of providing a program counter (18) coupled to said pointer (16) for loading said pointer (16) with said address location of a current instruction in said linearized program memory (12) to be fetched. The method of Claim 6 or 7 further comprising the step of providing a table pointer (22) coupled to said pointer (16) for allowing table reads and table writes to and from said program memory (12). The method of Claim 6, 7 or 8 wherein said first word and said second word of said two word instruction are both 16 bit instructions. The method of Claim 6, 7, 8 or 9 further comprising the step of providing a program memory which is a one megaword (where one word is equal to 16 bits) program memory.

Inventors: ALLEN STEVE, CHIAO JENNIFER, DRAKE RODNEY J, TRIECE JOSEPH W, WOJEWODA IGOR, YACH RANDY L, ALLEN, STEVE, CHIAO, JENNIFER, DRAKE, RODNEY, J., TRIECE, JOSEPH W., WOJEWODA, IGOR, YACH, RANDY L.
Applicants: MICROCHIP TECH INC, MICROCHIP TECHNOLOGY INC.
Application year: 1998
Main classification: G06F9
IPC codes: G06F9