INTERNAL CMOS REFERENCE GENERATOR AND VOLTAGE REGULATOR

Abstract: An embodiment of the present invention includes a reference generator and voltage regulator circuit (110) for deriving a reference signal having a reference voltage from a system voltage source having a system voltage level wherein the reference voltage level remains substantially unaffected by variations in the system voltage level and variations in temperature, the circuit (110) including a voltage reference sub-circuit (112), a voltage regulator sub-circuit (114), a voltage translator sub-circuit (116), a filter sub-circuit (118) and an output sub-circuit (120).

Description: SPECIFICATION INTERNAL CMOS REFERENCE GENERATOR AND VOLTAGE REGULATOR BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to circuitry used for the purpose of voltage regulation. Specifically, the present invention relates to a circuit for deriving a reference voltage signal from a system voltage source and for regulating the reference voltage signal so that it remains substantially unaffected by variations in the system voltage level, temperature of the environment, and processing related variations of circuit components. Description of the Prior Art Typically, an electronic system includes a system voltage source providing a system voltage level Vdd for its electronic sub-systems. Some electronic subsystems require voltage sources which provide particularly stable voltage levels not equal to the system voltage level Vdd. For example, solid state memory storage systems, such as flash memory components used in a portable computer, suffer in performance when the reference voltage is not maintained within predefined tolerance levels. There exists in the prior art a variety of methods and circuit devices for deriving a reference voltage signal from a system voltage source. There also exists a variety of methods and circuit devices for regulating voltage levels. Fig. 1 shows a schematic diagram of an exemplary prior art voltage regulator circuit 10. Circuit 10 comprises: a system voltage source 12; a voltage divider including a first resistor 14 having one terminal connected to voltage source 12 and an opposite terminal connected to a node 16, and a second resistor 18 having one terminal connected to ground and an opposite terminal connected to node 16; an operational amplifier (OP-Amp) 20 having a reference input 22 connected to node 16, a feedback input 24, a power input 28 connected to system voltage source 12, and an output 26; a first bipolar transistor 30 having its base 32 connected to output 26 of the OP-Amp, its collector 36 connected to ground, and having an emitter 34; a biasing resistor 38 having one terminal connected to emitter 34 and having an opposite terminal; a second bipolar transistor 40 having its base 42 connected to the opposite terminal of biasing resistor 38, its emitter 44 connected to system voltage source 12, and its collector 46 connected to a node 47; a load resistor 50 having one terminal connected to a node 48 and an opposite terminal connected to ground; and a capacitor 52 having one terminal connected to node 48 and an opposite terminal connected to ground. Circuit 10 generates an output reference voltage Vr across terminals 47 and 48. Feedback input 24 of Op-Amp 20 is connected to terminal 48. A switch 54 selectively connects terminals 47 and 48. The voltage divider is responsive to system voltage source 12 to generate a source reference voltage level Vref at node 16. Op- Amp 20 is responsive to the source reference voltage level Vref received at input 22 and the output voltage reference level Vr received at feedback input 24 to generate an output voltage level VO at its output 26 wherein voltage level VO which is proportional to the difference between the source reference voltage level Vref and the output reference voltage level VR. The output voltage level VO is increased when Vref < VR and is decreased when Vref >VR. Transistor 40 is a p-n-p type bipolar transistor and in the active mode, the collector current IC2 through transistor 40 increases as the positive bias VEB1 across the base junction of transistor 40 is decreased. When Vref = Vr, the output voltage level VO provided at output 26 of the Op-Amp is at a threshold level, transistor 40 is in the active region, and the output reference voltage level Vr across nodes 47 and 48 for example is at 3.3 volts. If the system voltage level Vdd, increases due to a power supply variation, then the output voltage reference level Vr generated at the output terminal is increased. In response, the output voltage level VO provided at output 26 of the Op-Amp increases causing a decrease in the collector current IC2 through transistor 40; and a decrease in the output voltage reference level Vr to compensate for the increase in Vdd. If the system voltage level Vdd decreases, then the output voltage reference level Vr generated at the output terminal is decreased. In response, the voltage level VO provided at output 26 of the Op- Amp decreases causing: a decrease in the voltage level VEB1 which causes: an increase in the collector current IC2 through transistor 40; and an increase in the output voltage reference level Vr. to compensate for the decrease in Vdd. The problem with this technique is that fluctuations in Vdd change Vref due to the proportionality between Vref and Vdd . This causes Vr to follow the changes in Vdd. As an example, if Vdd drops by 10%, Vref will also drop by 10%, as does Vr. In general, fluctuations in the system voltage level Vdd may result from power supply variances and other like affects. Fluctuations in the reference voltage level generated by a reference generator often arise due to variations in temperature of the environment. For example, temperature variations in the environment of an electronic system may range from 0C to 95 C. Fluctuations in the reference voltage level may also arise due to processing related variations of the circuit components of the reference generator. Reference generator circuitry implemented using complementary metal oxide semiconductor (CMOS) technology is particularly susceptible to voltage fluctuations caused by process related variations of the circuit components of the reference generator. This is partly due to the fact that N-channel and P- channel transistors are known to operate differently under varying temperatures. What is needed is a circuit for deriving a reference signal having a reference voltage from a system voltage source having a system voltage level Vdd and for regulating the reference signal such that the reference voltage level remains substantially unaffected by variations in the system voltage level Vdd and current load. What is also needed is such a circuit wherein complementary metal oxide semiconductor (CMOS) technology is used to implement the circuit. What is further needed is such a circuit wherein the voltage level of the reference signal remains substantially unaffected by variations in the behavior of components of the circuit due to processing characteristics and temperature characteristics of the components. SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit for deriving a reference signal having a reference voltage from a system voltage source having a system voltage level and for regulating the reference voltage level such that the reference voltage level remains substantially unaffected by variations in the system voltage level and variations in temperature. Briefly, a presently preferred embodiment of the present invention includes a circuit for deriving a reference signal having a reference voltage from a system voltage source having a system voltage level and for regulating the reference voltage level. The circuit includes an output sub-circuit, a reference generator sub-circuit, a regulator sub-circuit, a translator sub- circuit, and a low pass filter sub-circuit. The output sub-circuit, which is coupled to the system voltage source, is responsive to a voltage control signal, and is operative to generate the reference signal wherein the reference voltage level is less than or equal to the system voltage level. The reference generator sub-circuit is responsive to the reference signal and is operative to generate a prime voltage level which remains substantially unaffected by temperature variations and variations in the reference signal. The reference generator sub-circuit includes: a first p-channel transistor having its source coupled to receive the reference signal, its gate connected to ground, and its drain connected to a first node at which the prime voltage level is generated; a resistor having a first terminal connected to receive the reference signal and a second terminal connected to the first node; and an N-channel second transistor having its gate coupled to receive the reference signal, its drain connected to the first node, and its source connected to a second node. The reference generator sub-circuit may also include at least one trim transistor having its gate coupled to receive the reference signal, its drain connected to the first node, and its source connected to the second node, wherein the trim transistor is used to adjust the prime voltage level. The regulator sub-circuit includes a fourth transistor having its source coupled to receive the reference signal, its gate connected to the first node, and its drain connected to a third node at which the voltage control signal is generated. The regular sub-circuit also includes another transistor with its drain connected to a third node, its source to the second node and its gate to an incoming signal. The regulator sub-circuit is responsive to the reference signal and the prime voltage level and is operative to generate the voltage control signal. The translator sub-circuit is coupled to the system voltage source and functions to amplify the voltage control signal. The low pass filter sub-circuit is used for removing jitter from the voltage control signal. The output sub-circuit includes an output transistor having its gate coupled to receive the voltage control signal, its source connected to the system voltage source, and its drain connected to an output terminal at which the reference signal is provided. An advantage of the present invention is that the voltage level of the reference signal remains substantially unaffected by variations in the system voltage level Vdd of the voltage source. Another advantage is that the reference voltage level remains substantially unaffected by variations in the behavior of components of the circuit due to processing characteristics and temperature characteristics of the components. The foregoing and other objects, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiment which makes reference to the several figures of the drawing. TN THE DRAWING Fig. 1 is a schematic diagram of a prior art voltage regulator circuit implemented using bipolar junction transistors and an operation amplifier. Fig. 2 is a schematic diagram of a CMOS reference voltage generator and voltage regulator circuit according to an embodiment of the present invention. Fig. 3 is a schematic diagram of a CMOS reference voltage generator and voltage regulator circuit according to an alternative embodiment of the present invention. Fig. 4 is a schematic diagram of a CMOS reference voltage generator and voltage regulator circuit according to another alternative embodiment of the present invention. Figs. 5 and 5a are graphs illustrating output reference voltage signals provided by the circuits of Figs. 2, 3, and 4 as a function of time. Fig. 6 illustrates the use of a prior art voltage regulator circuit with a system using nonvolatile memory devices and a controller circuit. Fig. 7 shows the use of a preferred embodiment CMOS reference voltage generator and regulator in a system having a controller device and nonvolatile memory devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawing, Fig. 2 illustrates a CMOS reference generator and voltage regulator circuit 110 according to principles of the present invention. Circuit 110 includes a voltage reference generator sub-circuit 112, a voltage regulator sub-circuit 114, a voltage translator sub-circuit 116, an RC filter sub-circuit 118, an output sub-circuit 120, and a power conservation sub-circuit 121. Reference generator sub-circuit 112 includes a transistor 122 having its gate 124 connected to receive a reference signal VR, its drain 126 coupled to a node 128, and its source 130 coupled to a node 132. Sub-circuit 112 also includes a resistor 134 having a first terminal coupled to receive reference signal VR, and a second terminal coupled to node 128. Sub-circuit 112 further includes a transistor 136 having its source 138 coupled to receive reference signal VR, its gate 139 connected to ground, and its drain 140 connected to a prime reference node 142. Regulator sub-circuit 114 includes a transistor 150 having its source 152 connected to receive reference signal VR, its gate 153 connected to reference node 142, and its drain 154 connected to a node 156. Sub-circuit 114 also includes transistor 158 having its drain 160 connected to node 156, its gate 162 connected to a node 164, and its source 166 connected to node 132. Power conservation sub-circuit 121 includes a transistor 168 having its drain 169 connected to node 132, its gate 170 coupled to receive a reset signal rst, and its source 171 connected to ground. Sub-circuit 121 also includes a transistor 172 having its gate 174 connected to node 164 which is connected to gate 170 of transistor 168, its drain 176 connected to a node 178, and its source 180 connected to ground. Voltage translator sub-circuit 116 includes a transistor 182 having its source 184 connected to a system voltage source 185 which provides a system voltage level Vdd, its gate 186 connected to ground, and its drain 188 connected to a node 190. Sub-circuit 116 also includes a transistor 192 having its gate 194 connected to node 156, its drain 196 connected to node 190, and its source 198 connected to node 178. Sub-circuit 116 further includes a transistor 200 having its gate 202 connected to node 190, its drain 204 connected to a node 206, and its source 208 connected to node 178. In addition sub-circuit 116 includes a transistor 210 having its source 212 connected to system voltage source 185, its gate 214 connected to ground, and its drain 216 connected to node 206. RC filter sub-circuit 118 includes a transistor 218 having its gate 220 connected to ground, its source 222 connected to node 206, and its drain 224 connected to a node 226. Sub- circuit 218 also includes a capacitor 228 having one terminal connected to ground and an opposite terminal connected to node 226. In an embodiment, capacitor 228 is implemented as an NMOS transistor having its drain and source both coupled to ground so that capacitance is provided across the gate and body of the transistor. Output sub-circuit 120 includes a transistor 230 having its gate 232 connected to node 226, its source 234 connected to system voltage source 185, and its drain 236 connected to a node 238. In the depicted embodiment: transistors 122, 144, 158, 168, 172, 192, 200 and 228 are N- channel CMOS transistors; transistors 136, 150, 182, 210, 220, and 230 are P-channel CMOS transistors; and the system voltage level Vdd provided by system voltage source 185 is approximately equal to 5V. However, the system voltage level Vdd may be other than 5V so long as Vdd is higher than the voltage level Vr of the reference voltage signal generated by the circuit 110. Transistor 158 is selected in size to be much smaller than transistor 150 so that transistor 158 maintains node 156 at a voltage level approximately equal to 0V when transistor 150 is OFF so that node 156 does not float and thereby maintains a known voltage level. Transistor 150 is several hundred times larger than transistor 158. For example, transistor 150 may be 300/1 in size where as transistor 158 may be 1/8 in size. Because the size of transistor 158 is very small, it consumes very little current and functions like a large resistor. Capacitor 242 acts as a tank capacitor, to remove noise from the reference signal Vr generated at node 238 as further explained below. It should be noted that resistor 240 and capacitor 242 are not part of the invention. In Operation: In a power conserving mode, power conservation sub-circuit 121, which is responsive to reset signal , functions to reduce power consumption of circuit 110 when circuit 110 is not being used. The power conserving mode of sub-circuit 121 is explained following a description of the active operation of circuit 110 below. During operation of circuit 110, reset signal is at a HIGH logic state wherein its voltage level is approximately equal to the system voltage level Vdd of the system voltage source 185. During an inoperative state of circuit 110, reset signal is driven to a LOW logic state wherein its voltage level is approximately zero. When reset signal is driven HIGH, transistors 168 and 172 are turned ON and the voltages at nodes 132 and 178 are pulled down toward ground. Output sub-circuit 120 derives the reference signal Vr from the system voltage level Vdd provided at system voltage source 185. When transistor 230 of output sub-circuit 120 is turned ON by a voltage control signal received at its gate 232 as explained further below, the voltage level of the reference signal Vr provided at node 238 is equal to the system voltage level Vdd minus the voltage drop across transistor 230. Output circuit 120 is operative to modify the voltage level of the reference signal Vr in response to the voltage control signal received from an output of regulator sub-circuit 114 and is communicated via translator sub-circuit 116 and RC filter sub-circuit 118 as further explained below. The voltage level of the reference signal Vr remains substantially unaffected by variations in the behavior of components of circuit 110 caused by process related characteristics and temperature characteristics of the components and also remains substantially unaffected by variations in the system voltage level Vdd of the system voltage source 185. The variation of the system voltage level Vdd may result from factors including variations in the system power supply (not shown). Reference generator sub-circuit 112 is responsive to the reference signal Vr generated at the output terminal of output sub-circuit 120 and is operative to develop a prime reference voltage level Vr' at node 142 that remains substantially constant despite fluctuations in the reference signal Vr caused by temperature variations in the environment of circuit 110, processing related variations in the components of circuit 110, and variations in the system voltage level Vdd. For example, temperature variations in the environment of an electronic system hosting circuit 110 may range from 0C to 95C. The N-channel and P-channel transistors used to implement circuit 110 are known to operate differently under various temperature constraints. Processing related variations include variations in device characteristics due to variations in the process technology used to manufacture components of circuit 110. Transistor 136 of reference generator sub-circuit 112 is always ON because it is a P-channel transistor and because its gate 139 is connected to ground. Transistors 122 and 144 of sub- circuit 112 are turned ON when node 132 is pulled down toward ground as transistor 168 of sub- circuit 121 is turned ON as described above. The coupling of resistor 134 and transistors 122, 136, and 144 causes the voltage level of the reference signal Vr to be divided. For example, if the reference voltage level Vr is at 3.3V, the voltage level at reference node 142 is 2V. Transistor 122 is a small trim transistor and is used to lower the voltage level of the reference signal Vr if so desired. Transistor 122 may be alternatively eliminated from the sub-circuit 122 without departing from the spirit of the present invention. In accordance with principles of the present invention, the resistor value Rl of resistor 134 and the sizes of transistors 136 and 144 are chosen so as to maintain the voltage level Vr' at node 142 substantially constant despite fluctuations in the voltage level of the reference signal Vr, variations in temperature, and variations in process related characteristics of the elements of circuit 110. Also, the characteristics of the components of circuit 110 are taken into account in determining appropriate resistance values and transistor sizes for resistor 134 and transistors 122, 136, and 144 so as to minimize the effects of the temperature and process variations on the voltage level Vr' at node 142. The temperature and process variations are compensated by proper design of resistor 134 and transistors 136 and 144. Because these elements have different temperature characteristics, a compensation is possible. As the temperature rises, the Vt of the transistor 150 drops. In the case where the voltage at node 142 remains constant, transistor 150 turns on, causing the reference voltage Vr to drop. To keep Vr constant while temperature rises, the prime reference voltage Vr' at node 142 rises to compensate for a drop in the Vt of transistor 150. The current through the p-channel of transistor 136 and n-channel of transistor 124 drop as temperature rises, but the rate of drop depends on the size of the transistors. With respect to the resistor Rl, current therethrough increases with higher temperatures. The voltage at node 142 does not change if the sizes of transistors 136 and 124, and the size of the resistor Rl vary proportionally, but the rate of current change with temperature for these different elements would vary. By proportionally changing the sizes of transistors 136 and 124 and resistor Rl, a set of sizes may be ascertained such that at room temperature, the required Vr' is maintained and also the current node 142 is varied with temperature in such a way that the rise in the Vr' compensates for the fall in Vt of the p-channel transistor 150. When the fabrication process changes slightly, the reference voltage Vr has to stay relatively constant. As an example, if the process goes toward a fast corner where the length of the gates of transistors become narrower thereby causing the transistor currents to increase and the triggering voltage thresholds of the transistors to drop, the reference voltage Vr should not change. When the fabrication process causes transistors to operate faster, the Vt of transistor 150 drops and with the same value for Vr' on node 142, this causes the voltage at node 156 to increase thereby causing the voltage at node 190 to decrease, and the voltages at nodes 206 and 232 to increase. Thereafter, transistor 230 is turned off causing Vr to drop further. To compensate for this voltage drop, the voltage at node 142 has to rise. The gate length of transistor 136 is chosen to be minimum, while the gate length for transistor 124 is chosen to be 405 times wider than minimum. This makes transistor 136 more sensitive to poly gate size variations than transistor 124. Therefore, when poly gates narrow, the current through the transistor 136 rises with faster pace than that of transistor 124, causing the voltage at node 142 to rise. This compensates for the drop in the Vt (and increase in current) of transistor 150. When the fabrication process moves toward slower corners, the opposite of the above occurs and Vr does not change. That is, the transistor currents decrease and the triggering voltage thresholds of the transistors increase causing the reference voltage Vr not to change. In an embodiment, the resistance value Rl of resistor 134 is 4K Ohms and the sizes of the transistors 122 and 136 are 20/4 and 13/0.7, respectively. In this embodiment, where the system voltage level Vdd of the system voltage source 185 changes from 5V to 4.5V, the prime reference voltage level Vr' at reference node 142 fluctuates only by 0.02-0.05 volts. The sub- circuits 114 and 120 prevent the voltage at node 142 from fluctuating as a result of variations in Vdd. Regulator sub-circuit 114 is responsive to the reference signal Vr and the prime voltage level Vr' generated at reference node 142 and is operative to generate a voltage control signal which is provided to gate 232 of transistor 230 of the output sub-circuit 120 via translator sub-circuit 116 and RC filter sub-circuit 118. Regulator sub-circuit 114 develops a voltage at node 156 in response to the prime reference voltage level Vr' at node 142 and the reference voltage level of the reference signal Vr. Transistor 150 of sub-circuit 114 is turned ON when the voltage level of the reference signal Vr provided at its source 152 increases to a level that is greater than the voltage level Vr' at reference node 142 which is provided at gate 153 of transistor 150 by one Vt. If, for example, the system voltage level Vdd were to swing from 4.5V to 5.5V, the voltage level of the reference signal Vr increases thereby increasing the potential at source 152 of transistor 150 and reduces the voltage Vr' due to the increase in conduction of transistor 122. This reduces the voltage Vr' due to the increase in the conductor of the transistor 122 such that the drive of transistor 150 increases. When transistor 150 turns ON, the voltage level at node 156 rises very quickly because transistor 150 is much larger than transistor 158. As transistor 150 operates in an active mode, the drive of transistor 150 is controlled by the gate-source bias of transistor 150. When the drive of transistor 150 increases, the voltage level at node 156 is increased toward a maximum value which is equal to the voltage level of the reference signal Vr minus the voltage drop across transistor 150. Accordingly, the voltage level at node 156 is adjusted by the drive of transistor 150 which is a function of the prime reference voltage level Vr' generated at node 142 and the output voltage level of the reference signal Vr. Sub-circuit 114 may be said to provide a voltage control signal at node 156 which is provided to gate 232 of transistor 230 of the output sub- circuit 120 via translator sub-circuit 116 and RC filter sub-circuit 118. Voltage translator sub-circuit 116 operates to translate the voltage control signal generated at node 156 such that it draws from the system voltage source 185 instead of the voltage level of the reference signal Vr. Since the transistor 230 receives its voltage source from Vdd 185, the gate of transistor 230 at node 232 has to operate from the same power supply, otherwise, the transistor 230 can not be turned 'on' and 'off. This is the reason for having the translator sub- circuit 116. Transistor 182 of sub-circuit 116 is always ON because it is a P-channel transistor and its gate 186 is connected to ground. The drive of transistor 192 of sub-circuit 116 is increased when the voltage level at node 156 is increased as described above. When the drive of transistor 192 is increased, the voltage level at node 190 is decreased, or pulled down toward ground. The voltage level at node 190 tracks the voltage level at node 156 except that the voltage level at node 190 is an inverted version of the voltage level at node 156. That is, when the voltage level at node 156 increases, the voltage level at node 190 decreases. As discussed above, the voltage level at node 156 ranges between 0V and the voltage level of the reference signal Vr while the voltage level at node 190 ranges between zero and the system voltage level Vdd. Similarly, the voltage level generated at node 206 tracks the voltage level at node 190 except that the voltage at node 206 is an inverted version of the voltage level at node 190. Transistor 210 is always ON and acts like a resistor driving the voltage level at node 206 to equal the system voltage level Vdd minus the voltage drop across transistor 210. When the voltage level at node 190 is increased the drive of transistor 200 is increased and the voltage level at node 206 is pulled down toward ground. When the drive of transistor 192 is increased, the voltage level at node 190 is pulled down toward ground and as a result, the drive of transistor 200 decreases and the voltage level at node 206 is pulled up toward the voltage level Vdd. Therefore, the voltage level at node 206 ranges between a first voltage level which is approximately equal to 0V and a second voltage level equal to the system voltage level Vdd . The signal generated at node 206 is a translated version of the voltage control signal generated at node 156 with the difference that node 156 swings from 0 to Vr while node 206 swings from 0 to Vdd. When the voltage at node 206 is increased, the drive of transistor 230 of output sub-circuit 120 decreases. The voltage control signal generated by the voltage regulator circuit 114 at node 156 oscillates because as the system voltage level Vdd of the system voltage source 185 begins to increase, transistor 150 turns ON momentarily and turns OFF again to maintain the voltage level of the reference signal Vr constant. Then, as the voltage level of the reference signal Vr continues to increase, transistor 150 continues to turn ON and OFF resulting in an oscillation of the voltage control signal at node 156. This oscillation similarly affects nodes 190 and 206, and ultimately undesirably affects the voltage level of the reference signal Vr. RC filter sub-circuit 118 operates as a low pass filter to prevent high frequency components of the translated voltage control signal generated at node 206 from passing through to node 226 while passing lower frequency components of the signal. Transistor 218 of sub-circuit 118 is always ON because it is a P-channel CMOS transistor having its gate 220 connected to ground and therefore acts as a resistor. Transistor 218 is very small in size and is designed with capacitor 228 to form an RC circuit. Output sub-circuit 120 is operative to modify the voltage Vr of the reference signal in response to the voltage control signal generated by the regulator sub-circuit 114 which is provided via translator sub-circuit 116 and RC filter sub-circuit 118 to gate 232 of transistor 230. When the regulator circuit 114 detects an increase in the voltage level of the reference signal Vr at source 152, the drive of transistor 150 increases and the voltage level of the voltage control signal provided at gate 232 of transistor 230 increases to decrease the drive of transistor 230 in order compensate for the increase in the voltage level of the reference signal Vr. When the regulator circuit 114 detects a decrease in the voltage level of the reference signal Vr at source 152, the drive of transistor 150 decreases and the voltage level of the voltage control signal provided at gate 232 of transistor 230 decreases to increase the drive of transistor 230 in order compensate for the decrease in the voltage level of the reference signal Vr. For example, if the system voltage level Vdd of the system voltage source 185 swings from 4.5V to 5.5V, the voltage level of the reference signal Vr generated at node 238 will increase because the output voltage level of the reference signal Vr is equal to the system voltage level Vdd minus the voltage drop across transistor 230. As described above, such an increase in the voltage level of the reference signal Vr results in circuit behavior effects including: (1) the drive of transistor 150 increasing; (2) the voltage level at node 156 being pulled up toward the voltage level of the reference signal Vr thereby increasing the voltage level of the voltage control signal; (3) the drive of transistor 192 increasing; (4) the voltage level at node 190 being pulled down toward ground; (5) the drive of transistor 200 decreasing; (6) the voltage level at node 206 being pulled up toward Vdd; and (7) the drive of transistor 230 decreasing due to a decrease in the bias across the source and gate of transistor 230 thereby preventing the voltage level of the reference signal Vr from increasing any further. In summary, as the system voltage level Vdd increases, the voltage level of the reference signal Vr also increases, but at a much slower rate. The circuit 110 also compensates for an increasing load current drawn from output node 238. When the load current increases, the voltage level of the reference signal Vr tends to decrease causing transistor 150 to turn OFF. This causes nodes 156 and 206 to drop thus lowering the voltage at the gate 232 of transistor 230 thereby increasing the drive of transistor 230 to prevent the output voltage level of the reference signal Vr from decreasing further. As mentioned above, the power conserving mode of power conservation sub-circuit 121 allows reduction of power consumption when circuit 110 is not being used. When reset signal is LOW, transistors 168 and 172 of power conservation sub-circuit 121 are turned OFF and no current flows at nodes 132 and 178. Node 156 is therefore pulled up to a voltage level approximately equal to Vr. The voltage level at node 206 is pulled up to a voltage level which is approximately equal to Vdd. Therefore, the voltage at node 226 is increased to Vdd and transistor 230 is turned OFF. Total current consumption of the regulator goes to zero. Fig. 3 is a schematic diagram of a reference generator and voltage regulator circuit according to an alternative embodiment of the present invention. The depicted circuit includes the elements of circuit 110 (Fig. 1) and in addition includes a transistor 250 and a transistor 260. Transistor 250 is connected in parallel to transistor 122 and has its gate 252 connected to receive a first auxiliary reference signal Vrl, its drain 254 connected to node 142, and its source 256 connected to node 132. Similarly, a transistor 260 is connected in parallel to both transistor 122 and transistor 250 and has its gate 262 connected to receive a second auxiliary reference signal Vr2, its drain 264 connected to node 142, and its source 266 connected to node 132. Auxiliary reference signals Vrl and Vr2 provide auxiliary reference voltages that may be used in addition to the reference signal Vr to create a trimming effect in fine tuning the voltage level of the reference signal Vr generated by circuit 110. Each transistor 122, 250, and 260 that is turned ON creates a drop in the prime reference voltage level Vr' at node 142 and consequently affects the voltage level of the reference signal Vr. For example, if only transistor 122 is turned ON, the voltage level Vr' at node 142 becomes 2.0V thereby causing the reference signal Vr to drop from 3.3 to 3.1V. If the transistor 250 is additionally turned ON, the voltage level at reference node 142 becomes 1.9V thereby further reducing the voltage of the reference signal Vr to less than 3.1V and so on. Additional transistors may be similarly coupled in parallel with transistor 122 and coupled to receive additional auxiliary reference voltages to control and obtain a desired voltage level of the reference signal Vr. Optionally, the auxiliary reference signals Vrl and Vr2 supplied to the gate terminals of transistors 122, 250, and 260 may be software-controlled so that digital values representing voltage levels associated with the reference signal Vr are stored in registers (not shown) and as the values stored in the registers are changed by software, different voltage levels of the reference signal Vr are produced. Fig. 4 illustrates another alternative embodiment of the circuit 110 (Fig. 1) wherein an N- channel dampening transistor 270 has its gate 272 to system voltage source 185, its drain 274 connected to reference node 142, and at its source 276 to node 132. The size of dampening transistor 270 is chosen to be small and it remains ON during the operation of the circuit 110. In an embodiment, the size of dampening transistor 270 is 2/10. The effect of adding dampening transistor 270 to circuit 110 is explained below in reference to Fig. 5. Fig. 5 illustrates a graph 300 of voltage 302 as a function of time 304. This graph is shown to illustrate the operation of circuit 110 (Fig. 2) to better illustrate the regulation of the voltage level of the reference signal Vr in response to fluctuations in the system voltage level Vdd of system voltage source 185 (Fig. 2). A slope 306 shows the rate of change of the system voltage level Vdd as a function of time and a slope 308 represents the rate of change of the reference signal Vr as a function of time. As depicted, the reference signal Vr tracks the system voltage level Vdd fairly consistently up to a point 310 at which the voltage level Vr is 2.9V. Up to the voltage level 2.9, at point 310, the regulator sub-circuit 114 of circuit 110 is effectively not regulating and the voltage level of the reference signal Vr substantially tracks the system voltage level Vdd. After the time associated with 310 in Fig. 3, however, as the system voltage level Vdd changes, the reference signal Vr remains fairly constant. For example, as the system voltage level Vdd changes from 3V to 5.5V in approximately 220 microseconds, the voltage level of the reference signal Vr changes from 2.9V to approximately 3.4V, which is a change of 0.5V as opposed to the 2.5V swing experienced by the system voltage level Vdd of the system voltage source 185. Therefore, regulation of the reference signal begins only after the voltage level of the reference signal Vr reaches 2.9V and thereafter the reference signal Vr is maintained fairly constant despite significant increase in the system voltage level Vdd. In Fig. 5, the variation of Vdd from 3V to 5.5V causes a variation of 2.9 to 3.4V on the reference voltage Vr. The transistor 270 (in Fig. 4) is designed to reduce this variation on Vr to even lower values. Since the gate of the transistor 270 is connected to Vdd, at higher values of Vdd (e.g. 5.5V), more current goes through the transistor 270 causing the voltage at node 142 to decrease at higher Vdd values. This lower voltage at node 142(at higher Vdd values) reduces Vr. With proper sizing of transistor 270, the reference voltage Vr would stay the same (e.g. 3.3V) as Vdd varies from 3V to 5.5V. A very large size of transistor 270 could cause Vr to be lower at Vdd = 5.5V than 3V. The data shown by the graph of Fig. 5 was assuming that the circuit 110 is driving a load drawing 50mA. That is, the value of the resistance of Rl 240 is 66 Ohms. Fig. 5a shows the same kind of information as that of Fig. 5 but using a load of 6600 Ohms drawing 0.5mA. As shown at 320, Vr tracks Vdd even more closely at a time when the regulator sub-circuit is not regulating. Fig. 6 shows an application of a prior art voltage generator and regulator circuit. This application in particular is a solid state (or non-volatile) storage system 324, which includes a controller semiconductor device 310, a voltage regulator and generator circuit 312 and a flash memory unit 322. The controller 310 controls the operation of the flash memory unit 322. In so doing, the controller 310 supplies a Vr signal (generally at 3.3V) to the flash unit 322 through the use of the regulator circuit 312. The latter is similar in operation to the prior art circuit shown in Fig. 1 herein. In Fig. 6, the regulator circuit 312 is shown to reside, in part, within the controller and in part, outside of the controller 310. Specifically, a bipolar transistor device 314, a resistor 316, a bipolar transistor device 318 and a capacitor are shown included in the regulator circuit 312 but residing outside of the controller 310. These components occupy space on, for example, a card upon which the system 312 may be placed. Fig. 7 on the other hand, shows the same application as that of Fig. 6 but using a CMOS voltage generator and regulator 110 embodiment of the present invention. That is, the solid state storage system 350 includes a controller semiconductor device 352, which employs the regulator 110 to develop a reference voltage, Vr, for use by the flash memory unit 322. The flash memory unit 322 includes a plurality of flash memory chips 326, 328, . . ., 330, which act as the resistive load, RL, shown in Fig. 2. The regulator 110 resides entirely within the controller 352 and is responsive to Vdd, generating Vr therefrom for use by the flash memory unit 322. In comparing Figs. 6 and 7, it is clear that the system of 350 of Fig. 7 requires less components. That is, the transistors 314 and 318, the resistor 316 and the capacitor 320 of the system in Fig. 6 are eliminated from the system of Fig. 7. This results in less cost for manufacturing a system using the present invention. In addition, with the elimination of the components enumerated above, it is easier to electrically design a card, which additionally reduces the costs of manufacturing. Furthermore, as noted earlier, a more dynamic Vdd range is tolerated by the system of Fig. 7 while maintaining the reference voltage, Vr, supplied to the flash unit 322 substantially constant. This dynamic tolerance further allows a system using the present invention to use batteries, generating Vdd , for a longer period of time because as batteries are used, with time, the voltage they generate is decreased in level and regulators of the prior art could not tolerate a voltage level lower than generally 4.5V. The present invention, on the other hand, allows use of the batteries even when the voltage they generate falls below 4.5 V. This tends to lengthen the lifetime use of batteries. Although the present invention has been particularly shown and described above with reference to a specific embodiment, it is anticipated that alterations and modifications thereof will no doubt become apparent to those skilled in the art. It is therefore intended that the following claims be interpreted as covering all such alterations and modifications as fall within the true spirit and scope of the invention. What I claim is:

Claims: CLAIMS 1. A circuit for deriving a reference signal having a reference voltage level from a system voltage source having a system voltage level and for regulating said reference voltage level, said circuit comprising: a reference generator circuit responsive to said reference signal and operative to generate a prime reference signal having a prime reference voltage level which remains substantially unaffected by variations in said reference voltage level and by variations in temperature; a regulator circuit responsive to said prime reference signal and said reference signal and operative to generate a voltage control signal; and a translator circuit responsive to said voltage control signal and coupled to said system voltage source and operative to generate said reference voltage, said translator circuit for amplifying said voltage control signal, wherein said reference voltage of said reference signal is substantially unaffected by variations in said system voltage level and by temperature and process variations. 2. A circuit for deriving a reference signal as recited in claim 1 further comprising an output circuit coupled to said system voltage source and to said translator circuit and operative to develop said reference signal. 3. A circuit for deriving a reference signal as recited in claim 2 wherein said output circuit further comprises a low pass filter means for reducing jitter affects on said voltage control signal. 4. A circuit for deriving a reference signal as recited in claim 1 wherein said output circuit means comprises: an output transistor having its gate coupled to receive said voltage control signal, its source coupled to said system voltage source, and its drain coupled to an output terminal at which said reference signal is provided. 5. A circuit for deriving a reference signal as recited in claim 1 wherein said reference generator circuit further includes a first transistor having a gate terminal coupled to said reference signal, a drain terminal coupled to receive said reference signal and a source terminal coupled to said regulator circuit at a prime reference node at which said prime reference voltage is generated, said first transistor for maintaining said reference voltage level substantially constant despite variations in said system voltage level wherein the current passing through said first transistor decreases when system voltage level decreases thereby causing said prime voltage reference level and said reference voltage level to increase. 6. A circuit for deriving a reference signal as recited in claim 5 wherein said reference generator circuit further includes a second transistor having a gate terminal coupled to a ground terminal, a source terminal coupled to receive said reference signal and a drain terminal coupled to said prime reference node. 7. A circuit for deriving a reference signal as recited in claim 6 wherein said reference generator circuit further includes a resistor having a first terminal connected to receive said reference signal and a second terminal connected to said prime reference node. 8. A circuit for deriving a reference signal as recited in claim 7 wherein said first transistor is an NMOS transistor having a size of 40/4 and said second transistor is a PMOS transistor having a size of 27/0.55. 9. A circuit for deriving a reference signal as recited in claim 7 further comprising at least one auxiliary trim transistor having a gate terminal coupled to receive an auxiliary reference signal, a drain terminal coupled to said prime reference node, and a source terminal coupled to said source terminal of said first transistor at a second node, said auxiliary trim transistor for adjusting said prime voltage level. 10. A circuit for deriving a reference signal as recited in claim 9 wherein said auxiliary reference signal is software-controlled. 11. A circuit for deriving a reference signal as recited in claim 1 wherein said reference voltage level changes substantially within the range of 3V and 3.5V when said source voltage level changes from 3.5V to 5.5. 12. A circuit for deriving a reference signal as recited in claim 1 for use with a load circuit coupled to receive said reference signal for drawing current between 0 to 60 mA, wherein for such current variations, said reference voltage level varies less than 0.1V. 13. A circuit for deriving a reference signal as recited in claim 7 wherein said second node is connected to a source of a first power conserving transistor. 14. A circuit for deriving a reference signal as recited in claim 1 whereupon temperature variations of 0 to 90 degrees centigrade, said reference voltage level varies no more than 0.1V. 15. A circuit for deriving a reference signal as recited in claim 7 wherein said regulator circuit means comprises a third transistor having its source coupled to receive said reference signal, its gate connected to said prime reference node, and its drain connected to a third node at which said voltage control signal is generated. 16. A circuit for deriving a reference signal as recited in claim 15 wherein said regulator circuit means further comprises a fourth transistor having its source connected to said third node, its gate connected to said system voltage source, and its drain connected to said second node. 17. A circuit for deriving a reference signal as recited in claim 15 wherein said translator sub-circuit comprises: a fifth transistor having its source connected to said system voltage source, its gate connected to ground, and its drain connected to a fourth node; a sixth transistor having its gate connected to said third node, its drain connected to said fourth node, and its source connected to a fifth node; an seventh transistor having its source connected to said system voltage source, its gate connected to ground, and its drain connected to a sixth node; and a eighth transistor having its gate connected to said fourth node, its drain connected to said sixth node, and its source connected to said fifth node. 18. A circuit for deriving a reference signal as recited in claim 17 wherein said fifth node is maintained at a potential approximately equal to a ground potential level. 19. A circuit for deriving a reference signal as recited in claim 17 wherein said fifth node is connected to a drain of a second power conserving transistor. 20. A circuit for deriving a reference signal as recited in claim 17 further comprising a power conservation sub-circuit including: a first power conserve transistor having its drain connected to said second node, its gate coupled to receive a reset signal, and its source connected to ground; and a second power conserve transistor having its gate coupled to receive said reset signal, its drain connected to said fifth node, and its source connected to ground. 21. A circuit for deriving a reference signal as recited in claim 3 wherein said low pass filter means comprises : a transistor having its gate connected to ground, its source connected to said sixth node, and its drain connected to a seventh node; and a capacitor having one terminal connected to ground and an opposite terminal connected to said seventh node. 22. A circuit for deriving a reference signal as recited in claim 15 wherein said second transistor including an N-well region coupled to said source voltage source for causing said third transistor to an 'on' state and said prime reference voltage level to decrease when said source voltage level increases. 23. A circuit for deriving a reference signal as recited in claim 15 wherein said third transistor including an N-well region coupled to said source voltage source for causing said third transistor to turn 'off and said prime reference voltage level to increase when said source voltage level increases. 24. A circuit for deriving a reference signal as recited in claim 7 further comprising a dampening transistor having a gate terminal coupled to said system voltage source, a drain terminal coupled to said prime reference node, and a source terminal coupled to said second node, said dampening transistor for causing the rate of change of said reference voltage level to be substantially less than the rate of change of said system voltage level.

Inventors: KESHTBOD PARVIZ, KESHTBOD, PARVIZ
Applicants: KESHTBOD PARVIZ, LEXAR MEDIA INC, KESHTBOD, PARVIZ, LEXAR MEDIA, INC.
Application year: 1998
Main classification: G05F1
IPC codes: G05F1, G05F3, G11C16