Clock driver apparatus with programmable output characteristics

Abstract: A programmable clock driver circuit (100) and a clock tree (5) incorporating such a clock driver circuit. The clock driver circuit preferably includes a plurality of selectable semiconductor resistive elements (112,113,122,123,132,133) such as MOS transistors. By selecting various resistive elements, a clock signal propagated through the clock driver circuit can be programmed to have transitions that are based at least in part on a time constant created by the selected resistance and the capacitance of the load that the clock driver circuit is driving.

Description: FIELD OF THE INVENTION The present invention relates to clock drivers and clock trees and, more specifically, to providing clock drivers and clock trees with programmable output characteristics. BACKGROUND OF THE INVENTION In application specific integrated circuits (ASICs) and in other integrated circuits a clock signal may be distributed to thousands and perhaps tens of thousands of "locations." This distribution is conventionally achieved using clock trees and a typical clock tree consists of a plurality of buffer drivers arranged in stages with each stage having more outputs than inputs. If a representative clock tree provides a 1:10 input to output ratio at each stage and has four stages, then the number of clock signal lines increases from 1 to 10, 10 to 100, 100 to 1,000 and 1,000 to 10,000 at stages 1-4, respectively. This staged increase in the number of signal lines provides a like increase in the number of simultaneous or nearly simultaneous clock signal transitions (e.g., from positive to negative and vice versa). Since clock signal transitions are a source of electromagnetic interference (EMI), large numbers of simultaneous clock signal transitions produce an undesirably large amount of EMI. This problem is further exacerbated as semiconductor technologies advance. Reduction in integrated circuit feature size increases the density of clock signal transitions per unit area. Furthermore, faster operating speeds tend to increase a circuit's sensitivity to EMI and other parasitics. Patent Abstracts of Japan, Vol. 017, No. 359 (E-1395) & JP 05 055891 A, Patent Abstracts of Japan, Vol. 015, No. 315 (E-1099) & JP 03 117020 A and US 5 220 216 A each describe a single circuit comprising a plurality of pairs of transistors which are selectively enabled by logic signals so as to control the level of an output of the circuit. Patent Abstracts of Japan, Vol. 017, No. 137 (E-1335) & JP 04 306 917 A describes a distributor provided with a plurality of clock drivers in a clock tree. The clock signals are combined in a logic gate, the output of which is supplied to a synchronising circuit. It would be desirable: (a) to provide a clock signal driver that permits selection of the shape of the output clock signal; (b) to provide a clock signal driver wherein the amount of signal modification is programmable; and (c) to provide a clock driver with selectable resistive values so that when those values are combined with load capacitance values, a selectable time constant is effectively achieved. SUMMARY OF THE INVENTION In accordance with the present invention there is provided a clock signal driving apparatus as defined in claim 1. The resistive device may be configured as a MOS transistor and the modification logic selected so as to enable or disable the MOS transistor. The attainment of the foregoing and related advantages and features of the invention should be more readily apparent to those skilled in the art, after review of the following more detailed description of the invention taken together with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a clock tree in accordance with the present invention. Fig. 2 is a schematic block diagram of a clock signal driver circuit in accordance with the present invention. Fig. 3 is a schematic block diagram of selection logic 231 for use in circuit 100 of Fig. 2 in accordance with the present invention. DETAILED DESCRIPTION Referring to Fig. 1, a schematic block diagram of a clock tree in accordance with the present invention is shown. The embodiment of Fig. 1 illustrates a representative clock tree having four stages, though it should be recognized that the clock tree may have more or less stages without departing from the present invention. Clock tree 5 includes a clock source 8 which is conventionally a crystal oscillator or the like. A clock signal output from source 8 is propagated over line 9 to a first stage (10) buffer driver 11 (hereinafter referred to as a "driver"). The output of driver 11 is delivered to a plurality of second stage (20) drivers, four of which are shown (21-24). While four are shown, it should be recognized that this number can be as large or as small as permitted by known fanout or load determining factors such as impedance, conductor length, etc. The outputs of the second stage drivers are in turn coupled to the input of third stage (30) drivers 31-36 and the third stage drivers are similarly coupled to fourth stage (40) drivers 41-46. In the illustrated embodiment, clock signals output from the fourth stage are delivered to their destination (functional logic) that is indicated by loads 51-56. It should be recognized that the number of stages and the number of drivers within each stage is dependent upon the number of locations to which the clock signal need be delivered and the fanout ability of each driver, etc., as is generally known. In accordance with the present invention, some or all of the drivers (11, 21-24, 31-36, 41-46) are configured such that they permit programmable shaping of their output clock signal. The drivers may be controlled individually, in sets (e.g., drivers 31-33, 34-36, 41-43 and 44-46 may each be considered a "set" of drivers), in stages or as otherwise desired by a circuit designer. It should be recognized that the provision of programmable clock signal shaping may be more critical in the latter stages of the clock tree (such as the third and fourth stages of Fig. 1) because the number of nearly simultaneous clock signal transitions is increased at these stages. It should also be recognized that staggering the timing or shape of the clock signals output from the second stage drivers 21-24 creates staggered clock signal transitions throughout clock tree 10. The ability to program output clock signals is a function of the design of the drivers (as discussed in more detail below with reference to Fig. 2) and the delivery of appropriate control signals. While control signals may be delivered in many known manners (including tying inputs to a particular logic state, etc.), in a preferred embodiment, select lines 60 are provided that propagate signals from control logic 70. Control logic 70 preferably includes one or more data registers and a processor that writes control/select bits to the data registers. The data registers hold the value of a clock driver selection signal as discussed below. Referring to Fig. 2, a schematic block diagram of a clock signal driver circuit 100 in accordance with the present invention is shown. Each of the drivers 11, 21-24, 31-36, and 41-46 may be configured to include driver circuit 100. It is not necessary to configure driver 11 with programmable output characteristics if it is the only first stage buffer from source 8. It is preferred, however, that the other drivers or sets or subsets thereof are configured to provide programmable output characteristics. Fig. 2 illustrates that driver circuit 100 has a plurality of CMOS transistors 110,120,130. Appropriate combinational logic, such as an AND gate or the like (111, 121,131), is coupled to the gate of the PMOS and NMOS transistors 112,122,132 and 113,123,133, respectively, to control current flow therethrough. An input clock signal is delivered on line 105 to each of the AND gates. Another input to each of the AND gates is a select line such as one of the select lines 60 of Fig. 1. Each of select lines 60 preferably includes a plurality of individual transistor control lines. Three control lines 161-163 are shown in Fig. 2. A three bit representative selection signal of "101" is indicated as being delivered by these lines. The value 101 (or other value delivered by the control lines) is stored, for example, in the data register of control logic 70. The output of each CMOS transistor is coupled to a common output line to which load 150 is coupled. The circuit or other componentry driven by driver circuit 100 is represented generally by load 150. Each load has an appreciable capacitance associated therewith and this capacitance is represented in phantom lines by capacitor 151. While clock signals propagating through drivers are often illustrated as having a crisp square wave form, in reality these clock signals have rounded corners or, from another perspective, curved or sloping transitions. The rounded corners and curved transitions are a result, at least in part, of the time constant created by inherent or parasitic resistance in the clock signals current path and capacitance 151 in the load. Circuit 100 permits selection of the value of resistance in the clock signal's current path (within the driver) and this selected value in combination with the capacitance of the load creates a time constant that determines the shape of the output clock signal transitions. The provision of selectable time constants permits a circuit designer to soften and/or separate clock signal transitions. The softened and/or spaced clock signal transitions result in significantly reduced EMI and related noise. Referring more specifically to the embodiment of Fig. 2, select/control lines 161-163 permit a user to selectively enable CMOS transistors 110,120,130. Each enabled CMOS transistor effectively functions as a voltage divider with the necessary resistive components being provided primarily by the surface area dependent resistance value of the gate(s). Accordingly, if the three CMOS transistors have the same size gates (i.e., the same resistive values), then a designer may select between three possible resistive values, those values provided by enabling one, two or three of the transistors. Alternatively, the CMOS transistors may be configured such that one or more have differently sized gates. For example, if each of transistors 110,120,130 have a different sized gate, then a designer may select from amongst seven possible resistive values for circuit 100. These include the following enabled CMOS transistor scenarios (which are followed by their selection signal as propagated on lines 161-163 in parentheses): 110 (100), 120 (010), 130 (001), 110+120 (110), 110+130 (101), 120+130 (011) and 110+120+130 (111). It should also be recognized that, while the present invention is shown in Figs. 2-3 in a CMOS embodiment, it may also be implemented in an NMOS or PMOS setting, either using selectable NMOS or PMOS transistors arranged generally as discussed above or selectable NMOS or PMOS transistors in combination with resistors formed in the semiconductor material. Referring to Fig. 3, a schematic block diagram of selection logic 231 for use in circuit 100 of Fig. 2 in accordance with the present invention is shown. Logic 231 essentially takes the place of any or all of the AND gates of circuit 100. In Fig. 3, logic 231 is described as though it replaces gate 131, though it may understandably also replace gates 111,121. Logic 231 provides an inverter 241, a NAND gate 242 and a NOR gate 243. The input clock signal on line 205 is propagated to the NAND and NOR gates. The select signal is propagated via line 263 to the NOR gate and through invertor 241 to the NAND gate. Logic 231 permits CMOS transistor 230 (analogous to CMOS transistor 130) to be tri-stated such that a signal may be driven into the clock signal output 250. While the invention has been described in connection with specific embodiments thereof, it will be understood that it is capable of further modification, within the scope of the appended claims.

Claims: A clock signal driving apparatus comprising: a plurality of first driver circuits (21-24; 100) each having an input (105), for receiving the same input clock signal, and an output; a corresponding plurality of groups of second driver circuits (31-36; 100) each of said second driver circuits (31-36; 100) having an input (105) and an output; the output of each of the first driver circuits (21-24; 100) being connected to each of the respective inputs of a respective group of second driver circuits (31-36; 100); each of said first and said second driver circuits (21-24, 31-36; 100) comprising: a plurality of selectable semiconductor resistive elements (112, 113, 122, 123, 132, 133; 232, 233); and selection logic (70; 111, 121, 131; 231) for applying logic signals to the resistive elements (112, 113, 122, 123, 132, 133; 232, 233) to select one or more of said resistive elements and thereby to create a signal at the driver circuit output which represents the signal at the driver circuit input (105) modified to an extent determined by the selected resistive elements; thereby to generate a plurality of clock signals at the outputs of the second driver circuits (31-36; 100) each representing the input clock signal modified by a respective selected amount. A clock signal driving apparatus as claimed in claim 1, wherein said selection logic (70; 111, 121, 131; 231) is arranged to receive the signal which is present at the respective driver circuit input (105), together with a respective resistive element select signal (161, 162, 163; 263) for each resistive element and to generate respective enable signals which are supplied to said resistive elements (112, 113, 122, 123; 132, 133; 232, 233). A clock signal driving apparatus as claimed in claim 1 or claim 2, wherein said plurality of selectable semiconductor resistive elements (112, 113, 122, 123, 132, 133; 232, 233) within each of said driver circuits (21-24, 31-36; 100) comprises a plurality of pairs of MOS transistors (110, 120, 130; 230) each pair being connected in series between a voltage supply and ground and defining an output at the junction of the two transistors within each pair, the outputs from each pair of transistors within each driver circuit (21-24, 31-36; 100) being connected together to form the driver circuit output. A clock signal driving apparatus as claimed in claim 3, wherein said selection logic (70; 111, 121, 131; 231) serves to enable selectively one or more of said transistors (112, 113, 122, 123; 132, 133; 232, 233). A clock signal driving apparatus as claimed in any preceding claim, wherein said selection logic comprises tri-state logic (231) for disabling one or more of said resistive elements (232, 233).

Inventors: DAVIS RAYMOND A, STEPHENS CHARLES S, DAVIS, RAYMOND A., STEPHENS, CHARLES S.
Applicants: AGILENT TECHNOLOGIES INC, AGILENT TECHNOLOGIES, INC. (A DELAWARE CORPORATION)
Application year: 1998
Main classification: H03K17
IPC codes: H03K19, H03K5, G06F1