Voltage converter

Abstract: a converter for converting a floating voltage of a Band Gap Reference voltage generator fabricated in P-substrate CMOS technology to a fixed voltage with respect to ground utilizes a subtractor to convert the floating voltage to a fixed reference voltage. In addition, the converter utilizes two level shifters which are able to level shift the floating voltage down and level shift the shifted down voltage substantially back to the level of the floating voltage in order to allow a buffer to be used prior to the subtractor.

Description: This invention relates generally to a voltage converter and more particularly, to a voltage converter utilized to convert a floating reference voltage of a Band-Gap reference voltage generator of an integrated circuit, which is built in P-substrate CMOS technology, to a fixed reference voltage with respect to ground. Typically, a highly accurate and temperature independent Band-Gap Reference voltage generator for integrated circuits can be designed by using bipolar technologies. However, due to the popularity of the CMOS process and in particular P-substrate CMOS process, it is desirable to design a Band-Gap Reference voltage generator using bipolar transistors fabricated with P-substrate CMOS technology. Fabricating a bipolar transistor in P-substrate CMOS technology is well known in the industry. Yet, designing a Band-Gap Reference voltage generator with bipolar transistors in P-substrate CMOS technology creates a reference voltage with respect to the power supply. For the purpose of simplicity, hereinafter, the "Band-Gap Reference voltage generator is referred to as "BGR voltage generator". It is not desirable to have a reference voltage with respect to the power supply since the transient variation of the voltage of the power supply causes the output of the BGR voltage generator to vary (float). A typical voltage generator is designed to generate a reference voltage with respect to the ground of the integrated circuit and therefore the voltage is substantially fixed as the power supply voltage or the temperature varies. The reason a reference voltage generated by P-substrate CMOS technology is a floating voltage is that the bipolar transistors fabricated by P-substrate CMOS technology are PNP transistors. In order to generate a reference voltage with respect to the ground, NPN transistors are required which can be easily fabricated in N-substrate CMOS technology. Referring to Figure 1, there is shown a bipolar transistor 10 fabricated with P-substrate CMOS technology. In P-substrate CMOS technology, the substrate is typically connected to ground or to the most negative voltage used in the integrated circuit. Therefore, in P-substrate CMOS technology, in order to create a bipolar transistor, the bipolar transistor has to be created in a well. Since the substrate is a p-substrate, the well has to be n-well which then dictates that the bipolar transistor be a PNP transistor. In this type of configuration, n-well is used as the base B, one of the p+ regions is used as collector C and the other p+ region is used as the emitter E of the bipolar transistor 10. In Figure 1, layer 12 is an insulator and layer 14 is a material such as aluminum to be used for the gate G of a P-substrate CMOS transistor. Since the transistor 10 is used as a bipolar transistor, gate G is connected to a voltage above 5 volts which does not affect the function of bipolar transistor 10. Referring to Figure 2, there is shown a block diagram of a BGR voltage generator 20 built with NPN transistors which generates a temperature independent fixed 1 volt reference voltage with respect to ground. Since the reference voltage 1 volt is generated with respect to ground and the voltage of ground is designated as zero, the output voltage V R1 of the BGR voltage generator 20 is 1 volt. Referring to Figure 3, there is shown a block diagram of a BGR voltage generator 30 built with PNP transistors. The BGR voltage generator 30 generates a temperature independent reference voltage which is always 1 volt below the voltage of the power supply. The BGR voltage generator 30 generates a fixed 1 volt reference voltage with respect to power supply V 2 and since the voltage of the power supply V 2 is typically 5 volts, the output V R2 of the BGR voltage generator 30 is 5 - 1 = 4 volts. The output voltage of the BGR voltage generator 30 is floating since any transient change in the power supply causes the output voltage V R2 to vary. For example, if the voltage, of the power supply changes to 5.2, then the output V R2 is 5.2-1 = 4.2 volts. EP-A-0794477 describes, particularly in Figures 13, 13A and 13B, a circuit for producing a number of different reference voltages. The circuit includes a BGR voltage generator connected to a buffer and also includes a subtracting means. The output voltages vary with the input voltage but each output voltage is at a fixed level with respect to the instantaneous input voltage. Therefore, in this specification "a Band-Gap reference voltage with a floating reference voltage" and a "floating voltage source generating a floating voltage" both shall mean a Band-Gap reference voltage generator which generates a fixed reference voltage independent of temperature change and outputs a voltage such that the difference between the voltage of the power supply and the output voltage is a fixed voltage independent of temperature variations. The present invention is directed to converting a floating voltage of a Band Gap Reference voltage generator to a fixed reference voltage. In accordance with this invention a circuit for converting a floating voltage V BGR which is a fixed voltage independent of temperature, below the voltage V DD of a power source to a fixed voltage V GR3 with respect to ground comprises: a subtracting means having a first input, a second input and an output; a power source generating a voltage V DD ; said power source being electrically connected to said first input of said subtracting means; a floating voltage source generating a floating voltage V BGR with respect to said voltage of said power source V DD ; said floating voltage V BGR being a fixed voltage below said voltage V DD of said power source; a buffering means having an input and an output; a first level shifting means; a second level shifting means; said floating voltage source being electrically coupled to said second input of said subtracting means through said first level shifting means and said buffering means; said buffering means preventing any current being drawn from said floating voltage source; said first level shifting means shifting down said floating voltage of said floating voltage source to match the required input level of said buffering means and said second level shifting means shifting up said shifted down voltage at the output of said buffer to substantially the same level as the floating voltage V BGR ; and, the output of the buffering means being connected to the second input of the subtracting means via an intermediate node of a potential divider network R 2 , αR 2 connected to ground, said subtracting means arranged to subtract said voltage at said first input from said voltage at said second input and thus provide a voltage difference with respect to ground as an output voltage V BGR3 at said output, said output voltage V BGR3 being independent of temperature and power supply variations. Particular embodiments of voltage converters in accordance with this invention will now be described with reference to the accompanying drawings; in which:- Figure 1 shows a bipolar transistor fabricated with P-substrate CMOS technology; Figure 2 shows a block diagram of a reference voltage built with NPN transistors which generates a temperature independent voltage with respect to ground; Figure 3 shows a block diagram of a reference voltage built with PNP transistors which generates a temperature independent voltage with respect to a power supply; Figure 4 shows a circuit diagram of the first approach of this invention to convert a floating reference voltage of a BGR voltage generator to a fixed reference voltage; Figure 5 shows an improved version of the circuit diagram of Figure 6; and Figure 6 shows the preferred embodiment of this invention. Referring to Figure 4, there is shown a circuit diagram 40 of the first approach of this invention to convert a reference voltage with respect to the power supply (floating) to a reference voltage with respect to ground (fixed). Circuit 40 is connected to a BGR voltage generator 42 which generates a floating voltage V BGR with respect to its power supply V DD . As a result, V BGR is: V BGR = V DD - V REF . Where V REF is a temperature independent and a fixed voltage generated by a BGR voltage generator. In Figure 4, the power supply V DD is connected to the inverting (-) input of an Operational Amplifier (Op-Amp) 44 through resistor R 1 . The floating reference voltage V BGR is connected to the non-inverting (+) input of the Op-Amp 44 through resistor R 2 . The inverting (-) input of the Op-Amp 44 is also connected to the output of the Op-Amp 44 through resistor R 1 and the non-inverting (+) input of the Op-Amp 44 is connected to ground (GND) through resistor R 2 . Resistor R 1 is equal to resistor R 2 and α is a constant factor in the impedance of the resistors R 1 and R 2 . In Figure 4, the Op-Amp 44 works as a difference amplifier. A difference amplifier subtracts its two input voltages and sends out the result as an output voltage. Therefore, the output voltage V BGR1 of the Op-Amp 44 is the difference between the two input voltages V DD and V BGR . V BGR1 = a[V DD -V BGR ] Since V BGR = V DD - V REF then, V BGR1 = a[V DD - [V DD - V REF ] ] = aV REF . Therefore, by subtracting V BGR from V DD , only V REF is left. As a result, the output voltage V BGR1 will be a times V REF . This means that the output voltage is proportional to the reference voltage V REF regardless of fluctuations of V DD . By selecting a proper α, a desired fixed reference voltage can be generated. However, this is not a practical solution since connecting V BGR directly to Op-Amp 44 draws current from V BGR which in turn causes V BGR to undesirably vary. Referring to Figure 5, there is shown a circuit 50 which is an improved version of circuit 40 of Figure 4. In Figure 5, all the elements that are the same and serve the same purpose as the elements of circuit 40 of Figure 4 are designated by the same reference numerals. In Figure 5, again Op-Amp 44 subtracts its two input voltages to provide a reference voltage V BGR2 which is proportional to V REF of the BGR voltage generator 42. In Figure 5, the output voltage V BGR of the BGR voltage generator 42 is connected to non-inverting input of Op-Amp 44 through a Metal Oxide Silicon Field Effect Transistors (MOSFET) T 1 and buffer (Op-Amp) 52. Since the common mode voltages of the Op-Amps are lower (ex: 3.5 volt) than V BGR (ex: 4 volts), V BGR has to be shifted down to match the required input voltages of Op-Amp 52. Transistor T 1 , which is used as a level shifter to shift down the V BGR , prevents any current being drawn from BGR voltage generator 42. V BGR is connected to the gate of the N-channel MOSFET (NMOS) transistor T 1 . The drain of transistor T 1 is connected to V DD and its source is connected to the non-inverting input of Op-Amp 52. The output of the Op-Amp 52 is connected to its inverting input and also to the non-inverting input of the Op-Amp 44 through resistor R 2 . The gate and the drain of transistor T 2 are connected to V DD and its source is connected to the non-inverting input of Op-Amp 54. The output of the Op-Amp 54 is connected to its inverting input and also to the inverting input of the Op-Amp 44 through resistor R 1 . Transistor T 1 has a gate to source voltage V GS1 . Thus, the source voltage V S1 of the transistor T 1 is: V S1 = V G1 - V GS1 . Where V G1 is the gate voltage of the transistor T 1 . Since node VBGR output of BGR voltage generator 42 is connected to the gate of the transistor T 1 , the source voltage V S1 of transistor T 1 is: V S1 = V BGR -V GS1 . As a result, transistor T 1 shifts down voltage V BGR by V GS1 to V S1 . The Op-Amp 52 operates in linear mode due to negative feedback and therefore it delivers voltage of its non-inverting input to its output and to the non-inverting input of the Op-Amp 44 through resistor R 2 . The voltage of non-inverting input of Op-Amp 52 and its output voltage are both equal to: V a = V S1 = V BGR - V GS1 . Since V BGR = V DD -V REF , then V a = V DD - V REF - V GS1 . In order to subtract the two input voltages V a and V b of the difference amplifier formed by Op-Amp 54 and resistors R 1 , R 2 , R1 and R 2 and have a voltage proportional to V REF , V DD has to be shifted down. The reason V DD needs to be shifted down is that since the voltage at the non-inverting input of the Op-Amp 44 is the shifted down V BGR by V GS1 , V DD has to be shifted down by a voltage equal to V GS1 . In order to shift down the voltage V DD , the power supply V DD is connected to the gate and the drain of the transistor T 2 . The source voltage of the transistor T 2 is : V S2 = V b = V DD - V GS2 . Where V GS2 is the gate to source voltage of transistor T 2 . In order to shift down V DD by the same voltage as the voltage by which V BGR is shifted down, V GS1 must be equal to V GS2 . Therefore, the sizes of transistors T 1 and T 2 have to be the same and the source current I 1 of transistor T 1 has to be equal to the source current I 2 of transistor T 2 . In Figure 5, a current mirror 60 is used to provide identical currents to transistors I 1 and I 2 . The current mirror 60 has three MOSFET transistors T 4 , T 5 and T 6 . The gates of transistors T 4 , T 5 and T 6 are connected to each other and the sources of transistors T 4 , T 5 and T 6 are grounded. The drain of transistor T 5 is connected to the source of transistor T 1 and the drain of transistor T 6 is connected to the source of transistor T 2 . The drain of transistor T 4 is connected to its gate and also to the power supply V DD through resistor R 3 . By choosing the same sizes for transistors T 5 and T 6 , the current in transistors T 5 and T 6 and hence the current in transistors T 1 and T 2 will be the same. The Op-Amp 54 operates in linear mode due to negative feedback and therefore, the voltages of its non-inverting input, inverting input and the output are all equal to: V b = V DD -V GS2 . Therefore, the output voltage V BGR2 of Op-Amp 44 is: V BGR2 = [V b - V a ] = [V DD - V GS2 - [V DD - V REF - V GS1 ]] = [V REF - V GS2 + V GS1 ] In order to have V BGR2 proportional to V REF , the two voltages V GS1 and V GS2 have to be equal to cancel each other in the above equation. In theory, the current I 1 of the drain of transistor T 5 and the current I 2 of the drain of transistor T 6 are identical to the current I of the transistor T 4 . However, due to the non-ideal characteristics of MOSFET transistors, since the drain to source voltage of transistor T 1 is different from the drain to source voltage of transistor T 2 , their currents I 1 and I 2 are slightly different from each other. This causes V GS1 and V GS2 to be slightly different from each other. Therefore, V GS1 and V GS2 can not completely cancel each other. As a result, the output can not be exactly proportional to V REF . Referring to Figure 6, there is shown the preferred embodiment 70 of this invention which is an improved version of circuit 50 of Figure 5. In Figure 6, all the elements that are the same and serve the same purpose as the elements of circuit 50 of Figure 5 are designated by the same reference numerals. In the same manner as circuit 50 of Figure 5, transistor T 1 of Figure 6 shifts down V BGR by V GS1 . In Figure 6, instead of shifting down the power supply V DD , the V DD is connected to the inverting input of the Op-Amp 44 through resistor R 1 and the shifted down V BGR is shifted back up to V BGR and supplied to the difference amplifier formed by Op-Amp 44 and resistors R 1 , R 2 , aR 1 and aR 2 . The reason Op-Amp 72 is placed in circuit 70 is to prevent any current being drawn from the V BGR output of the BGR voltage generator 42. However, this requires the V BGR voltage to be shifted down to a level required by Op-Amp 72 and since V DD is not shifted down prior to its connection to Op-Amp 44, the shifted down V BGR has to be shifted up back to V BGR prior to its connection to Op-Amp 44. EP-A-0913932 filed concurrently herewith, discloses a circuit which shifts down a voltage and subsequently shifts it substantially back to the original voltage. In Figure 6, the source of transistor T 1 is connected to the non-inverting input of buffer 72. The output of Op-Amp 72 is connected to the gate of a NMOS transistor T 7 . The drain of transistor T 7 is connected to the power supply V DD and the source of transistor T 7 is connected to the drain of transistor T 6 . In circuit 70, the inverting input of Op-Amp 72 is connected to the source of transistor T 7 which causes the source voltage V S7 of transistor T 7 to be equal to the inverting and non-inverting inputs of the Op-Amp 72. It should be noted that in this configuration, the inverting and non-inverting inputs of the Op-Amp 72 are equal. Therefore, the source voltage V S7 of the transistor T 7 is set to be equal to the source voltage V S1 of transistor T 1 . This causes the gate voltage V G7 of transistor T 7 which is the output voltage of the Op-Amp 72 to be forced to be equal to: V G7 = V S7 + V GS7 , where V GS7 is the gate to source voltage of transistor T 7 . In this invention, transistor T 7 is used to guide the output of Op-Amp 72 to be shifted up. Both transistors T 1 and T 7 are NMOS transistors and they both are made with the same process and in the layout, they are placed close to each other to minimize the process variation of different locations on the wafer. As: a result, the gate to source voltages V GS1 and V GS7 of the two transistors T 1 and T 7 are substantially the same since the transistors T 1 and T 7 have identical sizes and currents. Therefore, since the source voltage V S1 of transistor T 1 is: V S1 = V BGR - V GS1 , and since V G7 = V S7 + V GS7 , V S1 = V S7 (source voltage of T 7 is set by Op-Amp 72 to be equal to source voltage of T 1 ) and V GS1 = V GS7 (two identical transistors T 1 and T 7 have same currents) then V 2 = V G7 = V S1 + V GS7 = V BGR - V GS1 + V GS7 = V BGR . Therefore, the output voltage of Op-Amp 72 which is the gate voltage V G7 of the transistor T 7 is substantially equal to the voltage V BGR . Furthermore, against the commonly accepted method of obtaining the level shifted output voltage from the source of transistor T 7 , the output is obtained from the gate of transistor T7 which is also the output of the Op-Amp 72 and is buffered by the Op-Amp 72. Op-Amp 44 receives V DD on its inverting input through resistor R 4 and V BGR on its non-inverting input through resistor R2. Therefore, the output voltage V BGR3 of the Op-Amp 44 is: V BGR3 = a [V DD - V BGR ] and since V BGR = V DD - V REF then V BGR3 = a [V DD - [V DD - V REF ]] = a V REF . As a result, V BGR is proportional to V REF . V BGR is a reference voltage with respect to the power supply V DD and is independent of temperature variations. Therefore, circuit 70 converts a floating reference voltage to a fixed and buffered reference voltage. The disclosed embodiment of this invention can also be utilized as a dual purpose BGR voltage generator. If desired, one can use the floating reference voltage V BGR or the fixed reference voltage V BGR3 . Usually, a conventional BGR voltage generator needs to be buffered since drawing current from a conventional BGR generator disturbs its performance and accuracy. In contrast to a conventional BGR voltage generator, the disclosed embodiments of this invention provide a fixed reference voltage which is also buffered and can provide current to external circuits. This is due to the fact that the output voltage is taken from the output of an Op-Amp which is capable of delivering current without disturbing its output voltage. It should be noted that circuit 70 can be built as a stand alone circuit' to be used in conjunction with a floating reference voltage generator or can be built as an integrated circuit in conjunction with a floating reference voltage generator on a common substrate. It should also be noted that the usage of the disclosed embodiments of this invention is not limited to BGR voltage generators made with P-substrate CMOS technology. The disclosed embodiments of this invention can be used in conjunction with any type of reference voltage generator which generates a floating reference voltage.

Claims: A circuit for converting a floating voltage (V BGR ) which is a fixed voltage independent of temperature, below the voltage (V DD ) of a power source to a fixed voltage (V GR3 ) with respect to ground comprising:. a subtracting means (44) having a first input, a second input and an output; a power source generating a voltage (V DD ); said power source being electrically connected to said first input of said subtracting means (44); a floating voltage source (42) generating a floating voltage (V BGR ) with respect to said voltage of said power source (V DD ) ; said floating voltage (V BGR ) being a fixed voltage below said voltage (V DD ) of said power source; a buffering means (72) having an input and an output; a first level shifting means (T1); a second level shifting means (T7); said floating voltage source (42) being electrically coupled to said second input of said subtracting means (44) through said first level shifting means (T1) and said buffering means (72); said buffering means (72) preventing any current being drawn from said floating voltage source (42); said first level shifting means (T1) shifting down said floating voltage of said floating voltage source (42) to match the required input level of said buffering means (72) and said second level shifting means (T7) shifting up said shifted down voltage at the output of said buffer (72) to substantially the same level as the floating voltage (V BGR ); and, the output of the buffering means (72) being connected to the second input of the subtracting means :(44) via an intermediate node of a potential divider network (R 2 , αR 2 ) connected to ground, said subtracting means (44) being so constructed and arranged to subtract said voltage at said first input from said voltage at said second input and thus provide a voltage difference with respect to ground as an output voltage (V BGR3 ) at said output, said output voltage (V BGR3 ) being independent of temperature and power supply variations. A circuit as recited in claim 1, wherein said circuit is formed as an integrated circuit. A circuit as recited in claim 2, wherein said integrated circuit is fabricated in P-substrate CMOS technology. A circuit as recited in any preceding claim, wherein said floating reference voltage source is a Band Gap Reference voltage generator (42). A circuit as recited in any one of the preceding claims, wherein the first and second level shifting means are formed by MOSFET transistors (T1,T2) connected between the power source and a current mirror circuit (60) and having their gates connected respectively to the output of the floating voltage source (42) and the output of the buffering means (72).

Inventors: MCINTYRE HARRY J, YAZDY MOSTAFA R, MCINTYRE, HARRY J., YAZDY, MOSTAFA R.
Applicants: XEROX CORP, XEROX CORPORATION
Application year: 1998
Main classification: G05F3
IPC codes: G05F1, G05F3, H01L21, H01L27