Frequency tracking arrangements

Abstract: A frequency tracking arrangement in which a frequency tracking circuit utilises a continuously variable analogue first order all-pass filter circuit as a controllable phase-shift element in a closed-loop system which produces a control signal to control the phase shift circuit to introduce a 90° phase shift of a received reference frequency signal when the circuit is tracking that reference frequency. The control signal may then be utilised to slave the cut-off frequency of a filter and/or the delay time introduced by a delay line.

Description: The present invention relates to frequency tracking arrangements. In particular although not exclusively the invention is concerned with frequency tracking arrangements by means of which the cut-off frequency of a continuous-time filter and/or the delay of one or more delay lines may be controlled in dependence upon the frequency of a reference frequency input signal. Such an arrangement may be used, for example, in the retrieval of data from an optical disk data carrier, where data is stored as a predetermined number of bits per unit length of data storage path. When reading such data carriers, the disk must rotate faster when data is being read from near the centre of the disk, or the data rate is slower, than when data is being read from near the periphery of the disk. A continuous frequency tracking/filter cut-off arrangement would allow data to be read at the different rates or while the disk is being speeded up or slowed down. Automatic adjustment of a filter characteristic is known, for example, from prior patent specification GB 2194402, in which the time constant of a filter circuit is controlled by a frequency tracking loop utilising a voltage-controlled oscillator. The control of the delay introduced by a delay line is described in GB 2130845, where the phase shift corresponding to that delay is compared with a fixed 90° phase shift of an input signal in a closed loop system. An article entitled "Continuous-Time MOSFET-C Filters in VLSI by Y. Tsividis published in IEEE Journal of Solid State Circuits, Vol. SC-21, No. 1, February 1986 discloses a frequency tracking arrangement where the frequency of a slave continuous-time filter is controlled by a master phase lock circuit employing a filter section as a variable analogue phase shift element. According to one aspect of the present invention, a frequency tracking arrangement comprises a continuously variable analogue phase shift circuit, a phase comparator, means to apply a reference frequency signal to respective inputs of the phase comparator directly and by way of said phase shift circuit, and means to derive a control signal for controlling the value of phase shift provided by said phase shift circuit in dependence upon the output of said comparator, said phase shift circuit comprising an active first order all-pass filter. The control signal may be utilised to control the cut-off frequency of a controllable continuous-time or analogue filter, or to control the value of delay introduced by a controllable delay line. The all-pass filter and the controllable analogue filter may utilise active filter circuits of the kind described in Applicants' co-pending application No. GB 9622182.5. A frequency tracking arrangement in accordance with the invention will now be described with reference to the accompanying drawings, of which:- Figure 1 shows the arrangement schematically, and Figures 2 and 3 show diagrammatically respective parts of the arrangement shown in Figure 1. Referring first to Figure 1, the frequency tracking arrangement comprises a frequency tracking circuit 1, a controllable cut-off frequency filter 2 and a controllable delay arrangement 3. The frequency tracking circuit 1 comprises a frequency divider 4 which receives a reference frequency input signal on a path 5 and which provides a frequency-divided signal to a controllable phase shift circuit 6 and to a phase comparator 7, which also receives a phase-shifted signal from the phase shift circuit 6. The phase comparator 7 provides a d.c. or slowly varying control signal on a path 8 by way of a loop filter 9, which may be a low-pass filter. The control signal is returned to a control input of the phase shift circuit to control the value of phase shift introduced by that circuit. The control signal on the path 8 is also applied by way of an adjusting circuit 10 to a controllable continuous time or analogue filter 11, the adjusting circuit 10 being arranged to provide any required off-sets or factoring in dependence upon an adjusting signal on a path 12, and by way of a compensation circuit 13 and a control circuit 14 to control the values of delay introduced by delay lines 15 to 17. Again the circuits 13 and 14 provide any necessary off-sets and factoring in dependence upon a control signal on a path 18. The cut-off frequency F c of the filter 11 and the delay T del introduced by any one of the delay lines 15 to 17 may be arranged to lock to and track the incoming reference frequency signal F ref such that:- F c = K1.(F ref ) and T del = K2. 1/(F ref ) The frequency divider 4 ensures a 50% duty cycle for signal to the phase shift circuit 6 and the phase comparator 7, the divide ratio allowing a degree of coarse control over the cut-off frequency of the filter 11 and the delays introduced by the delay lines 15 to 17. The phase shift circuit 6, the phase comparator 7 and the loop filter 9 form a closed loop control system which adjusts the phase shift such that the control signal on the path 8 is virtually zero. The choice of phase shift circuit 6 and phase comparator 7 are important. In particular:- i) the phase shift circuit should have a phase/frequency characteristic which offers substantially zero phase shift a low frequencies and substantially 180° phase shift at very high frequencies, and ii) the phase comparator/loop filter combination should provide substantially zero net output when the divided reference frequency signal and the phase-shifted signal are in phase quadrature. The latter condition ensures that the closed control loop will lock when the phase shift circuit is introducing (90° + n.180°) of phase shift. If the maximum phase shift which can be introduced is 180°, solutions for n>o, and "harmonic locking", are effectively impossible, and the loop has an extremely wide capture range. The phase shift circuit is an active filter having a first order all-pass characteristic, such as the circuit illustrated in Figure 2, since this circuit has the necessary phase/frequency response while providing a flat amplitude response. If a second order low-pass filter were to be used, the attendant amplitude response would present problems when the frequency tracking circuit 1 is required to track a step increase in reference frequency. Similarly, the use of a delay line, can introduce phase shifts of greater than 180°, so that the advantage of wide capture range would be lost. By constructing the phase shift circuit 6 from similar circuits to those of the filter 11, the filter 11 will be adjusted appropriately each time the tracking circuit responds to a change in reference frequency signal. Furthermore, the effects of physical and process variations, which would otherwise cause a shift in the characteristics of the filter 11, are compensated for because they affect the phase shift circuit 6 and the filter 11 in an identical manner. Further control over the relationship between the reference frequency and the characteristics of the filter 11 are made possible by means of the adjusting circuit 10, which may for example introduce an offset voltage or a factor to the control voltage as applied to the filter 11. Since the delay lines 15 to 17 may not be constructed from similar circuit elements to those used in the phase shift circuit 6 and the filter 11, the compensation circuit 13 may be used to remove the dependence on physical or process variables which are not common to the delay line elements. The control circuit 14 may be used to adjust the absolute value of each delay with respect to the reference frequency and also the relative delay between delay lines as required in any particular system. Referring now to Figure 2, the phase shift circuit 6 may comprise an active filter network as described in co-pending Patent Application No. GB 9622182.5, the control voltage on the path 8 being applied to control the variable current sources 19 such that an input signal frequency applied to input terminals 20 appears phase-shifted at output terminals 21. Referring to Figure 3, the phase comparator 7 may comprise an exclusive OR gate, or an analogue multiplier circuit such as the Gilbert cell shown, signals from the phase shift circuit 6 and from the frequency divider 4 being applied respectively to the pairs of terminals 22 and 23, and an output signal to the loop filter being derived at the terminals 24.

Claims: A frequency tracking arrangement comprising a continuously variable analogue phase shift circuit (6), a phase comparator (7), means (4) to apply a reference frequency signal to respective inputs of the phase comparator directly and by way of said phase shift circuit, and means (8) to derive a control signal for controlling the value of phase shift provided by said phase shift circuit (6) in dependence upon the output of said comparator, characterised in that said phase shift circuit (6) comprises an active first order all-pass filter. A frequency tracking arrangement in accordance with Claim 1 further comprising a controllable continuous-time filter, whereby the cut-off frequency of said controllable continuous-time filter is controlled by the control signal. A frequency tracking arrangement in accordance with Claim 2 wherein the controllable continuous-time filter comprises an active filter circuit. A frequency tracking arrangement in accordance with Claim 1, Claim 2 or Claim 3 further comprising a controllable delay line, whereby the value of delay introduced by said controllable delay line is controlled by the control signal. A frequency tracking arrangement in accordance with any preceding claim wherein the phase comparator is an analogue multiplier circuit. A frequency tracking arrangement in accordance with Claim 5 wherein the analogue multiplier circuit is a Gilbert cell. A frequency tracking arrangement as claimed in Claim 1 and including a controllable analogue filter arrangement to which said control signal is arranged to be applied to control the cut-off frequency thereof.

Inventors: BEATSON TREVOR PETER, BODDY DAVID IAN, FENNEY BREDAN PATRICK, MIHAILOVITS, BEATSON, TREVOR PETER, BODDY, DAVID IAN, FENNEY, BREDAN PATRICK
Applicants: LSI LOGIC CORP, LSI LOGIC CORPORATION
Application year: 1998
Main classification: H03L7
IPC codes: H03L7, H03H11, H03D7, H03J7