A dividing circuit for dividing by even numbers

Abstract: A dividing circuit comprises, connected in a ring, a plurality M of transistor stages (S1-S4), where M is an even integer. Each transistor stage comprises an input node, a clock node and an output node. A tri-state inverter stage (S5) has an input node connected to the output node of the preceding transistor stage in the ring (S4), an enable node connected to the clock nodes of the transistor stages, and an output node (CLKOUT) connected to the input node (I1) of the subsequent transistor stage in the ring. Each transistor stage comprises a first pair of transistors of a first conductivity type (T1,T2) connected in series between a first voltage level and an output node and a second pair of transistors of a second conductivity type (T3,T4) connected in series between a second voltage level and said output node, wherein control nodes of a first transistor (T1,T4) of each said transistor pair are connected together to provide the input node (I1) for the stage, and control nodes of a second transistor (T2,T3) of each said transistor pair are connected together to provide the clock node (CLKIN) for the stage, whereby when an input clock signal is applied to the clock nodes of the transistor stages, an output signal is generated at the output node of the tri-state inverter in which each cycle represents M cycles of the input clock signal.

Description: This invention relates to a divider circuit for dividing by even numbers. Clock divider circuits are useful in a number of applications, particularly in counters, where a complete cycle of the output signal represents a predetermined number of incoming clock cycles. The cycles of the output signal can be used to "count" the incoming clock cycles. It is desirable for such clock divider circuits to work at low power and at high frequencies. For example, desired operating parameters might be a current consumption of 10µA at a supply voltage of 3.3V, with an operating frequency of around 100 MHz. It is also desirable that such divider circuits consume a minimum amount of silicon when implemented on an integrated circuit. Existing counters are generally based on binary counters. Such counters are optimally designed to divide by 2 n . However, for other even numbers some concatenation of dividing circuits is frequently required to provide the required dividing factor. This increases signal path length and introduces unwanted delays. US Patent No 4,953,187 discloses a CMOS divide by 4/5 circuit comprising first to fifth inverting stages. Feed forward circuitry is provided to force the last three stages to change states simultaneously, thereby providing a divide by 4 circuit. When the feed forward circuitry is not active, the circuit divides by 5. It is an object of the present invention to provide a programmable dividing circuit which exhibits an improvement in operating frequency and reducing signal delays with reduced silicon consumption. According to one aspect of the present invention there is provided a dividing circuit comprising, connected in a ring: a plurality M of transistor stages (Sn), where M is an even integer, each transistor stage (Sn) comprising an input node (In), a clock node and an output node (On); and a tri-state inverter stage (S5, S9, S'7) having an input node connected to the output node of the preceding transistor stage in the ring, an enable node connected to the clock nodes of the transistor stages (Sn), and an output node connected to the input node of the subsequent transistor stage in the ring, wherein each transistor stage comprises a first pair of transistors (T1, T2) of a first conductivity type connected in series between a first voltage level and an output node (On); a second pair of transistors (T3, T4) of a second conductivity type connected in series between a second voltage level and said output node (On), wherein control nodes of a first transistor of each said transistor pair are connected together to provide the input node (In) for the stage, and control nodes of a second transistor of each said transistor pair are connected together to provide the clock node for the stage, whereby when an input clock signal (CLK IN) is applied to the clock nodes of the transistor stages, an output signal is generated at the output node of the tri-state inverter in which each cycle represents M cycles of the input clock signal (CLK IN); characterised in that the dividing circuit further comprising a switching circuit for selectively connecting one of at least two inputs (V7, V5) to an output, wherein the output nodes of at least two alternate transistor stages of the dividing circuit are connected respectively to said at least two inputs, whereby one of said output nodes is selectively connectable to the input node of a subsequent stage so that the integer M is programmable. Although two "pairs" of transistors are referred to, there is no need for transistors to be matched or otherwise be dependent on one another in their operating parameters. In the described embodiment, the first transistors are directly connected to the respective first and second voltage levels and the second transistors are directly connected between the first transistors and the output node. This provides a simple transistor configuration which does not consume an excessive amount of silicon in an integrated circuit yet which provides a high frequency, low power operating transistor stage. In an environment where the first voltage level is a power supply voltage for the stage and the second voltage level is ground, the first pair of transistors are PMOS transistors and the second pair of transistors are NMOS transistors. In the described embodiment, the switching circuit has its output connected to the input node of the tri-state inverter circuit. The dividing circuit described herein can operate at low powers, for example drawing a current of less than 10µA at a supply voltage of 3.3V and can operate up to high frequencies. It is envisaged that operation up to a frequency of 1GHz is possible, limited only by the characteristics of a single CMOS transistor. Moreover, the signal at the output of the tri-state inverter has a duty cycle of 50% regardless of the duty cycle of the input signal. The invention also provides a phase-locked-loop circuit incorporating a dividing circuit as defined herein. For a better understanding of the present invention and to show how the same may be carried into effect reference will now be made by way of example to the accompanying drawings. Figure 1 is a circuit diagram of a divide-by-four circuit for use with the programmable circuit of Figure 9; Figure 2 is a truth table for each transistor stage in the circuit; Figure 3 is a truth table for the tri-state inverter stage; Figure 4 represents the input and output signals for the circuit of Figure 1; Figure 5 shows the sequence of logic states for the circuit of Figure 1 in operation; Figures 6a to 6f represent the input and output waveforms for the circuit of Figure 1; Figure 7 is a circuit diagram of a divide by eight circuit for use with the programmable circuit of Figure 9; Figures 8a to 8j are waveforms for the circuit of Figure 7; Figure 9 is a diagram of a programmable divide-by-four/divide-by-six circuit; and Figure 10 is a block diagram of a phase-locked-loop. The preferred embodiment of the invention is shown in Figure 9. However, for a better understanding of the basic principles of the division circuitry incorporated in Figure 9. Figures 1 to 8j are first described in detail. Figure 1 illustrates a divide-by-four circuit which comprises four stages S1,S2,S3,S4 and a tri-state inverter stage S5 connected in a ring with an input node of each stage connected to an output node of a preceding stage. Each stage comprises a first pair of p-channel MOS transistors T1,T2 and a second pair of n-channel MOS transistors T3,T4. Only the first stage S1 is described in detail herein, the remaining transistor stages (excluding the tri-state inverter stage S5) being the same. The transistors T1,T2 of the first pair are connected in series between a supply voltage Vdd and an output node O1. The transistors T3,T4 of the second pair are connected in series between the output node O1 and ground. The gate of the outermost transistor of each pair T1,T4 is connected to an input node I1 for the stage S1. The gates of the inner two transistors T2,T3 are connected to receive an input clock signal CLK IN. S2,S3 and S4 represent similar stages, each of which have an outer set of transistors connected to an input node for the stage and an inner set of transistors connected to the input clock signal CLK IN. The output signal is taken from the output node of the tri-state inverter stage S5, the output signal being designated CLK OUT. In the following description, the node of each stage which receives the input signal CLK IN and is connected to the gates of the innermost transistors T2,T3 is referred to as the clock node of the stage. Figure 2 represents the truth table for each of the stages S1 to S4. Considering the stage S1, when the voltage at the input node I1 has logic state zero, transistor T4 is off and transistor T1 is turned on. In this situation, when the input signal CLK IN has a logic state of zero, transistor T2 is likewise turned on, creating a current path which allows the output node O1 to be pulled up to Vdd, as shown in the first line of the truth table of Figure 2. However, when the input signal CLK IN has a logic state of one, the transistor T2 is turned off with the consequence that the output node O1 "floats" at the logic state it held previously. That is, the output node represents a high impedance state to the subsequent stage and is not driving any output current. When the voltage at the input node I1 is in logic state one, the transistor T1 is turned off and the transistor T4 is turned on. Now, with the input clock signal CLK IN at logic state zero, the transistor T3 remains off and so the output node O1 floats. When the logic state of the input signal CLK IN changes to a one, the transistor T3 is turned on to create a current path allowing the transistors T3 and T4 to pull the output node O1 down to ground. The tri-state inverter stage S5 has an input node 2 connected to the output node of the preceding stage S4, an output node 4 which is connected to the input node of the transistor stage S1 and an enable input 6 which is connected to the clock nodes of the transistor stages S1 to S4. Tri-state inverters are known in the art and have the truth table shown in Figure 3, where the state marked "float" has the same meaning as that applied to the transistor stage S1 to S4. One exemplary circuit configuration of a tri-state inverter is illustrated in stage S5 of Figure 1, but it will be appreciated that other tri-state inverters can be used with the present invention. In the example of Figure 1, the tri-state inverter has a pair of p-channel transistors 10,12 connected between the supply voltage Vdd and the output node 4, and a pair of n-channel transistors 14,16 connected in series between the output node 4 and ground. The gates of the outermost transistors 10,16 are connected together to provide the input node 2 for the tri-state inverter. The gate of the innermost p-channel transistor 12 is connected to the enable input 6 via an inverter 18. The gate of the innermost n-channel transistor 14 is connected directly to the enable input 6. In the circuit of Figure 1, the enable input 6 receives the clock signal CLK IN supplied to the divide-by-four circuit, and thus acts as the clock node for the stage. As shown in Figure 4, the circuit represents a divide-by-four counter, that is, one cycle of the output signal CLK OUT represents four cycles of the input signal CLK IN. To achieve this, the circuit causes a change in state in the output signal only on every other rising edge of the input signal. That this is the case can be seen by following through the effect of the truth tables of Figures 2 and 3, as in the following description of Figure 5. Consider the initial state of the circuit illustrated in Figure 5, where the logic state of the input signal CLK IN is high or logic one. The output signal CLK OUT has the same logic state as the input stage I1 for the first stage S1, and is marked V1 in Figure 5. V2 to V5 represent the output signals of the stages S1 to S4 respectively. In the initial state of Figure 5, V2 has logic value one, V3 and V4 have logic value zero and V5 has logic value one. When the incoming signal CLK IN changes state to logic level zero, the stage S1 has its clock node at zero and its input at zero, so that its output V2 remains at logic level one. The stage S2 still has an input signal (V2) at logic stage one, but because the state of the incoming signal CLK IN is now zero, the output node V3 now floats at logic state zero. The stage S3 now has an input state of zero, while the input signal CLK IN is zero, thus the state of its output changes to logic state one. The stage S4 now has a logic state of one at its input while the clock signal is low so that its output V5 floats at the preceding logic state one. The tri-state inverter stage S5 has an input signal at logic state one, while the state of the clock signal CLK IN is low, so that the output V1 floats at the preceding logic state, that is at logic state zero. This analysis can be followed through for the subsequent changes in state of the incoming clock signal CLK IN with reference to the truth tables of Figures 2 and 3. The result is the tabular data shown in Figure 5, from which it can be seen that the sequence results in a repeating cycle marked R which is represented by the output waveform in Figure 4. Initialisation is not required to start the divider circuit. It will self-start within a few cycles of the input signal as the result of small asymmetries in the layout. However, initialisation circuitry may be added if desired to force a particular initial state. It will readily be appreciated that logic circuitry such as that marked L in Figure 1 may be inserted between any two sequential stages of the ring, provided that the logic circuitry is not inverting. Power consumption of the circuit is very low compared with existing device circuits. One reason for this is that only one internal node changes state on each clock edge, so that the power consumption is dominated by the charge/discharge currents of the capacitance of a single node. Moreover, the maximum operating frequency of the circuit can be very high, because the delay introduced by each stage is only that introduced by a single transistor. In other words, each stage only comprises one "layer" of transistor logic requiring a change in state between input and output. The circuit of Figure 1 has the useful property of maintaining a duty cycle of 50% in the output signal whether or not the input signal has a duty cycle of 50%. Figure 6a represents an input waveform CLK IN having a duty cycle of 50%. Figure 6b shows the output signal at the output node 4 of the tri-state inverter (marked V(1) in Figure 6b). The output signal is a divide-by-four version of the input clock signal and has a duty cycle of 50%. The outputs of the other transistor stages labelled V(2) to V(5) are shown in Figures 6c to 6f. These still represent a divide-by-four version of the input clock signal, but do not have a 50% duty cycle. Thus, for applications where a 50% duty cycle is important the output signal from the divide-by-four circuit should be taken from the output of the tri-state inverter. However, for applications where it is not necessary to supply a signal with a 50% duty cycle, the output may be taken from any of the transistor stages S1 to S4. The principle of operation of the divide-by-four circuit shown in Figure 1 can readily be extended to other even numbers to provide a divide-by-M circuit, where M is an even integer. Figure 7 is a circuit diagram of a divide-by-eight circuit, which has eight transistor stages S1 to S8, each of which is of the type labelled S1 to S4 in Figure 1, and a tri-state inverter stage labelled S9 similar to the stage S5 of Figure 1. Figures 8a to 8j represent the waveforms for the circuit of Figure 7. Figure 8a shows an input signal having a 50% duty cycle applied to the divide-by-eight circuit of Figure 7. Figure 8b illustrates the output waveform for the output signal CLK OUT at the output node of the tri-state inverter stage S9. As can be seen, this has a duty cycle of 50%. Figures 8c to 8j are the output signals from the other output nodes of the stages in the ring, labelled V2 to V9. The signals at these nodes each represent a divide-by-four version of the input signal, but not at a duty cycle of 50%. Figure 9 illustrates how a programmable dividing circuit may be constructed to divide by a selected even integer M. Figure 9 illustrates a programmable dividing circuit which can selectively divide by four or six. The circuit comprises six transistor stages S'1 to S'6 and a tri-state inverter stage S'7 connected in a ring. The transistor configuration of each of the stages S'1 to S'6 is not shown in Figure 9 but is the same as for Figure 1. The tri-state inverter stage S'7 can take the form illustrated in Figure 1 or any suitable alternative tri-state inverter circuit known in the art. A multiplexer 20 has one input connected to the output of the transistor stage S'6 and another input connected to the output of the fourth stage S'4. The output of the multiplexer 20 forms the input to the tri-state inverter stage S'7. The multiplexer 20 has a select input 22 which receives a select signal SEL which controls whether the output of the sixth transistor stage or the fourth transistor stage is supplied as the input to the tri-state inverter stage S'7. It will be appreciated that any suitable multiplexer could be used to selectively supply the output of the fourth or sixth stage as the input of the tri-state inverter stage S'7. It can thus be understood that the circuit can be programmed to divide by four or six depending on the state of the select signal SEL. When the select signal SEL is low, the output of the fourth stage S'4 is supplied as the input to the tri-state inverter stage S'7 so that the ring operates as a divide-by-four ring as described above with reference to Figure 1. If the select signal cell goes high, the output of the sixth stage S'6 is supplied as the input to the tri-state inverter stage S'7 so that the ring operates as a divide-by-six ring. It is possible to change the dividing integer M "on the fly" by appropriately selecting the time at which the state of the select input is changed relative to the clock signal CLK IN. It will readily be appreciated that the principle illustrated above with respect to a programmable divide-by-four/divide-by-six circuit can be applied to any selected even numbers by appropriately selecting the transistor stages whose outputs are supplied to the multiplexer. Moreover, it is possible to construct a circuit which can selectively divide by three or more even integers by having a multiplexer with three or more inputs to which the outputs of the appropriate transistor stages are supplied. Figure 11 is a diagram of a basic phase-locked-loop circuit in which the dividing circuits described herein are particularly useful. The phase-locked-loop receives a reference clock input REF CLK IN and generates a PLL clock output PLL CLK OUT. An input divider 50 creates from the reference clock input REF CLK IN a reference input frequency for a phase detector 52. The phase detector 52 also receives as an input a feedback signal  generated in a manner described in the following. If the two inputs to the phase detector differ in phase, an error output e is generated and is supplied to a charge pump 54. A loop filter 56 shapes the output of the charge pump 54 and generates a correction signal for a voltage controlled oscillator 58. The output of the voltage controlled oscillator is passed through a feedback divider 60 to generate the second input  to the phase detector. The output of the voltage controlled oscillator is also passed through an output divider 62 to generate the clock output PLL CLK OUT. A dividing circuit in accordance with the present invention can usefully be used to implement any of the input divider 50, feedback divider 60 or output divider 62 to provide a phase-locked-loop satisfying required technology, frequency and power constraints.

Claims: A dividing circuit comprising, connected in a ring: a plurality M of transistor stages (Sn), where M is an even integer, each transistor stage (Sn) comprising an input node (In), a clock node and an output node (On); and a tri-state inverter stage (S5, S9, S'7) having an input node (2) connected to the output node of the preceding transistor stage in the ring, an enable node (6) connected to the clock nodes of the transistor stages (Sn), and an output node (4) connected to the input node of the subsequent transistor stage in the ring, wherein each transistor stage comprises a first pair of transistors (T1, T2) of a first conductivity type connected in series between a first voltage level and an output node (On); a second pair of transistors (T3, T4) of a second conductivity type connected in series between a second voltage level and said output node (On), wherein control nodes of a first transistor of each said transistor pair are connected together to provide the input node (In) for the stage, and control nodes of a second transistor of each said transistor pair are connected together to provide the clock node for the stage, whereby when an input clock signal (CLK IN) is applied to the clock nodes of the transistor stages, an output signal is generated at the output node (4) of the tri-state inverter in which each cycle represents M cycles of the input clock signal (CLK IN); characterised in that the dividing circuit (20) further comprising a switching circuit for selectively connecting one of at least two inputs (V7, V5) to an output, wherein the output nodes of at least two alternate transistor stages of the dividing circuit are connected respectively to said at least two inputs, whereby one of said output nodes is selectively connectable to the input node of a subsequent stage so that the integer M is programmable. A dividing circuit according to claim 1, wherein M is ten or less. A dividing circuit according to claim 1 or 2, wherein noninverting logic (L) is connected in the ring between any two sequential stages. A dividing circuit according to any preceding claim, wherein the first transistors of each said transistor stage are directly connected to the respective first and second voltage levels, and wherein the second transistors of each said transistor stage are directly connected between the first transistors and the output node (On) of the stage. A dividing circuit according to claim 1, wherein the first voltage level is a power supply voltage for the circuit and the second voltage level is ground. A dividing circuit according to claim 5, wherein the first pair of transistors (T1, T2) are PMOS transistors and the second pair of transistors (T3, T4) are NMOS transistors. A dividing circuit according to any one of the preceding claims, wherein the switching circuit (20) has a select input (22) for receiving a select signal (SEL) to program said integer M by selectively connecting one of said at least two inputs (V7, V5) of the switching circuit to the output of the switching circuit. A dividing circuit according to any one of the preceding claims, wherein the switching circuit has its output connected to the input node of the tristate inverter stage (S'7). A phase locked loop comprising: a phase detector (52) having a first input for receiving a reference signal and a second input for receiving a feedback signal (Q), the phase detector (52) being operable to generate an error signal (e) according to the relative phase of the reference signal and the feedback signal; a voltage controlled oscillator (58) connected to receive a signal representative of the error generated by the phase detector (52); and a dividing circuit (60) connected to receive an output from the voltage controlled oscillator (58) and to divide that output by a predetermined integer to generate the feedback signal (Q), the dividing circuit (60) being in accordance with any of claims 1 to 8. A phase-locked-loop comprising: a phase detector (52) having a first input for receiving a reference signal and a second input for receiving a feedback signal (Φ), the phase detector being operable to generate an error signal (e) according to the relative phase of the reference signal and the feedback signal Φ; a voltage controlled oscillator (58) connected to receive a signal representative of the error generated by the phase detector (52); and a dividing circuit (60) connected to receive an output from the voltage controlled oscillator (58) and to divide that output by a predetermined integer to generate the feedback signal (Φ; and an output divider (62) connected to receive the output from the voltage controlled oscillator (58) to generate a divided output signal (PLLCLK OUT), the output divider (62) being in accordance with any of claims 1 to 8. A phase-locked-loop comprising: a phase detector (52) having a first input for receiving a reference signal (REFCLK IN) and a second input for receiving a feedback signal (Φ), the phase detector (52) being operable to generate an error signal (e) according to the relative phase of the reference signal and the feedback signal (Φ); a voltage controlled oscillator (58) connected to receive a signal representative of the error generated by the phase detector (52); and a dividing circuit (60) connected to receive an output from the voltage controlled oscillator (58) and to divide that output by a predetermined integer to generate the feedback signal (Φ); and an input divider (50) for dividing the reference signal (REFCLK IN) prior to the phase detector (52), the input divider (50) being in accordance with any of claims 1 to 8.

Inventors: MONK TREVOR, MONK, TREVOR
Applicants: SGS THOMSON MICROELECTRONICS, STMICROELECTRONICS LIMITED
Application year: 1998
Main classification: H03K23
IPC codes: H03K23, H03L7