A method for forming a laminated structure of polysilicon and tungsten silicide

Abstract: A method of forming a gate electrode of a multi-layer structure comprises a step of supplying a processing gas for poly-crystal film formation and impurities of a P-type into a film formation device, to form a poly-crystal silicon layer (10) doped with P-type impurities, on a surface of a gate film (6) target, a step of maintaining the processing target in the film formation device to prevent formation of no oxide film might not be formed on the poly-crystal silicon layer, and a step of supplying a processing gas for tungsten silicide film formation and impurities of a P-type into the film formation device, to form a tungsten silicide layer (12) doped with impurities of P-type impurities, on the poly-crystal silicon layer on which no oxide film is formed.

Description: The present invention relates to a laminated structure or multi-layer structure such as a gate electrode formed on a processing target comprising a semiconductor substrate or a glass substrate, and a method of forming the same. In general, in steps of manufacturing a semiconductor integrated circuit, a desired element or elements are obtained by repeatedly performing film formation, pattern etching, and the like on a semiconductor wafer or a glass plate as a processing target. For example, referring to Figure 3A, when a gate element for a MOSFET is formed on the surface of the wafer, impurities of one conductive type are diffused into positions where a source region 2 and a drain region 4 should be formed, in a wafer W, and a gate oxide film 6 made of, for example, SiO 2 is formed on the area between the positions on the surface of the wafer while a source-drain channel is formed below the gate oxide film 6. Further, a gate electrode 8 made of a conductive film is formed on the gate oxide film 6, to form a transistor. In recent days, the gate electrode 8 does not have a single-layer structure but has a multi-layer structure and has a two-layer structure in most cases, in consideration of conductivity. For example, a gate electrode 8 is formed by sequentially layering a poly-crystal silicon layer 10 doped with phosphorus and a metal silicide layer such as a tungsten silicide layer 11, on a gate oxide film 6. In accordance with down-sizing and high-integration of a semiconductor integrated circuit in recent days, the processing line width and the gate width are narrowed more and more and the film thickness tends to be thinner and thinner in response to demands for multi-layering. Even though the line width is narrowed, it is demanded that electric characteristics of respective layers and interlayer electric characteristics should maintain conventional performances or attain higher performances. In response to such demands, the gate electrode 8 adopts a two-layer structure consisting of poly-crystal silicon 10 doped with phosphorus and tungsten silicide 11. A film made of silicon material, e.g., a poly-crystal silicon layer 10 doped with phosphorus tends to easily form a natural oxide film 14 as shown in FIG. 3B on its own surface when exposed to air, moisture, or the like. If a tungsten silicide layer 11 as a next layer is layered on the silicon layer 10 with such a natural oxide film adhered, tightness of a contact between both of the layers 10, 11 is degraded or sufficient electric conductivity cannot be maintained therebetween, resulting in a problem that the electric characteristics are degraded. Film formations of the poly-crystal silicon layers 10 are normally carried out by batch processing in which wafers are treated in units each consisting of a number of wafers, e.g., 150 wafers, while film formations of a tungsten silicide layers 11 are carried out by piece-by-piece processing in which film formations are carried out for every wafer. As a result, the time for which one wafer is exposed to air varies between wafers, and the thickness of the natural oxide film varies accordingly. Therefore, wet washing is carried out, for example, with use of HF-based paper immediately before layering the tungsten silicide layer 11, in order to remove the natural oxide film 14 sticking to the poly-crystal silicon layer 10. However, even when wet washing is carried out immediately before layering the tungsten silicide layer 11, it is very difficult to completely remove the natural oxide film 14 once adhered to the surface of the poly-crystal silicon layer 10, without affecting a subbing layer (i.e., the poly-crystal silicon layer 10) below the natural oxide film 14. In this respect, there has been a proposal of a method in which a poly-crystal silicon layer 10 doped with phosphorus is formed on a semiconductor wafer in a chamber with use of a cluster tool formed, for example, by concentrating a plurality of chambers with airtightness maintained between each other, and thereafter, the semiconductor wafer is introduced into another chamber in the same cluster tool, to form a tungsten silicide layer 11, without exposing the semiconductor wafer to air, i.e., without allowing any natural oxide film to have an opportunity to stick to the wafer (ref. Japanese Patent Application KOKAI Publication No. 9-17705). As described above, if the tungsten silicide layer 11 is sequentially formed without exposing the wafer to air after the poly-crystal silicon layer 10 doped with phosphorus is formed, no oxide film is formed on the way of the manufacturing steps, and therefore, the entire gate electrode has a low resistance. It is possible to respond to design rules strictly limited under down-sizing and high integration. In this case, however, phosphorus doped in the poly-crystal silicon layer 10 unevenly re-diffuses into the upper tungsten silicide layer 11 through an interface between both of these layers, and therefore, phosphorus is unevenly distributed near the surface of the tungsten silicide layer (e.g., between MOSFETs formed in each wafer), resulting in another problem that the electric characteristic is degraded and/or varies. Also, as a result of this, variation appears between wafers and the manufacturing yield is degraded. If only a slight portion or portions of natural oxide film can remain on the surface of the poly-crystal silicon layer 10 doped with phosphorus after wet washing is carried out to remove the natural oxide film, the slight portion or portions of natural oxide film prevent phosphorus from diffusing into the upper layer, resulting in no problems. However, when sequential film formation is carried out so that no natural oxide film is formed in response to demands for a low resistance required for down-sizing, a new problem of uneven diffusion of phosphorus as described above appears. In this respect, explanation will be made in more detail with reference to a graph shown in FIG. 4. FIG. 4 is a graph showing a resistance of a gate electrode with respect to a phosphorus density of a poly-crystal silicon layer and dependence of a variation rate of the resistance, where the longitudinal axis represents the resistance and the lateral axis represents the phosphorus density of the poly-crystal layer. In this figure, a broken line A shows a case where a tungsten silicide layer 11 is formed after the poly-crystal silicon layer 10 doped with phosphorus at a phosphorus density represented by the lateral axis is formed and is thereafter exposed to air to apply thereto a natural oxide film. A continuous line B shows a case where a tungsten silicide layer 11 is formed without exposing a poly-crystal silicon layer 10 to air after the poly-crystal silicon layer 10 is formed. In the figure, black circles show average values of resistance at phosphorus densities, respectively, and lines extending vertically from the black circles as the centers indicate a variation rate (width). As is apparent from the graph, in the case of the broken line A , the resistance is slightly high while variation of the resistance is small and uniform. Hence, it is found that diffusion of phosphorus into the tungsten silicide layer is blocked by a natural oxide film. In contrast, in the case of the continuous line B , the resistance decreases as the phosphorus density increases while the variation rate of the resistance increases much more. Hence, it is found that phosphorus unevenly diffuses into the tungsten silicide layer and this case is not preferable for characteristics. FIGS. 5A and 5B are graphs for recognizing action of phosphorus where the left longitudinal axis represents the resistance of the tungsten silicide layer, the right longitudinal axis represents the uniformity of the resistance, and the lateral axis represents a wafer number. FIG. 5A is a graph showing the sheet resistance of the tungsten silicide layer of a gate electrode with respect to 25 pieces of wafers and the uniformity thereof where a tungsten silicide layer (Wsix) 11 is formed without forming a natural oxide film on a poly-crystal silicon layer 10 doped with phosphorus. FIG. 5B is a graph showing the resistance of the tungsten silicide layer of a gate electrode with respect to 25 pieces of wafers and the uniformity thereof where the tungsten silicide layer 11 is formed without forming a natural oxide film on a poly-crystal silicon layer 10 not doped with phosphorus. In these figures, a continuous line including white circles shows the sheet resistance of the tungsten silicide layer while a continuous line including black circles shows the uniformity of the sheet resistance. Arrows are used as indications thereof. As is apparent from the graphs, in the case of doping no phosphorus into the poly-crystal layer as shown in FIG. 5B, the value of the sheet resistance is naturally constant and the uniformity of the resistance is stable. In contrast, in the case of doping phosphorus into the poly-crystal silicon layer as shown in FIG. 5A, the resistance of the tungsten silicide layer greatly changes and the uniformity of the resistance is accordingly unstable and degraded greatly. Thus, direct formation of a tungsten silicide layer 11 on a poly-crystal silicon layer 10 doped with phosphorus causes uneven diffusion of phosphorus which leads to characteristic variation and is not preferable. EP-A-0 746 027 discloses a three layer structure of an impurity doped poly-Si layer, an impurity non-doped poly-Si layer and a WSi layer. The tungsten silicide is deposited on to the poly-Si layer by transporting the substrate under vacuum from the polysilicon deposition chamber to the tungsten silicide deposition chamber. The present invention has an object of providing a multi-layer structure and a method of forming the same, capable of preventing uneven diffusion of impurities into a tungsten silicide layer as an upper layer from a poly-crystal silicon layer as a lower layer. According to a first aspect, the present invention provides a method for forming a multi-layer structure comprising the steps of: supplying a processing gas for poly-crystal film formation and first impurities of one conductive type into a film formation device, to form a poly-crystal silicon layer (10) by CVD doped with the first impurities on a surface of a device being processed (W); maintaining the device being processed in the film formation device to prevent formation of an oxide film on the poly-crystal silicon layer; and supplying a processing gas for tungsten silicide film formation and second impurities of the same conductive type as the first impurities into the film formation device to form a tungsten silicide layer (12) by CVD doped with the second impurities on the poly-crystal silicon layer. Preferably the first impurities are the same as the second impurities. It is furthermore preferred that the processing gas for tungsten silicide formation includes PH 3 gas, SiH 2 Cl 2 gas and WF 6 gas. It is further preferred that the film formation device includes a chamber in which all of said layers are formed. According to the first aspect, it is possible to obtain a multi-layer structure made of a poly-crystal silicon layer doped with impurities of a conductive type and a tungsten silicide layer (sequentially) formed on and in direct contact with the poly-crystal silicon layer and doped with impurities of the same conductive type as the above-mentioned impurities. In this case, first, the tungsten silicide layer as an upper layer is doped with impurities with uniformity, and therefore, uneven diffusion of impurities from the poly-crystal silicon layer as a lower layer can be negligibly small in comparison with the density of the impurities in the tungsten silicide layer. As a result of this, impurities are kept uniformly diffused in the tungsten silicide layer. Therefore, characteristic variations are reduced and equalized. Second, impurities of one conductive type previously doped in the upper layer or tungsten silicide layer make the upper layer to have a crystal structure, for example, amorphous structure, which may prevent or minimize rediffusion of impurities from the lower layer or poly-crystal silicon layer, so that same effects as those above mentioned are obtained. A multi-layer structure as described above is applicable to a gate electrode of an MOSFET, for example. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a view schematically showing a state where a multi-layer structure according to a first embodiment of the present invention is applied to an MOSFET; FIG. 2A is a graph showing the resistance of a gate electrode and the uniformity with respect to 25 pieces of wafers each has a structure shown in FIG. 1; FIG. 2B is a graph showing a relationship between the resistivity of tungsten silicide layer of a gate electrode of the structure shown in FIG. 1 and flow rate of impurities doped in the upper layer; FIG. 2C is a graph showing a relationship between crystallity of the upper layer shown in FIG. 1 and flow rate of impurities doped in the upper layer; FIGS. 3A and 3B are views for explaining a conventional gate electrode, wherein FIG. 3A schematically shows the structure of the gate electrode and FIG. 3B shows no oxide film formed on a poly-crystal silicon; FIG. 4 is a graph showing the resistance of a conventional gate electrode and variations thereof with respect to a doping amount of phosphorus of a poly-crystal silicon layer; and FIGS. 5A and 5B are graphs showing the resistance of a tungsten silicide layer of a gate electrode and the uniformity thereof when a lower layer is doped with impurities (FIG. 5A) and when a lower layer is not doped with impurities (FIG. 5B). In the following, an embodiment of a multi-layer structure and a manufacturing method thereof according to the present invention will be described in details below with reference to MOSFETs on the basis of appended drawings. In FIG. 1, a reference W denotes a semiconductor substrate as a processing target, e.g., a single crystal silicon wafer. A number of MOSFETs are formed on the wafer W by a known method. Each FET has a source region 2 and a drain region 4 formed apart from each other, and a gate oxide film 6 formed between both regions on the wafer and consisting of an insulating film made of SiO 2 . A gate electrode 8 is formed on the gate oxide film 6. The gate electrode 8 has a multi-layer structure constructed by a poly-crystal silicon layer 10 which is uniformly and entirely doped with first impurities of one conductive type, e.g., phosphorus (P) in case of the present embodiment, and a tungsten silicide layer 12 (WSix) which is entirely and uniformly doped with second impurities of the same conductive type as the first impurities and which is formed so as to have a direct contact with the poly-crystal silicon layer 10. The first impurities may be the same as or different from the second impurities. Note that the first poly-crystal silicon layer 10 has the same structure as the poly-crystal silicon layer shown in FIG. 3. Next, a method of forming the multi-layer structure will be explained below. Firstly, a gate oxide film 6 having a thickness of, for example, about 8-10 nm (80 to 100Å) is formed on the surface of a silicon wafer W subjected to a predetermined treatment. The gate oxide film 6 is formed by oxidation processing in which the wafer W is heated for about 10 to 30 minutes in a wet oxygen atmosphere at a temperature of about 850 to 950°C. Subsequently, a poly-crystal silicon layer 10 is formed thereon which is doped with impurities of one conductive type such as phosphorus. Further, while maintaining the processing target in the same film formation device so that a natural silicon oxide film might not be formed on the surface of the poly-crystal silicon layer, a tungsten silicide layer 12 uniformly doped with impurities of the same type as the above-described conductive type such as phosphorus is directly formed on the poly-crystal silicon layer 10. Formation of the tungsten silicide layer 12 is carried out in the same chamber as that in which the poly-crystal silicon layer 10 has formed or a different chamber in one same cluster tool device, and film formation is sequentially carried out in the same or different chamber. Sequential film formation means that a tungsten silicide layer is directly formed on a poly-crystal silicon layer so that no oxide film formed by natural oxidization is formed on the poly-crystal silicon layer. The film formation is carried out under conditions as follows. Firstly, a poly-crystal silicon layer 10 is formed to have a thickness of about 100 nm (1000Å) in a piece-by-piece film formation furnace, with PH 3 gas, SiH 4 gas, and Ar gas flowing at 55 sccm, 400 sccm, and 540 sccm, respectively. In this state, the processing temperature and the processing pressure are respectively about 660°C and about 1 kPa (7.5 Torr). Next, a tungsten silicide layer 12 doped with phosphorus is also formed to have a thickness of about 100nm (1000Å) in the piece-by-piece film formation furnace, with PH 3 gas, SiH 2 Cl 2 gas, WF 6 gas, and Ar gas flowing at 5 sccm, 150 sccm, 6.0 sccm, and 350 sccm, respectively. In this state, the processing temperature and the processing pressure are respectively about 630°C and about 95 Pa (700 mTorr). Further, the layers 10 and 12 are subjected to pattern etching by means of a conventional lithography technique and a conventional etching technique, and impurities are selectively injected into the silicon wafer W by means of a self-alignment technique, to form source and drain regions 2 and 4. A number of MOSFETs as described above are formed at once on the wafer. The gate electrode 8 is thus constructed to have a multi-layer structure constructed by the poly-crystal silicon layer 10 doped with phosphorus and the tungsten silicide layer 12 also doped with phosphorus. In case of performing a heat treatment in a successive manufacturing step, even if phosphorus in the poly-crystal silicon layer 10 as a lower layer unevenly diffuses into the tungsten silicide layer 12 as an upper layer in a successive heat treatment step, the unevenness of such phosphorus does not substantially affect phosphorus uniformly diffused in the tungsten silicide layer 12, because the tungsten silicide layer 12 as an upper layer has been uniformly doped with phosphorus as impurities. Specifically, phosphorus as impurities in the tungsten silicide layer 12 maintains a uniform distribution, so that the resistance value is uniform in plane and therefore does not vary. It will be easily understood that this effect is increased as the amount of impurities previously doped uniformly in the tungsten silicide layer 12 increases. FIG. 2A is a graph showing the sheet resistance of a gate electrode and the uniformity thereof when 25 pieces of wafers are processed under the film formation conditions as described above. Note that the values of this graph are obtained after film formation. FIG. 2B shows that the bulk resistivity of the tungsten silicide layer decreases according to increase of flow rate of PH 3 , that is, an impurity concentration in the tungsten silicide layer. FIG. 2C shows that crystallity of the tungsten silicide layer reaches an amorphous state as the flow rate of PH 3 increases. For example, when the flow rate is 300 sccm, the crystallity almost shows an amorphous state. From Fig. 2A, it is found that each wafer has an excellent resistance uniformity of about 2% and does not have characteristic variation, leading to an excellent result. In contrast, in case where phosphorus is not doped in the upper tungsten silicide layer 12, the uniformity of the resistance of the gate electrode is about 25% as shown in FIG. 5A and the characteristic variation is thus large, resulting in that the electric characteristic is greatly degraded. Thus, by previously doping uniformly impurities into the upper tungsten silicide layer 12, it is possible to eliminate bad influences from impurities of the lower poly-crystal silicon layer 10. Here, the density of impurities in each layer is measured by an SIMS (Secondary Ion Micro Scope). The phosphorus density of the lower poly-crystal silicon layer 10 is an order of substantial 10 20 atms/cc while the phosphorus density of the upper tungsten silicide layer 12 is an order of substantial 10 19 atms/cc and is thus smaller by one figure than that the lower layer 10. The phosphorus density of the tungsten silicide layer 12 is not limited to the density described above as long as the phosphorus density can cancel influences from diffusion of phosphorus in the lower poly-crystal silicon layer 10. However, it will be easily understood that this effect is increased as the amount of impurities previously doped uniformly in the tungsten silicide layer 12 is increased. Although a white turbidity is viewed with eyes on the surface of the wafer shown in FIG. 5A and the morphogy is thus degraded, no white turbidity is confirmed in the present embodiment and the morphogy is thus improved. In the embodiments described above, explanation has been made with reference to a case where phosphorus is doped as impurities of one conductive type. Impurities are not limited thereto but other impurities such as B, As, Sb, or the like are naturally applicable. In addition, one same kind of impurities needs not be used for every layer, but impurities having one same conductive type may be doped, e.g., As or Sb may be doped as impurities with respect to P. It is apparent that the multi-layer structure is applicable not only to a gate electrode as described above but also to other electrodes, leads, or other structures which require a conductivity.

Claims: A method for forming a multi-layer structure comprising the steps of: supplying a processing gas for poly-crystal film formation and first impurities of one conductive type into a film formation device, to form a poly-crystal silicon layer (10) by CVD doped with the first impurities on a surface of a device being processed (W); maintaining the device being processed in the film formation device to prevent formation of an oxide film on the poly-crystal silicon layer; and supplying a processing gas for tungsten silicide film formation and second impurities of the same conductive type as the first impurities into the film formation device to form a tungsten silicide layer (12) by CVD doped with the second impurities on the poly-crystal silicon layer. A method according to Claim 1, wherein the first impurities are the same as the second impurities. A method according to Claim 1 or Claim 2, wherein said processing gas for tungsten silicide film formation includes PH 3 gas, SiH 2 Cl 2 gas and WF 6 gas. A method according to any preceding Claim, wherein the processing gas for poly-crystal film formation includes PH 3 gas and SiH 4 gas. A method according to any preceding Claim, wherein said film formation device includes a chamber in which all of said layers are formed.

Inventors: HASHIMOTO TSUYOSHI, KOIZUMI MASATO, MATSUSE KIMIHIRO, OKUBO KAZUYA, TAKAHASHI TSUYOSHI, HASHIMOTO, TSUYOSHI, KOIZUMI, MASATO, MATSUSE, KIMIHIRO, OKUBO, KAZUYA, TAKAHASHI, TSUYOSHI
Applicants: TOKYO ELECTRON LTD, TOKYO ELECTRON LIMITED
Application year: 1998
Main classification: H01L21
IPC codes: H01L21, H01L29, H01L23