THERMAL INFRARED DETECTOR

Abstract: An infrared detector includes a first thermal insulation layer (14) disposed between an etch stop layer (20) and an active substrate (10). The first thermal insulation layer is a xerogel, and is preferably an aerogel. A pixel having at least a lower electrode (26) and an upper electrode (26) with a thermal imaging element (24) disposed therebetween is constructed above the etch stop layer. Preferably direct thin film deposition techniques are used for the thermal imaging element, which in turn is preferably a pyroelectric material. The etch stop layer protects that portion of the first thermal insulation layer which underlies the pixel to enhance the performance of the pixel and detector incorporating the same, during etching to further define the thermal imaging element and/or expose the lower electrode. Encapsulation of the detector may be used to protect the same from the environment. In one embodiment this is affected through a silicon nitride layer (69), an oxy-nitride layer (68) disposed between this silicon nitride layer and the pixel.

Description: THERMAL INFRARED DETECTOR Related Applications This patent application is a continuation-in-part of U.S. Patent Application Serial No. 08/912,949, entitled "Uncooled Thin Film Pyroelectric IR Detector With Aerogel Thermal Isolation", and filed on August 14, 1997, the entire disclosure of which is incorporated by reference in its entirety herein. Field of the Invention The present invention generally relates to infrared detectors and, more particularly, to thermal infrared detectors which are uncooled. Government Rights This invention was made with United States Government support under Contract No. DE-AC04-94AL85000 awarded by the U.S. Department of Energy. The Government has certain rights in this invention. Background of the Invention Infrared detectors include both photon and thermal detectors. Photon detectors (e.g., PtSi available from Honeywell and CdTe available from Raytheon) can offer good sensitivity, fast response times, high spatial resolution, and low cost if standard semiconductor processing technology can be used. However, these detectors are sensitive to thermal noise effects and must be cryogenically cooled. The cooling units are expensive and cumbersome, making photon detectors impractical for most consumer and military applications. In addition, semiconductor infrared detectors suffer from pixel-to-pixel signal variations that make signal processing necessary in order to obtain < 1 °C resolution. The process of mathematically normalizing the signal from each pixel reduces the signal- to-noise ratio of the array. Thermal detectors, like pyroelectric imaging elements, offer excellent performance at room temperature and do not require cooling. They are suitable for small, light-weight detection systems that are reliable and require minimal power. Until now, these detectors have been difficult and costly to fabricate. The pyroelectric imaging elements manufactured at Texas Instruments consist of a laser reticulated barium strontium titanate (BST) ceramic that has been flat-lapped to a thickness of < 20 μm and then bump-bonded to an integrated circuit. The lapping process is wasteful and time-consuming, and the bonding process often leads to breakage of the very delicate BST ceramic. Therefore, the technical problem with these detector elements is that throughput is low and cost is high ($2500/detector array). In addition spatial resolution is limited (48 μm pixel size) because of the difficult bump-bonding process. Summary of the Invention A first aspect of the present invention relates to a thermal infrared detector which includes a substrate having a first semiconductor device. A first thermal insulation layer is disposed in overlaying relation with at least a portion of the substrate. "Overlaying" as used herein means that the first thermal insulation layer (or any other layer characterized as being "overlaying") is disposed directly above at least a portion of the substrate (or any other layer characterized as being "overlayed" or the like) (as opposed to being located at a "higher" elevation, but off to any one side), either directly thereon or with one or more intermediate layers therebetween. This first thermal insulation layer is xerogel, and more preferably is aerogel. Overlaying at least a portion of this first thermal insulation layer is a first etch stop layer in that the first etch stop layer is disposed directly above at least a portion of the first thermal insulation layer. Protection against at least certain processing of the thermal detector after the formation of the first thermal insulation layer is provided by this first etch stop layer. The thermal infrared detector of the subject first aspect further includes a first pixel. Components of the first pixel include a thermal imaging element which is at least partially disposed between lower and upper electrodes, and further which is formed of a ferroelectric material, and more preferably a pyroelectric material. The first pixel overlays at least a portion of the first etch stop layer in that the first pixel is disposed directly above at least a portion of the first etch stop layer. An appropriate electrical interconnection is provided between the first pixel and the first semiconductor device. The first aspect of the present invention is subject to further definition. Any one or more of the following features may be used in any combination with the first aspect as described above: 1 ) an oxide layer, such as thermal oxides or deposited oxides, may be disposed between the substrate and the first thermal insulation layer to protect the first semiconductor device and other active portions of the substrate from processing relating to one or more other parts of the detector, and in one embodiment this oxide layer is silicon dioxide; 2) a porosity of the first thermal insulation layer may be at least about 20%, more preferably at least about 80%, and typically within a range of about 80% to about 95%; 3) a planarization layer such as silicon dioxide or TiO 2 may overlay at least a portion of and interface with the first thermal insulation layer to provide a suitable surface on which the first pixel may be disposed; 4) direct thin film deposition techniques may be used to form the ferroelectric material layer from which the thermal imaging element of the first pixel is formed so as to avoid the bump-bonding techniques employed by many prior art thermal infrared detectors; 5) the first thermal insulation layer, at least that which is disposed directly below the thermal imaging element of the first pixel, may be protected from any etching employed in relation to the thermal imaging element by the first etch stop layer; 6) the integrity of the first thermal insulation layer may be preserved by selecting only those ferroelectric materials which may be crystal I ized/pyrolyzed through heating the ferroelectric material to a temperature of no more than about 650° C after being deposited on/above the lower electrode; 7) the thermal imaging element may employ a low heat mass to enhance the performance of the detector, such as by having a thickness of no more than about 0.5 micrometers at least for that portion of the thermal imaging element which is disposed directly above the lower electrode of the first pixel; 8) the thermal imaging element of the first pixel may be sized such that no dimension thereof is greater than about 4 micrometers, specifically the dimensions of that portion of the thermal imaging element on which wavelengths of light impact for development of an image therefrom; 9) a second thermal insulation layer may be utilized, such as xerogel and more preferably aerogel; 10) the noted second thermal insulation layer may be disposed over at least the first pixel and the first semiconductor device; 11) the noted second thermal insulation layer may be disposed in at least a portion of the area between the first pixel and the first semiconductor device; 12) the noted second thermal insulation layer may be disposed between the first pixel and another similarly configured pixel of an array in which the first pixel is utilized to provide interpixel thermal insulation to enhance the performance of the detector/array; 13) the noted second thermal insulation layer may have the same characteristics/properties as the first thermal insulation layer; 14) a scratch protection layer such as silicon dioxide may be disposed in overlaying relation with at least the first pixel and the first semiconductor device, and preferably over the entirety of any array which includes the first pixel; 15) an encapsulation layer may be disposed in overlaying relation with at least the first pixel and the first semiconductor device, and preferably over the entirety of any array which includes the first pixel, and a barrier layer may be disposed between the encapsulation layer and these structures to protect the same from processing which may be used in relation to the encapsulation layer (e.g., using an oxy-nitride barrier layer to protect the thermal imaging element of the first pixel from processing required to apply a silicon nitride encapsulation layer); 16) a plastic encasement may be provided for enclosing the thermal detector; 17) the detector may have a noise-equivalent-temperature- difference of no more than about 0.07°C, and more preferably no more than about 0.05°C, with the NETD being that temperature change on the detector which is required to produce a signal-to-noise ratio of "1"; 18) a fully monolithic/integrated system is available with the thermal infrared detector being assembled entirely on the underlying, active substrate; 19) techniques which are at least compatible with conventional semiconductor processing techniques may be employed to form the entire thermal infrared detector; and 20) the detector may be incorporated in a thermal imaging system whose readout circuitry causes the system to function as a bolometer (which is based upon measuring a change in resistance of a ferroelectric material, such as a pyroelectric, which is in turn based upon a change in temperature), or a pyroelectric detector (which is based upon measuring current flow as a function of a change in capacitance, which in turn is due to a change in temperature). A second aspect of the present invention relates to a thermal infrared detector which includes a substrate having a first semiconductor device. A first thermal insulation layer is disposed in overlaying relation with at least a portion of the substrate in that the first thermal insulation layer is disposed directly above at least a portion of the substrate. Overlaying at least a portion of this first thermal insulation layer is a first pixel. Components of the first pixel include a thermal imaging element which is at least partially disposed between lower and upper electrodes and further which is formed of a ferroelectric material, more preferably a pyroelectric material. An appropriate electrical interconnection is provided between the first pixel and the first semiconductor device. Encapsulation is provided with a barrier layer being disposed between an encapsulation layer and the first pixel so as to protect the same from processing which may be required in association with the application of the encapsulation layer. In the case where the first pixel is part of an array preferably of similarly configured pixels, these encapsulation and barrier layers would typically overlay the entirety of the array. The second aspect of the present invention is subject to further definition, and any one or more of the features discussed above in relation to the first aspect may be used in any combination with this second aspect as well. A third aspect of the present invention relates to encapsulation, such as of the type addressed in relation to the second aspect. A substrate includes a first semiconductor device, and possibly other semiconductor devices and/or integrated circuits. A dielectric material layer overlays at least a portion of the substrate, and typically only a portion of the substrate. One or more layers may be disposed between the dielectric material layer and the substrate, such as those discussed above in relation to the first and second aspects. Moreover, the dielectric material layer may be the thermal imaging element of a thermal detector, or may be a memory element of a memory device. Encapsulation of the device is provided with a barrier layer being disposed between an encapsulation layer and the dielectric material layer so as to protect the same from processing which may be required in association with the application of the encapsulation layer. One or more layers may be disposed between the barrier layer and the dielectric material layer. In one embodiment, the barrier layer is an oxy-nitride and the encapsulation layer is silicon nitride. In another embodiment, a plastic encasement encloses the structure as described. Brief Description of the Drawings Fig. 1 is a cross-sectional view of one embodiment of the structure of the detector. Fig. 2 is a graph showing the thermal conductivity of aerogels as a function of the % porosity. Figs. 3A, 3B and 3C are cross-sectional views of three other embodiments of the structure of the detector. Fig. 4 is a graph showing hysteresis loops for PZT on various substrates. Fig. 5 shows a schematic for a prior art uncooled infrared pyroelectric device that uses microbridge technology to thermally isolate the imaging element from the substrate. Fig. 6 is a cross-sectional view of a single imaging pixel in a fully integrated, 2- dimensional array embodiment of the present invention. Figure 7 illustrates a plurality of pixels which define an array of a monolithic thermal infrared detector. Figure 8 illustrates the detector of Figure 7 in a plastic encasement or package. Figures 9A-P illustrate a method for making a pixel of a monolithic thermal infrared detector. Figure 10 illustrates two adjacently disposed pixels of the type which may be made by the methodology presented in Figures 9A-P. Figure 11 illustrates an encapsulated memory device. Detailed Description By way of initial summary, one or more aspects of the present invention avoids the problems of the prior detectors by employing a novel structure in conjunction with standard silicon processing techniques to achieve better performance and much lower cost. This new IR detector is built upon a silicon substrate (on which could also be combined other microelectronic elements) on which a thermal oxide is grown. Above the oxide is formed an aerogel layer to provide thermal insulation. Above this is deposited a layer of a material that serves to planarize the aerogel in order to provide a smooth and flat surface for the remaining depositions. Next is emplaced a lower electrode layer with the thin film pyroelectric layer deposited above that. On top of the structure is the upper electrode layer capped by a blacking layer to enhance the capture of thermal radiation into the detector at the appropriate wavelengths. The pyroelectric imaging element of one or more aspects of the present invention is much thinner and has a lower thermal mass than the bulk ceramic imaging elements (BST) discussed above. The heat capacity of the thin film imaging element is smaller, resulting in faster response times (20-50 times faster) and larger voltage responses. The response time is a function of thermal mass (and volume). The thickness of the total stack of the present invention is about 0.4-1.0 μm as opposed to about 20 μm for the Texas Instruments device. The noise equivalent temperature difference (NETD) of the present detector is 0.05°C compared to 0.1 °C in the Texas Instruments product, indicating a 100% increase in the signal-to-noise ratio. In addition, the aerogel layer in the present detector acts as an effective thermal isolation barrier between the imaging element and the relatively massive heat-sinking substrate. Effective thermal isolation enables the pyroelectric element to achieve the maximum thermal and temporal resolution for the imaging device. The use of an aerogel layer also results in greater thermal insulation and easier fabrication than the self-support "microbridge" structures currently being investigated. The use of aerogel thin films for thermal insulation may become the easiest, least expensive, and most reproducible fabrication method for the preparation of thin film pyroelectric arrays as a direct result of this technology. The fully integrated design of the present uncooled IR detector enables mass production using semiconductor processing technology. This results in excellent spatial resolution (4 μm pixel size) at a greatly reduced cost (estimated about $10). Integrated ferroelectric thin films possess several attractive qualities for use in uncooled infrared (IR) pyroelectric imaging arrays. The high pyroelectric coefficients [p(nC/cm 2o K) = dP/dTJ and small thermal masses of these films, which may integrated on silicon at low temperatures, enable efficient thin film arrays for infrared imaging applications. Critical factors for pyroelectric imaging applications including the pyroelectric current, response time, and noise equivalent temperature difference (NETD) of an imaging array are listed in Table 1. For device applications, high sensitivity may be expressed as a low noise equivalent temperature difference (NETD), indicative of the approximate temperature variation due to system noise. Since NETD scales as the square root of substrate thermal conductance G, thin film pyroelectric pixels require thermal isolation from the device substrate. Several groups are pursuing micromachined ferroelectric thin film structures suspended above a substrate like that in Fig. 5, utilizing the relatively low thermal conductivity of air to achieve such thermal isolation and increased device sensitivity. TABLE 1 Selected pyroelectric imaging factors An alternative approach is presented here: use of aerogel thin films to achieve thermal isolation, but in a monolithic structure, avoiding potential complications associated with the micromachining of suspended or cantilevered devices. Silica-based aerogels, typically characterized by 70-99% porosity of a ~ 10 nm silica framework with ~ 50 nm pores, possess thermal conductivities lower than air (Fig. 2), spurring interest in use for a variety of thermal isolation applications. Recently, Brinker and co-workers demonstrated aerogel thin film deposition, whereby 0.4-2 μm thickness aerogel films with up to 98% porosity may be rapidly deposited by dip coating or spin coating onto silicon wafers, enabling use of aerogel thin films as thermal isolation interlayers within a multilayer thin film structure (S. Prakash, C.J. Brinker, A.J. Hurd, and S. Rao, "Silica aerogel films prepared at ambient pressure by using surface derivatization to induce reversible drying shrinkage," in Nature 374, 439-443 (1995). Aerogel thin films were deposited by dip coating on 3" silicon wafers, following the procedure outlined by Prakash et al., supra. This procedure comprises, in brief, preparing the silicate sols, aging the sols, conducting a pore fluid washing procedure, derivatizing the surface hydroxyl groups with trimethylsilyl groups, re-liquefying the gel with using ultrasound, dip-coating the substrate. The resulting aerogel layer has a porosity of about 60% which is then increased to over 90% by pyrolizing the aerogel for about an hour at about 450 °C. Although the aerogel used here was based on Si0 2 , a variety of other ceramics could be considered as candidates, although the silicon-based aerogel would appear to be preferred due to its similar chemistry to the Si microelectronic processing associated with the sensor. In more detail, the aerogel films are prepared by the following process. The basic starting chemicals or solutions for the preparation of the gel are the stock solution, ethanol and the base catalyst which is Ammonium Hydroxide (NH 4 OH) in this case. Preparation of "Stock" Solution (volumes may be multiplied) Volume Approximate molar ratio 61 ml Tetraethoxysilane 1 61 ml absolute ethanol 4 4.87 ml deionized water 1 0.2 ml 1 M HCl 0.007 Add chemicals to the reaction kettle in the order listed. Seal, assemble condenser, and heat to 60°C, 1.5 hrs (90 min.), with stirring. Cool, store in closed bottle in flammable- approved refrigerator or freezer if possible. Solution is stable indefinitely at 20°C. Preparation of the gel. Warm the stock solution after taking it out of the freezer and add 0.05 M NH 4 OH to promote gelation. The volume ratio of the stock solution: base: ethanol is 10:1 :44. For 10 ml of the stock solution, one needs to add 1 ml of base and .44 ml of ethanol. Thus, typically 55 ml of gel is prepared before proceeding to subsequent stages of the process. Then the gel is aged at 50°C in the aging oven for 4 days (note that this 4 days of time includes the gelation and aging time which are approximately 2 days each). Now, the gel is ready for the pore fluid exchange washes. Pore Fluid Exchange. The gel is washed three times in three hours with surplus ethanol (surplus implies typically around 60-70 ml for 55 ml of gel) at 50°C. Then it is washed two times in four hours with surplus hexane at 50°C. Now, the gel is ready to undergo surface derivatization which is the essence of the springback phenomenon which contributes to the high porosity of these films. Surface Derivatization. The surface derivatization is done with Trimethylchlorosilane (TMCS) in Hexane. Typically 5 volume % of TMCS is taken in Hexane (for example 5 ml of TMCS added to 95 ml of Hexane). The gel is kept soaked in this surplus silylating solution for about 20 hours also at 50° C. After the derivatization is over, the gel is washed depending on what would be the final solvent. If the final solvent is hexane, it is just washed two times with surplus hexane in two hours but if the final solvent is ethanol, it is washed once with surplus hexane in one hour followed by two times with surplus ethanol in two hours. The stock solution can be stored indefinitely at this point and removed when one desires to proceed with deposition on a particular wafer. Sonication. This involves the breaking up of the gel using ultrasound vibrations. As soon as all the washes are over, some amount of the final solvent is added additionally to the wet gel and the gel is broken down ultrasonically. A redispersed sol results from which one can obtain films using different coating techniques such as spin and dip coating. The final steps (after surface derivatization) include: Sonication (20-25 minutes); Spin coating (30 minutes); and Pyrolyzing (1 hour at 450° C). Total time including upramp and downramp is about 2.5 hours. This particular process employs dip coating and results in a film of about 3.5 μm thickness. Preferably the thickness of the aerogel is probably somewhat less at about 1 -2 μm thickness with a porosity of greater than about 70%. The uniformity of dip coated films is typically less than for spin coated films. However, when the above process was used in spin coating the aerogel, there were problems relating to the volatility of the solvents used and striations in the film. The high volatility of the hexane produced uneven drying because of the severe temperature and concentration gradients in the spin coating process. It was decided to substitute heptane for hexane in the pore fluid exchanges, the surface derivatization, and the post-derivatization washes. This has resulted in a striation- free film of about 0.90 μm thickness and refractive index of about 1.07 which corresponds to a porosity of about 83%. The maximum thickness variation is less than about 10%. Experimentation continues to achieve thicker films with the spin coating process. As-deposited aerogel thin films of thickness 0.4-1.2 μm were electroded by RF sputtering subsequent layers of Ti0 2 (600A), Ti (300A), Pt (2000A), and LSCO (600A). Ti promoted adhesion of the Pt layer, and LSCO was found to aid in reducing the crystallization temperature of PZT layers. Use of a lower crystallization temperature increases the survivability of the underlying aerogel layer. The electrode/aerogel/silicon stack was annealed at 550° C for 30 minutes to crystallize the LSCO (La 05 Sr 05 CoO 3 ), which is typically amorphous as-sputtered. PZT thin films were deposited by solution deposition using a methanol-based "inverted mixing order" (IMO) metal acetate/metal alkoxide system described in detail in R.W. Schwartz, R.A. Assink, and T.J. Headley, "Spectroscopic and Microstructural Characterization of Solution Chemistry Effects in PZT Thin Film Processing," in Ferroelectric Thin Films II, Mat. Res. Soc. Symp. Proc. 361 , 377-387 (1995). Solutions of 0.4M concentration spin coated at 3000 rpm reproducibly deposit 100 nm thick PZT films with high quality on substrates such as platinized silicon. For deposition on the electroded aerogels, however, modifications were necessary to address film stress and electrode smoothness issues. Typically, multiple layers of 0.1 M solutions were spin coated on the electroded aerogel substrates, with hot plate treatments to 300 °C between each layer, and crystallization at 550°C for 30 minutes every third layer. Films of 100-400 nm thickness were produced by repeating this cycle. Films so processed were top electroded with shadow masked, sputtered Pt electrodes (100 nm), and electrically characterized for dielectric and ferroelectric properties using a Hewlett Packard 4284A precision LCR meter and a Radiant Technologies RT-66A test unit, respectively. Pyroelectric measurements were obtained using the Byer-Roundy method, using a computer-controlled Signatone hot stage for linear heating and cooling ramp rates, and a Keithley 236 source measure unit to monitor current. Samples were poled at 300kV/cm for 30s, and held 15 minutes after poling before pyroelectric measurement. Pyroelectric measurements were repeated three times on heating and cooling to avoid any current transients associated with the film poling process. A composite PZT//LSCO//Pt//aerogel/silicon structure was fabricated by this process. The 400 nm PZT film was produced by firing at 550°C for 30 minutes on the electroded 0.4 μm aerogel film. The PZT film is characterized by a 0.3 μm grain size and appears to be single phase Pb(Zr 04 Ti 06 )O 3 , without evidence of pyrochlore or fluorite phases. The fine grain size suggests monodomain PZT grains may result, which would be advantageous if orientation may be controlled. Initial use of 0.4M solutions to deposit 100-400 nm PZT layers on the electroded aerogels gave rise to low yields and extensive shorting of PZT film capacitors. Before PZT deposition, the LSCO//Pt//aerogel//Si substrates appeared to exhibit long-range surface roughness suggested by diffuse reflection of background light. While AFM measurements indicated ~ 10 nm surface roughness, a longer range was suspected due to this diffuse appearance and the ~ 50 nm porosity typical of aerogels. Following the concept of other solution-deposition work used to planarize rough surfaces (see A.S. Holmes et al., "Fabrication of buried channel waveguides on silicon substrates using spin-on glass", Applied Optics 32(25), 4916 (1993)), multiple thin coatings of PZT were deposited by use of more dilute 0.1 M solutions. Individual layers were heated on a hot plate to 300° C between depositions, and crystallized by heating to 550°C for 30 minutes after every 3-4 layers. After 3-6 depositions (100-200 nm) of these PZT thin layers, the films exhibited little specular scattering, and displayed 80-100% pixel yields. Individual heat treatment of thinner layers is also believed to minimize tensile stress accumulation above the aerogel, as layers undergo less densification on each heat treatment. Ferroelectric properties of these thin films on LSCO//Pt//aerogel//Si substrates were compared with identically-processed PZT layers deposited on LSCO//Pt//Si substrates and LSCO//Pt//MgO substrates to gain an understanding of substrate stress effects on ferroelectric properties. It has been observed that PZT films deposited on high thermal expansion coefficient oxide substrates such as MgO and AI 2 O 3 are in compressive stress on cooling to room temperature, inducing c-axis orientation and square hysteresis loops with a large P r . In contrast, films deposited on platinized silicon substrates are typically in tensile stress, with a-axis orientation and less square hysteresis loops. It was hoped in the current research that use of an aerogel thin film might elastically decouple the film from the substrate, resulting in enhanced ferroelectric and pyroelectric properties. Hysteresis loops for 200 nm layers of Pb(Zr 04 Ti 06 )O 3 on the MgO, aerogel, and silicon substrates are shown in Fig. 4. While some modest stress decoupling may be responsible for the shape of the hysteresis loop on the aerogel, the overall shape is more akin to PZT in tensile stress on silicon. Thin film x-ray diffraction indicated the film to be dominantly a-axis oriented atop the aerogel, further confirming this possibility. Future research will investigate whether decoupling may be achieved for individually etched 50 μm pixels, rather than the coherent film on a 3" wafer investigated here. Pyroelectric measurements were obtained for a variety of PZT-based compositions on platinized silicon and MgO, and for Pb(Zr 04 Ti 06 )O 3 on the aerogel structure. Pyroelectric measurements, voltage figures of merit, and calculated NETD values for several compositions are shown in Table 2. Films of Pb(Zr 04 Ti 06 )O 3 on the electroded aerogel displayed a pyroelectric coefficient of 30 nC/cm 2 °K, and a calculated NETD of 0.07°C, assuming f/1.0 optics, G = 5x10 8 W/K thermal conductance, and a 50 μm pixel size. The thermal conductance value used, typical of air-gap structures, is probably conservative, since aerogels enable potentially even lower thermal conductivity. Measurements of actual thermal conductivity and conductance for aerogel structures are in progress. Several other PZT compositions appear to show promise for achieving similar NETD values. As discussed earlier, deposition of films on sapphire and MgO substrates has been observed to produce c-domain oriented films, with predicted greater pyroelectric coefficient as well. This appears to be the case for the highest pyroelectric coefficient observed to date, 71 nC/cm 2o Kfor PLZT 5/30/70 on platinized MgO, on first heating after the poling process. While results on first heating occasionally produce exaggerated pyroelectric current values, ostensibly related to post-poling phenomena, an NETD value of 0.04°C was calculated for this composition. All other values in Table 2 are from second and third heating cycles, with good agreement to respective values on cooling. 'measured on first heating of film Pyroelectric properties were measured for several compositions of pure, lanthanum- doped, and tantalum-doped PZT, often based on PZT 30/70 or 40/60, since they allow low temperature (550°C) crystallization. This property is expected to be advantageous for compatibility with integrated circuit metallization layers, as well as the aerogel film. The maximum aerogel processing temperature is near 600°C, above which the aerogel rapidly densifies, losing its thermal isolation properties. Ferroelectric properties of Pb(Zr 04 Ti 06 )O 3 were essentially the same for processing at either 550°C or 600°C, with only a mild increase in P r from 28μC/cm 2 to 30.5μC/cm 2 . What follows is a listing of the process steps that can be used to produce one embodiment of the uncooled IR detector of this invention as shown in Fig. 1. For elements above the blacking agent, reference should be made to Fig. 6. 1. Process the silicon substrate 10 through a standard semiconductor process flow up until the process step where the first metallization is deposited. The gate of the transistor can be made from a doped polysilicon. Doped polysilicon will withstand the thermal cycling required to crystallize the ceramic/pyroelectric thin film. 2. A 1 μm layer of SiO 2 12 is deposited as a protective layer on top of the underlying transistors/circuitry. 3. Deposit an aerogel thermal insulating layer 14 on the protective dense Si0 2 . The aerogel is deposited by a sol-gel deposition technique and is ~ 0.4 μm thick. 4. Deposit a dense SiO 2 layer 16 on the aerogel to encapsulate and planarize the aerogel. This can be achieved by RF sputtering. The dense layer is ~ 200 A to 400 A thick. Alternatively, a lower porosity solgel could be used. 5. On the dense SiO 2 layer deposit a ~ 1000 A of Ti metal by sputter deposition or e-beam evaporation. The Ti will become an etch stop 18 for a subsequent processing step. When the PZT is etched the aerogel will also be etched without the etch stop. 6. Pattern and etch Ti metal layer to yield Ti metal pads. There are several dry and wet etchants for Ti metal. One wet etchant is dilute H 2 O 2 . 7. Oxidize the Ti metal to TiO x 20. 8. Using a lift-off technique pattern the bottom electrode stack for the pyroelectric element. This includes a quick exposure to an O 2 plasma to remove any residual organic material for the vias. 9. Deposit a glue layer 20 for the pyroelectric metal stack. This typically is 500 A of Ti metal. 10. Deposit 1000 A of Pt by sputtering. 11. Deposit 1000 A of LSCO by sputtering Steps 8, 9, 10 can be executed at the same time. The Pt and LSCO together form the lower electrode 22. 12. Finish the patterning by removing the excess material and photoresist with an ultrasonic acetone rinse. 13. Deposit the pyroelectric ceramic thin film ~ 1 μm 24 by a sol-gel process. 14. Pattern and etch the ceramic pyroelectric material 24. The etchant is 6 to 1 BOE + 3HCL + HNO 3 + 10 H 2 O. 15. Using a lift-off technique, pattern the top electrode stack for the pyroelectric element. This includes a quick exposure to an O 2 plasma to remove any residual organic material for the vias. 16. Deposit 1000 A of LSCO by sputtering Steps 8, 9, 10 can be executed at the same time. 17. Deposit 1000 A of Pt by sputtering. The LSCO and the Pt form the upper electrode 26. 18. Deposit the blacking element 28. Steps 16, 17, 18 can be deposited at the same time. 19. Finish the patterning by removing the excess material and photoresist with an ultrasonic acetone rinse. 20. Deposit 1 μm of SiO 2 aerogel 60 to thermally isolate the pixels in the lateral dimensions and to serve as a protective coat. 21. Pattern and etch the SiO 2 to expose the contact to the top and bottom electrode for the pyroelectric structure. 22. Deposit 500 A TiN metal 62 as a barrier metal between the Al 64 and pyroelectric metal contact. 23. Pattern and etch vias to the source, gate, and drain. This can be accomplished by a CF 4 Plasma Etch. 24. Remove Photoresist using a standard resist strip. 25. Deposit Al 64 to make contact to the pyroelectric electrode stack and semiconductor structures (W, TiW or Cu can also be used). 26. Pattern and etch the Al 64 metal. 27. Remove Photoresist using a standard resist strip. 28. Deposit ~2 μm SiO 2 66 layer as a scratch protection. 29. Deposit 500 A of Oxy-nitride 68. 30. Deposit 2000 A of Si 3 N 4 as an encapsulation 69. 31. Pattern and etch the SiO 2 and Si 3 N 4 to expose bonding pads. 32. Remove Photoresist using a standard resist strip. 33. Saw wafer and package. The alternative structures shown in Figs. 3A, 3B and 3C differ in the details of making the transition between the top of the aerogel film layer and the base of the pyroelectric imaging layer. In all of these structures, the desired outcome is to be able to present a planar surface for the deposition of the layers above the aerogel to allow them to perform optimally. The problem is that the upper surface of the aerogel layer is quite rough. In Fig. 3A, the Ti adhesion layer 20 has been omitted. In some cases this will result in better adhesion between the layers. In Fig. 3B, a much thicker (-1000 - 5000A) TiO 2 is used both as the etch stop and as the planarization layer (instead of the SiO 2 in Fig. 1). This variation is also used in the structure shown in Fig. 6. In Fig. 3C, the much thicker Ti0 2 layer 36 substitutes for layers 16, 18 and 20 in Fig. 1. It is often advantageous to omit the Pt thin layers in the electrodes to avoid the risk of Pt hillock formation and also to reduce the number of process steps. The pyroelectric thin film imaging element (0.1 -2 μm thick) is composed of a material that is selected on the basis of its pyroelectric response over the operational temperature range (about 0 - 40°C) of the sensor and include barium strontium titanate (BST: Ba 1-x Sr x TiO3), lead scandium tantalate (PST: lead lanthanum titanate (PLT: and lead lanthanum zirconate titanate (PLZT: The pyroelectric response can be optimized by changing the compositions of these material systems. Deposition and processing of these thin film materials at temperatures up to 650°C does not affect the underlying silica aerogel thin film detrimentally. Thinner films give higher resolution. The pyroelectric response of a material is dependent upon the change in spontaneous polarization and dielectric constant with respect to temperature (dP s /dT and dε/dT respectively). These quantities can be measured accurately and correlated with the compositions, thicknesses, and depositions and processing parameters of the integrated structure. This iterative process allows one to adjust the design and fabrication techniques to optimize pyroelectric response. For some materials, dP s /dT and dε/dT are lower in thin film than in bulk as a result of strain within films. If the pyroelectric response to changes in temperature is too low, one can enhance it by doping the films with acceptor impurities (Fe, Mn, Co, Ni) which are known to create charged impurity and oxygen vacancy centers. These charge centers can complex and form defect-dipoles which can be aligned to enhance polarization by biasing the dielectric. Near the Curie temperature, however, one can anticipate that the defect- dipoles become randomly oriented. This should increase the dP s /dT value and increase the overall pyroelectric response significantly. In addition, we can fabricate more reliable pyroelectric films by adding dopant donors (W, Ta, and Nb) that reduce imprint. Finally, one can co-dope pyroelectric films with both donors and acceptors in order to suppress the traps that cause imprint and to create defect-dipoles that enhance pyroelectric properties, respectively. The Figures 1 , 3A-C, and 6 depict a separate blacking layer. The purpose of the blacking layer is to maximize absorption of radiation within the spectral bands of interest (2-5μm and 10-14μm) and subsequently increase the signal to noise ratio of the sensor. Some blacking agents, i.e. lamp black absorb radiation efficiently at a fairly broad bandwidth of radiation. However, other blacking agents absorb efficiently only within fairly narrow bandwidths. Hence, for applications where the absorption should be limited to particular bandwidths, one would choose a blacking agent suitable to the task. Such a selection is within the ordinary skill in the art. Only the blacking agent (step 18) need be changed to accomplish the particular desired result. The LSCO material used in the top electrode displays some of these characteristics and might eliminate the need for a separate blacking layer on top. Various other material substitutions may be made. Although Si was used as the substrate in the example, other materials such as MgO and Al 2 0 3 could also be used. A plurality of pixels 186 may be formed on an appropriate substrate 188 to define an imaging array 190 for a monolithic thermal infrared detector 196 as illustrated in Figure 7 and in accordance with principles of the present invention. Appropriate structures for the pixels 186 include those presented in Figures 1 , 3A-C, and 6 as discussed above, as well as the pixels 184 which are illustrated in Figures 9A-P and 10 and which will be discussed in more detail below. An interpixel spacing 194 exists between each adjacent pixel 186 and is defined as the center-to-center distance between the thermal imaging elements of adjacent pixels 186 in any given row or column of the array 190, or a lateral spacing (the center of the thermal imaging element from a top view as presented in Figure 7). In one embodiment, this interpixel spacing 194 is no more than about 10 micrometers due to the structure of the pixels 186 as will be discussed in more detail below. Moreover, in one embodiment each side 198 of the thermal imaging element of the individual pixels 186 is no more than about 4 micrometers, and in one embodiment the thermal imaging elements of the individual pixels 186 are at least substantially square-shaped from a top view as illustrated in Figure 7 and are no more than about 4 micrometers by about 4 micrometers. Performance characteristics of the detector 196 include a noise-equivalent-temperature which difference is less than about 0.1 °C in one embodiment, more preferably no more than about 0.07 °C in another embodiment, and even more preferably no more than about 0.05 °C in yet another embodiment. "Noise-equivalent-temperature-difference" as used herein means the temperature change (signal) on the detector 196 required to produce a signal-to-noise ratio of 1. This performance is realized without cooling the detector 196 other than through its existence in the environment as will be discussed in more detail below and is at least comparable with photon detectors which are cryogenically cooled and significantly more expensive to operate/manufacture. The readout circuitry/sensing architecture (e.g., control, sensor, and image processing circuitry) for the detector 196 will typically be disposed on a periphery 192 of the detector 196 which is that area which extends beyond the array 190. It is believed that existing readout circuity/sensing architecture will be appropriate for the pixels 186 having the above-noted structures. However, it is also anticipated that development efforts in this area will lead to new readout circuitry/sensing architecture which will take advantage of the desirable performance characteristics of these structures. In one embodiment, this readout circuitry is configured such that the detector 196 functions as a bolometer where a change in resistance is measured to generate the image, and which is generated based upon a change in temperature. In another embodiment, this readout circuitry is configured such that the detector 196 functions as a pyroelectric detector where a current flow is measured to generate the image, and which is generated based upon a change in capacitance which in turn is based upon a change in temperature. The monolithic thermal infrared detector 196 of Figure 7 may be disposed in a plastic encasement or package 200 as illustrated in Figure 8. Certain plastics may allow the wavelength(s) of light of interest to pass through the encasement 200 and to the pixels 186 of the detector 196. In other instances it may be necessary to include a window 204 which is transparent to the wavelength(s) of light of interest, which is illustrated by the dashed line presented in Figure 8, and which is at least as large as the array 190 and appropriately aligned therewith. The encasement 200 may be molded about the detector 196, or may be formed with a cover (not shown) which may be totally removed from the encasement or which may be movably interconnected therewith in an appropriate manner (e.g., one or more hinges). Employing the latter two designs would allow the detector 196 to be inserted into and removed from the encasement 200 without damaging the encasement 200. Moreover, it would also allow for selection of the manufacturing process of the encasement 200 without consideration of the detector 196 since they would each be separately formed and then assembled. Figures 9A-P illustrate an embodiment for assembling/forming a pixel 184 (Figures 9 H-P, 10) for a monolithic thermal infrared detector in accordance with principles of the present invention and in accordance with the above-described technique. This same methodology may be used to simultaneously assemble/form the plurality of pixels 186 to define the array 190 for the thermal infrared detector 196 of Figure 7. Referring to Figure 9A, an appropriate substrate 100 includes a semiconductor device 104 (e.g., transistor) having an n region 108 which may be the source or drain, an n region 112 which is laterally displaced from the n region 108 (i.e., in a direction which is at least substantially parallel with the upper surface of the substrate 100) and which is the other of the source and drain, and a p region 116 which extends therebetween and which defines a channel for the flow of current between the n region 108 and the n region 112. A gate 120 is disposed over the p region 116 to control this flow of current. In one embodiment, the gate 120 is doped polysilicon so as to be able to withstand processing relating to the actual thermal imaging element of the pixel 184 to be discussed in more detail below. The semiconductor device 104 is formed by standard semiconductor processing techniques and facilitates the reading out of information from the pixel 184 which is electrically interconnected therewith and which is laterally spaced therefrom (e.g., no portion of any pixel 184 is disposed directly above its corresponding semiconductor device 104). In this regard, metal runs (not shown) will be interconnected with one or more of the n regions 108, 112 (source and drain) and the gate 120. Appropriate materials for the substrate 100 for purposes of the monolithic thermal infrared detector 196 include silicon, silicon carbide, diamond, gallium arsenide, or other semiconductor materials. Active silicon is currently preferred for the substrate 100. Materials such as gallium arsenide would have to be encapsulated if used to form the substrate 100 so as to offer protection in relation to the processing to be further described, primarily the heat treatment of the actual thermal imaging element of the pixel 184. "Encapsulation" in relation to the substrate 100 in this respect means providing a barrier layer to prevent disassociation or diffusion from the substrate 100 into the thermal imaging element of the pixel 184 (e.g, diffusion of the arsenic forming the gallium arsenide substrate 100 into the pyroelectric material forming the thermal imaging element of the pixel 184). Materials which may be used to encapsulate the substrate 100 include silicon nitride, and these materials would cover all portions of the upper surface of the substrate 100 except where there is to be a bottom electrode for the pixel 184 disposed somewhere directly thereabove (i.e., no silicon nitride will be directly below any lower electrode of the pixel 184). Continuing to refer to Figure 9A, a first barrier layer 124 overlays (i.e., is disposed directly above) and interfaces with the upper surface of the substrate 100 at least in that region which is to include the array 190. In one embodiment, this first barrier layer 124 has a thickness of no more than about 4 micrometers, and more preferably about 1 micrometer. Standard semiconductor processing techniques may be used to deposit the first barrier layer 124 on the upper surface of the substrate 100 by (e.g. , wet or dry thermal processing). Functionally, the first barrier layer 124 protects the semiconductor device 104, as well as other semiconductor devices and integrated circuits contained within the substrate 100 for that matter, from chemical diffusion/interaction due to overlying layers of the detector 196 (e.g., prevents/reduces the potential of the pyroelectric material forming the thermal imaging element of the pixel 184 from diffusing back into the substrate 100). Thermal oxides will provide this function, as well as deposited oxides (e.g., via chemical vapor deposition, sputtering), with silicon dioxide currently being preferred for the first barrier layer 124. In this regard, silicon dioxide is inert at the processing temperatures used in the manufacture of the detector 196 such that it will not decompose, is compatible with the substrate 100 when silicon-based, and may provide adhesive qualities for the layer disposed thereabove. A first barrier layer 125 will be used even in the case where the silicon nitride encapsulated gallium arsenide is used for the substrate 100. Adequate thermal isolation of the thermal imaging element of the pixel 184 from the substrate 100 while generating thermal images is realized by depositing a first thermal insulation layer 128 directly on the upper surface of the first barrier layer 124 as illustrated in Figure 9B, and at least in that region which is to include the array 190. It is therefore proper to characterize the first thermal insulation layer 128 as overlaying (being disposed directly above) and interfacing with the first barrier layer 124. Compatibility between the first barrier layer 124 and the first thermal insulation layer 128 is an issue, as well and the thermal insulation characteristics of the first thermal insulation layer 128. In this regard, the thermal conductivity of the first insulation layer 128 is no more than about 80 mW/m°K in one embodiment, and more preferably no more than about 5 mW/m°K in another embodiment. One material which addresses both the compatibility and thermal insulation issues in a highly desirable manner are xerogels, and particularly aerogels (e.g., silica aerogel). Using aerogels for the first thermal insulation layer 128 is further desirable in that an aerogel will protect the substrate 100, more accurately its semiconductor devices and integrated circuits, from chemical diffusion/reaction in the processing of the thermal imaging element of the pixel 184 which is discussed in more detail below. Chemical formulations and desired methods of forming an aerogel layer are disclosed in U.S. Patent Application Serial No. 08/530,543 which was filed on September 1 , 1995 and which is entitled "Ambient Pressure Process for Preparing Aerogel Thin Films, the entire disclosures of which is incorporated by reference herein. Generally, a method for forming the first barrier layer 124 from aerogel must be compatible with standard semiconductor processing techniques, and in one embodiment may be described as a sol-gel deposition technique as described above. In one embodiment when a silica aerogel is used for the first thermal insulation layer 128, it has a thickness of no more than about 4 micrometers, and in another embodiment has a thickness of about 0.4 micrometers. This thickness is at least substantially uniform across the entirety of the substrate 100 at least in that region which is to include the array 190. Porosities of the aerogel which provide a desired degree of both thermal insulation and structural support for components of the pixel 184 disposed above the first thermal insulation layer 128 are in one embodiment at least about 20%. Commercial devices are expected to utilize a porosity for the aerogel of the first thermal insulation layer 128 of at least about 80%, and in one embodiment a porosity which is within a range of about 80% to about 95%. Even at these higher porosities, the aerogel still provides sufficient structural stability for the detector 196 (i.e., the aerogel is sufficiently robust so as to not collapse or density during the subsequent deposition and processing steps and it at least substantially retains its porosity, thickness, and structure). Addressing the upper surface of the aerogel if used as the first thermal insulation layer 128 may be required in certain, but not necessarily all instances. Figure 9C illustrates a planarization layer 132 which overlays the first thermal insulation layer 128 at least in that region which is to include the array 190, which interfaces with the upper surface of the first thermal insulation layer 128, and which may be applied using conventional semiconductor processing techniques (e.g., RF sputtering). Planarization layer 132 seals the upper surface of the first thermal insulation layer 128 which may be required when aerogel is utilized for layer 128 due to its porous nature. It may also be used to provide a suitable surface (e.g., smooth) upon which further layers may be formed to create the infrared detector 196 and which also may be required when aerogel is utilized for the layer 128 again due to its porosity and rough surface. In one embodiment, the thickness of the planarization layer 132 is no more than about 1 micrometer, and in another embodiment the thickness is within a range of about 200 Angstroms to about 400 Angstroms. Preferably the roughness of the upper surface of the planarization layer 132, or the upper surface of the first thermal insulation layer 128 if no planarization layer 132 is used for that matter, is no more than about 500 Angstroms. Compatibility with other layers of the detector 196 and standard semiconductor processing techniques is achieved by using silicon dioxide for the planarization layer 132, although it may be possible that other materials (e.g., titanium oxide) could be utilized as well with an aerogel forming the first thermal insulation layer 128 as long as such materials are compatible with the aerogel. Moreover, as noted the planarization layer 132 may not be required in all instances. Protection of the first thermal insulation layer 128 against subsequent processing which is required to complete the construction of the detector 196 is realized through an etch stop layer 136 which is illustrated in Figure 9D. One etch stop layer 136 will be formed over at least each portion of the first thermal insulation layer 128 on which a pixel 184 is to be disposed to define the array 190. In this regard, a layer of metal, such as titanium, zirconium, or other metals which are a chemically resistive and/or insulating oxide that is compatible with and/or germane to semiconductor processing (e.g., titanium oxide, zirconium oxide, tantalum oxide), is deposited directly on the planarization layer 132 or possibly directly on the first thermal insulation layer 128 by conventional semiconductor processing techniques (e.g., sputter deposition, e-beam evaporation) in overlaying and interfacing relation therewith. This layer of metal is masked and thereafter etched such that there is a remaining metal pad in each region where an etch stop layer 136 is required in accordance with the foregoing. No portion of an etch stop layer 136 associated with any given pixel 184 of the array 190 will be disposed in overlaying relation with its corresponding semiconductor device 104 (i.e., no portion of the etch stop 136 will be disposed directly above the semiconductor device 104 since vias 160 need to be etched down to the device 104 as will be discussed in more detail below). Various wet and dry etchants may be used in the case where the metal is titanium, such as dilute H 2 O 2 . Thereafter, the remaining metal pads are oxidized (e.g., to form TiO x (titanium oxide), zirconium oxide, tantalum oxide, or other insulating oxides that are germane to semiconductor processing) to complete the definition of the etch stop layer(s) 136 on the planarization layer 132 or the first thermal insulation layer 128 as the case may be. Typically, the thickness of each etch stop layer 136 will be no more than about 1 micrometer. A pixel 184 is constructed on the above-described structure which will be thermally isolated from the substrate 100 to enhance the sensitivity and performance of the detector 196. Referring to Figure 9E, a lower electrode 140 of the pixel 184 is appropriately formed in overlaying relation with only part of its corresponding etch stop layer 136 (i.e., the etch stop layer 136 extends beyond the lower electrode 140 on at least one side, and preferably on all sides). That is, the etch stop layer 132 extends a distance "d" further beyond its corresponding lower electrode 140 such that when an etching procedure is used to define the configuration of the thermal imaging element for the detector 196 (Figures 9F-G), the portion of the first thermal insulation layer 128 which is disposed directly beneath the thermal imaging element will not be etched or otherwise adversely affected. In one embodiment, the distance "d" is no more than about 2 micrometers and exists about the entire perimeter of the lower electrode 1 0. One particularly desirable lower electrode 140 is actually a laminated structure. First a layer of adhesive 141 , such as a titanium metal when the etch stop layer 136 is a titanium oxide, is deposited on the described portion of the etch stop layer 136 using conventional semiconductor processing techniques. In one embodiment, the thickness of the adhesive layer 141 is about 500 Angstroms. Second, a lower electrode first metal layer 142 is deposited on the adhesive layer 141 using conventional semiconductor processing techniques (e.g., sputtering, evaporation). In one embodiment, the lower electrode first metal layer 142 is platinum with a thickness of about 1 ,000 Angstroms. Third, a lower electrode second metal layer 143 is deposited on the lower electrode first metal layer 142 using conventional semiconductor processing techniques (e.g., sputtering, evaporation). In one embodiment, the lower electrode second metal layer 143 is LSCO (lanthium strontium cobalt oxide) with a thickness of about 600 Angstroms. Conventional lift-off techniques may be used to define the configuration of the lower electrode 140 illustrated in Figure 9E. Other materials may be used to form the lower electrode 140 either in single metal, multiple metal, or other conducting oxide configurations, such as platinum, rubidium, iridium, palladium, fully conductive single oxides, as well as binary and complex oxides, and single or multiple layer configurations may also be utilized. Overlaying at least a portion of the lower electrode 140 is a ferroelectric material layer 144 for the pixel 184 as illustrated in Figure 9F, and which is preferably a pyroelectric material. Although the layer 144 can be of any ferroelectric material which has a crystallization temperature which is below that which will have an adverse effect on the first thermal insulation layer 128 and in one embodiment a sintering temperature of no more than about 650° C provided that the necessary compatibility issues are appropriately addressed, at least for the case when the first thermal insulation layer 128 is an aerogel PZT (lead zirconium titanate) is preferred for the layer 144 which may be appropriately crystallized/pyrolyzed for purposes of the detector 196 at a temperature of no more than about 600°C. For cases when the first thermal insulation layer 128 is an aerogel, these types of processing temperatures should not adversely affect the structure/performance of the first insulation layer 128 as noted. Stated another way and for cases when the first thermal insulation layer 128 is an aerogel, the type of ferroelectric material 144 which is selected should be those which use a sintering temperature which is below that which will have an adverse effect on the layer 128 (e.g., by densifying or otherwise structurally affecting the aerogel). The ferroelectric material layer 144 is deposited on/above the lower electrode 140 by standard semiconductor processing techniques to define a thin film of ceramic, preferably using direct thin film deposition techniques. In one embodiment the layer 144 is formed by a solution deposition technique and has a thickness of no more than about 1 micrometer, and more preferably no more than about 0.5 micrometers, at least in the region which overlays (disposed directly above) the upper substantially planar surface of the lower electrode 140. Thereafter, the ferroelectric material layer 144 is patterned and etched to define the configuration illustrated in Figure 9G wherein it is disposed above only a portion of the upper surface of the lower electrode 140, and further such that it extends down at least a portion of the side of the lower electrode 140 to the etch stop layer 136. This reduces the potential for the development of an electrical short with the upper electrode 148 (Figure 9H). The etch stop layer 136 precludes this etching step from damaging at least that portion of the first thermal insulation layer 128 which is disposed directly below or underneath the ferroelectric material layer 144 such that there is sufficient thermal isolation of the pixel 184 relative to the substrate 100. Moreover, the planarization layer 132 and first thermal insulation layer 128 which overlays the first semiconductor device 104 (disposed directly above) are not adversely affected by this etching process, nor is the lower electrode 140. With the ferroelectric material layer 144 being in the desired configuration, the entire assembly thus far described is annealed within the above- described temperature limits to crystallize the ferroelectric material layer 144 and to pyrolyze the same to define the thermal imaging element 145. An upper electrode 148 is formed on top of and interfaces with at least a portion of the upper surface of the thermal imaging element 145 as illustrated in Figure 9H. Conventional semiconductor processing techniques may be used to form the upper electrode 148. One particularly desirable upper electrode 148 is actually a laminated structure. First, an upper electrode first metal layer 149 is deposited directly on/above the thermal imaging element 145 using conventional semiconductor processing techniques (e.g., sputtering, evaporation deposition). In one embodiment, the upper electrode first metal layer 149 is LSCO with a thickness of about 600 Angstroms. Second, an upper electrode second metal layer 150 is deposited on the upper electrode first metal layer 149 using conventional semiconductor processing techniques (e.g., sputtering, evaporation deposition). In one embodiment, the upper electrode second metal layer 150 is platinum with a thickness of about 1 ,000 Angstroms. Conventional lift-off techniques may be used to define the configuration of the upper electrode 148 illustrated in Figure 9H. The materials and configurations presented above in relation to the lower electrode 140 are equally applicable to the upper electrode 148. An appropriate blacking agent layer 152 is applied to at least a portion of the upper surface of the upper electrode 148 so as to be in overlaying relation therewith as illustrated in Figure 91 and which completes the definition of the pixel 184 (i.e., the blacking agent 152 if used, upper electrode 148, thermal imaging element 145, and lower electrode 140 collectively define the pixel 184). Conventional semiconductor processing techniques may be utilized for this step as well (e.g., sputtering, evaporation deposition). The blacking agent layer 152 controls which wavelengths of light are allowed to pass to the thermal imaging element 145, and therefore may be used to tailor the detector 196 to a particular application. In some cases, the function provided by the blacking agent layer 152 could be incorporated into the upper electrode 148 through selection of the appropriate material(s)/configuration for the upper electrode 148. In one embodiment, the thickness of the blacking agent layer 152 is no more than about 1 micrometer, and is typically about 0.5 micrometers. A second thermal insulation layer 156 is applied over each of the pixels 184 of the array 190, and preferably occupies at least a portion of the area between each adjacent pixel 184 as illustrated in Figure 9J and Figure 10. Conventional aerogel deposition techniques may be used to apply the second thermal insulation layer 156. The second thermal insulation layer 156 provides pixel-to-pixel thermal isolation which enhances the performance characteristics of the detector 196, and through selection of appropriate materials may also reduce/eliminate the capacitive coupling which may exist between the thermal imaging element 145 and its associated semiconductor device 104 so as to provide a "cleaner" signal (higher signal-to-noise ratio). In one embodiment, the second thermal insulation layer 156 is xerogel which has better thermal insulating characteristics than merely air which is employed in many known thermal infrared detectors, and in another embodiment is silicon dioxide. Aerogel is currently the preferred material for the second thermal insulation layer 156 which is a type of xerogel Qualities/characteristics presented above with regard to the first thermal insulation layer 128 (e.g., porosity) are equally applicable to the second thermal insulation layer 156. Moreover, preferably the thickness of the second thermal insulation layer 156 in the area between adjacent pixels 184 is such that a reference axis which extends from one pixel 184 to an adjacently disposed pixel 184 in a direction which is at least generally parallel with the upper surface of the substrate 100 will pass through at least a portion of the second thermal insulation layer 156, and more preferably will be totally contained within the second thermal insulation layer 156 except possibly for interconnecting structure which may be extending down through the second thermal insulation layer 156. Even more preferably, a reference axis which extends from the thermal imaging element 145 of one pixel 184 to the thermal imaging element 145 of an adjacent pixel 184, again in a direction which is at least generally parallel with the upper surface of the substrate 100, will pass through at least a portion of the second thermal insulation layer 156, and more preferably will be totally contained within the second thermal insulation layer 156 again except possibly for interconnecting structure which may be extending down through the second thermal insulation layer 156. This is illustrated in Figure 10 in relation to the adjacently disposed pixels 184a and 184b. Various vias 160 are formed to provide for the desired/required electrical interconnections between each of the pixels 184 and their corresponding semiconductor device(s) 104 as illustrated in Figure 9K. In the configuration presented in Figure 9K, one via 160 is etched down through the second thermal insulation layer 156 to each of the source and drain electrodes of the semiconductor device 104 (e.g., the two n regions 108, 112), the upper electrode 148 of the pixel 184, and the lower electrode 140 of the pixel 184. Appropriate metal interconnects 168 are then formed as illustrated in Figures 9L-M through the deposition of a metal layer 164 which is deposited in overlaying relation with the upper surface of the structure so far described and a subsequent etching of the same. In one embodiment, the metal layer 164 includes a barrier metal, such as titanium nitride (which is compatible with LSCO/platinum), as well another conducting metal such as aluminum. Since the thermal imaging element 145 of each pixel 184 has already been crystallized prior to the formation of the metal interconnects 168, the annealing of the ferroelectric material layers 144 can have no immediate effect on the metal interconnects 168. A scratch protection layer 172 is applied by conventional semiconductor processing techniques over at least that area of the detector 196 defined by the array 190 using conventional semiconductor processing techniques as illustrated in Figure 9N. The scratch protection layer 172 provides a mechanical barrier of sorts to protect the pixels 184, and typically is not a seal against gases or chemical diffusion. In one embodiment, the scratch protection layer 172 may have any one or more of the following characteristics: 1) the thickness of the scratch protection layer 172 is no more than about 4 micrometers; 2) the scratch protection layer 172 is formed of silicon dioxide; 3) the scratch protection layer 172 has a density of at least about 98-99%; and 4) the scratch protection layer 172 may be applied by chemical vapor deposition, sputtering, or other applicable semiconductor processing techniques. Protection of the underlying pixels 184 against at least certain types of chemical diffusion and/or protection against subsequent processing is provided by a second barrier layer 176 which is illustrated in Figure 90. Preferably, the second barrier layer 176 overlays at least the entirety of the array 190. In one embodiment, the second barrier layer 176 may have any one or more of the following characteristics: 1 ) the thickness of the second barrier layer 176 is within a range of about 500 Angstroms to about 1 micrometer; and 2) the second barrier layer 176 is formed of a silicon oxy-nitride. Finally, an encapsulation layer 180 is applied over at least that area having the array 190 using standard semiconductor processing techniques as illustrated in Figure 9P. "Encapsulation" in relation to the layer 180 means providing a barrier layer to prevent disassociation or diffusion from the environment to the thermal imaging element 145 of the pixel 184 (e.g, any reducing ambience), particularly acids and/or hydrogen reducing elements/compounds such as hydrogen ions and hydroxide ions. In one embodiment, the encapsulation layer 180 is silicon nitride. The conditions required to deposit the silicon nitride for the encapsulation layer 180 are such that without the second barrier layer 176, the thermal imaging elements 145 of one or more of the pixels 184 would be undesirably damaged. The thickness of the encapsulation layer in one embodiment is no more than about 800 Angstroms, and in another embodiment is no more than about 500 Angstroms. Moreover, preferably the density of the encapsulation layer 180 is at least about 98% dense. The thermal detectors presented herein in relation to the present invention offer a number of significant advantages. Initially, the detectors are uncooled and yet have performance characteristics which are comparable, if not superior, to cooled photon detectors. Moreover, in one embodiment the entire device has a "lower" profile in that no portion of the above-described stack extends more than about 2 micrometers above the upper surface of the substrate 100. Furthermore, the thermal detectors use a monolithic or fully integrated structure such that the detectors may be made using standard semiconductor processing techniques through the addition of multiple layers and without the need for bump bonding techniques used by other thermal detector designs. In this regard, thin film pyroelectric materials are used for the imaging element. Finally, areogels are successfully utilized in the above-noted structure and using the above-noted manufacturing techniques in a manner such that the thermal imaging element is more effectively thermally isolated from the substrate, and preferably such that the individual pixels of the detector are more effectively thermally isolated from each other. Each of these contributes to the enhanced thermal, spatial, and temporal resolutions available from two-dimensional arrays of thermal infrared detectors in accordance with principles of the present invention. The encapsulation technique disclosed above in relation to the encapsulation layer 180 and the second barrier layer 176 is applicable to other applications as well, for instance memory applications. In this regard, a schematic of a memory device 206 is presented in Figure 11. The memory device 206 includes an active substrate 208 (i.e., having one or more semiconductors and/or integrated circuits). Overlaying typically only a portion of the substrate 208 is a memory element 210. The memory element 210 is formed from a dielectric material, such as the types of ferroelectric/pyroelectric materials referred to above in relation to the infrared detector application which are also dielectrics. Overlaying the memory element 210 is a barrier layer 212. The barrier layer 212 may be the same as the second barrier layer 176 discussed above. Overlaying the barrier layer 212 is an encapsulation layer 214. The encapsulation layer 214 may be the same as the encapsulation layer 180 discussed above. In one embodiment, a plastic encasement, such as the encasement 200 referenced above, may enclose the memory device 206 (not shown in combination). The foregoing description of the present invention has been presented for purposes of illustration and description. Furthermore, the description is not intended to limit the invention to the form disclosed herein. Consequently, variations and modifications commensurate with the above teachings, and skill and knowledge of the relevant art, are within the scope of the present invention. The embodiments described hereinabove are further intended to explain best modes known of practicing the invention and to enable others skilled in the art to utilize the invention in such, or other embodiments and with various modifications required by the particular application(s) or use(s) of the present invention. It is intended that the appended claims be construed to include alternative embodiments to the extent permitted by the prior art.

Claims: What is claimed is: 1. A thermal infrared detector, comprising: a substrate comprising a first semiconductor device; a first thermal insulation layer overlaying at least a portion of said substrate, wherein said first thermal insulation layer comprises a xerogel; a first etch stop layer overlaying at least a portion of said first thermal insulation layer, wherein a pixel comprises a lower electrode, a thermal imaging element comprising a ferroelectric material overlaying at least a portion of said lower electrode, and an upper electrode overlaying at least a portion of said thermal imaging element, and wherein said detector further comprises: a first said pixel overlaying at least a portion of said first etch stop layer and electrically interconnected with said first semiconductor device. 2. A detector, as claimed in Claim 1 , wherein: said substrate is selected from the group consisting of silicon, gallium arsenide encapsulated in silicon nitride, silicon carbide, , and diamond. 3. A detector, as claimed in Claim 1 , further comprising: an oxide layer overlaying at least a portion of said substrate and being disposed between said at least a portion of said substrate and said first thermal insulation layer, wherein at least a portion of said first thermal insulation layer overlays at least a portion of said oxide layer. 4. A detector, as claimed in Claim 3, wherein: said oxide layer has a thickness of no more than about 4 micrometers. 5. A detector, as claimed in Claim 3, wherein: said oxide layer is silicon dioxide. 6. A detector, as claimed in Claim 1 , wherein: said first thermal insulation layer has a thickness of no more than about 4 micrometers. 7. A detector, as claimed in Claim 1 , wherein: said first thermal insulation layer has a porosity of at least about 20%. 8. A detector, as claimed in Claim 1 , wherein: said first thermal insulation layer has a porosity of at least about 80%. 9. A detector, as claimed in Claim 1 , wherein: said first thermal insulation layer has a porosity within a range of about 80 percent to about 95 percent. 10. A detector, as claimed in Claim 1 , wherein: said first thermal insulation layer comprises aerogel. 11. A detector, as claimed in Claim 1 , further comprising: a planarization layer overlaying at least a portion of said first thermal insulation layer and disposed between said first thermal insulation layer and said first etch stop layer. 12. A detector, as claimed in Claim 11 , wherein: said planarization layer comprises silicon dioxide. 13. A detector, as claimed in Claim 11 , wherein: said planarization layer has a thickness of no more than about 1 micrometer. 14. A detector, as claimed in Claim 1 , wherein: said first etch stop layer is selected from the group consisting of titanium oxide, zirconium oxide, tantalum oxide, and other insulating oxides that are germane to semiconductor processing. 15. A detector, as claimed in Claim 1 , wherein: said first etch stop layer has a thickness of no more than about 1 micrometer. 16. A detector, as claimed in Claim 1 , wherein: said first etch stop layer is laterally spaced from said first semiconductor device, whereby no portion of said first etch stop layer is disposed directly above said first semiconductor device. 17. A detector, as claimed in Claim 1 , wherein: said first said pixel is laterally spaced from said first semiconductor device, whereby no portion of said first said pixel is disposed directly above said first semiconductor device. 18. A detector, as claimed in Claim 1 , wherein: said ferroelectric material has a sintering temperature which is below that which will have an adverse effect on said first thermal insulation layer. 19. A detector, as claimed in Claim 1 , wherein: said ferroelectric material is formed using a direct thin film deposition technique. 20. A detector, as claimed in Claim 1 , wherein: said ferroelectric material is a pyroelectric material. 21. A detector, as claimed in Claim 1 , wherein: said thermal imaging element has a thickness of no more than about 0.5 micrometers. 22. A detector, as claimed in Claim 1 , wherein: no dimension of said thermal imaging element is more than about 4 micrometers. 23. A detector, as claimed in Claim 1 , further comprising: a blacking agent layer overlaying at least a portion of said upper electrode of said first said pixel. 24. A detector, as claimed in Claim 1 , further comprising: a second thermal insulation layer overlaying at least a portion of said substrate in at least a portion of an area between said first said pixel and said first semiconductor device. 25. A detector, as claimed in Claim 1 , further comprising: a scratch protection layer overlaying at least a portion of each of said first said pixel and said first semiconductor device. 26. A detector, as claimed in Claim 25, wherein: said scratch protection layer is silicon dioxide. 27. A detector, as claimed in Claim 25, wherein: said scratch protection layer has a thickness of no more than about 4 micrometers. 28. A detector, as claimed in Claim 1 , further comprising: a barrier layer overlaying at least said first said pixel and said first semiconductor device; and an encapsulation layer overlaying an entirety of said barrier layer. 29. A detector, as claimed in Claim 28, wherein- said barrier layer is an oxy-nitride and said encapsulation layer is silicon nitride. 30. A detector, as claimed in Claim 28, further comprising: a plastic container which encases said substrate, said first said pixel, said barrier layer, and said encapsulation layer. 31. A detector, as claimed in Claim 1 , further comprising: a second semiconductor device formed in said substrate and laterally spaced from said first semiconductor device; a second etch stop layer overlaying at least a portion of said first aerogel layer; and a second said pixel overlaying at least a portion of said second etch stop layer, electrically interconnected with said second semiconductor device, and laterally spaced from said first said pixel. 32. A detector, as claimed in Claim 31 , further comprising: a second thermal insulation layer which occupies at least a portion of a lateral space between said first said pixel and said second said pixel, wherein at least one reference axis extending from said first said pixel to said second said pixel in a direction which is at least substantially parallel with an upper surface of said substrate passes through said second thermal insulation layer. 33. A detector, as claimed in Claim 32, wherein: said second thermal insulation layer has a porosity of at least about 20 percent. 34. A detector, as claimed in Claim 32, wherein: said second thermal insulation layer has a porosity of at least about 80 percent. 35. A detector, as claimed in Claim 32, wherein: said second thermal insulation layer has a porosity within a range of about 80 percent to about 95 percent. 36. A detector, as claimed in Claim 32, wherein: said second thermal insulation layer is a xerogel. 37. A detector, as claimed in Claim 32, wherein: said second thermal insulation layer is an aerogel. 38 A detector, as claimed in Claim 31 , wherein a distance between a center of said thermal imaging element of said first said pixel and a center of said thermal imaging element of said second said pixel is no more than about 10 micrometers 39 A detector, as claimed in Claim 1 , further comprising a plurality of said pixels which are each disposed above said first thermal insulation layer and which collectively define an array, and a plastic encasing for said array 40 A detector, as claimed in Claim 39, further comprising an oxy-nitride layer which overlays at least an entirety of said array and which is disposed within said plastic encasing, and a silicon nitride layer which overlays at least an entirety of said oxy-nitride layer and which is disposed within said plastic encasing 41 A detector, as claimed in Claim 1 , wherein said first semiconductor device comprises a transistor 42 A detector, as claimed in Claim 1 , wherein said detector has a noise-equivalent-temperature-difference of no more than about 007 °C, wherein said noise-equivalent-temperature-difference is the temperature change on said detector required to produce a signal-to-noise ratio of 1 43 A detector, as claimed in Claim 1 , wherein said detector has a noise-equivalent-temperature-difference of no more than about 005 °C, wherein said noise-equivalent-temperature-difference is the temperature change on said detector required to produce a signal-to-noise ratio of 1 44. A detector, as claimed in Claim 1 , wherein: said detector is part of a thermal imaging system, said thermal imaging system comprising readout circuity which is selected from the group consisting of being for a bolometer and a pyroelectric detector. 45. A thermal infrared detector, comprising: a substrate comprising a first semiconductor device; a first thermal insulation layer overlaying at least a portion of said substrate, wherein a pixel comprises a lower electrode overlaying a portion of said first aerogel layer, a thermal imaging element comprising a ferroelectric material layer overlaying at least a portion of said lower electrode, and an upper electrode overlaying at least a portion of said thermal imaging element, and wherein said detector further comprises: a first said pixel overlaying a portion of said first thermal insulation layer and electrically interconnected with said first semiconductor device; a barrier layer overlaying at least said first said pixel; and an encapsulation layer overlaying at least both said barrier layer and said thermal imaging element of said first said pixel, wherein said barrier layer protects said ferroelectric material of said first said pixel from processing associated with said encapsulation layer. 46. A detector, as claimed in Claim 45, wherein: said substrate is selected from the group consisting of silicon, gallium arsenide encapsulated in silicon nitride, silicon carbide, and diamond. 47. A detector, as claimed in Claim 45, further comprising: an oxide layer overlaying at least a portion of said substrate and being disposed between said at least a portion of said substrate and said first thermal insulation layer, wherein at least a portion of said first thermal insulation layer overlays at least a portion of said oxide layer. 48. A detector, as claimed in Claim 47, wherein: said oxide layer has a thickness of no more than about 4 micrometers. 49. A detector, as claimed in Claim 47, wherein: said oxide layer is silicon dioxide. 50. A detector, as claimed in Claim 45, wherein: said first thermal insulation layer has a thickness of no more than about 4 micrometers. 51. A detector, as claimed in Claim 45, wherein: said first thermal insulation layer has a porosity of at least about 20 percent. 52. A detector, as claimed in Claim 45, wherein: said first thermal insulation layer has a porosity of at least about 80 percent. 53. A detector, as claimed in Claim 45, wherein: said first thermal insulation layer has a porosity within a range of about 80 percent to about 95 percent. 54. A detector, as claimed in Claim 45, wherein: said first thermal insulation layer comprises aerogel. 55. A detector, as claimed in Claim 45, further comprising: a planarization layer overlaying at least a portion of said first thermal insulation layer. 56. A detector, as claimed in Claim 55, wherein: said planarization layer comprises silicon dioxide. 57. A detector, as claimed in Claim 55, wherein: said planarization layer has a thickness of no more than about 1 micrometer. 58. A detector, as claimed in Claim 45, further comprising: a first etch stop layer overlaying a portion of said first thermal insulation layer, wherein said first etch stop layer is disposed between said first said pixel and said first thermal insulation layer. 59. A detector, as claimed in Claim 58, wherein: said first etch stop layer is selected from the group consisting of titanium oxide, zirconium oxide, tantalum oxide, and other insulating oxides that are germane to semiconductor processing. 60. A detector, as claimed in Claim 58, wherein: said first etch stop layer has a thickness of no more than about 1 micrometers. 61. A detector, as claimed in Claim 58, wherein: said first etch stop layer is laterally spaced from said first semiconductor device, whereby no portion of said first etch stop layer is disposed directly above said first semiconductor device. 62. A detector, as claimed in Claim 45, wherein: said first said pixel is laterally spaced from said first semiconductor device, whereby no portion of said first said pixel is disposed directly above said first semiconductor device. 63. A detector, as claimed in Claim 45, wherein: said ferroelectric material has a sintering temperature which is below that which will have an adverse effect on said first thermal insulation layer. 64. A detector, as claimed in Claim 45, wherein: said ferroelectric material is formed using a direct thin film deposition technique. 65. A detector, as claimed in Claim 45, wherein: said ferroelectric material is a pyroelectric material. 66. A detector, as claimed in Claim 45, wherein: said thermal imaging element has a thickness of no more than about 0.5 micrometers. 67. A detector, as claimed in Claim 45, wherein: no dimension of said thermal imaging element is more than about 4 micrometers. 68. A detector, as claimed in Claim 45, further comprising: a first blacking agent layer overlaying at least a portion of said upper electrode of said first said pixel. 69. A detector, as claimed in Claim 45, further comprising: a second thermal insulation layer overlaying at least a portion of each of said first said pixel and said first semiconductor device. 70. A detector, as claimed in Claim 45, further comprising: a scratch protection layer overlaying at least a portion of each of said first said pixel and said first semiconductor device, wherein said scratch protection layer is disposed between said first said pixel and said barrier layer. 71. A detector, as claimed in Claim 70, wherein: said scratch protection layer is silicon dioxide. 72. A detector, as claimed in Claim 70, wherein: said scratch protection layer has a thickness of no more than about 4 micrometers. 73. A detector, as claimed in Claim 45, further comprising: a second semiconductor device formed in said substrate and laterally spaced from said first semiconductor device; and a second said pixel overlaying at least a portion of said first aerogel layer and said substrate, electrically interconnected with said second semiconductor device, and laterally spaced from said first said pixel. 74. A detector, as claimed in Claim 73, further comprising: a second thermal insulation layer which occupies at least a portion of a lateral space between said first said pixel and said second said pixel, wherein at least one reference axis extending from said first said pixel to said second said pixel in a direction which is at least substantially parallel with an upper surface of said substrate passes through said second thermal insulation layer. 75. A detector, as claimed in Claim 74, wherein: said second thermal insulation layer has a porosity of at least about 20 percent. 76. A detector, as claimed in Claim 74, wherein: said second thermal insulation layer has a porosity of at least about 80 percent. 77. A detector, as claimed in Claim 74, wherein: said second thermal insulation layer has a porosity within a range of about 80 percent to about 95 percent. 78. A detector, as claimed in claim 74, wherein: said second thermal insulation layer is a xerogel 79. A detector, as claimed in claim 74, wherein: said second thermal insulation layer is an aerogel. 80. A detector, as claimed in Claim 73, wherein: a distance between a center of said thermal imaging element of said first said pixel and a center of said thermal imaging element of said second said pixel is no more than about 10 micrometers. 81. A detector, as claimed in Claim 45, further comprising: a plurality of said pixels which are each disposed above said first thermal insulation layer and which collectively define an array; and a plastic encasing for said array. 82. A detector, as claimed in Claim 81 , wherein: said barrier layer overlays an entirety of said first said pixel; and said encapsulation layer overlays an entirety of said barrier layer; and said plastic encasing overlays an entirety of said encapsulation layer. 83. A detector, as claimed in Claim 45, wherein: said first semiconductor device comprises a transistor. 84. A detector, as claimed I Claim 45, wherein: said barrier layer is oxy-nitride and said encapsulation layer is silicon nitride. 85. A detector, as claimed in Claim 45, wherein: said detector has a noise-equivalent-temperature-difference of no more than about 0.07 °C, wherein said noise-equivalent-temperature-difference is the temperature change on said detector required to produce a signal-to-noise ratio of 1. 86. A detector, as claimed in Claim 45, wherein: said detector has a noise-equivalent-temperature-difference of no more than about 0.05 °C, wherein said noise-equivalent-temperature-difference is the temperature change on said detector required to produce a signal-to-noise ratio of 1. 87. A detector, as claimed in Claim 45, wherein: said detector is part of a thermal imaging system, said thermal imaging system comprising readout circuity which is selected from the group consisting of being for a bolometer and a pyroelectric detector. 88. A method for forming a thermal infrared detector on a substrate comprising a first semiconductor device, said method comprising the steps of: forming a first thermal insulation layer which overlays at least a portion of said substrate, wherein said first thermal insulation layer comprises xerogel; forming a first etch stop layer which overlays at least a portion of said first thermal insulation layer and after said forming a first thermal insulation layer step, wherein a forming a pixel step comprises forming a lower electrode, forming a thermal imaging element comprising a ferroelectric material layer which overlays at least a portion of said lower electrode, and forming an upper electrode which overlays at least a portion of said thermal imaging element, and wherein said method further comprises the step of: executing a first said forming a pixel step to define a first said pixel which overlays at least a portion of said first etch stop layer, wherein said executing a first said forming a pixel step is executed after said forming a first etch stop layer step. 89. A method, as claimed in Claim 88, wherein: said forming a first thermal insulation layer step, said forming a first etch stop layer step, and said executing a first said forming a pixel step each comprise using processing techniques which are at least compatible with standard semiconductor processing techniques. 90. A method, as claimed in Claim 88, wherein: said forming a thermal imaging element step of said executing a first said forming a pixel step comprises using direct thin film deposition techniques to define a thin film of said ferroelectric material and etching only perimeter portions of said thin film to form said thermal imaging element, wherein said first etch stop layer precludes said etching step from damaging said first thermal insulation layer underlying said first etch stop layer. 91. A method, as claimed in Claim 88, wherein: said executing a first said forming a pixel step is executed at a location which is laterally displaced from said first semiconductor device, and wherein said method further comprises the step of electrically interconnecting said first said pixel and said first semiconductor device. 92. A method, as claimed in Claim 88, further comprising the step of: electrically interconnecting said first said pixel with said first semiconductor device. 93. A method, as claimed in Claim 92, wherein: said electrically interconnecting step is executed after said executing a first said forming a pixel step. 94. A method, as claimed in Claim 92, wherein: said electrically interconnecting step comprises etching at least one via down through at least said first thermal insulation layer and to said first semiconductor device without passing through said first said pixel and etching at least one via to at least one of said upper and lower electrodes of said first said pixel. 95. A method, as claimed in Claim 92, further comprising the step of: forming a second thermal insulation layer which overlays at least both said first semiconductor device and said first said pixel, wherein said forming a second thermal insulation layer step is executed after said executing a first said forming a pixel step and wherein said electrically interconnecting step comprises etching at least one via down through at least one of said second and first thermal insulation layers to said first semiconductor device and etching at least one via down through at least said second thermal insulation layer to said first said pixel. 96. A method, as claimed in Claim 88, further comprising the step of: forming a second thermal insulation layer layer which overlays said substrate in at least a portion of an area between said first said pixel and said first semiconductor device, said forming a second thermal insulation layer step being executed after said executing a first said forming a pixel step. 97. A method, as claimed in Claim 88, further comprising the steps of: forming a barrier layer which overlays at least said first said pixel; and forming an encapsulation layer which overlays at least said barrier layer, wherein said forming a barrier layer comprises protecting said thermal imaging element of said first said pixel from said forming an encapsulation layer step. 98. A method, as claimed in Claim 97, wherein: said barrier layer comprises an oxy-nitride and said encapsulation layer comprises silicon nitride. 99. A method for forming a thermal infrared detector on a substrate comprising a first semiconductor device, said method comprising the steps of: forming a first thermal insulation layer which overlays at least a portion of said substrate, wherein said first thermal insulation layer comprises xerogel, and wherein a forming a pixel step comprises forming a pixel which overlays at least a portion of said first thermal insulation layer which in turn comprises the steps of forming a lower electrode which overlays at least a portion of said first thermal insulation layer, forming a thermal imaging element which comprises a ferroelectric material layer which overlays at least a portion of said lower electrode, and forming an upper electrode which overlays at least a portion of said thermal imaging element, and wherein said method further comprises the step of: executing a first said forming a pixel step to define a first said pixel; forming a barrier layer which overlays at least said first said pixel; and forming an encapsulation layer which overlays at least a portion of said barrier layer and which further overlays said first said pixel, wherein said forming a barrier layer step protects said thermal imaging element of said first said pixel from said forming an encapsulation layer step. 100. A method, as claimed in Claim 99, wherein: said forming a first thermal insulation layer step, said executing a first said forming a pixel step, said forming a barrier layer step, and said forming an encapsulation layer step each comprise using processing techniques which are at least compatible with standard semiconductor processing techniques. 101. A method, as claimed in Claim 99, further comprising the step of: forming a first etch stop layer which overlays at least a portion of said first thermal insulation layer, wherein said forming a first etch stop layer step is executed after said forming a first insulation layer step and before said executing a first said forming a pixel step, and wherein at least a portion of said executing a first said forming a pixel step is executed over said first etch stop layer. 102. A method, as claimed in Claim 101 , wherein: said forming a thermal imaging element step of said executing a first said forming a pixel step comprises using direct thin film deposition techniques to define a thin film of said ferroelectric material and etching only perimeter portions of said thin film to form said thermal imaging element, wherein said first etch stop layer precludes said etching step from damaging said first thermal insulation layer underlying said first etch stop layer. 103. A method, as claimed in Claim 99, further comprising the step of: electrically interconnecting said first said pixel with said first semiconductor device. 104. A method, as claimed in Claim 103, wherein: said electrically interconnecting step is executed after said executing a first said forming a pixel step. 105. A method, as claimed in Claim 103, wherein: said electrically interconnecting step comprises etching at least one via down through at least said first thermal insulation layer and to said first semiconductor device without passing through said first said pixel and etching at least one via to at least one of said upper and lower electrodes of said first said pixel. 106. A method, as claimed in Claim 103, further comprising the step of: forming a second thermal insulation layer which overlays both said first semiconductor device and said first said pixel, wherein said forming a second thermal insulation layer step is executed after said executing a first said forming a pixel step and wherein said electrically interconnecting step comprises etching at least one via down through at least one of said second and first thermal insulation layers to said first semiconductor device and etching at least one via down through at least said second thermal insulation layer to said first said pixel. 107. A method, as claimed in Claim 99, further comprising the step of: forming a second thermal insulation layer which overlays said substrate at least in a portion of an area between said first said pixel and said first semiconductor device, said forming a second thermal insulation layer step being executed after said executing a first said forming a pixel step. 108. A method, as claimed in Claim 99, wherein: said barrier layer comprises an oxy-nitride and said encapsulation layer comprises silicon nitride. 109. A device, comprising: a substrate comprising a first semiconductor device; a layer of dielectric material overlaying at least a portion of said substrate and operatively interconnected with said first semiconductor device; a barrier layer overlaying at least said layer of dielectric material; and an encapsulation layer overlaying at least both said barrier layer and said layer of dielectric material, wherein said barrier layer protects said layer of dielectric material from processing associated with said encapsulation layer. 110. A device, as claimed in Claim 109, wherein: said layer of dielectric material is a memory element. 111. A device, as claimed in Claim 109, wherein: said layer of dielectric material is a thermal imaging element. 112. A device, as claimed in Claim 109, wherein: said barrier layer is an oxy-nitride and said encapsulation layer is silicon nitride.

Inventors: BRINKER C JEFFREY, BULLINGTON JEFFREY A, CLEM PAUL G, RUFFNER JUDITH A, SCHWARTZ ROBERT W, TUTTLE BRUCE A, WARREN WILLIAM L, BRINKER, C., JEFFREY, BULLINGTON, JEFFREY, A., CLEM, PAUL, G., RUFFNER, JUDITH, A., SCHWARTZ, ROBERT, W., TUTTLE, BRUCE, A., WARREN, WILLIAM, L.
Applicants: BRINKER C JEFFREY, BULLINGTON JEFFREY A, CLEM PAUL G, RUFFNER JUDITH A, SANDIA CORP, SCHWARTZ ROBERT W, TUTTLE BRUCE A, WARREN WILLIAM L, BRINKER, C., JEFFREY, BULLINGTON, JEFFREY, A., CLEM, PAUL, G., RUFFNER, JUDITH, A., SANDIA CORPORATION, SCHWARTZ, ROBERT, W., TUTTLE, BRUCE, A., WARREN, WILLIAM, L.
Application year: 1998
Main classification: G01J5
IPC codes: G01J1, G01J5, H01L37