System for converting instructions, and method thereto

Abstract: A system (100) has a memory (110), a data bus 120, in a converter (130), and a processor (140). The converter (130) comprises pluralities of buffers (140-143, 150-153), multiplexers (145, 155, 160, 170), and decoders (180, 190). The memory (110) send code words (220) with compressed code bit numbers to the buffers of the converter (130). First multiplexers (145, 155) concatenate the code bits to bitstream, and second multiplexers (160, 170) feed bit clusters (260) with code portions (220) to the decoders (180, 190). The decoder (180, 190) extracts instruction portions (210) which can be executed by the processor (140) at run time without significant delay or intermediate storing. The decoders (180, 190) also provide pointers (S, S') which determine the location of the clusters (260).

Description: Field of the Invention The present invention generally relates to computer systems, and particularly to a converter which is part of the system, and to a method. Background of the Invention Computers can be classified into complex instruction set computers (CISC) and reduced instruction set computers (RISC). The CISC machines conveniently read instruction words with variable length (e.g., 8 bit to 64 bit) in a single software program, wherein the RISC machines often read instructions words with constant length (e.g., 32 bit). The number of possible bit combinations which form the instruction words is often high for CISC and low for RISC. Among others, these features make RISC especially suitable for the integration of processor and memory into a single chip in embedded systems. However, a software program written for RISC may require more memory space than a software program with the same function which runs on a CISC machine. From International patent publication no. WO 95 27244 A there is known a computer system with a RISC processor using 32-bit instructions, certain instructions being stored in 16-bit compressed form and expanded for use by the processor, reducing their fetch time. An instruction is extracted from memory via a set of buffers which are loaded sequentially with 8-bit or 16-bit words. A compressed instruction detector unit expands a compressed instruction and controls a multiplexer to pass either expanded instructions therefrom or full-length instructions direct from the buffers to the processor. The present invention seeks to provide a computer system which mitigates or avoid these and other disadvantages and limitations of the prior art. Brief Description of the Drawings FIG. 1 illustrates a simplified block diagram of a computer system according to the present invention; FIG. 2 illustrates simplified block diagrams of an instruction word and a code word; FIG. 3 illustrates a simplified block diagram of a memory used in the system of FIG. 1; FIG. 4 illustrates a simplified block diagram of a converter used in the system of FIG. 1; and FIGS. 5-6 are simplified diagrams illustrating a method of the present invention to operate the converter of FIG. 4; wherein FIG. 5 is a flowchart diagram and FIG. 6 is a diagram of a bit stream. Detailed Description of a Preferred Embodiment For convenience, a glossary of terms used here and their definitions is provided prior to the claims. Some portions of this description are presented in terms of symbolic representations. Such representations are used by persons skilled in data processing to more effectively convey the substance of their work to other persons. Among others, the representations stand for physical manipulations of physical quantities. Usually, these quantities take the form of electrical, optical, magnetic or other signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. All of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Further, the manipulations performed are often referred to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary or desirable in most cases in any of the operations described herein which form part of the present invention; the operation are machine operations. In all cases the distinction between the method operations in operating a computer and the method of computation itself should be considered. FIG. 1 illustrates a simplified block diagram of computer system 100 of the present invention. System 100 comprises memory 110, bus 120, converter 130, and processor 140. Memory 110 sends code words 220 (details in FIG. 2) in, preferably, compressed form, to converter 130 via bus 120. Converter 130 decodes code words 220 and sends instruction words 210 in, preferably, expanded form, to processor 140. A reverse operation is also possible: Processor 140 sends instruction words 210 to converter 130; converter 130 codes instruction words 210 into code words 220; and bus 120 forwards code words 220 to memory 110. Processor 140 executes the instructions represented by instruction words 210. For the convenience of explanation, it is assumed that converter 130 provides or receives a single instruction word 210 at one time. Bus 120 can carry portions of code words 220 in parallel or serially. Also, bus 120 can simultaneously carry portions which belong to different code words 220. Memory 110 has a plurality of memory lines 115. For simplicity of explanation, it is assumed that data bus 120 carries the contents of a single memory line 115 at one time. More details for memory 110 are explained in connection with a non-limiting example illustrated in FIG. 3. Details of converter 130 are explained in connection with FIG. 4. Computer system 100 can comprise other elements, e.g., address busses, well known in the art. For simplicity, such elements are not illustrated. The present invention has a series of advantages, among them: ( a ) Converter 130 can provide instruction words 210 in real time without significant delay and without significant intermediate memory between converter 130 and memory 140. For example, a cache is not required. ( b ) The software program stored in memory 110 by code portions 220 needs less memory space than with the program stored by uncompressed instruction words 210. ( c ) Conveniently, but not necessarily, system 100 is an embedded system in which memory 110, bus 120, converter 130, and processor 140 are integrated into a single semiconductor substrate. ( d ) Preferably, processor 140 is a RISC machine. FIG. 2 illustrates simplified block diagrams of instruction word 210 (dashed) and code word 220 (dashed). In FIG. 2 and in other figures, data units 230, which are not further divided, have symbols 1 ○ 2 ○ 3 ○ 4 ○ or simply ○. The numbers in the circle symbols (e.g., 1, 2, 3, 4) are collectively referred to by portion index "p". Preferably, data units 230, for convenience hereinafter "bits", represent binary quantities with logical "0" and "1" values, as the case may be. But this is only a convention used for the simplicity of explanation. Those of skill in the art, are able, based on the description herein to use other values. The actual values (e.g., "0" or "1") of bits 230 are not important for the description. The term "instruction" used alone or in combination with other terms is intended to be a convenient label for any information which is supplied to a processor, such as commands, numerical data or text data, and other kind of data. Conveniently, instruction word 210 has a predefined number of P*U instruction bits 231 (e.g., 32 bits) which have symbols . Instruction word 210 is divided into P instruction portions 212@p (conveniently p=1 to P). Preferably, all instruction portions 212@p each comprise an equal number of U(p) = U instruction bits 231. For example and not intended to be limiting, instruction word 210 has P = 4 instruction portions 212@p: e.g., instruction portion 212@1 with U(1) = 8 instruction bits , portion 212@2 with U(2) = 8 instruction bits , portion 212@3 with U(3) = 8 instruction bits and portion 212@4 with U(4) = 8 instruction bits . For convenience, instruction bit indices u (e.g., u = 0 to U-1 = 7) within each instruction portion 212@p are given at the top of the blocks which symbolize instruction portions 212@p. Instruction word 210 is illustrated by a single block of instruction portions 212@1 to 212@P indicating that they are, preferably, used in combination. Instruction word 210 can be transformed to code word 220 with P code portions 222@p (p=1 to P), and vice versa. Code portions 222@p comprise code bits 232 (symbols 1 ○ 2 ○ 3 ○ 4 ○). As shown by unidirectional arrows, coding 241 transforms a single instruction portion 212@p to a single code portion 222@p, and decoding 242 transforms a single code portion 222@p to a single instruction portion 212@p. Code portions 222@p can be conveniently stored, transferred, or otherwise manipulated separately. Preferably, coding 241 is performed with compression so that code portion 222@p has less bits 232 than its corresponding instruction portion 212@p. For example, coding 241 has reduced the number of bits from U(1) = 8 bits in instruction portion 212@1 to V(1) = 3 bits 1 ○ in code portion 222@1. This bit reduction is convenient, but not essential: For example, instruction portion 212@2 (with U(2) = 8 bits ) can be coded to code portion 222@p with V(2) = 12 bits 2 ○. Decoding 242 is, preferably, performed by expanding, i.e. increasing the number of bits. For example, P = 4 code portions 222@p have the following numbers of bits: code portion 222@ 1 with V(1) = 3 code bits 1 ○, code portion 222@2 with V(2) = 12 code bits 2 ○, code portion 222@3 with V(3) = 4 code bits 3 ○, and code portion 222@4 with V(4) = 3 code bits 4 ○. The number of code bits in each code portion 222@p is limited by a minimum number V MIN ("bounded code") and the maximum number V MAX , that is: V MIN ≤ V(p) ≤ V MAX , with the symbol ≤ for smaller than or equal to. In the example used for explanation herein, V(p) has the following values: 3 ≤ V(p) ≤ 12, for all p (p = 1 to P). Some instruction portions 212@p can be coded such that some code portions 222@p (e.g., portions with V(p) > U(p) ) can include or duplicate instruction portions 212@p. Methods and devices for coding and decoding are well known in the art. The following reference [1] gives an introduction to coding and decoding: Bernard Sklar: "DIGITAL COMMUNICATIONS Fundamentals and Applications", published by Prentice Hall, Englewood Cliffs 1998, ISBN 0-13-211939-0, especially chapter 11.6 "Source Coding" on pages 595-667. Therefore, persons of skill in the art are able, based on the description herein, to practice the present invention using known coders and decoders without the need for further explanation. Conveniently, code words 220 used in the present invention are Huffman coded (see sub-chapter 11.6.2 of [1] with a coding tree). The Huffman code is a prefix-free code (e.g., no additional bits between 1 ○ and 2 ○ required) and a variable length code (e.g., V(p) are different). Huffman coding (e.g., coding 241) is assumed only for the purpose of explaining the present invention and not intended to be limiting. Apparatus and method of the present invention can be applied to code words 220 based on other coding 241 and decoding 242 procedures which are already known in the art or which will be developed in the future. The present invention can also be applied for encrypting or decrypting data. Preferably, the number of possible variations (e.g., 2 (U*P) ) of instruction bits 231 is adapted for RISC processors (e.g., processor 140). FIG. 3 illustrates a simplified block diagram of memory 110 used in computer system 100. For convenience, memory 110 is considered as a matrix of memory fields 118@i@j with row indices i (i = 0 to I-1, e.g., I = 6) and column indices j (j = 0 to J-1, e.g., J = 32). Memory fields 118@i@0) to 118@i@(J-1) belong to memory line 115@i (cf. FIG. 1). Preferably, each memory field 118@i@j stores a single bit of information. The majority of J BIT < J (e.g., J BIT = 31) memory fields 118@i@j are "bit fields" and store code bits 232, (cf. FIG. 2, symbols 1 ○ 2 ○ 3 ○ 4 ○ or ○). As mentioned above, the logical values (e.g., "1" or "0") of the code bits are not considered here. For each memory line 115@i, code bits 232 can optionally be classified in two or more groups G(i) ) and G'(i). For convenience of explanation, groups are illustrated by frames 113 surrounding code bits 232. For convenience, at the beginning of each group, frame 113 has sharp comers; and at the end of each group, frame 113 has round corners. Each group G(i) or G'(i) can comprise 1 ≤ L(i) ≤ L MAX code bits. For example, group G(0) comprises L(0) = 12 code bits 1 ○ 1 ○ 1 ○ 2 ○ 2 ○ 2 ○ 2 ○ 2 ○ 2 ○ 2 ○ 2 ○ 2 ○ (in fields 118@0@0 to 118@0@11). The first V(1) = 3 bits 1 ○ of group G(0) (beginning with column index 0, see the sharp frame comer on the left side) belong to code portion 222@1 (cf. FIG. 2) and the other 9 bits 2 ○ of group G(0) belong to the V(2) = 12 bits of code portion 222@2. Group G'(0) comprises L'(0) = 19 code bits 3 ○ 3 ○ 3 ○3 ○ 4 ○ 4 ○ 4 ○ 4 ○ ... ○ (in fields 118@0@12 to 118@0@30). The remaining 3 bits 2 ○ of code portion 222@2 stored in memory line 115@1 and form part of group G(1). The remaining bits in groups G(1) to G(5) belong, preferably to further code portions 222@ 1 and 222@ 2 of further code words. For convenience, the underscoring of symbols (e.g., 1 ○ and 2 ○ ) and reference numbers or indices (e.g., 1 , 2 , p ) indicate further portions. Accordingly, still further portions are indicated by double-underscoring (e.g. 1 ○ and 2 ○ ). For example, the first 4 bits 3 ○ of group G'(0) (beginning with column 30, sharp corner) belong to code portion 222@3; the next 3 bits 4 ○ belong to code portion 222@4; the next 3 bits 3 ○ to further code portion 222@ 3 and so on. The numbers L(i) and L'(i) indicate group lengths by bit numbers. In memory line 110@1, group G(1) has L(1) = 19 code bits b(1,0) to b(1,18) and group G'(1) has L'(1) = 12 code bits b(1,19) to b(1,30), and so on. Optionally, a number of J TAG memory fields 118@j@i of each memory line 118@i have the function of tag fields. Preferably, J TAG + J BIT = J. In the example of FIG. 3, each memory line 118@i has a single tag field 118@30 (J TAG = 1) in column J-1, illustrated at the right side of memory 110. The column position of the tag fields is not important for the present invention. For every memory line 115@i, tag field 118@i@30 stores line tag TAG(i). TAG(i) is an indication for the lengths of groups G(i) and G'(i) in bits. In the example of FIG. 3, TAG(i) can have binary values "1" or "0" which define the group lengths L(i) as follows: L(i) = 12 and L'(i) = 19 for TAG(i) = "1" (e.g., lines i = 0, 2, 3 and 5) L(i) = 19 and L'(i) = 12 for TAG(i) = "0" (e.g., lines i = 1 and 4) Preferably, if group G(i) has a first length (e.g., 19 bits), then group G'(i) has a second length (e.g., 12 bits), and vice versa. Also, group lengths L(i) and L'(i) in combination correspond, preferably, to J BIT , that is: L(i) + L'(i) = J BIT FIG. 4 illustrates a simplified block diagram of converter 130 used in computer system 100. Preferably, the converter elements are 2*B buffers 140, 141, 142, 143, 150, 151, 152 and 153, multiplexers 145, 155, 160, 170, and decoders 180, and 190. For convenience, FIG. 4 also illustrates bus 120 (cf. FIG. 1) as one of the elements. Single lines symbolize the transfer of bits. Double lines 122, 182 and 192 symbolize the transfer of control signal which can, optionally, comprise multiple bits. The arrows on the lines indicate a preferred signal flow and also distinguish inputs and outputs of the elements. For the purpose of explanation, inputs and outputs are identified by representative reference indices within the elements (e.g., 0 to 18 in buffers 140-153). These indices are intended to be non-limiting examples and are counted from 0 to the number of inputs/outputs minus 1. The indices are referred to also by lowercase letters, such as, e.g., "i" and the numbers are given by uppercase letters, e.g., N. Persons of skill in the art are able, based on the description herein, to implement converter 130 with elements which have higher, equal or lower input/output numbers and buffer numbers B than illustrated in FIG. 4. Also, the relation between the numbers is, unless specified in the following text, not essential for the present invention. Preferably, bus 120 has J outputs identified in the text as 120@j (e.g., J = 32, 120@0 to 120@31). The writing convention "reference@index" is conveniently applied hereinafter to other elements. Among the J outputs 120@j, bus 120 simultaneously provides J BIT code bits (e.g., 1 ○ 2 ○ 3 ○ 4 ○, not shown) at outputs 120@0 to 120@(J BIT -1) (e.g., 120@0 to 120@31). Buffers 140-143 and 150-153 each have L MAX inputs and outputs (e.g., L MAX = 19). Outputs 120@0 to 120@(L MAX -1) of bus 120 are coupled to inputs 140@0 to 140@(L MAX -1) of buffer 140, to inputs 141@0 to 141@(L MAX -1) of buffer 141, to inputs 142@0 to 142@(L MAX -1) of buffer 142, and to inputs 143@0 to 143@(L MAX -1) of buffer 143, respectively. Outputs 120@(J BIT -1) (e.g., 120@30) to 120@(J BIT -L MAX ) (e.g., 120@12) are coupled to inputs 150@0 to 150@J MAX of buffer 150, to inputs 151@0 to 151@J MAX of buffer 151, to inputs 152@0 to 152@J MAX of buffer 152, and to inputs 153@0 to 153@J MAX of buffer 153, respectively. Multiplexer 145 has M inputs 145@0 to 145@(M-1). Preferably, number M is related to L MAX as: M ≥ B * L MAX B = 4 (for example) M = 76 (for example) wherein B indicates the number of buffers (e.g., B = 4, buffers 140-143) which are coupled to multiplexer 145. Preferably, multiplexer 145 can service all B = 4 buffers 140-143 simultaneously. Outputs 140@0 to 140@(L MAX -1) of buffer 140 are coupled to inputs 145@0 to 145@(L MAX -1), respectively; outputs 141@0 to 141@(L MAX -1) of buffer 141 are coupled to inputs 145@(L MAX ) to 145@(2*L MAX -1), respectively; outputs 142@0 to 142@(L MAX -1) of buffer 142 are coupled to inputs 145@(2*L MAX ) to 145@(3*L MAX -1), respectively; and outputs 143@0 to 143@(L MAX -1) of buffer 143 are coupled to inputs 145@(3*L MAX ) to 145@(4*L MAX -1), respectively. Similarly, B' is the number of buffers which are coupled to multiplexer 155 (e.g., B' = B = 4, buffers 150-153). Multiplexer 155 has M' inputs 155@0 to 155@(M'-1), that is: M' ≥ 4 * L MAX . M' = M M' = 76 (for example) Outputs 150@0 to 150@(L MAX -1) of buffer 150 are coupled to inputs 155@0 to 155@(L MAX -1) of multiplexer 155, respectively; outputs 151@0 to 151@(L MAX -1) of buffer 151 are coupled to inputs 155@(L MAX ) to 155@(2*L MAX -1), respectively; outputs 152@0 to 152@(L MAX -1) of buffer 152 are coupled to inputs 155@(2*L MAX ) to 155@(3*L MAX -1), respectively; and outputs 153@0 to 153@(L MAX -1) of buffer 153 are coupled to inputs 155@(3*L MAX ) to 155@(4*L MAX -1), respectively. Also, multiplexers 145 and 155 have inputs 146 and 156 coupled to output 120@J-1 (e.g., 120@31) via line 122 to receive line tag TAG(i). Multiplexer 145 has N outputs 145@0 to 145@(N-1) coupled to N inputs 160@0 to 160@(N-1) of multiplexer 160, respectively. Similarly, multiplexer 155 has N' outputs 155@0 to 155@(N'-1) coupled to N' inputs 170@0 to 170@(N'-1) of multiplexer 170, respectively. Conveniently, inputs 160@n and 170@n' are also identified by indices n (e.g., 0 ≤ n ≤ (N-1)) and n' (e.g., 0 ≤ n' ≤ (N'-1)), respectively. The numbers N and N' are conveniently chosen as: N ≥ 2*L MAX + V MAX - 1 N' = N V MAX -1 = 11 (for example) N = 48 (for example) Multiplexer 160 has V MAX outputs 160@0 to 160@(V MAX -1) which are coupled to V MAX inputs 180@0 to 180@(V MAX -1), respectively, of decoder 180. Similarly, multiplexer 170 has V MAX outputs 170@0 to 170@(V MAX -1) which are coupled to V MAX inputs 190@0 to 190@(V MAX -1), respectively, of decoder 190. In other words, multiplexers 160 and 170 move an V MAX wide observation window of decoders 180 and 190, respectively. The term "V MAX - 1" in equation (14) conveniently results from the worst case in which a single code portion 222@p is stored in two adjacent buffers (e.g., 140-143) with one bit in one buffer and the other V MAX - 1 bits in the adjacent buffer. Decoder 180 has control output 181 coupled to control input 161 of decoder 160 via line 182; and decoder 190 has control output 191 coupled to control input of decoder 170 via line 192. Decoder 180 has U outputs 180@0 to 180@(U-1) for consecutively providing instruction portions 212@1 (cf. FIG. 2) with instruction bits and instruction portions 212@2 with instruction bits . Decoder 190 has U outputs 180@0 to 190@(U-1) for consecutively providing instruction portions 212@3 with instruction bits and instruction portions 212@4 with instruction bits . Buffers 140-143 and 150-153 are intended to be storage means, while multiplexers 145, 155, 160 and 170 and decoders 180 and 190 are not intended to be storage means. Decoders 180 and 190 can be implemented, for example, and not intended to be limiting, by look-up tables or by logic circuits which perform decoding according the code tree, or by other means which are well known in the art. Decoders 180 and 190 can send instruction portions 212@p to processor 140 without significant delay. Preferably, decoders 180 and 190 operate under real-time conditions and can provide instruction portions 212@p when required by processor 140. FIGS. 5-6 are simplified diagrams illustrating method 300 of the present invention to operate converter 130. As illustrated in the flow chart diagram of FIG. 5, method 300 comprises storing step 310, concatenating step 320, selecting step 330, and decoding step 340. The diagram of FIG. 6 gives more details for concatenating step 320, selecting step 330 and decoding step 340 by way of example. Steps 310-340 are, preferably, executed consecutively. Optionally, some steps can be executed simultaneously with different data sets. Pipelining is well known in the art, so that persons of skill in the art able, based on the description herein, to implement pipelining. For convenience, method 300 is explained in connection with buffers 140-143, multiplexers 145 and 160, and decoder 160 illustrated on the left side of FIG. 4. It is explained in detail how converter 130 converts unprimed groups G(i) (see FIG. 3) of code bits 1 ○ and 2 ○ and provides instruction portions 212@1 and 212@2 with instruction bits and . Persons of skill in the art will understand without the need of further explanation how the converter elements of the right side of FIG. 4 (buffers 150-153, multiplexers 155 and 170, and decoder 190) operate accordingly and how they convert primed groups G'(i) with code bits 3 ○ and 4 ○ to instruction portions 212@3 and 212@4 with instruction bits and . Method 300 can be executed by elements on one side alone and can thereby be applied to all code bits 1 ○ 2 ○ 3 ○ 4 ○ and all instruction bits . Details for steps of method 300 are given in the following. For convenience of explanation, in steps 310-330, the code bits are given with the p-indices. However, buffers 140-143, 150-153 and multiplexers 145, 155, 160 and 170 which participate in steps 310-330, do not need to distinguish to which portion 222@p a particular code bit ○ belongs to. Storing step 310 : Bus 120 consecutively sends groups G(i) of code bits to buffers 140-143 which store groups G(i). For example, the 12 code bits 1 ○1 ○1 ○2 ○2 ○2 ○2 ○2 ○2 ○2 ○2 ○2 ○ of group G(0) (cf. FIG. 3, e.g., TAG(0) = "1") go into buffer 140 (e.g., outputs 120@0 to 120@11, inputs 140@0 to 140@11). The numbers p = 1 and p = 2 within the circles are not important here and given only for convenience. Conveniently, buffers 140-143 and multiplexers 145 and 160 do not distinguish to which code portions 222@p the code bits belong to. In the next repetition, the code 19 bits 2 ○2 ○2 ○ 1 ○ 1 ○ 1 ○ 1 ○ 1 ○ 2 ○ 2 ○ 2 ○ 2 ○ 1 ○ 1 ○ 1 ○ 1 ○ 1 ○ 1 ○ 1 ○ of group G(1) go into buffer 141 (e.g., TAG(1) = "0", outputs 120@0 to 120@18, inputs 141@0 to 141 @18); then the 12 code bits ○ of group G(2) go into buffer 142; and finally the 12 code bits ○ of group G(3) go into buffer 143. Buffers 140-143 conveniently store the bits until they are no longer needed (details later). In a next cycle, bus 120 sends the bits of group G(4) to buffer 140 and so on. Storing step 310 can require enabling / disabling of buffer inputs or switching of bus output 120@j to buffer inputs well understood by a person of skill in the art. Conveniently, bus 120 can also send bits ○ from neighboring group G'(i) to buffers 140-143 wherein the bits from G'(i) are disregarded in the next step. For example, bus 120 sends the 12 bits of group G(0) to buffer 140 and sends bits ○ of group G'(0) (from memory.fields 118@0@12 to 118@0@18) to buffer 140. This is convenient, but not essential for the present invention. Concatenating step 320: Multiplexer 145 receives tag bit TAG(i) at input 146 and the code bits from groups G(i) at inputs 145@m. Multiplexer 145 concatenates the bits to bit stream 250 (example in FIG. 6) at outputs 145@n according to the tag bits TAG(i). For example, but not intended to be limiting, bit stream 250 (FIG. 6) can start with the following bits: 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 ... For convenience, numbers at the top of the bit symbols indicate index n. In the example, bit stream comprises V(1) = 3 code bits 1 ○ of code portion 222@ 1 at inputs 160@0 to 160@2 of multiplexer 160, V(2) = 8 code bits 2 ○ of code portion 222@2 at inputs 160@3 to 160@14, V( 1 ) = 5 code bits 1 ○ of further code portion 222@ 1 at inputs 160@15 to 160@19, V( 2 ) = 4 code bits 2 ○ of further code portion 222@ 2 at inputs 160@20 to 23, and an unspecified number of code bits 1 ○ of still further code portion 222@ 1 . Bitstream 250 is available also at inputs 160@n of multiplexer 160. Selecting step 330: Multiplexer 160 receives bit stream 250 from multiplexer 145 and receives shift pointer S at input 161 from decoder 180. Multiplexer 160 consecutively sends clusters 260@p (frames in FIG. 6) etc. of V MAX code bits to inputs 180@0 to 180@(V MAX -1) of decoder 180. Initially, shift pointer S is S = 0 so that multiplexer 160 provides cluster 260@ 1 with the first V MAX code bits. In the example, cluster 260@ 1 comprises V MAX code bits 1 ○1 ○1 ○2 ○2 ○2 ○2 ○2 ○2 ○2 ○2 ○2 ○ (from inputs 160@0 to 160@11). With the next repetition of step 330, shift pointer is changed to S = 3 which corresponds to the number S = V(1) of code bits in code portion 222@ 1 (details in the next step). Multiplexer 160 provides cluster 260@2 with bits 2 ○2 ○2 ○2 ○2 ○2 ○2 ○2 ○2 ○2 ○2 ○2 ○ (from inputs 160@3 160@14). Multiplexer 160 can twice or even more times send the same code bits to decoder 180. For example, the 9 code bits 2 ○2 ○2 ○2 ○2 ○2 ○2 ○2 ○2 ○ which have initially belonged to cluster 260@1 now belong to cluster 260@2. Shift pointer S is now S = 12 and multiplexer 160 provides cluster 260@ 1 with bits 1 ○ 1 ○ 1 ○ 1 ○ 1 ○ 2 ○ 2 ○ 2 ○ 2 ○ 1 ○ 1 ○ 1 ○ (from inputs 160@15 to 160@26). Then (next repetition), shift pointer S becomes S = 5 and multiplexer 160 provides cluster 260@ 2 with the bits from input 160@20 to 160@32. Preferably, multiplexer 160 can form further clusters by connecting inputs in an wraparound mode (e.g., input 160@(N-1) to output 160@0, input 160@0 to output 160@1). Decoding step 340: Decoder 180 consecutively receives clusters 260@p. After receiving a single cluster 260@p, decoder provides U instruction bits belonging to instruction portion 212@p. Also, decoder 180 determines the number V(p) of code bits in code portion 222@p and provides shift pointer S (at output 181) according to: S = V(p) For example, decoder 180 receives the V MAX = 12 code bit of cluster 260@ 1 and provides the U = 8 instruction bits of instruction portion 212@1 by decoding bits 1 ○1 ○1 ○ and determines that code portion 222@ 1 has V(1) = S = 3 code bits 1 ○1 ○1 ○. In the next repetition of decoding step 340, decoder 180 receives cluster 260@2, provides U = 8 instruction bits of code portion 222@2 and S = 12. As mentioned above, code portion 222@2 has the maximum possible number V MAX = 12 of bits. Next, decoder 180 receives cluster 260@ 1 and decodes bits 1 ○ 1 ○ 1 ○ 1 ○ 1 ○ to further instruction portion 212@ 1 with bits . It is well known in the art, how decoder 180 can obtain S = V(p) from a cluster 260@p which has code bits belonging to different code portions 210@p and 210@p'. However, having shift pointer S obtained and used in a feed back scheme from decoding step 340 to selecting step 330, is convenient, but not essential for the present invention. Those of skill in the art, are able, based on the description herein, to derive shift pointer otherwise, for example, from a multibit tag line TAG(i). In other words, method 300 of the present invention can also be described as a data converting method for converting code portions 222@p with code bits 232 to instruction portions 210@p with instruction bits 231, comprising in repetitions the steps of: (a) storing groups of code bits in buffers (e.g., G(i) to buffers 140-143); (b) concatenating the groups of code bits to a bitstream (e.g., bitstream 250); (c) selecting clusters of code bits (e.g., clusters 260) from the bitstream, wherein each cluster comprises at least one code portion (e.g., cluster 260@1 with portion 222@1); and (d) decoding code portions to instruction portions (e.g., portion 222@ 1 to 210@1) and providing a shift pointer (e.g., S = 3) which is recursively used in the selecting step to identify new clusters (e.g., cluster 260@2). Conveniently, (i) each group G(i) comprises a predefined number of code bits (e.g., 12 bits or 19 bits); (ii) in the storing step, code bits which do not belong to a given group are also stored in the buffers (e.g., 7 bits of G'(0) also into buffer 140) and (iii) in the concatenating step only the code bits which belong to a predetermined group are concatenated (i.e., multiplexer 145 disregards the bits of G'(i)). Code portions 222@p and instruction portions 210@p are conveniently related by Huffman coding. Further, method 300 of the present invention can also be described as a method for converting code portion 222@p having V MIN ≤ V(p) ≤ V MAX code bits to a corresponding instruction portion 212@p having U(p) instruction bits, with the following steps of: (i) distributing groups G(i) of L(i) ≤ L MAX code bits to a plurality of B buffers identified by index b (e.g., b = 1 for buffer 140, b = 2 for buffer 141, b = 3 for buffer 142 and b = B = 4 for buffer 143), wherein each group G(i) comprises a code portion 222@p or a further code portion 222@(p+1), and buffer b = (mod B i) (modulo operation to the base B) stores at least a single group G(i) (cf. storing step 310); (ii) combining the L(i) code bits of group G(i) to the L(i+1) code bits of group G(i+1) and so on to bitstream 250 (cf. concatenating step 320); and (iii) sending clusters (e.g., 260@1) of V MAX code bits which comprise the code bits of code portion 222@p from bitstream 250 to decoder 180 which provides instruction portion 210@p (cf. selecting step 330 and decoding step 340). Optionally, some code portions have code bits located in groups G(i) and G(i+1), as for example in reference to FIG. 3, some bits 2 ○ of portion 222@2 in G(0) and some bits 2 ○ in G(1). Optionally, distributing, combining, and sending steps are performed cyclically and in a pipeline. For example, while decoder 180 is decoding cluster 260@ 1 , buffer 140 can already receive a new group G(i). In the sending step, the clusters are cyclically modified by disregarding S old code bits and adding S new code bits, with S = V(p-1) being the number of code bits of a previous code portion p-1. For example, in reference to FIG. 6, bits 1 ○ 1 ○ 1 ○ of cluster 260@1 (p = 1) are disregarded and bits 2 ○ 2 ○ 2 ○ of portion 222@2 (p = 2) are added. While the invention has been described in terms of particular structures, devices and methods, those of skill in the art will understand based on the description herein that it is not limited merely to such examples and that the full scope of the invention is properly determined by the claims that follow. Glossary of Terms 1 ○2 ○3 ○4 ○ ○ symbols for code bits, optionally with index p in the circle symbols for instruction bits, index p in the circle "1" or "0" binary values e.g., 1 ○ (single underscoring) for belonging to further code portions e.g., 1 ○ (double underscoring) for still further code portions @ used to combine reference numbers with indices b buffer index B number of buffers G(i), G'(i) group identifier i row index I number of memory rows j column index J number of memory columns, J = J BIT + J TAG J BIT number of bit fields J TAG number of tag fields L(i) and L'(i) group length L MAX buffer length (number of inputs and outputs) m, m' input indices of multiplexer n, n' output indices of multiplexer M, M' number of inputs of multiplexer N, N' number of inputs/outputs of multiplexer p portion index P number of portions S, S' shift pointer TAG(i) line tag u index for instruction bits U(p), U number of instruction bits in instruction portion V(p) variable number of code bits in code portion V MIN , V MAX minimum and maximum numbers of code bits in code portions, number decoder inputs

Claims: A system (100) which converts code portions identified by index p each having a variable number V(p) ≤ V MAX of code bits to corresponding instruction portions identified by index p each having U(p) instruction bits, said system comprising: a first plurality of B buffers (140-143) each having L MAX inputs and L MAX outputs, said buffers consecutively receiving variable length groups G(i) with L(i) ≤ L MAX code bits from a data bus (120) and; a first multiplexer (145) having a plurality of M inputs coupled to said outputs of said buffers and concatenating said groups of code bits to a bitstream at a plurality of N outputs; a second multiplexer (160) having a plurality of N inputs coupled to said N outputs of said first multiplexer and providing clusters with code bits of said first bitstream according to a shift pointer, such that each cluster comprises at least the code bits of one of said code portions; and a first decoder (180) having V MAX inputs receiving one cluster at a time, providing said instruction portions of U(p) bits by decoding, and providing said first shift pointer S which corresponds to the number of code bits V(p) of the code portion which has been decoded as part of said cluster. The system of claim 1 wherein N ≥ 2 * L MAX + V MAX - 1 and M ≥ B * L MAX . The system of claim 1 wherein said clusters each comprise V MAX code bits. The system of claim 1 wherein some of said clusters comprise code bits belonging to neighboring code portions. The system of claim 1 wherein said first multiplexer receives an indication for L(i) from said data bus. The system of claim 5 wherein said indication for L(i) is a tag bit TAG(i) and indicates either a first group length or a second group length. The system of claim 1 further comprising: a second plurality of B' further buffers (150-153) each having L MAX inputs and L MAX outputs, said further buffers consecutively receiving further variable groups G'(i) of L'(i) ≤ L MAX further code bits from said data bus; a third multiplexer (155) having a plurality of M' inputs coupled to said outputs of said further buffers and concatenating said further groups of code bits to a second bitstream at a plurality of N' outputs; a fourth multiplexer (170) having a plurality of N' inputs coupled to said N' outputs of said third multiplexer and providing further clusters with code bits of said second bitstream according to a second shift pointer S', such that each further cluster comprises at least the code bits of one of said further code portions; and a second decoder (190) receiving said further clusters, also providing instruction portions by decoding, and providing a second shift pointer S'. The system of claim 7 wherein N' = N, M' = M, and L(i) + L'(i) = J BIT with J BIT being the number of code bits which said data bus can supply simultaneously. The system of claim 7 wherein (a) p = 4 code portions p = 1 to p = 4 are converted to p = 4 instruction portions p = 1 to p = 4, respectively; (b) groups G(i) comprise code bits of code portions p = 1 and p = 2, further groups G'(i) comprise code bits of code portions p = 3 and p = 4; and (c) said system uses said first plurality of buffers, said first and second multiplexers, and said first decoder to convert code portions p = 1 to p = 2 and uses said second plurality of buffers, said third and fourth multiplexers, and said second decoder to convert code portions p = 3 and p = 4. The system of claim 1 wherein U(p) = U for all p. The system of claim 1 further comprising a processor (135) which executes instruction words each having p instruction portions. The system of claim 1 further comprising: a memory (110) storing said groups G(i) and sending said groups G(i) to said data bus; and a processor (135) receiving said instruction portions without significant delay. The system of claim 1 further comprising a memory (110) coupled to said first plurality of said buffers via said data bus and a processor (135) coupled to said first decoder; said memory, said buffers, said first and second multiplexers and said first decoder being integrated into a single semiconductor substrate. A data converting method (300) for converting code portions with code bits to instruction portions with instruction bits, said method comprising in repetitions the steps of: (a) storing (310) groups of code bits in buffers; (b) concatenating (320) said groups of code bits to a bitstream; (c) selecting (330) clusters of code bits from said bitstream, wherein each cluster comprises at least one code portion; and (d) decoding (340) code portions to instruction portions and providing a shift pointer which is recursively used in said selecting step to identify new clusters. The method of claim 14 wherein (a) said groups each comprise a predefined number of code bits; (b) in said storing step, code bits which do not belong to a given group are also stored in said buffers and (c) in said concatenating step only the code bits which belong to a predetermined group are concatenated. The method of claim 14 wherein said code portions and said instruction portions are related by Huffman coding. The method of claim 14 for converting a code portion p having V MIN ≤ V(p) ≤ V MAX code bits to a corresponding instruction portion p having U(p) instruction bits, wherein: said step of storing comprises distributing groups G(i) of L(i) ≤ L MAX code bits to a plurality of B buffers identified by index b, wherein each group G(i) comprises a code portion p or a further code portion p+1, and buffer b = (mod B i) stores at least a single group G(i); said step of concatening comprises combining the L(i) code bits of group G(i) with the L(i+1) code bits of group G(i+1) to form a bitstream; and said steps of selecting and decoding comprise sending clusters of V MAX code bits which comprise the code bits of code portion p from said bitstream to a decoder which provides the instruction portion p. The method of claim 17 wherein some code portions have code bits located in groups G(i) and G(i+1). The method of claim 17 wherein said distributing, combining, and sending steps are performed cyclically and in a pipeline. The method of claim 17 wherein in said sending step, said clusters are cyclically modified by disregarding S old code bits and adding S new code bits, with S = V(p-1) being the number of code bits of a previous code portion p-1.

Inventors: GINSBERG AVI, GROBMAN ALEXANDER, MIRETSKY ALEX, GINSBERG, AVI, GROBMAN, ALEXANDER, MIRETSKY, ALEX
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1998
Main classification: G06F9
IPC codes: G06F9