PHASE-LOCKED LOOP AND METHOD FOR AUTOMATICALLY LOCKING TO A VARIABLE INPUT FREQUENCY

Abstract: An apparatus is provided for automatically and dynamically adjusting a frequency division factor of a clock divider situated in the feedback loop of a phase-locked loop (PLL). The frequency division factor is modified based on changes in the input signal frequency forwarded to the PLL. If the input signal frequency increases, the decision circuit coupled to the input of the voltage controlled oscillator records that change as an encoded digital signal. That signal will accordingly modify the current frequency division factor dependent on current division factor as well as the current input signal frequency. The decision circuit can be modeled as an A/D converter, and the control unit placed between the decision circuit and the clock divider can be modeled as a state diagram. Each state of the state diagram is indicative of a frequency division factor, or a change in that division factor, wherein the coded digital signal indicates possible change from one state to another. By modifying the frequency division factor, the PLL can dynamically lock upon a changed input signal frequency without varying the clocking signal output from the PLL. Thus, the PLL can accommodate various input signal frequencies yet maintain a relatively fixed clocking signal to be forwarded as a timing reference to a digital processor.

Description: PHASE-LOCKED LOOP AND METHOD FOR AUTOMATICALLY LOCKING TO A VAR IABLE INPUT FREQUENCY BACKGROUND OF THE INVENTION 1 Field of the Invention This invention relates to an integrated circuit and. more particularly to a phase-locked loop ("PLL") which can, within the feedback loop of the PLL. automatically detect and incrementally or directly lock upon a change in frequencv of an mput signal without substantially changmg the PLL output signal frequency 2 Descπption of the Related Art A PLL is generally used m many areas of electronics to control the frequency and/or phase of a signal Instances of use mclude, for example, applications as frequency synthesizers, analog-to-digital modulators, and clock recovery circuits As a clock recovery circuit, a PLL extracts a timing reference from, for example, an incoming data stream The timing reference, or recovered clock, is typically synchronized to transitions of data within the data stream The timing reference is output from the PLL arranged at the receivmg end of, for example, a transmission channel Usmg a PLL at the receivmg end to reconstruct a clocking signal avoids having to forward with the data a separate clocking signal It is often desirable to modify the transition rate, or frequency, of the data stream forwarded across a transmission channel Thus, a PLL at the receive end of the transmission channel must be capable of accepting an mput signal at a variety of frequencies If the mput signal comprises data, it is important that the PLL support both regular and high-speed data rates If the mput signal is a clockmg signal, the PLL must therefore accept and be able to choose among a variety of clockmg frequencies While the mput signal frequency to the PLL can vary dependmg on the transmission rate of the transmission mechanism (l e . transmitter, receiver and channel) it is generally desned that a digital circuit coupled to the PLL output run at a relatively fixed rate In most mstances, the clockmg frequency of the digital circuit or digital processor must run at a frequency within the manufacturer specified frequency range Thus, when the PLL is locked upon the mput signal frequency, the output signal (hereinafter "clockmg signal") from the PLL must not exceed (or be less man) the operatmg specification of the digital circuit or digital processor If the mput signal frequency should change given, for example, an mcrease m data rate, the PLL will attempt to lock upon the changed mput signal frequency In most cases, a PLL is used in applications where the clockmg signal frequency output from the PLL must be a multiple of the mput signal frequency This aπses smce, m most mstances, the digital processor can operate at a higher frequency than the transmitted data stream To achieve a static discrepancy between the mput signal and clockmg signal frequencies, a clock divider is situated m the feedback loop of the PLL The clock divider compπses a frequency division factor An mcrease m the division factor will proportionally mcrease the clockmg signal frequency relanve to the mput signal frequency Thus, for example, if the mput signal frequency is at 1 Ox and division factor is 16, then the clockmg signal frequency is 16 Ox An unfortunate aspect of the division factor is that it is typically static with changes m the mput signal frequency The inability to automatically or dynamically change commensurate with changes m the mput signal frequency causes numerous problems with respect to the clockmg signal A static (or fixed) division factor presents a feedback signal frequency that will be momentarily dissimilar from an mcreasmg mput signal frequency durmg mstances of "unlock" This will cause an mcrease m DC voltage to the PLL voltage controlled oscillator ("VCO"), resultmg in an mcrease m the clockmg signal frequency Once the clockmg signal achieves a steady state value, and the clockmg signal is divided m the PLL feedback loop to substantially match the mput signal frequency, then the PLL is said to be "locked" Unfortunately, when locked, the clockmg signal may exceed the maximum frequency of the digital processor to which the clockmg signal is connected If this should occur, then the digital processor may lose its internal state and/or malfunction Furthermore, if the clockmg signal exceeds the maximum frequency of the digital processor, the VCO may be forced outside its dynamic operatmg range SUMMARY OF THE INVENTION The problems outlmed above are m large part solved by improvements to the PLL Improvements involve, for example, inserting a decision circuit between the loop filter and VCO of the PLL The decision cncuit monitors DC voltage applied to the VCO indicative of a change m frequency of the mput signal The decision cncuit presents a coded signal to a control unit indicative of the DC voltage relative to one or more threshold voltages The control unit responds to the coded signal by either maintaining or modifymg the frequency division factor within the clock divider of the PLL feedback loop Input to the VCO is therefore indicative of the frequency of the mput signal The decision cncuit m combmation with the control unit provide a control function that can select an appropπate division factor based on the DC voltage at the mput of the VCO The decision cncuit can be implemented as, for example, an analog-to-digital ("A/D") converter which essentially takes a DC value and produces a digital coded signal based on the relationship of the that DC value to one or more reference voltages The control unit can be implemented m hardware or software to recognize vaπous digital encoded signals m dissimilar ways and to produce a unique modification of the division factor dependent on the existing (current) division factor M or the existmg division factor M and the existing (current) mput signal frequency The decision cncuit and control unit serves to adapt the PLL via the clock divider to high speed and low speed incoming data and/or clockmg mput frequencies If the mput signal frequency should mcrease to accommodate a faster data stream, the decision cncuit will respond by dispatchmg a coded signal based on an mcrease m the DC voltage at the mput of the VCO, relative to a reference voltage The coded signal will the be interpreted by the control unit based on the current status of the clock divider division factor Dependmg on how the control unit is programmed, an mcrease m the mput signal frequency may preferably cause a proportional decrease in the frequency division factor of the clock divider This will result m two important outcomes Fnst, the feedback signal frequency forwarded from the clock divider, based on the new frequency division factor, will substantially equate to the mput signal frequency thereby locking the PLL m a rapid fashion Without a differential between the feedback signal frequency and the mput signal frequency, the DC voltage will quickly transition back to a mid-scale, locked value relative to the voltage reference values so as not to cause further transitions of the frequency division factor. Second, the clocking signal output from the PLL will retain its previous frequency and will be minimally affected in the interim when the increased input signal frequency , occurs and the time in which the frequency division factor is changed. Accordingly, the present apparatus and/or circuit achieves a rapid locked status to a variable input signal frequency without modifying or varying the clocking signal forwarded to, for example, a down-stream digital circuit. As an alternative, the feedback signal frequency may not substantially equate to a changed input signal frequency after a first iterative change of the frequency division factor. The DC voltage may remain or transition back above threshold even after die frequency division factor is changed. Another (second and subsequent) iterative change may be needed to cause the DC voltage to remain at mid-scale (i.e., to lock the input and output signal frequencies). In instances where the current output signal frequency is known and the frequency division factor is (after one or more iterative changes) known, then the present technique can be used to determine the frequency of the changed (i.e., next) input signal or data rate. The decision circuit and control unit thereby allow automatic detection of the input signal frequency either directly or through iterative changes in the division factor. A direct change needed to rapidly lock upon the input signal implies a high resolution frequency division factor, the magnitude of differences between a current divider state and a next divider state can be any integer or fractional number. Broadly speaking, the present invention contemplates a PLL. The PLL comprises a clock divider circuit arranged within a feed back loop of the PLL. The clock divider comprises a frequency division factor adapted to be preferably modified inversely proportional to a change in the frequency of an input signal forwarded to the PLL. The frequency division factor is modified by multiplying a current frequency division factor by a positive number M greater than 1.0, and wherein the change in frequency of the input signal is modified by multiplying a current frequency of the input signal by 1/M. Alternatively, the frequency division factor can be modified by multiplying a current frequency division factor by 1/M, such that the change in frequency of the input signal is modified by multiplying a current frequency of the input signal by M. The present invention further contemplates an apparatus. The apparatus is coupled to receive an input signal frequency and produce an output signal frequency (i.e., clocking signal frequency). A phase detector and loop filter are coupled to produce a DC voltage corresponding to a difference between the input signal frequency and the output signal frequency reduced by a division factor. A VCO is coupled to receive the DC voltage and change the output signal frequency dependent on die DC voltage. A clock divider circuit is coupled to receive the output frequency and, in accordance with the division factor, forward the output signal frequency reduced by a division factor to the phase detector. A decision circuit is coupled to receive the DC voltage and produce a coded signal based on the comparison of the DC voltage to the reference voltage. A control unit is coupled to receive the coded signal and automatically (dynamically) modify the frequency division factor in response thereto. The present invention yet further contemplates a method for automatically and dynamically changing a clock divider within a feedback loop of a PLL. The clock divider is changed in order to directly or iteratively lock the frequency of the clocking signal to the frequency of an input signal. The method further includes steps of monitoring a DC voltage from a detector which compares phase and frequency of a feedback signal to the input signal. The frequency of the feedback signal can be changed to substantially match a change in frequency of the mput signal while maintaining substantially constant the frequency of the output signal. The feedback signal frequency is changed based on a compaπson of a reference voltage to the DC voltage pπor to the readjustment of the feedback signal to bring the feedback signal frequency m lme agam with the changed mput signal frequency BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of die invention will become apparent upon readmg the following detailed description and upon reference to the accompanymg drawings m which: Fig 1 is a block diagram of a PLL accordmg to the present invention configured to receive and lock upon a frequency of an mput signals havmg a vaπable frequency; Fig. 2 is cncuit diagram of a decision cncuit as shown in Fig. 1 accordmg to one exemplary embodiment; and Fig. 3 is a state diagram of a control unit as shown m Fig. 1, accordmg to one exemplary embodiment, for performmg iterative rangmg/detection of the PLL frequency division factor to a change m frequency of the mput signal; Fig. 4 is a state diagram of a control unit as shown m Fig. 1, accordmg to one exemplary embodiment, for performing direct detection of the PLL frequency division factor to a change m frequency of the mput signal; and Fig. 5 is a state diagram of the control unit as shown m Fig. 1, accordmg to a more generalized, exemplary embodiment, for performmg iterative rangmg detection and dnect, high resolution rangmg/detection of the PLL frequency division factor to a change m frequency of the mput signal. While the invention is susceptible to vaπous modifications and alternative forms, specific embodiments thereof are shown by way of example m the drawings and will herem be descπbed in detail. It should be understood, however, that the drawings and detailed descπption thereto are not intended to limit the invention to the particular form disclosed, but on die contrary, the mtention is to cover all modifications, equivalents and alternatives falling within the spmt and scope of the present invention as defined by the appended claims DETAILED DESCRIPTION OF THE INVENTION Turning now to the drawings, Fig. 1 illustrates a signal 10 mput to a PLL 12. The mput signal can be forwarded at different frequencies, shown as x, mx and x/m, wherem m represents a vaπation of the base frequency x. If a need exists for a higher data rate, for example, then the mput signal frequency can be mcreased; the same applies if the data rate must be reduced. The frequency of the mput signal is mostly a function of the transmitting and receivmg component and d erefore can vary dissimilar from the components within PLL 12 PLL 12 mcludes, accordmg to one example, a phase/frequency ("PFD") detector 14, a loop filter 18, a VCO 20 and a clock divider 22. Clock divider 22 is placed m me feedback loop of PLL 12, and provides a multiplication factor between the mput signal frequency and a higher frequency output signal. PFD 14 can be formulated, for example, as a multiplier (or mixer) compπsmg an exclusive OR gate, a R-S latch or, m the instance of frequency detection, any cncuit which produces non-complimentary outputs proportional to die frequency differences between the mputs Loop filter 18 may be implemented with passive elements compnsmg a capacitor and a resistor linked between conductors bearing the output from PFD 14 and the mput to VCO 20 Loop filter 18 may serve to remove transient noise from the rail-dπven signal forwarded from PFD 14, and therefore provides stability to the loop That noise may be attπbuted to, for example, mput signal flicker and/or PFD 14 transient conditions VCO 20 may be implemented, for example, as a ring oscillator compnsmg, for example, an odd number of seπes-connected inverters The components shown m PLL 12 can be made m numerous different ways The mechanism and cncuitry needed to embody each component can vary dependmg on the accuracy and application desned The examples descπbed are therefore only examples of ways to implement each component Vaπations and modifications may be made to the form and structure of each component as mandated by me application m which the components are placed VCO 20 is designed to produce a peπodic output whose frequency is a lmear function of the DC voltage forwarded from loop filter 18 If the DC voltage increases, for example, then VCO 20 will mcrease the output signal frequency The output signal is forwarded to the digital cncuit coupled as a load to PLL 12 as well as to clock divider 22 Clock divider 22 mcludes a frequency division factor which enables the output signal (clockmg signal) frequency to be a multiple of the mput signal frequency Thus, the clockmg signal frequency is reduced (l e , divided) before it is fed back to PFD 14 The frequency division factor M is modified m real-time dependmg on the amount of frequency multiplication needed Thus, factor M is a number equal to or greater than 1 0 If M is an mteger, frequency division can be suitably performed, for example, by a digital counter Included widi or separate from PLL 12 is a decision cncuit 30 and a control unit 32 Decision cncuit 30 is essentially a A/D converter which encodes m digital form the compaπson of a reference voltage (or reference voltages) to the DC voltage forwarded to VCO 20 For example, there may be two reference voltages in the simplest form A first reference voltage can be configured between the mid-scale voltage and V DD , whereas the second reference voltage may be placed between the mid-scale voltage and ground If, for example, die DC voltage exceeds die first reference voltage, (possibly indicating a rapid πse m the mput signal frequency) the decision cncuit will encode a binary signal mdicatmg mat πse The converse is true if the mput signal frequency decreases and the DC voltage extends below the second reference voltage to produce anotiier, uniquely encoded signal It is recognized mat, however, more than two reference voltages may be used If die DC voltage exceeds midscale and one but not anotiier reference voltage, the digital signal resultmg from the compaπson will have sufficient binary bits to indicate the wmdow between reference voltages at which the DC voltage resides Fig 2 illustrates one example of decision cncuit 30 which generally performs A/D encodmg If two reference voltages are used, dien a first comparator 34 will produce a digital "1" value if die DC voltage exceeds die first reference voltage v t+ A second comparator will produce a digital "1" value if the DC voltage is less than a second reference voltage v, Accordmg to one example, the first reference voltage may be a value between mid-scale and V DD while the second reference voltage is between mid-scale and ground Of course, tiiere may be numerous other comparators and associated reference voltages The additional reference voltages may be spaced quantifiable distances from one another between ground and V DD to enhance resolution of die A/D converter output. The example shown m Fig. 2 presents a coded two-bit output However, additional comparators and associated reference voltages can encode more than two binary bits if additional resolution of PLL frequency is desned Two comparators and two reference voltages provide a two bit binary value indicative of whether the DC voltage is. (1) above v t+ , (2) between v t and v t+ , or (3) below v t Additional comparators and reference voltages allow indication of where die DC voltage is within a closely defined voltage range Given close indication of DC voltage, control unit 32 may more rapidly (and dnectly) respond to diat voltage by transitioning to an appropπate "next" divider state knowing die current divider state. If, however, only two comparators are used, then an auto rangmg function can occur. More particularly, an iterative change m divider state can occur to ultimately achieve the dnect change afforded by the high resolution. Fig 3 illustrates the iterative detection technique, while Fig 4 illustrates dnect detection. Fig. 3 is a state diagram 40 used in implementing control unit 32 accordmg to an iterative, auto-rangmg technique. Diagram 40 illustrates three states 42, 44 and 46. State 42 mdicates a decrement m the frequency division factor within clock divider 22 if die mput signal frequency, as registered by die DC voltage on decision circuit 30, is above an upper threshold (e.g., v t+ ). If the mput signal frequency is not too high, then transition will occur to state 44 indicative of DC voltage between the upper and lower thresholds Further, if the DC voltage extends below die lower threshold mdicatmg a low frequency, men transition will occur toward state 46 from state 44 State diagram 40 presumes three detectable levels and two comparators, and die next level is adjacent me current level m magnitude For example, if d e current mput frequency is 4x and die next mput frequency mcreases to 16x, then die DC value will extend above the upper threshold and be coded as a "frequency too high" signal upon die control unit The control unit responds as shown by state diagram 40 by decrementing the division factor from, e.g., a - 16 to a - 15. Decrementing continues if the decision cncuit again codes a frequency to high signal until eventually die proper frequency division factor is reached, e g , - 4 At least one benefit in die iterative approach is its use as an mput signal frequency detector Knowing that die output signal frequency must remam relatively fixed and further knowing the current frequency division factor, one can determine the next mput signal frequency when or if the mput signal frequency changes. The iterative approach will change accordmg to defined increments (i.e., mtegers and/or fractions) die division factor whenever the DC voltage exceeds or is less tiian the threshold values. Those increments will eventually cause die DC voltage to remam near midscale mdicatmg state 44 and a corresponding locked condition. The frequency division factor at state 44 will be known along witii the unchanged output signal frequency to tiiereby allow detection of the changed (i.e , next) mput signal frequency Fig. 4 is a state diagram 48 used to implement control unit 32 accordmg to a more dnect, rapid detection/locking function More man two levels and tinee comparators are requned if it is necessary to change die division factor commensurate witii a DC voltage within a ratiier narrowly defined window In die example of Fig. 4, seven levels and eight comparators can be u«ed to produce die vaπous wmdows. Division factor can change dnectly between any of states 50, 52, 54 and 56. Thus, Fig 4 mdicates coding tiiat requnes at least tinee encoded bits (i.e., representing seven wmdows or states) to carry out a transition from one frequency division state to any of the others Fig. 5 illustrates a more generalized state diagram of 60 used for implementing control unit 32. Depending upon the values of M and die options shown in dashed line, direct detection/locking or iterative ranging to ultimate locking can occur. State diagram 60 can be embodied eitiier in hardware or software to recognize a coded digital signal and tiierefore modify die division factor from the current frequency division factor to die next frequency division factor. Thus, the coded signal indicates possible change in the input signal frequency, and state diagram 60 indicates die affect of die coded signal on die clock divider 22 (shown in Fig. 1). For example, if die current division factor is modeled as x, as shown by state 62, then die division factor can change or remain in its current state. If the encoded signal is 00, tiien state 62 will remain. However, if the encoded signal is 01, tiien division factor will change from state 62 to state 64. If, however, the encoded signal is 10, then die division factor may remain e same or transition to state 66. The option is shown by the dashed lines adjacent coded signals 10. An examination of state diagram 60 indicates an increase in die frequency division factor from state 66, to state 62, and tiien to state 64 whenever the encoded signal is 01. A reduction in frequency division factor conversely occurs if the encoded signal is 10. It is appreciated diat while three states are shown, tiiere may be more than three depending on die amount of bits witiiin the encoded signal and die amount of resolution needed for achieving an appropriate frequency division. To aid in understanding how state diagram 60 might be carried out according to one example, a further example will be presented. Assuming x within state 62 is 4, and m in states 64 and 66 is also 4, it is apparent tiiat state 62 represents a - 4 state, and state 64 represents a - 16 state. Solely for the benefit and understanding the functionality of states 62 and 64, for die example provided, die following Table 1 is presented: TABLE 1 Referring to Figs. 1 - 4 and Table 1 in conjunction, the first line in Table 1 indicates a current divider state within clock divider 22 of a - 4. Additionally, die current input frequency is 4x (where m in Fig. 1 is equal to 4). From those pre-existing conditions, line 1 indicates the next input frequency remains at 4x. This does not produce a DC voltage which would extend above or below die dneshold voltages. Accordingly, the compare high/low outputs from high comparator 34 and low comparator 36 is 00. The effect of 00 coded signal upon state 62 (where x equals 4) is no change whatsoever. Accordingly, d e next divider state remains as state 62 (i.e., - 4). Thus, the current/next output signal frequency remains as 16x (i.e., 4x current/next input frequency times the current/next divider state). The next line of Table 1 indicates what would happen if die input signal frequency decreases from 4x to lx. A decrease in DC voltage will occur as a result of the decrease in input signal frequency, tiius producing a compare high/low coded signal of 01. The 01 coded signal, as shown in Fig. 5, will cause a change in state from state 62 to state 64. This is indicated as a change in a ÷ 4 as the current divider state to a ÷ 16 (where m in state 64 is equal to 4). The current/next output frequency, however, remains unchanged at 16x since the current divider state multiplied by die current input frequency equals the next divider state multiplied by the next input frequency. Line 3 in Table 1 becomes apparent given me previous descriptions of lines 1 and 2. However, it is illustrated tiiat, as an example, a compare high/low encoded signal of 10 may not effect (or change) die divide-by- state. However, it is understood tiiat, if desired, a 10 encoded value may cause a state transition if there are more than two states. In the example of Table 1, only two states are illustrated only for sake of brevity. Fig. 5, however, depicts a tiiird state, and possibly numerous other states, and die effect of coded signal 10 on die transition from state 62 to state 66. Lines 4 through 6 of Table 1, in conjunction witii Fig. 5) indicate transition from state 64 to state 62 if the coded signal is 10. Otherwise, in the example provided, state 64 remains if the encoded signals are 00 or 01. The example shown in Table 1 is indicative of two dissimilar input signal frequencies and two dissimilar clock divider states. Further as an example, Table 1 indicates a two-bit encoded signal derived from only two comparators and only two dissimilar d reshold voltages applied to tiiose comparators. It is recognized, however, that numerous input signal frequencies can be applied, as well as numerous clock divider states and comparators, reference voltage, etc. Regardless of die number of input signal frequencies and clock division states, the intent remains die same. If die input signal frequency is higher than die feedback signal frequency forwarded from the clock divider, die feedback loop will cause die VCO input voltage to increase to try and match the input signal frequency. Similarly, if the input signal frequency is below die feed back signal frequency , the feedback loop will cause die VCO input voltage to decrease and try and match die input signal frequency. If any of die comparators produce a "1" output, this means the input signal frequency is either too high or too low for the current frequency range set by clock divider 22. Control unit 32 evaluates die decision circuit 30 coded output and selects the appropriate clock divider control signal value to allow PLL 12 to lock to the input signal frequency. The intent behind control unit 32 is to maintain, increase or decrease die division factor within clock divider 22 from its current value. This causes reset of the VCO input voltage back to mid-scale. The PLL will then lock to d e input signal frequency and die decision circuit next output will be, for example, 00. It will be appreciated by tiiose skilled in die art having me benefit of this disclosure tiiat this invention is believed to be capable of applications witii any integrated circuit having both analog and digital portions. The integrated circuit may include the PLL, the decision circuit and die control unit all within a single monolithic substrate. It is intended tiiat the following claims be interpreted to embrace all such modifications and changes and, accordingly, the specification and drawings are to be regarded in an illustrative rather tiian a restrictive sense.

Claims: WHAT IS CLAIMED: 1. A phase-locked loop, comprising a clock divider circuit arranged witiiin a feedback loop of die phase- locked loop, said clock divider comprising a frequency division factor adapted to be modified inversely proportional to a change in frequency of an input signal forwarded to die phase-locked loop. 2. The phase-locked loop as recited in claim 1, wherein said frequency division factor is modified by multiplying a current frequency division factor by a positive factor M greater than 1.0, and wherein said change in frequency of said input signal is modified by multiplying a current frequency of said input signal by 1/M. 3. The phase-locked loop as recited in claim 1, wherein said frequency division factor is modified by multiplying a current frequency division factor by 1/M (where M is a factor greater than 1.0), and wherein said change in frequency of said input signal is modified by multiplying a current frequency of said input signal by M. 4. The phase-locked loop as recited in claim 1 , wherein said frequency division factor is adapted to be modified by a decision circuit operably coupled to determine whetiier the change in frequency of the input signal exceeds a direshold amount. 5. The phase-locked loop as recited in claim 4, wherein said decision circuit comprises a plurality of comparators, each of which is connected to receive a dc voltage proportional to the change in frequency of the input signal. 6. The phase-locked loop as recited in claim 5, wherein each of the plurality of comparators is further connected to receive a unique reference voltage to which the dc voltage is compared. 7. An apparatus coupled to receive an input signal frequency and produce an output signal frequency, the apparatus comprising: a phase detector coupled to produce a dc voltage corresponding to a difference between the input signal frequency and die output signal frequency reduced by a division factor; a voltage controlled oscillator coupled to receive die dc voltage and change the output signal frequency dependent on die dc voltage; a clock divider circuit coupled to receive die output frequency and, in accordance witii the division factor, forward die output signal frequency reduced by die division factor to the phase detector; a decision circuit coupled to receive die dc voltage and produce an encoded signal based on a comparison of the dc voltage to a reference voltage; and a control unit coupled to receive die encoded signal and modify die frequency division factor in response thereto. 8. The apparatus as recited in claim 7, wherein modification to the frequency division factor changes die dc voltage to a state which causes the voltage controlled oscillator to change the output signal frequency inversely proportional to modification of the frequency division factor. 9. The apparatus as recited in claim 7, wherein said control unit dispatches a control signal based on a current frequency division factor and die encoded signal. 10. The apparatus as recited in claim 7, wherein said encoded signal comprises binary bits. 11. The apparatus as recited in claim 7, wherein the number of said binary bits is two. 12. The apparatus as recited in claim 7, wherein said phase detector comprises a frequency detector. 13. A metiiod for changing a clock divider witiiin a feedback loop of a phase-locked loop for locking the frequency of an output signal to the frequency of an input signal forwarded from and to, respectively, the phase- locked loop, said metiiod comprising: monitoring a dc voltage output from a detector which compares phase and frequency of a feedback signal to die input signal; and changing the frequency of die feedback signal to substantially match a change in frequency of the input signal while maintaining substantially constant the frequency of the output signal based on a comparison of a reference voltage to the dc voltage prior to the change in frequency of the input signal. 14. The method as recited in claim 13, wherein said changing comprises reducing the frequency of the feedback signal inversely proportional to increasing the frequency of die input signal. 15. The method as recited in claim 13, wherein said changing comprises increasing die frequency of die feedback signal inversely proportional to reducing die frequency of the input signal.

Inventors: HARRIS LARRY L, KNAPP DAVID J, SUSANTO TONY, TRAGER DAVID S, HARRIS, LARRY, L., KNAPP, DAVID, J., SUSANTO, TONY, TRAGER, DAVID, S.
Applicants: OASIS DESIGN INC, OASIS DESIGN, INC.
Application year: 1998
Main classification: H03L7
IPC codes: H03L7