Time interleaved digital signal processing in a read channel with reduced noise figure

Abstract: A read and analog-to-digital data conversion channel comprising preamplifying circuits (Pre-Amp), automatic gain control circuits (VGA), harmonics filters (MRA), equalizing low pass filters (LPF), a time interleaved analog-to-digital converter (INTERLEAVED ATOD) including a pair of identical analog/digital converters (ATOD_EVEN, ATOD_ODD) functioning in parallel and at a half clock frequency, subdividing the signal path into two parallel paths through said two identical converters, one for even bits and the other for odd bits, and a digital post-processing block (DIGITAL Post Processing) fed by two output streams of said time interleaved converter (INTERLEAVED ATOD) and outputting a reconstructed data stream (DATA) and controlling said circuits, through dedicated digital-to-analog converters (DAC_VGA, DAC_MRA, DAC_FC, DAC_BOOST), means for compensating the offset of the digital-to-analog converters contained in said pair of identical analog-to-digital converters (ATOD_EVEN, ATOD_ODD) of said time interleaved converter (INTERLEAVED ATOD), controlled by said post-processing block (DIGITAL Post Processing) through a digital-to-analog converter, further comprises two distinct offset compensating circuits, each composed of an offset compensating stage (OFFSET_EVEN_STAGE, OFFSET_ODD_STAGE) independently controlled by said digital post-processing block through a dedicated digital-to-analog converter (DAC_OFF_E, DAC_OFF_O), preventing appearance of spurious patterns in frequency domain.

Description: FIELD OF THE INVENTION The present invention relates to data acquisition and digital data processing systems and more in particular to read channels of data stored in mass memory devices. BACKGROUND OF THE INVENTION In recent years the mass storage memories market has gone through an enormous growth especially in the area of magnetic disks; the continuous request for higher and higher memory capacity and for a higher and higher speed of data processing has prompted manufacturers to invest more and more resources in a highly competitive and rapidly evolving market. The introduction of digital processing of signals originating from the read pickups has determined a remarkable increment of the linear storage density. For example, the techniques of storing data on magnetic supports are based on the ability of ferromagnetic materials to remain biased in the direction of the applied magnetic field even when the magnetic field is no longer applied. The data are stored by either inverting or not the direction of magnetization on the disk. During a read phase, the presence or absence at a certain instant of a transition in the magnetic flux reveals the data sequence. For the same magnetic support properties, in order to increase the linear storage density, the distance between two adjacent transitions must be reduced. Eventually, an intersymbolic interference (or briefly ISI) becomes unavoidable. The problem of a correct detection of symbols affected by ISI and by noise is not limited to magnetic disks, indeed it may also arise in similar mass memory supports. Generally, it represents the main problem in data transfer channels, of which the read channels of hard disks drives (HDD), represent just one important example. The efforts to overcome the problem of ISI have led to the development and use of special coding techniques, such as so-called Partial Response (PR) signaling. These coding techniques are based on the fact that if the ISI on the transmitted data is known, then it can be taken into consideration during reception and reliably reconstruct the correct sequence of the original data. By assuming to be sampling the signal originating from a read pick-up with a clock synchronous with the writing clock, it is possible by the use of special algorithms of maximum likelihood (or briefly ML) to obtain the most likely data sequence effectively read from the memory support. By combining the PR technique with ML methods, the so-called PRML systems are implemented. The PRML decoding techniques work on a sequence of samples and the algorithms are digitally implemented. The electronics of a read/write channel must ensure a high speed, and for some functions such as for example clock generation, it is also mandatory a very high accuracy. The necessary circuits are of different kinds: analog and digital filters, A/D converters and low jitter Voltage-Controlled-oscillators (VCO) being among the most significative. Moreover, during a read phase, it is necessary to interface with the reading heads by way of low noise wide band amplifiers. During a write phase, in case of a magnetic support, the writing head must be driven with a relatively high current. Nowadays, a read/write channel with a relatively standard architecture has not yet been established. Various solutions have been proposed to meet the requirement of a higher speed and density of storage, solutions which range from a completely analog approach to a completely digital approach. The electronics of a HDD or similar apparatus, requires both analog and digital functionality. Manufacturing reasons, such as the standardization of the design and the adaptability among different technologies, foster implementation in the digital domain of functions that historically were implemented with analog circuits. Commonly, the analog part is dedicated to the correct generation of timing signals for writing and reading and for interfacing with the heads (Pre-Amp, VGA, MRA, LPF, OFFSET-STAGE, ATOD, VCO, etc.), the digital part is dedicated to the processing of data and to communicate with a data bus of the system (digital filters, maximum-likelihood detector, encoder-decoder, etc.). By way of example, a typical functional scheme of a single stream HDD read channel with digital processing of data is depicted in Fig. 1. As shown in the example of Fig. 1, read channels always include automatic gain control circuits (AGC) implemented with a variable gain amplifier controlled by way of a dedicated digital-to-analog converter DAC_VGA by the digital processing circuitry present downstream of the analog/digital switch, or briefly ATOD, in order to maintain constant the amplitude of the signal fed to the converter's input. In case of a magnetic support such as in a HDD, the Magnetic Resistive Asymmetry (MRA) block eliminates or in any case decisively attenuates the second harmonic (that is the contribution of the term α*x 2 ) of the input analog signal originating from the read head MR. Even this corrective operation of the signal spectrum is dynamically controlled through a dedicated digital-to-analog converter, DAC_MRA. The equalization of the signal is performed by the low pass filter LPF that controls the cut-off frequency, through the DAC_FC converter, and the boost, through the DAC_BOOST converter, which convert analog control signals of the transfer function of the low pass filter LPF, in digital commands (Word_FC and Word_Boost). In cascade to the equalization low pass filter LPF there exists an OFFSET STAGE that compensates the offset of the digital-to-analog converter present in the ATOD block. Even in this case there is a control loop for compensating the offset, implemented by the DIGITAL POST PROCESSING block and the DAC_OFF converter. Moreover, the DIGITAL POST PROCESSING block maintains a correct sampling synchronism by the ATOD block, by way of the control implemented by the DAC converter and the voltage controlled oscillator VCO. The above described system has several drawbacks: the digital data processing after the conversion takes place at full-rate, thus limiting the maximum frequency that the system may reach for a certain available technology; also the ATOD block operates at full-rate and represents a real bottleneck for the entire architecture in terms of the maximum possible frequency, current consumption and noise generated in the analog portion. To overcome or alleviate the above noted drawbacks, a new read channel architecture has been proposed, as shown in Fig. 2, wherein the post conversion digital processing is carried out on two distinct streams, one for the even bits and the other for the odd bits, by a time interleaving technique, as highlighted in greater detail in the partial scheme of Fig. 3. According to this approach, both the digital processing block, DIGITAL Post Processing, and the time interleaved converter, INTERLEAVED ATOD, work at half-rate, thus offering the possibility to provide for enhanced performances. An architecture of this type is described with great detail in the article: "A 200-Msample/s Trellis-Coded PRML Read/Write Channel with Analog Adaptive Equalizer and Digital Servo", IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, November 1997. Essentially, the architecture of Fig. 2 rests on the use of an INTERLEAVED ATOD converter whose structure is shown in Fig. 3. In practice, the structure is composed of two distinct identical comparators, ATOD_EVEN and ATOD_ODD, which divide the data stream into two digital output streams, one for even bits, EVEN_S, and the other for odd bits, ODD_S. In general, time interleaved solutions trade off is an increment of the circuit complexity and consequently of the area occupied by the converter on silicon. The increment of throughput obtained by introducing a parallelism in the signal path, if on one side offers undisputed advantages as it breaks the tight link between the maximum speed obtainable by a circuit and the limits to it imposed by the technology (cut-off frequency of transistors, settling time of the amplifier, etc.). on the other side introduces problems related to ensuring a somewhat perfect path matching. The existence of mismatches of gain, offset and/or timing, translates itself in an increment of the error mean power (or noise) and/or in the appearance of spurious patterns in the frequencies domain, which may fall in the signal band, distorting it, as it is amply demonstrated in the article "Time Interleaved Converter Arrays", IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 6, December 1980. OBJECT AND SUMMARY OF THE INVENTION It has now been found that an outstanding enhancement of the performance of a read channel may be obtained by using two distinct offset compensating circuits for the two ATOD converters used to implement a single path parallelism in a time interleaved converter, each independently controlled by the post-processing circuit by way of a respective digital-to-analog converter. The appearance of spurious patterns in the frequency domain, originating from offset mismatches which are likely to occur between the digital-to-analog converter of the ATOD converter of the signal path for the even bits and that of the digital-to-analog converter of the ATOD converter of the signal path for the odd bits, is effectively prevented by duplicating the compensation elements and by controlling them independently one from the other. In particular, generation of uncorrelated patterns in the signal spectrum, typically constituted by lines in correspondence of multiples of Fs/2, which would degrade the performance of the entire read channel is prevented, considering that the converter, in a typical application as that of a modem HDD, works above the Nyquist frequency. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1, as already mentioned, shows the architecture of a read channel for a single stream HDD with digital post-processing. Figure 2, as already mentioned, shows the architecture of a read channel for a split streams HDD with digital post-processing, employing a time interleaved ATOD. Figure 3, as already mentioned, highlights the internal structure of a time interleaved ATOD converter. Figure 4, shows the architecture of a read channel for a split stream HDD, modified according to the present invention. Figure 5 is a detail diagram of the time interleaved ATOD converter and of the doubled compensation circuits, of the offsets for the two signal paths. DESCRIPTION OF AN EMBODIMENT By referring to Figures 4 and 5, the INTERLEAVED ATOD converter is constituted by two identical analog-to-digital converters, one, ATOD_EVEN, for the signal path of the even bits, EVEN_S, and the other, ATOD_ODD, for the signal path of the odd bits, ODD_S. The two converters, ATOD_EVEN and ATOD_ODD, function in parallel and advantageously at a half-rate clock frequency. According to the invention, the offset of the digital-to-analog converter contained in each of the two analog-to-digital converters: ATOD_EVEN and ATOD_ODD, is independently compensated through a respective loops, each composed of an offset compensating stage, OFFSET_EVEN_STAGE and OFFSET_ODD_STAGE, respectively, controlled by the digital post-processing block, DIGITAL Post-Processing, through a dedicated digital-to-analog converter, DAC_OFF_E and DAC_OFF_O, respectively.

Claims: A read and analog-to-digital data conversion channel comprising preamplifying circuits (Pre-Amp), automatic gain control circuits (VGA), harmonics filters (MRA), equalizing low pass filters (LPF), a time interleaved analog-to-digital converter (INTERLEAVED ATOD) including a pair of identical analog/digital converters (ATOD_EVEN, ATOD_ODD) functioning in parallel and at a half clock frequency, subdividing the signal path into two parallel paths through said two identical converters, one for even bits and the other for odd bits, and a digital post-processing block (DIGITAL Post Processing) fed by two output streams of said time interleaved converter (INTERLEAVED ATOD) and outputting a reconstructed data stream (DATA) and controlling said circuits, through dedicated digital-to-analog converters (DAC_VGA, DAC_MRA, DAC_FC, DAC_BOOST), means for compensating the offset of the digital-to-analog converters contained in said pair of identical analog-to-digital converters (ATOD_EVEN, ATOD_ODD) of said time interleaved converter (INTERLEAVED ATOD), controlled by said post-processing block (DIGITAL Post Processing) through a digital-to-analog converter, characterized in that it comprises two distinct offset compensating circuits, each composed of an offset compensating stage (OFFSET_EVEN_STAGE, OFFSET_ODD_STAGE) independently controlled by said digital post-processing block through a dedicated digital-to-analog converter (DAC_OFF_E, DAC_OFF_O).

Inventors: BRUCCOLERI MELCHIORRE, DEMICHELI MARCO, OTTINI DANIELE, SAVO ALESSANDRO, BRUCCOLERI, MELCHIORRE, DEMICHELI, MARCO, OTTINI, DANIELE, SAVO, ALESSANDRO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1998
Main classification: G11B20
IPC codes: G11B20, H03M1, H04L27