Computer Memory controller

Abstract: A computer memory controller comprises a DRAM timing control section that provides, during memory back-up operation mode, self-refresh timing to DRAM array having self-refresh function. It also comprises a refresh/back-up control section that provides information as to memory back-up state to the DRAM timing control section. A DRAM identification mode register is provided. When DRAM array without self-refresh function is mounted, the state of the register changes. The state of the register is fed to the DRAM timing control section, thereby to provide timing according to the conventional CBR refresh method to the DRAM array.

Description: FIELD OF THE INVENTION The present invention relates to a computer memory controller, and more particularly to a computer memory controller for a memory in the form of a DRAM structure that has a battery back-up function, according to the preamble of claim 1. BACKGROUND OF THE INVENTION Memories are widely well known which have memory back-up function to hold information by a battery in case of a power failure. If the memory is a DRAM, it is essential, in the memory back-up control, for the DRAM to perform refresh operation. Usually, refresh operation of DRAM may be performed according to a RAS only refresh (ROR) method or a CAS before RAS (CBR) method or a self-refresh method. However, the CBR method is usually employed in performing refresh operation for memory back-up control in case of power failure. The ROR method may be used in performing refresh operation over memory back-up control in case of power failure. However, this method requires setting of fresh addresses each time upon performing refresh operation. Further, the refresh addresses must be handed over during a shift from memory back-up operation to usual operation or vice versa causing increased complexity of memory back-up control. This explains why the ROR method has not been widely employed. Conventionally, few computer memory controllers are designed to render self-refresh function of DRAM operable to perform refresh operation when memory back-up operation is needed. This is because DRAMs with self-refresh function are not yet popular in market and thus the number of such DRAMs is very small. Accordingly, it is the conventional practice to use the CBR method in performing refresh operation upon memory back-up operation using battery as shown, for example, in JP-A 3-237678, which is illustrated in Figure 4. In Figure 4, the reference numeral 44 indicates a clock generator, which generates a refresh-oriented RAS signal (RRS signal) 48 and a refresh-oriented clock source signal (RFCK signal) 46. The reference numeral 45 indicates a refresh switch. A power failure signal (PF signal) 43 is used as the input to the refresh switch 45 for the refresh switch 45 to output a switch signal 47. The level of the PF signal 43 determines the level of the switch signal 47. RAS signal 41 and RFCK signal 46 are used as the inputs to the refresh switch 45, causing latter to generate a refresh-oriented CAS signal (RCS signal) 49. The reference numerals 4A and 4B designate a RAS selector and a CAS selector, respectively. RAS signal 41 and RRS signal 48 are use as the inputs to the RAS selector 4A. CAS signal 42 and RCS signal 49 are used as the inputs to the CAS selector 4B. In response to the refresh switch signal 47, the RAS selector 4A selects one of its inputs for feeding the selected one to a DRAM 4C, and the CAS selector 4B selects one of its inputs for feeding the selected one to the DRAM 4C. This accomplishes refresh operation mode necessary for assuring contents stored in the memory. The timing chart of Figure 5 illustrates operation of the conventional example shown in Figure 4. During usual operation mode, RAS signal 41 and CAS signal 42 are fed to DRAM 4C. As illustrated in Figure 5, ROR method is used for refresh operation during normal operation mode, while CBR method is used for refresh operation during back-up operation. According to the conventional computer controller, the CBR method, which is employed for refresh operation during back-up mode operation, consumes a great amount of electricity out of limited amount of electric power supply, resulting in shortening the memory back-up period of time. This is because the power consumption by DRAM during refresh operation according to CBR method is as great as that during usual operation. To remedy this problem, it may be alternative to employ self-refresh operation of DRAM by redesigning a computer memory controller. However, the computer memory controller as redesigned poses a potential problem that it cannot provide memory back-up function when a DRAM without self-refresh function is installed. As mentioned before, the number of DRAMs with self-refresh function is limited in the market and most of DRAMs available in the market are not provided with self-refresh function, which require CBR method for refresh operation. US 5 640 357 discloses a computer memory controller for a memory in the form of DRAM having memory back-up function in case of power failure, configured to perform self-refresh operation during memory back-up operation mode. DE 30 03 524 A1 discloses a memory controller which enables refresh of DRAM with refresh function during power down. WO 97 17647 A1 discloses a DRAM memory controller with a configuration register with a bit indicating if CAS-before-RAS or self-refresh DRAM is used. The object of the present invention is to provide a computer memory controller, which is operable to reduce power consumption during memory back-up operation within DRAM having memory back-up function. SUMMARY OF THE INVENTION This object is solved with the features of claim 1. A computer memory controller according to the present invention is intended for a memory in the form of DRAM having memory back-up function in case of power failure. The computer memory controller is operable to perform refresh operation, during memory back-up operation mode, in accordance with self-refresh method, and is operable to select refresh operation during memory back-up mode in case of installation with DRAM that is not provided with a special refresh function, such as self-refresh function, needed for reducing power consumption. Specifically, the computer memory controller comprises a DRAM timing control section, which generates timing signal fit for self-refresh function of DRAM and provides the timing signal to the DRAM, and a back-up control section, which detects memory back-up state and inform the detected result to the DRAM timing control section. The computer memory section also comprises a DRAM identification mode register, which can identify the fact that DRAM without self-refresh function is in use. The DRAM timing control section is operable in response to the state of the register to provide refresh operation suitable for the DRAM that is in use. BRIEF DESCRIPTION OF THE DRA WINGS Figure 1 shows a block diagram of a controller as configured in the preferred embodiment. Figure 2 shows a timing chart of signals within the controller for DRAMs with a self-refresh function. Figure 3 shows a timing chart of signals within the controller for DRAMs without a self-refresh function. Figure 4 shows a block diagram of a controller as configured according to the prior art. Figure 5 shows a timing chart of signals within the controller of Figure 4. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Figures 1 to 3, the preferred embodiment of the controller according to the present invention is described. In the block diagram shown in Figure 1, a power-fail indicative (PFI) signal 14 and a DRAM identification mode setting (DIMS) signal 18 are used as inputs to a refresh/back-up control section 1. The refresh/back-up control section 1 generates a refresh operation trigger (ROT) signal 16 and a back-up trigger (BT) signal 17. ROT signal 16, BT signal 17, and usual operation trigger (UOT) signal 23 are used, as inputs, to a DRAM timing control section 2. The DRAM timing control section 2 generates a RAS signal 24 and a CAS signal 25. RAS signal 24 and CAS signal 25 are used as inputs to a dynamic random access memory (DRAM) array 3. The DRAM timing control section 2 receives ROT signal 16 or BT signal 17 from the refresh/back-up control section 1, and UOT signal 23 from a memory control section, not shown. In response to levels of these signals, the control section 2 selects an appropriate one of timings that are predetermined for memory write-in/read-out operation, CBR function, and self-refresh function, respectively, and generates RAS signal 24 and CAS signal 25 at the selected timing. The refresh/back-up control section 1 includes a back-up command signal generator 11, a DRAM identification mode register 12, an AND gate 15, and a refresh operation trigger signal generator 13. The back-up command signal generator 11 receives PFI signal 14 and outputs back-up command (BC) signal 19 in response to the PFI signal 14. The DRAM identification mode register 12 receives DIMS signal 18 and outputs DRAM identification (DI) signal 1A in response to the DIMS signal 18. The BC signal 19 and DI signal 1A are used as inputs of the AND gate 15, respectively. The AND gate 15 performs logical product of the two inputs and outputs BT signal 17. The refresh operation trigger signal generator 13 receives BT signal 17 and outputs ROT signal 16 in response to BT signal 17. Suppose that the state level of PF signal 14 indicates power fault, and the DRAM array 3 has self-refresh function. In this case, the back-up command signal generator 11 generates BS signal 19, and the DRAM identification mode register 12 sets the DI signal 1A to a level indicative of the fact that the DRAM array 3 has self-refresh function. This causes the AND gate 15 to apply, as the output, BT signal 17 to the DRAM timing control section 2. In response to the BT signal 17, the DRAM timing control section 2 creates timing that corresponds to self-refresh function of the DRAM, putting the self-refresh function into memory back-up operation. The BC signal 19 is fed also to the refresh operation trigger signal generator 13, causing the generator 13 to stop producing the ROT signal 16. Let us next consider the case that the state level of PF signal 14 indicates power fault, but the DRAM array 3 has no self-refresh function. In this case, the DI signal 1A is set to a level indicative of the fact that the DRAM array 3 has no self-refresh function. This causes the AND gate 15 to stop producing the BT signal 17, causing the refresh operation trigger signal generator 13 to produce the ROT signal 16. This results in realizing memory back-up operation using CBR. The operation is further described in connection with the timing charts of Figures 2 and 3. The timing chart of Figure 2 illustrates the case where a DRAM array 3 with self-refresh function is used. In this timing chart, usual memory access operation, refresh operation by CBR, and memory back-up operation by self-refresh function happen in this order. Suppose that the DRAM identification mode register 12 contains a logical high "H" level, which is indicative of the fact that the DRAM array 3 has self-refresh function, and PF signal has a logical low "L" level, which is indicative of the fact that the power supply is normal. The DRAM identification mode register 12 was set to the "H" level via DIMS signal 18. In this case, the usual memory access operation is performed. The DRAM timing control section 2 receives UOT signal 23, which is sent by the memory control section (not shown). The UOT signal 23 are used as the input to RAS signal generator 21 and also as the input to CAS signal generator 22, causing the generators 21 and 22 to output RAS signal 24 and CAS signal 25, each of which corresponds to normal memory access. The RAS signal 24 and CAS signal 25 are fed to DRAM array 3. Subsequently, at moment when refresh operation is requested during usual operation, the DRAM timing control section 2 receives ROT signal 16 from the refresh operation trigger signal generator 13 within the refresh/back-up control section 1. The ROT signal 16 appears at regular intervals. It is used as the input to the RAS signal generator 21 and also as the input to the CAS signal generator 22, causing the generators 21 and 22 to output RAS signal 24 and CAS signal 25, each of which corresponds to CBR. The RAS signal 24 and CAS signal 25 are fed to DRAM array 3. Lastly, at a moment when power fault happens, the PF signal 14 shifts to a logical high "H" level, causing the back-up command signal generator 11 within the refresh/back-up control section 1 to generate BC signal 19, which has a logical high "H" level. Since the "H" level DI signal 1A and the "H" level BC signal 19 are impressed onto the inputs, the AND gate 15 provides as its output a signal having a logical high "H" level. This output of the AND gate 15 is fed, as BT signal 17, to the refresh operation trigger signal generator 13 and also to the DRAM timing control section 2. Impressing the BT signal 17 onto the refresh operation trigger signal generator 13 causes same to stop generating ROT signal, which appeared at regular intervals. Within the DRAM timing control section 2, the BT signal 17 is used as the input to the RAS signal generator 21 and also as the input to the CAS signal generator 22. This causes the generators 21 and 22 to output RAS signal 24 and CAS signal 25, each of which corresponds to the self-refresh. The RAS signal 24 and CAS signal 25 are fed to DRAM array 3. With regards to power consumption by the DRAM array 3 during the above-discussed three operation modes, the power consumption during the self-refresh operation mode drops down to P/several hundreds (P/several 100s), if the power consumption during usual memory access operation mode is P. The power consumption during CBR operation mode is P. It is now possible to considerably lower the power consumption during memory back-up operation. The timing chart of Figure 3 illustrates the case where the DRAM array 3 does not have self-refresh function. In this timing chart, usual memory access operation, refresh operation by CBR, and memory back-up operation happen in this order. The usual memory access and refresh operations in this timing chart are the same as those in the timing chart of Figure 2. Thus, detailed description there of is hereby omitted for sake of brevity. The timing chart of Figure 3 is different from that of Figure 2 only in refresh operation for memory back-up operation. The DRAM identification mode register 12 contains a logical high "L" level, which is indicative of the fact that the DRAM array 3 does not have self-refresh function. Referring to Figure 3, at a moment when power fault happens, the PF signal 14 shifts to a logical high "H" level, causing the back-up command signal generator 11 within the refresh/back-up control section 1 to generate BC signal 19, which has a logical high "H" level. As different from Figure 2, the "L" level DI signal 1A is impressed onto one of the inputs, the AND gate 15 provides as its output a signal having a logical low "L" level irrespective of the logical level impressed onto the other input. Thus, BT signal 17 becomes invalid, and the refresh operation trigger signal generator 13 continues to output ROT signal 16 at regular intervals. Thus, even during memory back-up operation, the DRAM timing control section 2 continues to output RAS signal 24 and CAS signal 25, each of which corresponds to the CBR refresh. The RAS signal 24 and CAS signal 25 are fed to DRAM array 3. The power consumption by the DRAM array 3 during this operation remains the same and is equal to P.

Claims: A computer memory controller for a memory in the form of DRAM (3) having memory back up function in the case of power failure, which computer memory controller comprises a DRAM timing control section (2) able to generate a self-refresh timing during memory back-up operation mode, and to output said self-refresh timing to said DRAM (3), characterized in : that said DRAM timing control section (2) is further able to generate a refresh timing different from said self-refresh timing during said memory back-up operation mode and to output said refresh timing to said DRAM (3), and that said computer memory controller comprises a DRAM identification mode register (12) for detecting if DRAM with or without self-refresh function is in use, and outputting a corresponding DRAM identification signal (1A), wherein when said DRAM identification signal (1A) indicates that DRAM with self-refresh is in use, said self-refresh timing is generated by said DRAM timing control section (2), while, when said DRAM identification signal (1A) indicates that DRAM without self-refresh is in use, said refresh timing different from said self-refresh timing is generated by said DRAM timing control section (2). A computer memory controller as claimed in claim 1, comprising a back-up control signal generator (11) outputting a back-up control signal, (19), the DRAM timing control section (2) receiving as its input a back-up trigger signal (17), which results from said back-up control signal (19) and said DRAM identification signal (1A), and a refresh operation trigger signal (16), and a refresh operation trigger signal generator (13) receiving as its input said back-up tigger signal (17), and outputting the refresh trigger signal (16), such that the DRAM timing control section (2), when receiving an active back-up trigger signal (17), generates timing that corresponds to self-refresh timing, and when receiving an active refresh operation trigger signal (16), generates a refresh timing different from self refresh timing. A computer memory controller as claimed in claim 2, comprising a logical gate (15) receiving as its inputs said back-up control signal (19) and said DRAM identification signal (1A), said logical gate (15) outputting said back-up trigger signal (17) . A computer memory controller as claimed in claim 1, comprising a power failure responsive back-up control section (1) outputting a back-up trigger signal (17), generated from said DRAM identification signal (1A), the DRAM timing control section (2) receiving as its input said back-up trigger signal (17), and a refresh trigger signal generator (13) normally, during times in which said back-up trigger signal (17) is not received, outputting a refresh trigger signal (16), said refresh trigger signal generator (13) receiving as its input said back-up trigger signal (17) and being operable to prevent outputting of said refresh trigger signal (16) during times in which said back-up trigger signal (17) is received.

Inventors: KISHINO TSUYOSHI, KISHINO, TSUYOSHI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1998
Main classification: G11C11
IPC codes: G11C11, G06F12