PHASE DETECTOR ARRANGEMENT

Abstract: The invention relates to a phase detector arrangement for use in a phase locked loop circuit, for recovery of clock and data pulses from a data stream comprising Return to Zero RZ signals comprising digital data. The arrangement comprises a comparator (10), a phase detector (16), a loop filter (17) and a voltage controlled oscillator (18). The phase detector (16) comprises a phase position indicator (20; 21) which is activated by each incoming data pulse in the output line (12; 13) of the comparator (10). The invention also includes a method for recovery of clock and data pulses. The method comprises the steps of monitoring the data pulses in the or each output line (12; 13) of the comparator and controlling the voltage controlled oscillator in relation to both edges of each data pulse, for clocking data synchronously with the pulse.

Description: Title: Phase detector arrangement TECHNICAL FIELD The present invention relates to a phase detector arrangement for use in a phase locked loop circuit, for recovery of clock and data pulses from a data stream which comprises Return to Zero RZ signals comprising digital data, said arrangement comprising a comparator, a phase detector, a loop filter and a voltage controlled oscillator, wherein the phase detector comprises a phase position indicator which is activated by each incoming data pulse in the output line of the comparator, said phase position indicator being adapted to control the voltage controlled oscillator in relation to both edges of each data pulse, for clocking data synchronously with said data pulse. The present invention also relates to a method for recovery of clock and data pulses from a received data stream which comprises Return to Zero RZ signals comprising digital data and is received via a comparator, said arrangement comprising a phase detector, a loop filter and a voltage controlled oscillator, wherein the data pulses in the or each output line of the comparator are monitored and the voltage controlled oscillator is controlled in relation to both edges of each data pulse, for clocking synchronously with said data pulse. STATE OF THE ART In the field of single line digital communication, the recovery of clock and data pulses from a received RZ-signal can be accomplished by means of a tank circuit. A tank circuit comprises LC-filters that filters out the clock frequency from the timing contents of the input signal plus a sine/square wave converter that converts it into a square wave digital clock signal. These solutions are cost-efflcient and are often applied to traditional PDH-equipment . One peculiarity with tank circuits is that the clock signal disappears about 10-20 pulses after that the input signal has disappeared. While the tank circuits are capable to withstand a tremendously jittered input signal, they are not good at dampening jitter and they are not good at enduring noise. There is also a risk of producing jitter within said circuits. Another solution is to use a phase locked loop circuit for clock and data recovery. This type of circuit is more flexible and may for example be made more narrow-banded than tank circuit solutions, and is therefore able to damp jitter more efficiently and is less sensitive to noise and maintains the clock signal even if the input signal is missing. Commonly used phase detectors, for example of the type Phase-Frequency comparators, Exclusive-or or Set-Reset flip-flop, all being present within the circuit 74HC4046, require input signals continuously each period from signal and reference in order to be able to detect the phase position correctly. These phase detectors can not work upon RZ signals . In order to be able to detect the phase position of a RZ signal, for example of any of the types B3ZS, HDB-3, AMI or RZ, and the clock with which the data should be recovered, the comparison must be made exclusively with those parts of the signal which provide a pulse of the type RZ . It would be possible to measure the time it takes from the front edge of the RZ-signal to the desired clock- edge. This may be accomplished analogously or digitally by means of digital counters. One drawback with counters is that the clock frequency to the counters must be considerably higher than that of the clock and data that is to be recovered, if a high phase position accuracy is desirable. This may be a problem at high frequencies, among other with regard to technology, power consumption and cost. SUMMARY OF THE INVENTION What s needed is therefore a cost-efficient phase detector arrangement which is able to operate at high frequencies with low power . According to the invention, this is accomplished by connecting the phase position indicator output is in series via a resistor to an earth-connected capacitor, for integration of the output signal with reference to the duration of each data pulse to a mean value which corresponds to the phase position between the data pulse and the clock signal . In a particular embodiment of the invention, the output line of the phase detector is connected to the voltage controlled oscillator via the loop filter. The comparator may be provided with two output lines and the phase detector may comprise two phase position indicators, wherein either one or the other indicator is activated for each incoming data pulse in the output lines of the comparator. These phase position indicators may be mutually connected to a connection point and from said point connected m series via the resistor to the earth-connected capacitor. The clock signal of the voltage controlled oscillator may be used as input to the phase detector. The voltage over the capacitor is preferably used for controlling the output phase of the voltage controlled oscillator. The or each phase position indicator may be a tristate buffer. Alternatively, the or each phase position indicator may be an analogue switch. The arrangement according to the invention is preferably used m a telecommunication system. The method according to the invention comprises the steps of integrating the input signal controlled by the or each output line with reference to the duration of each pulse to a mean value which corresponds to the phase position between the data pulse and the clock signal . Preferably, the clock signal is used to be switched out as phase position pulses. BRIEF DESCRIPTION OF THE DRAWINGS The invention will in the following be further described in a non- 1uniting way with reference to the accompanying drawings m which: Fig. 1 is a circuit diagram showing the phase detector arrangement according to the invention, and Fig. 2 schematically illustrates a phase detector circuit which is included in the phase detector arrangement according to Fig. 1. DESCRIPTION OF PREFERRED EMBODIMENTS The circuit diagram in Fig. 1 shows the structure of a NRZ data and clock recovering circuit for bipolar RZ-signals according to the present invention. As shown in this figure, the PLL circuit comprises a comparator 10 with a data signal input line 11. Each of two data signal output lines 12, 13 from said comparator is connected to a respective D- A phase locked loop is connected to lines 12, 13 and comprises a phase detector 16, a loop filter 17 and a voltage controlled oscillator 18. The VCO 18 is controlled by the phase detector 16 via the loop filter 17. The intention is to convert the input bipolar RZ signals to a digital NRZ and a clock signal . The phase detector receives two different signals via the connections to lines 12, 13 from the comparator 10 which converts a bipolar RZ signal to inverse RZ data (Return to Zero) to IRZ+=0, IRZ-=1 for positive input pulse, IRZ+=1, IRZ-=0 for negative pulse and IRZ+=1, IRZ-=1 for no input pulse. The VCO 18 controls the frequency of the clock elk, line 19, and thus the clocking of the two D-flip-flops 14 and 15 which in turn clock the inverted RZ-data to NRZ-data. The phase detector 16 is shown m Fig. 2 and it comprises two phase position indicators 20 and 21 which are mutually connected to a connection point 22 and from this point 22 via a resistor 23 to an earth-connected capacitor 24. The phase detector circuit operates in such a way, that for each input data pulse created by IRZ+ or IRZ-, either the phase position indicator 20 or 21 is activated. The VCO clock 18 delivers input signals to the phase position indicators 20 and 21. The phase position indicators 20, 21 are for example tristate buffers. The output signals from the tristate buffers are either 0, 1 or TRISTATE (high ohmic) . The tristate buffers are controlled by the data pulses in the lines 12, 13 of the comparator 10 and said buffers, in co-operation with the resistor 23 and the capacitor 24, are adapted to integrate the output signal from the or each output line with reference to the duration of each pulse to a mean value which corresponds to the phase position between the data pulse and the clock signal . Similar behaviour can be obtained with analogue switches. In this way, a voltage is created over the filter capacitor 24 which corresponds to the phase position between the front and the back edge of the data signal and the clock signal. Thus, this voltage is a measure of how well in the middle of the data pulse the data is clocked. If a clock pulse is a little earlier or a little later than the previous pulse, the capacitor 24 will either be charged or discharged through the phase detector circuit 16 and thus the voltage Vdet will either increase or decrease. Thus, the voltage Vdet controls the VCO output phase to the right clock position. The invention is not limited to the above described embodiments, instead several modifications may be made within the scope of the invention. If, for example, incoming data pulses only comprise unipolar RZ-pulses, the second phase position indicator 21 is not needed .

Claims: CLAIMS 1. A phase detector arrangement for use in a phase locked loop circuit, for recovery of clock and data pulses from a data stream comprising Return to Zero RZ signals comprising digital data, said arrangement comprising a comparator (10) , a phase detector (16) , a loop filter (17) and a voltage controlled oscillator (18) , wherein the phase detector (16) comprises a phase position indicator (20; 21) which is activated by each incoming data pulse in the output line (12; 13) of the comparator (10), said phase position indicator (20; 21) being adapted to control the voltage controlled oscillator (18) in relation to both edges of each data pulse, for clocking data synchronously with said data pulse, c h a r a c t e r i z e d in that the phase position indicator (20; 21) output (22) is connected in series via a resistor (23) to an earth-connected capacitor (24) , for integration of the output signal with reference to the duration of each data pulse to a mean value which corresponds to the phase position between the data pulse and the clock signal . 2. An arrangement according to claim 1, wherein the output line of the phase detector is connected to the voltage controlled oscillator (18) via the loop filter (17) . 3. An arrangement according to claim 1, wherein the comparator is provided with two output lines (12, 13) and the phase detector (16) comprises two phase position indicators (20, 21) , either one or the other indicator being activated for each incoming data pulse in the output lines (12, 13) of the comparator (10) . 4. An arrangement according to claim 3 , wherein the phase position indicators (20, 21) are mutually connected to a connection point (22) and from said point connected in series via the resistor (23) to the earth-connected capacitor (24) . 5. An arrangement according to any of the above claims, wherein the clock signal of the voltage controlled oscillator (18) is used as input to the phase detector (16) . 6. An arrangement according to claim 5 , wherein the voltage over the capacitor (24) is used for controlling the output phase of the voltage controlled oscillator (18) . 7. An arrangement according to any of claims 1-6, wherein the or each phase position indicator (20, 21) is a tristate buffer. 8. An arrangement according to any of claims 1-6, wherein the or each phase position indicator (20, 21) is an analogue switch. 9. Use of an arrangement according to any of the above claims, in a telecommunication system. 10. A method for recovery of clock and data pulses from a data stream comprising digital signals being received by a comparator (10) , said arrangement comprising a phase detector (16) , a loop filter (17) and a voltage controlled oscillator (18) , wherein the data pulses in the or each output line (12; 13) of the comparator (10) are monitored and the voltage controlled oscillator (18) is controlled in relation to both edges of each data pulse, for clocking synchronously with said data pulse, c h a r a c t e r i z e d in the step of : integrating the input signal controlled by the or each output line (12, 13) with reference to the duration of each pulse to a mean value which corresponds to the phase position between the data pulse and the clock signal. 11. A method according to claim 10, wherein it further comprises the step of using the clock signal (19) to be switched out as phase position pulses.

Inventors: BLADH MATS, BLADH, MATS
Applicants: ERICSSON TELEFON AB L M, TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
Application year: 1998
Main classification: H03L7
IPC codes: G01R25, H03L7, H04L7