Output logic setting circuit in semiconductor integrated circuit.

Abstract: An output logic setting circuit includes a fusible fuse element (8) which is selectively rendered conductive or disconnected by external signal operation. The output logic setting circuit is designed to output, from an output terminal (10), an output logic set when the fuse element (8) is rendered conductive or disconnected. The output logic setting circuit includes an inverter circuit (102) which is arranged between the fuse element (8) and the output terminal and has a threshold larger than a predetermined value.

Description: BACKGROUND OF THE INVENTION 1. FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit and, more particularly, to an output logic setting circuit which is arranged in a semiconductor integrated circuit to perform output logic setting, and is of the type outlined in the preamble of patent claim 1. 2. DESCRIPTION OF THE PRIOR ART An output logic setting circuit of this type includes a fuse to perform output logic setting. For example, such an output logic setting circuit is used in a constant-current generating circuit which has a fuse connected to the input terminal of a decoder for outputting trimming data so as to obtain necessary trimming data from the decoder by externally and selectively fusing the fuse. Fig. 1 shows an output logic setting circuit arranged in a conventional semiconductor integrated circuit and described as well as depicted in document JP-63-204627(A). As shown in Fig. 1, this conventional circuit is constituted by a power-down reset circuit 100, an inverter circuit 101 having one terminal connected to the output stage of the power-down reset circuit 100 and the other terminal connected to an output terminal, and a fusible fuse 8 which is connected between the power-down reset circuit 100 and a ground potential V cc and is selectively rendered conductive or disconnected by external signal operation. The power-down reset circuit 100 includes transistors 1 and 3 having gate terminals connected to a reset terminal 11, and a pull-up transistor 2 having a gate terminal connected to the ground potential V cc . The inverter circuit 101 includes transistors 4 and 5 having gate terminals connected to the output stage of the power-down reset circuit 100. When the initial value in the output logic setting circuit having the above arrangement is to be changed, a fusing voltage is applied between a fusing pad 12 and the ground potential V cc to sever the fuse 8. The active-low power-down reset circuit 100 is then operated. With this operation, the input potential of the inverter circuit 101 on the subsequent stage is changed by the pull-up transistor 2 whose gate level is set to the ground voltage, thereby performing output logic setting. In general, in an output logic setting circuit manufactured on a semiconductor substrate, a fuse element is made of a polysilicon layer formed on a field oxide film, and output logic setting is performed by selectively rendering the fuse element conductive or disconnecting it in accordance with external signal operation. When, however, the output logic setting circuit shown in Fig. 1 is manufactured on a semiconductor integrated circuit for the above purpose, the resistance of the fuse element increases due to a change in quality with time after a lapse of a long period of time since the manufacture of the circuit. In this case, the circuit may be kept in a connected state even if the fuse element is set in a disconnected state. As a result, the input voltage to the inverter circuit becomes unstable, and the output logic value may be inverted with respect to an expected value. Similar circuitry is also shown in JP-01-062898(A). SUMMARY OF THE INVENTION The present invention has been made in consideration of the above situation in the prior art, and has as its object to provide an output logic setting circuit in a semiconductor integrated circuit, which can prevent a change in output logic due to a change in quality with time. In order to achieve the above object, according to the principal aspect of the present invention, there is provided an output logic setting circuit comprising the features of patent claim 1. The threshold in the inverter circuit according to the principal aspect is set such that a resistance of the fuse element becomes not less 1 kΩ even if the fuse element is in a connected state. According to the output logic setting circuit of the present invention, which has the above arrangement, since the inverter circuit whose threshold is larger than a predetermined value is arranged between the fuse element and the output terminal, the gate level of the pull-up transistor in the power-down reset circuit is controlled by the inverter circuit. Even if, therefore, the fuse element is in a connected state, its resistance becomes several kΩ. For this reason, the output logic is not inverted. In this manner, the output logic setting circuit is stabilized The above and many other objects, features and advantages of the present invention will become manifest to those skilled in the art upon making reference to the following detailed description and accompanying drawing in which a preferred embodiment incorporating the principles of the present invention are shown by way of an illustrative example. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing a conventional output logic setting circuit arranged in a semiconductor integrated circuit; and Fig. 2 is a circuit diagram showing an output logic setting circuit according to an embodiment of the present invention which is arranged in a semiconductor integrated circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawing. Fig. 2 is a circuit diagram showing an output logic setting circuit according to an embodiment of the present invention which is arranged in a semiconductor integrated circuit. As shown in Fig. 2, this embodiment includes a power-down reset circuit 100, a first inverter circuit 102 having a threshold larger than a predetermined value and connected to the output stage of the power-down reset circuit 100, a second inverter circuit 101 connected to the power-down reset circuit 100 and the output stage of the first inverter circuit 102, and a fusible fuse 8 which is connected between the power-down reset circuit 100 and a ground potential V cc and is selectively rendered conductive or disconnected by external signal operation. The power-down reset circuit 100 is constituted by transistors 1 and 3 arranged on the input side of the circuit and having gate terminals connected to a reset terminal 11, and a pull-up transistor 2 arranged on the output side of the circuit and having a gate terminal connected to the output stage of the first inverter circuit 102 and the input stage of the second inverter circuit 101. The first inverter circuit 102 is constituted by transistors 6 and 7 having gate terminals connected to the output stage of the power-down reset circuit 100. The second inverter circuit 101 is constituted by transistors 4 and 5 having gate terminals connected to the gate terminal of the transistor 2 in the power-down reset circuit 100 and the output stage of the first inverter circuit 102. A threshold is set in the first inverter circuit 102 such that the resistance of the fuse 8 becomes several kΩ or more even in a connected state. The fuse 8 is made of a polysilicon layer formed on a field oxide film. When the initial value in the circuit having the above arrangement is to be changed, a fusing voltage is applied between a fusing pad 12 and the ground potential V cc to disconnect the fuse 8. Subsequently, the low-active power-down reset circuit 100 is operated. With this operation, the input voltage to the first inverter circuit 102 on the subsequent stage is changed by the pull-up transistor 2 whose gate level is set to the level of an output from the first inverter circuit 102. At the same time, the second inverter circuit 101 on the next state is controlled to perform output logic setting. As is obvious from the above description, according to the output logic setting circuit of the present invention, since the inverter circuit whose threshold is larger than a predetermined value is arranged between the fuse element and the output terminal, the gate level of the pull-up transistor in the power-down reset circuit is controlled by the inverter circuit. Even if, therefore, the fuse element is in a connected state, its resistance becomes several kΩ. For this reason, the output logic is not inverted. In this manner, the output logic setting circuit is stabilized.

Claims: An output logic setting circuit comprising: a power-down reset circuit (100) including at least one first transistor (1, 3) arranged on the circuit input side and having a gate terminal connected to a reset terminal (11), and a second transistor (2) arranged on the circuit output side; a fusible fuse (8) which is connected between said power-down reset circuit (100) and ground potential and is selectively rendered conductive or disconnected by external signal operation; and a first inverter circuit (102) having a threshold larger than a predetermined value and connected to the output stage of said power-down reset circuit (100); characterized in that a second inverter circuit (101) is provided connected to said power-down reset circuit (100) and the output stage of said first inverter circuit (102); and the output of said first inverter circuit (102) is connected to the gate of said second transistor (2). A circuit according to claim 1, characterized in that said first inverter circuit (102) comprises at least one third transistor (6, 7) whose gate terminal is connected to the output stage of said power-down reset circuit (100), and said second inverter circuit (101) comprises at least one fourth transistor (4, 5) whose gate terminal is connect to the gate terminal of the second transistor (2) arranged on the output side of said power-down reset circuit (100) and the output stage of said first inverter circuit (102). A circuit according to claim 1, characterized in that the threshold in said first inverter circuit (102) is set such that the resistance of said fuse element (8) becomes not less than 1 kΩ even if said fuse element is in a connected state. A circuit according to claim 1, characterized in that said fuse element (8) is made of a polysilicon layer formed on a field oxide film.

Inventors: MATSUSHITA HIROSHI, MATSUSHITA, HIROSHI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1998
Main classification: H03K19
IPC codes: H03K19, H01L21