ZERO-DELAY SLEW-RATE CONTROLLED OUTPUT BUFFER

Abstract: An output buffer (100; 200) in accordance with the present invention exhibits a fixed output signal slew rate. The output signal behavior is independent of the capacitive load (CL) seen by the buffer. The circuit includes a capacitive feedback path from the output node to circuitry which drives the output transistors. In one embodiment, the feedback path comprises two capacitive elements (CFP, CFN), one which comes into play during a rising edge transition and the other which affects a falling edge transition. In a second embodiment, a single capacitive element (CF) is coupled to a switching circuit (P4, N4) for use during either a falling transition or a rising transition. The second embodiment provides precharging of the output transistor gates, and so improves response time.

Description: Description ZERO-DELAY SLEW-RATE CONTROLLED OUTPUT BUFFER TECHNICAL FIELD The present invention generally relates to output buffer circuitry, and more specifically to a slew-rate controlled output buffer circuit. BACKGROUND ART Output buffers found in integrated circuits provide an interface for driving external loads, both capacitive and inductive. External capacitive loads typically consist of the bonding wire, the pin, conductors on the printed circuit board, and the input capacitances of the gates to which an output buffer is coupled. The inductive load usually comprises the series parasitic inductances of the power supply and ground lines supply- ing the output buffer which in turn are coupled to the external power and ground rails on the printed circuit board. With traditional output buffers (i.e. an inverter chain), output transistor sizing is constrained by DC operating characteristics. This leads to several problems: unacceptably high current peaks which occur with the simultaneous switching of many output buffers; inductive power supply noise which results in large voltage drops, and electromagnetic interference due to high output edge switching rates. Inductive switching noise appears as an unde- sired undershoot or overshoot in the internal power supply or ground voltage rails, as the buffer supplies current to or sinks current from an external load. The resulting noise voltage is harmful in many ways. Firstly, non-switching circuits which share the same power and/or ground rails are subject to the switch- ing noise of active circuits, potentially causing spurious transitions at the inputs of the non-switching circuits. Secondly, switching speed is degraded since the noise narrows the gap between the power supply and ground voltage levels . Inductive switching noise is exacerbated when there is simultaneous switching of two or more circuits. Prior art solutions to these problems include reducing the signal swing, but at the cost of abandoning TTL compatibility, along with the added penalty of having to provide an extra power supply voltage. A simple approach is to slow down the turn-on time of the output switching transistor, but at the cost of having a transition time that is load-dependent and increasing the prop- agation delay. A circuit is required which provides a load independent slew rate controlled output signal. The circuit should be simple in design so that a minimum amount of silicon is needed to implement the circuit. SUMMARY OF THE INVENTION A first embodiment of the output buffer of the present invention includes an input stage comprising first and second inverters, each having an input terminal coupled to the input node of the buffer. The output terminal of each inverter drives the control gate of an output transistor. The two output transistors are coupled in a common drain configuration to the output node of the buffer. A capacitive feedback path is provided between the buffer output node and the control gates of the output transistors. The feedback controls the gate voltage such that it is maintained at a constant voltage during most of the time that an external load capacitance is charging or discharging during a rising or falling transition. The result is a constant drain current through the active output transistor and thus a constant slew rate that is independent of the output load. In a second embodiment of the present invention, the capacitive feedback path includes means for switching a capacitive element between each of the control gates of the output transistors. The capacitive element, already having a charge, serves to precharge the control gate of the active output transistor. This increases the response time of the output buffer and thus lowers the propagation delay. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a first embodiment of an output buffer in accordance with the present invention. Fig. 2A is a portion of the buffer circuit of Fig. 1 which is involved in a falling edge transition. Figs. 2B and 2C are equivalent circuits of Fig. 2A during different stages of circuit operation. Fig. 3 illustrates a schematic representation of the three regions of operation of the present invention for a falling edge transition. Figs. 4A and 4B are simulated gate and output waveforms respectively for the output buffer of the present invention and for a classic output buffer, during a falling edge transition. Figs. 5A and 5B are simulated current waveforms respectively for the output buffer of the present invention and for a classic output buffer, during a falling edge transition. Fig. 6 is a second embodiment of the output buffer of the present invention. Figs. 7A and 7B are simulated waveforms illustrating the operation of the circuit of Fig. 6, for a falling edge transition. BEST MODE FOR CARRYING OUT THE INVENTION Referring to Fig. 1, the output buffer circuit 100 in accordance with the present invention comprises an input node v A for receiving a digital signal. The input node is coupled to the control gates of four transistors: P-channel transistors P2 and P3 and N-channel transistors N2 and N3. Transistors P3 and N2 are coupled as an inverter II, and transistors P2 and N3 are coupled as inverter 12. The output of buffer 100 is driven by transistors Pi and Nl, whose drains are coupled to output node v 0 . The source of transistor Pi is coupled to V DD while the source of transistor Nl is coupled to ground potential. The control gate of transistor Pi is coupled to the drains of transistors P3 and N2. Similarly, the control gate of transistor Nl is coupled to the drains of transistors P2 and N3. Further in accordance with the present invention, a feedback path from output node v 0 to the control gate of transistor Pi includes a capacitive element C FP . Likewise, capacitive element C ra is provided between output node v 0 and the control gate of transistor Nl . In the context of the present invention, a "capacitive element" is meant to refer to an actual capacitor device (e«g« devices C^ and C FP ) which is to be distinguished from the parasitic capacitances inherently present in transistor devices. For example. Fig. 1 shows in phantom the parasitic gate capacitance C^, for output transistor Nl. Still further in accordance with the present invention, for reasons which will become clear in the discussion below, transistor P3 is sized so that its W/L ratio is greater than that of transistor N2. In like manner, transistor N3 has a W/L ratio greater than that of transistor P2. The specific sizing of the devices depends upon the particular application. As an example, the transistor sizes used to generate the waveforms shown in the figures were: Nl = 120/0.8; Pi = 360/0.8; N2 = 2/24; P2 = 6/24; N3 = 10/0.8; and P3 = 30/0.8. Turn now to a discussion of the operation of the circuit of Fig. 1. Consider the case of a falling transition of the input signal. At a time prior to such a transition, transistor P3 is OFF and transistor N2 is in saturation and thus fully ON. Thus, output transistor Pi is fully ON and so load capacitor C L is charged to V DD potential. Similarly, transistor P2 is OFF and transistor N3 is ON, thus keeping output transistor Nl in the non-conducting OFF state. Consider next the transition of the input signal to the lower voltage level. In such a situation, transistor N2 begins to turn OFF and transistor P3 begins to turn ON. Likewise, transistor N3 begins to turn OFF while transistor P2 begins to conduct. Recall that transistors P3, N2, N3, and P2 are sized so that P3 is stronger than N2 and N3 is stronger than P2; i.e. the W/L ratios of P3 and N3 are greater than N2 and P2 respectively. The consequence of such sizing is that the "in- active" output transistor (transistor PI in the case of a falling transition) will turn OFF faster than the "active" output transistor (namely transistor Nl) is turned ON. Conversely, in the case of a rising transition, the "inactive" output transistor Nl will turn OFF faster than the "active" output transistor PI turns ON by virtue of N3 being stronger than P2. This is an important aspect of the invention, because such transistor sizing serves to eliminate a short circuit current between output transistors PI and Nl during logic level transitions, thus isolating the circuitry which controls falling edge transitions from the circuitry which controls rising edge transitions. The falling edge circuitry of output buffer 100 comprises: output transistor Nl, feedback capacitor C ra , transistor P2, parasitic capacitance C^, and output load capacitor C L . These elements are shown in Fig. 2A. The waveform shown in Fig. 3 schematically illustrates three periods of time during the operation of the buffer for a falling edge transition. Referring to Figs. 2B and 3, transistor Nl is OFF at the beginning of region A, and is shown in the equivalent circuit of Fig. 2B as a switch in the open position. Transistor P2 is in saturation and thus be- haves like a constant current source, charging the parasitic gate capacitance C^, of transistor Nl until node v g reaches the threshold voltage of Nl. In the meantime, since Nl is OFF, the increasing voltage at node v g causes a corresponding increase in v 0 through feedback capacitor C ra . The time equations of the variation at node v g and at the output node v 0 can be determined. The time function v g (t) for node v g is: v σ (t) _I_ r Eqn, where C j is the total capacitance node v ( and I is the current provided by transis- tor P2 The time function v 0 (t) for the output node is: v 0 ( ) = V DD + C ^ • v g (t) Eqn. 2 Referring to Figs. 2C and 3, operation of the output buffer in region B and the corresponding equivalent circuit are shown. As P2 continues to charge capacitor C ra , the gate voltage at node v g continues to rise until output transistor Nl begins to turn ON. Consequently, the output load C L begins to discharge through Nl. At the same time, capacitor C^ also begins to discharge through Nl. This tends to slow the rising voltage at node v g , which in turn reduces the current in Nl. The rate at which C ra discharges through Nl depends on the size of the load capacitance C L . C pH , however, continues to be charged by transistor P2. This tends to raise the potential at node v g . and consequently the current in Nl . This feedback effect will result in an equilibrium state where the discharge rate of capacitor C^ through output transistor Nl is balanced by the charge rate of transistor P2. Thus at equilibrium, the voltage at node v g (i.e. the gate voltage of transistor Nl) remains constant during operation of the output buffer 100 in region B. Since the gate voltage remains constant, output transistor Nl behaves like a constant current source, generating a constant output slope. The fall time for a falling edge transition therefore is perfectly controlled in this fashion. As in the case of operation in region A, the equations for the voltage a node v g and the time function v 0 (t) for output node v 0 can be determined. The standard quadratic equation for modeling transistor activity in saturation is used for transistor Nl, namely: I = -^ • (V g - V ral ) 2 Eqn, where: K N1 is the transistor gain of Nl V TO1 is the threshold voltage of Nl I N1 is the current in Nl From which the constant gate voltage at node v g is: At equilibrium, V g is constant because Nl gate charging (by current I) is fully compensated by the dis- charge of the output load, leading to: and the current in transistor Nl is: dv. I NI = "(C L + C ra ) -^ , Eqn. 6 Eqns. 5 and 6 can be used together to recast Eqn. 4 as: The time varying function v 0 (t) for the output voltage is determined as follows: dv n I - -c Eqn. 8 c ™ d t V Q (t)) == VV DDD + FN V o ( t D + _ ^ r " • • Vv GG - - - I- (t - t A ) c *-FN + c ^ c ^ where : t A is the duration of region A and is equal to CI • V r -, C 1 being taken from Eqn. 1; V G is the constant gate voltage expressed in Eqn. 7; and the integration constant is V DD + —— • V G , ^FN + ^ which takes into account the overshoot induced by the feedback capacitor during operation in region A. The voltage V G represents the control voltage to be applied to the output transistor Nl in order to discharge the output load C L with a constant slope in a given time. It can be seen that the output slope is constant and depends only on internal elements, namely the charging current I provided by transistor P2 and the capacitance of feedback capacitor C^. The current I N1 through output transistor Nl during the discharge is adjusted to the load C L , so that the slope of the output v 0 is inde- pendent of the load. Referring once again to Fig. 3, operation of the buffer in region C continues with the gate voltage at node v g continuing to rise after the load capacitor is fully discharged. The gate of output transistor Nl, therefore, will continue to rise until it reaches V DD providing at that time full DC characteristics. From the above equations, the propagation delay t PHL and the fall time t SHL can be deduced. The propagation delay is the sum of the delay in region A t A and the delay necessary for the output to reach one-half of the supply voltage V DD , thus: The fall time is measured between 90% and 10% of the output variation, thus : t SHL = ^ψ O . 8V DD Eqn . 10 Notice that in Eqn. 10, the fall time is independent of the output load C L . Turn now to the waveforms shown in Figs. 4A and 4B. These waveforms show the gate voltage measured at node v g and the output voltage measured at output node v 0 . Waveforms are generated for varying output loads: 10 pF, 30 pF, 100 pF, and 300 pF; for an output buffer in accordance with the present invention shown in Fig. 4A and for a classic output buffer shown in Fig. 4B. Fig. 4A also identifies the three regions A - C of operation initially shown in Fig. 3. Consider first Fig. 4A. The effect of the feedback capacitor is shown in region B where the gate voltage is flat. As a result of the constant gate volt- age, the slew rate of the signal at the output node v 0 is constant for all capacitive loads. The effects of the load capacitance do not come into play until the device is operating in region B. As shown in Fig. 4A, the load capacitance C L determines the time it takes for the charg- ing and discharging of feedback capacitor C^ to reach equilibrium, as evidenced by the onset of the flat portion of the V g waveforms. By comparison, the waveform shown in Fig. 4B of a classic buffer without the feedback capacitor shows that the gate voltage reaches V DD almost instantaneously, thus putting output transistor Nl immediately into saturation. Consequently, with transistor Nl at maximum conductivity, the discharge rate at the output node v 0 is a function of the time constant defined by the load ca- pacitance C L and the channel resistance of Nl. The slew rate therefore will vary with the capacitive load, since the channel resistance remains constant. Fig. 5A shows that output buffer 100 produces a constant drain current in transistor Nl during operation in region B, the current self-adjusts to different levels depending on the load C L . Because of this self-adjusting behavior, the discharge time is the same regardless of the size of the load. A larger load having a greater charge stored, will discharge more current in a given amount of time, while a smaller load having a smaller charge stored will discharge less current in that same amount of time. The result is a constant slew rate regardless of load capacitance. In contrast, the drain current profile of a classic output buffer shown in Fig. 5B indicates that the load discharges at the maximum rate, the time for discharge simply being a function of the amount of charge stored in the load. The result is a slew rate that varies depending on the load capacitance. As a final observation, the propagation delay of the present invention is increased by a factor of about eight, as can be seen by comparing the output waveforms in Figs. 4A and 4B. Referring to Figs. 5A and 5B, the circuit of the present invention shows a reduced current peak by the same factor. The reduced current peak helps to minimize noise. As can be seen in Fig. 5A, the current reducing capability is even better for smaller loads. The foregoing discussion addresses the operation of the output buffer during a falling transition, and so focuses on the bottom half of the buffer circuitry 100 depicted in Fig. 1. A similar analytical treatment is possible with respect to a rising transition which involves the upper half of the buffer circuitry. It can be shown that for a rising transition, the slope of the changing voltage at output node v 0 is the same regardless of the capacitive load C L . Turn now to Fig. 6 for a discussion of a second embodiment of the invention. Transistors Pi - P3 and Nl - N3 are the same as those comprising output buffer 100 in Fig. 1. The embodiment shown in Fig. 6 includes an inverter 202 whose input is coupled to input node Vi. Transistor P4 has a first terminal coupled to the control gate of output transistor PI and a second terminal coupled to node v f . Transistor N4 has a first terminal coupled to the control gate of output transistor Nl and a second terminal coupled to node v f . The gates of transistors P4 and N4 are tied together and coupled to the out- put of inverter 202. A feedback capacitor C F is coupled between output node v 0 and node v f . As will be discussed below, transistors P4 and N4 serve as a switching element to selectively couple one end of feedback capacitor C F either to the control gate of output transistor Pi or the control gate of output transistor Nl. Operation of the circuit 200 shown in Fig. 6 is similar to the circuit of Fig. 1 in all respects, except for the following aspect. Consider a falling transition. The conditions just prior to the transition are: the potential at input node v ± is V DD . Thus, transistors N2, N3, and P4 are turned ON, while transistors P3, P2, and N4 are OFF. Consequently, the gate voltage of output transistor Pi is held at zero by transistor N2, and the gate voltage of output transistor Nl is held at zero by transistor N3. PI is therefore ON and output node v 0 is held at V DD . The output of inverter 202 is zero, thus turn- ing ON transistor P4 and turning OFF transistor N4. Observe that although P4 is ON, the potential at node v f cannot rise above -V tp4 , the threshold voltage of P4. The reason is that, under these conditions, node v f is the source node for P4. Recall that conduction occurs when V gs >= V t . In this case, V gs = 0 - V £ , where V f is the potential at node v f . When V f reaches -V tp4 , any tendency for node v f to rise above -V tP4 will turn OFF P4. V f/ therefore, stabilizes at -V tP4 . Similarly, it can be shown that in a rising transition scenario V f will not rise above (V DD - V tN4 ). When the transition occurs, transistor N4 turns ON, thus transferring the charge at feedback capacitor C F to the gate of output transistor Nl through a process known as charge sharing. Thus, the gate of Nl can be precharged to a level close to its threshold voltage by appropriately sizing the feedback capacitor C F . In accordance with the invention, N4 is fully turned ON prior to transistor P2 turning ON. This is accomplished by sizing the P-channel and N-channel tran- sistors of inverter 202 so that they are faster than P3/N2 and P2/N3. Thus, during a falling transition, inverter 202 will go high before transistor P2 turns ON, and during a rising transition, the inverter will go low -13- before transistor N2 turns ON. This provides a quick precharge of the gate of Nl (or PI in the case of a rising transition) before the transistor P2 (N2) turns ON and begins charging the gate. By precharging the gate, the output load C L can begin to discharge at an earlier time during the transition as compared to the buffer circuit of Fig. 1. Consequently, the propagation delay is reduced. The gain on the propagation delay due to the precharging is equal to the delay necessary, with the circuit of Fig. 1, for the gate voltage to reach the precharge voltage. Considering that the value of the feedback capacitor C F is negligible against the value of the output load C L , the following expression for the propagation delay is obtained: c + c -PHL v G + 'DD - |v t | Eqn. 11 where : Vt is the threshold voltage of transistor P4 in the case of falling transitions, and N4 in the case of rising transitions. In addition, overshoots are also reduced because of the precharging by feedback capacitor C F . The precharging eliminates the charge build-up at the output that occurs with the circuit of Fig. 1 as the gate capacitance is being charged during operation in region A (Fig. 3). With precharging, there is effectively no region A. This is shown in Fig. 7A where it can be seen that the gate voltage instantly reaches the threshold voltage of the output transistor (Pi, Nl) due to precharging by the feedback capacitor. Thus, the onset of the falling edge occurs at a time earlier than in the circuit of Fig. 1, and so propagation delay is reduced. Note that precharging also has eliminated the overshoot that exists at the onset of the falling transition in the circuit of Fig. 1. The drain current profiles of Fig. 7B also show the increased responsiveness of output buffer 200 as compared to the profile of Fig. 5A for output buffer 100. Another aspect of the embodiment of Fig. 6 is the reduced area of the circuitry on silicon. Note that the circuit of Fig. 6 uses one feedback capacitor C F as compared to the circuit of Fig. 1 which uses two feedback capacitors C ra , C FP . Capacitors consume a large area as compared to transistors. For example, a 1 pF capacitor is roughly 25 x 55 μM in area. Thus, while the circuit of Fig. 6 uses more transistors than does the circuit of Fig. 1, the total area required of the former circuit is still smaller than that of the latter circuit because of the use of only one capacitor. Typical W/L ratios for transistors N4, P4 are 8/0.8 μM and 24/0.8 μM respectively. Similarly, the transistors comprising inverter 202, are also small; e.g. 4/0.8 μM for the N-channel device and 12/0.8 μM for the P-channel device are deemed sufficient for driving the small gate capacitances of transistors N4 and P4.

Claims: Claims 1. An output buffer circuit comprising: a signal-receiving node (Vi); a first inverter (P3,N2) having input and output terminals, the input terminal coupled to the signal-receiving node; a second inverter (P2,N3) having input and output terminals, the input terminal coupled to the signal-receiving node; a first output transistor (Pi) having first and second terminals and having a gate terminal coupled to the output terminal of the first inverter; a second output transistor (Nl) having first and second terminals and having a gate terminal coupled to the output terminal of the second inverter; a signal output node (Vo) to which the second terminal of the first output transistor and the first terminal of the second output transistor are coupled; and a capacitive feedback means (CFP,CFN;CF) for coupling the signal output node back to the gate terminals of the first and second output transistors. 2. The output buffer circuit of claim 1 wherein the capacitive feedback means includes a first capacitive element (CFP) coupled between the signal output node and the gate terminal of the first output transistor (Pi) and a second capacitive element (CFN) coupled between the signal output and the gate terminal of the second output transistor (Nl). 3. The output buffer circuit of claim 2 wherein the first output transistor (PI) is a P-channel device and the second output transistor (Nl) is an N-channel device, 4. The output buffer circuit of claim 1 wherein the capacitive feedback means further includes third and fourth transistors (P4,N4) coupled in series and connected between the gates of the first and second output transistors, and a third inverter (202) coupled between the signal-receiving node and gates of the third and fourth transistors. 5. The output buffer circuit of claim 4 wherein the first output transistor (Pi) is a P-channel device and the second output transistor (Nl) is an N-channel device, 6. The output buffer circuit of claim 5 wherein the third transistor (P4) is a P-channel device and the fourth transistor (N4) is an N-channel device. 7. The output buffer circuit of claim 1 wherein the first inverter includes a P-channel device (P3) and an N-channel device (N2), the P-channel device having a greater W/L ratio than the N-channel device. 8. The output buffer circuit of claim 7 wherein the second inverter includes a P-channel device (P2) and an N-channel device (N3), the N-channel device having a greater W/L ratio than the P-channel device. 9. An output buffer circuit comprising: an input node (Vi) and an output node (Vo); an input stage having first and second inverters (P3,N2;P2,N3) , each inverter having an input coupled to the input node; a P-channel transistor (PI) having a gate terminal coupled to an output of the first inverter and further having a drain terminal coupled to the output node (Vo); an N-channel transistor (Nl) having a gate terminal coupled to an output of the second inverter and further having a drain terminal coupled to the output node (Vo); a first capacitive element (CFP) coupled between the drain and gate terminals of the P-channel transistor; and a second capacitive element (CFN) coupled between the drain and gate terminals of the N-channel transistor. 10. The output buffer circuit of claim 9 wherein the first inverter includes a P-channel device and an N-channel device, the P-channel device having a greater width dimension than the N-channel device. 11. The output buffer circuit of claim 9 wherein the second inverter includes a P-channel device and an N-channel device, the N-channel device having a greater width dimension than the P-channel device. 12. An output buffer comprising: a signal input node (Vi); a signal output node (Vo); a first inverter (P3,N2) having an input terminal coupled to the signal input node and further having an output terminal; a pull-up transistor (PI) having a first terminal for being coupled to a first potential, a second terminal coupled to the signal output node, and a control terminal coupled to the output terminal of the first inverter; a second inverter (P2,N3) having an input terminal coupled to the signal input node and further having an output terminal; a pull-down transistor (Nl) having a first terminal for being coupled to a second potential, a second terminal coupled to the signal output node, and a control terminal coupled to the output terminal of the second inverter; and a capacitive feedback path having a capacitive element (CF) and switching means (P4,N4,202), the capacitive element having a first end coupled to the signal output node, the switching means for selectively coupling a second end of the capacitive element between the control gate of the pull-up transistor and the control gate of the pull-down transistor. 13. The output buffer of claim 12 wherein the switching means includes a third inverter (202), a P-channel transistor (P4), and an N-channel transistor (N4); the third inverter having an input terminal coupled to the signal input node (Vi) and further having an output terminal coupled to control gates of the P-channel and N-channel transistors; the transistors having a common drain connection; a source of the P-channel transistor coupled to the control gate of the pull-up transistor (PI); a source of the N-channel transistor coupled to the control gate of the pull-down transistor (Nl); the common drain connection being coupled to the second end of the capacitive element (CF). 14. The output buffer circuit of claim 12 wherein the first inverter includes a P-channel device (P3) and an N-channel device (N2), the P-channel device having a greater W/L ratio than the N-channel device. 15. The output buffer circuit of claim 14 wherein the second inverter includes a P-channel device (P2) and an N-channel device, the N-channel device (N3) having a greater W/L ratio than the P-channel device. AMENDED CLAIMS [received by the International Bureau on 19 March 1999 (19.03.99); original claims 2-4 and 9-1 1 cancelled; original claims 1 and 12 amended; remaining claims unchanged (3 pages)] 1. An output buffer circuit comprising: a signal-receiving node (Vi) ; a first inverter (P3,N2) having input and output terminals, the input terminal coupled to the signal-receiving node; a second inverter (P2,N3) having input and output terminals, the input terminal coupled to the signal-receiving node; a first output transistor (PI) having first and second terminals and having a gate terminal coupled to the output terminal of the first inverter; a second output transistor (Nl) having first and second terminals and having a gate terminal coupled to the output terminal of the second inverter; a signal output node (Vo) to which the second terminal of the first output transistor and the first terminal of the second output transistor are coupled; and a capacitive feedback means (CF) for coupling the signal output node back to the gate terminals of the first and second output transistors, including third and fourth transistors (P4,N4) coupled in series and connected between the gates of the first and second output transistor and a third inverter (202) coupled between the signal-receiving node and gates of the third and fourth transistors. Canceled Canceled Canceled 5. The output buffer circuit of claim 4 wherein the first output transistor (PI) is a P-channel device and the second output transistor (Nl) is an N-channel device. 6. The output buffer circuit of claim 5 wherein the third transistor (P4) is a P-channel device and the fourth transistor (N4) is an N-channel device. 7. The output buffer circuit of claim 1 wherein the first inverter includes a P-channel device (P3) and an N-channel device (N2) , the P-channel device having a greater W/L ratio than the N-channel device. 8. The output buffer circuit of claim 7 wherein the second inverter includes a P-channel device (P2) and an N-channel device (N3) , the N-channel device having a greater W/L ratio than the P-channel device. 9. Canceled 10. Canceled 11. Canceled 12. An output buffer comprising: a signal input node (Vi) ; a signal output node (Vo) ; a first inverter (P3,N2) having an input terminal coupled to the signal input node and further having an output terminal; a pull-up transistor (PI) having a first terminal for being coupled to a first potential, a second terminal coupled to the signal output node, and a control terminal coupled to the output terminal of the first inverter; a second inverter (P2,N3) having an input terminal coupled to the signal input node and further having an output terminal; a pull-down transistor (Nl) having a first terminal for being coupled to a second potential, a second terminal coupled to the signal output node, and a control terminal coupled to the output terminal of the second inverter; and a capacitive feedback path having a capacitive element (CF) and switching means (P4,N4,202), the capacitive element having a first end coupled to the signal output node, the switching means for selectively coupling a second end of the capacitive element directly to either the control gate of the pull-up transistor the control gate of the pull-down transistor. 13. The output buffer of claim 12 wherein the switching means includes a third inverter (202) , a P-channel transistor (P4), and an N-channel transistor (N4) ; the third inverter having an input terminal coupled to the signal input node (Vi) and further having an output terminal coupled to control gates of the P-channel and N-channel transistors; the transistors having a common drain connection; a source of the P-channel transistor coupled to the control gate of the pull-up transistor (PI) ; a source of the N-channel transistor coupled to the control gate of the pull-down transistor (Nl) ; the common drain connection being coupled to the second end of the capacitive element (CF) . 14. The output buffer circuit of claim 12 wherein the first inverter includes a P-channel device (P3) and an N-channel device (N2) , the P-channel device having a greater W/L ratio than the N-channel device. 15. The output buffer circuit of claim 14 wherein the second inverter includes a P-channel device (P2) and an N-channel device, the N-channel device (N3) having a greater W/L ratio than the P-channel device. STATEMENT UNDER ARTICLE 19 The invention is directed to an output buffer circuit having an input node and an output node, with first and second inverters having inputs coupled to the input node. Outputs of the inverters are coupled to the gates of first and second drive transistors. The drive transistors have a common drain connection coupled to the output node. A capacitive feedback path includes series coupled third and fourth transistors having a common gate connection and a common drain connection. A capacitor is coupled between the common drain and the output node. An inverter is coupled between the input node and the common gate. The reference to Boomer shows in Figs. 2 and 3 an output buffer having a capacitive feedback path comprising a first capacitor (Cp) coupled between the output node (Vout) and the gate of a first drive transistor (PI) and a second capacitor (Cn) coupled between the output node and the gate of a second drive transistor (Nl) . No other capacitive feedback paths are shown. The reference to Lewis shows in Fig. 4 an output buffer having a first capacitor (Cin) coupled between the gate of a first drive transistor (20) and ground and a second capacitor (Cip) coupled between the gate of a second drive transistor (22) and ground. The Lewis reference does not disclose the use of any capacitive feedback paths. The reference to Nessi et al. is directed to a slew rate controlled output driver for use with switched inductive loads. The circuitry disclosed avoids the immediate and abrupt transfer of charge that characterizes switched circuits. Figure 3 shows a circuit which avoids such changes in current. The circuit includes a pair of integrating stages (op-amps, unnumbered) which share a capacitor (cu) . The capacitor is switched (si, s2) between the op-amps. Signals (NW, PW) operate each switch in synchrony so that capacitor (cu) is coupled to only one op-amp at a time. The slew rates during the turn-off phase of the output transistors (PU, NU) are controlled to avoid abrupt changes by an integrating effect during operation of the integrating stages.

Inventors: GARCIA FLORENT, GARCIA, FLORENT
Applicants: ATMEL CORP, ATMEL CORPORATION
Application year: 1998
Main classification: H03K3
IPC codes: H03F3, H03K5, H03K17, H03K19