METHOD AND ARRANGEMENT IN A DC-TO-DC CONVERTER

Abstract: A method and an arrangement for controlling the output voltage (V2) of a DC-to-DC converter (100). The DC-to-DC converter (100) comprises converting means (101) and regulating means (102). The converting means is fed by a first DC-voltage (V1) from the regulating means. The first DC-voltage (V1) is determined by a feed back portion (VDIV) of the output voltage (V2) from the converting means and a reference voltage (VREF). The reference voltage is derived from a pulse train (PT1). The output voltage (V2) depends on both the first DC-voltage (V1) and the pulse train (PT1). The output voltage (V2) from the DC-to-DC converter is kept constant under varying load and the output voltage level can be adjusted in an easy and flexible manner by the pulse train.

Description: METHOD AND ARRANGEMENT IN A DC-TO-DC CONVERTER TECHNICAL FIELD OF THE INVENTION The invention relates to a method and an arrangement for controlling the output voltage of a DC-to-DC converter. DESCRIPTION OF RELATED ART On a printed circuit board in e.g. a mobile phone different electronic devices (e.g. LCD, digital signal processor etc) may need to be fed with different supply voltages. These different supply voltages are often generated from a single DC-power source, e.g a battery, by DC-to-DC converters. A problem with these converters is that they very often have a rather high output impedance, which results in a change of their output when the load changes . To ensure that the output voltage does not change when the load changes some kind of regulation circuit must be applied. In addition, some circuitry needs to be fed with different output voltage levels at different times. For an example, the supply voltage to a LCD display typically needs to be adjusted according to the temperature. This implies the need for an easy and flexible way of adjusting the output voltage level of the DC-to-DC converter to different levels. One known way to implement this regulation circuit, in connection with a DC-to-DC converter whose output voltage depends on the pulse frequency of a pulse train applied as input to the DC-to-DC converter, is to feed-back the DC-to- DC converter output voltage via an A/D-converter to a micro controller. The micro controller then adjusts the parameters of the pulse train generator such that the desired output voltage from the DC-to-DC converter is maintained. Two disadvantages of this solution is that it requires an A/D- converter and the extra processing burden on the micro controller. Japanese patent abstract JP 63-228.809 discloses an arrangement for securing a constant output voltage level from a DC-to-DC converter. The output voltage of the DC-to- DC converter is fed back via a voltage divider and applied to an inverting input terminal of an operational amplifier. An input voltage is applied to a non- inverting input terminal of the operational amplifier. The operational amplifier controls the supply voltage to the DC-to-DC converter so that the output voltage level of the DC-to-DC converter is kept at a constant relation with the input voltage applied to the non-inverting input terminal of the operational amplifier. The patent abstract provides no details on how to adjust the output voltage to different levels. The datasheet for the MAX662 regulated charge pump DC-to-DC converter from Maxim, discloses that in the MAX662 circuit energy is accumulated in a set of charge-pump capacitors and then transferred to an output capacitor building up an output voltage over that capacitor. The MAX622 circuit comprises an oscillator providing pulses that controls the energy transfer form the charge-pump capacitors to the output capacitor. Regulation of the output voltage from the MAX622 circuit is provided by a pulse-skipping scheme that monitors the output voltage level and turns on the charge pump, i.e. enables the oscillator, when the output voltage begins to drop and turns off the charge pump, i.e. disables the oscillator, when the correct output voltage is reached. The MAX662 circuit provides a fixed +12 V output voltage i.e. the output voltage level can not be adjusted. A frequency-to-voltage converter could be regarded as performing some kind of DC-to-DC converting, since the frequency-to-voltage converter is fed by one DC-voltage and on its output terminal a second DC-voltage is produced whose value depends on the frequency of a signal applied to an input terminal. However, the frequency-to-voltage converter is, unlike an DC-to-DC converter, not intended to provide supply current to other circuits but is only intended to produce a voltage that can be sensed by other circuits and be used as a measure of the frequency of the applied signal to its input terminal. Furthermore, the frequency-to-voltage converter can also not provide an output voltage level above the supply voltage level . SUMMARY OF THE INVENTION The problem dealt with by the present invention is how to provide a DC-to-DC converter whose output voltage does not vary with the connected load and whose output voltage level can be adjusted in an easy and flexible manner. ' The problem is solved essentially by a method and arrangement in which an internal converting means of the DC-to-DC converter is fed by a first DC-voltage. This first DC-voltage is determined by a comparision of a fed back portion of the output voltage from the converting means and a reference voltage. The reference voltage is derived from a pulse train. More specifically, the problem is solved in the following manner. The DC-to-DC converter comprises the converting means and a regulating means. A first pulse train and the first DC-voltage is received by the converting means, which generates a second DC-voltage being the output voltage from the DC-to-DC converter. The second DC-voltage is depending on both the first DC-voltage and the first pulse train. The output voltage from the DC-to-DC converter, i.e. the second DC-voltage, is fed back to the regulating means. The regulating means compares a portion of the fed back second DC-voltage with the reference voltage and generates the first DC-voltage such that said portion of the second DC- voltage is forced towards the reference voltage level. The regulating means receives a second pulse train from which the reference voltage is generated. According to one embodiment of the invention, the second pulse train, received by the regulating means, is essentially the same as the first pulse train, received by the converting means. One intention of the invention is to provide a method and arrangement enabling the output voltage from the DC-to-DC converter to be maintained at a constant level regardless of the connected load. Another intention of the invention is to provide a method and arrangement which in an easy and flexible manner enables the output voltage level of the DC-to-DC converter to be adjusted. One advantage afforded by the invention is that the output voltage of the DC-to-DC converter can be kept at a constant level even if the load varies . Another advantage is that the output voltage level of the DC-to-DC converter can be adjusted in an easy and flexible manner . The invention will now be described in more detail with reference to exemplifying embodiments thereof and also with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a block diagram of an arrangement according to the invention. Fig. 2 is a more detailed block diagram of the arrangement according to Fig. 1. Fig. 3 is a block diagram of a simple frequency-to-voltage converter. Fig. 4 is a block diagram of a capacitor based charge pump. Fig. 5 is a block diagram of a coil based charge pump. Fig. 6A is a time diagram illustrating a pulse train having a low frequency. Fig. 6B is a time diagram illustrating a pulse train having a higher frequency. Fig. 7 is a function diagram illustrating an increasing function Fig. 8A-8B are flow charts illustrating the method steps carried out by the DC-to-DC converter in Fig. 1. DETAILED DESCRIPTION OF THE EMBODIMENTS Fig. 1 illustrates how a DC-to-DC converter 100 according to one embodiment of the invention is used to supply power to a load 120, e.g. an LCD-display. The load 120 may both be varying, i.e. a current I extracted from the DC-to-DC converter 100 may vary, and require to be fed by the DC-to- DC converter 100 with different voltage V2 at different times . The DC-to-DC converter 100 has a first input terminal 111 , a second input terminal 112 and an output terminal 113. The DC-to-DC converter 100 comprises converting means 101 and regulating means 102. The converting means 101 has a first input terminal 103, a second input terminal 104 and an output terminal 105. The second input terminal 104 of the converting means 101 is connected to the second input terminal of the DC-to-DC converter 100 and the output terminal 105 of the converting means 101 is connected to the output terminal 113 of the DC- to-DC converter 100. The converting means 101 receives a first DC-voltage VI on the first input terminal 103. The converting means receives a first pulse train PTl on the second input terminal 104 via the second input terminal of the DC-to-DC converter 100. The first pulse train PTl has a pulse frequency FI . The converting means emits the voltage V2 , hereinafter denoted as second DC-voltage V2 , on the output terminal 105. This second DC-voltage V2 is emitted to the load 120 via the output terminal 113 of the DC-to-DC converter 100. The second DC-voltage V2 depends on both the first DC-voltage VI and the frequency FI of the first pulse train PTl . The converting means may e.g. be implemented as a capacitor based charge pump or a coil based charge pump. See Fig. 4 and Fig. 5 respectively. The regulating means 102 has a first input terminal 106, connected to the first input terminal 111 of the DC-to-DC converter 100, for receiving a supply voltage VS from a DC- power source 107. The DC-power source 107 is typically a battery. The regulating means 102 further has a second input terminal 108, connected to the output terminal 105 of the converting means 101, for sensing the second DC-voltage V2 emitted by the converting means 101. The regulating means 102 has a third input terminal 109 for receiving a second pulse train. In this specific embodiment, the second input terminal 104 of the converting means 101 and the third input terminal 109 of the regulating means 102 are joined together and hence the second pulse train is identical with the first pulse train PTl. The regulating means 102 also has an output terminal 110 connected to the first input terminal 103 of the converting means 101. The regulating means 102 compares a portion of the sensed second DC- oltage V2 with a reference voltage (VREF, see Fig. 2) and generates on the output terminal 110 the first DC- voltage VI supplied to the converting means 101. Fig. 2 provides more details on the internal structure of the DC-to-DC converter 100 and in particular the internal structure of the regulating means 102. The regulating means 102 comprises a differential amplifier 201, a frequency-to-voltage converter 202 and two resistors 203, 204 connected in series and having values Rl and R2 respectively. The differential amplifier 201 has an output terminal 205, an inverting input terminal 206 and a non-inverting input terminal 207. The output terminal of the differential amplifier 201 is connected to the output terminal 110 of the regulating means 102. The frequency-to-voltage converter 202 has an input terminal 208 and an output terminal 209. The converter input terminal 208 is connected to the input terminal 109 of the regulating means 102 and the converter output terminal 209 is connected to the non-inverting input terminal 207 of the differential amplifier 201. The two resistors 203, 204 are connected between the second input terminal 108 of the regulating means 102 and ground GND. A point between the two resistors is connected to the inverting input 206 of the differential amplifier 201. The frequency-to-voltage converter 202 generates said reference voltage VREF. In this embodiment, the generated reference voltage VREF is proportional to the frequency FI of the first pulse train PTl and this relation can thus be described as VREF=K*F1 (1) . The two resistors 203, 204 acts as a voltage divider and provides, at said point between the two resistors 203, 204, a portion of the second DC-voltage V2. The relation between the portion VDIV and the second DC-voltage V2 can be expressed as VDIV=V2*R2/ (R1+R2) (2). The second DC-voltage V2 emitted by the converting means 101 increases as the first DC-voltage VI increases i.e. the second DC-voltage V2 expressed as a function of the first DC-voltage VI has a positive derivative. The differential amplifier 201 has a sufficiently high amplification that the feed-back loop will force the voltage level VDIV at the inverting input terminal 206 towards the voltage level VREF applied to the non-inverting input terminal 207, i.e. the feed-back loop will try to keep the voltage difference VREF-VDIV=0 (3) . By combining equations (1), (2) and (3) the following approximative relationship between the second DC-voltage V2 and the frequency FI of the first pulse train PTl is found: V2=K* (R1+R2) /R2*F1 (4) Any variations of the load 120 in Fig. 1 will be compensated by the feed back loop in order to satisfy equation (4) . Fig. 3 shows a simple way of implementing the frequency-to- voltage converter 202 of Fig. 2. A resistor 301 and capacitor 302, with values R and C respectively, are connected in series between the input terminal 208 of the frequency-to-voltage converter 202 and ground GND. The output terminal 209 of the frequency-to-voltage converter 202 is connected to a point between the resistor 301 and capacitor 302. The circuit in Fig.3 acts as an integrator. The first pulse train PTl is illustrated in the time diagrams Fig. 6A and Fig. 6B. In these time diagrams time has a common denotation T. In Fig. 6A each pulse has a pulse duration Tl and a pulse distance T2. In Fig. 6B each pulse has the same pulse duration Tl as in Fig. 6A, but the pulse distance T3 is shorter than in Fig. 6A. The pulse train has a frequency FI . For the pulse train PTl a duty cycle DC1 can be defined as the relation between the pulse duration Tl and the pulse distance T2 , e.g. DCl=Tl/T2. The duty cycle DC1 has a lower value in Fig. 6A than in Fig. 6B. If the characteristics of the first pulse train PTl is such that the pulse duration, as illustrated in Fig. 6A and Fig. 6B, is not changed with a variation of the frequency FI and the frequency FI is much smaller than 1/ (2πRC) the relationship according to equation (1) holds for the circuit in Fig. 3 and the constant K will be close to one. The converting means 101 in Fig. 1 can be implemented in different ways. Fig. 4 illustrates an embodiment of the converting means comprising a capacitor based charge pump 400. The capacitor based charge pump 400 comprises a first diode 401 and a second diode 402, each having a cathode and an anode. The anode 405 of the first diode 401 is connected to the first input terminal 103 of the converting means, the cathode 406 of the first diode 401 is connected to the anode 407 of the second diode 402, the cathode 408 of the second diode is connected to one pole of a first capacitor 403 while the other pole of the first capacitor 403 is connected to ground GND. A second capacitor 404 is connected between the second input terminal 104 of the converting means and a point between the two diodes 401, 402. The output terminal 105 of the converting means is connected to a point between the second diode 402 and the first capacitor 403. When a pulse in the pulse train PTl arrives at the second input terminal 104, the voltage in the point between the diodes 401 and 402 is raised from the first voltage VI (minus a diode forward bias) with the amplitude of PTl. If this voltage (minus a diode forward bias) exceeds the second voltage V2 over the first capacitor 403, then the first capacitor 403 is charged by a current flowing from the second capacitor 404 to the first capacitor 403. When the trailing edge of the pulse reaches the second input terminal 104, the voltage in the point between the diodes 401 and 402 will be lowered. If the voltage fall below the first voltage VI (minus a diode forward bias) then a current will flow from the source supplying the first voltage VI, i.e. the regulating means 102 in Fig. 2, to the capacitor 404. This procedure will be repeated for each pulse in the pulse train PTl resulting in the second voltage V2 over the first capacitor 403 being close to the sum of the first voltage VI and the amplitude of the pulse train PTl, assuming a neglible load connected to the output terminal 105. The second voltage V2 is held constant at varying load by the feed back arrangement described in connection with Fig. 2. Fig. 5 illustrates a second embodiment of the converting means comprising a coil based charge pump 500. The coil based charge pump 500 comprises an inductor 501, a transistor 502, a diode 503, and a capacitor 504. The transistor has a collector 505, an emitter 506 and a base 507. The diode has an anode 508 and a cathode 509. The inductor 501 is connected at one pole to the first input terminal 103 of the converting means and connected at the other pole to the collector 505 of the transistor 502. The emitter 506 of the transistor 502 is connected to ground GND. The base 507 of the transistor 502 is connected to the second input terminal 104 of the converting means. The anode of the diode 503 is connected to the collector 505 of the transistor 502, the cathode 509 of the diode 503 is connected to one pole of the capacitor 504 and the other pole of the capacitor 504 is connected to ground GND. The output terminal 105 of the converting means is connected to a point between the diode 503 and the capacitor 504. When a positive pulse in the pulse train PTl arrives at the second input terminal 104, the transistor 502 will open up and provide a low resistans connection between the inductor 501 and ground GND. As one end of the inductor 501 is connected to the first input terminal 103 on which the first (positive) voltage VI is received from a source, i.e. the regulating means 102 in Fig. 2, a current will flow through the inductor 501 to ground GND. When the trailing edge of the pulse reaches the second input terminal 104, the transistor 502 will close and cut off the current flowing through the transistor 502. The inductor 501 reacts by inducing a positive voltage at its pole connected to the diode 503. If this voltage exceeds the second voltage V2 over the capacitor 504 (minus a diode forward bias) , then the capacitor 504 will be charged by a current from the inductor 501. This procedure will be repeated for each pulse in the pulse train PTl, resulting in the second voltage V2 over the capacitor 504 that is higher than the first voltage VI. The second voltage V2 depends on the inductance value, the frequency FI of the pulse train PTl and the duty cycle DC1 of the pulse train PTl, as well as the load connected to the capacitor 504. In the example of Fig. 1, the first pulse train PTl is generated by a micro controller 121 having inherent support for generating a train of pulses. The pulse duration and pulse distance, e.g. Tl respective T2 in Fig. 6A, are set by writing appropriate values in specific registers of the micro controller 121. The flowcharts in Fig. 8A and Fig. 8B describes a method according to the invention such as carried out by the DC-to- DC converter 100 illustrated in Fig. 1 and Fig. 2. Fig. 8A illustrates the method steps carried out in the converting means 101. In step 801 the first pulse train PTl is received from the micro controller 121. The first DC- voltage VI is received in step 802 from the regulating means 102. In step 803, the second DC-voltage V2 is generated as described previously. These method steps 801-803 are carried out repeatedly in the converting means 101. Fig. 8B illustrates the method steps carried out in the regulating means 102. In step 804 the supply voltage VS is received from the DC-power source 107. In step 805 the second DC-voltage V2 is received from the converting means 101. In step 806 the second pulse train, in this particular embodiment being identical with the first pulse train, is received from the micro controller 121. In step 807 the reference voltage VREF is generated by the frequency-to- voltage converter 202. In step 808 the portion VDIV of the second DC-voltage V2 is compared with the reference voltage VREF generated in step 807 and in step 809 the result of this comparison is used when generating the first DC-voltage VI. These method steps 804-809 are carried out repeatedly in the regulating means 101. The invention can be varied in a number of different ways. The converting means 101 can be implemented in several other ways than those disclosed in Fig. 4 and Fig. 5. In all these different embodiments of the converting means 101 the converting means 101 is arranged such that the generated second DC-voltage V2 depends on both the first DC-voltage VI and at least one characteristic of the first pulse train PTl and that the second DC-voltage V2 is a monotonic function of the first DC-voltage VI. Fig. 7 provides an example of a monotonic function MF1, i.e. the function never decreases or never increases as the independent variable increases. In this particular example V2 is an increasing function of VI. More precisely V2 is a linear function of VI having a positive derivative. In the capacitor based charge pump 400 of Fig. 4, the generated second DC-voltage V2 depends on both the frequency and amplitude of the first pulse train PTl. In the coil based charge pump 500 of Fig. 5, the generated second DC- voltage depends on both the frequency and duty cycle of the first pulse train PTl. In both charge pumps 400, 500, the generated second DC-voltage V2 , when considered as a function of the first DC-voltage VI, increases as the received first DC-voltage VI is increased. For both charge pumps 400, 500 the second DC-voltage V2 expressed as a function of the first DC-voltage VI is approximately a linear function having a positive derivative. Thus the function MF1 in Fig. 7 can serve as an illustration of how the second DC-voltage V2 depends on the first DC-voltage VI for both the capacitor based charge pump 400 and the coil based charge pump 500. The regulating means 102 can also be implemented in several different ways. For some of these embodiments, the internal structure of the regulating means 102 corresponds to that of Fig. 2, while other embodiments do not necessarily need to have an internal structure corresponding to that of Fig. 2. The differential amplifier 201 in Fig. 2 can be implemented in different ways. The differential amplifier 201 must be able to supply sufficient power to the converting means 101. If the amplifier 201 is implemented as an integrated circuit it may be necessary to add a discrete transistor output stage to handle the heat dissipation. The power dissipation in the differential amplifier 201 is kept to a minimum by chosing an appropriate working point for the differential amplifier 201. This is achieved by selecting an appropriate reference voltage level VREF and selecting the two resistors 203 and 204 so that a matching voltage division of V2 is achieved. Instead of a differential amplifier controlling the first DC-voltage emitted by the regulating means, a comparator could be used for the same purpose. The frequency-to-voltage converter 202 in Fig. 2 can be implemented in other ways apart from that shown in Fig. 3. Instead of generating the reference voltage by means of a frequency-to-voltage converter, some other kind of reference voltage generating means can be used. In all different embodiments of the reference voltage generating means the generated reference voltage depends on at least one characteristic, e.g. the frequency or duty cycle, of the second pulse train received by the regulating means . Even though Fig. 6A and Fig. 6B only discloses rectangular pulses the invention is not limited to only be used in connection with pulse trains having rectangular pulses. However, a pulse train with rectangular pulses is very easy to generate and if the converting means is implemented according to Fig. 5 it is preferred to have very sharp pulse edges since this enables the transistor, acting as a switch, to work efficiently. It is also not a necessary requirement that the first pulse train, received by the converting means, and the second pulse train, received by the regulating means, are identical. However it is easier to only provide one pulse train.

Claims: CLAIMS 1. A DC-to-DC converter (100) comprising: converting means (101) , having a first input terminal (103) for receiving a first DC-voltage (VI) and an output terminal (105) on which the converting means emits a second DC- voltage (V2) ; regulating means (102) having a first input terminal (106) for receiving a supply voltage (VS) from a DC-power source (107) , a second input terminal (108) connected to the output terminal (105) of the converting means (101) , an output terminal (110) connected to the first input terminal (103) of the converting means (101) , the regulating means (102) emitting said first DC-voltage (VI) determined in the regulating means (102) by a comparision of a portion (VDIV) of the second DC-voltage (V2) with a reference voltage (VREF) whereby said first DC- voltage (VI) is generated such that the portion (VDIV) of the second DC-voltage (V2) is forced towards the reference voltage (VREF) level c h a r a c t e r i z e d by the converting means (101) having a second input terminal (104) for receiving a first pulse train (PTl) , the converting means (101) being arranged such that the generated second DC-voltage (V2) depends on both the first DC-voltage (VI) and at least one characteristic (FI, DCl) of the first pulse train (PTl) and that the second DC-voltage (V2) is a monotonic function (MF1) of the first DC-voltage (VI) ; the regulating means (102) having a third input terminal (109) for receiving a second pulse train (PTl) and the regulating means (102) comprising reference voltage generating means (202) being arranged to generate the reference voltage (VREF) depending on at least one characteristic (FI, DCl) of the second pulse train (PTl) . 2. A DC-to-DC converter (100) according to claim 1 c h a r a c t e r i z e d by the DC-to-DC converter (100) being arranged such that said second pulse train is essentially identical with said first pulse train (PTl) . 3. A DC-to-DC converter (100) according to claim 1 or 2 c h a r a c t e r i z e d by said converting means (101) being arranged such that said at least one characteristic of the first pulse train (PTl) on which said generated second DC-voltage (V2) depends is the frequency (FI) . 4. A DC-to-DC converter (100) according to claim 1 or 2 c h a r a c t e r i z e d by said converting means (101) being arranged such that said at least one characteristic of the first pulse train (PTl) on which said generated second DC-voltage (V2) depends is the duty cycle (DCl) . 5. A DC-to-DC converter (100) according to any of the claims 1-4 c h a r a c t e r i z e d by said reference voltage generating means (202) being arranged such that said at least one characteristic of the second pulse train (PTl) on which said generated reference voltage (VREF) depends is the frequency (FI) . 6. A DC-to-DC converter (100) according to any of the claims 1-4 c h a r a c t e r i z e d by said reference voltage generating means (202) being arranged such that said at least one characteristic of the second pulse train (PTl) on which said generated reference voltage (VREF) depends is the duty cycle (DCl) . 7. A DC-to-DC converter (100) according to any of the claims 1-6 c h a r a c t e r i z e d by the DC-to-DC converter (100) being arranged such that said second DC-voltage (V2) has an absolute value greater than the absolute value of said supply voltage (VS) . 8. A DC-to-DC converter (100) according to any of the claims 1-3 c h a r a c t e r i z e d by said converting means (101) comprising a capacitor based charge pump (400) . 9. A DC-to-DC converter (100) according to any of the claims 1-4 c h a r a c t e r i z e d by said converting means (101) comprising a coil based charge pump (500) . 10. A DC-to-DC converter (100) according to any of the claims l- 5 c h a r a c t e r i z e d by said regulating means ( 102 ) comprising : a differential amplifier (201) having an .output terminal (205) , an inverting input terminal (206) and a non-inverting input terminal (207) , the output terminal (205) of the differential amplifier (201) being connected to the output terminal (110) of the regulating means (102) ; a frequency-to-voltage converter (202) as said reference voltage generating means, having an input terminal (208) and an output terminal (209) , the input terminal (208) of the frequency-to-voltage converter (202) being connected to the third input terminal (109) of the regulating means (102) and the frequency-to-voltage converter (202) on its output terminal (209) , connected to the non-inverting input terminal (207) of the differential amplifier (201) , emitting said reference voltage (VREF) ; two resistors (203, 204) connected in series, the resistors (203, 204) being connected between said second input terminal (1 . 08) of the regulating means (102) and a predetermined potential (GND) , a point between the two resistors being connected to the inverting input terminal (206) of the differential amplifier (201) and the resistors (203, 204) thus determining said portion (VDIV) of said second DC-voltage (V2) . 11. A method for controlling a second DC-voltage (V2) emitted by a DC-to-DC converter (100) , the DC-to-DC converter (100) comprising converting means (101) and regulating means (102), said method comprising the steps of: a) receiving (801) in the converting means (101) a first pulse train (PTl) ; b) receiving (802) in the converting means (101) a first DC-voltage (VI) ; c) generating (803) the second DC-voltage (V2) in the converting means (101) such that the second DC-voltage (V2) depends on both the first DC-voltage (VI) and at least one characteristic (FI, DCl) of the first pulse train (PTl) and that the second DC-voltage (V2) is a monotonic function (MF1) of the first DC-voltage (VI) ; d) receiving (804) in the regulating means (102) a supply voltage (VS) from a DC-power source (107) ; e) receiving (805) in the regulating means (102) the second DC-voltage (V2) ; f) receiving (806) in the regulating means (102) a second pulse train (PTl) ; g) generating (807) in the regulating means (102) a reference voltage (VREF) such that the reference voltage (VREF) is depending on at least one characteristic (FI, DCl) of the second pulse train (PTl) ; h) comparing (808) in the regulating means (102) a portion (VDIV) of the second voltage (V2) with the reference voltage (VREF) ; i) generating (809) the first DC-voltage (VI) in the regulating means (102) based on the comparision in step h) such that the portion (VDIV) of the second DC-voltage (V2) is forced towards the reference voltage (VREF) level . 12. A method according to claim 11 c h a r a c t e r i z e d by that said second pulse train (PTl) is essentially identical with said first pulse train (PTl) . 13. A method according to claim 11 or 12 c h a r a c t e r i z e d by that said at least one characteristic of the first pulse train (PTl) on which said generated second DC-voltage (V2) depends is the frequency (FI) . 14. A method according to claim 11 or 12 c h a r a c t e r i z e d by that said at least one characteristic of the first pulse train (PTl) on which said generated second DC-voltage (V2) depends is the duty cycle (DCl) . 15. A method according to any of the claims 11-14 c h a r a c t e r i z e d by that said at least one characteristic of the second pulse train (PTl) on which said generated reference voltage (VREF) depends is the frequency (FI) . 16. A method according to any of the claims 11-14 c h a r a c t e r i z e d by that said at least one characteristic of the second pulse train (PTl) on which said generated reference voltage (VREF) depends is the duty cycle (DCl) . 17. A method according to any of the claims 11-16 c h a r a c t e r i z e d by that said second DC-voltage (V2) is generated in step c) such that it has an absolute value greater than the absolute value of said supply voltage (VS) .

Inventors: BJOERKENGREN ULF, BJOERKENGREN, ULF
Applicants: ERICSSON TELEFON AB L M, TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
Application year: 1998
Main classification: H02M3
IPC codes: G05F1, H02M3