Circuit and method for arbitrarily shifting M-sequence

Abstract: A circuit, which shifts an M-sequence code with an arbitrary number of bits, is realized by a small circuit scale. D-type flip-flops 1-6 form a shift register for generating an M-sequence and having outputs d 0 -d 5 of respective stages, to which 2 5 bit shift inserting circuit 10 is connected in the manner of receiving the outputs d 0 -d 5 as respective inputs and of outputting outputs O 0 -O 5 , to which 2 4 bit shift inserting circuit 11 is connected in the manner of receiving the outputs O 0 -O 5 as respective inputs. In the same manner, a 2 3 bit shift inserting circuit 12, a 2 2 bit shift inserting circuit 13, a 2 1 bit shift inserting circuit 14, and a 2 0 bit shift inserting circuit 15 are sequentially connected with one another. Each of bit shift inserting circuits 10-15 respectively shifts a predetermined bit when control signals b 5 -b 0 are "1", and does not shift a bit when "0" so as to output an input as it is. Therefore, it is possible to obtain an arbitrary bit shift.

Description: The present invention relates to a circuit for generating an M-sequence code (Maximum Length Code) which is used as a spread code such in a frequency spread communication (Spread Spectrum Communication), and particularly to the circuit for shifting the M-sequence code with an arbitrary bit. An M-sequence is a kind of PN (Pseudorandom Noise), which can be easily generated by a shift register comprising D-type flip-flops 1-6 having a feedback circuit using an exclusive OR circuit 7 as shown in Fig. 9, for example. Accordingly, the M-sequence code is often used as a spread code in a spread spectrum communication. In the spread spectrum communication, it is necessary for a reception side to generate an inverse spread code which synchronizes and coincides with the spread code, so that it is necessary to have a synchronization by arbitrarily shifting the M-sequence which is used in spreading. There has been known a conventional circuit disclosed in JP-A-8-181679 (1996), which is one of conventional methods for arbitrarily shifting the M-sequence. The conventional technology is shown in Fig. 10. In Fig. 10, entire data of the M-sequence or PN-sequence are stored in a ROM look-up table 54. An address added to the ROM 54 includes a value of which an N-bit binary counter 53 counts a system clock signal 56, and a value of which an adder 52 adds an offset signal 55 which is held in a register 51 based on an external designation. Since the address increases one by one at every one count of the clock signal 56 by the counter 53, the ROM 54 outputs in the order a PN-sequence 57 stored therein. Further, the offset signal 55 is written in the register 51 to increase the address with its amount so as to output a shift output signal as the PN-sequence 57, thereby enabling to arbitrarily shift the PN-sequence. By the way, in the conventional example described above, it is necessary to store entire of the M-sequence or PN-sequence in the ROM, and it is no problem if a stage number of the M-sequence is small. However, in the case of the M-sequence having 42 stages such in Fig. 11, for example, a cycle is 2 42 -1 bit which corresponds to about 4000 Gbit. There has not been a ROM for holding such large data, which is impractical idea at the present time. Further, Fig. 11 is a circuit diagram showing a circuit for generating a long code as a kind of a spread code, which is used in the IS95 system of CDMA (Code Division Multiple Access) in U.S.A. The circuit uses an M-sequence of a forty-second stage, and comprises registers 601-642, adders 643-648, AND gate circuits 649-690, a modulo 2 adder 691, thereby obtaining a long code 693 of which a bit is random shifted corresponding to a value of a mask code 692 which is inputted in the AND gate circuits 649-690. The mask code 692 is used as a cipher key, and it is necessary that mask codes are the same as each other in the transmission side and the reception side. Accordingly, there has been no original purpose to shift the M-sequence with an arbitrary number of bits by using the mask code. Therefore, it is necessary that a mask code corresponding to a shift amount thereof is previously obtained and stored for shifting the M-sequence. Accordingly, it is difficult to instantaneously shift it with an arbitrary number of bits. In US-A-5 532 695, a PN sequence generator is provided wherein a mask value and a comparison value are calculated for shifting the PN sequence output having a length of 2 N as much as wanted, so that the PN sequence can be shifted as much as a predetermined value in response to a single clock signal. The objective of the present invention is to solve the above-mentioned tasks. Moreover, the objective of the invention is to provide a technology for arbitrarily shifting an M-sequence, the circuit capable of generating the M-sequence, which is shifted with an arbitrary number of bits by a smalls circuit scale. The objective of the present invention its achieved with the features of the claims. This and other objects, features and advantages of the present invention will become more apparent upon a reading of the following detailed description and drawings, in which: Fig. 1 is a block diagram showing a circuit for arbitrarily shifting an M-sequence according to an embodiment of the present invention; Fig. 2 is a block diagram showing the 2 5 bit shift inserting circuit 10, the 2 4 bit shift inserting circuit 11, the 2 3 bit shift inserting circuit 12, the 2 2 bit shift inserting circuit 13, the 2 1 bit shift inserting circuit 14, and the 2 0 bit shift inserting circuit 15; Fig. 3 is a block diagram showing the 2 0 bit shift circuit; Fig. 4 is a block diagram showing the 2 1 bit shift inserting circuit; Fig. 5 is a block diagram showing the 2 2 bit shift circuit; Fig. 6 is a block diagram showing the 2 3 bit shift inserting circuit; Fig. 7 is a block diagram showing the 2 4 bit shift circuit; Fig. 8 is a block diagram showing the 2 5 bit shift inserting circuit; Fig. 9 is a block diagram showing an example of six stage PN generating circuit; Fig. 10 is a block diagram showing the first conventional example; and Fig. 11 is a block diagram showing the second conventional example. There will be described an embodiment according to the present invention. There will be described first a principle of a bit shift of an M-sequence by using Fig. 1. Even though the register shown in Fig. 1 has six stages, the principles are the same as that having stages more than six. It is assumed that each stage of in the register (which is constructed from D-type flip-flops 1-6) shown in Fig. 1, has values d0-d5 as shown in the figure. Values after one bit can be obtained by the present values d0-d5 according to the following equation (1). where a product of the matrix operation is a logical product, a sum of the matrix operation is a logical sum, a suffix of "n" of a vector denotes a presence, and a suffix of "n+k" of a vector denotes a condition after shifted by k bits. When the above-described matrix and vector are simplified, they can be represented by the equation as follows: If the condition can be represented as above-described equation, values after shifted with k bits can be represented by the following equation: d n + k = A k o d n A " k " can be represented by a power of two as follows: Accordingly, the following equation can be obtained as a conclusion: Accordingly, on the basis of a matrix A which shifts the values of the registrer with one bit, a matrix of two to several power of the matrix A is previously obtained, and the obtained matrix is caused to be respectively operated with the original vector corresponding to a binary number representation bi of a value of k , thereby introducing the values of the register after shifted with k bit. According to the above-described contents, the present invention can obtain an output shifted by k bits, in the manner of obtaining a product of two to several power of the matrix A , and of providing a shift circuit corresponding to an operation of the product, the shift circuit which operates the above operation when the binary number representation bi of k is "1", and operates by bypassing the above operation to d0-d5 when the representation bi is "0". This is the basis of the present invention. The followings are showing the calculation of two to several power products of the matrix A in the M-sequence having six stages. In the case of a large number of stages, the calculation method is the same as that of the six stages. That is, the matrix of A to 2 0 (two to zero power) power is a matrix that an M-sequence of six stages (six bits) is caused to be shifted with one bit. Further, the matrix of A to 2 1 (two to the first power) power is a matrix that an M-sequence of six stages (six bits) is caused to be shifted with two bits. Further, the matrix of A to 2 2 (two to the second power) power is a matrix that an M-sequence of six stages (six bits) is caused to be shifted with four bits. Further, the matrix of A to 2 3 (two to the third power) power is a matrix that an M-sequence of six stages (six bits) is caused to be shifted with eight bits. Further, the matrix of A to 2 4 (two to the fourth power) power is a matrix that an M-sequence of six stages (six bits) is caused to be shifted with sixteen bits. Further, the matrix of A to 2 5 (two to the fifth power) power is a matrix that an M-sequence of six stages (six bits) is caused to be shifted with thirty-two bits. It is possible to arbitrarily shift an M-sequence by means of a combination of these matrices (or determinants). For example, it will be supposed that an M-sequence of six stages (six bits) is caused to be shifted with five bits. In the case of shifting the M-sequence with five bits, it is sufficient that one bit is shifted first, and then four bits are shifted. Accordingly, if the matrix of A to 2 0 power and the matrix A to 2 2 power are multiplied in the order to the M-sequence, it is possible to obtain an M-sequence in which five bits are shifted. Next, there will be described in detail a shift circuit according to the preferred embodiment of the present invention with reference to the attached drawings. Fig. 1 is a block diagram showing a configuration of a circuit for arbitrarily shifting an M-sequence according to one embodiment of the present invention. The circuit of this embodiment comprises a plurality of D-type flip-flops 1-6 constituting a shift register for generating an M-sequence, an exclusive OR gate 7, a 2 5 (two to the fifth power) bit shift inserting circuit 10 for inputting a plurality of outputs d 0 , d 1 , d 2 , d 3 , d 4 and d 5 which are outputted from the D-type flip-flops 6, 5, 4, 3, 2, 1, respectively, a 2 4 (two to the fourth power) bit shift inserting circuit 11 for inputting an output of the 2 5 bit shift inserting circuit 10, a 2 3 (two to the third power) bit shift inserting circuit 12 for inputting an output of the 2 4 bit shift inserting circuit 11, a 2 2 (two to the second power) bit shift inserting circuit 13 for inputting an output of the 2 3 bit shift inserting circuit 12, a 2 1 (two to the first power) bit shift inserting circuit 14 for inputting an output of the 2 2 bit shift inserting circuit 13, and a 2 0 (two to the zero power) bit shift inserting circuit 15 for inputting an output of the 2 1 bit shift inserting circuit 14. Respective bit shift inserting circuits 10-15 perform a predetermined bit shift when control signal b 5 -b 0 are "1", and do not perform the bit shift when the signals are "0" to output an input as it is. By this, it is possible to obtain a shift of the bit as follows: Here, there will be described a control signal. The control signal is outputted from a control circuit 100. When the control circuit 100 receives an order for shifting with k bit(s), k is rewritten by a binary scale representation of six figures. For example, there is 000101 when k is five, and there is 100000 when k is 32, respectively. A number of the first figure is outputted by a control signal b 0 , a number of the second figure is outputted by a control signal b 1 , a number of the third figure is outputted by a control signal b 2 , a number of the fourth figure is outputted by a control signal b 3 , a number of the fifth figure is outputted by a control signal b 4 , and a number of the sixth figure is outputted by a control signal b 5 , respectively. For example, when five bits are shifted, there is 000101 when five is represented by a binary scale. Accordingly, the control signal b 0 is "1", the control signal b 1 is "0", the control signal b 2 is "1", the control signal b 3 is "0", the control signal b 4 is "0", and the control signal b 5 is "0", respectively. The bit shift inserting circuits 10-15 have the above-described operation when each of control signals is inputted. In this case, the control signal b 5 =0 is inputted into a 2 5 bit shift inserting circuit 10, the control signal b 4 =0 is inputted into a 2 4 bit shift inserting circuit 11, the control signal b 3 =0 is inputted into a 2 3 bit shift inserting circuit 12, the control signal b 2 =1 is inputted into a 2 2 bit shift inserting circuit 13, the control signal b 1 =0 is inputted into a 2 1 bit shift inserting circuit 14, and the control signal b 0 =1 is inputted into a 2 0 bit shift inserting circuit 15, respectively. The 2 5 -bit shift inserting circuit 10 does not shift a bit by the control signal, and outputs the input as it is. The 2 4 -bit shift inserting circuit 11 does not shift a bit in the output of the 2 5 -bit shift inserting circuit 10 by the control signal, and outputs the input as it is. The 2 3 -bit shift inserting circuit 12 does not shift a bit in the output of 2 4 -bit shift inserting circuit 11 by the control signal, and outputs the input as it is. The 2 2 -bit shift inserting circuit 13 outputs after shifting the output of the 2 3 -bit shift inserting circuit 12 with four bits by the control signal. The 2 1 -bit shift inserting circuit 14 does not shift a bit in the output of the 2 2 -bit shift inserting circuit 13 by the control signal, and outputs the input as it is. The 2 0 -bit shift inserting circuit 15 outputs after shifting the output of the 2 1 -bit shift inserting circuit 14 with one bit by the control signal. Accordingly, a bit string outputted from the 2 0 -bit shift inserting circuit 15 is that the M-sequence outputted from the shift register has been shifted with five bits. Fig. 2 is a block diagram showing each of the 2 3 -2 0 bit shift inserting circuits 10-15 shown in FIG. 1 Each of the 2 n bit shift inserting circuits (n=5, 4, ···, and 0,) 10-15 comprises input terminals I 0 , I 1 , I 2 , I 3 , I 4 , I 5 , and CNT, a 2 n bit shift inserting circuit 21 for performing a predetermined bit shift with respect to a plurality of inputs A 0 -A 5 of the input terminals I 0 -I 5 so as to output a plurality of outputs B 0 -B 5 , and a data selector 22 for outputting the outputs B 0 -B 5 when the input terminal CNT has a control signal being "1" and for alternatively outputting the inputs A 0 -A 5 of the input terminals I 0 -I 5 when the control signal b is "0", respectively from output terminals O 0 -O 5 . Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7 and Fig. 8 are block diagram respectively showing the 2 0 bit shift circuit, the 2 1 bit shift circuit, the 2 2 bit shift circuit, the 2 3 bit shift circuit, the 2 4 bit shift circuit, and the 2 5 bit shift circuit. The 2 0 bit shift circuit has an exclusive OR circuit 31 for taking an exclusive OR of the input A 0 of the input terminal I 0 the input A 3 of the input terminal I 3 . The 2 0 bit sift circuit outputs the inputs A 1 , A 2 , A 4 and A 5 of the input terminals I 1 , I 2 , I 3 , I 4 and I 5 respectively to the output terminals O 0 , O 1 , O 2 , O 3, and O 4 , and outputs the output of the exclusive OR circuit 31 to the output terminal O 5 . The 2 1 bit shift circuit has an exclusive OR circuit 32 for taking anexclusive OR of the input A 0 of the input terminal I 0 and the input A 3 of the input terminal I 3 , and an exclusive OR circuit 33 for taking an exclusive OR of the input A 1 of the input terminal I 1 and the input A 4 of the input terminal I 4 . The 2 1 bit sift circuit outputs the inputs A 2 , A 3 , A 4 and A 5 of the input terminals I 2 , I 3 , I 4 and. I 5 , respectively to the output terminals O 0 , O 1 , O 2 , and O 3 , and outputs the outputs of the exclusive OR circuits 32 and 33 to the output terminals O 4 and O 5 . The 2 2 bit shift circuit has an exclusive OR circuit 34 for taking an exclusive OR of the input A 0 of the input terminal I 0 and the input A 3 of the input terminal I 3 , an exclusive OR circuit 35 for taking an exclusive OR of the input A 1 of the input terminal I 1 and the input A 4 of the input terminal I 4 , and an exclusive OR circuit 36 for taking an exclusive OR of the input A 2 of the input terminal I 2 and the input A 5 of the input terminal I 5 . The 2 2 bit sift circuit outputs the inputs A 4 , A 5 , and A 0 of the input terminals I 4 , I 5 and I 0 , respectively to the output terminals O 0 , O 1 and O 5 , and outputs the outputs of the exclusive OR circuits 34, 35 and 36 to the output terminals O 2 , O 3 and O 4 . The 2 3 bit shift circuit has an exclusive OR circuit 37 for taking an exclusive OR of the input A 2 of the input terminal I 2 and the input A 5 of the input terminal I 5 . The 2 3 bit sift circuit outputs an output of the exclusive OR circuit 37 and the inputs A 0 , A 1 , A 2 , A 3 and A 4 of the input terminals I 0 , I 1 , I 2 , I 3 and I 4 respectively to the output terminals O 0 , O 1 , O 2 , O 3 , O 4 and O 5 . The 2 4 bit shift circuit has an exclusive OR circuit 38 for taking an exclusive OR of the input A 1 of the input terminal I 1 and the input A 4 of the input terminal I 4 , an exclusive OR circuit 39 for taking an exclusive OR of the input A 2 of the input terminal I 2 and the input A 5 of the input terminal I 5 . The 2 4 bit sift circuit outputs each of outputs from the exclusive OR circuits 38 and 39 and the inputs A 0 , A 1 , A 2 , and A 3 of the input terminals I 0 , I 1 , I 2 and I 3 respectively to the output terminals O 0 , O 1 , O 2 , O 3 , O 4 and O 5 . The 2 5 bit shift circuit has an exclusive OR circuit 40 for taking an exclusive OR of the input A 0 of the input terminal I 0 and the input A 3 of the input terminal I 3 , an exclusive OR circuit 41 for taking an exclusive OR of the input A 1 of the input terminal I 1 and the input A 4 of the input terminal I 4 , and an exclusive OR circuit 42 for taking an exclusive OR of the input A 2 of the input terminal I 2 and the input A 5 of the input terminal I 5 . The 2 5 bit sift circuit outputs the inputs A 5 , each of outputs of the exclusive OR circuits 40, 41 and 42, the input A 0 of the input terminal I 0 , and the input A 1 of the input terminal I 1 , respectively to the output terminals O 0 , O 1 , O 2 , O 3 , O 4 and O 5 . The above-described constitution can easily configured from each value of the power in the matrix A as has been described above. Even though the six-stage M-sequence has been described above, it is clear that the present invention can apply to another M-sequence having a plurality number of stages more than six stages. As has been described above, since the present invention can realize a small circuit scale of the circuit that shifts the M-sequence with an arbitrary bit, it is possible to miniaturize the unit, to decrease an electric power consumption, and to reduce a cost.

Claims: A circuit for generating an M-sequence (maximum length sequence) with arbitrary shifts, comprising: a shift register (1 to 6) having N stages for generating the M-sequence; characterized by a plurality of two to several power bit shift inserting circuits (10 to 15) which are connected in series between the output of each stage of said shift register and a final N bit output. The circuit as set forth in claim 1, wherein said two to several power bit shift inserting circuit (10 to 15) comprises two to several power bit shifting circuit (21) for shifting an input signal of N-bit (I 0 to I 5 ) with two to several power bits so as to output an output signal of N-bit (O 0 to O 5 ), and a data selector (22) for changing between said input signal of N-bit and said output signal of N-bit corresponding to a control signal supplied from an outside, so as to output an output signal of N-bit thereof. The circuit as set forth in claim 1, wherein said two to several power bit shift inserting circuit (10 to 15) is adapted to provide a value equal to two to the power of an integer from 0 to N-1. The circuit as set forth in claim 1, further comprising control means (100) for outputting as a control signal, in a case of shifting said M-sequence of N-bit with k bit or bits, a binary number which is converted from said k into a binary number representation, and wherein each of said two to several power bit shift inserting circuits (10 to 15) is adapted to provide a value equal to two to the power of an integer from 0 to N-1, and wherein each of said two to several power bit shift inserting circuits (10 to 15) is adapted to input an input signal corresponding to said binary number representation of said control signal and to shift said M-sequence of N-bit with a value of two to the power of an integer when said binary number representation of said control signal is 1, and to output said M-sequence of N-bit, as it is, when said binary number representation of said control signal is 0. The circuit as set forth in claim 4, wherein said two to several power bit shift inserting circuit (10 to 15) comprises: a two to several power bit shifting circuit for shifting said M-sequence of N-bit with two to several power bits; and a data selector for changing between said M-sequence of N-bit and an output signal of N-bit which is outputted from said two to several power bit shifting circuit corresponding to said control signal. A method for generating an M-sequence (maximum length sequence) by using a shift register having N-stages and for shifting said sequence by k bits, said method comprises: a step of decomposing the value k into a binary number representation with weights two to the power of zero, two to the power of one, ..., two to the power of N-1; a step of selecting a combination of shifting means connected in series to the outputs of said N-stages, said shifting means being adapted to implement shifts of two to the power of zero, two to the power of one, ..., two to the power of N-1, respectively, the selection being made according to the bits of said binary number representation; a step of sequentially shifting the N bits at said outputs by using the selected shifting means in sequence.

Inventors: ICHIHARA MASAKI, ICHIHARA, MASAKI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1998
Main classification: H04J13
IPC codes: H03K3, H04J13