High data rate spread spectrum transceiver and associated methods

Abstract: A spread spectrum radio transceiver includes a high data rate baseband processor and a interconnected radio circuit. The baseband processor includes a modulator for spread spectrum phase shift keying (PSK) modulating information for transmission via the radio circuit. The modulator includes at least one modified Walsh code function encoder for encoding information according to a modified Walsh code for substantially reducing an average DC signal component to enhance overall system performance when AC-coupling the received signal through at least one analog-to-digital converter to the demodulator. The demodulator is for spread spectrum PSK demodulating information received from the radio circuit. The modulator and demodulator are each operable in one of a bi-phase PSK (BPSK) mode at a first data rate and a quadrature PSK (QPSK) mode at a second data rate.

Description: The invention relates to the field of communication electronics, and, in particular, to a spread spectrum transceiver and associated methods. Wireless or radio communication between separated electronic devices is widely used. For example, a wireless local area network (WLAN) is a flexible data communication system that may be an extension to, or an alternative for, a wired LAN within a building or campus. A WLAN uses radio technology to transmit and receive data over the air, thereby reducing or minimizing the need for wired connections. Accordingly, a WLAN combines data connectivity with user mobility, and, through simplified configurations, also permits a movable LAN. Over the past several years, WLANs have gained acceptance among a number users including, for example, health-care, retail, manufacturing, warehousing, and academic areas. These groups have benefited from the productivity gains of using hand-held terminals and notebook computers, for example, to transmit real-time information to centralized hosts for processing. Today WLANs are becoming more widely recognized and used as a general purpose connectivity alternative for an even broader range of users. In addition, a WLAN provides installation flexibility and permits a computer network to be used in situations where wireline technology is not practical. In a typical WLAN, an access point provided by a transceiver, that is, a combination transmitter and receiver, connects to the wired network from a fixed location. Accordingly, the access transceiver receives, buffers, and transmits data between the WLAN and the wired network. A single access transceiver can support a small group of collocated users within a range of less than about one hundred to several hundred feet. The end users connect to the WLAN through transceivers which are typically implemented as PC cards in a notebook computer, or ISA or PCI cards for desktop computers. Of course the transceiver may be integrated with any device, such as a hand-held computer. Harris Corporation has developed and manufactured a set of integrated circuits for a WLAN under the mark PRISM 1 which is compatible with the proposed IEEE 802.11 standard. The architecture and circuit details are disclosed in Rf Design, Cardiff Publishing Co. Englewood, co, US (01-10-1995), 18 (10), 42, 45-51 and also in EP-A-0757449. The PRISM 1 chip set provides all the functions necessary for full or half duplex, direct sequence spread spectrum, packet communications at the 2.4 to 2.5 GHz ISM radio band. In particular, that known in the trade as the HSP3824 baseband processor manufactured by Harris Corporation employs quadrature or bi-phase phase shift keying (QPSK or BPSK) modulation schemes. While the PRISM 1 chip set is operable at 2 Mbit/s for BPSK and 4 Mbit/s for QPSK, these data rates may not be sufficient for higher data rate applications. Spread spectrum communications have been used for various applications, such as cellular telephone communications, to provide robustness to jamming, good interference and multi-path rejection, and inherently secure communications from eaves-droppers, as disclosed in the specifications of U.S. Patent No. 5,515,396 which discloses a code division multiple access (CDMA) cellular communication system using four Walsh spreading codes to allow transmission of a higher information rate without a substantial duplication of transmitter hardware. The specifications of U.S. Patent No.'s. 5,535,239; 5,416,797; 5,309,474; and 5,103,459 also disclose a CDMA spread spectrum cellular telephone communications system using Walsh function spreading codes. WO-A-9632784 discloses a spread spectrum communication system. This system uses an orthogonal code for reducing an average DC signal component. From EP-A-0757451 a baseband processor is known which is suitable for receiving packet data having a header and data comprising a carrier tracking loop for the header format and a second carrier tracking loop for the data format. An object of the present invention is to provide a spread spectrum transceiver and associated method permitting operation at higher data rates than conventional transceivers with an improved carrier tracking which may switch on-the-fly between different data rates and/or formats. The present invention includes a spread spectrum radio transceiver comprising: a baseband processor and a radio circuit connected thereto, said baseband processor comprising a demodulator for spread spectrum phase shift keying (PSK) demodulating information received from said radio circuit, at least one analog-to-digital (A/D) converter having an output connected to said demodulator and an input AC-coupled to said radio circuit, said demodulator comprising at least one predetermined orthogonal code function correlator for decoding information according to the predetermined orthogonal code, a modulator for spread spectrum PSK modulating information for transmission via the radio circuit, said modulator comprising at least the predetermined orthogonal code function encoder for encoding information according to the predetermined orthogonal code in which said modulator comprises means for operating in one of first format defined by bi-phase PSK (BPSK) modulation at a first data rate and a second format defined by quadrature PSK (QPSK) modulation at a second data rate; said modulator (50) comprises means for modulating data packets to include a header at a third format defined by a predetermined modulation at a third data rate and variable data operating in one of the first and second formats with the predetermined modulation of the third format being differential BPSK (DBPSK), and the third data rate is lower than the first and second data rates, said means for modulating data packets reducing average DC signal component, and that said demodulator (60) comprises header modulator means for demodulating data packets by demodulating the header at the third format and for switching two the respective one of the first and second formats of the variable data after the header, with said demodulator (60) further comprising a first carrier tracking loop (72,75) for the third format, and a second carrier tracking loop (61,62,63,76) for the first and second formats, said demodulator means providing reduced average DC signal component which in combination with the AC - coupling to said at least one A/D converter enhances overall performance. The invention further includes a method for baseband processing for spread spectrum radio communication, the method comprises the steps of: spread spectrum phase shift keying (PSK) modulating information for transmission by encoding information according to a predetermined orthogonal code for reducing an average DC signal component; spread spectrum PSK demodulating received information by decoding the information according to the predetermined orthogonal code, including the step of AC-coupling and A/D-converting received information for spread spectrum PSK demodulating so that the reduced average DC signal component in combination with the AC-coupling enhances overall performance. Further developments of the invention are subject of depending claims. The present invention will now be described, by way of example, with reference to the accompanying drawings in which: FIG. 1 is a schematic circuit diagram of a transceiver; FIG. 2 is a schematic circuit diagram of a modulator portion of the high data rate baseband processor; FIG. 3 is a timing diagram of signals generated by the present invention; FIG. 4 is a timing diagram of additional signals generated by the present invention; FIG. 5 is a schematic circuit diagram of a demodulator portion of the high data rate baseband processor; FIG. 6 is a schematic circuit diagram of the correlator portion of the demodulator of the high data rate baseband processor; FIG. 7 is a schematic circuit diagram of additional portions of the demodulator of the high data rate baseband processor; FIG. 8 is a schematic circuit diagram of further portions of the demodulator of the high data rate baseband processor; Like numbers refer to like elements throughout. Referring to FIG. 1, a wireless transceiver 30 may be readily used for WLAN applications in the 2.4 GHz ISM band in accordance with the proposed IEEE 802.11 standard. The transceiver 30 includes the selectable antennas 31 coupled to the radio power amplifier and TX/RX switch 32 as may be provided by a Harris part number HFA 3925. Multiple antennas may be provided for space diversity reception. A low noise amplifier 38, as may be provided by Harris Corporation U.S.A. part number HFA3424, is also operatively connected to the antennas. The illustrated up/down converter 33 is connected to both the low noise amplifier 38 and the RF power amplifier and TX/RX switch 32 as would be readily understood by those skilled in the art. The up/down converter 33 is provided by a Harris part number HFA3624. The up/down converter 33 , in turn, is connected to the illustrated dual frequency synthesizer 34 and the quad IF modulator/demodulator 35 . The dual synthesizer 34 may be a Harris part number HFA3524 and the quad IF modulator 35 may be a Harris part number HFA3724. The up/down converter 33 , in turn, is connected to the illustrated dual frequency synthesizer 34 and the quad IF modulator/demodulator 35 . The dual synthesizer 34 may be a part number HFA3524 and the quad IF modulator 35 may be a part number HFA3724. All the components described so far are included in a 2.4 GHz direct sequence spread spectrum wireless transceiver chip set manufactured by Harris Corporation under the designation PRISM 1. Various filters 36 , and the illustrated voltage controlled oscillators 37 may also be provided as would be readily understood by those skilled in the art and as further described in the Harris Corporation PRISM 1 chip set literature. The right hand side of FIG. 1 depicts the high data rate direct sequence spread spectrum (DSS) baseband processor 40 . The conventional Harris PRISM 1 chip set includes a low data rate DSS baseband processor available under the designation HSP3824. This prior baseband processor is described in detail in a publication entitled "Direct Sequence Spread Spectrum Baseband Processor, March 1996, file number 4064.4 of Harris Corporation, U.S.A. Like the HSP3824 baseband processor, the high data rate baseband processor 40 of the invention contains all of the functions necessary for a full or half duplex packet baseband transceiver. The processor 40 has on-board dual 3-bit A/D converters 41 for receiving the receive I and Q signals from the quad IF modulator 35 . Also like the HSP3824, the high data rate processor 40 includes a receive signal strength indicator (RSSI) monitoring function with the on-board 6-bit A/D converter and CCA circuit block 44 provides a clear channel assessment (CCA) to avoid data collisions and optimize network throughput. The present invention provides an extension of the PRISM 1 product from 1 Mbit/s BPSK and 2 Mbit/s QPSK to 5.5 Mbit/s BPSK and 11 Mbit/s QPSK. This is accomplished by keeping the chip rate constant at 11 Mchip/s. This allows the same RF circuits to be used for higher data rates. The symbol rate of the high rate mode is 11 MHz/8 = 1.375 Msymbol/s. For the 5.5 Mbit/s mode of the present invention, the bits are scrambled and then encoded from 4 bit nibbles to 8 chip modified Walsh functions. This mapping results in bi-orthogonal codes which have a better bit error rate (BER) performance than BPSK alone. The resulting 11 Mchip/s data stream is BPSK modulated. The demodulator comprises a modified Walsh correlator and associated chip tracking, carrier tracking, and reformatting devices. For the 11 Mbit/s mode, the bits are scrambled and then encoded from 4 bit nibbles to 8 chip modified Walsh functions independently on each I and Q rail. There are 8 information bits per symbol mapped to 2 modified Walsh functions. This mapping results in bi-orthogonal codes which have better BER performance than QPSK alone. The resulting two 11 Mchip/s data streams are QPSK modulated. The theoretical BER performance of this type of modulation is approximately 10 -5 at an Eb/No of 8 dB versus 9.6 dB for plain BPSK or QPSK. This coding gain is due to the bi-orthogonal coding. There is bandwidth expansion for all of the modulations to help combat multi-path and reduce the effects of interference. Referring additionally to FIG. 2, the output of the QPSK/BPSK modulator and scrambler circuit 51 is partitioned into nibbles of Sign-Magnitude of 4 bits, with the least significant bit (LSB) first. For QPSK, 2 nibbles are presented in parallel to the Modified Walsh Generators 53a, 53b -- the first nibble from the B serial-in/parallel-out SIPO circuit block 52b and the second from A SIPO 52a . The two nibbles form a symbol of data. The bit rate may be 11 Mbit/s as illustrated. Therefore, the symbol rate is 1.375 Mbit/s (11/8 = 1.375). For BPSK, nibbles are presented from the A SIPO 52a only. The B SIPO 52b is disabled. A nibble forms a symbol of data. The bit rate in this instance is 5.5 Mbit/s and the symbol rate remains 1.375 Mbit/s (5.5/4 = 1.375). The Magnitude part of the SIPO output points to one of the Modified Walsh Sequences shown in the table below, along with the basic Walsh sequences for comparison. MAG BASIC WALSH MODIFIED WALSH 0 00 03 1 0F 0C 2 33 30 3 3C 3F 4 55 56 5 5A 59 6 66 65 7 69 6A. The Sel Walsh A, and Sel Walsh B bits from the clock enable logic circuit 54 multiplex the selected Walsh sequence to the output, and wherein the LSBs are output first. The A Sign and B Sign bits bypass the respective Modified Walsh Generators 53a, 53b and are XOR'd to the sequence. In addition, the Modified Walsh code may be generated by modulo two adding a fixed hexadecimal code to the basic or standard Walsh codes to thereby reduce the average DC signal component and thereby enhance overall performance. The output of the Diff encoders of the last symbol of the header CRC is the reference for the high rate data. The header may always be BPSK. This reference is XOR'd to I and Q signals before the output. This allows the demodulator 60 , as described in greater detail below, to compensate for phase ambiguity without Diff decoding the high rate data. Data flip flops 55a, 55b are connected to the multiplexer, although in other embodiments the flip flops may be positioned further downstream as would be readily understood by those skilled in the art. The output chip rate is 11 Mchip/s. For BPSK, the same chip sequence is output on each I and Q rail via the multiplexer 57 . The output multiplexer 58 provides the selection of the appropriate data rate and format. Referring now additionally to FIG. 3, the timing and signal format for the interface 80 is described in greater detail. Referring to the left hand portion, Sync is all 1's, and SFD is F3AOh for the PLCP preamble 90 . Now relating to the PLCP header 91 , the SIGNAL is: OAh 1 Mbit/s BPSK, 14h 2 Mbit/S QPSK, 37h 5.5 Mbit/s BPSK, and 6Eh 11 Mbit/s QPSK. The SERVICE is OOh, the LENGTH is XXXXh wherein the length is in µs, and the CRC is XXXXh calculated based on SIGNAL, SERVICE and LENGTH. MPDU is variable with a number of octets (bytes). The PLCP preamble and PLCP header are always at 1 Mbit/s, Diff encoded, scrambled and spread with an 11 chip barker. SYNC and SFD are internally generated. SIGNAL, SERVICE and LENGTH fields are provided by the interface 80 via a control port. SIGNAL is indicated by 2 control bits and then formatted as described. The interface 80 provides the LENGTH in µs. CRC in PLCP header is performed on SIGNAL, SERVICE and LENGTH fields. MPDU is serially provided by Interface 80 and is the variable data scrambled for normal operation. The reference phase for the first symbol of the MPDU is the output phase of the last symbol of the header for Diff Encoding. The last symbol of the header into the scrambler 51 must be followed by the first bit of the MPDU. The variable data may be modulated and demodulated in different formats than the header portion to thereby increase the data rate, and while a switchover as indicated by the switchover point in FIG. 3, occurs on-the-fly. Turning to FIG. 4, the timing of the high data rate modulator 50 may be understood. With the illustrated timing, the delay from TX_RDY to the first Hi Rate Output Chip is = ten 11 MHz clock periods or 909.1 ns. FIG. 5 refers to the high data rate demodulator 60 . The high rate circuits are activated after the signal field indicates 5.5 or 11 Mbit/s operation. At a certain time, the start phase is jammed into the Carrier NCO 61 and the start frequency offset is jammed into the Carrier Loop Filter 62 . The signal is frequency translated by the C/S ROM 63 and the Complex Multiplier 64 and passed to the Walsh Correlator 65 . The correlator 65 output drives the Symbol Decision circuits 66 , as illustrated. The output of the Symbol Decision circuits 66 are serially shifted by the parallel-in/serial-out SIPO block 67 to the descrambler portion of the PSK Demodulator and Descrambler circuit 70 after passing through the Sign Correction circuit 68 based on the last symbol of the header. The timing of the switch over desirably makes the symbol decisions ready at the correct time. The signal is phase and frequency tracked via the Complex Multiplier 64 , Carrier NCO 61 and Carrier Loop Filter 62 . The output of the Complex Multiplier 64 also feeds the Carrier Phase Error Detector 76 . A decision directed Chip Phase Error Detector 72 feeds the illustrated Timing Loop Filter 75 which, in turn, is connected to the Clock Enable Logic 77 . A decision from the Chip Phase Error Detector 72 is used instead of early-late correlations for chip tracking since the SNR is high. This greatly reduces the additional circuitry required for high rate operation. The 44 MHz master clock input to the Clock Control 74 will allow tracking high rate mode chips with ± 1/8 chip steps. Only the stepper is required to run at 44 MHz, while most of the remaining circuits run at 1 MHz. The circuit is only required to operate with a long header and sync. Turning now to FIG. 6, a pair of Walsh Correlators 65a, 65b is further described. The I_END and Q_END inputs from the chip tracking loop are input at 11 MHz. The Modified Walsh Generator 81 produces the 8 Walsh codes (W0 to W7) serially to sixteen parallel correlators (8 for I_END and 8 for Q_END). The sixteen correlations are available at a 1.375 MHz rate. The Walsh Codes (W0 to W7) are the same as listed in the table above for the high data rate modulator. For the 11 Mbit/s mode, the largest magnitude of I WO to I W7 is selected by the Pick Largest Magnitude circuit 81a to form I sym. I sym is formatted in Sign-Magnitude. The Magnitude is the Modified Walsh Index (0 to 7) of the largest Correlation and Sign is the sign bit of the input of the winning Correlation. The Q channel is processed in parallel in the same manner. For the 5.5 Mbit/s mode, the largest magnitude of I WO to I W7 is selected to form Isym. In this case, only I sym is output. AccEn controls the correlator timing and is supplied by timing and control circuits. With reference to FIG. 7, the carrier tracking loop 90 is now described. In the described embodiment, the number of bits are worst case for estimation purposes. While 3 bits are used for the A/D conversion, a higher number may be desired in other embodiments as would be readily appreciated by those skilled in the art. The Phase BIAS circuit 91 compensates for constellation rotation, that is, BPSK or QPSK. FSCALE compensates for the NCO clock frequency. PHASE SCALE compensates for a phase shift due to frequency offset over the time difference of the first and second loops. The Lead and Lag Shifters 92, 93 form the loop multiplier for the second order carrier tracking loop filter 62 . Referring to FIG. 8, the Chip Tracking Loop 110 is further described. All circuits except Chip Advance/Retard 111 use the 22 MHz clock signal. The Chip Advance/Retard circuit 111 may be made to integrate with the existing clock of the prior art PRISM 1 circuit. PRISM 1 steps in ± 1/4 chips. The PRISM 1 timing may be changed to switchover this circuit for high data rate operation. The A/D clock switches without a phase shift. I_ROT and Q_ROT are from the Complex Multiplier 64 at 22 MHz. They are sampled by the illustrated Registers 112 to produce I_End and Q_End at 11 MHz, which are routed to the Correlators 65 (FIG. 6). The alternate samples I_Mid and Q_Mid are used to measure the chip phase error. For QPSK, errors are generated from both rails, and for BPSK, the error is only generated from the I rail. QPSK En disables the Q rail phase error for BPSK operation. The sign of the accumulator is used to advance or retard the chip timing by 1/8 chip. This circuit must be enabled by the PRISM 1 circuits at the proper time via the HI_START signal. The errors are summed and accumulated for 32 symbols (256 chips). The Chip Track Acc signal them dumps the accumulator for the next measurement. The chip phase error is generated if the End Sign bits bracketing the Mid sample are different. This is accomplished using the transition detectors. The sign of the chip phase error is determined by the sign of the End sample after the Mid sample. A multiplier 114 is shown for multiplying by + 1 if the End Sign is 0 or by -1 if the End Sign is 1. If the End sign bits are identical, the chip phase error for that rail is 0. The AND function is only enabled by transitions. A spread spectrum radio transceiver includes a high data rate baseband processor and a interconnected radio circuit. The baseband processor includes a modulator for spread spectrum phase shift keying (PSK) modulating information for transmission via the radio circuit. The modulator includes at least one modified Walsh code function encoder for encoding information according to a modified Walsh code for substantially reducing an average DC signal component to enhance overall system performance when AC-coupling the received signal through at least one analog-to-digital converter to the demodulator. The demodulator is for spread spectrum PSK demodulating information received from the radio circuit. The modulator and demodulator are each operable in one of a bi-phase PSK (BPSK) mode at a first data rate and a quadrature PSK (QPSK) mode at a second data rate.

Claims: A spread spectrum radio transceiver comprising: a baseband processor and a radio circuit connected thereto, said baseband processor comprising: at least one analog-to-digital (A/D) converter (41) having an input AC-coupled to said radio circuit and an output connected to a demodulator (60) for spread spectrum phase shift keying (PSK) demodulating information received from said radio circuit, said demodulator (60) comprising at least one predetermined orthogonal code function correlator (65) for decoding information according to a predetermined orthogonal code, and further header modulator means for demodulating data packets by demodulating the header at the third format and for switching to the respective one of the first and second formats of the variable data after the header, a modulator (50) for spread spectrum PSK modulating information for transmission via the radio circuit, said modulator comprising at least one predetermined orthogonal code function encoder (53a, 53b) for encoding information according to the predetermined orthogonal code in which said modulator comprises means for operating in one of first format defined by bi-phase PSK (BPSK) modulation at a first data rate and a second format defined by quadrature PSK (QPSK) modulation at a second data rate, and further means for modulating data packets to include a header at a third format defined by a predetermined modulation at a third data rate and variable data operating in one of the first and second formats with the predetermined modulation of the third format being differential BPSK (DBPSK), and the third data rate is lower than the first and second data rates charaterized in that said means for modulating data packets reducing average DC signal component, and that said demodulator (60) comprises a first carrier tracking loop (72, 75) for the third format, and a second carrier tracking loop (61, 62, 63, 76) for the first and second formats, said demodulator means provides a reduced average DC signal component which in combination with the AC - coupling to said at least one A/D converter (41) enhances overall performance, said second carrier tracking loop comprises a carrier numerically controlled oscillator (NCO)(61), and carrier NCO control means (64) for selectively operating said carrier NCO based upon a carrier phase of said first carrier tracking loop (72, 75) and wherein said second carrier tracking loop further comprises: a carrier loop filter (62), and carrier loop filter control means for selectively operating said carrier loop filter based upon a frequency of said first carrier tracking loop (72, 75) to thereby facilitate switching to the format the variable data, and said modulator (50) further comprises: means (52a,52b) for partitioning data into four bit nibbles of sign and magnitude to said at least one predetermined orthogonal code function encoder (53a,53b), and the predetermined orthogonal code is a Walsh code modified by a modulo two addition of a fixed hexadecimal code thereto. A spread spectrum radio transceiver as claimed in claim 1, wherein said at least one predetermined orthogonal code function correlator (65) comprises a predetermined orthogonal code function generator (81), a plurality of parallel connected correlators (65a,65b) connected to said predetermined orthogonal code function generator (81), and the predetermined orthogonal code is a bi-orthogonal code. A spread spectrum radio transceiver as claimed in claims 1 and 2, wherein said at least one modified Walsh code function correlator comprises a modified Walsh function generator (81); a plurality of parallel connected correlators 65a,65b) connected to said modified Walsh function generator, and wherein said modulator comprises spreading means for spreading each data bit using a pseudorandom (PN) sequence at a predetermined chip rate and preamble modulating means for generating a preamble; and wherein said demodulator comprises preamble demodulator means for demodulating the preamble for achieving initial PN sequence synchronization. A spread spectrum radio transceiver as claimed in any one of claims 1 to 3 wherein said radio circuit comprises: a quadrature intermediate frequency modulator/demodulator (35) connected to said baseband processor (40), an up/down frequency converter (33) connected to said quadrature intermediate frequency modulator/demodulator, and a low noise amplifier (38) having an output connected to an input of said up/down converter and a radio frequency power amplifier having an input connected to an output of said up/down converter. A spread spectrum radio transceiver as claimed in claim 4 including an antenna (31) and an antenna (32) switch for switching said antenna between the output of said radio frequency power amplifier and the input of said low noise amplifier (38). A method for baseband processing for spread spectrum radio communication, the method comprising the steps of: spread spectrum phase shift keying (PSK) modulating information for transmission while encoding the information according to a predetermined orthogonal code for reducing an average DC signal component, spread spectrum PSK demodulating received information by decoding the received information according to the predetermined orthogonal code, including the step of AC-coupling and A/D-converting received information for spread spectrum PSK demodulating so that the reduced average DC signal component in combination with the AC-coupling enhances overall performance, modulating and demodulating in one of first format defined by bi-phase PSK (BPSK) modulation at a first data rate and a second format defined by quadrature PSK (QPSK) modulation at a second data rate further comprising the steps of modulating data packets to include a header at a third format defined by a predetermined modulation at a third data rate and variable data in one of the first and second formats, demodulating data packets by demodulating the header at the third format and for switching to the respective one of the first and second formats of the variable data after the header in which the predetermined modulation of the third format is differential BPSK (DBPSK), and wherein the third data rate is lower than the first and second data rates, and the predetermined orthogonal code is a Walsh code modified by a modulo two addition of a fixed hexadecimal code thereto, and the predetermined orthogonal code is a bi-orthogonal code.

Inventors: SNELL JAMES LEROY, SNELL, JAMES LEROY
Applicants: HARRIS CORP, HARRIS CORPORATION
Application year: 1998
Main classification: H04L27
IPC codes: H04Q7, H04B1, H04L27, H04J13