SPEECH AND SOUND SYNTHESIZING

Abstract: A speech synthesizing circuit includes a speech synthesizing integrated circuit chip and an audio synthesizing integrated circuit chip. The speech synthesizing integrated circuit chip has a microprocessor, a speech synthesizer, a programmable memory, an input/output port, and a speech address register. The audio synthesizing integrated circuit chip has a microprocessor, an audio synthesizer, a programmable memory, an audio data storage memory, and an input/output port. The input/output port of the speech synthesizing integrated circuit chip is connected to input/output port of the audio data storage memory of the audio synthesizing integrated circuit chip. The programmable memory of the speech synthesizing integrated circuit chip is programmed to cause the microprocessor of the speech synthesizing integrated circuit chip to retrieve speech data from the audio data storage memory of the audio synthesizing integrated circuit chip for speech synthesis by the speech synthesizer of the speech synthesizing integrated circuit chip. The programmable memory is programmed by providing software simulations of instructions pre-programmed into the speech synthesizing integrated circuit chip during manufacture thereof that cause an address to be loaded onto the speech address register, and cause speech data located at an address stored in the speech address register to be obtained. The software simulations cause an address to be loaded into the audio synthesizing integrated circuit chip and cause speech data to be obtained by the speech synthesizing integrated circuit chip from the external memory integrated circuit chip at an address stored in the external memory integrated circuit chip.

Description: SPEECH AND SOUND SYNTHESIZING Reference to Appendices Text Appendices A-D are being submitted with the present application. Background of the Invention The present invention relates in general to speech and sound synthesizing circuits and more particularly concerns techniques for combining high-efϊϊciency LPC speech synthesizing chips with the low-cost memory of ADPC audio synthesizing chips. One example of LPC (linear predictive coding) speech synthesizing chips is the Texas Instruments TSP50CXX family of LPC chips. These chips are highly efficient in their use of stored speech data because their speech synthesizer models a tube of resonant cavities corresponding to the human vocal cords, mouth, etc. Thus, these chips can synthesize speech at a low data rate. TSP50CXX chips are described in the Texas Instruments Design Manual for the TSP50C0X/ IX Family Speech Synthesizer and also in U.S. Patents Nos. 4,234,761, 4,449,233, 4,335,275, and 4,970,659. An example of ADPCM (adaptive pulse code modulation) audio synthesizing chips is the Sunplus SPC40A, SPC256A, and SPC512A family of chips. These chips produce speech and other sounds at a high data rate. The chips provide low-cost memory because the chips compete with the LPC chips on a cost-per-second basis, and given that their data usage rate is higher than that of the LPC chips by an order of magnitude, these chips must therefore be designed to achieve a cost per memory element that is lower than that of the LPC chips by an order of magnitude. In addition, these chips do not include complex speech synthesis circuitiy. Summary of the Invention One aspect of the invention features a speech synthesizing circuit that includes a speech synthesizing integrated circuit chip and an external memory integrated circuit chip. The speech synthesizing integrated circuit chip includes a microprocessor, a speech synthesizer, a programmable memory, an input/ output port, and a speech address register for storing an address containing speech data. The speech synthesizing integrated circuit chip includes an instruction, pre-programmed into the speech synthesizing integrated circuit chip during manufacture thereof, that causes an address to be loaded onto the speech address register. The input/ output port of the speech synthesizing integrated circuit chip is connected to the external memory integrated circuit chip. The programmable memory of the speech synthesizing integrated circuit chip is programmed to cause the microprocessor to retrieve speech data from the external memory integrated circuit chip for speech synthesis by the speech synthesizer. The programmable memory is programmed by providing a software simulation of the instruction that causes an address to be loaded onto the speech address register. The software simulation causes the address to be loaded into the external memory integrated circuit chip. In certain embodiments the external memory is an audio data storage memory of an audio synthesizing integrated circuit chip that could not ordinarily interface directly with the speech synthesizing integrated circuit chip. The software simulation makes it is possible to retrieve speech data from a preferably relatively inexpensive external memory without the use a hardware interface, thereby minimizing overall cost. The minimization of cost is especially important in certain electronic toys. According to another aspect of the invention, the speech synthesizing integrated circuit chip includes one or more instructions, preprogrammed into the speech synthesizing integrated circuit chip during manufacture thereof, that obtain speech data located at an address stored in the speech address register. At least one of the integrated circuit chips is programmed to cause speech data to be delivered from the external memory integrated circuit chip to the speech synthesizing integrated circuit chip for speech synthesis by the speech synthesizer, by providing a software simulation of the one or more instructions that obtain speech data located at an address stored in the speech address register. The software simulation causes speech data to be obtained by the speech synthesizing integrated circuit chip from the external memory integrated circuit chip at an address stored in the external memory integrated circuit chip. According to another aspect of the invention, the speech synthesizing integrated circuit chip includes a linear predictive coding (LPC) speech synthesizer and the external memory is the audio data storage memory of an audio synthesizing integrated circuit chip that also includes a microprocessor, an adaptive pulse code modulation (ADPCM) synthesizer, a programmable memory, and an input/ output port. The programmable speech data retrieved from the audio data storage memory of the audio synthesizing integrated circuit chip by the speech synthesizing integrated circuit chip is used for speech synthesis by the speech synthesizing integrated circuit chip. In certain embodiments the programmable memory of the audio synthesizing integrated circuit chip is programmed to cause the microprocessor of the audio synthesizing integrated circuit chip to retrieve audio data (e.g., data for non-speech sounds such as breaking glass, ringing bells, etc.) from the audio data storage memory of the audio synthesizing integrated circuit chip for audio synthesis by the audio synthesizer of the audio synthesizing integrated circuit chip. In other embodiments the audio data from the audio synthesizing integrated circuit chip is delivered to the speech synthesizing integrated circuit chip for speech synthesis by the speech synthesizer. The ability to combine the LPC speech synthesizing integrated circuit chip and the ADPCM audio synthesizing integrated circuit chip is useful in certain electronic toys, in which the speech synthesizing integrated circuit chip produces speech while the audio synthesizing integrated circuit chip produces non-speech sound effects. The sharing of speech data between the two integrated circuit chips can be an efficient way to take advantage of a preferably relatively inexpensive memory on the audio synthesizing integrated circuit chip and a preferably relatively efficient speech generation algorithm used by the speech synthesizing integrated circuit chip. This makes it possible to provide extended speech at low cost. According to another aspect of the invention, one of the integrated circuit chips includes a balanced speaker driver having two outputs for connection of a first speaker impedance between the two outputs, and another of the integrated circuit chips includes a single-ended speaker driver having a single output for connection to a second speaker impedance. A speaker is connected between the two outputs of the balanced speaker driver of the first audio synthesizer and is also connected to the single- ended speaker driver of the second audio synthesizer. The connection of a single speaker to the balanced speaker driver and the single-ended speaker driver (with the use of an appropriate resistance network to ensure that each driver "sees" an appropriate effective resistance to which it is connected) makes it possible to combine audio effects from both integrated circuit chips (for example, speech from one chip and non-speech sound effects from the other chip) with a single speaker, thereby minimizing cost. This minimization of cost is important in certain electronic toys. The audio effects from the two integrated circuit chips can be combined simultaneously if the balanced speaker driver produces a pulse width modulated output while the single-ended speaker driver produces an analog output. Numerous other features, objects, and advantages of the invention will become apparent from the following detailed description when read in connection with the accompanying drawings. Brief Description of the Drawings FIG. 1 is a functional block diagram of the Texas Instruments TSP50CXX family of speech synthesizing chips. FIG. 2 is a block diagram of a Texas Instruments TSP50C1X speech synthesizing chip interfaced with an external memory chip through a Texas Instruments TMS60C20-SE hardware interface chip. FIG. 3 is a functional block diagram of a Sunplus SPC40A, SPC256A, or SPC512A audio synthesizing chip. FIG. 4 is a block diagram of a circuit according to the invention combining a Texas Instruments TSP50CXX speech synthesizing chip with a Sunplus SPC40A, SPC256A, or SPC512A audio synthesizing chip. FIG. 5 is a listing of steps that utilize the LUAPS and GET instructions of a Texas Instruments TSP50CXX speech synthesizing chip for synthesizing speech. FIG. 6 is a listing of the steps performed by software simulations, according to the invention, of the steps in FIG. 5. FIG. 7 is a listing of functions performed by certain input and output lines of a Texas Instruments TSP50CXX speech synthesizing chip and a Sunplus SPC40A, SPC256A, or SPC512A chip combined together according to the invention. FIG. 8 is a listing of commands that can be delivered from a Texas Instruments TSP50CXX speech synthesizing chip to a Sunplus SPC40A, SPC256A, or SPC512A chip in accordance with the invention. FIG. 9 is a timing diagram of a write operation in accordance with the invention. FIG. 10 is a timing diagram of a read operation in accordance with the invention. FIG. 11 is a flow chart of the operation of a Sunplus SPC40A, SPC256A, or SPC512A chip according to the invention. Detailed Description With reference to FIG. 1, a Texas Instruments TSP50CXX speech synthesizing chip 10, such as a TSP50C1X or TSP50C3X chip, includes an LPC-12 speech synthesizer circuit 12 (Linear Predictive Coding, 12-pole digital filter), which is capable of operating at a speech sample rate ranging up to ten kilohertz or eight kilohertz (but typically at a data rate of only 1.5 kilobits per second for normal speech), and a microcomputer 14 capable of executing up to 600,000 instructions per second. The microcomputer includes an eight-bit microprocessor 16 with sixty-one instructions, a four- kilobyte, six-kilobyte, eight-kilobyte, sixteen-kilobyte, or thirty- two-kilobyte read-only memory 18 for storing program instructions for microprocessor 16 and for storing speech data corresponding to about twelve, twenty, thirty, sixty, or one hundred and twenty seconds of speech, and an input/ output circuit 20 for ten software-controllable input/output lines (in the case of a TSP50C1X chip, seven lines for connecting the chip to an external memory or an interface adapter for an external memory, as described below, and three arbitrary lines). Speech synthesizing chip 10 also includes a random- access memory 22 having a capacity of sixteen twelve-bit words and either forty-eight or one hundred and twelve bytes of data, depending on the model of the chip, an arithmetic logic unit 24, an internal timing circuit 26, for use in conjunction with microcomputer 14 and speech synthesizer circuit 12, and a speech address register (SAR) 13 for storing addresses at which speech data is located. In the case of a TSP50ClX chip, microcomputer 14 includes a built-in interface that enables microcomputer 14 to connect directly to an optional external Texas Instruments TSP60C18 or TSP60C81 read-only memory that is designed to store speech data in addition to the speech data stored in internal read-only memory 18 for use by speech synthesizer circuit 12 (a mode register in speech synthesizer chip 10 contains a flag indicating whether data is to be retrieved from internal read-only memory 18 or an external memory). This built-in interface includes input/output circuit 20 and seven of the input/ output lines with which it is associated. The built-in interface is controlled by the program in internal read-only memory 18. Referring to FIG. 2, as an alternative to connecting a TSP50C1X speech synthesizing chip 10 directly to a TSP60C18 or TSP60C81 read-only memory, speech synthesizing chip 10 can interface with an arbitrary, industry-standard read-only memory 28 through an external Texas Instruments TMS60C20-SE hardware interface chip 30. The connection between speech synthesizing chip 10 and hardware interface chip 30 includes seven of the input/ output lines of speech synthesizing chip 10, and the connection between hardware interface chip 30 and read-only memory 28 includes about thirty-two lines. Thus, hardware interface chip 30 makes it possible to connect speech synthesizing chip 10 to an external read-only memory 28 having more output lines than could otherwise be connected to speech synthesizing chip 10. Hardware interface chip 30 is controlled by calls from the program in internal read-only memory 18. The structure of the Texas Instruments TSP50C3X chips is similar to that of the TSP50C1X chips described above in connection with Figs. 1 and 2, except that the TSP50C3X chips do not include hardware for connecting to and obtaining data from an external memory. An example of code provided by Texas Instruments for programming read-only memory 18 of a TSP50CXX speech synthesizing chip is attached to this application as Text Appendix A. With reference to FIG. 3, a Sunplus SPC40A, SPC256A, or SPC512A audio synthesizing chip 34 contains a large microcontroller 36 that includes an eight-bit RISC controller 38, a 40, 256, or 512 kilobyte read-only-memory 40 for storing program instructions for RISC controller 38 and for storing audio data corresponding to about twelve seconds of sound, and a 128-byte random-access memory 42 for use in conjunction with RISC controller 38. Audio synthesizing chip 34 also includes an eight-bit digital- to-analog converter 44 that functions as an audio synthesizer by converting data from read-only-memory 40 to analog signals and an internal timing circuit 46 for coordinating operation of microcontroller 36 and digital-to- analog converter 44. A general input/ output port 48 is provided for connecting audio synthesizing chip 34 with external memory for storing additional audio data. Input/ output port 48 has sixteen pins in the case of an SPC40A chip, twenty-four pins in the case of an SPC256A chip, and eleven pins in the case of an SPC512A chip. Audio synthesizing chip 34 typically operates at a data rate of about 24 kilobits per second, which is much higher than the typical data sample rate of the speech synthesizing chip described above in connection with FIG. 1. The speech synthesizing chip of FIG. 1 and the audio synthesizing chip of FIG. 3 are of comparable price and both can store data corresponding to about twelve seconds of sound. The audio synthesizing chip of FIG. 3 must store more data than the speech synthesizing chip of FIG. 1 because of the difference in the data sample rates, and thus it can be said that the audio synthesizing chip of FIG. 3 uses a cheaper memory. An examples of code provided by Sunplus for programming the read-only memory 40 of an SPC40A, SPC256A, or SPC512A audio synthesizing chip is attached to this application as Text Appendix B. Referring to Fig. 4, in a circuit according to the present invention the input/ output circuit 20 of a Texas Instruments TSP50C1X or TSP50C3X speech synthesizing chip 10 is connected directly to the input/ output port 48 of a Sunplus SPC40A, SPC256A, or SPC512A audio synthesizing chip 34 by means of four input/ output lines. The flow of audio data is illustrated by paths 50, 52, and 54. In particular, speech synthesizer circuit 12 of speech synthesizing chip 10 receives speech data from read-only memory 18 of speech synthesizing chip 10 along path 50 and also receives additional speech data from read-only memory 40 of audio synthesizing chip 34 along path 52. Digital-to-analog converter 44 of audio synthesizing chip 34 can receive non-speech audio data (e.g., music, breaking glass, ringing bells) from read-only memory 40 of audio synthesizing chip 34 along path 54. Thus, speech synthesizer circuit 12 receives more speech data than can be included in internal read-only memory 18, the additional speech data being received from an external read-only memory 40 that is cheaper per unit of speech data than internal read-only memory 18. Because digital-to-analog converter 44 does not include the LPC speech processing capabilities of speech synthesizer circuit 12, and because speech synthesizer circuit 12 is not specifically designed for synthesizing non-speech sounds, it can be more appropriate to direct non-speech data from read-only memory 40 to digital- to-analog converter 44 than speech synthesizer circuit 12. Both chips 10 and 34 can create sound effects at the same time, with chip 10 producing speech and chip 34 simultaneously producing non-speech sound effects. The flow of data along paths 50 and 54 is conventional in each of chips 10 and 34, but the flow of data along path 52 is obtained by modifying the standard code for read-only memory 18 and the standard code for read-only memory 40 to permit the direct connection between the two chips. An example of a code modification for read-only memory 18 of chip 10 is attached to this application as Text Appendix C and an example of a code modification for read-only memory 40 is attached as Text Appendix D. The modification of the code in read-only memory 40 instructs the microprocessor of chip 34 to send speech data to input/ output port 48 along path 52 rather than to digital-to-analog converter 44 along path 54. The flow of data along path 52 between chips 10 and 34 occurs through four input/ output lines of each of chips 10 and 34. The four input/ output lines may be, for example, lines PAO, PA1, PA2, and PB1 of chip 10, and lines PD0, PD6, PD 1, and PD4 respectively of chip 34. The modification of the code in read-only memory 18 is a software simulation of the hardware "LUAPS" and "GET" instructions of chip 10 (hardware instructions are implemented by hard-wired gates or micro-code instructions programmed into a chip during manufacture). With reference to Fig. 5, ordinarily, a desired start address of a speech segment is loaded into the A register of chip 10, and then the "LUAPS" instruction loads the address from the A register into the SAR register (Speech Address Register) on chip 10 and loads a parallel- to-serial register on chip 10 with the contents of the address contained in the SAR register. Then, each successive "GET X" instruction transfers X bits from the parallel-to-serial register, to the A register of chip 10. The SAR register is incremented every time the parallel-to-serial register is loaded, and whenever the parallel-to- serial register becomes empty, it is loaded with contents of the address contained in the SAR register. The groups of bits obtained by the "GET" instructions form the frames of LPC parameters described in detail in the above-mentioned Texas Instruments Design Manual and patents. In the TSP50C1X chips, the address pointed to by the SAR register may be on-chip or off-chip (if a specially configured Texas Instruments external memory is used), because the TSP50C1X chips include hardware for connecting to and obtaining data from a specially configured Texas Instruments external memory. In the TSP50C3X chips the address pointed to by the SAR register must be on-chip. With reference to Fig. 6, according to the present invention, a software simulation of the LUAPS and GET instructions of Fig. 5 is provided. Instead of loading the address from the A register of the LPC chip into an SAR register as in the case of the LUAPS instruction of Fig. 5, CALL STPNTR(X) causes pointer X to be stored in the ADPCM chip. Instead of loading a parallel-to-serial register in the LPC chip with the contents of the address contained in an SAR register and transferring bits from the parallel- to-serial register to the A register of the LPC chip as in the case of the LUAPS and GET instructions of Fig. 5, CALL PREPGET P(X) prepares the ADPCM chip to send to the LPC chip the data to which pointer X points, and CALL GET(Y) causes Y bits of data pointed to by pointer X to be read from the ADPCM chip. In one embodiment, up to three pointers are used, so that data can be read from up to three sets of storage locations corresponding to three different sounds to be produced simultaneously by the LPC chip (for example, music with three-part harmony). With reference to Fig. 7, according to the input/ output structure of the LPC chip provided by the invention, the interface operation is accomplished over four wires and is a command-driven structure. All commands are initialized on the side of the LPC chip and the ADPCM chip is slave to the requested operations. Lines PAO-2 provide command codes to the ADPCM chip, and line PB1 indicates to the ADPCM chip that there is a command on lines PAO-2. The LPC chip drops command strobe line PB1 after setting up a command on lines PAO-2, and the ADPCM chip responds by executing the command that was strobed. Thus, the processor of the LPC chip initiates each command and the processor of the ADPCM chip executes that command. The various commands are shown in Fig. 8. Commands 1-3 indicate that data pointer 1, 2, or 3 is to be sent to the ADPCM chip (this corresponds to CALL STPNTR(X)), and commands 4-6 indicate that data to which pointer 1, 2, or 3 points is to be read from the ADPCM chip (this corresponds to CALL PREPGET P(X). In one particular embodiment useful in certain toys, command 0 instructs the ADPCM chip to strobe one of eight strobe outputs to a game keyboard. Referring again to Fig. 7, once the ADPCM chip has received the appropriate command, line PAO is used to read data from the ADPCM chip or send a pointer to the ADPCM chip, and line PA1 is used to clock the data serially into or out of the LPC chip. The ADPCM processor maintains address pointers and counter that are advanced on clock events received on line PA1. Line PA2 is used as a handshake signal during the process of reading data from the ADPCM chip. With reference to Fig. 9, the LPC processor will perform CALL STPNTR(X) by placing a "Write Pointer X" command on lines PA0-PA2 and lowering strobe line PB1. After a period of time sufficient for the ADPCM chip to read the command has elapsed, the LPC chip provides the first bit of data on line PAO and then drops the clock signal on line PA1. During the clock low time the ADPCM chip will accept and read in the bit on line PAO, and then the next bit of data is placed on line PA1, and so on. Operations that write data from the LPC processor to the ADPCM processor are done without a handshaking signal. The data is clocked out by a fixed clock cycle. The clock cycle time is the minimum time required for the ADPCM chip to reliably clock in the data. The LPC processor completes the operation by raising strobe line PB1 high. When the ADPCM chip detects a "Write Pointer X" command it will expect up to sixteen clocked data bits. When the operation is complete the ADPCM chip stores the received value as Pointer X. It is possible to clock in fewer than sixteen bits of data to specify an address. In particular, the first bit read out is the first bit of the address, and once strobe line PB1 goes high, the unclocked data bits are all assumed to be zeros. The timing diagram of Fig. 9 is also used in connection with the "Write Keyboard Strobe" command (Command 0 in Fig. 8). When the ADPCM chip detects a "Write Keyboard Strobe" command it will expect a clocked data bit to specify the next output state. Once strobe line PB1 goes high, the ADPCM chip drives the strobe lines to the proper value. In this way, the LPC chip controls eight outputs of the ADPCM chip, and thus the interface between the LPC and ADPCM chips effectively increases the number of input/ output lines available to the LPC chip. With reference to Fig. 10, operations that read data from the ADPCM chip to the LPC chip involve a handshaking signal on line PA2. The "Read Data from Pointer X" commands (see discussion of Fig. 8 above) require line PA2 to be high, which is necessary in order for handshaking to proceed correctly. This is because line PA2 is configured as an open-drain output at initialization, externally pulled high by a 10K resistor. When the LPC processor performs CALL PREPGET P(X) in order to prepare to read data, the LPC chip issues a "Read Data from Pointer X" command on lines PAO- 1 and then lowers strobe PB1. In response to the command, the ADPCM chip switches from its default input mode to an output mode with respect to lines PAO and PA2 of the LPC chip (consequently, for a brief period of time, line PAO of the LPC chip will receive output signals from both the LPC chip and the ADPCM chip). The ADPCM chip then acknowledges acceptance of the command by pulling low line PA2 of the LPC chip. The LPC chip then performs CALL GET(Y) by setting line PAO to an input, lowering line PA1 to start the clocking of data, and raising strobe line PB1 to indicate to the ADPCM chip that the LPC chip is ready to receive data. The ADPCM chip places the first bit of data on line PAO and releases line PA2. The LPC chip reads the data and raises the clock signal on PAl to signal that the data has been read. The ADPCM chip responds by advancing an internal bit counter and pulling line PA2 low to acknowledge receipt of the clock signal, and the LPC chip then responds by lowering line PAl to start the clocking of the next bit of data. The ADPCM chip then places the next bit of data on line PAO and releases line PA2, and the process continues until the LPC chip has received as much data as it wants. The LPC processor completes the operation by raising strobe line PB1 high after Y bits of data have been received. The four-wire interface between the two chips may also be used to transfer non-speech data in either direction between the LPC RAM and the ADPCM RAM, in a manner similar to the timing diagrams of Figs. 9 and 10, in order to effectively expand the amount of RAM available to the master chip (the LPC chip in the embodiments described above). Fig. 1 1 is a flow chart of the operation of the ADPCM chip. The ADPCM chip watches for strobe line PB1 of the LPC chip to go down (step 100), and when this happens the ADPCM chip receives a read or write command on lines PA0-PA2 of the ADPCM chip (step 102), handles the read command (step 104; Fig. 10) or write command (step 106; Fig. 12), and then returns to step 100. In another alternative embodiment, the ADPCM chip can be set up as the master microcontroller, and the LPC chip can function as the slave. In this embodiment there is no need to perform a software simulation of the LUAPS instruction of the LPC chip, because the pointers to the data in the ADPCM chip all originate from the ADPCM chip itself. It will now be apparent to those skilled in the art that data can be transferred from the ADPCM chip to the LPC chip according to a technique similar to the technique shown in the timing diagram of Fig. 10 (the initial synchronization process at the beginning of the timing diagram would differ but then the actual data transfer process could proceed in a manner similar to that shown in Fig. 10). Thus, a type of software simulation of the LUAPS and GET instructions of the LPC chip can be performed, even though the LPC chip in this particular embodiment functions as a slave. With reference to Fig. 4, the outputs of speech synthesizer circuit 12 of chip 10 and digital-to-analog converter 44 of chip 34 are connected to a single speaker 56. The output of speech synthesizer circuit 12 is a pulse- width-modulated push-pull bridge balanced drive for a 32-ohm speaker, and the output of digital-to-analog converter 44, amplified by transistor 58, is a single-ended drive for an 8-ohm speaker. The output of digital-to- analog converter 44, amplified by transistor 58, is connected to a node between 16-ohm speaker 56 and 16-ohm resistor 60. Thus, the output of digital-to-analog converter 44 is connected to two parallelly connected 16- ohm resistances, or, in other words, an 8-ohm single-ended resistance. At the same time, the output of speech synthesizer circuit 12 is connected to two series-connected 16-ohm resistances, or, in other words, a 32-ohm resistance. When speech synthesizer 12 is silent, its push-pull bridge balanced drive goes to low impedance, and the two outputs 62 and 64 of the push-pull bridge balanced drive are at a positive voltage. This makes it possible for current to pass from output 62, through speaker 56, and through amplifier 58 while audio synthesizer integrated circuit chip 34 is operating. When chip 34 is silent, transistor 58 goes to high impedance (i.e., transistor 58 switches off). Meanwhile, pulse width modulated current may pass between outputs 62 and 64 of the push-pull bridge balanced drive of speech synthesizer 12 through speaker 56 while speech synthesizer 12 is operating. It is possible for both of chips 10 and 34 to operate simultaneously with the single speaker 56 because, when chip 10 is operating, output 62 of speech synthesizer 12 pulses high and low, and whenever output 62 is high, current can pass from output 62 through transistor 58 to produce the audio sounds synthesized by chip 34. The frequency of on and off pulsing of output 62 is too fast to affect the perceived sound output produced by chip 34. There has been described novel and improved apparatus and techniques for speech and sound synthesizing. It is evident that those skilled in the art may now make numerous uses and modifications of and departures from the specific embodiment described herein without departing from the inventive concept. APPENDIX A Title: SPEECH AND SOUND SYNTHESIZNG Applicant: Hasbro, Inc. Standard TI D6 Speech Engine ********************************* ** ********* ** * ** ** **** *** * Speak Utterance - Phrase number in A register * *** ******* * ***** * * * ** * ** ** *** * ******** ****** ** ******* **** * SPEAK INTGR BR SPEAK3 -Go to getlst word number SPEAK 1 RETN -yes, exit routine SPEAK3 SALA -Double index to get offset ACAAC SPEECH -Add base of table LUAB -get address MSB IAC LUAA -Get address LSB XBA SALA4 -Combine MSB and LSB SALA4 ABAAC LUAPS -Load Speech Address Register CLA -Kill Kl 1 and K12 parameters TAMD Kl 1 TAMD K12 TAMD FLAGS -Init flags for speech CLA -Load C2 parameter ACAAC C2_Value TAMD C2 CLA -Load Cl parameter ACAAC Cl_Value TAMD Cl * * * * * * Now we give an initial value to the Pitch in case the utterance starts * with a silent frame. * * * * * ACAAC #0C TAMD PHV1 TAMD PHV2 ***** * Now we preload the first two frames. * * * * * CALL UPDATE -Load first frame CALL UPDATE -Load 2nd frame * * * * * * Now we give some values to the Timer and Prescaler so that we can do a * valid interpolation on the first call to INTP. Then I do the first * call to INTP to preload the first valid interpolation. * * * * * TCA PSVALue -Initialize prescale TAPSC TCA #7F -Pretend there was a previous update TAMD TIMER TCA #FF -Set timer to max value to... TATM -...disable interpolation CALL INTP -Do first interpolation * * * * * * Now we enable the synthesizer for speech * * * * * TCX MODE -Turn on LPC synthesizer ORCM LPC_ON TMA TAMODE RETI -Reset interrupt pending latch ORCM INT_ON -Enable interrupt TMA TAMODE * * * * * * Now we loop until the utterance is complete. When the utterance is * finished, the routine UPDATE will execute a RETN instruction which * will exit this routine. In the mean time, this loop will poll the * Timer register and update the frame whenever it underflows. * * * * * SPEAK_LP TCX FLAGS TSTCM Update_Flg -Update already done? BR SPEAKJJ? -yes, loop TCX TIMER -Get old timer TMA register valu TAB -into B register TTMA -Get new timer register SARA -value and scale it. TAM -Store new value XBA -Exchange new and old values SBAAN -Subtract new from old BR UPDATE -If underilowed, do an update TMA -Get new timer value again. ANEC 0 -Is it about to underflow? BR SPEAK_LP no, loop again BR UPDATE yes, do update now * * * * * * INTERPOLATION ROUTINE * * * * * * First we need to get the current value of the timer register and store * it away. It will be divided by two with the SARA instruction so that * the most significant bit is guaranteed to be zero so that it will always * be interpreted as a positive number during the interpolation. * * * * * INTP TTMA -Get timer register contents SARA -shift to make positive TAMD SCALE -and store it * * * * * * Next we need to see if the frame type has changed between voiced and * unvoiced frames. If it has, we do not want to interpolate between * them; we just want to use the current frame values until we have two * frames of the same type to interpolate between. * * * * * TCX FLAGS -Test to see if Interpolation TSTCM Int nh -is inhibited BR NOINT -yes, use inhibit code BR INTPCH -yes, use inhibit code * * * * * * The following code is reached if interpolation is inhibited. It sets * the stored timer value to #7F which effectively forces the interpolation * to yield the old values for the working values, thus effectively disabling * interpolation. * * * * * NOINT TCA #7F -Set Scale factor to TAMD SCALE -highest value * * If the new frame has a voicing different fromthe last frame, * we want to zero the energy until the Unvoiced bit in the mode * register is changed and the K paramaters are all to the current * values. We therefore check in this section of code to see if * the frame voicing is different from the setting in MODE. If it * is, we zero the energy until after MODE is modified. * TCX FLAGS TSTCM Unv_Flg2 -Is new frame unvoiced? BR Uv -Yes, go to unvoiced branch TCX MODE -New frame is voiced TSTCM UNV -Has mode been changed to voiced? BR ClrEN -No, clear the energy Uv TCX MODE -New frame is unvoiced TSTCM UNV -Has mode been changed to unvoiced? BR INTPCH -Yes, no action required ClrEN CLA -Zero Energy during update TAMD EN BR INTPCH * * * * * * Interpolate Pitch and store the result in the working register * * * * * INTPCH INTGR -Need Integer mode for pitch TCX PHV2 -Combine pitch and fractional TMAIX -pitch and leave in SALA4 -the B register AMAAC IXC TAB TMAIX -Combine current pitch and SALA4 -current fractional pitch AMAAC -and leave in A register SBAAN -(Pcurrent - Pnew) TCX SCALE AXMA -(Pcurrent - Pnew) * Timer ABAAC -Pnew + (Pcurrent - Pnew)* Timer SALA -LSB must be 0 to address excitation table TASYN -Write to pitch register EXTSG -Allow negative K parameters * * * * * * Interpolate Energy and store the result in the working register * * * * * TCX ENV2 -Combine energy and fractional TMAIX -energy and leave in SALA4 -the B register AMAAC IXC TAB TMAIX -Combine current energy and SALA4 -current fractional energy & AMAAC -leave in A register SBAAN -(Ecurrent - Enew) TCX SCALE AXMA -(Ecurrent - Enew) * Timer ABAAC -Enew + (Ecurrent - Enew) * Timer TAMD EN_TEMP -Store Energy til mode is switched TAMD EN EXTSG -Allow K parameters to be negative ***** * Interpolate Kl and store the result inthe working Kl register ** *** TCX K1V2 -Combine New Kl and New TMAIX -fractional Kl and SALA4 -leave in the B register AMAAC IXC TAB TMAIX -Combine current Kl and SALA4 -current fractional Kl and AMAAC -leave in the A register SBAAN -(Klcurrent - Klnew) TCX SCALE AXMA -(Kl current - Klnew) * Timer ABAAC -Klnew+(Klcurrent-Klnew) * Timer TAMD Kl -Load interpolated value to synth ***** Interpolate K2 and store the result in the working K2 register ** *** TCX K2V2 -Combine New K2 and New TMAIX -fractional K2 and SALA4 -leave in the B register AMAAC IXC TAB TMAIX -Combine current K2 and SALA4 -current fractional K2 and AMAAC -leave in the A register SBAAN -(K2current - K2new) TCX SCALE AXMA -(K2current - K2new) * Timer ABAAC -K2new+(K2 current- K2new) * Timer TAMD K2 -Load interpolated value to synth ** *** Interpolate K3 and store the result in the working K3 register * * *** TCX K3V2 -Combine New K3 and New TMAIX -fractional K3 and SALA4 -leave in the B register TAB TMAIX -Combine current K3 and SALA4 -current fractional K3 and SBAAN -(K3current - K3new) TCX SCALE AXMA -(K3current - K3new) * Timer ABAAC -K3new+(K3current-K3new) * Timer TAMD K3 -Load interpolated value to synth * * * * * Interpolate K4 and store the result in the working K4 register * * * * * TCX K4V2 -Combine New K4 and New TMAIX -fractional K4 and SALA4 -leave in the B register TAB TMAIX -Combine current K4 and SALA4 -current fractional K4 and SBAAN -(K4current - K4new) TCX SCALE AXMA -(K4current - K4new) * Timer ABAAC -K4new+(K4current-K4new) * Timer TAMD K4 -Load interpolated value to synth ***** Interpolate K5 and store the result in the working K5 register ***** TCX K5V2 -Put New K5 (adjusted to TMAIX -12 bits) in B register SALA4 TAB TMAIX -Put Current K5 (adjusted to SALA4 - 12 bits) in A register SBAAN -(K5current - K5new) TCX SCALE AXMA -(K5current - K5new) * Timer ABAAC -K5new+(K5current-K5new) * Timer TAMD K5 -Load interpolated value to synth ***** Interpolate K6 and store the result in the working K6 register * * * * * TCX K6V2 -Put New K6 (adjusted to TMAIX -12 bits) in B register SALA4 TAB TMAIX -Put Current K6 (adjusted to SALA4 -12 bits) in A register SBAAN -(Kόcurrent - K6new) TCX SCALE AXMA -(K6current - K6new) * Timer ABAAC -K6new+(K6current-K6new) * Timer TAMD K6 -Load interpolated value to synth * * * * Interpolate K7 and store the result in the working K7 register * * * * TCX K7V2 -Put New K7 (adjusted to TMAIX - 12 bits) in B register SALA4 TAB TMAIX -Put Current K7 (adjusted to SALA4 -12 bits) in A register SBAAN -(K7current - K7new) TCX SCALE AXMA -(K7current - K7new) * Timer ABAAC -K7new+(K7current-K7new) * Timer TAMD K7 -Load interpolated value to synth * * * * Interpolate K8 and store the result in the working K8 register * * * * TCX K8V2 -Put New K8 (adjusted to TMAIX - 12 bits) in B register SALA4 TAB TMAIX -Put Current K8 (adjusted to SALA4 - 12 bits) in A register SBAAN -(K8 current - K8new) TCX SCALE AXMA -(K8 current - K8new) * Timer ABAAC -K8new+(K8current-K8new) * Timer TAMD K8 -Load interpolated value to synth * * * * Interpolate K9 and store the result in the working K9 register * * * * TCX K9V2 -Put New K9 (adjusted to TMAIX -12 bits) in B register SALA4 TAB TMAIX -Put Current K9 (adjusted to SALA4 -12 bits) in A register SBAAN -(K9current - K9new) TCX SCALE AXMA -(K9 current - K9new) * Timer ABAAC -K9new+(K9current-K9new) * Timer TAMD K9 -Load interpolated value to synth * * * * * * Interpolate KIO and store the result in the working KIO register * * * * * TCX K10V2 -Put New KIO (adjusted to TMAIX ■ 12 bits) in B register SALA4 TAB TMAIX -Put Current KIO (adjusted to SALA4 -12 bits) in A register SBAAN -(KlOcurrent - KlOnew) TCX SCALE AXMA -(KlOcurrent - KlOnew) * Timer ABAAC -K10new+(K10current-K10new) * Timer TAMD KIO -Load interpolated value to synth * * * * * * Kκ 1l1 l1 aanndd KK1l .22 a arree nr ot needed for LPC 10, so I have taken them out. * * * * * * * * * * * Set voiced/unvoiced mode according to current frame type. This is * done in a two step fashion: first the value in the MODE register * is adjusted with an AND or OR operation, then the result is written * to the synthesizer with a TAMODE operation. We do it this way to keep * a copy of the current status of the synthesizer mode at all time. * * * * * STMODE INTGR -Back to integer mode TCX FLAGS ANDCM -Update_Flg -Signal that interp done TSTCM Unv_Flg2 -Is current frame unvoiced? BR SETUV -Yes, set mode to unvoiced TCX MODE -No, set mode to voiced ANDCM -LPCJJNV TMA TAMODE TMAD EN_TEMP -Change Energy parameter, TAMD EN .to correct value RETI -Return from interrupt RETN -Return from first call SETUV TCX MODE -Current frame is unvoiced, so ORCM LPC UNV -Set mode to unvoiced. TMA TAMODE * TMAD EN_TEMP -Change Energy parameter... * TAMD EN -...to correct value. * RETI -Return from interrupt RETN -Return from first call ** * * * * Update the parameters for a new frame ***** * First we inhibit the operation of the interpolation routine. ***** UPDATE TCX MODE ANDCM ~INT_ON TMA TAMODE ** * ** * To prevent double updates, if the stored value of the timer register * is zero, then we need to change it to #7F. If we do not do this, than * the polling routine will discover an underflow and call Update a second * time. * * * * * TCX TIMER -Get stored value TMA -of Timer into A ANEC 0 -Is it zero? BR UPDTOO -no, do nothing TCA #7F -yes, replace value TAM * **** * First we need to test to see if a stop frame was encountered on the last * pass through the routine. If the previous frame was a stop frame, we * need to turn off the synthesizer and stop speaking. ***** UPDTOO TCX FLAGS TSTCM STOPFLAG -Was stop frame encountered BR STOP -yes, stop speaking * * * * * * Transfer the state of the previous frame to the Unvoiced flag (Current) * and set the mode mirror buffer to reflect the voicing of the previous frame. *** * * TSTCM Unv_Flgl -Was previous frame unvoiced? BR SUNVL -Yes, set current frame unvoiced ANDCM #7F -No, set current frame voiced BR TSIL SUNVL ORCM Unv_Flg2 -Set current frame unvoiced. * * * * * * Transfer the state of the previous frame to the Silence flag (Current) * and set the mode mirror buffer * * * * * TSIL TSTCM Sil_Flgl -Was previous frame silent? BR SSIL -Yes, set current frame silen ANDCM ~Sil_Flg2 -No, set current frame not silent BR ZROFLG SSIL ORCM Sil_Flg2 -Set current frame unvoiced. * * * * * * Reset the Repeat Flag, Silence Flag, Unvoiced Flag, and Interpolation * Inhibit flag so that new values can be loaded in this routine. * * * * * ZROFLG TCX FLAGS ANDCM #C5 * * * * * * Transfer the current new frame parameters into the storage location used * for the current frame parameters. * * * * * TCX ENV2 -Transfer new frame energy TMAIX -to current frame location TAMD ENV1 TMAIX -Transfer new fractional energy IXC -to current frame location TAMIX * PITCH— TMAIX -Transfer new frame pitch TAMD PHV1 -to current frame location TMAIX -Transfer new fractional pitch IXC -to current frame location TAMIX * κi TMAIX -Transfer new frame Kl paramete TAMD K1V1 -to current frame location TMAIX -Transfer new fractional Kl par IXC -to current frame location TAMIX * K2 TMAIX -Transfer new frame K2 paramete TAMD K2V1 -to current frame location TMAIX -Transfer new fractional parame IXC -to current frame location TAMIX * K3 TMAIX -Transfer new frame K3 paramete TAMIX * K4 TMAIX -Transfer new frame K4 paramete TAMIX * K5 TMAIX -Transfer new frame K5 paramete TAMIX -to current frame location * K6 TMAIX -Transfer new frame K6 paramete TAMIX -to current frame location * K7 TMAIX -Transfer new frame K7 paramete TAMIX -to current frame location * K8— - TMAIX -Transfer new frame K8 paramete TAMIX -to current frame location * K9 TMAIX -Transfer new frame K9 paramete TAMIX -to current frame location * KIO TMAIX -Transfer new frame KIO paramet TAMIX -to current frame location * * * * * * Kl 1 and K12 are not used in LPC 10 synthesis, so the code has been * commented out. * * * * * * Kl l * TMAIX -Transfer new frame Kl l paramet * TAMIX -to current frame location * K12 * TMAIX -Transfer new frame Kl 2 paramet * TAMIX -to current frame location * * * * * * We have now discarded the "current" values by replacing it with the * "new" values. We now need to read in another frame of speech data and * used them as the new "new" values. * * * * * * ENERGY CLA TCX FLAGS GET EBITS -Get coded energy ANEC ESILENCE -Is it a silent frame? BR UPDTO -No, continue ORCM Sil_Flgl+Int_Inh -Yes, set silence flag BR ZeroKs -zero K params * UPDTO ANEC ESTOP -Is it a stop frame? BR UPDT1 -No, continue ORCM STOPFLAG+Sil_Flgl+Int_Inh yes, set flags BR ZeroKs -Zero Ks * UPDT1 ACAAC TBLEN -Add table offset to energy index LUAA -Get decoded energy TAMD ENV2 -Store the Energy in RAM * * * * * * If this is a silent frame, we are done with the update If the previous * frame was silent, the new frame should be spoken immediately with no * ramp up due to interpolation. * * * * * TCX FLAGS TSTCM Sil_Flgl -Is this a silent frame? BR RTN -yes, exit * * * * * A repeat frame will use the K parameter from the previous frame. If it is, we need to set a flag. * * * * * UPDT2 GET RBITS -Get the Repeat bit TSTCA #01 -Is this a repeat frame? BR SFLG1 -yes, set repeat flag BR UPDT3 SFLG1 ORCM R_FLAG -Set repeat flag * PITCH UPDT3 CLA GET 4 -Get coded pitch GET 3 -Get coded pitch ANEC PUnVoiced -Is the frame unvoiced? BR UPDT3A -no, continue ORCM Unv_Flgl -yes, set unvoiced flag UPDT3A SALA -Double coded pitch and ACAAC TBLPH -add table offset to point to table LUAB -Get decoded pitch IAC LUAA -Get decoded fractional pitch TCX PHV2 -Store the pitch and fractional TBM -pitch in RAM IXC TAM ***** * If the voicing has changed with the new frame, then we need to change * the voicing in the mode register. ***** TCX FLAGS TSTCM Unv_Flgl -Is the new frame unvoiced? BR UPDT3B -yes, continue BR VOICE -no, go to voiced code * * * * * * The following code is reached if the new frame is unvoiced. We inspect * the flags to see if the previous frame was either silent or voiced. * If either condition applies, then we branch to code which inhibits * interpolation. * * * * * UPDT3B TSTCM Sil_Flg2 -Was the previous frame silent? BR UPDT5 -yes, inhibit interpolation TSTCM Unv_Flg2 -Was the previous frame unvoiced BR UPDT4 -yes, no need to change anything BR UPDT5 -no, inhibit interpolation * * * * * * The following code is reached if the new frame is voiced. We inspect the * flags to see if the previous frame was also voiced. If it was not, we * need to inhibit interpolation. ***** VOICE TSTCM Unv_Flg2 -Was the previous frame voiced? BR UPDT5 -no, set no interpolation flag BR UPDT4 -yes, no need to change anything UPDT5 ORCM Int nh -Inhibit interpolation * * * * * * Now we test the repeat flag. If the new frame is a repeat frame, then * the current values are used for the K factors, so new values do not need * to be loaded and we can exit the routine now. * * * * * UPDT4 TSTCM R_FLAG -Is repeat flag set? BR RTN -yes, exit routine * * * * * * Now we need to load the "new" K factors (Kl through KIO). EachK * factor is a 12 bit value which will be stored in two bytes. The most * significant 8 bit in the first byte, and the least significant 4 bits * (called the fractional value) in the second byte. For K5 through K12, * the fractional part is assumed to be zero. Kl 1 and K12 are not used in * LPC synthesis, and the code loading them is commented out. A coded * factor is read into the A register. It is then converted to a pointer * to a table element which contains the uncoded factor. Since each table * element consists of two bytes, the conversion consists of doubling the * uncoded factor and adding the offset of the start of the table. The * uncoded factor is fetched and stored into RAM. * * * * * ' Kl CLA GET 4 -Get coded Kl GET 2 -Get coded Kl SALA -Convert it to a ACAAC : TBLKl pointer to table element LUAB -Fetch MSB of uncoded Kl IAC LUAA -Fetch fractional Kl TCX K1V2 TBM -Store uncoded Kl IXC TAM -Store fractional Kl • K2 CLA GET 4 -Get coded K2 GET 2 -Get coded K2 SALA -Convert it to a ACAAC : TBLK2 pointer to table element LUAB -Fetch MSB of uncoded K2 IAC LUAA -Fetch fractional K2 TCX K2V2 TBM -Store uncoded K2 IXC TAM -Store fractional K2 K3 CLA GET 4 -Get Index into K3 table GET 1 -Get Index into K3 table ACAAC TBLK3 -and add offset of table to it LUAA -Get uncoded K3 TAMD K3V2 -and store it in RAM -K4 CLA GET 4 -Get Index into K4 table GET 1 -Get Index into K4 table ACAAC TBLK4 -and add offset of table to it LUAA -Get uncoded K4 TAMD K4V2 -and store it in RAM * * * * * * If this is a unvoiced frame, we only use four K factors, so we load * zeroes to the rest of the K factors. If this is a voiced frame, load * the rest of the uncoded factors. * * * * * TCX FLAGS TSTCM Unv_Flgl -Is this an unvoiced frame? BR UNVC -Yes, zero rest of factors * * * * * * The following code is executed if the current frame is voiced. Since * we assume that the fractional parameter is zero for the remaining K * factors, the table elements are only one byte long. The conversion to a * table pointer now consists of adding the offset of the start of the table. * * * * * ' K5 CLA GET K5BITS -Get Index into K5 table ACAAC TBLK5 -and add offset of table to it LUAA -Get uncoded K5 TAMD K5V2 -and store it in RAM K6 CLA GET K6BITS -Get Index into K6 table ACAAC TBLK6 -and add offset of table to i LUAA -Get uncoded K6 TAMD K6V2 -and store it in RAM ■ K7 CLA GET K7BITS -Get Index into K7 table ACAAC TBLK7 -and add offset of table to i LUAA -Get uncoded K7 TAMD K7V2 -and store it in RAM K8-— CLA GET K8BITS -Get Index into K8 table ACAAC TBLK8 -and add offset of table to i LUAA -Get uncoded K8 TAMD K8V2 -and store it in RAM * K9— - CLA GET K9BITS -Get Index into K9 table ACAAC TBLK9 -and add offset of table to i LUAA -Get uncoded K9 TAMD K9V2 -and store it in RAM * KIO CLA GET K10BITS -Get Index into KIO table ACAAC TBLK10 -and add offset of table to i LUAA -Get uncoded KIO TAMD K10V2 -and store it in RAM * * * * * * Since Kll and K12 are not used in LPCIO, the Kll and K12 code is removed * * * * * BR RTN * * * * * * The following code is executed if the K parameters need to be cleared. * If the new frame is a stop frame or a silent frame, we clear all K * parameters and set energy to zero. If the new frame is an unvoiced * frame, then we need to zero out the unused upper K parameters. * * * * * ZeroKs CLA TAMD ENV2 -Kill Energy TAMD ENV2+1 TAMD K1V2 -Kill Kl TAMD K1V2+1 TAMD K2V2 -KillK2 TAMD K2V2+1 TAMD K3V2 -Kill K3 TAMD K4V2 -KillK4 UNVC CLA TAMD K5V2 -KH1K5 TAMD K6V2 -KillK6 TAMD K7V2 -KU1K7 TAMD K8V2 -Kill K8 TAMD K9V2 -KU1K9 TAMD K10V2 -Kill KIO BR RTN * ** * * * STOP AND RETURN * * * * * The following code has three entry points. STOP is reached if the current frame is a stop flag, it turns off synthesis and returns to the program. RTN is the general exit point for the UPDATE routine, it sets the Update flag and leaves the routine. * * * * * STOP TCX MODE ANDCM -LPC -Turn off synthesis ANDCM -ENA1 -Disable interrupt ANDCM -UNV -Go back to voiced for next word ORCM PCM -Enable PCM mode TMA TAMODE -Set mode per above setting CLA TASYN Write a zero to the DAC TCA #FA BACK IAC -Wait for 30 instruction cycles BR OUT BR BACK OUT TCX MODE -Disable PCM ANDCM -J PCM TMA TAMODE -Set mode per above setting BR SPEAK1 -Go back for next word * RTN TCX FLAGS -Set a flag indicating that ORCM Update_Flg -the parameters have been updated TCX MODE -Get mode TSTCM LPC -Are we speaking yet? BR RTN1 -Yes, reenable interrupt RETN -No, return for mode data RTN1 ORCM ENA1 -Reenable the interrupt TMA TAMODE BR SPEAK_LP -Go back to loop unl * * * * * D6 (654P74) SPEECH DECODING TABLES * * * * * * ENERGY DECODING TABLE * * * * * TBLEN BYTE #00,#01,#02,#03,#04,#05,#07 ) #0B BYTE #11,#1A,#29,#3F,#55,#70,#7F,#00 * * * * * * D6 PITCH DECODING TABLE * * * * * TBLPH BYTE #0C,#00 BYTE #10,#00 BYTE #10,#04 BYTE #10,#08 BYTE #11,#00 BYTE #11,#04 BYTE #11,#08 BYTE #11,#0C BYTE #12,#04 BYTE #12,#08 BYTE #12,#0C BYTE #13,#04 BYTE #13,#08 BYTE #14,#00 BYTE #14,#04 BYTE #14,#0C BYTE #15,#00 BYTE #15,#08 BYTE #15,#0C BYTE #16,#04 BYTE #16,#0C BYTE #17,#00 BYTE #17,#08 BYTE #18,#00 BYTE #18,#04 BYTE #18,#0C BYTE #19,#04 BYTE #19,#0C BYTE #1A,#04 BYTE #1A,#0C BYTE #1B,#04 BYTE #1B,#0C BYTE #1C,#04 BYTE #1C,#0C BYTE #1D,#04 BYTE #1D,#0C BYTE #1E,#04 BYTE #1F,#00 BYTE #1F,#08 BYTE #20,#00 BYTE #20,#0C BYTE #21,#04 BYTE #21,#0C BYTE #22,#08 BYTE #23,#00 BYTE #23,#0C BYTE #24,#08 BYTE #25,#00 BYTE #25,#0C BYTE #26,#08 BYTE #27,#04 BYTE #28,#00 BYTE #28,#0C BYTE #29,#08 BYTE #2A,#04 BYTE #2B,#00 BYTE #2B,#0C BYTE #2C,#08 BYTE #2D,#04 BYTE #2E,#04 BYTE #2F,#00 BYTE #30,#00 BYTE #30,#0C BYTE #31,#0C BYTE #32,#08 BYTE #33,#08 BYTE #34,#08 BYTE #35,#08 BYTE #36,#08 BYTE #37,#08 BYTE #38,#08 BYTE #39,#08 BYTE #3A,#08 BYTE #3B,#0C BYTE #3C,#0C BYTE #3D,#0C BYTE #3F,#00 BYTE #40,#04 BYTE #41,#04 BYTE #42,#08 BYTE #43,#0C BYTE #45,#00 BYTE #46,#04 BYTE #47,#08 BYTE #49,#00 BYTE #4A,#04 BYTE #4B,#0C BYTE #4D,#00 BYTE #4E,#08 BYTE #50,#00 BYTE #51,#04 BYTE #52,#0C BYTE #54,#08 BYTE #56,#00 BYTE #57,#08 BYTE #59,#04 BYTE #5A,#0C BYTE #5C,#08 BYTE #5E,#04 BYTE #60,#00 BYTE #61,#0C BYTE #63,#08 BYTE #65,#04 BYTE #67,#04 BYTE #69,#00 BYTE #6B,#00 BYTE #6D,#00 BYTE #6F,#00 BYTE #71,#00 BYTE #73,#04 BYTE #75,#04 BYTE #77,#08 BYTE #79,#0C BYTE #7C,#00 BYTE #7E,#04 BYTE #80,#08 BYTE #82,#0C BYTE #85,#04 BYTE #87,#0C BYTE #8A,#04 BYTE #8C,#0C BYTE #8F,#08 BYTE #92,#00 BYTE #94,#0C BYTE #97,#08 BYTE #9A,#04 BYTE #9D,#00 BYTE #A0,#00 * * * * * * Kl DECODING TABLE * * * * * TBLK1 BYTE #81 , #00 BYTE #82, #04 BYTE #83, #04 BYTE #84,#08 BYTE #85,#0C BYTE #87,#00 BYTE #88,#04 BYTE #89,#0C BYTE #8B,#04 BYTE #8C,#0C BYTE #8E,#04 BYTE #90,#00 BYTE #91,#0C BYTE #93,#08 BYTE #95,#08 BYTE #97,#04 BYTE #99,#08 BYTE #9B,#08 BYTE #9D,#08 BYTE #9F,#0C BYTE #A2,#00 BYTE #A4,#04 BYTE #A6,#0C BYTE #A9,#04 BYTE #AB,#08 BYTE #AE,#00 BYTE #B0,#0C BYTE #B3,#08 BYTE #B6,#04 BYTE #B9,#00 BYTE #BC,#00 BYTE #BF,#04 BYTE #C2,#04 BYTE #C5,#08 BYTE #C8,#0C BYTE #CC,#04 BYTE #CF,#0C BYTE #D3,#08 BYTE #D7,#08 BYTE #DB,#04 BYTE #DF,#04 BYTE #E3,#08 BYTE #E7,#0C BYTE #EC,#00 BYTE #F0,#04 BYTE #F4,#0C BYTE #F9,#0C BYTE #FE,#0C BYTE #04,#04 BYTE #09,#0C BYTE #0F,#04 BYTE #15,#08 BYTE # 1C,#08 BYTE #23,#08 BYTE #2A,#0C BYTE #32, #08 BYTE #3A,#08 BYTE #42,#0C BYTE #4B,#08 BYTE #54,#00 BYTE #5C,#04 BYTE #65,#00 BYTE #6E,#00 BYTE #78,#08 * * * * * * K2 DECODING TABLE * * * * * TBLK2 BYTE #8A,#0( BYTE #98,#00 BYTE #A3,#0C BYTE #AD,#0C BYTE #B4,#08 BYTE #BA,#08 BYTE #C0,#00 BYTE #C5,#00 BYTE #C9,#0C BYTE #CE,#04 BYTE #D2,#0C BYTE #D6,#0C BYTE #DA,#0C BYTE #DE,#08 BYTE #E2,#00 BYTE #E5,#0C BYTE #E9,#04 BYTE #EC,#0C BYTE #F0,#00 BYTE #F3,#04 BYTE #F6,#08 BYTE #F9,#0C BYTE #FD,#00 BYTE #00,#00 BYTE #03,#04 BYTE #06, #04 BYTE #09,#04 BYTE #0C,#04 BYTE #0F,#04 BYTE # 12, #08 BYTE # 15, #08 BYTE #18, #08 BYTE #1B,#08 BYTE #1E,#08 BYTE #21,#08 BYTE #24,#0C BYTE #27,#0C BYTE #2A,#0C BYTE #2D,#0C BYTE #30,#0C BYTE #34,#00 BYTE #37,#00 BYTE #3A,#04 BYTE #3D,#00 BYTE #40,#00 BYTE #43,#00 BYTE #46,#00 BYTE #49,#00 BYTE #4C,#00 BYTE #4F,#04 BYTE #52,#04 BYTE #55,#04 BYTE #58,#04 BYTE #5B,#04 BYTE #5E,#00 BYTE #61,#00 BYTE #63,#0C BYTE #66,#08 BYTE #69,#04 BYTE #6C,#00 BYTE #6F,#00 BYTE #72,#00 BYTE #76,#04 BYTE #7C,#00 ***** * K3 DECODING TABLE ***** TBLK3 BYTE #8B BYTE #9A BYTE #A2 BYTE #A9 BYTE #AF BYTE #B5 BYTE #BB BYTE #C0 BYTE #C5 BYTE #CA BYTE #CF BYTE #D4 BYTE #D9 BYTE #DE BYTE #E2 BYTE #E7 BYTE #EC BYTE #F1 BYTE #F6 BYTE #FB BYTE #01 BYTE #07 BYTE #0D BYTE #14 BYTE #1A BYTE #22 BYTE #29 BYTE #32 BYTE #3B BYTE #45 BYTE #53 BYTE #6D ***** * K4 DECODING TABLE * **** TBLK4 BYTE #94 BYTE #B0 BYTE #C2 BYTE #CB BYTE #D3 BYTE #D9 BYTE #DF BYTE #E5 BYTE #EA BYTE #EF BYTE #F4 BYTE #F9 BYTE #FE BYTE #03 BYTE #07 BYTE #0C BYTE #11 BYTE #15 BYTE #1A BYTE #1F BYTE #24 BYTE #29 BYTE #2E BYTE #33 BYTE #38 BYTE #3E BYTE #44 BYTE #4B BYTE #53 BYTE #5A BYTE #64 BYTE #74 ***** * K5 DECODING TABLE ***** TBLK5 BYTE #A3 BYTE #C5 BYTE #D4 BYTE #E0 BYTE #EA BYTE #F3 BYTE #FC BYTE #04 BYTE #0C BYTE #15 BYTE #1E BYTE #27 BYTE #31 BYTE #3D BYTE #4C BYTE #66 ***** * K6 DECODING TABLE ***** TBLK6 BYTE #AA BYTE #D7 BYTE #E7 BYTE #F2 BYTE #FC BYTE #05 BYTE #0D BYTE #14 BYTE #1C BYTE #24 BYTE #2D BYTE #36 BYTE #40 BYTE #4A BYTE #55 BYTE #6A ***** * K7 DECODING TABLE * * * * * TBLK7 BYTE #A3 BYTE #C8 BYTE #D7 BYTE #E3 BYTE #ED BYTE #F5 BYTE #FD BYTE #05 BYTE #0D BYTE #14 BYTE #1D BYTE #26 BYTE #31 BYTE #3C BYTE #4B BYTE #67 * **** * K8 DECODING TABLE * * * * * TBLK8 BYTE #C5 BYTE #E4 BYTE #F6 BYTE #05 BYTE #14 BYTE #27 BYTE #3E BYTE #58 ** *** * K9 DECODING TABLE * **** TBLK9 BYTE #B9 BYTE #DC BYTE #EC BYTE #F9 BYTE #04 BYTE #10 BYTE #1F BYTE #45 ***** * KIO DECODING TABLE * ** ** TBLK10 BYTE #C3 BYTE #E6 BYTE #F3 BYTE #FD MISSING UPON TIME OF PUBLICAΗON APPENDIX B Title: SPEECH AND SOUND SYNTHESIZNG Applicant: Hasbro, Inc. .LINKLIST ;; reserved for x2s.exe used only .SYMBOLS ;; reversed for SICE.EXE used SPC40A: EQU 1 SystemClock: EQU 3579545 .PAGEO ;; defined zero pages registers (VARIABLES) .ORG 80H R_IntFlags: DS 1 ;; Defined the interrupt enable flags reg ister R_IntTempReg: DS 1 ;; Reversed one byte for temparity store interrupt status .Include Hardware. inn ;; include all hardware informations .Include Adpcm.Inh ;; include header file to ;; located variables and definitions .Include Io.Inh ;; include io object header file .CODE ;; change back to program section .ORG OOH ;; put any data to the locate OOh at CODE section DB FFH ;; to avoid the bug of AD2500 assembler .ORG 600H ;; skip the area of test program used Reset: LDX #FFH ;; Initial the stack pointer TXS LDX #80H ;; Clear all registers LDA #00H L_ClearRamLoop : STA 07FH,X ;; Clear the register DEX BNE L_ClearRamLoop %Init_Speech ;; Macro to initial the object 'ADPCM' %IoPowerUpInitial ;; Initial the I/ O object after power up reset LDA R_IntFlags ;; initial interrupt control port STA P nts CLI ;; turn on the interrupt service LDX #DS_Test ;; play back the sentence 'Test' JSR F_PlaySentence L_MainLoop: JSR F_ServiceAdpcm ;; Service routine to service sentence player JSR F_IoService ;; Serivce routine to service KeyScan JSR F_Main JMP L_MainLoop * ** ******** * * ***** ****** ** * * ******* * ** , ;/ ;/* Main Object . ************************************** , F_Main: %GetCh BCC L_NoKeyIn AND #%00000011 TAX JMP F_PlaySentence L_NoKeyIn: RTS Irq: PHA ;; Store the Ace to stack TXA PHA ;; Store the Xreg to stack LDA PJnts ;; Read back the interupt status STA R_IntTempReg ;; Temparity store to a register EOR #%00111111 ;; Just clear the active interrupt sources AND RJntFlags STA PJnts ;; disable the interrupe which is actived LDA RJntFlags STA PJnts ;; Re-enable interrupt sources LDA RJntTempReg AND #%00100000 ;; Check If TimerA interrupt is actived BEQ L_NotTimerAInt JSR F_SpeechIntRoutine ;; If TimerA interrupt, service ADPCM L NotTimerAInt: LDA RJntTempReg AND #TimeBase500Hz ;; Test key debounce interrupt BEQ L_NotTimeBase500Hz %IntDeb ounce L NotTimeBase500Hz: PLA ;; restore X, A registers TAX PLA RTI Return the interrupt routine Nmi: RTI ;— Speech service routine ;— Speech Data Fetch and Pointer update F_SpeechIntRoutine: Ida R_ADPCMFlags and #D_SpeechEnable+D_RampUpFlag+D_RampDownFlag bne L_ADPCM_Active? rts L_ADPCM_Active?: and #D_RampUpFlag+D_RampDownFlag beq L_NormalSpeech? ldx RJSpeechData ;Sent current Data stx PJDacl stx PJ}ac2 and #DJ^ampUpFlag bne L_RampUp? ;/* RampDown */ ;After RampDown, close speech cpx #0 beq L_EndSpeechPlay LJ-.ower?: dec R_SpeechData rts LJRampUp?: cpx #80H beq L_EndRampUp? ; After RampUp, Go on Speech bcs L_Lower? inc RJSpeechData rts L_EndRampUp? : Ida R_ADPCMFlags and # . NOT. D_Ramp Up Flag sta R_ADPCMFlags rts L_NormalSpeech?: Ida RJSpeechData sta PJDacl ;output current DATA to hardware port sta PJDac2 ; output current DATA to hardware port Ida R.ADPCMFlags and #D_MuteFlag ;Test Playing Mute ? beq LJMotMute ;if not play Mute, play ADPCM ;/* if mute status is playing, DPTR will be length */ Ida R_SpeechDPTR bne LJDecreaseLower Ida R_SpeechDPTR+l beq L_EndSpeechPlay ;if length = 0, end playing dec R_SpeechDPTR+l LJDecreaseLower: dec RJSpeechDPTR RTS ;return from calling L_EndSpeechPlay: Ida RJntFlags and #. NOT. (Timer AEnable) sta RJntFlags sta PJnts Ida R_ADPCMFlags and #.NOT. (D_SpeechEnable+D_RampDownFlag) ssttaa R_ADPCMFlags RTS L_NotMute: clc ;clear carry flag for First nibble play Ida R_ADPCMFlags ;Change nibble status for ADPCM eor #D_LowNibbleFlag sta R_ADPCMFlags and #D_LowNibbleFlag bne L_FirstNibble ;/* Process second nibble, increase DPTR */ Ida R_SpeechDPTR+2 sta P_BankSel ;setup bank ldx #0 Ida (R_SpeechDPTR,X);Read encoded data from memory tax inc R_SpeechDPTR bne L_CheckOverBank inc R_SpeechDPTR+l bne L_SecondNibble ;always jump L_CheckOverBank: Ida R_SpeechDPTR cmp #F0H bne L_SecondNibble Ida R_SρeechDPTR+l eor #7FH and #7FH bne L_SecondNibble sta R_SpeechDPTR Ida #80H sta R_SpeechDPTR+l inc R_SpeechDPTR+2 Ida R_SpeechDPTR+2 cmp #DJ.astPage bne L_NormalPage Ida #D_LastPageStart sta R_SpeechDPTR+l L_NormalPage : L_SecondNibble : txa sec ;set carry flag for second nibble play bcs L_PlayHighNibble L_FirstNibble: ;/* Process first nibble, read encoded data */ Ida R_SpeechDPTR+2 sta P_BankSel ;setup bank ldx #0 Ida (R_SpeechDPTR,X);Read encoded data from memory bcc LJ-owerNibble LJPlayHighNibble: ror A ror A ror A ror A L_LowerNibble: ror A .**** * *** * *** *** **** *** * ** * ** * ** * * *** **** ***** ** * * ** ****** **** ** *** * **** * * * ** ;* Decoding new speech data from current data and encoded code by ADPCM * ;* UAAAAAAAAAAAAi UAAAAAAAAAAAAAAAA<:<-- the slope Jable is * ;* 3encoded dataAAAAA>3 3-bit adaptive 3 UA<: ;* AAAAAAAAAAAAAU 3 3 Quantizer AAA>3+AAAA> next new * ;* already fetch 3 3 look-up table 3 AAU speech data ;* from rom into ACC 3 AAAAAAAAAAAAAAAAAU Λ 3 Λ 3 update 3 UAAAAAAAAAAi 3 * current 3 3 Adaptive 3 3 * adaptive AAAAA>3 status 3 3 current speech data status index 3 index 3 AAAAA "SpeechData." * for next Quantizer AAAAAAAAAAAU<— variable "Qindex" * used * **************************************************************************** input Acc:encoded data, caπy:0-> plus, l-> minlus and #%00000111 ora RJ^Index ;set Quantizer table base on Qindex bne L_NotEnd bcs L_EndSpeechPlay ;End code detected, End playing L NotEnd: tax Ida TJSfextStep,X sta R_QIndex ;Update Quantizer index Ida T_SlopeTable,X ;gets Quantizer output bcc L_slope_up ;decide plus or milus eor #$ff ;if sign == milus adc RJSpeechData ;SpeechData = SpeechData QJevel bcs LJn_range ; = SpeechData + -QJevel + 1 Ida #0 ; if < 0 then set to 0 bcc L_in_range L_slope_up: adc R_SpeechData ;if sign == plus, SpeechData += QJevel bcc LJn_range Ida #Sff ; if >255 then set to 255 LJn_range: sta RJSpeechData rts ******************************************************************************* * ADPCM Object Maintanence Routines * ******************************************************************************* — prepare sentence to speech — - input: serial number of sentence in X -> 0, 1, 2, 3 FJ^laySentence: ;/* initial synchronous index registers */ TXA CLC ROL A TAX Ida T_WordTable,X sta R_SentenceDPTR Ida T_WordTable+l ,X sta R SentenceDPTR+1 — prepare Word To Speech - input: Word to speech table address, higher byte into X, lower byte into Ace ; and this program will transfer it into dptπSpeechToWord, and gets the ; ADPCM start and end address of first word into SpeechDPTR and SpeechEnd, respectively, and goto start the interrupt.... Datas of Speech-To-Word table arragement as following: $00-$3f -> indicate number of word $40-$fd -> reserve $fe,length(lower),length(higher) -> mute word with length $ff -> end of Speech-To-Word — Use variable TempRegO LJServiceSentencePlay: ldx #0 Ida (R_SentenceDPTR,X) ;get byte from sentence table cmp #D_EndSentence bne L_GoOnPlay ;if not end-of-sentence ;/* End-of-sentence */ sei Ida R_ADPCMFlags and # . NOT. D_SentenceEnable ora #D_RampDownFlag+D_SpeechEnable sta R.ADPCMFlags Ida T_8KHzTable sta P_TmAL Ida T_8KHzTable+l sta P_TmAH Ida RJntFlags ora #TimerAEnable sta RJntFlags sta PJnts cli rts L_GoOnPlay: tax sei Ida R_ADPCMFlags ;setup Sentence active ora #D_SentenceEnable sta R_ADPCMFlags inc R_SentenceDPTR ;get next byte bne LJMotOverflowO? inc R_SentenceDPTR+ 1 L_NotOverflow0?: cpx #D_MuteWord bne F_PlaySpeech ;if normal speech ;/* Mute word playing */ ldx #0 Ida (R_SentenceDPTR,X) sta R_SρeechDPTR ;put lower of length inc R_SentenceDPTR ;get next byte bne L_NotOverflowl? inc R_SentenceDPTR+l LJMotOverflowl?: Ida (R_SentenceDPTR,X) sta R_SpeechDPTR+l inc R_SentenceDPTR ;get next byte bne L_NotOverflow2? inc R_SentenceDPTR+l L_NotOverflow2?: F_PlayMute: sei Ida T_8KHzTable sta PJTmAL Ida T_8KHzTable+l sta PJTmAH Ida R_ADPCMFlags ora #D_MuteFlag sta R_ADPCMFlags sec bcs LJnitPlaySpeech F_PlaySpeech: sei ; disable interrupt Ida T_SpeechLowAddressTable,X ;get start address sta R_SpeechDPTR Ida T_SpeechHighAddressTable,X sta R_SpeechDPTR+l Ida T_SpeechBankAddressTable,X sta R_SpeechDPTR+2 txa ;Index *= 2 clc rol A tax Ida T_SampleRateTable,X ;get sample fr< sta P_TmAL Ida T_SampleRateTable+ 1 ,X sta P_TmAH Ida R.ADPCMFlags and #.NOT.D_MuteFlag ;Speech Mode sta R_ADPCMFlags LJnitPlaySpeech: Ida #0 sta R_Q Index Ida R_ADPCMFlags ora #D_SpeechEnable+D_RampUpFlag and # .NOT. D J,o wNibbleFlag sta R_ADPCMFlags Ida RJntFlags ora #TimerAEnable sta R_IntFlags sta P_Ints cli ;enable interrupt rts ; Process Word to speech F_ServiceAdpcm: Ida R_ADPCMFlags and #D_SentenceEnable beq L_SentencePlayerDisable Ida R_ADPCMFlags and #D_SpeechEnable bne L_StillPlaying jmp L_ServiceSentencePlay L_StillPlaying: L_SentencePlayerDisable: rts ******************************************************************************* * Rom Table Area * ** * **** * * * ********** **** * * ***** * **** * ********** * *************************** * * * * IFNDEF T_SlopeTable T_SlopeTable: db 0, 1 , 2, 4, 6, 8, 12, 16 ;ADPCM w/ repeat db 1, 3, 5, 9, 13, 17,25, 33 ; db 2, 5, 8, 14, 20, 26, 38, 50 db 3, 7, 11, 19, 27, 35,41, 67 db 4, 9, 14, 24, 34, 44, 64, 84 db 5, 11, 17,29,41,53,77,111 db 6, 13,20,34,48,62,90,118 db 7, 15,23,39,55,71,103,125 ENDIF IFNDEF T_NextStep ; -1,-1, 0, 0, 2, 2, 3, 4 ; Step transition table T_NextStep: db $00,$00,$00,$00,$10,$10,$18,$20 ;0 - 7 db $00,$00,$08,$08,$18,$18,$20,$28 ;8 - 15 db $08,$08,$10,$10,$20,$20,$28,$30 ;16 - 23 db $10,$10,$18,$18,$28,$28,$30,$38 ;24 - 31 db S18,$18,$20,$20,$30,$30,$38,$38 ;32 - 39 db $20,$20,$28,$28,$38,$38,$38,$38 ;40 - 47 db $28,$28,$30,$30,$38,$38,$38,$38 ;48 - 55 db $30,$30,$38,$38,$38,$38,$38,$38 ;56 - 63 ENDIF T_SampleRateTable: %LoadSampleRate 8015 ;for speech number 0 %LoadSampleRate 8015 ;for speech number 1 %LoadSampleRate 8015 ;for speech number 2 %LoadSampleRate 8015 ;for speech number 3 %LoadSampleRate 8015 ;for speech number 4 %LoadSampleRate 8015 ;for speech number 5 %LoadSampleRate 8015 ;for speech number 6 %LoadSampleRate 8015 ;for speech number 7 %LoadSampleRate 8015 ;for speech number 8 %LoadSampleRate 8015 ;for speech number 9 T_8KHzTable: %LoadSampleRate 10000 ;for mute reference .Include StoWord.Tab .Include SpechAdr.Tab .Include Io.Asm ;; Included the object body 'IO' .ORG 1000H DB 'PEND',0 ;; the end of mark for splinker.exe ;; to identify the end of program .ORG 7FFAH DW Nmi DW Reset DW Irq .ORG FFFAH DW Nmi DW Reset DW Irq APPENDIX C Title: SPEECH AND SOUND SYNTHESIZNG Applicant: Hasbro, Inc. * Modified D6 speech Engine for use with Speech Data in Sunplus * Uses External GETS with 4-line interface code /hardware RWJ 1/30/97 ************* * *********************************** * Speak Utterance - Phrase number in A register **** *************************** **** ***:* * ** * * **** ********** ** * * **** speak 1 retn SPEAK INTGR * CLA -Kill Kl 1 and K12 parameters TAMD Kl 1 TAMD K12 TAMD FLAGS -Init flags for speech CLA -Load C2 parameter ACAAC C2_Value TAMD C2 CLA -Load Cl parameter ACAAC Cl /alue TAMD Cl * * * ** * Now we give an initial value to the Pitch in case the utterance starts * with a silent frame. ***** ACAAC #0C TAMD PHV1 TAMD PHV2 * * * * * * Now we preload the first two frames. * * * * * CALL UPDATE -Load first frame CALL UPDATE -Load 2nd frame * * * * * * Now we give some values to the Timer and Prescaler so that we can do a * valid interpolation on the first call to INTP. Then I do the first * call to INTP to preload the first valid interpolation. * * * ** TCA PSVALue -Initialize prescale TAPSC TCA #7F -Pretend there was a previous update TAMD TIMER TCA #FF -Set timer to max value to... TATM -...disable interpolation CALL INTP -Do first interpolation ***** * Now we enable the synthesizer for speech ***** TCX MODE -Turn on LPC synthesizer ORCM LPC_ON TMA TAMODE RETI -Reset interrupt pending latch ORCM INT_ON -Enable interrupt TMA TAMODE ***** * Now we loop until the utterance is complete. When the utterance is * finished, the routine UPDATE will execute a RETN instruction which * will exit this routine. In the mean time, this loop will poll the * Timer register and update the frame whenever it underflows. ** * * * SPEAK_LP TCX FLAGS TSTCM Update_Flg -Update already done? BR SPEAK JLP -yes, loop TCX TIMER -Get old timer TMA register valu TAB -into B register TTMA -Get new timer register SARA -value and scale it. TAM -Store new value XBA -Exchange new and old values SBAAN -Subtract new from old BR UPDATE -If underflowed, do an update TMA -Get new timer value again. ANEC 0 -Is it about to underflow? BR SPEAKJ.P no, loop again BR UPDATE yes, do update now ***** * INTERPOLATION ROUTINE * **** First we need to get the current value of the timer register and store it away. It will be divided by two with the SARA instruction so that the most significant bit is guaranteed to be zero so that it will always be interpreted as a positive number during the interpolation. * *** * INTP TTMA -Get timer register contents SARA -shift to make positive TAMD SCALE -and store it * * * * * * Next we need to see if the frame type has changed between voiced and * unvoiced frames. If it has, we do not want to interpolate between * them; we just want to use the current frame values until we have two * frames of the same type to interpolate between. * * * * * TCX FLAGS -Test to see if Interpolation TSTCM Intjnh -is inhibited BR NOINT -yes, use inhibit code BR INTPCH -yes, use inhibit code * * * * * * The following code is reached if interpolation is inhibited. It sets * the stored timer value to #7F which effectively forces the interpolation * to yield the old values for the working values, thus effectively disabling * interpolation. * * * * * NOINT TCA #7F -Set Scale factor to TAMD SCALE -highest value * * If the new frame has a voicing different from the last frame, * we want to zero the energy until the Unvoiced bit in the mode * register is changed and the K paramaters are all to the current * values. We therefore check in this section of code to see if * the frame voicing is different from the setting in MODE. If it * is, we zero the energy until after MODE is modified. TCX FLAGS TSTCM Unv_Flg2 -Is new frame unvoiced? BR Uv -Yes, go to unvoiced branch TCX MODE -New frame is voiced TSTCM UNV -Has mode been changed to voiced? BR ClrEN -No, clear the energy Uv TCX MODE -New frame is unvoiced TSTCM UNV -Has mode been changed to unvo BR INTPCH -Yes, no action required * ClrEN CLA -Zero Energy during update TAMD EN BR INTPCH * **** * Interpolate Pitch and store the result in the working register ** * * * INTPCH INTGR -Need Integer mode for pitch TCX PHV2 -Combine pitch and fractional TMAIX -pitch and leave in SALA4 -the B register AMAAC IXC TAB TMAIX -Combine current pitch and SALA4 -current fractional pitch AMAAC -and leave in A register SBAAN -(Pcurrent - Pnew) TCX SCALE AXMA -(Pcurrent - Pnew) * Timer ABAAC -Pnew + (Pcurrent - Pnew)* Timer SALA -LSB must be 0 to address excitation table TASYN -Write to pitch register EXTSG -Allow negative K parameters ***** Interpolate Energy and store the result in the working register ** * * * TCX ENV2 -Combine energy and fractional TMAIX energy and leave in SALA4 the B register AMAAC IXC TAB TMAIX -Combine current energy and SALA4 -current fractional energy & AMAAC -leave in A register SBAAN -(Ecurrent - Enew) TCX SCALE AXMA -(Ecurrent - Enew) * Timer ABAAC -Enew + (Ecurrent - Enew) * Timer TAMD EN_TEMP -Store Energy til mode is switched TAMD EN EXTSG -Allow K parameters to be negative ** * * * Interpolate Kl and store the result inthe working Kl register * * * * * TCX K1V2 -Combine New Kl and New TMAIX -fractional Kl and SALA4 -leave in the B register AMAAC IXC TAB TMAIX -Combine current Kl and SALA4 -current fractional Kl and AMAAC -leave in the A register SBAAN -(Kl current - Klnew) TCX SCALE AXMA -(Kl current - Klnew) * Timer ABAAC -Klnew+(Klcurrent-Klnew) * Timer TAMD Kl -Load interpolated value to synth * * * * * Interpolate K2 and store the result in the working K2 register * * * * * TCX K2V2 -Combine New K2 and New TMAIX -fractional K2 and SALA4 -leave in the B register AMAAC IXC TAB TMAIX -Combine current K2 and SALA4 -current fractional K2 and AMAAC -leave in the A register SBAAN -(K2current - K2new) TCX SCALE AXMA -(K2 current - K2new) * Timer ABAAC -K2new+(K2current-K2new) * Timer TAMD K2 -Load interpolated value to synth * * * * * Interpolate K3 and store the result in the working K3 register ***** TCX K3V2 -Combine New K3 and New TMAIX -fractional K3 and SALA4 -leave in the B register TAB TMAIX -Combine current K3 and SALA4 -current fractional K3 and SBAAN -(K3current - K3new) TCX SCALE AXMA -(K3current - K3new) * Timer ABAAC -K3new+(K3curτent-K3new) * Timer TAMD K3 -Load interpolated value to synth ***** Interpolate K4 and store the result in the working K4 register ***** TCX K4V2 -Combine New K4 and New TMAIX -fractional K4 and SALA4 -leave in the B register TAB TMAIX -Combine current K4 and SALA4 -current fractional K4 and SBAAN -(K4current - K4new) TCX SCALE AXMA -(K4current - K4new) * Timer ABAAC -K4new+(K4current-K4new) * Timer TAMD K4 -Load interpolated value to synth ***** * Interpolate K5 and store the result in the working K5 register ***** TCX K5V2 -Put New K5 (adjusted to TMAIX •12 bits) in B register SALA4 TAB TMAIX -Put Current K5 (adjusted to SALA4 -12 bits) in A register SBAAN -(K5current - K5new) TCX SCALE AXMA -(K5current - K5new) * Timer ABAAC -K5new+(K5current-K5new) * Timer TAMD K5 -Load interpolated value to synth ***** * Interpolate K6 and store the result in the working K6 register ** * ** TCX K6V2 -Put New K6 (adjusted to TMAIX 12 bits) in B register SALA4 TAB TMAIX -Put Current K6 (adjusted to SALA4 -12 bits) in A register SBAAN -(K6 current - K6new) TCX SCALE AXMA -(Kδcurrent - K6new) * Timer ABAAC -K6new+(K6current-K6new) * Timer TAMD K6 -Load interpolated value to synth ** * * * Interpolate K7 and store the result in the working K7 register ***** TCX K7V2 -Put New K7 (adjusted to TMAIX •12 bits) in B register SALA4 TAB TMAIX -Put Current K7 (adjusted to SALA4 -12 bits) in A register SBAAN -(K7 current - K7new) TCX SCALE AXMA -(K7 current - K7new) * Timer ABAAC -K7new+(K7current-K7new) * Timer TAMD K7 -Load interpolated value to synth Interpolate K8 and store the result in the working K8 register TCX K8V2 --PPuutt NNeeww KK88 ((aaddjjuusstted to TMAIX -12 bits) in B register SALA4 TAB TMAIX -Put Current K8 (adjusted to SALA4 -12 bits) in A register SBAAN -(Kδcurrent - K8new) TCX SCALE AXMA -(K8current - K8new) * Timer ABAAC -K8new+(K8current-K8new) * Timer TAMD K8 -Load interpolated value to synth Interpolate K9 and store the result in the working K9 register * * * * TCX K9V2 -Put New K9 (adjusted to TMAIX -12 bits) in B register SALA4 TAB TMAIX -Put Current K9 (adjusted to SALA4 - 12 bits) in A register SBAAN -(K9 current - K9new) TCX SCALE AXMA -(K9current - K9new) * Timer ABAAC -K9new+(K9current-K9new) * Timer TAMD K9 -Load interpolated value to synth Interpolate KIO and store the result in the working KIO register * TCX K10V2 --PPuutt NNeeww KKIIOO ((aaddjjuusted to TMAIX -12 bits) in B register SALA4 TAB TMAIX -Put Current KIO (adjusted to SALA4 - 12 bits) in A register SBAAN -(KlOcurrent - KlOnew) TCX SCALE AXMA -(KlOcurrent - KlOnew) * Timer ABAAC -K10new+(K10current-K10new) * Timer TAMD KIO -Load interpolated value to synth * * * * * * Kl 1 and K12 are not needed for LPC 10, so I have taken them out. * * * * * * * * * * * Set voiced /unvoiced mode according to current frame type. This is * done in a two step fashion: first the value in the MODE register * is adjusted with an AND or OR operation, then the result is written * to the synthesizer with a TAMODE operation. We do it this way to keep * a copy of the current status of the synthesizer mode at all time. * * * * * STMODE INTGR -Back to integer mode TCX FLAGS ANDCM ~Update_Flg -Signal that interp done TSTCM Unv_Flg2 -Is current frame unvoiced? BR SETUV -Yes, set mode to unvoiced TCX MODE -No, set mode to voiced ANDCM -LPCJJNV TMA TAMODE * * TMAD ENJTEMP -Change Energy parameter.. * TAMD EN -...to correct value * RETI -Return from interrupt RETN -Return from first call SETUV TCX MODE -Current frame is unvoiced, so ORCM LPCJJNV -Set mode to unvoiced. TMA TAMODE TMAD ENJTEMP -Change Energy parameter... * TAMD EN -...to correct value. * RETI -Return from interrupt RETN -Return from first call * * * * * * Update the parameters for a new frame * * * * * * * * * * First we inhibit the operation of the interpolation routine. * * * * * UPDATE TCX MODE ANDCM -INT_ON TMA TAMODE * * * * * * To prevent double updates, if the stored value of the timer register * is zero, then we need to change it to #7F. If we do not do this, than * the polling routine will discover an underflow and call Update a second * time. * * * * * TCX TIMER -Get stored value TMA -of Timer into A ANEC 0 -Is it zero? BR UPDTOO -no, do nothing TCA #7F -yes, replace value TAM * * * * * * First we need to test to see if a stop frame was encountered on the last * pass through the routine. If the previous frame was a stop frame, we * need to turn off the synthesizer and stop speaking. * * * * * UPDTOO TCX FLAGS TSTCM STOPFLAG -Was stop frame encountered BR STOP -yes, stop speaking * * * * * * Transfer the state of the previous frame to the Unvoiced flag (Current) * and set the mode mirror buffer to reflect the voicing of the previous frame. * * * * * TSTCM Unv_Flgl -Was previous frame unvoiced? BR SUNVL -Yes, set current frame unvoiced ANDCM #7F -No, set current frame voiced BR TSIL SUNVL ORCM Unv_Flg2 -Set current frame unvoiced. * * * * * * Transfer the state of the previous frame to the Silence flag (Current) * and set the mode mirror buffer * * * * * TSIL TSTCM Sil_Flgl -Was previous frame silent? BR SSIL -Yes, set current frame silen ANDCM ~Sil_Flg2 -No, set current frame not silent BR ZROFLG SSIL ORCM Sil Flg2 -Set current frame unvoiced. * * * * * * Reset the Repeat Flag, Silence Flag, Unvoiced Flag, and Interpolation * Inhibit flag so that new values can be loaded in this routine. * * * * * ZROFLG TCX FLAGS ANDCM #C5 ***** * Transfer the current new frame parameters into the storage location used * for the current frame parameters. * * * * * TCX ENV2 -Transfer new frame energy TMAIX -to current frame location TAMD ENV1 TMAIX -Transfer new fractional energy IXC -to current frame location TAMIX -PITCH TMAIX -Transfer new frame pitch TAMD PHV1 -to current frame location TMAIX -Transfer new fractional pitch IXC -to current frame location TAMIX -Kl TMAIX -Transfer new frame Kl paramete TAMD K1V1 -to current frame location TMAIX -Transfer new fractional Kl par IXC -to current frame location TAMIX -K2 TMAIX -Transfer new frame K2 paramete TAMD K2V1 -to current frame location TMAIX -Transfer new fractional parame IXC -to current frame location TAMIX -K3— - TMAIX -Transfer new frame K3 paramete TAMIX -K4 TMAIX -Transfer new frame K4 paramete TAMIX -K5 TMAIX -Transfer new frame K5 paramete TAMIX -to current frame location -K6— - TMAIX -Transfer new frame K6 paramete TAMIX -to current frame location * K7 TMAIX -Transfer new frame K7 paramete TAMIX -to current frame location * K8 TMAIX -Transfer new frame K8 paramete TAMIX -to current frame location * K9 TMAIX -Transfer new frame K9 paramete TAMIX -to current frame location * KIO TMAIX -Transfer new frame KIO paramet TAMIX -to current frame location * * * * * * Kl 1 and K12 are not used in LPC 10 synthesis, so the code has been * commented out. * * * * * * Kl l * TMAIX -Transfer new frame Kl l paramet * TAMIX -to current frame location * K12 * TMAIX -Transfer new frame K12 paramet * TAMIX -to current frame location * * * * * * We have now discarded the "current" values by replacing it with the * "new" values. We now need to read in another frame of speech data and * used them as the new "new" values. * * * * * * ENERGY CLA TCX FLAGS call PrepGetPl call SPGET4 * GET EBITS -Get coded energy ANEC ESILENCE -Is it a silent frame? BR UPDTO -No, continue ORCM Sil_Flgl+IntJnh -Yes, set silence flag BR ZeroKs -zero K params * UPDTO ANEC ESTOP -Is it a stop frame? BR UPDT1 -No, continue ORCM STOPFLAG+Si Flgl+IntJnh yes, set flags BR ZeroKs -Zero Ks * UPDT1 ACAAC TBLEN -Add table offset to energy index LUAA -Get decoded energy TAMD ENV2 -Store the Energy in RAM * * * * * * If this is a silent frame, we are done with the update If the previous * frame was silent, the new frame should be spoken immediately with no * ramp up due to interpolation. * * * * * TCX FLAGS TSTCM SuAFlgl -Is this a silent frame? BR RTN -yes, exit * * * * * * A repeat frame will use the K parameter from the previous frame. If it * is, we need to set a flag. * * * * * UPDT2 call PrepGetPl call SPGET1 GET RBITS -Get the Repeat bit TSTCA #01 -Is this a repeat frame? BR SFLG1 -yes, set repeat flag BR UPDT3 SFLG1 ORCM R_FLAG -Set repeat flag * PITCH UPDT3 CLA call PrepGetPl call SPGET7 * GET 4 -C Get coded pitch * GET 3 -C Get coded pitch ANEC PUnVoiced -Is the frame unvoiced? BR UPDT3A -no, continue ORCM Unv_Flgl -yes, set unvoiced flag UPDT3A SALA -Double coded pitch and ACAAC TBLPH -add table offset to point to table LUAB -Get decoded pitch IAC LUAA -Get decoded fractional pitch TCX PHV2 -Store the pitch and fractional TBM -pitch in RAM IXC TAM * * * * * If the voicing has changed with the new frame, then we need to change * the voicing in the mode register. * * * * * TCX FLAGS TSTCM Uny gl -Is the new frame unvoiced? BR UPDT3B -yes, continue BR VOICE -no, go to voiced code * * * * * * The following code is reached if the new frame is unvoiced. We inspect * the flags to see if the previous frame was either silent or voiced. * If either condition applies, then we branch to code which inhibits * interpolation. * * * * * UPDT3B TSTCM Sil_Flg2 -Was the previous frame silent? BR UPDT5 -yes, inhibit interpolation TSTCM Unv_Flg2 -Was the previous frame unvoiced BR UPDT4 -yes, no need to change anything BR UPDT5 -no, inhibit interpolation * * * * * The following code is reached if the new frame is voiced. We inspect the * flags to see if the previous frame was also voiced. If it was not, we * need to inhibit interpolation. * * * * * VOICE TSTCM Unv_Flg2 -Was the previous frame voiced? BR UPDT5 -no, set no interpolation flag BR UPDT4 -yes, no need to change anything UPDT5 ORCM Intjnh -Inhibit interpolation * * * * * Now we test the repeat flag. If the new frame is a repeat frame, then * the current values are used for the K factors, so new values do not need * to be loaded and we can exit the routine now. * * * * * UPDT4 TSTCM R_FLAG -Is repeat flag set? BR RTN -yes, exit routine * * * * * * Now we need to load the "new" K factors (Kl through KIO). Each K * factor is a 12 bit value which will be stored in two bytes. The most * significant 8 bit in the first byte, and the least significant 4 bits * (called the fractional value) in the second byte. For K5 through K12, * the fractional part is assumed to be zero. Kl 1 and K12 are not used in * LPC synthesis, and the code loading them is commented out. A coded * factor is read into the A register. It is then converted to a pointer * to a table element which contains the uncoded factor. Since each table * element consists of two bytes, the conversion consists of doubling the * uncoded factor and adding the offset of the start of the table. The * uncoded factor is fetched and stored into RAM. * * * * * -Kl CLA call PrepGetPl call SPGET6 GET 4 -Get coded Kl GET 2 -Get coded Kl SALA -Convert it to a ACAAC TBLK1 pointer to table element LUAB -Fetch MSB of uncoded Kl IAC LUAA -Fetch fractional Kl TCX K1V2 TBM -Store uncoded Kl IXC TAM -Store fractional Kl -K2-— CLA call PrepGetPl call SPGET6 GET 4 - -Get coded K2 GET 2 -Get coded K2 SALA -Convert it to a ACAAC TBLK2 pointer to table element LUAB -Fetch MSB of uncoded K2 IAC LUAA -Fetch fractional K2 TCX K2V2 TBM -Store uncoded K2 IXC TAM -Store fractional K2 -K3 CLA call PrepGetPl call SPGET5 GET 4 -Get Index into K3 table GET 1 -Get Index into K3 table ACAAC TBLK3 -and add offset of table to it LUAA -Get uncoded K3 TAMD K3V2 -and store it in RAM -K4 CLA call PrepGetPl call SPGET5 GET 4 -Get Index into K4 table GET 1 -Get Index into K4 table ACAAC TBLK4 -and add offset of table to it LUAA -Get uncoded K4 TAMD K4V2 -and store it in RAM * * * * * * If this is a unvoiced frame, we only use four K factors, so we load * zeroes to the rest of the K factors. If this is a voiced frame, load * the rest of the uncoded factors. * * * * * TCX FLAGS TSTCM UnvJFlgl -Is this an unvoiced frame? BR UNVC -Yes, zero rest of factors * * * * * * The following code is executed if the current frame is voiced. Since * we assume that the fractional parameter is zero for the remaining K * factors, the table elements are only one byte long. The conversion to a * table pointer now consists of adding the offset of the start of the table. * * * * * -K5 CLA call PrepGetPl call SPGET4 GET K5BITS -Get Index into K5 table ACAAC TBLK5 -and add offset of table to it LUAA -Get uncoded K5 TAMD K5V2 -and store it in RAM ■ K6 CLA call PrepGetPl call SPGET4 GET K6BITS -Get Index into K6 table ACAAC TBLK6 -and add offset of table to i LUAA -Get uncoded K6 TAMD K6V2 -and store it in RAM -K7 CLA call PrepGetPl call SPGET4 GET K7BITS -Get Index into K7 table ACAAC TBLK7 -and add offset of table to i LUAA -Get uncoded K7 TAMD K7V2 -and store it in RAM -K8— - CLA call PrepGetPl call SPGET3 * GET K8BITS -Get Index into K8 table ACAAC TBLK8 -and add offset of table to i LUAA -Get uncoded K8 TAMD K8V2 -and store it in RAM * K9 CLA call PrepGetPl call SPGET3 GET K9BITS -Get Index into K9 table ACAAC TBLK9 -and add offset of table to i LUAA -Get uncoded K9 TAMD K9V2 -and store it in RAM * KIO CLA call PrepGetPl call SPGET3 GET K10BITS -Get Index into KIO table ACAAC TBLK10 -and add offset of table to i LUAA -Get uncoded KIO TAMD K10V2 -and store it in RAM * * * * * * Since Kl l and K12 are not used in LPCIO, the Kl l and K12 code is removed * * * * * BR RTN * * * * * * The following code is executed if the K parameters need to be cleared. * If the new frame is a stop frame or a silent frame, we clear all K * parameters and set energy to zero. If the new frame is an unvoiced * frame, then we need to zero out the unused upper K parameters. ***** ZeroKs CLA TAMD ENV2 -Kill Energy TAMD ENV2+1 TAMD K1V2 -KillKl TAMD K1V2+1 TAMD K2V2 -KillK2 TAMD K2V2+1 TAMD K3V2 -KiUK3 UNVC CLA TAMD K5V2 -KillK5 TAMD K6V2 -KL11K6 TAMD K7V2 -KillK7 TAMD K8V2 -KLUK8 TAMD K9V2 -KillK9 TAMD K10V2 -Kill KIO BR RTN * * * * * * STOP AND RETURN * * * ** The following code has three entry points. STOP is reached if the current frame is a stop flag, it turns off synthesis and returns to the program. RTN is the general exit point for the UPDATE routine, it sets the Update flag and leaves the routine. * * * * * STOP TCX MODE ANDCM -LPC -Turn off synthesis ANDCM -ENA1 -Disable interrupt ANDCM -UNV -Go back to voiced for next word ORCM PCM -Enable PCM mode TMA TAMODE -Set mode per above setting CLA TASYN Write a zero to the DAC TCA #FA BACK IAC -Wait for 30 instruction cycles BR OUT BR BACK OUT TCX MODE -Disable PCM ANDCM ~ PCM TMA TAMODE -Set mode per above setting BR SPEAK1 -Go back for next word * RTN TCX FLAGS -Set a flag indicating that ORCM Update_Flg -the parameters have been updated TCX MODE -Get mode TSTCM LPC -Are we speaking yet? BR RTN1 -Yes, reenable interrupt RETN -No, return for mode data * RTN1 ORCM ENA1 -Reenable the interrupt TMA TAMODE BR SPEAK ,P -Go back to loop list * * ** * * D6 (654P74) SPEECH DECODING TABLES * * * * * * ENERGY DECODING TABLE ***** TBLEN BYTE #00,#01,#02,#03,#04,#05,#07,#0B BYTE #11,#1A,#29,#3F,#55,#70,#7F,#00 *** * * * D6 PITCH DECODING TABLE ** * * * TBLPH BYTE #0C,#00 BYTE #10,#00 BYTE #10,#04 BYTE #10,#08 BYTE #11,#00 BYTE #11,#04 BYTE #11,#08 BYTE #11,#0C BYTE #12,#04 BYTE #12,#08 BYTE #12,#0C BYTE #13,#04 BYTE #13,#08 BYTE #14,#00 BYTE #14,#04 BYTE #14,#0C BYTE #15,#00 BYTE #15,#08 BYTE #15,#0C BYTE #16,#04 BYTE #16,#0C BYTE #17,#00 BYTE #17,#08 BYTE #18,#00 BYTE #18,#04 BYTE #18,#0C BYTE #19,#04 BYTE #19,#0C BYTE #1A,#04 BYTE #1A,#0C BYTE #1B,#04 BYTE #1B,#0C BYTE #1C,#04 BYTE #1C,#0C BYTE #1D,#04 BYTE #1D,#0C BYTE #1E,#04 BYTE #1F,#00 BYTE #1F,#08 BYTE #20,#00 BYTE #20,#0C BYTE #21,#04 BYTE #21,#0C BYTE #22,#08 BYTE #23,#00 BYTE #23,#0C BYTE #24,#08 BYTE #25,#00 BYTE #25,#0C BYTE #26,#08 BYTE #27,#04 BYTE #28,#00 BYTE #28,#0C BYTE #29,#08 BYTE #2A,#04 BYTE #2B,#00 BYTE #2B,#0C BYTE #2C,#08 BYTE #2D,#04 BYTE #2E,#04 BYTE #2F,#00 BYTE #30,#00 BYTE #30,#0C BYTE #31,#0C BYTE #32,#08 BYTE #33,#08 BYTE #34,#08 BYTE #35,#08 BYTE #36,#08 BYTE #37,#08 BYTE #38,#08 BYTE #39,#08 BYTE #3A,#08 BYTE #3B,#0C BYTE #3C,#0C BYTE #3D,#0C BYTE #3F,#00 BYTE #40,#04 BYTE #41,#04 BYTE #42,#08 BYTE #43,#0C BYTE #45,#00 BYTE #46,#04 BYTE #47,#08 BYTE #49,#00 BYTE #4A,#04 BYTE #4B,#0C BYTE #4D,#00 BYTE #4E,#08 BYTE #50,#00 BYTE #51,#04 BYTE #52,#0C BYTE #54,#08 BYTE #56,#00 BYTE #57,#08 BYTE #59,#04 BYTE #5A,#0C BYTE #5C,#08 BYTE #5E,#04 BYTE #60,#00 BYTE #61,#0C BYTE #63,#08 BYTE #65,#04 BYTE #67,#04 BYTE #69,#00 BYTE #6B,#00 BYTE #6D,#00 BYTE #6F,#00 BYTE #71,#00 BYTE #73,#04 BYTE #75,#04 BYTE #77,#08 BYTE #79,#0C BYTE #7C,#00 BYTE #7E,#04 BYTE #80,#08 BYTE #82,#0C BYTE #85,#04 BYTE #87,#0C BYTE #8A,#04 BYTE #8C,#0C BYTE #8F,#08 BYTE #92,#00 BYTE #94,#0C BYTE #97,#08 BYTE #9A,#04 BYTE #9D,#00 BYTE #A0,#00 * * * * * * Kl DECODING TABLE * * * * * TBLKl BYTE #81,#0( BYTE #82,#04 BYTE #83,#04 BYTE #84,#08 BYTE #85,#0C BYTE #87,#00 BYTE #88,#04 BYTE #89,#0C BYTE #8B,#04 BYTE #8C,#0C BYTE #8E,#04 BYTE #90,#00 BYTE #91,#0C BYTE #93,#08 BYTE #95,#08 BYTE #97,#04 BYTE #99,#08 BYTE #9B,#08 BYTE #9D,#08 BYTE #9F,#0C BYTE #A2,#00 BYTE #A4,#04 BYTE #A6,#0C BYTE #A9,#04 BYTE #AB,#08 BYTE #AE,#00 BYTE #B0,#0C BYTE #B3,#08 BYTE #B6,#04 BYTE #B9,#00 BYTE #BC,#00 BYTE #BF,#04 BYTE #C2,#04 BYTE #C5,#08 BYTE #C8,#0C BYTE #CC,#04 BYTE #CF,#OC BYTE #D3,#08 BYTE #D7,#08 BYTE #DB,#04 BYTE #DF,#04 BYTE #E3,#08 BYTE #E7,#0C BYTE #EC,#00 BYTE #FO,#04 BYTE #F4,#0C BYTE #F9,#0C BYTE #FE,#OC BYTE #04,#04 BYTE #09,#0C BYTE #OF,#04 BYTE #15,#08 BYTE #1C,#08 BYTE #23,#08 BYTE #2A,#0C BYTE #32,#08 BYTE #3A,#08 BYTE #42,#0C BYTE #4B,#08 BYTE #54,#00 BYTE #5C,#04 BYTE #65,#00 BYTE #6E,#00 BYTE #78,#08 * * * * * * K2 DECODING TABLE * * * * * TBLK2 BYTE #8A,#00 BYTE #98,#00 BYTE #A3,#0C BYTE #AD,#0C BYTE #B4,#08 BYTE #BA,#08 BYTE #C0,#00 BYTE #C5,#00 BYTE #C9,#0C BYTE #CE,#04 BYTE #D2,#0C BYTE #D6,#0C BYTE #DA,#OC BYTE #DE,#08 BYTE #E2,#00 BYTE #E5,#0C BYTE #E9,#04 BYTE #EC,#OC BYTE #FO,#00 BYTE #F3,#04 BYTE #F6,#08 BYTE #F9,#0C BYTE #FD,#00 BYTE #00,#00 BYTE #03,#04 BYTE #06,#04 BYTE #09,#04 BYTE #0C,#04 BYTE #0F,#04 BYTE #12,#08 BYTE #15,#08 BYTE #18,#08 BYTE #1B,#08 BYTE #1E,#08 BYTE #21,#08 BYTE #24,#0C BYTE #27,#0C BYTE #2A,#0C BYTE #2D,#0C BYTE #3O,#0C BYTE #34,#00 BYTE #37,#00 BYTE #3A,#04 BYTE #3D,#00 BYTE #40,#00 BYTE #43,#00 BYTE #46,#00 BYTE #49,#00 BYTE #4C,#00 BYTE #4F,#04 BYTE #52,#04 BYTE #55,#04 BYTE #58,#04 BYTE #5B,#04 BYTE #5E,#00 BYTE #61,#00 BYTE #63,#0C BYTE #66,#08 BYTE #69,#04 BYTE #6C,#00 BYTE #6F,#00 BYTE #72,#00 BYTE #76,#04 BYTE #7C,#00 ***** * K3 DECODING TABLE ***** TBLK3 BYTE #8B BYTE #9A BYTE #A2 BYTE #A9 BYTE #AF BYTE #B5 BYTE #BB BYTE #C0 BYTE #C5 BYTE #CA BYTE #CF BYTE #D4 BYTE #D9 BYTE #DE BYTE #E2 BYTE #E7 BYTE #EC BYTE #F1 BYTE #F6 BYTE #FB BYTE #01 BYTE #07 BYTE #0D BYTE #14 BYTE #1A BYTE #22 BYTE #29 BYTE #32 BYTE #3B BYTE #45 BYTE #53 BYTE #6D * * * * * K4 DECODING TABLE * * * * * [4 BYTE #94 BYTE #B0 BYTE #C2 BYTE #CB BYTE #D3 BYTE #D9 BYTE #DF BYTE #E5 BYTE #EA BYTE #EF BYTE #F4 BYTE #F9 BYTE #FE BYTE #03 BYTE #07 BYTE #0C BYTE #11 BYTE #15 BYTE #1A BYTE #1F BYTE #24 BYTE #29 BYTE #2E BYTE #33 BYTE #38 BYTE #3E BYTE #44 BYTE #4B BYTE #53 BYTE #5A BYTE #64 BYTE #74 * * * * * * K5 DECODING TABLE *** * * TBLK5 BYTE #A3 BYTE #C5 BYTE #D4 BYTE #E0 BYTE #EA BYTE #F3 BYTE #FC BYTE #04 BYTE #0C BYTE #15 BYTE #1E BYTE #27 BYTE #31 BYTE #3D BYTE #4C BYTE #66 ***** * K6 DECODING TABLE ***** TBLK6 BYTE #AA BYTE #D7 BYTE #E7 BYTE #F2 BYTE #FC BYTE #05 BYTE #0D BYTE #14 BYTE #1C BYTE #24 BYTE #2D BYTE #36 BYTE #40 BYTE #4A BYTE #55 BYTE #6A ***** * K7 DECODING TABLE ***** TBLK7 BYTE #A3 BYTE #C8 BYTE #D7 BYTE #E3 BYTE #ED BYTE #F5 BYTE #FD BYTE #05 BYTE #0D BYTE #14 BYTE #1D BYTE #26 BYTE #31 BYTE #3C BYTE #4B BYTE #67 ***** * K8 DECODING TABLE ***** TBLK8 BYTE #C5 BYTE #E4 BYTE #F6 BYTE #05 BYTE #14 BYTE #27 BYTE #3E BYTE #58 ***** * K9 DECODING TABLE ***** TBLK9 BYTE #B9 BYTE #DC BYTE #EC BYTE #F9 BYTE #04 BYTE #10 BYTE #1F BYTE #45 ***** * KIO DECODING TABLE ***** TBLKl0 BYTE #C3 BYTE #E6 BYTE #F3 BYTE #FD BYTE #06 BYTE #11 BYTE #1E BYTE #43 unl Texas Instruments EXTERNAL INTERFACE SUBROUTINES WIDE OPTION BUNLIST,PAGEOF ******************************************************************************* * * MODIFICATION HISTORY * ******************************************************************************* * * 11/20/96 Initial file creation, Jack Millerick * * 12/2/96 First release. * * 12/3/96 Made MusicData use all bits of A for address in order to share * this function with speech lookup. Speech when using luab must * not change the SAR. MusicData is used to accomplish this. * 12/18/96 Added shift functions to operate the keyboard. * 12/29/96 Removed luaps from store pointer 2 and 3, removed B,A address * combination code. Pointer 2 and 3 will never see more that * 8 bits of address in A. * * * 01/07/97 Added in store pointer savings code. Moved FlipAtoB to main. * * 01/14/97 Removed MusicData * 01/29/97 Jeffway * Removed PAPER as temp variable - now use PwrSeed * Entry Points * * StPntr * StPntrl StPntr2 * StPntr3 * SHIFTO * SHIFT 1 * PrepGetPl * PrepGetP2 * PrepGetP3 * SPGET8 #ifdef BEL0W4K Equates required in the module CLOCK EQU #02 NCLOCK EQU #FD DATA EQU #01 NDATA EQU #FE HANDS EQU #04 NHANDS EQU #FB STROBE EQU #02 NSTROBE EQU #FD DLYTIM EQU #FF * o+.j-p Pointer ************************************************************* * * This function stores the pointer contained in B, A. This function MUST * preserve the X register. It is known that only the lower 8 bits of the * B register are valid so exchanges are used to save the X register. Note * that the A register may contain 9 bits due to code savings in creating the * pointer. Always treat the A register as at least 14 bits. This function also * executes a luaps with the resulting pointer which is used for the simulation * and is only valid for lookups under 16K. The Luaps instruction MUST be execute d * in the final version also in case the table is left within 4K and a get * instruction is executed. * * Input: B,A Specifies the 16 address to be stored in pointer .1 * Output: None Destroys: A,B * ******************************************************************************* * * _ _ _. _ _ _ _ _ _ _ _ _. _ _. _ _ _ _ _ _ _ _ — _ — _ _ _ _ _ _ _ _ _ _ * STORE ADDRESS AT POINTER1 * _________________=_________________ * StPntr StPntrl * * It is possible for the value in the A to be 14 bits wide. This simplifys * math when creating the pointer. Ensure that the upper 6 bits of A are added * in to the MS B value. Do this before using memory to save X tamd ExtlRAM save lower 8 bits of A axca 1 shift A right 7 bits sara shift once more for a total oi abaac combine MSB portion of A with B xba place in the B register tmad ExtlRAM restore A xbx NOTE is destroys the upper bits of xba the B register. OK because B is 8 bits, uppers n ot needed tamd ExtlRAM xba restore registers as they were xbx * The StrPntr sets up the SAR for use in speech and music. This MUST also be * done in the final version. * * This is also done in the get8 call. Doesn't hurt to do it here as well. This * means that a StrPntr will set up the address for a real get instruction as is * the case while under development and may be the case v?hex?. table is intention ally left * in the lower 4K. tax save LS 8 bits xba get MS back tab save, will need MS 8 bits in B sala4 get the upper bits back to MS po; sala4 xbx LS to B, MS in X abaac luaps load the SAR xbx restore MS 8 bits to B tax slice out upper bits in A txa * A and B must contain the 16 bit address in two 8 bit blocks TCX PADDR CHANGE HS(PA2) AND DATA TO BUFFER ED OUTPUT ORCM HANDS ORCM DATA TCX PAPER ANDCM NHANDS TCX DLYTIM MAY NOT BE NEEDED DELAYA IXC br DELAYB br DELAYA DELAYB TCX PADOR SET COMMAND # TO 1 ANDCM #F8 ORCM #01 BR STPTCNT GO TO THE STORE POINTER CONTINUAT ION * STORE ADDRESS AT POINTER2 StPntr2 xbx NOTE is destroys the upper bits of xba the B register. OK because B is 8 bits, uppers n ot needed tamd ExtlRAM xba restore registers as they were xbx TCX PADDR CHANGE HS(PA2) AND DATA TO BUFFERED OUTPUT ORCM HANDS ORCM DATA TCX PAPER ANDCM NHANDS TCX DLYTIM MAY NOT BE NEEDED DELAYAA IXC br DELAYBA br DELAYAA DELAYBA TCX PAD OR SET COMMAND # TO 2 ANDCM #F8 ORCM#02 BR STP CNT GO TO THE STORE POINTER CONTINUATION * STORE ADDRESS AT POINTER3 StPntr3 xbx NOTE is destroys the upper bits of xba the B register. OK because B is 8 bits, uppers n ot needed tamd ExtlRAM xba restore registers as they were xbx TCX PADDR CHANGE HS(PA2) AND DATA TO BUFFERED OUTPUT ORCMHANDS ORCMDATA TCX PAPER ANDCM NHANDS TCX DLYTIM MAY NOT BE NEEDED DELAYAB IXC br DELAYBB br DELAYAB DELAYBB TCX PADOR SET COMMAND # TO 3 ANDCM #F8 ORCM #03 * CONTINUE WITH STORE POINTER * StPtCnt TCX PBDOR STROBE = 0 ANDCM #FD TCX PwrSeed TIME DELAY and PREP VARIABLE ANDCM #00 ANDCM #00 * DO THE A REGISTER * 1 BIT OUT StPtr4 TCX PADOR PREP X TO PADOR ANDCM NDATA SET DATA BIT TO O TSTCA DATA IS DATA 1 OR 0 br StPtrl 1 br StPtr2 0 StPtrl ORCM DATA SET DATA BIT TO 1 StPtr2 ORCM CLOCK SET CLOCK BIT TO 1 TCX DLYTIM TIME DELAY TCX PADOR CLOCK = 0 ANDCM NCLOCK TCX PwrSeed INCMC TSTCM #10 br StPtr5 COUNTER SAYS WE ARE DONE WITH B TSTCM #08 br StPtr3 COUNTER SAYS WE ARE DONE WITH A ( maybe) StPtrό SARA Not Done Yet, Continue br StPtr4 StPtr3 TSTCM #04 MAYBE WE HAVE ALREADY PASSED #40? br StPtrό TSTCM #02 br StPtr6 TSTCM #01 br StPtrδ XBA br StPtr4 DONE StPtr5 TCX DLYTIM DELAY64 IXC br DELAY65 BR DELAY64 DELAY65 TCX PBDOR STROBE = 1 ORCM #02 TCX DLYTIM DELAY66 IXC br DELAY67 br DELAY66 DELAY67 TCX PADOR CLOCK = 1 COULD ELIM? WOULD NEED TO REWRITE SP ORCM CLOCK tmxd ExtlRAM restore x retn PREP TO GET SOME NUMBER OF BITS FROM PO INTER 1 * Revision 12/20/96 rwj * Removed GET 8 * Revised to use PAPER as loop counter for GETs * Revision 12/23/96 rwj * Modified for new Full Handshake Protocol * Revision 01 /29/97 * Revised to use PwrSeed instead of PAPER as temp RAM PrepGetPl txa use A to save x register, it will contain tamd ExtlRAM the result CLA TCX PADDR CHANGE HS(PA2) TO INPUT WITH PULLUP ANDCM NHANDS TCX PAPER ORCM HANDS TCX PwrSeed ANDCM #00 TCX PADOR SET COMMAND # TO 4 ANDCM #F8 ORCM #04 RETN * PREP TO GET SOME NUMBER OF BITS FROM POINTER2 * Revision 12/20/96 rwj Removed GET 8 * Revised to use PAPER as loop counter for GETs * Revision 12/23/96 rwj * Modified for new Full Handshake Protocol * Revision 01/29/97 * Revised to use PwrSeed instead of PAPER as temp RAM PrepGetP2 txa use A to save x register, it will contain tamd ExtlRAM the result GET 8 CLA TCX PADDR CHANGE HS(PA2) TO INPUT WITH PULLUP ANDCM NHANDS TCX PAPER ORCM HANDS TCX PwrSeed ANDCM #00 TCX PADOR SET COMMAND # TO 5 ANDCM #F8 ORCM#05 RETN * PREP TO GET SOME NUMBER OF BITS FROM POINTERS * Revision 12/20/96 rwj * Removed GET 8 * Revised to use PAPER as loop counter for GETs * Revision 12/23/96 rwj * Modified for new Full Handshake Protocol * Revision 01/29/97 * Revised to use PwrSeed instead of PAPER as temp RAM PrepGetP3 txa use A to save x register, it will contain tamd ExtlRAM the result GET 8 CLA TCX PADDR CHANGE HS(PA2) TO INPUT WITH PULLUP ANDCM NHANDS TCX PAPER ORCM HANDS TCX PwrSeed ANDCM #00 TCX PADOR SET COMMAI D # TO b ANDCM #F8 ORCM#06 RETN * *** * *********** *** * * **** * * ** * ** * GET ROUTINE SPGET7 TCX PwrSeed ORCM #01 br DOGET SPGET6 TCX PwrSeed ORCM #02 br DOGET SPGET5 TCX PwrSeed ORCM#03 br DOGET SPGET4 TCX PwrSeed ORCM #04 br DOGET SPGET3 TCX PwrSeed ORCM #05 br DOGET SPGET2 TCX PwrSeed ORCM #06 br DOGET SPGET1 TCX PwrSeed ORCM #07 * NOW DO THE GET SPGET8 DOGET TCX PBDOR ;STROBE = 0 ANDCM NSTROBE TCX PADIR ;WAIT FOR HS LOW GETBIT1 TSTCM HANDS BR GETBIT1 TCX PADDR ;NOW SET DATA BIT TO INPUT(PAO) ANDCM #FE TCX PADOR ;MAKE SURE CLOCK IS LOW (PAl) ANDCM NCLOCK TCX PBDOR ;RAISE THE STROBE TEMP ORCM STROBE TCX PADIR ;WAIT FOR HS HIGH GETBITOA TSTCM HANDS br GETBITOB br GETBITOA GETBITOB TCX PBDOR ;STROBE BACK TO LOW ANDCM NSTROBE TOP OF MAIN GET LOOP GETBIT3 TCX PADIR TSTCM DATA ;GET THE DATA BR GETBIT4 1 BR GETBIT5 0 GETBIT4 ACAAC 1 GETBIT5 TCX PADOR ;RAISE THE CLOCK ORCM CLOCK TCX PwrSeed INCMC TSTCM #08 br GETBIT9 ;COUNTER SAYS WE ARE DONE SALA TCX PADIR ;WAIT FOR HS LOW GETBIT1A TSTCM HANDS BR GETBIT1A TCX PADOR ;MAKE SURE CLOCK IS LOW (PAl) ANDCM NCLOCK TCX PADIR ;WAIT FOR HS HIGH (DATA VALID) GETBIT2 TSTCM HANDS BR GETBIT3 BR GETBIT2 * ********* * *************** ** ****** * * * Get here when we are done with GET * Close everything up and leave GETBIT9 TCX DLYTIM ;MAY NOl MEED THIS?? DELAY72 IXC BR DELAY73 BR DELAY72 DELAY73 TCX PBDOR ;RAISE THE STROBE ORCM STROBE TCX PADDR ;RESTORE PADDR TO DEFAULT STATE ORCM #07 RestXRet tmxd ExtlRAM restore x retn Keyboard Strobe ************************************************************** * The following are functions to clear the external strobe lines to * all 0 or to advance the walking 0. * * SHIFTO Clears all strobe lines to 00 * * SHIFTl Advances active strobe line. If all strobes are cleared * the SHIFTl command the sets the first strobe line active. SEND A CLEAR COMMAND TO THE "SHIFT REGISTER" SHIFTO TCX PADOR SET COMMAND # TO 0 ANDCM #F8 TCX PBDOR STROBE = 0 ANDCM #FD DELAY76 IXC br DELAY77 br DELAY76 DELAY77 TCX PADOR ANDCM NDATA SET DATA BIT TO O br ClkDtaStb * SEND A SHIFT COMMAND TO THE "SHIFT REGISTER" SHIFTl TCX PADOR SET COMMAND # TO 0 ANDCM #F8 TCX PBDOR STROBE = 0 ANDCM #FD TCX DLYTIM DELAY86 IXC br DELAY87 br DELAY86 DELAY87 TCX PADOR ORCM DATA SET DATA BIT TO 1 ClkDtaStb ORCM CLOCK SET CLOCK BIT TO 1 DELAY88 IXC br DELAY89 br DELAY88 DELAY89 TCX PADOR CLOCK - 0 ANDCM NCLOCK DELAY90 IXC br DELAY91 br DELAY90 DELAY91 TCX PBDOR STROBE = 1 ORCM #02 DELAY92 IXC br DELAY93 br DELAY92 DELAY93 TCX PADOR CLOCK = 1 COULD ELIM? WOULD NEE D TO REWRITE SP ORCM CLOCK RETN #endif BELOW4K ******* * ********************* * * * * * ****************** p i f i o xt in **** ** *** * APPENDIX D Title: SPEECH AND SOUND SYNTHESIZNG Applicant: Hasbro, Inc. ; TISP 4 Wire Interface ; Version 0.1 ; Derrived from ROMBD (Released Version) ; Full handshake implemented in PrepGet 12/21 /96 22:51 per Jacks Request Moved table orgs to 0900 and ObaO from OdOO and 1800 Added Sleep at Address Store of ffa5 Removed wait for Strobe = 1 to aid in Initial Sync-up Rev 03 01 / 15/97 Removed my Speech Data Include Removed PEND and A5 @ 4800 Rev 04 1 /23/97 Add Sync Byte of A5 @ 0600 After Rcving address from TI, if 7f00 or greater, add 6100 At NewByte (Inc address in get) change MSB of pointer to eO if = 7f (After Inc) ; Removed TiTables Include @ 0900 .SYMBOLS .LINKLIST SPC40A: EQU 1 .INCLUDE HARDWARE. INH .INCLUDE IO.INH StackTop EQU $0FF .PAGE0 org $80 ; IntTempRegX: ds 1 ; VolumnlndexChl : ds 1 ; VolumnIndexCh2: ds 1 LSB: DS 1 MSB: DS 1 cntl : DS 1 tmp l : DS 1 ShiftData DS 1 Command DS 1 PointerLl DS 1 PointerMl DS 1 Bitl DS 1 Datal DS 1 PointerL2 DS 1 PointerM2 DS 1 Bit2 DS 1 Data2 DS 1 PointerL3 DS 1 PointerM3 DS 1 Bit3 DS 1 Data3 DS 1 PointerLx DS 1 PointerMx DS 1 Bitx DS 1 Datax DS 1 .CODE ;/ ******* * **************************************************** ;/ * * / * Normal program here */ /* / ****** *** ************ ** *** ****** * ** ********** V***** ** ******** org $0 db 0 org $600 Sync: db $a5 Reset: LDX #StackTop ;Reset stack pointer address SOFFH TXS ;Transfer Index X to SP LDA #00H LDX #StackTop ;Clear RAM to 00H RAMClear: STA 00,X DEX CPX #05FH ;Fill OFFH - 60H WITH 00H BNE RAMClear ; Clear All Interrupts Ida #$C0 sta $0D ; Set to Bank 1 Ida #$01 sta $07 Clear Wake-Up Mask ldx #$00 Ida $08 stx $08 and #01 ;can test here for wake-up with one Warm: ; Prep the I/O Ports jsr IOIn ; First time through, wait for Strobe High ????????? Ida #$10 WaitStartHi: bit PortD beq WaitStartHi ; Wait for Strobe Low (PD4) WaitStrobeO: Ida #$10 ;Wait for Stoobe Low (PD4) WaitStrobe: bit PortD bne WaitStrobe ;Stll Low ; Got Low Strobe, now test HS to see id a read or write operation Ida #$02 bit PortD bne DoRead ;Do Read if HS High DoWrite: Ida PortD ;Save the command # for later and #$41 sta Command jsr GetAddress ; Clock in the address, put it in MSB, LSB jsr FillGap ;If we get an address => 7f00, add 6100 jsr PutlnPointer ;Put the data in the proper pointer jmp WaitStrobeO DoRead: Ida PortD ;Save the command # for later and #$41 sta Command jsr PickPointer ;Set up to use data from the proper pointer jsr ReadPointerx ;Handle the read of the data 'till complete jsr SavelnPointer ;Save all generic pointer values in the right pointer jmp WaitStrobeO ; Go to sleep if we get the Special Address stored to pointer GoSleep: Ida #$00 ; All Input with pullup/dn sta PortIO_Ctrl Ida #$ff sta Port Attrib Ida #$00 ;No Port Wakeup sta $08 Ida #$01 sta $09 ;Go to Sleep!! ; end of Sleep Section BEGIN SUBROUTINES Set Port D IO to Inputs and Outputs for For Read Command 10 Out Ida #$73 sta PortIO_Ctrl Ida #$0C sta Port_Attrib Ida #$00 sta PortD ; always leave SR output 0 sta PortC rts Set Port D 10 to Inputs For Write Command IOIn Ida #$33 sta PortIO_Ctrl Ida #$0C sta Port_Attrib rts Clock in the address, 16 bits or less, put it in MSB, LSB Also handle keyboard GetAddress: Ida #$00 sta MSB sta LSB Ida #08 sta cntl ;Preset the 8 bit counter WaitHighAO: bit PortD ;Asuure we have a high clock before we ge t started bvc WaitHighAO ;Its just been used as command data, so we can't be sur e Ida Command beq DoKeyboard WaitLowLA: bit PortD ;Wait here for Clock (PD6) to go low bvs WaitLowLA InBitLA: clc ror LSB Ida PortD ;Input Bit 1 and #$01 clc ror a ror a ora LSB sta LSB ;Save current value Ida #$10 ;Prep to look at the strobe WaitHighLA: bit PortD ;Wait here for clock to go back high, che ck Strobe also bne AddrReturn ;Strobe has gone high, get out bvc WaitHighLA ;Clock still low, strobe still low Clock gone High, continue dec cntl bne WaitLowLA Done 8 LSBits, now go work on MSBits Ida #08 sta cntl ; Preset the 8 bit counter WaitLowMA: bit PortD ;Wait here for Clock (PD6) to go low bvs WaitLowMA InBitMA: clc ror MSB Ida PortD ;Input Bit 1 and #$01 clc ror a ror a ora MSB sta MSB ;Save current value Ida #$10 ;Prep to look at the strobe WaitHighMA: bit PortD ;Wait here for clock to go back high, che ck Strobe also bne AddrReturnx jStrobe has gone high, get out bvc WaitHighMA ; Clock still low, strobe still low ; Clock gone High, continue dec cntl bne WaitLowMA ; If we get here, we got a high Strobe AddrReturnx: ; If we get here, we never got a high strobe during a low clock, but we've done 1 6 bits Ida MSB ; Check for sleep request cmp #$ff bne AddrReturn Ida LSB cmp #$a5 bne AddrReturn jmp GoSleep ; Do the Keyboard DoKeyboard: WaitLowK: bit PortD ;Wait here for Clock (PD6) to go low bvs WaitLowK Ida #$01 bit PortD ;Input Bit 1 bne KeyClock ;Data is 1 , so shift it one bit left Ida #$00 ;Data is 0, so clear all bits sta ShiftData sta PortA sta PortC jmp AddrReturn KeyClock: Ida ShiftData sec rol a sta ShiftData cmp #$01 beq PreSetlt ;See if data is all O's (would be 0000 0001 now) cmp #$ff bne DataNotl PreSetlt: Ida #$fe sta ShiftData DataNotl: sta PortA ; Output the shift register data ror a ror a ror a ror a sta PortC Ida #$10 ;Prep to look at the strobe WaitHighK: bit PortD ;Wait here for clock to go back high, che ck Strobe also bne AddrReturn jStrobe has gone high, get out bvc WaitHighK ; Clock still low, strobe still low AddrReturn: Ida #$10 ;Make absoluly sure clock and strobe are high LastCheck: bit PortD ;Wait here for clock to be high, check St robe also beq LastCheck ; Strobe is still low, wait bvc LastCheck ;Clock still low, strobe now high rts ; = Used for Write Commands ; = Put The MSB, LSB data in the proper pointer as indicated by command PutlnPointer: Ida Command beq WriteCmdO cmp #$01 beq WriteCmdl cmp #$40 beq WriteCmd2 WriteCmd3: Ida . MSB sta PointerM3 Ida LSB sta PointerL3 ldx #$00 Ida (PointerL3,x) sta Data3 Ida #$08 sta Bit3 rts WriteCmd2: Ida MSB sta PointerM2 Ida LSB sta PointerL2 ldx #$00 Ida (PointerL2,x) sta Data2 Ida #$08 sta Bit2 rts WriteCmdl: Ida i MSB sta PointerMl Ida LSB sta PointerLl ldx #$00 Ida (PointerLl, x) sta Datal Ida #$08 sta Bitl rts WriteCmdO: rts ;It was a keyboard command, so just retur n ; = Read Data From Pointer x ReadPointerx: jsr IOOut Ida #$00 sta PortD ;HS to Low Ida #$10 ;wait for temporary strobe high Waitl: bit PortD beq Waitl ; Output a bit OutABit: Ida Datax ;Get data and #$01 ora #$02 ;Set HS to high sta PortD ; Output Bit 1 with HS high Ida Datax ror a sta Datax ;Update current value WaitHighW: bit PortD ;Wait for clock to go high, ackn'ing data rcvd bvc WaitHighW Ida #00 ; Clock is now high: Set HS to Low, OK to trash data sta PortD dec Bitx beq NewByte GoneHighO: Ida #$10 ;prep A so we can look at Strobe GoneHigh: bit PortD ;HS has been set low, now wait for clock to follow bne ReadReturn ;Got a high Strobe, and a low clock, so get out bvs GoneHigh ;Strobe still low, so watch the clock line bvc OutABit ;Strobe low, Clock low, HS Low - So output a bit NewByte: ; Increment the address Ida PointerLx clc adc #1 sta PointerLx Ida PointerMx adc #00 cmp #$7f ;If = 7f, then set to eO (Gap Fill) bne NoGap Ida #$e0 NoGap: sta PointerMx ; Load up a new byte ldx #00 ;Get a new Byte Ida #08 sta Bitx ;Preset the 8 bit counter Ida (PointerLx,x) sta Datax ;Save it jmp GoneHighO ReadReturn: jsr IOIn rts Used for Read Commands Return the updated generic data to the proper Pointer Registers as indicated by command SavelnPointer: Ida Command beq SaveCmdO cmp #$01 beq SaveCmdl cmp #$40 beq SaveCmd2 SaveCmd3: rts SaveCmd2: Ida PointerMx sta PointerM3 Ida PointerLx sta PointerL3 Ida Datax sta Data3 Ida Bitx sta Bιt3 rts SaveCmdl: Ida PointerMx sta PointerM2 Ida PointerLx sta PointerL2 Ida Datax sta Data2 Ida Bitx sta Bit2 rts SaveCmdO: Ida PointerMx sta PointerM 1 Ida PointerLx sta PointerLl Ida Datax sta Datal Ida Bitx sta Bitl rts Used for Read Commands Copy the data from the proper Pointer Registers to the generic registe ϊrrss as indicated by command PickPointer: Ida Command beq PickCmdO cmp #$01 beq PickCmdl cmp # #$$4400 beq PickCmd2 PickCmd3: Ida #$00 sta PointerMx Ida #PointerLl sta PointerLx Ida #$00 sta Datax Ida #$08 sta Bitx rts PickCmd2: Ida PointerM3 sta PointerMx Ida PointerL3 sta PointerLx Ida Data3 sta Datax Ida Bit3 sta Bitx rts PickCmdl: Ida PointerM2 sta PointerMx Ida PointerL2 sta PointerLx Ida Data2 sta Datax Ida Bit2 sta Bitx rts PickCmdO: Ida PointerM 1 sta PointerMx Ida PointerLl sta PointerLx Ida Datal sta Datax Ida Bitl sta Bitx rts Used for Read Commands Copy the data from the proper Pointer Registers to the generic registers as indicated by command FillGap: Ida MSB cmp #$7f bcc FillGap 1 ;7e00 or less clc ;7f00 or greater adc #$61 sta MSB FillGap 1: rts ; END SUBROUTINES org $0900 .INCLUDE D6TABTI.SUN org $0ba0 .INCLUDE TONKLPC.SUN org $5000 • huh???????? DB 'PEND',0 org $7ffa DW Reset DW Reset DW Reset org $fffa DW Reset DW Reset DW Reset

Claims: What is claimed is: 1. A speech synthesizing circuit, comprising: a speech synthesizing integrated circuit chip having a microprocessor, a speech synthesizer, a programmable memory, an input/ output port, and a speech address register for storing an address containing speech data, the speech synthesizing integrated circuit chip . including an instruction, pre-programmed into the speech synthesizing integrated circuit chip during manufacture thereof, that causes an address to be loaded onto the speech address register; and an external memory integrated circuit chip, the input/ output port of the speech synthesizing integrated circuit chip being connected to the external memory integrated circuit chip; the programmable memory of the speech synthesizing integrated circuit chip being programmed to cause the microprocessor to retrieve speech data from the external memory integrated circuit chip for speech synthesis by the speech synthesizer, the programmable memory being programmed by providing a software simulation of the instruction that causes an address to be loaded onto the speech address register, the software simulation causing the address to be loaded into the external memory integrated circuit chip. 2. The speech synthesizing circuit of claim 1 wherein the speech synthesizing integrated circuit chip comprises hardware for connecting to and obtaining data from an external memory. 3. The speech synthesizing circuit of claim 1 wherein the external memory integrated circuit chip comprises an audio synthesizing integrated circuit chip having a microprocessor, an audio synthesizer, an input/ output port, and an audio data storage memory. 4. The speech synthesizing circuit of claim 3 wherein the audio synthesizing integrated circuit chip comprises a programmable memory programmed to cause the microprocessor of the audio synthesizing integrated circuit chip to retrieve audio data from the audio data storage memory of the audio synthesizing integrated circuit chip for audio synthesis by the audio synthesizer of the audio synthesizing integrated circuit chip. 5. The speech synthesizing circuit of claim 4 wherein the programmable memory of the audio synthesizing integrated circuit chip comprises the audio data storage memory of the audio synthesizing integrated circuit chip. 6. The speech synthesizing circuit of claim 3 wherein the speech synthesizer of the speech synthesizing integrated circuit chip processes speech data at a higher efficiency than the audio synthesizer of the audio synthesizing integrated circuit chip processes. 7. The speech synthesizing circuit of claim 6 wherein the speech synthesizer of the speech synthesizing integrated circuit chip comprises a linear predictive coding synthesizer. 8. The speech synthesizing circuit of claim 7 wherein the speech synthesizing integrated circuit chip is selected from the family of TSP50C4X, TSP50C1X, and TSP50C3X chips. 9. The speech synthesizing circuit of claim 8 wherein the speech synthesizing integrated circuit chip comprises a TSP50C3X chip. 10. The speech synthesizing circuit of claim 6 wherein the audio synthesizer of the audio synthesizing integrated circuit chip comprises an adaptive pulse code modulation synthesizer. 11. The speech synthesizing circuit of claim 10 wherein the audio synthesizing integrated circuit chip is selected from the family of SPC 0A. SPC256A, and SPC512A chips. 12. The speech synthesizing circuit of claim 3 wherein: the speech synthesizing integrated circuit chip comprises a balanced speaker driver having two outputs for connection of a first speaker impedance between the two outputs; the audio synthesizing integrated circuit chip comprises a single- ended speaker driver having a single output for connection to a second speaker impedance; and a speaker is connected between the two outputs of the balanced speaker driver of the first audio synthesizer and is also connected to the single-ended speaker driver of the second audio synthesizer. 13. The speech synthesizing circuit of claim 1 wherein the programmable memory of the speech synthesizing integrated circuit chip is programmed with speech data for speech synthesis by the speech synthesizer. 14. A method of combining a speech synthesizing integrated circuit chip with an external memory integrated circuit chip, comprising the steps of: providing a speech synthesizing integrated circuit chip having a microprocessor, a speech synthesizer, a programmable memory, an input/ output port, and a speech address register for storing an address containing speech data, the speech synthesizing integrated circuit chip including an instruction, pre-programmed into the speech synthesizing integrated circuit chip during manufacture thereof, that causes an address to be loaded onto the speech address register; providing the external memory integrated circuit chip; connecting the input/ output port of the speech synthesizing . integrated circuit chip with the external memory integrated circuit chip; programming the programmable memory of the speech synthesizing integrated circuit chip to cause the microprocessor to retrieve speech data from the external memory integrated circuit chip for speech synthesis by the speech synthesizer, the programmable memory being programmed by providing a software simulation of the instruction that causes an address to be loaded onto the speech address register, the software simulation causing the address to be loaded into the external memory integrated circuit chip. 15. A speech synthesizing circuit, comprising: a speech synthesizing integrated circuit chip having a microprocessor, a speech synthesizer, a programmable memory, an input/ output port, and a speech address register for storing an address at which speech data is located, the speech synthesizing integrated circuit chip including one or more instructions, pre-programmed into the speech synthesizing integrated circuit chip during manufacture thereof, that obtain speech data located at an address stored in the speech address register; and an external memory integrated circuit chip, the input/ output port of the speech synthesizing integrated circuit chip being connected to the external memory integrated circuit chip; at least one of the integrated circuit chips being programmed to cause speech data to be delivered from the external memory integrated circuit chip to the speech synthesizing integrated circuit chip for speech synthesis by the speech synthesizer, by providing a software simulation of the one or more instructions that obtain speech data located at an address stored in the speech address register, the software simulation causing speech data to be obtained by the speech synthesizing integrated circuit chip from the external memory integrated circuit chip at an address stored in the external memory integrated circuit chip. 16. The speech synthesizing circuit of claim 15, wherein the programmable memory of the speech synthesizing integrated circuit chip is programmed to cause speech data to be delivered from the external memory integrated circuit chip to the speech synthesizing integrated circuit chip for speech synthesis by the speech synthesizer, by providing the software simulation of the one or more instructions that obtain speech data located at an address stored in the speech address register. 17. The speech synthesizing circuit of claim 15 wherein the speech synthesizing integrated circuit chip comprises hardware for connecting to and obtaining data from an external memory. 18. The speech synthesizing circuit of claim 15 wherein the external memory integrated circuit chip comprises an audio synthesizing integrated circuit chip having a microprocessor, an audio synthesizer, an input/ output port, and an audio data storage memory. 19. The speech synthesizing circuit of claim 18 wherein the audio synthesizing integrated circuit chip comprises a programmable memory programmed to cause the microprocessor of the audio synthesizing integrated circuit chip to retrieve audio data from the audio data storage memory of the audio synthesizing integrated circuit chip for audio synthesis by the audio synthesizer of the audio synthesizing integrated circuit chip. 20. The speech synthesizing circuit of claim 19 wherein the programmable memory of the audio synthesizing integrated circuit chip comprises the audio data storage memory of the audio synthesizing integrated circuit chip. 21. The speech synthesizing circuit of claim 18 wherein the speech synthesizer of the speech synthesizing integrated circuit chip processes speech data at a higher efficiency than the audio synthesizer of the audio synthesizing integrated circuit chip processes. 22. The speech synthesizing circuit of claim 21 wherein the speech synthesizer of the speech synthesizing integrated circuit chip comprises a linear predictive coding synthesizer. 23. The speech synthesizing circuit of claim 22 wherein the speech synthesizing integrated circuit chip is selected from the family of TSP50C4X, TSP50C1X, and TSP50C3X chips. 24. The speech synthesizing circuit of claim 23 wherein the speech synthesizing integrated circuit chip comprises a TSP50C3X chip. 25. The speech synthesizing circuit of claim 21 wherein the audio synthesizer of the audio synthesizing integrated circuit chip comprises an adaptive pulse code modulation synthesizer. 26. The speech synthesizing circuit of claim 21 wherein the audio synthesizing integrated circuit chip is selected from the family of SPC40A, SPC256A, and SPC512A chips. 27. The speech synthesizing circuit of claim 18 wherein: the speech synthesizing integrated circuit chip comprises a balanced speaker driver having two outputs for connection of a first speaker impedance between the two outputs; the audio synthesizing integrated circuit chip comprises a single- ended speaker driver having a single output for connection to a second speaker impedance; and a speaker is connected between the two outputs of the balanced speaker driver of the first audio synthesizer and is also connected to the single-ended speaker driver of the second audio synthesizer. 28. The speech synthesizing circuit of claim 15 wherein the programmable memory of the speech synthesizing integrated circuit chip is programmed with speech data for speech synthesis by the speech synthesizer. 29. A method of combining a speech synthesizing integrated circuit chip with an external memory integrated circuit chip, comprising the steps of: providing a speech synthesizing integrated circuit chip having a microprocessor, a speech synthesizer, a programmable memory, an input/ output port, and a speech address register for storing an address containing speech data, the speech synthesizing integrated circuit chip including one or more instructions, pre-programmed into the speech synthesizing integrated circuit chip during manufacture thereof, that obtain speech data located at an address stored in the speech address register; providing the external memory integrated circuit chip; connecting the input/ output port of the speech synthesizing integrated circuit chip with the external memory integrated circuit chip; programming at least one of the integrated circuit chips to cause speech data to be delivered from the external memory integrated circuit chip to the speech synthesizing integrated circuit chip for speech synthesis by the speech synthesizer, by providing a software simulation of the one or more instructions that obtain speech data located at an address stored in the speech address register, the software simulation causing speech data to be obtained by the speech synthesizing integrated circuit chip from the external memory integrated circuit chip at an address stored in the external memory integrated circuit chip. 30. A speech synthesizing circuit, comprising: a speech synthesizing integrated circuit chip having a microprocessor, a linear predictive coding speech synthesizer, and an input/ output port for interfacing with an external memory; and an audio synthesizing integrated circuit chip having a microprocessor, an adaptive pulse code modulation synthesizer, an input/ output port, and an audio data storage memory; the input/ output port of the speech synthesizing integrated circuit chip being interfaced with the input/ output port of the audio synthesizing integrated circuit chip; the speech synthesizing integrated circuit chip being programmed to cause the microprocessor of the speech synthesizing integrated circuit chip to retrieve speech data from the audio data storage memory of the audio synthesizing integrated circuit chip for speech synthesis by the speech synthesizer of the speech synthesizing integrated circuit chip. 31. The speech synthesizing circuit of claim 30 wherein the audio synthesizing integrated circuit chip is programmed to cause the microprocessor of the audio synthesizing integrated circuit chip to retrieve audio data from the audio data storage memory of the audio synthesizing integrated circuit chip for audio synthesis by the adaptive pulse code modulation synthesizer of the audio synthesizing integrated circuit chip. 32. The speech and audio synthesizing circuit of claim 30 wherein the speech synthesizing integrated circuit chip is selected from the family of TSP50C4X, TSP50C1X, and TSP50C3X chips. 33. The speech synthesizing circuit of claim 32 wherein the speech synthesizing integrated circuit chip comprises a TSP50C3X chip. 34. The speech synthesizing circuit of claim 30 wherein the audio synthesizing integrated circuit chip is selected from the family of SPC40A, SPC256A, and SPC512A chips. 35. A method of combining a speech synthesizing integrated circuit chip and an audio synthesizing integrated circuit chip, comprising the steps of: providing a speech synthesizing integrated circuit chip having a microprocessor, a linear predictive coding speech synthesizer, and an input/ output port for interfacing with an external memory; providing an audio synthesizing integrated circuit chip having a microprocessor, an adaptive pulse code modulation synthesizer, an input/ output port, and an audio data storage memory; interfacing the input/ output port of the speech synthesizing integrated circuit chip with the input/ output port of the audio synthesizing integrated circuit chip; and programming the speech synthesizing integrated circuit chip to cause the microprocessor of the speech synthesizing integrated circuit chip to retrieve speech data from the audio data storage memory of the audio synthesizing integrated circuit chip for speech synthesis by the speech synthesizer of the speech synthesizing integrated circuit chip. 36. An audio synthesizing circuit, comprising: a first audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory, and a balanced speaker driver having two outputs for connection of a first speaker impedance between the two outputs; a second audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory, and a single-ended speaker driver having a single output for connection to a second speaker impedance; and a speaker connected between the two outputs of the balanced speaker driver of the first audio synthesizer and also connected to the single-ended speaker driver of the second audio synthesizer. 37. The audio synthesizing circuit of claim 36 wherein the first speaker impedance differs from the second speaker impedance. 38. The audio synthesizing circuit of claim 36 further comprising at least one resistor connected to the speaker so as to from a resistive network with the speaker, the resistive network having an impedance between the two outputs of the balanced speaker driver equal to the first speaker impedance and having a single-ended impedance connected to the output of the single-ended speaker driver equal to the second speaker impedance. 39. The audio synthesizing circuit of claim 38 wherein the resistor is connected in series with the speaker, and the output of the single-ended speaker driver is connected to the junction between the resistor and the speaker. 40. The audio synthesizing circuit of claim 39 wherein the first speaker impedance is four times the second speaker impedance, and wherein the resistor has a resistance equal to the resistance of the speaker. 41. The audio synthesizing circuit of claim 36 wherein the first and second audio synthesizing circuits are formed on respective integrated circuit chips. 42. The audio synthesizing circuit of claim 36 wherein the first audio synthesizing circuit comprises a speech synthesizing circuit and the second audio synthesizing circuit comprises a non-speech sound synthesizing circuit. 43. The audio synthesizing circuit of claim 36 wherein the audio synthesizer of the first audio synthesizing integrated circuit produces a pulse width modulated output. 44. The audio synthesizing circuit of claim 43 wherein the audio driver of the second audio synthesizing integrated circuit produces an analog output. 45. A method of combining a plurality of audio synthesizing integrated circuits, comprising the steps of: providing a first audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory, and a balanced speaker driver having two outputs for connection of a first speaker impedance between the two outputs; providing a second audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory, and a single-ended speaker driver having a single output for connection to a second speaker impedance; and connecting a speaker between the two outputs of the balanced speaker driver of the first audio synthesizer and also connecting the speaker to the single-ended speaker driver of the second audio synthesizer.

Inventors: JEFFWAY ROBERT W, JEFFWAY, ROBERT, W.
Applicants: HASBRO INC, HASBRO, INC.
Application year: 1998
Main classification: G10L
IPC codes: G10L13