METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, LIQUID CRYSTAL DISPLAY AND ELECTRONIC DEVICE BOTH PRODUCED BY THE METHOD

Abstract: A method for manufacturing a highly reliable non-single crystal silicon thin film transistor. A polycrystalline silicon layer (17) is formed on a base SiO 2 film (15) after the film (15) is formed on a glass substrate (14). Then the layer (17) is patterned and a gate SiO 2 film (18) is formed by ECR-PECVD or TEOS-PECVD. After forming the film (18), a gate electrode (19) is formed and source and drain regions (20) and (20) are formed by ion-doping. Then, after an SiO 2 interlayer insulating film (21) is formed and a contact hole (22) is opened, an electrode (23) composed of an Al-Si-Cu film is formed. Lastly, wet-annealing is conducted for three hours at a temperature of 350 °C.

Description: [TECHNICAL FIELD] The present invention relates to a method for making a thin film transistor using a non-single-crystal silicon thin film suitable for driving elements of, for example, liquid crystal display devices, and a liquid crystal display device and an electronic device using the same. [BACKGROUND ART] Thin film transistors using thin films composed of non-single-crystal silicon thin films, such as amorphous silicon and polycrystalline silicon, have been intensively studied and developed. The technologies are expected to be used in various fields, for example, active matrix panels, which permit thin displays by the use of an inexpensive insulating substrate and inexpensive high-performance image sensors. An example of conventional methods for making the thin film transistor will now be described with reference to Fig. 14. Thin film transistors are classified into two types, that is, a top-gate-type thin film transistor composed of an underlying silicon thin film forming source and drain regions and an overlying gate electrode, and a bottom-gate-type thin film transistor composed of an underlying gate electrode and an overlying silicon thin film. Herein, a top-gate-type thin film transistor is exemplified. The following manufacturing method is cited from "Fabrication of Self-Aligned Aluminum Gate Polysilicon Thin-Film Transistors Using Low-Temperature Crystallization Process", E. Ohno et al.; Jpn. J. Appl. Phys. Vol. 33 (1994), pp. 635-638. As shown in Fig. 14(a), after a SiO 2 buffer layer 2 is formed on a glass substrate 1, an amorphous silicon layer 3 having a thickness of 100 nm is formed thereon by a low-pressure chemical vapor deposition (LPCVD) process. The amorphous silicon layer 3 is annealed in a nitrogen atmosphere at 600 °C for 24 hours. Next, as shown in Fig. 14(b), after patterning the amorphous silicon layer 3, a SiO 2 gate insulating film 4 having a thickness of 100 nm is formed by a atmospheric pressure CVD process and is annealed at 600 °C for 12 hours. Next, as shown in Fig. 14(c), an aluminum (Al) film is formed by a sputtering process and patterned to form a gate electrode 5. Phosphorus or boron is implanted using the gate electrode 5 as a mask to form source and drain regions 6 in the silicon layer 3. Since protons are simultaneously implanted, no annealing is required. Next, as shown in Fig. 14 (d), a SiO 2 insulating interlevel film 7 is formed by a tetraethoxysilane plasma enhanced CVD (hereinafter referred to as TEOS-PECVD) process, contact holes 8, 8 are formed in the interlevel film 7, and an aluminum film 9 is finally deposited and formed as an electrode. The thin film transistor manufactured by the above-mentioned steps is used as a driving element, for example, for a liquid crystal display device for a long period, hence it is important to reduce change in electrical characteristics with time as much as possible and to ensure sufficient reliability. In conventional manufacturing processes of thin film transistors, however, correlations between various parameters in production and reliability of devices have not been clarified, and a manufacturing process with high reliability has not been investigated. The manufacturing steps (environment and processing atmospheres) and devices must be isolated from moisture in order to ensure reliability as much as possible, however, spin-on-glass films (hereinafter referred to as SOG) often used as interlevel films for planarization in semiconductor devices has a disadvantage of high moisture absorption. Japanese Patent Laid-Open No. 4-93049 discloses removal of moisture in the SOG film by nitrogen annealing at approximately 430 °C after coating of an SOG film. Further, Japanese Patent Laid-Open No. 4-164351 discloses removal of moisture in an SOG film by annealing, for example, at 400 °C for 30 minutes after the formation of a plasma oxide film on the SOG film. On the other hand, it has been reported that when a thin film transistor provided with a SiO 2 gate insulating film by a PECVD process is annealed at approximately 270 °C in a moist atmosphere, the interface state density between the SiO 2 film and the polycrystalline silicon film decreases and thus the threshold voltage (hereinafter referred to as Vth) of the thin film transistor is reduced ( "High Quality SiO 2 /Si Interfaces of Poly-Crystalline Silicon Thin Film Transistors by Annealing in Wet atmosphere" , N. Sano et al.; IEEE ELECTRON DEVICE LETTERS, VOL. 16, NO. 5, MAY 1995). According to another report, wet oxygen annealing (moisture-containing oxygen annealing) after deposition of a TEOS-O 3 NSG film modifies the film quality into a nonhygroscopic state ("Effect of Low-Temperature Annealing on Hygroscopicity of TEOS-O 3 Atmospheric CVD NSG Film", Oda et al.; Semiconductor World, February 1993). Although these reports refer to the control of the Vth and the improvement in the moisture resistance by employing annealing in moist environments (hereinafter referred to as wet annealing), these do not clarify the correlation between the wet annealing and the reliability of the device, and thus these technologies do not improve the reliability of thin film transistors. US Patent No. 5475252, PROCESS FOR MANUFACTURE OF RADIATION RESISTANT POWER MOSFET AND RADIATION RESISTANT POWER MOSFET, discloses a process for producing a radiation resistant power MOSFET where the gate oxide is formed toward the end of the processing and is not exposed to substantial thermal cycling. International Patent Publication No. 97/25738, A WATER VAPOR ANNEALING PROCESS, discloses a method of fabricating semiconductor devices including the steps of forming a silicon-based dielectric layer and annealing the dielectric layer on a water vapor atmosphere. Japanese Patent No. 52066377, MANUFACTURE OF SEMICONDUCTOR DEVICE, discloses heat treating a semiconductor element under steam or steam containing atmosphere after a silicon dioxide layer has been deposited on the glass layer. Japanese Patent No. 52076937, METHOD OF CHEMICALLY VAPOR-DEPOSITING A LOW-STRESS GLASS LAYER, discloses a method of chemically vapor-depositing a low-stress glass layer onto a substrate which is heated in an atmosphere including silane, oxygen and an inert carrier gas, comprises the step of adding water vapor to the atmosphere. Japanese Patent No. 8055847, METHOD AND APPARATUS FOR HEAT TREATMENT OF SILICON OXIDE FILM, discloses heat treating a silicon oxide film, used as a gate insulating film. Japanese Patent No. 6232402, MANUFACTURE OF THIN FILM SEMICONDUCTOR DEVICE, discloses forming an insulating film which has excellent boundary characteristics by keeping a glass substrate at a specific temperature and at the same time depositing an insulating layer thereon and then applying heat treatment. DISCLOSURE OF INVENTION The present invention is accomplished to solve the above-mentioned problems and it is an object of the present invention to provide a method for making a highly reliable thin film transistor using a non-single-crystal silicon thin film. In accordance with the present invention for achieving the object, a method for making a thin film transistor comprising a channel region composed of a non-single-crystal silicon thin film facing a gate electrode with a gate insulating film of an field effect transistor therebetween, the method characterized by the gate insulating film consisting of a film of silicon oxide alone and the gate insulating film being wet-annealed at least after forming the gate insulating film. Specifically, the gate insulating film may be formed by a PECVD process or a TEOS-PECVD process, and preferably the wet annealing is performed at a temperature of 300 °C or higher and for a duration of one hour or more. In addition to the above-mentioned steps, a step forming a silicon oxide insulating interlevel film which covers the non-single-crystal silicon thin film or the gate electrode may be provided and the wet annealing step may be performed after forming the insulating interlevel film. The insulating interlevel film may be a silicon oxide film formed by a TEOS-PECVD process. Alternatively, an underlying insulating film composed of a silicon oxide film may be formed on the glass substrate and the non-single-crystal silicon thin film may be formed on the underlying insulating film, followed by wet annealing. The underlying insulating film may be formed by a PECVD or TEOS-PECVD process, and preferably the film thickness is in the range from 100 nm to 500 nm. The present invention includes modification of the quality of the films forming a thin film transistor by means of moisture during wet annealing after the formation of the major components in the thin film transistor in order to improve the reliability of the thin film transistor. Since a thin film transistor cannot be formed on a glass substrate at a high temperature, the temperature must be reduced to 450 °C or less during the entire process. The formation of, for example, a silicon oxide film in a low temperature process forming a thin film transistor on a glass substrate results in a different structure of the silicon oxide film from that in a high temperature process such as thermal oxidation. The silicon oxide film immediately after the deposition in a low temperature process contains a weak bond 11 between a silicon (Si) atom and an oxygen (O) atom, as shown in Fig. 13(a), and the silicon oxide film having such an unstable bond results in a change of the electrical characteristics, for example Vth. During wet annealing, however, water (H 2 O) penetrates into the silicon oxide film, as shown in Fig. 13(b) and cuts the weak bond 11 to form -OH groups. Then, as shown in Fig. 13(c), water is eliminated to form a strong bond 12 between the silicon and oxygen atoms. Since the bonds in the silicon oxide film are stabilized by wet annealing in such a manner, change in the electrical characteristics is significantly reduced. [BRIEF DESCRIPTION OF DRAWINGS] Fig. 1 is a process flow chart of steps of a method for making a thin film transistor in accordance with an embodiment of the present invention. Fig. 2 is a continuation of the process flow chart. Fig. 3 is a graph illustrating the results of reliability evaluation of an embodiment of the present invention, that is, a graph illustrating the change in V gs vs I ds characteristics by a BT test of a test piece not subjected to wet annealing. Fig. 4 is a graph of a test piece subjected to wet annealing at 300 °C for 1 hour. Fig. 5 is a graph of a test piece subjected to wet annealing at 300 °C for 3 hours. Fig. 6 is a graph of a test piece subjected to wet annealing at 350 °C for 1 hour. Fig. 7 is a graph of a test piece subjected to wet annealing at 350 °C for 3 hours. Fig. 8 is a graph illustrating the change in V gs vs I ds characteristics by a current flow stress test of a test piece not subjected to wet annealing. Fig. 9 is a graph of a test piece subjected to wet annealing at 300 °C for 1 hour. Fig. 10 is a graph of a test piece subjected to wet annealing at 300 °C for 3 hours. Fig. 11 is a graph of a test piece subjected to wet annealing at 350 °C for 1 hour. Fig. 12 is a graph of a test piece subjected to wet annealing at 350 °C for 3 hours. Fig. 13 is a schematic view illustrating a mechanism of the improvement in the film quality in accordance with the present invention. Fig. 14 is a process flow chart of steps of a conventional method for making a thin film transistor. Fig. 15 is a schematic view of an active matrix substrate configuration in a liquid crystal display device or the like formed by a method for making a thin f ilm transistor in accordance with the present invention. Fig. 16 is a schematic view of a liquid crystal display device (liquid crystal display panel) configuration based on an active matrix substrate formed by a method for making a thin film transistor in accordance with the present invention. Fig. 17 is an electronic device using a liquid crystal display device formed in an embodiment of the present invention. Fig. 18 shows a liquid crystal projector configuration as an example of electronic devices formed in an embodiment of the present invention. Fig. 19 shows a personal computer configuration as an example of electronic devices formed in an embodiment of the present invention. Fig. 20 shows a pager configuration as an example of electronic devices formed in an embodiment of the present invention. Fig. 21 shows a liquid crystal display device configuration as a part for electronic devices connected to a tape carrier package (TCP) formed in an embodiment of the present invention. Fig. 22 is a schematic view of wet annealing using a hot plate in accordance with the present invention. Fig. 23 is a schematic view of wet annealing using a hot wall system in accordance with the present invention. [Reference Numerals] 14 glass substrate 15 underlying SiO 2 film (underlying insulating film, silicon oxide film) 16 amorphous silicon layer 17 polycrystalline silicon layer (non-single-crystal silicon thin film) 18 gate SiO 2 film (gate insulating film, silicon oxide film) 19 gate electrode 20 source and drain regions 21 SiO 2 insulating interlevel film (insulating interlevel film, silicon oxide film) 22 contact hole 23 electrode [BEST MODE FOR CARRYING OUT THE INVENTION] An embodiment of the present invention will now be described with reference to Fig. 1 and Fig. 2. Fig. 1 and Fig. 2 are process flow charts illustrating steps of a method for making a thin film transistor in accordance with this embodiment. A glass substrate 14, for example, OA-2 (trade name, made by Nippon Electric Glass Co., Ltd.) or 7059 (trade name, made by Corning Incorporated), is prepared. As shown in Fig. 1(a), an underlying SiO 2 film 15 (silicon oxide film) having a thickness of 100 to 500 nm is formed on the entire glass substrate 14 by a PECVD process using electron cyclotron resonance (hereinafter referred to as ECR) or a TEOS-PECVD process. Next, as shown in Fig. 1(b) an amorphous silicon layer 16 having a thickness of approximately 50 nm is formed on the entire underlying SiO 2 film 15 by an LPCVD process at a temperature of 450 °C using disilane (Si 2 H 6 ) or a PECVD process at a temperature of 320 °C using monosilane (SiH 4 ). Next, laser annealing is performed on the amorphous silicon layer 16. An excimer laser such as XeCl or KrF is used with an energy density of 200 to 300 mJ/cm 2 . By the laser annealing, the amorphous silicon layer 16 is crystallized to form a polycrystalline silicon layer 17 (non-single-crystal s ilicon thin film), as shown in Fig . 1(c). Next, hydrogen (H 2 ) annealing is performed at a temperature of 300 °C. After patterning the polycrystalline silicon layer 17 as shown in Fig. 1(d), a gate SiO 2 film 18 (silicon oxide f ilm) having a thickness of approximately 120 nm is formed to cover the polycrystalline silicon layer 17 by an ECR-PECVD or TEOS-PECVD process, as shown in Fig. 1(e). Next, a tantalum (Ta) film having a thickness of 600 to 800 nm is deposited on the entire surface by a sputtering process, and patterned to form a gate electrode 19, as shown in Fig. 2(f). As shown in Fig. 2(g), source and drain regions 20, 20 at a Nch side of the thin film transistor are formed by an ion doping process using PH 3 /H 2 and the gate electrode 19 as a mask, and then source and drain regions (not shown in the drawing) at a Pch side of the thin film transistor are formed by an ion doping process using B 2 H 6 /H 2 . A region between the source and drain regions 20, 20 functions as a channel region. These ion doping processes have a dose rate of approximately 7×10 15 atoms/cm 2 . Next, hydrogen annealing is performed at 300 °C for 2 hours. Next, as shown in Fig. 2(h), a SiO 2 insulating interlevel film 21 ( silicon oxide film) having a thickness of 500 to 1,000 nm is formed by a TEOS-PECVD process. Further, as shown in Fig. 2(i), the insulating interlevel film 21 is pierced to form contact holes 22, 22 connected to the source and drain regions 20, 20 on the polycrystalline silicon layer, and an Al-Si-Cu film is deposited on the entire surface and patterned to form electrodes 23, 23 for applying a voltage to the source and drain regions 20, 20. Finally, a wet annealing step characteristic to the present invention is performed. The wet annealing step is performed under the conditions of, for example, a temperature of 350 °C for an annealing time of 3 hours in an atmosphere containing water of a partial pressure of 10 Torr or more. Wet annealing for more than 3 hours is also allowable. In accordance with the method for making a thin film transistor of this embodiment, after the gate electrode facing the source and drain regions 20, 20 and the channel region separated by the gate insulating film is formed, the quality of the silicon oxide films, such as the gate SiO 2 film 18, is improved by the wet annealing. That is, during the annealing of the oxide film in a moist atmosphere, weak bonds in the oxide film are hydrolyzed and then recombined by elimination of water, resulting in the stabilization of the oxide film. As a result, the quality of the gate SiO 2 film 18, the insulating interlevel film 21 composed of a silicon oxide film, and insulating films such as the underlying insulating film 15 are stabilized, and thus changes in the electrical characteristics of the thin film transistor are reduced, resulting in improved reliability. (Examples) The experimental results illustrating the advantages of the present invention will now be described. Polycrystalline silicon thin film transistors made by a method in accordance with the above-mentioned embodiment were subjected to reliability tests. Among various reliability tests, changes in V gs -I ds characteristics before/after bias temperature treatment (BT treatment or temperature treatment while applying a biasing current) and before/after current stress (stress by an on-current flow) were measured in the present invention. The V gs -I ds characteristics are fundamental electrical characteristics of transistors. The polycrystalline silicon thin film transistor has an underlying SiO 2 film having a thickness of 200 nm formed by an ECR-PECVD process and a gate SiO 2 film having a thickness of 120 nm formed by an TEOS-PECVD process. The TEOS-PECVD process for forming the gate SiO 2 film was performed under the conditions of a TEOS flow rate of 105 sccm, an O 2 flow rate of 5, 000 sccm, a pressure of 1.2 Torr, a high-frequency power of 800 W, a temperature of 350 °C, and a deposition rate of 72 nm/min. or less. The gate W/L (gate width/gate length) was 10 µm/10 µm. [Evaluation 1] BT Test Fig. 3 to Fig 7 are graphs illustrating BT tests of the samples which were subjected to wet annealing under various conditions (temperatures and times), that is, Fig. 3 for the characteristics of a sample without wet annealing, Fig. 4 for wet annealing at 300 °C for 1 hour, Fig. 5 for wet annealing at 300 °C for 3 hours, Fig. 6 for wet annealing at 350 °C for 1 hour, and Fig. 7 for wet annealing at 350 °C for 3 hours. The BT treatment was carried out at a substrate temperature of 200 °C, and a V gs of +20 V or -20V (the voltage is applied to only the gate, and the source and drain were grounded) for 20 seconds, and the V gs -I ds characteristics after the BT treatment was measured at a V ds of 4V after the temperature decreased to the room temperature. In order to compare the changes in the V gs -I ds characteristics under various treatment conditions, the Vgs value at Ids = 1 nA (1E-9A) is defined as Vth, and the difference between Vth values before the BT treatment is represented by "ΔVth". Hereinafter, the BT treatment at V gs = +20 V is referred to as "+BTS", that at V gs = -20 V is referred to as "-BTS". The ΔVth values under the treatment conditions determined in accordance with Fig. 3 to Fig. 7 are shown in the following table. ΔVth(+BTS) ΔVth(-BTS) Drawing Without wet annealing -9.0 V - Fig. 3 300 °C for 1 hour -7.8 V - Fig. 4 300 °C for 3 hours -6.0 V - Fig. 5 350 °C for 1 hour +1.0 V -0.2 V Fig. 6 350 °C for 3 hours +0.1 V -0.6 V Fig. 7 Table 1 evidently demonstrates that the ΔVth of the sample without wet annealing is -9 V, the ΔVth slightly decreases to - 7.8 V by wet annealing at 300 °C for 1 hour and decreases to - 6V by extending the annealing temperature to 3 hours at the same temperature. The ΔVth values at +BTS and -BTS significantly decreases to +1 V, and -0.2 V, respectively by wet annealing at 350 °C for 1 hour. The ΔVth values at +BTS and - BTS become less than - 1 V by extending the annealing temperature to 3 hours at the same temperature. Accordingly, the results demonstrates that the ΔVth value starts to decrease by wet annealing at 300 °C for 1 hour, and the change in the Vth before/after the BT treatment can be reduced to be 1 V or less at a wet annealing temperature of 350 °C for a duration of at least one hour. [Evaluation 2] Current Stress Test Polycrystalline silicon thin film transistors used in this test had the same structure as in the BT test, except that the gate size was W/L = 100 µm/10 µm. Fig. 8 to Fig. 12 are graphs illustrating the results of current stress tests of samples subjected to various wet annealing conditions (temperature and time), that is, Fig. 8, Fig. 9, Fig. 10, and Fig. 11 correspond to characteristics with non-wet annealing, at 300 °C for 1 hour, 300 °C for 3 hours, 350 °C for 1 hour, and 350 °C for 3 hours, respectively. The current stress was applied under the conditions of V gs = +15 V and V ds = +12 V (the source was grounded) and energizing times of 30 seconds, 1 minute, 5 minutes, 15 minutes, 30 minutes and 60 minutes, and the V gs -I ds characteristics were measured at V ds = 4V after completion of the energizing. In an overall feature in the current stress test, the V gs -I ds characteristic curve becomes gentle at a shorter energizing time, for example, 30 seconds compared to that in non-energizing time, and returns to the characteristic curve in non-energizing time at a longer energizing time. Regarding such a change in the characteristic curve, Fig. 8 to Fig. 10 evidently demonstrate that wet annealing at 300 °C for 1 hour, as well as non-wet annealing, gives a large change in the characteristic curve, and such a change slightly decreases by extending the annealing time to 3 hours. Fig. 11 and Fig. 12 demonstrate that the change in the characteristic curve becomes significantly small by the wet annealing at 350 °C for 1 hour and is not substantially observed by extending the annealing time to 3 hours. Accordingly, the results demonstrate that the change in the characteristic curve starts to decrease by wet annealing at 300 °C for 1 hour, and the change in the V gs -I ds characteristic curve before/after the current stress application can be satisfactorily reduced at a wet annealing temperature of 350 °C for a duration of at least one hour. The results of the BT and current stress tests illustrate that by the wet annealing at a temperature of 300 °C or more, and preferably at 350 °C or more, for at least one hour the change in the electrical characteristics can be significantly reduced compared to a conventional manufacturing process without wet annealing, resulting in improved reliability. It is preferable that the wet annealing temperature be within a range from 300 °C to 500 °C because a temperature of higher than 500 °C may eliminate hydrogen embedded into the silicon oxide film. The apparatus for the wet annealing will be described. The wet annealing is performed, as described above, at a temperature of 300 °C or more, and preferably at 350 °C or more, for at least one hour. Wet annealing using a hot plate and wet annealing using a hot wall system will be described with reference to the drawings. Fig. 22 is a schematic view of the wet annealing using a hot plate. In Fig. 22, numeral 201 represents a hot plate which is maintained at 300 °C or more and preferably 350 °C or more. A glass substrate 202 provided with a silicon oxide film such as a gate insulating film (underlying insulating film, or insulating interlevel film) is placed on the hot plate 20, and the glass substrate 202 is maintained together with a water-containing vessel 204 in a quartz container 203 for one hour or more. The glass substrate 202 which comes into contact with the hot plate 201 is maintained at approximately 350 °C by the heat from the hot plate 201. The interior of the quartz container 203 is maintained at approximately 100 °C because of evaporation of water. During the wet annealing, moisture (H 2 O) penetrates into the silicon oxide film, unstable or weak bonds in the silicon oxide film are decomposed to form -OH groups, and thus the quality of the silicon oxide film is improved. Fig. 23 is a schematic view of wet annealing using a hot wall system. In Fig. 23, guide grooves 304 are provided on a quartz boat 302 in the near center of a quartz reaction chamber 301 of the hot wall system. Substrates 303 provided with silicon oxide films such as a gate insulating film are placed horizontally along the guide grooves. In Fig. 23, although the glass substrate 303 is placed horizontally, it may be placed vertically or obliquely. A furnace heater 305 is provided on the outside of the quartz reaction chamber 301. The furnace heater 305 heats the interior of the quartz reaction chamber 301 to a given temperature. Numeral 306 represents a gas inlet unit and controls the flow rate of gas introduced into the quartz reaction chamber 301. Numeral 307 represents a gas exhaust unit provided on the quartz reaction chamber 301 which evacuate gas in the quartz reaction chamber 301 and controls the quartz reaction chamber 301 to a constant pressure. The gas exhaust unit 307 may be provided with a pump in order to rapidly exchange the gas in the quartz reaction chamber 301. An operational procedure of the hot wall system is explained. The interior of the quartz reaction chamber 301 is heated to 350 °C to 500 °C and preferably approximately 350 °C, and nitrogen is introduced through the gas inlet unit 306 to remove air in the quartz reaction chamber 301. After the quartz reaction chamber 301 is heated to a given temperature near 350 °C, the glass substrate 303 provided with the silicon oxide film such as a gate insulating film is inserted into the quartz reaction chamber 301 while continuing supply of nitrogen gas. The glass substrate 303 is maintained until it is heated to a given temperature near 350 °C. Steam is supplied instead of nitrogen into the quartz reaction chamber 301 through the gas inlet unit 306. The steam may be formed by bubbling water, or combustion of hydrogen with oxygen. It is preferable that the partial pressure of the steam introduced into the quartz reaction chamber 301 through the gas inlet unit 306 be 10 Torr or more. The gas introduced into the quartz reaction chamber 301 is exhausted from the gas exhaust unit 307, and the quartz reaction chamber 301 is maintained to a given pressure, for example, an atmospheric pressure. The glass substrate 303 is maintained at a temperature of 300 °C or more for a given time, for example 1 hour to 3 hours and is wet-annealed. After the wet annealing, the gas introduced into the quartz reaction chamber 301 through the gas inlet unit 306 is changed from the steam to oxygen or nitrogen, and the steam in the quartz reaction chamber 301 is evacuated from the gas exhaust unit 307 to reduce condensation in the quartz reaction chamber 301. The glass substrate 303 is removed from the quartz reaction chamber 301. The hot wall system makes the control of the flow rate of the steam easier than the hot plate, makes the temperature of the glass substrate uniform, and maintains the quartz reaction chamber to a high temperature of 300 °C or more. The quality of the silicon oxide film is therefore more effectively improved. According to experimental results, the overall spin density of the silicon oxide film is 9×10 17 spins/cm 3 when using the hot plate, and 3H10 17 spins/cm 3 when using the hot wall system with a partial pressure of water of 10 Torr or more, and thus the spin density when using the hot wall system decreases to approximately one third. The reliability of the FTF wet-annealed using such a hot wall system is significantly improved. The technical scope in the present invention is not limited to the above-mentioned embodiment, and various modifications may be added within the scope. Although a top-gate-type thin film transistor is exemplified in the above-mentioned embodiment, the present invention is also applicable to a bottom-gate-type thin film transistor in which a gate electrode lies at a lower layer and a silicon thin film lies at a higher layer. Amorphous silicon instead of polycrystalline silicon may be used in the silicon thin film. The thicknesses of the films and the conditions in the manufacturing steps can be modified according to demand. In the above-mentioned embodiment, the wet annealing is performed after forming the gate electrode facing the source and drain regions and the channel region separated by the gate insulating film, another wet annealing step may be provided after forming the underlying SiO 2 film, after forming the gate SiO 2 film or after forming the insulating interlevel film. When wet annealing is performed immediately after forming the silicon oxide film, moisture rapidly penetrates into the silicon oxide film and thus the annealing time can be reduced to several minutes. Fig. 15 shows an active matrix substrate configuration such as a liquid crystal display device formed by the above-mentioned method for making the thin film transistor. In the active matrix substrate 811 shown in Fig. 15, a source line driver circuit 812 and a gate line driver circuit 821, of a complementary thin film transistor composed of a silicon thin film, are formed together with a pixel matrix 822 on a common transparent substrate. The source line driver circuit 812 includes a shift resistor 813, sample hold circuits 817, 818, 819 and video signal busses 814, 815 and 816, and the gate line driver circuit 821 includes a shift resistor 820 and a buffer 823 if necessary. The pixel matrix 822 includes a plurality of source lines 826, 827 and 828 connected to the source line driver circuit 812, a plurality of gate lines 824 and 825 connected to the gate line driver circuit 821, and pixels 833, 833 connected to the source lines and gate lines. Each pixel includes a TFT 829 and a liquid crystal cell 830 comprising a pixel electrode, a counter electrode 831 and a liquid crystal. The shift resistors 813 and 820 may be replaced with other circuits having functions for sequentially selecting the source lines and gate lines, for example, counters or decoders . A clock signal CLX, a start signal DX, and video signals V1, V2 and V3 are input to the input terminals 834, 835 and 836, respectively, of the source line driver circuit, whereas a clock signal CLY and a start signal DY are input to the input terminals 837 and 838, respectively, of the gate line driver circuit. A liquid crystal display device (liquid crystal display panel) manufactured by using the above-mentioned active matrix substrate will now be exemplified. The liquid crystal display device (liquid crystal display panel) includes, as shown in Fig. 16, for example, a back light 900, a polarization plate 922, an active matrix substrate 923, a driver circuit section 9231 provided on the active matrix substrate, a liquid crystal 924, a counter substrate (color filter substrate) 925 and a polarization plate 926. An electronic apparatus formed of the liquid crystal display device (liquid crystal display panel) includes, as shown in Fig. 17, a display image output source 1000, a display image processing circuit 1002, a display driving circuit 1004, a display panel 1006 such as a liquid crystal panel, a clock generating circuit 1008 and an electric power source 1010 . The display image output source 1000 includes memories, such as ROMs and RAMs, and a tuning circuit for tuning and outputting television signals, and outputs display information, for example, video signals based on clocks from the clock generating circuit 1008. The display image processing circuit 1002 processes and outputs display information based on clocks from the clock generating circuit 1008. The display image processing circuit 1002 may include an amplifying and polarization reversion circuit, a circuit with parallel data input, a rotation circuit, a gamma correction circuit and/or a clamp circuit. The display driving circuit 1004 includes a scanning line driving circuit and a data line driving circuit and drives the liquid crystal panel 1006 for display. The electrical power circuit 1010 supplies electrical power to these circuits. Examples of electronic apparatuses having such a configuration include liquid crystal projectors as shown in Fig. 18, personal computers (PC) as shown in Fig. 19 and engineering work stations for multimedia, pagers as shown in Fig. 20, portable phones, word processors, electronic notebooks, portable electronic calculators, car navigation systems, POS terminals, and other devices provided with touch panels. The liquid crystal projector shown in Fig. 18 uses a transparent liquid crystal panel as a light valve including, for example, a triple-prism-type optical system. In the projector 1100 shown in Fig. 18, projection light emerging from a lamp unit 1102 for a white light source is separated into three primaries, R, G and B by a plurality of mirrors 1106 and two dichroic mirrors 1108 inside a light guide 1104, and the three primaries are introduced into their respective liquid crystal panel 1110R, 1110G and 1110B. Light beams modulated in the liquid crystal panels 1110R, 1110G and 1110B are incident on a dichroic prism 1112 from three directions. Red light beams R and blue light beams are bent by 90 in the dichroic prism 1112 whereas green beams G goes straight ahead, hence these separated images are synthesized and a color image is projected onto a screen through a projection lens 1114. The personal computer shown in Fig. 19 includes a main body 1204 provided with a keyboard and a liquid crystal display screen 1206 comprising a liquid crystal panel. The pager shown in Fig. 20 includes a liquid crystal display substrate 1304, a light guide provided with a back light 1306a, a circuit board 1308, first and second shielding plates 1310 and 1312, two elastic conductors 1314 and 1316, and a film carrier tape 1318 which are packaged in a metallic frame 1302. The two elastic conductors 1314 and 1316 and the film carrier tape 1318 are provided for connecting the liquid crystal display substrate 1304 with the circuit substrate 1308. The liquid crystal display substrate 1304 is composed of two transparent substrates 1304a and 1304b and a liquid crystal panel encapsulated therebetween and forms a dot-matrix-type liquid crystal display panel. A driving circuit 1004 shown in Fig. 17 and a display information processing circuit 1002 may be provided on one transparent substrate. Other circuits not mounted on the liquid crystal display substrate 1304 can be mounted on the circuit board 1308 in Fig. 18 as external circuits of the liquid crystal display substrate. The pager shown in Fig. 20 requires a liquid crystal display substrate 1304 and a circuit board 1308. When a liquid crystal display device is used as a part in an electronic device and a display driving circuit is mounted on a transparent substrate, the minimum unit of the liquid crystal display device is a liquid crystal display substrate 1304. Alternatively, a liquid crystal display substrate 1304 fixed to a metallic frame 1302 as a casing can be used as a liquid crystal display device as a part of an electronic device. In a back light type, a liquid crystal display device is fabricated by assembling a liquid crystal display substrate 1304 and a light guide 1306 provided with a back light 1306a into the metallic frame 1302. Alternatively, as shown in Fig. 21, a tape carrier package (TCP) 1320 composed of a polyimide tape 1322 provided with a metallic conductive film and an IC chip 1324 mounted thereon is connected to one of two transparent substrates 1304a and 1304b in a liquid crystal display substrate 1304 in order to used as a liquid crystal display device which is a part of the electronic device. The present invention is not limited to the above-mentioned examples and permits various modifications within the scope of the present invention. For example, the present invention is applicable to electroluminescence devices and plasma display devices other than various liquid crystal panels. [Industrial Applicability] In accordance with the method for making the thin film transistor as described above, by the wet annealing treatment after forming the gate electrode facing the source and drain regions and the channel region separated by the gate insulating film, bonds between atoms in the silicon oxide films such as the gate insulating film are stabilized by means of moisture, hence the change in electrical characteristics of the thin film transistor is reduced, resulting in improved reliability. In particular, wet annealing under conditions of a temperature of 300 °C or more and for a duration of at least one hour can effectively reduce the change in V gs -I ds characteristics in the BT test and the current stress test.

Claims: A method for making a thin film transistor comprising a channel region composed of a non-single-crystal silicon thin film (17) facing a gate electrode (19) with a gate insulating film (18) of a field effect transistor therebetween, said gate insulating film (18) consisting of a film of silicon oxide alone, the method characterized by : said gate insulating film (18) being wet-annealed in a moist atmosphere at least after forming said gate insulating film (18). A method for making a thin film transistor according to claim 1, wherein said gate insulating film (18) is formed by a PECVD process or a TEOS-PECVD process. A method for making a thin film transistor according to any one of claims 1 to 2, wherein said wet annealing in a moist atmosphere is performed at a temperature of 300 °C or higher and for a duration of one hour or more. A method for making a thin film transistor according to any one of claims 1 to 3, wherein said method further comprises a step forming an insulating interlevel film (21) composed of a silicon oxide film which covers said non-single-crystal silicon thin film or said gate electrode (19), said wet annealing being performed after forming said insulating interlevel film (21). A method for making a thin film transistor according to claim 4, wherein said insulating interlevel film (21) is a silicon oxide film formed by a TEOS-PECVD process. A method for making a thin film transistor according to claim 1, wherein an underlying insulating film (15) composed of a silicon oxide film is formed on the glass substrate (14) and said non-single-crystal silicon thin film is formed on said underlying insulating film (15). A method for making a thin film transistor according to claim 6, wherein said annealing is performed in a moist atmosphere after forming said underlying insulating film (15). A method for making a thin film transistor according to either claim 6 or 7, wherein said underlying insulating film (15) is formed by a PECVD or TEOS-PECVD process. A method for making a thin film transistor according to any one of claims 6 to 8, wherein the thickness of said underlying insulating film (15) is in the range from 100 nm to 500 nm. A method for making a thin film transistor according to claim 1, wherein said gate electrode (19) is on a substrate (14); and said substrate provided with at least said gate insulating film (18) is inserted into a hot wall system and is subjected to wet annealing in a moist atmosphere. A method for making a thin film transistor according to claim 10, wherein said wet annealing is performed in a moist atmosphere having a partial pressure of water of 10 Torr or more. A method for making a thin film transistor according to either claim 10 or. 11, wherein said wet annealing is performed at a temperature of 300 °C to 500 °C. A method for making a thin film transistor according to either claim 10 or 11, wherein said wet annealing is performed at a temperature of 300 °C to 500 °C, for a duration of one hour or more.

Inventors: ISHIGURO HIDETO, NAKAZAWA TAKASHI, ISHIGURO, HIDETO, NAKAZAWA, TAKASHI, ISHIGURO, Hideto, Seiko Epson Corporation, NAKAZAWA, Takashi, Seiko Epson Corporation
Applicants: SEIKO EPSON CORP, SEIKO EPSON CORPORATION
Application year: 1997
Main classification: H01L29
IPC codes: H01L29, G02F1, H01L21