Conditional restore for execution unit

Abstract: A circuit for conditionally restoring an execution unit in a computer processor, to reduce power consumption. Execution units, such as an arithmetic logic unit, shift/rotate unit, multiply unit, etc., have bits in transit that flow through a series of logic gates. These gates must be precharged after an operation has occurred to prepare the unit for the next operation. The conditional restore circuit evaluates either the data input to the execution unit, or the data output from the execution unit, to determine whether an operation has occurred. The precharge device for the execution is turned on only when the evaluation indicates that an operation has just occurred. The circuit includes an AND gate whose output controls the precharge device, and whose inputs include one line from the evaluation circuit, and one line for cycling (the system clock). In an embodiment wherein the execution unit has two operand multiplexers which receive the data input, the evaluation circuit includes two select line respectively connected to the multiplexers, and to inputs of the AND gate. In an alternative embodiment wherein the execution unit has data output in the form of a TRUE line and a COMPLEMENTARY line, the evaluation circuit includes a NOR gate means having a first input connected to said TRUE line, a second input connected to said COMPLEMENTARY line, and an output connected to said first input of the AND gate.

Description: The present invention generally relates to computer systems, and more particularly to electrical power consumption by memory arrays such as static random access memory. The present invention is directed to a method, circuit and device for conserving power required by restore operations for the memory array. Conventional computers use several pieces of interconnected hardware, including input/output devices for the user interface (such as a keyboard and display), a permanent storage device (such as a magnetic or optical disk), a temporary memory device (such as random access memory or RAM), and a central processing unit (CPU or processor) which accesses the permanent storage and temporary memory when carrying out program instructions. The present invention relates to power consumption by these devices, particularly by temporary memory devices such as RAM, and execution units in the CPU, such as an arithmetic logic unit. There are basically three types of RAM: dynamic RAM, static RAM, and pseudo-static RAM. Dynamic RAM stores data in capacitors, that is, it can hold data for only a few milliseconds, so DRAM is typically refreshed (precharged) using external refresh circuitry. Pseudo-static RAM is like DRAM with internal refresh circuitry. Static RAM is a read-write memory array whose storage cells are typically made up of four or six transistors forming flip-flop elements that indefinitely remain in a given binary state (i.e., 1 or 0, corresponding respectively to high or low voltage states) until the information in the cell is intentionally changed, or the power to the memory circuit is shut off, so this memory does not need to be regularly refreshed. It is only necessary to restore (electrically precharge) the SRAM array after or before each evaluation (read or write operation). In a traditional (sense amplifier) memory array, the complete array is restored even though only a small segment of the array is being accessed, resulting in excess power consumption by the array. In addition, the entire array is restored every clock cycle or by some other form of periodic signal and will therefore be restored even if the array is idle (no read/write). Although power considerations are not significant for mainframe or desktop computers, there is a continual attempt to reduce overall power consumption in portable computers that often run on batteries. In some prior art SRAM designs such as those referred to as a clocked dynamic array, the memory array is broken into groups of "bit lines." See, e.g., U.S. Patent Nos. 4,972,377 and 5,191,554. In this way, only the group containing the memory location to be accessed is required to be restored. If such a scheme were employed, it would conserve power. These prior designs still require the entire array, i.e., all groups of bit lines, to be restored every clock cycle even if the array is idle (no read or write operations), and the SRAM is usually not accessed every cycle (e.g., a level 2 cache), so this requires additional, unneeded power. It would, therefore, be desirable to reduce power consumption by conditionally restoring only the accessed segments of static RAM. It would be further advantageous if this were also applicable to other circuit functions in the computer system, such as execution units in the CPU. European patent application 0 827 151 discloses a sense amplifier in which the potential at a data line is compared to a reference and sense amplifiers are deactivated in response to the comparison. It does not evaluate whether the circuit with which the sense amplifier is associated with has performed an operation. It is therefore one object of the present invention to provide a system and method to reduce power consumption in circuit functions such as execution units for computer processors. It is another object of the present invention to provide such a system and method which does not require restoring the execution unit when it is idle. It is yet another object of the present invention to provide such a system and method which can be easily implemented with conventional designs for execution units. The foregoing objects are achieved in a system according to claim 1 and a method according to claim 8. Preferably, the restoring means includes gate means such as an AND gate. In an embodiment wherein the evaluating means evaluates the data input to the execution unit, the execution unit has first and second operand inputs emanating, respectively, from first and second operand multiplexers which receive the data input, and the evaluating means includes a first select line connected to the first operand multiplexer and the first input of the gate means, and a second select line connected to the second operand multiplexer and a third input of the gate means. The execution unit can be prevented evaluating (and consequently being precharged), by de-asserting all selects to the operand multiplexers, and power consumption by the restore phase (clock switching, etc.) is eliminated by gating the restore clock with the select signals. Embodiments of the invention will now be described with reference to the accompanying drawings, in which: Figure 1 is a representation of a conditional restore circuit which precharges a circuit function based on control logic associated with the data input to the circuit function; and Figure 2 is a block diagram of one embodiment of the present invention corresponding to the conditional restore circuit of Figure 1, for precharging an execution unit in a computer processor. The present invention is directed to a computer system having components which require electrical restoration, or precharging, such as an execution unit (like an arithmetic logic unit) in a computer processor. These components are examined in order to determine when they have been accessed, so as to minimize power consumption by allowing the restore to occur only when the component has actually been accessed. As explained further below, the approach of the present invention involves examination of the incoming control logic ( Figures 1 and 2 ). With reference now to the figures, and in particular with reference to Figure 1 , there is depicted one embodiment 10 of the conditional restore circuit of the present invention. Conditional restore circuit 10 is comprised of a generalized circuit function 12 (which, as explained in conjunction with Figure 2 , can be any one of a number of devices such as an execution unit), an evaluate circuit 14 , and means for restoring circuit function 12 , the restoring means comprising a gate 16 which examines the output of evaluate circuit 14 every clock cycle. Evaluate circuit 14 has as its input control logic which is related to the data that is fed into circuit function 12 . Every clock cycle, evaluate circuit 14 periodically determines whether circuit function 12 has been accessed based on the control logic. If it has, then the output of gate 16 turns on to precharge circuit function 12 . In this manner, circuit function 12 is restored only when necessary. In this embodiment, neither gate 16 nor evaluate circuit 14 are connected in any manner to the output of circuit function 12 . The same idea can be alternatively implemented by keeping circuit function 12 held in precharge until released by the evaluate circuit. A further example is given of the general circuit of Figure 1 . Figure 2 represents a conditional restore circuit for an execution unit which is responsive to incoming control logic. With further reference to Figure 2 , the depicted conditional restore circuit 30 is adapted to restore an execution unit 32 in a central processing unit (CPU). Those skilled in the art will appreciate that there are a variety of such execution units used in conventional processors that can take advantage of the present invention, including arithmetic logic units (ALUs), shift/rotate units, multiply units, etc., having bits in transit that flow through a series of logic gates. Two inputs (operands A and B) are used to access and manipulate execution unit 32 . These inputs to execution unit 32 are outputs of respective multiplexers 34 and 36 , which in turn have as inputs a plurality of source lines 34a , 34b , 34c and 34d , and 36a , 36b , 36c and 36d , respectively. The source lines carry the information required to operate execution unit 32 , such as an instruction, data value, or address. Source lines 34a-34d and 36a-36d can be any size (width), e.g., 32 bits. The multiplexers 34 and 36 also have respective select lines 38a, 38b, 38c and 38d , and 40a, 40b, 40c and 40d which activate the multiplexers so that, when the select lines are de-asserted, the multiplexers and execution unit 32 are idle. Select lines 38a-38d and 40a-40d are inputs to an OR gate 41 whose output is one input to an AND gate 42 , having a second input which is connected to the system clock. In this manner, it is possible to prevent execution unit 32 from evaluating (and consequently being precharged), by de-asserting all selects to the operand multiplexers. Although the execution unit would be idle for that particular cycle, power would still be consumed by the restore phase (clock switching, etc.) if it were not for gate 42 . Restore power can be eliminated by gating the restore clock with the select signals. Thus, the restore operation is performed only if execution unit 32 has been previously (immediately) evaluated. Clock power used by this method is insignificant since it only goes to one gate per execution unit.

Claims: A system comprising: first (34, 54) and second (36, 56) operand multiplexers having a plurality of data inputs (34a-34d, 36a-36d, 54a-54d, 56a-56d); an execution unit (32, 52) having a data input and a data output, and at least first and second operand inputs emanating, respectively, from said first and said second operand multiplexers; and means for electronically restoring the execution unit by precharging logic components in the execution unit, the means comprising: means (14, 14') for evaluating the data input of the execution unit to determine whether the execution unit has performed an operation; and means (16, 16'), connected to said evaluating means, for restoring the execution unit if said evaluating means determines that the execution unit has performed the operation, wherein said evaluating means includes a first select line connected to said first operand multiplexer, and a second select line connected to said second operand multiplexer. The system of Claim 1 wherein said restoring means further comprises: a precharge device connected to the execution unit (32, 52); and a gate (16, 16') having a first input connected to an output of said evaluating means (14, 14'), a second input connected to a system clock, and an output connected to said precharge device. The system of Claim 1 wherein said evaluating means (14, 14') evaluates the data input of the execution unit (32, 52). The system of Claim 1 wherein said restoring means includes an AND gate (42, 62) having a first input connected to an output of said evaluating means (41, 64), a second input connected to a system clock, and an output connected to the execution unit. The system of Claim 3 wherein the data input to the execution unit (32, 52) has associated control logic; and said evaluating means evaluates the data input by evaluating said control logic. The system of Claim 4 wherein: the execution unit (32) has at least first and second operand inputs emanating, respectively, from first and second operand multiplexers (34, 36) which receive the data input; and said evaluating means (41) includes a first select line connected to said first operand multiplexer and said first input of said AND gate, and a second select line connected to said second operand multiplexer and a third input of said AND gate. The system of Claim 1 wherein the execution unit (32, 52) has at least first and second operand inputs emanating, respectively, from first and second operand multiplexers (34, 36, 54, 56) which receive the data input, said multiplexers further being respectively connected to first and second select lines. A method of conditionally restoring an execution unit (32, 52) which performs an operation for a computer processor, the method comprising the steps of: maintaining a precharge device for the execution unit in an idle state wherein the execution unit is not restored; periodically evaluating the execution unit to determine if it has performed an operation; and sending a signal to the precharge device when said evaluating step indicates that the operation has been performed, and thereafter returning said precharge device to said idle state.

Inventors: CIRAULA MICHAEL KEVIN, LATTIMORE GEORGE MCNEIL, YEUNG GUS WAI-YAN, CIRAULA, MICHAEL KEVIN, LATTIMORE, GEORGE MCNEIL, YEUNG, GUS WAI-YAN
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1997
Main classification: G11C11
IPC codes: G11C7, G11C11