Auxiliary translation lookaside buffer for assisting in accessing data in remote address spaces

Abstract: A computer system includes a data processor, a primary translation lookaside buffer for storing page table entries and translating virtual addresses into physical addresses, local memory coupled to the data processor for storing data and computer programs at specified physical addresses, and remotely located memory coupled to the data processor by a computer network for storing data at specified remote physical addresses. The computer system further includes a remote translation lookaside buffer (RTLB) that stores a plurality of remote page table entries. Each remote page table entry represents a mapping between a range of physical addresses and a corresponding range of remote physical addresses. The primary translation lookaside buffer translates a virtual address asserted by the data processor into a physical address. When the physical address does not correspond to a location in the local memory, the RTLB determines whether the physical address matches at least one of the remote page table entries stored in the RTLB, and selects one of those remote page table entries when at least one match is found. The RTLB's selection circuitry selects a single remote page table entry in accordance with predefined RPTE selection criteria when two or more of the remote page table entries match the physical address. Then, a remote physical address is generated by combining a portion of the selected remote page table entry with a portion of the physical address.

Description: The present invention relates generally to a computer system and to a translation lookaside buffer and to a method of operating such a system. Referring to Fig. 1, there is shown a distributed computer system 100 that includes a plurality of processor clusters 102. Each cluster 102 will typically include one to four symmetric processors 104 that are coupled via a common bus 106 to a local memory store 108. One or more of the clusters may also include secondary memory 110 (non-volatile memory such as magnetic disc storage). Access to the local memory store 108 (and secondary memory 110, if present) shared by all the processors in the cluster 102 is governed by a memory controller 112 that also can send requests via a network 114 to pull in pages of data stored in the memory stores or secondary memory of other clusters 102 or other devices coupled to the network 114. Each processor 104 in a cluster 102 includes its own local cache memory 120 that must be kept coherent (i.e., consistent) with the contents stored in the cache memories of the other processors in the system. Each processor 104 in a cluster 102 also includes a translation lookaside buffer (TLB) 122, the purpose of which will be explained below. Virtual Memory Management Within a Single Processor Cluster The following is a very brief explanation of virtual memory management and the role of the TLB in virtual memory management. In this initial explanation, accessing data stored outside the cluster will not be considered. Referring to Figs. 2 and 3, application programs typically access data using virtual addresses. For instance, every process running in a computer system may have a virtual address space of 4 Gigabytes, using address values ranging from 0 (zero) to OFF FFF FFF 16 (4,284,967,295 10 ). However, the amount of primary physical memory in the system will generally be much less than N x 4 Gigabytes, where N is the number of simultaneously active processes. Rather, each process will generally use only a very small fraction of its full address space during any short period of time, and each "page" of virtual memory address space that is actively being used will be mapped into a page of primary physical memory 108 using a data structure called a page table 130. A "page" is typically sized between 1K and 16K bytes, with 4K bytes being a frequently used page size. The page table 130, which is divided into pages called page table pages 132, typically contains a distinct entry, called a page table entry (PTE) 134 for each page of virtual memory that has been defined to store data or instructions. The PTE 134 for a particular virtual memory page directly or indirectly includes a tag 136 that identifies the virtual page to which it applies, and a physical memory page address (PPA) 138 that identifies where the corresponding physical memory page is located primary memory 108 or secondary memory 110. Like a conventional cache memory that stores the data most recently used by a processor, the translation look aside buffer (TLB) 122 stores the PTEs most recently used by the processor. The TLB 122 in each processor not only acts as a cache memory for PTEs, it is also the device that translates virtual addresses into physical addresses. In particular, to translate a virtual memory address into a physical memory address, the high order X-N bits of the address (where X is the number of bits in each address and 2 N is the number of bytes in each page) of the virtual address are compared with the tags of the PTE's in the TLB 122. If the high order address bits match the tag of a valid PTE (i.e., a PTE in the TLB 122 whose valid flag 140 is set to "1" or True), then the TLB generates a physical address value (PA) in which the X-N high order bits of the virtual address are replaced with the physical page address (PPA) 138 in the PTE. If the PTE 134 required to translate a virtual address is not currently located in the TLB 122, a request is sent to the memory controller 112 to locate and send that PTE to the TLB. After the required PTE 134 is stored in the TLB 122 the virtual address to physical address translation process described above is performed by the TLB 122. If a copy of the data in the resulting primary physical memory address is stored in cache memory 120, then the processor 104 accesses the addressed data directly in its cache memory 120. If the addressed data is not in cache memory 120, the memory controller 112 retrieves the addressed data from primary memory 108 and stores it in the cache memory 120. Then the processor 104 accesses the addressed data from its cache memory 120. When a process attempts to address data that is not currently stored in primary memory 108, but is stored in the local secondary memory 110, the PTE 134 corresponding to the virtual address specified by the program being executed will have its valid flag 140 set to False, indicating that the PTE cannot map the address to a primary physical memory page, but other flags 142 in the PTE will indicate that the page is stored in local secondary memory 110. When the PTE for translating a virtual address is found to be invalid, this is called a "page fault." In response to the page fault the operating system of the cluster 102 will request the memory controller 112 to retrieve the specified page from secondary memory 110 and store it in a free page in primary memory 108. After the page retrieval is completed, the PTE is updated to indicate the page's new location in primary memory 108 and its valid flag is set to True, and then the application program requiring that data resumes execution using the page of data that has just been swapped in to primary memory. Extending the Address Space to Memory Outside the Cluster Referring to Figs. 1 and 4, many present day server computers are symmetric multiprocessor systems that use a bus based "snoop scheme" to maintain cache coherence. This architecture typically accommodates 4 to 16 processor systems reasonably well. However, for many applications such as database decision support, Web servers, multimedia storage and retrieval servers, online transaction processing, computer clusters, and the like, there is a need to scale to systems having more than 4 or 16 processors. A distributed system 100 having multiple symmetric processor clusters 102 can be used for such applications. WO 95/16964 discloses an address translation means for a distributed memory massively parallel processing system. This includes means for defining virtual addresses for processing elements (PEs) and memory relative to a partition of PEs under program control. Address references generated by a PE within a partition in virtual address mode are converted to logical addresses and physical addresses for routing on the network. EP-A-497600 discloses a memory access method for a multiprocessor system, in which each processor is capable of accessing the local memories of other processors. This is performed by first executing an address conversion into an intermediate real address forming the address space shared by the system, and then executing an address conversion from the intermediate real address into a real address of the memory which is the object of the accessing operation. US 5230045 discloses a system in which virtual addresses from multiple address spaces are translated to real addresses in main memory by generating for each virtual address an address space identifier (AID) identifying its address space. Then, the virtual address and its AID are used to obtain the real address. If a processor's local cache does not have data for a virtual address and cannot translate the virtual address to a real address, the local cache provides the virtual address on a bus. A dedicated VLSI map cache is connected to the bus for receiving virtual addresses and providing real addresses. US 5117350 discloses a computer system having plural nodes interconnected by a common broadcast bus. The system has dynamically configurable memory which may be located within the system address space of a distributed system architecture. The memory in the system address space is addressable by system physical addresses which are isolated from the physical addresses for memory in each node. The node physical addresses are translatable to and from the system physical addresses by partition maps located in partition tables at each node. US 5247629 discloses a multiprocessor system having global data replication in each of the local memories, each associated with one of the processors. This is performed by translating global data logical addresses into addresses conventionally defined as real. This is then followed by a translation of the real address into a physical address generally differing for each local memory. There are, in general, two ways of extending the scalability of symmetric processor systems. The first method uses "message passing" to extend scalability, and the second method uses a "shared memory" paradigm. The present invention falls is the latter class. In the distributed system 100 each cluster 102 is perceived as a single node whose address space is extended to include a global address space. To map sections of the global address space in the physical address space of each cluster, a remote page table 150 (or portions of a remote page table) can be stored in the local memory 108/110 of each cluster 102. The remote page table 150 contains remote page table entries (RPTEs) 152, each of which is used to translate a range of physical addresses into a range of remote physical addresses. From the viewpoint of each cluster, the global address space is considered to be a "remote physical address space". The size of the address space represented by each RPTE 152 may differ from the size of the address space associated with each PTE 132. Thus, it is possible that one RPTE 152 might used to map a large address space (e.g., 256 Mbytes) from physical address space to remote physical address space (also sometimes called the global address space). Translating a physical address to a remote physical address can be slow because of the need to first access the page in primary memory 108 that stores the corresponding RPTE 152 in the remote page table 150, and then translate the address using appropriate software. If the cluster's memory 108 does not store the page of the remote page table containing the required RPTE, that page of the remote page table 150 will first need to be downloaded from an appropriate remotely located processor or cluster in the distributed system 100. Once the required RPTE 152 is found and the address translation into a remote physical address (RPA) is performed, then a request is transmitted via the network 114 to load a copy of the page being addressed into the requesting cluster's local memory 108. While many of the delays associated with retrieving remotely located data are hard to avoid, the present invention provides mechanisms for speeding the translation of physical addresses into the remote physical addresses, and also for reducing the need to load pages of the remote page table 150 into local memory 108. Particular and preferred aspects of the invention are set out in the accompanying independent and dependent Claims. A computer system according to an embodiment of the invention includes a data processor, a primary translation lookaside buffer (TLB) for storing page table entries and translating virtual addresses into physical addresses, local memory for storing data and computer programs at specified physical addresses, and remotely located memory coupled to the data processor by a computer network for storing data at specified remote physical addresses. The computer system further includes a remote translation lookaside buffer (RTLB), also called an auxiliary TLB, that stores a plurality of remote page table entries. Each remote page table entry represents a mapping between a range of physical addresses and a corresponding range of remote physical addresses. The primary translation lookaside buffer translates a virtual address asserted by the data processor into a physical address. When the physical address does not correspond to a location in local memory, the RTLB determines whether the physical address matches at least one of the remote page table entries stored in the RTLB, and selects one of those remote page table entries when at least one match is found. Then, a remote physical address is generated by combining a portion of the selected remote page table entry with a portion of the physical address. Each remote page table entry stored in the RTLB includes address range size data indicating how large a physical address range is mapped into remote physical addresses by that remote page table entry. Two or more of the remote page table entries stored in the RTLB can map overlapping physical address ranges. The RTLB's selection circuitry includes circuitry for selecting a single remote page table entry in accordance with predefined RPTE selection criteria when two or more of the remote page table entries match the physical address. Each remote page table entry stored in the RTLB has an associated index position in the RTLB. In one embodiment, the predefined RPTE selection criteria is to select the one of the two or more remote page table entries that match the physical address having a lowest index position in the RTLB. Exemplary embodiments of the invention are described hereinafter, by way of example only, with reference to the accompanying drawings in which: Fig. 1 is a block diagram of a distributed computer system having a number of multiprocessor clusters interconnected by a communications network. Fig. 2 depicts data structures associated with page tables for virtual memory management. Fig. 3 depicts the structure of a page table entry. Fig. 4 depicts data structures associated with a remote page table. Fig. 5 schematically depicts the process by which a virtual address is translated first to a physical address, and then to a remote physical address in accordance an embodiment of the present invention. Fig. 6 depicts the structure of an embodiment of a remote lookaside translation buffer (RTLB). Fig. 7 depicts the structure of a remote page table entry. Fig. 8 depicts how overlapping entries in a remote lookaside translation buffer are utilized. Fig. 9 is a block diagram of a one node of a distributed computer system. Referring to Figs. 1 and 5, in an embodiment of the invention, when the memory controller 112 is called upon to translate a physical address (PA) into a remote physical address (RPA), instead of having to retrieve the corresponding remote page table entry 152 from memory 108 and then convert the address using software, the embodiment of the invention provides the memory controller 112 with a secondary or auxiliary TLB, herein called a cluster TLB or remote TLB (RTLB) 160. In some respects, the RTLB 160 works in much the same way as the regular TLB 122, except that its job is to store a set of remote page table entries (RPTEs) and to convert a physical address (PA) into a remote physical address (RPA) in hardware in a single processor clock cycle. The RLTB 160 speeds up the process of converting a physical address (PA) into a remote physical address (RPA) considerably both by caching RPTEs and by performing the address conversion in hardware instead of software. Of course, a physical address is converted by the RTLB into a remote physical address only if the physical address does not correspond to a location in either the local primary memory 108 or the local secondary memory 110. Referring to Figs. 6 and 7, the RTLB 160 includes a content addressable memory (CAM) 162, a filter-selector 164, a static random access memory (SRAM) 166, and an address bit merge circuit 167 for generating the remote physical address (RPA) output by the RTLB 160. In one embodiment of the present invention, the CAM 162 and SRAM 166 together store 32 RPTEs, with the CAM 162 storing the tag portion of each RPTE 152 and the SRAM 166 storing the remote physical address portion of each RPTE. The RPTEs in this embodiment utilize variable address space size entries. The size of the address space represented by each RPTE 152 is governed by the size value stored in the CAM portion of the entry. In particular, each bit of the size value masks out a corresponding bit of the PA tag. The size value is fully decoded, meaning that if the Nth bit of the size value is set equal to 1, then all of the size bits less significant that the Nth bit are also set equal to 1. For each additional bit of the size value that is set, the size of the address space represented by the RPTE is increased by an additional factor of 2. The smallest address space that can be represented by an RPTE is one page (e.g., 4K bytes), and the largest address space that can be represented by an RPTE is 64K pages (e.g., 256 Mbytes). Referring to Fig. 8, the RTLB 160 of the present embodiment allows the entries in the RTLB to be arranged so that a specified physical address can be simultaneously matched by more than one entry. That is, simultaneously valid RPTEs in the RTLB can represent overlapping address ranges. This is directly contrary to normal TLB operation, in which all valid PTEs must represent non-overlapping address ranges. As will be explained below, the ability to have RPTEs representing overlapping address ranges is useful in a number of contexts, such as when working with very large remotely stored files and very large remotely stored databases. The 32 entries in the RTLB are organized into four groups of eight entries (entries 0:7, 8:15, 16:23 and 24:31). While the physical address ranges of the RPTEs in any one group may overlap, it is the responsibility of the operating system 180 (see Fig. 9) to make sure that the RPTEs in different groups do not have overlapping address ranges. As just indicated, the contents of the RTLB are controlled by the operating system 180 of the associated processors 104. That is, the operating system decides what RPTEs to store in the RTLB 160, which RPTEs to evict from the RTLB, and where to position the RPTEs within the RTLB 160. For most purposes, the operating system updates the contents of the RTLB using criteria similar to the criteria used to determine the contents of the TLB 122. However, in order to use the "overlapping address range" feature of the RTLB 160, the operating system must also include additional criteria for positioning overlapping address range entries within the same group of entries in the RTLB, and within each such group must also store the larger address range entries at higher index positions than the smaller address range entries. In an alternate embodiment, the entire RTLB is treated as a single group of RPTEs. In this embodiment, matches in lower index positions still override matches in higher index positions, and thus the operation system must still store larger address range entries at higher index positions than the smaller address range entries. The CAM 162 works as follows. When a physical address is presented to the RTLB 160 (which generally means that the physical address is not located in local primary or secondary memory 108 or 110), the physical address is presented simultaneously to all entries of the CAM 162. Each CAM entry 162 generates a match signal, match;, whose boolean value is equal to: match i = Valid i && ( Size i (0) OR { PA i (0) = PA(0)}) && ( Size i (1) OR { PATag i (1) = PA(1)}) ... && ( Size i (15) OR { PATag i (15) = PA(15)}) && ( PATag i (23:16) = PA(23:16)) where && represents the logical AND operation. In other words, a match signal equal to True is generated for a particular CAM entry if (A) the valid bit is set, and (B) all the upper address bits not masked by the Size value match the PA tag value in the CAM. The CAM outputs a match value for each and every CAM entry, as well as a hit/miss signal that is equal to 1 if the physical address PA presented to the CAM matches at least one entry in the CAM: Hit[0] = match 7 OR match 6 OR match 5 OR match 4 OR match 3 OR match 2 OR match 1 OR match 0 Hit[1] = match 15 OR match 14 OR match 13 OR match 12 OR match 11 OR match 10 OR match 9 OR match 8 Hit[2] = match 23 OR match 22 OR match 21 OR match 20 OR match 19 OR match 18 OR match 17 OR match 16 Hit[3] = match 31 OR match 30 OR match 1 OR match 4 OR match 3 OR match 2 OR match 1 OR match 0 Hit = HIT[3] OR Hit[2] OR Hit[1] OR Hit[0] The four sub-hit signals correspond to the four groups of CAM entries. The match values generated by the CAM are transmitted to a filter-selector 164. Within each of the four groups of CAM entries, the filter-selector 164 generates filtered match signals MatchF i that are all set to 0 (False) other than the lowest index match signal whose value is 1 (True). That is: MatchF i = Match i AND (no lower indexed Match value in same group is equal to 1) where MatchF i represents the filtered match signals. For instance, if most of a large file is stored at a first location in the system 100, but a segment of the file has been moved to a particular cluster 102 for updating, a first RPTE would be used to indicate the position of the entire file at the first location, and a second RPTE stored at a lower index position in the same group as the first RPTE would be used to indicate the position of the file segment that has been moved. If a physical address is presented to the RTLB that corresponds to the large file, but outside the moved segment, then only one match signal is generated, and that one match signal is passed by the filter-selector 164 to select a corresponding entry in the SRAM 166. If, however, a physical address is presented to the RTLB that corresponds to the moved segment of the large file, then two match signals are generated (one for the main file RPTE and one for RPTE for the moved segment). In this case the filter-selector 164 passes only one the match signal, the one at the lower index position corresponding to the moved segment, to the SRAM. As a result, the entry in the SRAM for mapping the moved segment is activated. The filter-selector 164 never passes more than one match signal to the SRAM 166. The SRAM 166 portion of the RTLB 160 stores one remote physical page address (RPPA) 168 for each entry (RPTE) stored in the RTLB. The remote physical page address 168 consists of a node-ID 170, a remote physical page address 172, and a size value 174 that together indicate the location of the data being addressed by a processor. The node-ID 170 indicates the node of the system 100 at which the addressed data is stored, the remote physical page address 172 indicates the address of the page or memory block at that node where the addressed data is stored, and the size value 174 indicates the size of the memory block addressed by the remote physical page address 172. The size value 174 also indicates how many of the least significant bits of the remote physical page address 172 must be replaced with corresponding address bits of the physical address being translated before sending out a page request to the network 114. For instance, if size value 174 were equal to 4, then the address of the remote page being addressed is generated by replacing the four least significant bits of the remote physical page address 172 with the corresponding four bits of the physical address being translated by the RTLB. The merge circuit 167 generates either a remote physical address or a remote physical page address, depending on the requirements of the network 114, by concatenating a portion of the remote physical page address stored in the selected RPTE with a portion of the asserted physical address. The number of address bits used from the asserted physical address depends on the size of the address range mapped by the selected RPTE. When the size of the address range mapped by the selected RPTE is equal to one page, only the low order address bits of the asserted physical address are used to specify a location within the specified remotely stored page and no address bits from the asserted physical address are used to generate the remote physical page address. As just indicated, the size value 174 is used by the merge circuit 167 to determine how many high order address bits to use from the selected RPTE and how many low order address bits to use from the asserted physical address. In particular, if S is the size value, and the page size is 4096 bytes, and the number of address bits in the remote physical page address 172 is 24, then the merge circuit 167 concatenates 24-S of the high order bits from the remote physical page address 172 with 12+S of the low order bits from the asserted physical address to generate a 36-bit remote physical address (plus a 12 bit node-ID, which is unaffected by the size value). Alternately, the merge circuit 167 concatenates 24-S of the high order bits from the remote physical page address 172 with S bits from the asserted physical address (i.e., the S bits just above the address bits used to specify a location within a page) to generate a 24-bit remote physical page address. Each remote physical page address 168 also includes a set of control flags 176 that can be used to govern the mode of memory access being requested. For instance, the control flags 176 may be used to indicate "read only" access or "read/write" access to the specified remote memory block. Referring to Figs. 8 and 9, when working with large files or databases, certain operating system calls (e.g., shmget() and mmap() in UNIX) can be used to set up the file in shared memory. However, such calls bring all of the file into memory, and thus even portions which are not needed are present in memory. This implies that "less memory" is available for other processes which are working on other objects and files. Moreover, in order to get the entire file into memory a number of TLB misses have to be endured. These TLB misses results in a slowdown of the operation in progress. An embodiment of the invention provides support for mapping a file, locking a portion of it in memory and then using that portion without having to lock the entire file in memory. For instance, initially the application using the large file or database can use a first call with a special "Initial_Map" flag to indicate the entire file that needs to be memory mapped. Then through a second call it can open various "windows" into the file and lock those "windows" in memory for as long as it needs to work on them. This method of using the RTLB is demonstrated by the following pseudocode. In the above example, the remote memory mapping command MMAP and un-mapping command DEMMAP are procedures provided by the operating system 180 and that are available for use by application programs 182 when working with remote files and databases. Typically, the MMAP and DEMMAP procedure calls would be generated by other operating system procedures in response to application procedure calls requesting use of specified remote files and file portions. In the above example, the mapping of the entire file with a first MMAP command uses an "INITIAL_MAP" flag, indicating that the file need not be locked in memory and that the file can be accessed on a read-only basis at a specified range of global addresses. The file portion mappings using a "WINDOW_MAP" flag indicate portions of the file that need to be locked in memory so that the requesting cluster can access and modify its contents. The DEMMAP commands with the "WINDOW_MAP" unlock previously locked file portions, and the DEMMAP command with the "INITIAL_MAP" flag eliminates the mapping between physical addresses and global addresses for the large file. While the present invention has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications may occur to those skilled in the art without departing from the scope of the invention. In the embodiment described above, when two or more of the remote page table entries stored in the RTLB that map overlapping physical address ranges match an asserted physical address, the RTLB's selection circuitry selects the one of the matching remote page table entries having a lowest index position in the RTLB. In an alternate embodiment, the RTLB's selection circuitry could select the one of the matching remote page table entries having a highest index position in the RTLB. In yet other embodiments, other RPTE selection criteria could be used. In alternate embodiments, the number of maskable address bits in the PA tag could be more or less than the 16 maskable address bits provided in the embodiment described above. By providing a larger number of maskable address bits, the size of largest address range mappable by a single RPTE would be increased.

Claims: A remote translation lookaside buffer RTLB (160), for use in a computer system (100) having a data processor (104), a primary translation lookaside buffer TLB (122) for storing page table entries PTEs (134) and converting virtual addresses into physical addresses, local memory (108) coupled to the data processor for storing data and computer programs at specified physical addresses, and remotely located memory coupled to the data processor by a computer network (114) for storing data at specified remote physical addresses; the remote translation lookaside buffer RTLB (160) comprising: memory (162, 166) for storing a plurality of remote page table entries RPTEs (168), each remote page table entry RPTE representing a mapping between a range of physical addresses and a corresponding range of remote physical addresses; and match circuitry (162) for determining whether an asserted physical address matches at least one of said remote page table entries stored in said memory; selection circuitry (164), coupled to said match circuitry, for selecting one of said remote page table entries stored in said memory in response to an asserted physical address when said match circuitry makes a positive determination; and output circuitry (167) for generating a remote physical address by combining a portion of said selected remote page table entry RPTE with a portion of said asserted physical address. The remote translation lookaside buffer of claim 1, each said remote page table entry stored in said memory including address range size data (174) indicating how large a physical address range is mapped into remote physical addresses by said each remote page table entry; wherein two or more of the remote page table entries stored in said memory can map overlapping physical address ranges; said selection circuitry including circuitry for selecting a single one of said remote page table entries in accordance with predefined RPTE selection criteria when said match circuitry determines that two or more of said remote page table entries match said asserted physical address. The remote translation lookaside buffer of claim 2, wherein said remote page table entries stored in said memory each have an associated index position in said memory; and said predefined RPTE selection criteria is to select the one of said two or more of said remote page table entries that match said asserted physical address having a lowest index position in said memory. The remote translation lookaside buffer of claim 2, wherein said remote page table entries stored in said memory each have an associated index position in said memory; and said predefined RPTE selection criteria is to select the one of said two or more of said remote page table entries that match said asserted physical address having a highest index position in said memory. A computer system that is coupled to a remotely located memory by a computer network (114) for storing data at specified remote physical addresses; the computer system comprising: a data processor (104), including a primary translation lookaside buffer TLB (122) for storing page table entries PTEs (134) and converting virtual addresses into physical addresses, local memory (108) coupled to the data processor for storing data and computer programs at specified physical addresses; and a memory controller (112) for managing access to the local memory and the remotely located memory, the memory controller including a remote translation lookaside buffer (160); said remote translaction lookaside buffer including: RPTE memory (162, 166) for storing a plurality of remote page table entries RPTEs (168), each remote page table entry RPTE representing a mapping between a range of physical addresses and a corresponding range of remote physical addresses; and match circuitry (162) for determining whether an asserted physical address matches at least one of said remote page table entries stored in said RPTE memory; selection circuitry (164), coupled to said match circuitry, for selecting one of said remote page table entries stored in said RPTE memory in response to an asserted physical address when said match circuitry makes a positive determination; and output circuitry (167) for generating a remote physical address by combining a portion of said selected remote page table entry with a portion of said asserted physical address. The computer system of claim 5, each said remote page table entry stored in said RPTE memory including address range size data (174) indicating how large a physical address range is mapped into remote physical addresses by said each remote page table entry; wherein two or more of the remote page table entries stored in said RPTE memory can map overlapping physical address ranges; said selection circuitry including circuitry for selecting a single one of said remote page table entries in accordance with predefined RPTE selection criteria when said match circuitry determines that two or more of said remote page table entries match said asserted physical address. The computer system of claim 6, wherein said remote page table entries stored in said RPTE memory each have an associated index position in said RPTE memory; and said predefined RPTE selection criteria is to select the one of said two or more of said remote page table entries that match said asserted physical address having a lowest index position in said RPTE memory. The computer system of claim 6, wherein said remote page table entries stored in said RPTE memory each have an associated index position in said RPTE memory; and said predefined RPTE selection criteria is to select the one of said two or more of said remote page table entries that match said asserted physical address having a highest index position in said RPTE memory. A method of operating a computer system (100) having a data processor (104), a primary translation lookaside buffer TLB (122) for storing page table entries PTEs (134) and translating virtual addresses into physical addresses, local memory (108) coupled to the data processor for storing data and computer programs at specified physical addresses, and remotely located memory coupled to the data processor by a computer network (114) for storing data at specified remote physical addresses; the steps of the method comprising: storing in a remote translation lookaside buffer RTLB (160) a plurality of remote page table entries RPTEs (168), each remote page table entry representing a mapping between a range of physical addresses and a corresponding range of remote physical addresses; translating (162), using said primary translation lookaside buffer, a virtual address asserted by said data processor into a physical address; when said physical address does not correspond to a location in said local memory, determining whether said physical address matches at least one of said remote page table entries stored in said RTLB; selecting (164) one of said remote page table entries stored in said RTLB when said match determining step makes a positive determination; and generating (167) a remote physical address by combining a portion of said selected remote page table entry with a portion of said physical address. The method of claim 9, each said remote page table entry stored in said RTLB including address range size data (174) indicating how large a physical address range is mapped into remote physical addresses by said each remote page table entry; wherein two or more of the remote page table entries stored in said RTLB can map overlapping physical address ranges; said selection circuitry including circuitry for selecting a single one of said remote page table entries in accordance with predefined RPTE selection criteria when said match determining step determines that two or more of said remote page table entries match said physical address. The method of claim 10, wherein said remote page table entries stored in said RTLB each have an associated index position in said RTLB; and said predefined RPTE selection criteria is to select the one of said two or more of said remote page table entries that match said physical address having a lowest index position in said RTLB. The method of claim 10, wherein said remote page table entries stored in said RTLB each have an associated index position in said RTLB; and said predefined RPTE selection criteria is to select the one of said two or more of said remote page table entries that match said physical address having a highest index position in said RTLB.

Inventors: AYBAY GUNES, VISHIN SANJAY, AYBAY, GUNES, VISHIN, SANJAY
Applicants: SUN MICROSYSTEMS INC, SUN MICROSYSTEMS, INC.
Application year: 1997
Main classification: G06F12
IPC codes: G06F12