Chopper comparator showing high speed and low power operations free of malfunction under variation of logical threshold voltage of invertor

Abstract: The present invention also provides a chopper comparator for comparing an analog input signal voltage (Vin) and a comparative reference voltage (Vref). The chopper comparator comprises the following elements. First and second input terminals (8, 9) are provided for receiving the analog input signal voltage (Vin) and the comparative reference voltage (Vref) respectively. A first capacitance (C1) is provided which has a first input side terminal being connected through a first switch (1) to the first input terminal (8). A second capacitance (C2) is provided which has a second input side terminal being connected through a second switch (2) to the second input terminal (9). A data latch circuit (12) is provided which is connected to first and second output terminals of the first and second capacitances (C1, C2). A third switch (3) is provided between the first and second input side terminals of the first and second capacitances (C1, C2), wherein after the first and second switches (1, 2) have turned OFF to discontinue applications of the analog input signal voltage (Vin) and the comparative reference voltage (Vref) to the first and second capacitances (C1, C2) respectively, then the third switch (3) turns ON to form a short circuit between the first and second input side terminals of the first and second capacitances (C1, C2).

Description: The present invention relates to a chopper comparator formed in a semiconductor integrated circuit, and more particularly to a chopper comparator showing high speed and low power operation free of malfunction under variation of a logical threshold voltage of invertor. Chopper comparators have been used as voltage comparators for analog-to-digital converters for converting analog signals to digital signals. The chopper comparator judges whether a voltage level of analog signals inputted is higher or lower than a comparative reference voltage. One of the chopper comparators is disclosed in IEEE Journal of Solid State Circuit, Vol. SC-20, No. 6, pp. 1138-1143, December 1985. A conventional chopper comparator will be described with reference to FIG. 1, which is a circuit diagram illustrative of the conventional chopper comparator, and FIG. 2, which is a timing chart illustrative of signal waveforms of the conventional chopper comparator. The conventional chopper comparator has two input terminals 8 and 9. An analog input voltage Vin is applied to input terminal 8. A comparative reference voltage Vref is applied to input terminal 9. The input terminal 8 is connected through a first switch 1 to a first capacitor C21. The input terminal 9 is connected through a second switch 2 to the first capacitor C21. The first capacitor C21 is charged with either the analog input voltage Vin or the reference voltage Vref. The conventional chopper comparator has a first invertor 23 having an input terminal connected to the first capacitor C21. The conventional chopper comparator has a second capacitor C22 connected to an output terminal of the first invertor 23. A third switch 19 is provided between the input and output terminals of the first invertor 23 so that the third switch 19 and the first invertor 23 are connected in parallel to each other to the first capacitor C21. A second invertor 24 is provided having an input terminal connected to the second capacitor C22. A fourth switch 20 is provided between input and output terminals of the second invertor 24 so that the fourth switch 20 and the second invertor 24 are connected in parallel to each other to the second capacitor C22. A data latch circuit 12 is provided having an input terminal connected to the output terminal of the second invertor 24. The conventional chopper comparator has an output terminal 15 connected to an output terminal of the data latch circuit 12. An output voltage Dout appears on the output terminal 15 as a result of the comparison of the input analog signal voltage level to the comparative reference voltage level. Operation of the above conventional chopper comparator will subsequently be described with reference to FIG. 2. The operation of the above conventional chopper comparator may be considered to be divided into two periods of time, for example, first and second periods. In the first period, the first, third and fourth switches 1, 19 and 20 are in ON state whilst the second switch 2 is in OFF state. Since the first switch 1 is ON, the analog input signal voltage Vin is applied through the first switch 1 to the first capacitor C21. A first short circuit is formed by the third switch 19 between the input and output terminals of the first invertor 23. A second short circuit is also formed by the fourth switch 20 between the input and output terminals of the second invertor 24. The first invertor 23 outputs an output voltage corresponding to the logical threshold voltage VLT23 as an operational point at which input and output voltages of the first invertor 23 are balanced. The second invertor 24 outputs an output voltage corresponding to the logical threshold voltage VLT24 as an operational point at which input and output voltages of the second invertor 24 are balanced. The analog input signal voltage Vin is applied to an. input side terminal of the first capacitor C21. The logical threshold voltage VLT23 is generated on an output side terminal of the first capacitor C21. Since the third switch 19 is ON, the logical threshold voltage VLT23 is also applied to an input side terminal of the second capacitor C22. The logical threshold voltage VLT24 is generated on an output side terminal of the second capacitor C22. The first capacitor C21 is biased by a voltage corresponding to the difference between the analog input signal voltage Vin and the logical threshold voltage VLT23. The first capacitor C21 is charged in accordance with the difference between the analog input signal voltage Vin and the logical threshold voltage VLT23. The second capacitor C22 is also biased by a voltage corresponding to a difference between the logical threshold voltages VLT23 and VLT24. The second capacitor C22 is charged in accordance with the difference between the logical threshold voltages VLT23 and VLT24. Even if the first and second invertors 23 and 24 are designed to be identical with each other, the logical threshold voltages VLT23 and VLT24 somewhat differ from each other due to unavoidable variations in fabrication processes for the semiconductor integrated circuits. For that reason, the second capacitor C22 is charged in accordance with the difference between the logical threshold voltages VLT23 and VLT24. In the second period, the first third and fourth switches 1, 19 and 20 turn OFF whilst the second switch 2 turns ON. The comparative reference voltage Vref is applied through the second switch 2 to the first capacitor C21. If the analog input signal voltage Vin is higher than the comparative reference voltage Vref, this means that the voltage applied to the input side terminal of the first capacitor C21 drops from the analog input signal voltage Vin to the comparative reference voltage Vref. The drop of the voltage level or the potential of the input side terminal of the first capacitor C21 causes a potential drop on the output side terminal of the first capacitor C21 in accordance with the principle of conservation of charge. Namely, the potential of the output side terminal of the first capacitor C21, for example, drops from the logical threshold voltage VLT23 to a voltage VLT23' provided that Vin - VLT23 = Vref - VLT23'. The potential of the input terminal of the first invertor 23 also drops from the logical threshold voltage VLT23 to the voltage VLT23', which potential drop causes a rise of the potential of the output terminal of the first invertor 23. This rise causes a rise of the potential of the input side terminal of the second capacitor C22, which latter rise causes a rise of the potential of the output side terminal of the second capacitor C22. This rise causes a rise of the potential of the input terminal of the second invertor 24, which rise, in turn causes a drop of the potential of the output terminal of the second invertor 24. The output voltage from the second invertor 24 is then fetched by the data latch circuit 12 before the output voltage from the second invertor 24 is converted into logic levels to be outputted onto the output terminal 15 as the result of the comparison of the analog input signal voltage to the comparative reference voltage. If, however, the analog input signal voltage Vin is lower than the comparative reference voltage Vref, this means that the voltage applied to the input side terminal of the first capacitor C21 rises from the analog input signal voltage Vin to the comparative reference voltage Vref. The rise of the voltage level or the potential of the input side terminal of the first capacitor C21 causes a potential rise on the output side terminal of the first capacitor C21 in accordance with the principle of conservation of charge. Namely, the potential of the output side terminal of the first capacitor C21 is, for example, raised from the logical threshold voltage VLT23 to a voltage VLT23' provided that Vin - VLT23 = Vref-VLT23'. The potential of the input terminal of the first inventor 23 is also raised from the logical threshold voltage VLT23 to the voltage VLT23' and causes a drop of the potential of the output terminal of the first inventor 23. This drop causes a drop of the potential of the input side terminal of the second capacitor C22, which drop, in turn causes a drop of the potential of the output side terminal of the second capacitor C22. The latter drop causes a drop of the potential of the input terminal of the second invertor 24, whereas this drop causes a rise of the potential of the output terminal of the second invertor 24. The output voltage from the second invertor 24 is then fetched by the data latch circuit 12 before the output voltage from the second invertor 24 is converted into logic levels to be outputted onto the output terminal 15 as the result of the comparison of the analog input signal voltage to the comparative reference voltage. FIG. 3 is a diagram illustrative of input output characteristics L1 and output characteristics L2 and L3 of the inventor in the above conventional chopper comparator. The input output characteristics for the logical threshold voltage of the invertor are represented by a line L1. The output characteristic of the invertor when supplied with a power voltage of Vdd is represented by a curve L2. The output characteristic of the invertor when supplied with a power voltage of Vdd' is represented by a curve L3. If the power voltage is Vdd in the first time period and then unintentionally drops to a voltage Vdd' in the second time period, the logical threshold voltage VLT (point A) having occurred in the first period also drops to a voltage VLT' (point B). The output characteristic L2 having occurred in the first period is also changed to the output characteristic L3. If the input voltage to be inputted to the invertor remains corresponding to the logical threshold voltage VLT through the first and second periods, the output voltage from the invertor corresponds to the point A on the output voltage curve L2 in the first period and then drops to a voltage corresponding to the point C on the output voltage curve L3 in the second time period. If, for example, the input voltage to be inputted into the invertor has corresponded to point A in the first period before the input voltage drops to correspond to point D due to the variation of the logical threshold voltage by the power voltage drop, the output voltage from the invertor will correspond to the point D2 on the curve L3. If, however, no power voltage drop appears, the output voltage should have to correspond to point D1 on the curve L2. Namely, if the power voltage drop appears, the result of the comparison of the analog input signal voltage to the comparative reference voltage is opposite to the correct one. If the power voltage drop appears, the malfunction of the chopper comparator may appear. Further, if the difference between the analog input signal voltage and the comparative reference voltage is made narrower by the power voltage drop, the period when the output voltage from the invertor remains at an intermediate voltage level between the power voltage level and the ground level is increased. As a result, the period of flowing a punch through current through the invertor is made longer. When the operational point of the invertor remains at the intermediate voltage level, the invertor shows an amplification factor of about 10. If the difference between the analog input signal and the comparative reference voltage is small, then it is required to make a series connection of plural invertors in order to amplify the output voltage up to the logic level. This results in increased power. Moreover, there is known from US-A-5,332,931 a chopper comparator unit as disclosed in the preamble of patent claim 1. In this known structure, the circuitry includes third and fourth capacitors cross-coupled to the input and output terminals, and vice versa, of the first and second inverters, respectively, which capacitors act as feedback capacitors to properly balance the inverters if there is a difference between their pre-charged voltage values. Such capacitors being frequency-dependent circuitry elements, they remain open in the case of DC. Thus correspondingly designed chopper comparators are restricted regarding their fields of application. Under the above circumstances, it is required to develop a novel chopper comparator showing high speed and low power operation free of any malfunction under variation of logical threshold voltage of invertors in a sampling time period for sampling analog input signal voltage and comparative reference voltage and other time period. Accordingly, it is an object of the present invention to provide a novel chopper comparator free from any problems and disadvantages as described above. It is a further object of the present invention to provide a novel chopper comparator showing high speed and low power operation free of any malfunction under variation of logical threshold voltage of invertors in a sampling time period for sampling analog input signal voltage and comparative reference voltage and other time period. In order to obtain these objects, the chopper comparator unit including a voltage sampling circuitry, for comparing an analog input signal voltage and a comparative reference voltage comprises the combination of the features of patent claim 1. Thus, the present invention provides a chopper comparator unit including a voltage sampling circuitry, for comparing an analog input signal voltage and a comparative reference voltage. This voltage sampling circuitry comprises the following elements: First and second input terminals are provided for receiving the analog input signal voltage and the comparative reference voltage respectively. A first capacitor is provided which has a first input side terminal being coupled through a first switch to the first input terminal. A second capacitor is provided which has a second input side terminal being coupled through a second switch to the second input terminal. A third switch is provided between the first and second input side terminals of the first and second capacitors, wherein after the first and second switches have turned OFF to discontinue application of the analog input signal voltage and the comparative reference voltage to the first and second capacitors, respectively, the third switch turns ON to form a short circuit between the first and second input side terminals of the first and second capacitors. A first invertor is provided which has an input terminal coupled to the first output terminal of the first capacitor. A fourth switch is provided which is connected between the input terminal and an output terminal of the first invertor. A second invertor is provided which has an input terminal coupled to the second output terminal of the second capacitor. A fifth switch is provided which is connected between the input terminal and an output terminal of the second invertor. A sixth switch is provided which is coupled between the input terminal of the first invertor and the output terminal of the second invertor. A seventh switch is provided which is coupled between the input terminal of the second invertor and the output terminal of the first invertor. It is preferable to further provide first and second voltage amplification circuits which are connected to first and second output side terminals of the first and second capacitors for amplifying voltages which appear on the first and second output side terminals of the first and second capacitors. It is also preferable to further provide, in the chopper comparator unit, first and second voltage amplification circuits which are coupled to first and second output side terminals of the first and second capacitors, respectively for amplifying voltages which appear on the first and second output side terminals, and furthermore provide a data latch circuit which is connected to first and second output terminals of the first and second voltage amplification circuits respectively. Preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a circuit diagram illustrative of the conventional chopper comparator. FIG. 2 is a timing chart illustrative of signal waveforms of the conventional chopper comparator. FIG. 3 is a diagram illustrative of input output characteristics L1 and output characteristics L2 and L3 of the invertor in the above conventional chopper to be in comparator. FIG. 4 is a circuit diagram illustrative of a novel chopper comparator in a first embodiment according to the present invention. FIG. 5 is a timing chart illustrative of signal waveforms of a novel chopper comparator of FIG. 4. FIG. 6 is a circuit diagram illustrative of a novel chopper comparator in a second embodiment according to the present invention. FIG. 7 is a timing chart illustrative of signal waveforms of a novel chopper comparator of FIG. 6. FIRST EMBODIMENT : A first embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5. The novel chopper comparator has a voltage sampling circuit, a positive feed-back circuit connected to the voltage sampling circuit, and a data latch circuit connected to the positive feed-back circuit. It has first and second input terminals 8 and 9. The first input terminal is provided to receive an analog input signal voltage Vin whilst the second input terminal is provided to receive a comparative reference voltage Vref. The voltage sampling circuit has first and second capacitors C1 and C2. The first capacitor C1 has an input side terminal connected through a first switch 1 to the first input terminal Vin. The second capacitor C2 has an input side terminal connected through a second switch 2 to the second input terminal Vref. The input side terminals of the first and second capacitors C1 and C2 are connected to each other through a third switch. The positive feed-back circuit is connected to output side terminals of the first and second capacitors C1 and C2, and has first and second invertors 10 and 11 as well as fourth, fifth, sixth and seventh switches 4, 5, 6 and 7. The first invertor 10 has an input terminal connected to the output side terminal of the first capacitor C1. The second invertor 11 has an input terminal connected to the output side terminal of the second capacitor C2. The fourth switch 4 is connected between the input side terminal and the output side terminal of the first invertor 10 so that if the fourth switch 4 is in ON state, a short circuit will occur between the input side terminal and the output side terminal of the first invertor 10. The fifth switch 5 is connected between the input side terminal and the output side terminal of the second invertor 11 so that if the fifth switch 5 is in ON state, a short circuit will occur between the input side terminal and the output side terminal of the second invertor 11. The output side terminal of the first invertor 10 is connected to the input side terminal of the second invertor 11 through the seventh switch 7. The output side terminal of the second invertor 11 is connected to the input side terminal of the first invertor 12 through the sixth switch 6. The output side terminals of the first and second invertors 10 and 11 are connected to the data latch circuit 12. The data latch circuit 12 is connected to an output terminal 15 on which an output from the data latch circuit appears. The operation of the above chopper comparator will be described in detail with reference to FIGS. 4 and 5. It is divided into four periods of time. In the first period, the first, second, fourth and fifth switches 1, 2, 4 and 5 are in ON state, whilst the third, sixth and seventh switches 3, 6 and 7 are in OFF state. Since the fourth switch 4 is ON a short circuit is formed between the input side terminal and the output side terminal of the first invertor 10 whereby the first invertor 10 outputs a first logical threshold voltage VLT10. Since the fifth switch 5 is ON as well, short circuiting occurs between the input side terminal and the output side terminal of the second invertor 11 whereby the second invertor 11 outputs a second logical threshold voltage VLT11. Since the first switch 1 is ON, the analog input signal voltage Vin is transmitted through the first switch 1 and applied to the input side terminal of the first capacitor C1. Since the second switch 2 is ON too, the comparative reference voltage Vref is transmitted through the second switch 2 and applied to the input side terminal of the second capacitor C2. The input side terminal and the output side terminal of the first capacitor C1 are charged with the analog input signal voltage Vin and the first logical threshold voltage VLT10 respectively. Namely, the first capacitor C1 is biased by a voltage corresponding to the difference between the analog input signal voltage Vin and the first logical threshold voltage VLT10. This means that the first capacitor C1 performs sampling of the difference between the analog input signal voltage Vin and the first logical threshold voltage VLT10. The input side terminal and the output side terminal of the second capacitor C2 are applied with the analog input signal voltage Vin and the second logical threshold voltage VLT11 respectively. Namely, the second capacitor C2 is biased by a voltage corresponding to the difference between the analog input signal voltage Vin and the second logical threshold voltage VLT11. This means that the second capacitor C2 performs sampling of the difference between the analog input signal voltage Vin and the second logical threshold voltage VLT11. In the second period, the first and second switches 1 and 2 turn OFF to discontinue the application of the analog input signal voltage Vin and the comparative reference vollage Vref to the first and second capacitors C1 and C2 respectively. Subsequently, the fourth and fifth switches 4 and 5 turn OFF to disconnect both short circuits between the input side terminal and the output side terminal of the first and second invertors 10 and 11. During the second period, the third, sixth and seventh switches 3, 6 and 7 remain OFF. In the third period, the third switch 3 turns ON to form a short circuit between the input side terminals of the first and second capacitors C1 and C2 so as to re-distribute the charges to the first and second capacitors C1 and C2. As described above, in the above first and second time periods, the input side terminals of the first and second capacitors C1 and C2 are applied with the analog input signal voltage Vin and the comparative reference voltage Vref. After the third switch 3 has turned ON tn form the short circuit between the input side terminals of the first and second capacitors C1 and C2 in the third period, the analog input signal voltage Vin of the input side terminal of the first capacitor C1 and the comparative reference voltage Vref of the output side terminal of the second capacitor C2 are varied to an intermediate voltage between the analog input signal voltage Vin and the comparative reference voltage Vref. Such potential variations having appeared on the input side terminals of the first and second capacitors C1 and C2 cause potential variations on the output side terminals nf the first and second capacitors C1 and C2. If, for example, the analog input signal voltage Vin is higher than the comparative reference voltage Vref, the potential of the input side terminal of the first capacitor C1 drops to the intermediate potential from the analog input signal voltage Vin in turning the third switch 3 ON. This potential drop appearing on the input side terminal of the first capacitor C1 causes a potential drop on the output side terminal of the first capacitor C1, which drop, in turn causes the same potential drop on the input terminal of the first invertor 10. This potential drop appearing on the input terminal of the first invertor 10 causes a potential rise on the output terminal of the first invertor 10. On the other hand, the potential of the input side terminal of the second capacitor C2 rises to the intermediate potential from the comparative reference voltage Vref in turning the third switch 3 ON. This potential rise appearing on the input side terminal of the second capacitor C2 causes a potential rise on the output side terminal of the second capacitor C2. This latter potential rise causes the same potential rise on the input terminal of the second invertor 11, which rise, in turn, causes a potential drop on the output terminal of the second invertor 11. If, however, the analog input signal voltage Vin is lower than the comparative reference voltage Vref, the potential of the input side terminal of the first capacitor C1 rises to the intermediate potential from the analog input signal voltage Vin in turning the third switch 3 ON. This potential rise causes a potential rise on the output side terminal of the first capacitor C1, which rise, in turn, causes the same potential drop on the input terminal of the first invertor 10, this latter drop on the input terminal of the first invertor 10 causing a potential drop on the output terminal of the first invertor 10. On the other hand, the potential of the input side terminal of the second capacitor C2 drops to the intermediate potential from the comparative reference voltage Vref in turning the third switch 3 ON. This potential drop causes a potential drop on the output side terminal of the second capacitor C2, which potential drop of the output side terminal of the second capacitor C2 causes the same potential drop on the input terminal of the second invertor 11. This latter drop causes a potential rise on the output terminal of the second invertor 11. In the fourth period, the sixth and seventh switches 6 and 7 turn ON to effect or form the positive-feedback circuit. The first, second, fourth and fifth switches 1, 2, 4 and 5 remain OFF whilst the third switch 3 remains ON. In the first to third periods, the output terminal of the second invertor 11 is disconnected from the input terminal of the first invertor 10, and the output terminal of the first invertor 10 is disconnected from the input terminal of the second invertor 11 as well. In the fourth period, however, the output terminal of the second invertor 11 is connected to the input terminal of the first invertor 10 and also the output terminal of the first invertor 10 is connected to the input terminal of the second invertor 11. As a result, the output from the first invertor 10 is transmitted through the seventh switch 7 to the input terminal of the second invertor 11. The output from the second invertor 11 is transmitted through the sixth switch 6 to the input terminal of the first invertor 10. This positive feed-back circuit amplifies the outputs from the first and second invertors 10 and 11 and the amplified outputs are fetched by the data latch circuit 12. If the analog input signal voltage Vin is higher than the comparative reference voltage Vref, in the above third period the potential rise appears on the input terminal of the first invertor 10 whilst the potential drop appears on the output terminal of the first invertor 10. On the other hand, the potential drop appears on the input terminal of the second invertor 11 whilst the potential rise appears on the output terminal of the second invertor 11. In the fourth period, the sixth and seventh switches 6 and 7 turn ON to form the positive feed-back circuit. As a result, the potential drop on the output terminal of the first invertor 10 causes a potential drop of the input terminal of the second invertor 11. This potential drop, in turn, causes a potential rise on the output terminal of the second invertor 11, which rise is superimposed on the potential rise caused by the potential rise of the output side terminal of the second invertor 11, thereby amplifying the potential rise on the output terminal of the second invertor 11. As a result, the amplified potential rise having appeared on the output terminal of the second invertor 11 is fetched into the data latch circuit 12. On the other hand, a potential rise appears on the input terminal of the first invertor 10 whilst a potential drop appears on the output terminal of the first invertor 10. In the fourth period, the sixth and seventh switches 6 and 7 turn ON to form the positive feed-back circuit. As a result, the potential rise on the output terminal of the second invertor 11 causes a potential rise of the input terminal of the first invertor 10. This latter rise causes a potential drop on the output terminal of the first invertor 10, which drop is superimposed on the potential drop caused by the potential drop of the output side terminal of the first invertor 10, thereby amplifying the potential drop on the output terminal of the first invertor 10. As a result, the amplified potential drop having appeared on the output terminal of the first invertor 10 is fetched into the data latch circuit 12. If, however, the analog input signal voltage Vin is lower than the comparative reference voltage Vref, in the above third period a potential drop appears on the input terminal of the first invertor 10 whilst a potential rise appears on the output terminal of the first invertor 10. On the other hand, a potential rise appears on the input terminal of the second invertor 11 whilst a potential drop appears on the output terminal of the second inventor 11. In the fourth period, the sixth and seventh switches 6 and 7 turn ON to form the positive feed-back circuit. As a result, the potential rise on the output terminal of the first inventor 10 causes the potential rise of the input terminal of the second invertor 11. This latter potential rise causes a potential drop on the output terminal of the second invertor 11, which drop is superimposed on the potential drop caused by the potential drop of the output side terminal of the second invertor 11, thereby amplifying the potential drop on the output terminal of the second invertor 11. As a result, the amplified potential drop having appeared on the output terminal of the second invertor 11 is fetched into the data latch circuit 12. On the other hand, a potential drop appears on the input terminal of the first invertor 10 whilst a potential rise appears on the output terminal of the first invertor 10. In the fourth period, the sixth and seventh switches 6 and 7 turn ON to form the positive feed-back circuit. As a result, a potential drop on the output terminal of the second invertor 11 causes a potential drop of the input terminal of the first invertor 10, which drop in turn, causes a potential rise on the output terminal of the first invertor 10. This rise is superimposed on the potential rise caused by the potential rise of the output side terminal of the first invertor 10, thereby amplifying the potential rise on the output terminal of the first invertor 10. As a result, the amplified potential rise on the output terminal of the first invertor 10 is fetched into the data latch circuit 12. Consequently, the above positive feed-back circuit amplifies the output voltages from the first and second invertors 10 and 11. In the fourth period, the data latch circuit 12 fetches the amplified output voltages from the first and second invertors 10 and 11 for translation into the logic levels and subsequent comparison thereof. The result of the comparison will appear on the output terminal 15 of the chopper comparator. The following description will focus on the operation of the above chopper comparator when the power voltage is varied by superimposing noises onto the power source. The variation of the power voltage causes variation in the first and second logical threshold voltages of the first and second invertors 10 and 11. The first and second logical threshold voltages VLT10 and VLT11 of the first and second invertors 10 and 11 are varied in the same phase into third and fourth logical threshold voltages VLT10' and VLT11'. The difference between the third logical threshold voltage VLT10' from the first logical threshold voltage VLT10 has the same polarity as the difference between the fourth logical threshold voltage VLT11' from the second logical threshold voltage VLT11. Namely, the first and second logical threshold voltages VLT10 and VLT11 are varied in the same phase and in the same polarity into the third and fourth logical threshold voltages VLT10' and VLT11'. Whereas the first and second invertors 10 and 11 were designed to be identical with each other, the first and second logical threshold voltages VLT10 and VLT11 thereof are somewhat different from each other by variations thereof in manufacturing processes, for which reason the third and fourth logical threshold voltages VLT10' and VLT11' are also somewhat different from each other. In the third period, however, the third switch turns ON to form a short circuit between the input side terminals of the first and second invertors 10 and 11 whereby the output side terminals of the first and second capacitors C1 and C2 or the input terminals of the first and second invertors 10 and 11' show potential variation in response to the potential variation having appeared on the input side terminals of the first and second capacitors C1 and C2 in accordance with the difference between the analog input signal voltage Vin and the comparative reference voltage Vref in forming the short circuit through the third switch 3. Accordingly, even if variation in the logical threshold voltages of the first and second invertors 10 and 11 caused by the variation in power voltage of the power source would be higher than the difference between the analog input signal voltage Vin and the comparative reference voltage Vref, the relationship of whether the output from the first invertor 10 is higher or lower than the output from the second invertor 11 would be the same as when no voltage variation appears on the first and second logical threshold voltages VLT10 and VLT11. In the fourth period, the sixth and seventh switches 6 and 7 turn ON to form the positive feed-back circuit. The relationship of whether the output from the first invertor 10 is higher or lower than the output from the second invertor 11 would then be the same as when no voltage variation appears on the first and second logical threshold voltages VLT10 and VLT11. The above novel chopper comparator shows no malfunction in operation even if the first and second logical threshold voltages VLT10 and VLT11 are varied by the variation in voltage of the power source. Further, the positive feed-back circuit shortens the time period when outputs from the invertors are in the intermediate voltage levels even if the difference between the analog input signal voltage Vin and the comparative reference voltage Vref is small. The shortening of the time period when outputs from the invertors are in the intermediate voltage levels causes reduction in punch through current of the first and second invertors 10 ands 11. This enables the chopper comparator to perform, at relatively small current consumption and relatively high speed, a comparison operation between the analog input signal voltage Vin and the comparative reference voltage Vref even if the difference between the analog input signal voltage Vin and the comparative reference voltage Vref is small. SECOND EMBODIMENT : A second embodiment according to the present invention will be described in detail with reference to FIGS. 6 and 7. This chopper comparator has a voltage sampling circuit, a positive feed-back circuit connected to the voltage sampling circuit, and a data latch circuit connected to the positive feed-back circuit. It has first and second input terminals 8 and 9. The first input terminal 8 is provided to receive an analog input signal voltage Vin whilst the second input terminal 9 is provided to receive a comparative reference voltage Vref. The voltage sampling circuit has first, second third and fourth capacitors C1, C2, C3 and C4 and further third and fourth invertors 17 and 18 as well as eighth and ninth switches 13 and 14. The first capacitor C1 has an input side terminal connected to the first input terminal Vin through a first switch 1. The second capacitor C2 has an input side terminal connected to the second input terminal Vref through a second switch 2. The input side terminals of the first and second capacitors C1 and C2 are connected to each other through a third switch. The third invertor 17 has an input terminal connected to the output side terminal of the first capacitor C1. The fourth invertor 18 has an input terminal connected to the output side terminal of the second capacitor C2 The eighth switch 13 is connected between the input side terminal and the output side terminal of the third invertor 17 so that if the eighth switch 13 is in ON state, a short circuit occurs between the input side terminal and the output side terminal of the third invertor 17. The ninth switch 14 is connected between the input side terminal and the output side terminal of the fourth invertor 18 so that if the ninth switch 14 is in ON state, a short circuit occurs between the input side terminal and the output side terminal of the fourth invertor 18. The output side terminal of the third invertor 17 is connected to an input side terminal of the third capacitor C3. The output side terminal of the fourth invertor 18 is connected to an input side terminal of the fourth capacitor C4. The positive feed-hack circuit is connected to output side terminals of the third and fourth capacitors C3 and C4. The positive feed-back circuit has first and second invertors 10 and 11 and fourth, fifth, sixth and seventh switches 1, 5, 6 and 7. The first invcrtor 10 has an input terminal connected to the output side terminal of the third capacitor C3. The second invertor 11 has an input terminal connected to the output side terminal of the fourth capacitor C4. The fourth switch 4 is connected between the input side terminal and the output side terminal of the first invertor 10 so that if the fourth switch 4 is in ON state, a short circuit will occur between the input side terminal and the output side terminal of the first invertor 10. The fifth switch 5 is connected between the input side terminal and the output side terminal of the second invertor 11 so that if the fifth switch 5 is in ON state, a short circuit will occur between the input side terminal and the output side terminal of the second invertor 11. The output side terminal of the first invertor 10 is connected through the seventh switch 7 to the input side terminal of the second invertor 11. The output side terminal of the second invertor 11 is connected through the sixth switch 6 to the input side terminal of the first invertor 12.. The output side terminals of the first and second invertors 10 and 11 are connected to the data latch circuit 12. The data latch circuit 12 is connected to an output terminal 15 on which an output from the data latch circuit appears. Operation of this chopper comparator will be described in detail with reference to FIGS. 6 and 7. The operation is divided into four periods. In the first period, the first, second, fourth, fifth, eighth and ninth switches 1, 2, 4, 5 13 and 18 are ON, whilst the third, sixth and seventh switches 3, 6 and 7 are in OFF state. Since the eighth switch 13 is ON, the short circuit occur between the input side terminal and the output side terminal of the third invertor 17 whereby the third invertor 17 outputs a third logical threshold voltage VLT13. Since also the ninth switch 14 is ON, the short circuit is formed between the input side terminal and the output side terminal of the fourth invertor 18 whereby the fourth invertor 18 outputs a fourth logical threshold voltage VLT18. Since the fourth switch 4 is ON, the short circuit is formed between the input side terminal and the output side terminal of the first inventor 10 whereby the first invertor 10 outputs a first logical threshold voltage VLT10. Since also the fifth switch 5 is ON, short circuiting will occur between the input side terminal and the output side terminal of the second invertor 11 whereby the second invertor 11 outputs a second logical threshold voltage VLT11. Since the first switch 1 is ON, the analog input signal voltage Vin is transmitted through the first switch 1 and applied to the input side terminal of the first capacitor C1. Since also the second switch 2 is ON, the comparative reference voltage Vref is transmitted through the second switch 2 and applied to the input side terminal of the second capacitor C2. The input side terminal and the output side terminal of the first capacitor C1 are charged with the analog input signal voltage Vin and the third logical threshold voltage VLT17 respectively. Namely, the first capacitor C1 is biased by a voltage corresponding to the difference between the analog input signal voltage Vin and the third logical threshold voltage VLT17. This means that the first capacitor C1 performs sampling of the difference between the analog input signal voltage Vin and the third logical threshold voltage VLT17. The input side terminal and the output side terminal of the second capacitor C2 are charged with the analog input signal voltage Vin and the fourth logical threshold voltage VLT18 respectively, Namely, the second capacitor C2 is biased by a voltage corresponding to the difference between the analog input signal voltage Vin and the fourth logical threshold voltage VLT18. This means that the second capacitor C2 performs sampling of the difference between the analog input signal voltage Vin and the fourth logical threshold voltage VLT18. The input side terminal and the output side terminal of the third capacitor C3 are charged with the third and first logical threshold voltages VLT17 and VLT10 respectively Namely, the third capacitor C3 is biased by a voltage corresponding to the difference between the third and first logical threshold voltages VLT17 and VLT10. This means that the third capacitor C3 performs sampling of the difference between the third and first logical threshold voltages VLT17 and VLT10. The input side terminal and the output side terminal of the fourth capacitor C4 are applied with the fourth and second logical threshold voltages VLT18 and VLT11 respectively. Namely, the fourth capacitor C4 is biased by a voltage corresponding to the difference between the fourth and second logical threshold voltages VLT18 and VLT11. This means that the fourth capacitor C4 performs sampling of the difference between the fourth and second logical threshold voltages VLT18 and VLT11. In the second period, the first and second switches 1 and 2 turn OFF to discontinue application of the analog input signal voltage Vin and the comparative reference voltage Vref to the first and second capacitors C1 and C2 respectively. Subsequently, the eighth and ninth switches 13 and 14 turn OFF disconnecting both short circuits between the input side terminal and the output side terminal of the third and fourth invertors 17 and 18. Further, subsequently, the fourth and fifth switches 4 and 5 turn OFF disconnecting both short circuits between the input side terminal and the output side terminal of the first and second invertors 10 and 11. During the second period, the third, sixth and seventh switches 3, 6 and 7 remain OFF. In the third period, the third switch 3 turns ON to form short circuiting between the input side terminals of the first and second capacitors C1 and C2 so as to re-distribute the charges to the first and second capacitors C1 and C2. As described above, in the above first and second periods, the input side terminals of the first and second capacitors C1 and C2 are applied with the analog input signal voltage Vin and the comparative reference voltage Vref. After the third switch 3 has turned ON to form the short circuit between the input side terminals of the first and second capacitors C1 and C2 in the third time period, the analog input signal voltage Vin of the input side terminal of the first capacitor C1 and the comparative reference voltage Vref of the output side terminal of the second capacitor C2 are varied to an intermediate voltage between the analog input signal voltage Vin and the comparative reference voltage Vref. Such potential variation on the input side terminals of the first and second capacitors C1 and C2 causes potential variation on the output side terminals of the first and second capacitors C1 and C2. Such potential variation on the output side terminals of the first and second capacitors C1 and C2 causes potential variation on the input terminals of the third and fourth invertors 17 and 18. Such potential variation on the input terminals of the third and fourth invertors 17 and 18 causes potential variation on the output terminals of the third and fourth invertors 17 and 18. Such potential variation on the output terminals of the third and fourth invertors 17 and 18 causes potential variation on the input terminals of the third and fourth capacitors C3 and C4. Such potential variation on the input side terminals of the third and fourth capacitors C3 and C4 causes potential variation on the output side terminals of the third and fourth capacitors C3 and C4. Such potential variation on the output side terminals of the third and fourth capacitors C3 and C4 causes potential variation on the input terminals of the first and second invertors 10 and 11, whereas potential variation on the input terminals of the first and second invertors 10 and 11 causes potential variation on the output terminals of the first and second invertors 10 and 11. If, for example, the analog input signal voltage Vin is higher than the comparative reference voltage Vref, the potential of the input side terminal of the first capacitor C1 drops to the intermediate potential from the analog input signal voltage Vin in turning the third switch 3 ON. This potential drop on the input side terminal of the first capacitor C1 causes a potential drop on the output side tenninal of the first capacitor C1, which drop causes the same potential drop on the input terminal of the third invertor 17. This latter potential drop causes a potential rise on the output terminal of the third invertor 17, which rise causes the same potential rise on the input side terminal of the third capacitor C3, which rise, in turn causes a potential rise on the output side terminal of the third capacitor C3. This latter rise causes the same potential rise on the input terminal of the first invertor 10, which, in turn, causes a potential drop on the output terminal of the first invertor 10. On the other hand, the potential of the input side terminal of the second capacitor C2 rises to the intermediate potential from the comparative reference voltage Vref in turning the third switch 3 ON. This potential rise on the input side terminal of the second capacitor C2 causes a potential rise on the output side terminal of the second capacitor C2. This potential rise of the output side terminal of the second capacitor C2 causes the same potential rise on the input terminal of the fourth invertor 18. This potential rise on the input terminal of the fourth invertor 18 causes a potential drop on the output terminal of the fourth invertor 18, which potential drop causes the same potential drop on the input side terminal of the fourth capacitor C4. This latter potential drop causes a potential drop on the output side terminal of the fourth capacitor C4, which in turn, causes the same potential drop on the input terminal of the second invertor 11. This latter drop causes a potential rise on the output terminal of the second invertor 11. If, however, the analog input signal voltage Vin is lower than the comparative reference voltage Vref, the potential of the input side terminal of the first capacitor C1 rises to the intermediate potential from the analog input signal voltage Vin in turning the third switch 3 ON. This potential rise on the input side terminal of the first capacitor C1 causes a potential rise on the output side terminal of the first capacitor C1, which causes the same potential rise on the input terminal of the third invertor 17. This potential rise on the input terminal of the third invertor 17 causes a potential drop on the output terminal of the third invertor 17, which potential drop causes the same potential drop on the input side terminal of the third capacitor C3. This drop, in turn, causes a potential drop on the output side terminal of the third capacitor C3, which causes the same potential drop on the input terminal of the first invertor 10. This latter drop causes a potential rise on the output terminal of the first invertor 10. On the other hand, the potential of the input side terminal of the second capacitor C2 drops to the intermediate potential from the comparative reference voltage Vref in turning the third switch 3 ON. This potential drop on the input side terminal of the second capacitor C2 causes a potential drop on the output side terminal of the second capacitor C2, which drop causes the same potential drop on the input terminal of the fourth invertor 18. This potential drop appearing on the input terminal of the fourth invertor 18 causes a potential rise on the output terminal of the fourth invertor 18, which causes the same potential rise on the input side terminal of the fourth capacitor C4. This potential rise appearing on the input side terminal of the fourth capacitor C4 causes a potential rise on the output side terminal of the fourth capacitor C4, which rise, in turn, causes the same potential rise on the input terminal of the second invertor 11. This potential rise appearing on the input terminal of the second invertor 11 causes a potential drop on the output terminal of the second invertor 11. In the fourth period, the sixth and seventh switches 6 and 7 turn ON to effect or form the positive feedback circuit. The first, second, fourth, fifth eighth and ninth switches 1, 2, 4, 5, 13 and 14 remain OFF whilst the third switch 3 remains ON. In the above first to third periods, the output terminal of the second invertor 11 is disconnected from the input terminal of the first invertor 10 and also the output terminal of the first invertor 10 is disconnected from the input terminal of the second invertor 11. In the fourth period, however, the output terminal of the second invertor 11 is connected to the input terminal of the first invertor 10 and also the output terminal of the first invertor 10 is connected to the input terminal of the second invertor 11. As a result, the output from the first invertor 10 is transmitted through the seventh switch 7 to the input terminal of the second invertor 11. The output from the second invertor 11 is transmitted through the sixth switch 6 to the input terminal of the first invertor 10. This positive feed-back circuit amplifies the outputs from the first and second invertors 10 and 11. The amplified outputs are fetched by the data latch circuit 12. If the analog input signal voltage Vin is higher than the comparative reference voltage Vref, in the above third period a potential rise appears on the input terminal of the first invertor 10 whilst a potential drop appears on the output terminal of the first invertor 10. On the other hand, a potential drop appears on the input terminal of the second invertor 11 whilst a potential rise appears on the output terminal of the second invertor 11. In the fourth period, the sixth and seventh switches 6 and 7 turn ON to form the positive feed-back circuit. As a result, a potential drop appearing on the output terminal of the first invertor 10 causes a potential drop of the input terminal of the second invertor 11. This potential drop causes a potential rise on the output terminal of the second invertor 11. This latter potential rise is superimposed on the potential rise caused by the potential rise of the output side terminal of the second invertor 11, thereby amplifying the potential rise on the output terminal of the second invertor 11. As a result, the amplified potential rise appearing on the output terminal of the second invertor 11 is fetched into the data latch circuit 12. On the other hand, a potential rise appears on the input terminal of the first invertor 10 whilst a potential drop appears on the output terminal of the first invertor 10. In the fourth period, the sixth and seventh switches 6 and 7 turn ON to form the positive feed-back circuit. As a result, the potential rise having appeared on the output terminal of the second invertor 11 causes the potential rise of the input terminal of the first invertor 10. This causes a potential drop on the output terminal of the first invertor 10. This potential drop is superimposed on the potential drop caused by the potential drop of the output side terminal of the first invertor 10, thereby amplifying the potential drop on the output terminal of the first invertor 10. As a result, the amplified potential drop appearing on the output terminal of the first invertor 10 is fetched into the data latch circuit 12. If, however, the analog input signal voltage Vin is lower than the comparative reference voltage Vref, in the above third period the potential drop appears on the input terminal of the first invertor 10 whilst the potential rise appears on the output terminal of the first invertor 10. On the other hand, a potential rise appears on the input terminal of the second invertor 11 whilst a potential drop appears on the output terminal of the second invertor 11. In the fourth period, the sixth and seventh switches 6 and 7 turn ON to form the positive feed-back circuit. As a result, the potential rise appearing on the output terminal of the first invertor 10 causes the potential rise of the input terminal of the second invertor 11. This causes a potential drop on the output terminal of the second invertor 11. This potential drop appearing on the output terminal of the second invertor 11 is superimposed on the potential drop caused by the potential drop of the output side terminal of the second invertor 11, thereby amplifying the potential drop on the output terminal of the second invertor 11. As a result, the amplified potential drop appearing on the output terminal of the second invertor 11 is fetched into the data latch circuit 12. On the other hand, the potential drop appears on the input terminal of the first invertor 10 whilst the potential rise appears on the output terminal of the first invertor 10. In the fourth period, the sixth and seventh switches 6 and 7 turn ON to form the positive feed-back circuit. As a result, the potential drop appearing on the output terminal of the second invertor 11 causes the potential drop of the input terminal of the first invertor 10. This causes a potential rise on the output terminal of the first invertor 10, which potential rise is superimposed on the potential rise caused by the potential rise of the output side terminal of the first invertor 10, thereby amplifying the potential rise on the output terminal of the first invertor 10. As a result, the amplified potential rise appearing on the output terminal of the first invertor 10 is fetched into the data latch circuit 12. Consequently, the above positive feed-back circuit amplifies the output voltages from the first and second invertors 10 and 11. In the fourth period, the data latch circuit 12 fetches the amplified output voltages from the first and second invertors 10 and 11 for translation into the logic levels and subsequent comparison thereof. The result of the comparison will appear on the output terminal 15 of the chopper comparator. The following description will focus on the operation of the above chopper comparator when the power voltage is varied by superimposing noises onto a power source. The variation of the power voltage causes variation in the first, second, third and fourth logical threshold voltages VLT10, VLT11, VLT17 and VLT18 of the first, second, third and fourth invertors 10, 11 17 and 18, respectively. These logical threshold voltages are varied in the same phase into fifth, sixth, seventh and eighth logical threshold voltages VLT10', VLT11', VLT17' and VLT18'. The difference between the fifth logical threshold voltage VLT10' from the first logical threshold voltage VLT10 has the same polarity as the difference between the sixth logical threshold voltage VLT11' from the second logical threshold voltage VLT11. Namely, the first and second logical threshold voltages VLT10 and VLT11 are varied in the same phase and in the same polarity into the fifth and sixth logical threshold voltages VLT10' and VLT11'. Whereas the first and second invertors 10 and 11 were designed to be identical with each other, the first and second logical threshold voltages VLT10 and VLT11 are somewhat different from each other by variation thereof in manufacturing processes, for which reason the fifth and sixth logical threshold voltages VLT10' and VLT11' of the first and second invertors 10 and 11 are also somewhat different from each other. The third invertor 17, the eighth switch 13 and the first capacitor C1 are in the form of a voltage amplification circuit. The fourth invertor 18, the ninth switch 14 and the second capacitor C2 are in the form of a voltage amplification circuit. Those voltage amplification circuits perform amplification of the difference between the analog input signal voltage Vin and the comparative reference voltage Vref. In the third period, however, the third switch turns ON to form a short circuit between the input side terminals of the first and second invertors 10 and 11 whereby the output side terminals of the first and second capacitors C1 and C2 show potential variation in response to the potential variation on the input side terminals of the first and second capacitors C1 and C2 in accordance with the difference between the amplified analog input signal voltage Vin and the amplified comparative reference voltage Vref. Accordingly, even if variation in the logical threshold voltages of the first and second invertors 10 and 11 caused by the variation in power voltage of the power source were higher than the difference between the analog input signal voltage Vin and the comparative reference voltage Vref, the relationship of whether the output from the first invertor 10 is higher or lower than the output from the second invertor 11 would be the same as when no voltage variation appears on the first and second logical threshold voltages VLT10 and VLT11. In the fourth period, the sixth and seventh switches 6 and 7 turn ON to form the positive feed-back circuit. The relationship of whether the output from the first invertor 10 is higher or lower than the output from the second invertor 11 would then be the same as when no voltage variation appears on the first and second logical threshold voltages VLT10 and VLT11. Further, the above voltage amplifying circuitry reduces the critical voltage difference between the analog input signal voltage Vin and the comparative reference voltage Vref wherein the chopper comparator enables the intended comparative operation when the difference between the analog input signal voltage Vin and the comparative reference voltage Vref is not less than the critical voltage difference. The above voltage amplification circuits are capable of reducing the influence of the variations of the logical threshold voltages of the invertors by a reciprocal number of a gain value of the voltage amplification circuits. The above novel chopper comparator shows no malfunction in operation even if the first and second logical threshold voltages VLT10 and VLT11 are largely varied by the variation in voltage of the power source. Furthermore, the positive feed-back circuit shortens the period when outputs from the invertors are in the intermediate voltage levels even if the difference between the analog input signal voltage Vin and the comparative reference voltage Vref is small. Shortening the time period when outputs from the invertors are in the intermediate voltage levels causes reduction in punch through current of the first and second invertors 10 ands 11. This enables the chopper comparator to perform, at relatively small current consumption and at relatively high speed, a comparison operation between the analog input signal voltage Vin and the comparative reference voltage Vref even if the difference between the analog input signal voltage Vin and the comparative reference voltage Vref is small.

Claims: A chopper comparator unit including a voltage sampling circuitry for comparing an analog input signal voltage and a comparative reference voltage, said voltage sampling circuitry comprising: first and second input terminals (8, 9) being provided for receiving said analog input signal voltage (Vin) and said comparative reference voltage (Vref) respectively; a first capacitor (C1) having a first input side terminal being coupled through a first switch (1) to said first input terminal (8); a second capacitor (C2) having a second input side terminal being coupled through a second switch (2) to said second input terminal (9); a third switch (3) being,provided between said first and second input side terminals of said first and second capacitors (C1, C2); a first inverter (10) having an input terminal coupled to a first output terminal of said first capacitor (C1) and an output terminal coupled to said input terminal of the first inverter through a fourth switch (4); a second inverter (11) having an input terminal coupled to a second output terminal of said second capacitor (C2) and an output terminal coupled to said input terminal of the second inverter through a fifth switch (5); the structure of the circuitry being such that after said first and second switches (1, 2) have turned OFF to discontinue application of said analog input signal voltage and comparative reference voltage to said first and second capacitors (C1, C2) respectively, said third switch (3) turns ON to form a short circuit between said first and second input side terminals of said first and second capacitors (C1, C2); characterized by a sixth switch (6) being coupled between said input terminal of said first inverter (10) and said output terminal of said second inverter (11); and a seventh switch (7) being coupled between said input terminal of said second inverter (11) and said output terminal of said first inverter (10). The chopper comparator unit as claimed in claim 1, further characterized by first and second voltage amplification circuits (13, 14, 17, 18, C3, C4) being connected to first and second output side terminals of said first and second capacitances (C1, C2) for amplifying voltages which appear on said first and second output side terminals of said first and second capacitances (C1, C2). The chopper comparator unit as claimed in claim 1, further characterized by first and second voltage amplification circuits (13, 14, 17, 18, C3, C4) being coupled to first and second output side terminals of said first and second capacitors, respectively, for amplifying voltages which appear on said first and second output side terminals; and a data latch circuit (12) being coupled to first and second output terminals of said first and second voltage amplification circuits, respectively.

Inventors: KURAUCHI AKIRA, YUKAWA AKIRA, KURAUCHI, AKIRA, YUKAWA, AKIRA
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1997
Main classification: H03M1
IPC codes: H03K5, H03M1