APPARATUS AND METHOD FOR DEPACKETIZING AND ALIGNING PACKETIZED INPUT DATA

Abstract: Apparatus for depacketizing and aligning packetized input data. Data processing means (305) receives the input data via an input memory (301) and detects, identifies and determines payload size of a data packet of the input data. The data processing means (305) generates a payload size signal indicative of the size of the payload. A word formatter (303) receives units of the payload from the input memory (301) and gathers and aligns these to form data words. A payload counter (306) controls flow of input data from the input memory (301) to the word formatter (303) in accordance with the payload size signal. An input buffer (304) receives the data words from the word formatter (303), stores these and transfers them to the data processing means (305) for effecting data processing.

Description: .APPARATUS AND METHOD FOR DE-PACKETIZING AND ALIGNING PACKETIZED INPUT DATA DETAILED DESCRIPTION OF THE INVEN. TION (1) Field of the Invention This invention relates to apparatus and method for de-packetizing and aligning packetώed input data. (ϋ) Prior Art In data retrieval or communication systems, digital data or digitized multimedia information Wahich can be, potentially, large or variable in size is normally packetized before storage or transmission. This process breaks the data into .smaller packets where each packet contains one or more detectable synctironi-zation patterns called sync-word, necessary information about the packet, and a payload of a smaller partition of the original data. The information about the packet may consist of a packet identification (ID), size of the payload contained in the current packet, timing information, and any necessary side inforπuttion. In applications where there could be multiple sources of data, for example shared data network or multimedia audio/visual information for local data storage device, each source of data is packetized and the resulting packets from all sources are interleaved before transmission or storage. The packet ID is used to identify the data source of each packet. Timing information, which may be in die form of time stamps or temporal references, is used for ordering of the packets or for synchronization between each data source for transmission or presentation. Information related to both multimedia audio and video data is often very large in size, and therefore data compression techniques such as .MPEG video ..and audio compression techniques are usually appli.ed before packetization. Packetization in this case may also follow the method as specified by the .MPEG Systems specifications. With respect to data retrieving operations, packets received from a communication system or read from local storage are .required to be de-packetized before processing by each re.spective data processor. The de-packetization process includes, first, detection of the sync-word, follow by verification of the packet ID, enaction of timing and necessary side information, determining tie payload size and, finally, extraction and concatenation of the payload to reconstruct the data. The de-packetized data may be passed to a data processor for further processing. For ejumple, the data processor for MPEG compressed audio data will be a corresponding MPEG audio decoder; furthermore, this audio decoder may be implemented using progr∑immable DSP (Digital Signal Processor). Figure 1 illustrates a block diagram of a prior art system. Packetized data is received via a data input interface 101, where hand shaking with the packetized data source is performed, and also, if .necessary, serial-to-parallel conversion is effected. The received packetized data is processed by a De-packetizer 103. In order to handle possible jitters in overall transmission rate of the packetized data source and the processing speed of die de-packetizer, an Input FIFO (first-in-fixst-out memory) 102 is inserted in between the data input interface 101 and the de-packetizer 103. The de-packetizer 103 can be a dedicated and fixed function hardware or a programmable processor performing the de-packetization process, as described, to produce the de-packetized data. The de-packetized data is placed into an Input Buffer 104 before being read by Data Processor 105. The .si∞ of the Input Buffer 104 is determined by the nature and type of the data involved, the processing bandwidth of the data processor 105 and, possibly, synchronization requirements of other processes outside the system. For example, it may serve as a delay buffer for synchroriization of an audio data stream to an external video data stream, or a temporal storage buffer such that it can feed regularly to a high speed data processor a block of data, at a rate .higher that the input rate. In Figure 2, a block di.agr.am of another prior art system prior art is illustrated. In order to reduce overall system cost and improve perfoπnance of the data processor, single port system RAM (random access memory) couplijng to the system bus of the data processor 205 serves as the Input Buffer 204, and a D.MA Controller (direct memory access contra Der) 206 is normally used for transferring the de-packetized data from the de-packetizer 203 to the input buffer 204 via the system bus. The Input Buffer 204 may be optimized in size by using a ci.rcu.lar buffer technique. It is likely that the system RAM and the input data (packetized or de-packetized) do not sliare the .same word format in terms of number of bit resolution. For example, the MPEG systems data is bylc aligned and must DSP iyaL«iiϊϋ (SySlέiU buS, Sγ5 ϋ-l RAM, fclύ.) ϋi d lttsft ύl' more bits per word for performance reasons. It is a task for die de-packetizer 203 to align the de-packeti-∞d data to the word format required by the data processor before outputting it to the Input Buffer 204, since this input buf er belongs also to part of the data processor system RAM. .In most systems implementations, flexibility in the De-Packetizer is required, for handling variations in the decoding of the sync-word, ID, timing and necessary side information in each packet; hence, a programmable processor core is very suitable for these jobs. On the other hand, the De-Packetizer is al∞ required to perform simple but highly repetitive tasks of reading payload from the data input interface, aligning the de-packetized data to the data processor word format, and moving the de-packetized and aligned data to the input buffer. A programmable processor core, is .highly inefficient for such simple but highly repetitive tasks as it takes up a high percentage of die processing cycles. A large FIFO may al∞ be required as buffer memory in between the Data Input Interface and the De-Packetizer, due to the requirements of flexibility in the de-packetization process and inefficiencies of a programmable processor core for simple and Mgl ly repetitive taslcs. .Furtiieπnore, aidditional memory must be associated with the programmable processor core for storing and processing of the necessary side information of the packets. SUMMARY OF THE INVENTION It is an object of the current invention to provide an improved apparatus and method for de- packetizating and aligning packetized input data. In one aspect, the invention provides apparatus for depacketizing and aligning packetized input data, having: an input memory for receiving storing, and output of the input data, and for outputting of units of a payload of a data packet of the input data; data processing means for receiving the outputted input data from the input memory and detecting, identifying and determining payload size of the data packet and generating a payload size signal indicative of the size of the payload, and for separately receiving and effecting data processing of the payload; a word formatter for receiving said units of said payload outputted from the input memory, gathering and aligning said units to form data words, and outputting said words; a payload counter for controlling the input memory in accordance with the payload size signal whereby to cause the payload units to be outputted from the input memory to the word foπnatter, and an input buffer for receiving said data words from the word formatter and storing these, and for transferring the data words to the data processing means, to effect said separate receiving of said payload; said data processing means for effecting .said data processing using the received said data words. The apparatus may have a data input interface through which the input data is transferred to the input memory, said data input interface for perfoiming hand shaking with a packetized data source of said input data. The input memory may have a fullness level detector for generating a level filled signal when the input data received thereby is such as to fill the input memory to a predetermined level, and said data processing means may be responsive to generation of said level filled signal to execute said receiving the outputted input data from the input memory and detecting, identifying and determining payload size of the data packet and generating said payload size signal. An interrupt controller may be provided for receiving said level filled signal and generating an interrupt signal pursuant to receipt thereof, .said data processing means being arranged for receipt of said interrupt sgnal and, on receipt thereof, for executing said receiving the outputted input data from the input memcπy ϊtnd detecting, identi.fying and determining payload size of the data packet therein and generating said payload size signal. The input memory may have a further fullness level detector for generating and directing to said data input internee a .further level filled signal when the input thereto of fresh input data is such as to .fill the input memory to a further predetermined level, said data input interface being responsive to receipt of said further level filled signal to generate a data request signal for direction to said packetized data source, indicative of a need to modify the data tr.ansmission rate of the input data directed to the apparatus from the packetized data source. The input memory may be controlled whereby said input data comprising said packet is removed from the input memory and relaced by fresh input data , pursuant to the transfer to the data processing means of said words representing the data packet to the data the apparatus being .arranged for repetitive depacketizing and aligning of data packets and data processing thereof, the data processing means being arranged for repetitively and alternatingly executing a step comprising said receiving the outputted input data from the input memory and detecting, identifying and determining payload size of the data packet therein and generating said payload size signal, and a step comprising said separately receiving and effecting data processing of the payload of the data packet. The data processing means may include a digital signal processor, data/program memory, DMA controller and input buffer, each in data communication via a bus. The wo.rd formatter may be arranged for generating a DMA request sigrral when a .said data word is formed thereby, and the DMA controller is responsive to said DMA request signal to generate and direct a transfer signal to the digital signal processor, the digital signal processor being responsive to the tr.ansfer signal to enable the DMA controller to move the data word from the word formatter to the input buffer for .subsequent proces.sing. The input memory may comprise a firrt in first out memory. The data processing means may be arranged to execute said detecting and identifying the data packet by detection of a sync-word, followed by verification of the packet ID. The data processing means may, pursuant to said detecting and identifying the data packet, extract timing infoimation from the input data. The data processing means may, pursuant to said detecting and identifying the data packet, extract side information from the input data. The invention also provides a method for depacketizing and aligning packetized input data compriaSing: receiving and storing the input data in an input memory; outputting the stored input data to data processing means; by use of the data processing means, detecting, identifying and determining the size of a payload of a data packet of the input data outputted thereto; by use of the data processing eaω, generating a payload size signal indicative of the size of the payload; controlling the input memory in accordance with the payload size signal whereby to cause payload units which form said payload to be outputted from the input memory to the word formatter; by use of said word formatter, gathering and aligning said payload units outputted thereto to form data words; outputting said data words from said word formatter to an input buffer and storing these in said input buffer; transferring said data words to the data processing means; and effecting data processing on the data packet represented by the data words tran.sfeιτed thereto, using the transfeπed data words. The input data may be transferred to the input memory via an data input interface which performs hand shaking with a packetized data source of said input data. The method may include the step of generating a level filled signal when the input data received by the input memory is such as to fill the input memory to a predetermined level, and causing said data processing means to effect said detecting, identifying and determining payload size of the data packet, and to said generate payload size signal, pursuant to generation of the level filled signal. The method may include the step of generating an interrupt signal from said level filled signal and directing said interrupt .signal to said data processing means to cause said data processing means to effect said receiving the outputted input data from the irψut memory and detecting, identifying and determining payload size of the data packet therein and to generate said payload size signal The method may include the step of generating and directing to said data input interface a further level filled signal when the input thereto of fresh input data is such as to fill the input memory to a further predetermined level, and causing said data input interface to generate, responsive to receipt thereby of said further level filled signal a data request signal for direction to said packetized data source, indicative of a need to modify the data transmission rate of the input data directed to the apparatus from the packetized data source, The input memory may be controlled whereby said input data comprising a said packet is removed from the input memory and relaced by fresh input data pursuant to the transfer of said words representing that data packet to the data processor. A step comprising said receiving the outputted input afr from the input memory and detecting, identifying and determining payload size of the data packet therein and generating said payload size signal indicative of the s e of the payload, and a step comprising effecting data processing of the payload may be repetitively and alternatingly executed. A D.MA request signal may be generated when a said word is formed, and applying the DMA request signal to a digital signal processor forming part of said data processing means to cause the digital signal processor to enable a DMA controller to move that data word from the word formatter to an input buffer of the data processor for subsequent processing. The data processing means may execute said detecting and identifying the data packet by detection of a sync-word, followed by verification of the packet ID. The invention also provides apparatus for depacketizing .and aligning packetized input data, having: an input memory for receiving storing, and output of the input data, and for outputting of units of a payload of a data packet of the input data; data processing means for receiving the outputted input data from the input memory and detecting, identifying and determining payload size of the data packet and generating a payload size signal indicative of the size of the payload, and for separately receiving and effecting data processing of the paylo-ad; a word formatter for receiving said units of said payload outputted from the input memory, gathering and .aligning said units to form data words, and outputting said words; a payload counter for controlling the input memory in accordance with the payload size signal whereby to cause the payload units to be outputted from the input memory to the word formatter; and means for traru&rring the data words to the data processing means, to effect said separate receiving of the data packet, when the stored data words complete said payload. The invention also provides a method for depacketizing and aligning packetized input data comprising: receiving and storing the input data in an input memory; outputting the stored input data to data processing means; by use of the data processing means, detecting, identifying and deteπnining the size of a payload of a data packet of the input data outputted thereto; by use of the data processing means, generating a payload size signal indicative of the size of the payload; controlling the input memory in accordance with the payload size signal whereby to cause payload units which form said payload to be outputted from the input memory to the word formatter, by use of said word formatter, gathering and aligning said payload units outputted thereto to foπn data words; outputting said data words from said word formatter to an input buffer and storing these in said input buffer; transferring said data words to the data processing means. The invention further provides apparatus for depacketising and aligning packetised input data, including data processing means which in use detects a payload of a data packet in the input data and processes the payload. The data processing means may repetitively and altematingly execute functions of detecting payloads and processing these. The invention further provides a method for depacketizing and aligning packetized input data wherein functions of detecting a payload of a data packet in the input data and processing the payload are effected separately by the same data processing means. The functions of detecting and processing may be repetitively and altematingly executed sequentially with respect to successive data packets in the input data. In a particular form of the invention, a single programmable proces∞r core is used, as the Data .Processor of the system for processing of the de-packetized data; the detection of sync- wo.rd, decoding of the packet ID, payload size, timing and necessary side information of the data packet which take up only little processing cycles are instead performed by the same Data PjOcessor in software to provide the necessary flexibility. The De-Packetizer hardware can be simplified to an implement^on with only the Payload Counter which controls size of payload transferred and the Word Formatter to align the payload data to the Data Processor word format. By combining the functions of the De-Packetizer which may require flexibility and the data processor implementation on the same programmable processor core, overall system complexity and cost can be mirii.mi.zed; furthermore, the use of a programmable processor core provides maximum flexibility to the De-Packetizer functions. On the other hand, the Payload counter and Word Formatter can take care of simple but repetitive tasks in such a way that overall system performance mziy be significantly enhanced with minimal implementation cost. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a prior art system for de-packetizing and processing data; Figure 2 is a block diagram of a convention circuit for de-packetiring and processing data; Figure 3 is a block diagram of an embodiment of a device for practising die present invention; Figure 4 is a block diagram of an alternate embodiment of the present invention; and Figure 5 is a flow charge illustratmg an embodiment of part of the de-packetizing process according to the present invention. DETAILED DESCRIPTION Referring to Figure 3, Packetized data is input via the data input interface 301 to an input memory formed as an Input FIFO 302. When the Input .FIFO 302 is filled to a predetermined level, data processing means in die foim of a Data Processor 305 is signaled by FIFO Level Fdled Signal 307, and packetized data is read from the Input FIFO 302 by the Data Processor 305 via path 308. The Data .Processor 305 scans die read packetized data for sync-word detection, ID checking, payload size, timing and necessary side information decoding. When a valid packet is detected (by oheclάng die sync-word and ID) and its payload size, timing and necessary side infoπnation decoded, the Data Processor stops .reading packetized data directly from the .Input FIFO 302, sets the Payload Counter 306 with the decoded payload size value, and returns to its normal data processing functions. When the Payload Counter value is set, it starts loadmg the Word Formatter 303 with the payload. The Payload Counter counts as each unit of the payload is being tr.ansfe.rred from die input FIFO 302 to die Word Formatter 303. Tlie Word Formatter 303 gathers and aligns the received payload units according to the data processor word format. After a complete data word is formed in the Word Formatter 303, the data word is transferred to the Input Buffer 304. The Payload Counter 306 stops outputting of die payload from die Input .FIFO 302 to the Word Formatter 303 after it has transferred the full payload s.ώe for the current packet. The Input FIFO 302 is then filled witii the input packetized data, and die wliole piOcess is repeated again. When die .Input Buffer 304 is .filled witii certain required level of de-packetized data, die Data Processor 305 reads the de-packetized data from the Input Buffer 305 for further processing. The Data Processor 305 outputs the results of the processing. Figure 4 illustrates in more detail an embodiment of a device for de-packetizing and aligning input data, according to the present invention. A packetized data source (not shown) is connected to a Data Input .Interface 401 which provides necessary signalling for die external packetized data source as well as possible format conversion. For example, the data input interface may be an enώodiment of a seri^-to-parallel adaptive which converts serial format data such as the I2S foπnat to parallel data. The Data Input Interface 401 is coupled to an Input FIFO 402. Tlie Input FIFO 402 is a first-in-first-out memory buffer for accumulating input packetized data. A suitable size for the Input FIFO 402 depends on die requirements on process latency and processing bandwiddi of the Digital Signal Processor 405. Preferably the Input FIFO 402 has a storage format which is commonly usable by all input packetized data types. For example, the byte format is preferred as most packetized data and payload sizes are .specified in unit byte s.ize; in this case, the Data Input Interface 401 provides die necess.ary conversion of die input packetized data to byte format before storing it into the Input FIFO. The Input FIFO 402 .should contain at least one fullness level detector. This fullness level detector will generate a FIFO Level Filled Signal 407 when the Input FIFO is filled to a level which is equal to and optionally greater than a threshold level defined by die fullness level detector. This tiireshold level may be pre-defined or progr.ammable. A ..second fullness level detector may be provided in the Input FIFO 402 for detecting if die Input FIFO is reaching a fullness level wMch cannot be filled further. This option∑d second fullness level detector will generate the :πecess-ffy .FIFO Full signal 412 to the Data .Input Interface 401 which wUl in turn adjust a possible Data Request agnal 413 to the external packetized data source for stop or start of transmission. Ag.ain, the level for rulings detection in the second fullness level detector can be pre-defined or programmable. It is likely that for most applications the original data such as audio, video, and/or digital multimedia data is packetized and interleaved to form a data stream containing many packets. Before decoding and processing the data stream, it is de-interleaved if necessary and de- packetized. The de-packetization process starts by detecting the sync-word in each packet. This is initiated when the FIFO .Level Filled Signal 407 is generated by die Input FIFO 402. The FIFO Level Filled Signal 407 is connected to an Interrupt Controller 410 which generate an Interrupt Signal 416 to the Digital Signal Processor 405. The Interrupt Controller 410 is used for arbitrating and prioritizing other possible signals in the device. In simplified systems, the .Interrupt Controller may be removed, and die FIFO Level Filled Sigral connected directly to Digital Signal Processor 405. When the Digital Signal Processor 405 is signalled by the Interrupt Signal 416 generated by the FIFO Level Filled Signal 407, it switches to de-packetization process. In this process, the Digital Signal Processor 405 reads direcdy from die Input FIFO 402 through path 414 and the system bus 408. An embodiment of me de-packetization process is illustrated in Figure 5. Basically, on 5 detection of die FIFO level filled signal 500, input packetized data is read, at step 501 and scanned at step 502 for the sync-word. The .sync-word is defined based on applications or packet types, and is norrmilly a digital pattern not easily found within the payload. After detection of die sync-word, he process checks at step 503 for the correct packet ID which may be used to differentiate packets from different data sources, types, or versions. Fault 10 detection of d e sync- word (emulation of the sync- ord within payload data) is also minimized with the packet ID check. If tiiere is wrong ID found, die process is reset to sync- word detection again. After checking the ID, the process executes step 504 at which the correct amount of packetized data is extracted from the Input FIFO for payload size, timing information, and necessary side information Before exiting the de-packetization process (step 15 506), the Payload Counter (406) is set, at step 505 with payload size which defines d e si∞ of the data payload with the current packet. The Input FIFO 402 may become empty while reading by die Digital Si n^ Processor 405 in the middle of the de-packetization process. In this case, the Digital Signal Processor exits 20 the de-packetization process and retum to its original process. When the HFO is filled to the threshold level again, die Digital Signal Processor is signalled again and the de-packetization process resumes. The Payload Counter 406 may include a decrement byte counter which can be set by the 25 Digital Signal Process 405 through the System Bus 408, and some necessary control circuits. When the decrement byte counter is set with die payload size in terms of number of bytes (value greater than zero), a Payload request signal is sent to die Input FIFO 402 through patii 415. If the Input FIFO 402 is not empty, die Word Formatter 403 is not full, .and die decrement byte counter's value is greater tiian zero (payload request signal set), one byte will 30 be transferred from the Input .FIFO 402 to the Word Formatter 403, and the decrement byte counter's value is .reduced by one indicated by payload acknowledge signal from Input FIFO 402 through path 415. Hence, the Payload Counter 406 provides the function of moving the exact amount of payload data of each packet from the Input FIFO 402 to the Word Formatter 403. The Word Formatter 403 .aligns the payload data according to the word format of the Digital Signal Processor 405 and moves d e aligned payload data to an Input Buffer 404. The word format is defined by bit width for a data word handled by the Digital Signal Processor 405. The Input Buffer 404, possible data/program memory 411 for the Digital Signal Processor, and the coupling System .Bus 408 are supporting die same word format. For example, if the word format is given at 16-bit, two bytes must be received from me Input FIFO which is byte format memory to foπn a data word. When a data word is formed, it is transferred to the Input .Buffer 404 via the System Bus 408. A DMA Controller 409 may be used to minimize the interruption to the Digital Signal Processor 405 for die transfer. In this case, when a data word is fo.πned in the Word Formatter 403, a DMA request signal is generated to the DMA controller 409 which in turn make a Transfer request signal to the Digital Signal Proces»r. The Digital Signal Processor acknowledges the request when it releases die System Bus 408. The DMA Controller 409 will tiien move die data word from the Word Formatter to the Input Buffer through die system bus. There may be packets with payload which contain a non-integer number of data words; for example, a packet witii payload size in an odd number of bytes where the data word format is 16-bit. In this example, the last byte of the packet payload is stored in the word formatter until the first byte of the next packet payload is tr.ansfe.rred to the word formatter. Therefore, the Word Formatter 403 provides all necessary data word alignment functions for the packet payload to the .Input .Buffer 404 to form the final de-packetized data which will be processed by die Digital Signal Processor 405. The Digital Signal Processor 405 may be replaced by any otiier suitable programmable processor core in other embodiments .according to the pre∞nt invention. The writing of de-packetized data to the Input Buffer 404 and die reading of it by the Digital Signal Processor 405 can be organi.zed in a circular buffer mode to increase efficiency. In another embodiment of the current invention, it is advantageous to combine the Input Buffer 404 with any Data/Program Memory 411. The present invention does not exclude embodiments with multiple word formatter a d input buffers, as it can be easily expanded to handle de-interleaving, de-packetization and alignment of multiple packetized input data. With the coupling of die payload counter .and word formatter with data input interface and input FIFO, the present invention provides a very low cost but efficient implementation for de-packetizing .and ahgning packeti.zed input data. Tl e payload counter and word formatter combination releases data processing load from die data processor for the system. Its capability of aligning the de-packetized data for the input buffer allows saving of memory size .needed for the input buffer and hence saving of implementation cost. The described arrangements of the invention have the ability of .sliaring the data processing task and d e part of d e de-packetizing task with the same data processor .and therefore provides all needed flexibility in die de-packeάαng task. The described arrangements have been aadvanced merely by way of explanation any many modifications may be made thereto without departing from die spirit and scope of the invention which includes eve.ry novel feature and combination of novel features herein disclosed.

Claims: CLMMS.- 1. Apparatus for depacketizing and aligning packetized input data, having: an input memory for receiving storing, and output of the input data, and for outputting of units of a payload of a data packet of the input data; data processing means for receiving the outputted input data from the input memory .and detecting, identifying and determining payload size of the data packet and generating a payload size signal indicative of the size of the payload, and for separately receiving and effecting data processing of the payload; a word formatter for receiving said units of said payload outputted from the input memory, gathering and aligning said units to form data words, and outputting said words; a payload counter for controlling the input me oiy in accordance with the payload size signal whereby to cause the payload units to be outputted from the input memory to the word formatter; and an input buffer for receiving said data words from the word formatter .and storing these, and for transferring the data words to the data proce.ssing means, to effect said separate receiving of said payload; said data processing means for effecting ..said data processing using the received said data words. 2. Apparatus as claimed in claim 1 having a data input interface through which the input data is transferred to d e input memory, said data input interface for performing hand shaking with a packetized data source of said input data. 3. Apparatus as claimed in claim 1 or claim 2 wherein the input memory has a fullness level detector for generating a level filled signal when the input data received thereby is such as to .fill the input memory to a predetermined level, and said data processing means is responsive to generation of said level filled signal to execute said receiving the outputted input data from the input memory and detecting, identifying and determining payload size of the data packet and generating said payload size sigωl. 4. Apparatus as claimed in claim 3 having an interrupt controller, for receiving said level filled signal and generating an interrupt signal pursuant to receipt thereof, said data processing means being arranged for receipt of said interrupt sign^ and, on receipt thereof, for executing said receiving the outputted input data from the input memory and detecting, identifying and determining payload size of the data packet therein and generating said payload size signal. 5. Apparatus as claimed in claim 3 or claim 4, as appended directly or indirectly to claim 2, wherein the input memory lias a .further fullne^ level detector for generating and directing to said data input interlace a further level filled agi l when the input thereto of fresh input data is such as to fill die input memory to a .further predetermined level, said data input interface being responsive to receipt of said further level filled signal to generate a data request signal for direction to said packetized data .source, indicative of a need to modify the data transmission rate of the input data directed to the apparatus from the packetized data source. 6. Apparatus as claimed in any preceding claim wherein the input memory is controlled whereby said input data comprising said packet is removed from the input memory and relaced by fresh input data, pursuant to the tranter to the data processing means of said words representing the data packet to the data the apparatus being arranged for repetitive depacketizing and aligning of data packets and data processing thereof, the data processing means being arranged for repetitively and altematiaOgly executing a step comprising said receiving the outputted input data from the input memory and detecting, identifying and determining payload size of the data packet therein and generating said payload size signal, and a step comprising said separately receiving and effecting data processing of the payload of the data packet. 7. Apparatus as claimed in .any preceding claim wherein the data processing means includes a digital .signal processor, data/program memory, DMA controller and input buffer, each in data communication via a bus. 8. Apparatus as claimed in claim 7, wherein the word formatter is arranged for generating a DMA request signal when a said data word is formed thereby, and the DMA controller is responsive to said DMA request signal to generate and direct a transfer signal to the digital signal processor, the digital signal processor being responsive to the transfer signal to enable the DMA controller to move the data word from the word formatter to the input buffer for subsequent processing. 9. .Apparatus as claimed in claim 5 wherein said input memory is a first in first out memory. 10. Apparatus as claimed in any preceding claim wherein the data processing means is arranged to execute said detecting and identifying the data packet by detection of a sync-word, followed by verification of the packet ID. 11. .Apparatus as clai.med in any preceding claim wherein the data processing means, pursuant to said detecting and identifying the data packet, extracts timing information from the input data. 12. Apparatus as claimed in any preceding claim wherein the data processing means, pursuant to said detecting and identifying the data packet, ej xacts side information from the input data. 13. A method for depacketizing and aligning packetized input data comprising: receiving and storing the input data in an input memory; outputting d e stored input data to data processing means; by use of the data processing means, detecting, identifying and determining the size of a payload of a data packet of the input data outputted thereto; by use of the data processing means, generating a payload size signal indicative of d e size of the payload; coπtrollύig the iiψut memory in .acco.rdaπce with the payload size signal whereby to cause payload units which form said payload to be outputted from the input memory to the word formatter; by use of said word formatter, gadiering and aligning said payioad units outputted thereto to form data words; outputting .said data words from said word formatter to an input buffer and storing these in said input buffer; transfeiring said data words to the data processing means; and effecting data processing on the data packet represented by the data words transferred thereto, using the transferred data words. 14. A method as claimed in claim 13 wherein the input data is transferred to the input 5 memory via an data input interface which performs hand shaking with a packetized data source of said input data. 15. A med od as claimed in claim 13 or claim 14 including the step of generating a level filled signal when the input data received by the input me oiy is such as to fill the input memory to 10 a predetermined level, and causing said data processing means to effect .said detecting, identifying .and determining payload size of the data packet, and to said generate payload size signal, pursuant to generation of the level filled signal. 16. A method as claimed in claim 3 including d e step of generating an interrupt signal from 15 said level filled signal and directing said interrupt signal to said data processing means to cause said data proces.sing means to effect said receiving the outputted input data from the input memory and detecting, identifying and determining payload size of the data packet therein and to generate said payload size signal. 20 17. A method as claimed in claim 15 or claim 16, as appended directly or indirectly to claim 14, including the step of generating and directing to said data input interface a further level filled signal when die input thereto of fresh input data is such as to fill die input memory to a further predetermined level, and causing said data input interface to generate, responsive to receipt thereby of said further level filled signal, a data request signal for direction to said packetized 25 data source, indicative of a need to modify the data transmission rate of the input data directed to the apparatus from the packetized data source, 18. A method as claimed in any one of claims 13 to 17 wherein the input memory is controlled whereby said input data comprising a said packet is removed from the input memory 30 and relaced by fresh input data pursuant to the transfer of said words representing that -lata packet to the data processor, and wherein a step comprising said receiving the outputted input data from me input memory and detecting, identifying and determining payload size of the data packet tiierein and generating said payload size signal indicative of the size of the payload, and a step comprising effecting data processing of the payload are repetitively .and altematingly executed. 5 19. Amethod as claimed in claim 18, including generating a D.MA request signal when a said word is formed, and applying the DMA request signal to a digital signal processor forming part of said data processing means to cause the digital signal processor to enable a DMA controller to move that data word from the word formatter to an input buffer of the data processor for 10 subsequent processing. 20. A method as claimed in .any one of claims 13 to 19 wherein said input memory is a first in first out memory. 15 21. A metiiod as claimed in any one of ckrims 13 to 20 wherein the data processing means executes said detecting and identifying the data packet by detection of a sync-word, followed by verification of the packet ID. 22. A method as claimed in any one of claims 13 to 21 wherein the data processing means 20 extracts timing information from d e irφut data pursuant to said detecting and identifying the data packet. 23. A method as claimed in any one of claims 13 to 22 wherein the data processing means extracts side information from d e input data pursuant to said detecting and identifying the data 25 packet. 24. .Apparatus for depacketizing and aligning packetized input data, having: an input memory for receiving storing, and output of the input data, and for outputting of units of a payload of a data packet of the input data; 30 data processing means for receiving the outputted input data from the input memory and detecting, identifying and determining payload size of the data packet and generating a payload size signal indicative of the size of the payload, and for separately receiving and effecting data processing of the payload; a word formatter for receiving said units of said payload outputted from the input memory, gathering and aligning said units to form data words, and outputting said words; a payload counter for controlling the input memory in accordance with the payload size signal whereby to cause the payload units to be outputted from the input memory to the word formatter, and means for transferring the data words to die data processing means, to effect said separate receiving of said payload. 25. Amethod for depacketizing and aligning packetized input data comprising: receiving and storing the input data m an input memory; outputting the stored input data to data processing means; by use of the data processing means, detecting, identifying and determining the size of a payload of a data packet of the input data outputted thereto; by use of the data processing means, generating a payload size signal indicative of the size of the payload; controlling die input memory in accordance with the payload size signal whereby to cause payload units which form said payload to be outputted from die input memory to the word formatter; by use of said word formatter, gathering and aligning said payload units outputted thereto to form data words; outputting said data words from said word formatter to an input buffer and storing these in said input buffer; transferring said data words to the data processing means. 26. Apparatus for depacketising and aligning packetised input data, including data processing means which in use detects a payload of a data packet in die input data and processes the payload. 27. Apparatus as claimed in claim 26 wherein the data processing means repetitively and alternatingly executes functions of detecting payloads and processing these. 28. A method for depacketizing and aligning packetized input data wherein functions of detecting a payload of a data packet in the input data and processing the payload are effected separately by the same data processing means. 29. Amethod as claimed in claim 28, wherein said functions are repetitvely and altematingly executed with respect to successive data packets in the input data.

Inventors: HUI YAU WEI LUCAS, LABORIE JEAN LOUIS, LASSURE GAEL, HUI, YAU, WEI, LUCAS, LABORIE, JEAN, LOUIS, LASSURE, GAEL
Applicants: HUI YAU WEI LUCAS, LABORIE JEAN LOUIS, LASSURE GAEL, SGS THOMSON MICROELECTRONICS, SGS THOMSON MICROELECTRONICS A, HUI, YAU, WEI, LUCAS, LABORIE, JEAN, LOUIS, LASSURE, GAEL, SGS-THOMSON MICROELECTRONICS ASIA PACIFIC (PTE) LTD., SGS-THOMSON MICROELECTRONICS S.A.
Application year: 1997
Main classification: H04J3
IPC codes: H04J3, H04L12