ULTRA-LOW POWER-DELAY PRODUCT NNN/PPP LOGIC DEVICES

Abstract: Transistors have source, drain and bulk regions all of the same conductivity type. The bulk region is very thin, not more than about 500 ANGSTROM and preferably about 300 ANGSTROM or even 100 ANGSTROM in thickness. A very thin oxide layer having a thickness of much less than about 100 ANGSTROM , such as 20 ANGSTROM and preferably about 5 to about 10 ANGSTROM , isolates a gate electrode from the bulk region. When operated at temperatures at or below 150 DEG K, such as 77 DEG K, very low threshold voltages, well below 25 millivolts, are achieved. Gigahertz speed complementary MOS transistors, formed by adjacent NNN and PPP devices exhibit power-delay products of about 1E-16 joules operating at supply voltages on order 100 millivolts or lower, making this technology of particular interest for multi-gigahertz processing rates at very low power.

Description: ULTRA-LOW POWER-DELAY PRODUCT NN/PPP LOGIC DEVICES BACKGROUND OF THE INVENTION Field of the Invention This invention is directed to very thin gate oxide semiconductor devices having source, drain and channel regions all doped with dopants of the same conductivity type, and to complementary devices in which the three regions of one device are all of the same conductivity type, but opposite to the conductivity type of the three regions of the other device. Background Information Conventional complimentary metal oxide silicon (CMOS) transistors have source and drain regions of the same conductivity type with a channel region between of the opposite conductivity type. Thus, one transistor is a npn device and the complimentary transistor is a pnp type These devices have a threshold voltage which is typically about 500 to 1500 millivolts Furthermore, the capacitance of such devices is high due in part to an oxide layer of about 100 TO 500 Angstroms (A) in thickness insulating the gate electrode from the channel region. Since the power required by these devices and their switching speed are both direct functions of the capacitance and threshold voltage, they are relatively power hungry and slow for certain applications One such application is an interface between high temperature superconducting (HTSC) circuits, typically operating at 77°K, and conventional silicon devices operating at ambient conditions p00°K) The HTSC circuits potentially have P * Tau (power-delay) product capabilities as low as the I E- 17 to the I E- 16 joule level Because of the relatively high threshold voltages and slow response times of conventional silicon NPN/PNP logic families, they themselves do not approach such power-delay products, and hence, are a poor match to serve as glue circuits for the HTSC families There is a need therefore, in general, tor higher speed, significantly lower power semiconductor devices, and there is a particular need for such a device which can serve for instance as an interface between HSTC circuits and ambient silicon devices In this connection, there is a need tor improved semiconductor devices which have lower thiesholcl voltages, and particularly well below about the 100 millivolt level SUMMARY OF THE INVENTION These needs and others are sattsfied by the invention which is directed to a semiconductor device comprising a substrate, an active layer on the substrate having spaced apart source and dram regions, both of the same conductivity type, and a bulk region between the source and dram regions, also of the same conductivity type A key feature is that the bulk region is no more than about 500A thick and preferably only about lOOA thick An oxide layer is provided between the bulk region and a gate electrode. Another important feature of the invention is that this oxide layer is no more than about lOOA thick, but more likely only about 2θA thick, and preferably between about 5 and lOA in thickness The devices are adapted for operation at temperatures which pin the Fermi level near or at the majority dopant level, thus, temperatures from less than about I 50°K to about 77°K Electrodes are also provided for the source and drain regions Complimentary devices are provided by one such device in which the source, bulk dram regions are N + , N, N and an adjacent P + , P, P+ device Preferably, an oxide layer is provided between the substrate and the active layer to more easily establish the thickness ot bulk region Preferably, the active layer is silicon, although other materials with MOS properties such as silicon carbide, and gallium arsenide can be used As is known, doped polysilicon can be used in place of metal for the electrodes, including the gate electrode The thinness of the bulk region between the source and drain keeps the current which flows at a zero value ot gate voltage to a minimum. It can be shown that ON/OFF ratios of 100 or more can be easily met by a combination of a 200A thick bulk region between the source and drain regions and the fact that a small reverse bias on the gate electrode (a few millivolts) depletes the channel in the bulk region completely, forcing the current to near zero at the origin of the VI (voltage/current) curve. In a preferred form of the invention, the bulk region has a dopant - thickness product of about 3 to 10EI0 charges/cm 3 . Also, the length of the bulk region, between the source and dram regions, is from about 500A to 2500A and preferably about 1250A. BRIEF DESCRIPTION OF THE DRAWINGS A full understanding of the invention can be gained from the following description of the preferred embodiments when read in conjunction with the accompanying drawings in which: Figure 1 is a diagram of a prior art CMOS device. Figure 2 is an energy level diagram for the prior art CMOS device of Figure 1. Figure 3 is a section through a semiconductor device in accordance with the invention. Figure 4 is an energy diagram for the NNN device in accordance with the invention. Figure 5 is a plot of the Fermi level versus temperature for several doping levels of the bulk region of a device in accordance with the invention. Figure 6 A is a plot of mobile charges per square centimeter versus gate voltage illustrating the threshold voltage of an NNN device in accordance with the invention Figure 6B is a similar plot on a smaller scale illustrating a comparison of the threshold voltage ot the NNN device with that of a conventional NPN device Figure 7 is a plot ot electron concentration versus temperature for several doping levels of the bulk material in an NNN device of the invention Figure 8 is a plot ot power dissipation versus speed for several semiconductor devices including the invention DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to better understand the invention it is helpful to consider first a conventional CMOS device 1 such as shown in Figure I . This device 1 includes an npn transistor 3 formed by N + source and drain regions 5 and 7 and a P region 9. A thin oxide layer 1 1 extends over the source, bulk and drain regions. Typically, this oxide layer 1 1 is lOOA to 50θA thick. A metal or polysilicon gate electrode 13 is isolated from the bulk region 9 by the oxide layer 1 1. Source and drain electrodes 15 and 17, respectively, are positioned through the oxide layer 1 1 over the source and drain regions. A complimentary PNP transistor 1 adjacent to the end NPN transistor 3 includes P+ source region 21 and drain region 23 separated by an N type substrate 25. The oxide layer 1 1 extends over these regions and insulates a gate electrode 27 from the bulk region formed by the substrate 25. Electrodes 29 and 31 positioned through the oxide layer 1 1 form source and drain electrodes, respectively. Figure 2 is a Fermi diagram for the NPN transistor portion of Figure 1 . In this diagram, E c is the conduction band, E v is the valence band, E d is the donor level, and E F is the Fermi level. The p doping of the p region 9 in the NPN device 3 leads to a high threshold voltage shown by the fact that the onset of current requires that the conduction and valence bands bend as indicated at point 33 by 2φ which is typically about 0.5 to 0.75 volts. As mentioned above, this high turn-on gate voltage makes the device 3 power hungry and slow, since the gate capacitance has to be charged up to to on order 2φ volts. In contrast to the conventional CMOS devices of Figure 1 , the present invention is directed to devices which utilize the same conductivity type of material for the source, drain, and bulk regions. Thus, as shown in Figure 3, a complimentary device 35 includes an NNN transistor 37 and a PPP transistor 39 formed side- by-side in an active layer 41 formed on a substrate 43. Preferably, an oxide layer 45 is provided between the substrate 43 and the active layer 4 1 . The NNN device 37 is formed by an N + source region 47 and an N + drain region 49 spaced apart in the active layer 41 by the N bulk region 1 . A thin oxide layer 53 insulates a gate electrode 55 from the bulk region 5 1 . The oxide layer 53 also extends over the source and drain regions 47 and 49 where source and chain contacts 57 and 59, are formed , respectively The PPP device 39 includes a P + source region 61 and a P + drain region 63 in the active layer 4 1 separated by a P bulk region 65 As in the case of the NNN device, a thin oxide layer 67 insulates a gate electrode 69 from the bulk region 65 and extends across the source and dra region 61 and 63 where a source electrode contact 71 and a dram electrode contact 73 are formed The bulk regions 51 and 65 are very thin; namely, less than about 500A in thickness and preferably only about 300A, but even about lOOA The oxide layers 53 and 67 are also very thin, namely not more than about lOOA but more like 2θA and preferably 5 to lOA The length of the bulk regions 51 and 65, between the source and drain regions is between about 500 to 2500A and preferably about 500 to 1500A with 1250A being suitable Preferably the active layer 41 is silicon into which the source and drain region are diffused and separated by photolithography techniques to form the bulk regions However, other materials exhibiting MOS activity such as silicon carbide and gallium arsenide could be utilized The source and dram regions 49, 63 and 47, 61 in the illustrative device are doped to about 1 E20 charges/cm' The bulk regions 51 and 65 can be doped to levels ot about 1 E+ 16 charges per cm 1 to produce 'dopant- thickness products in the range of about 3 to about 30 E+ 10 charges per cm 2 As shown by the Fermi diagram of Figure 4 for NNN device 37, the voltage drop required to move the Fermi level E, to the onset of conduction E t , does not contain the2φ voltage term In particular, with the bulk regions 51 and 65 doped to about the lE16/c , range, the Fermi level at 77K just about sits on the donor level E d , which is only about 50 milh-electron volts away trom the conduction band E c for phosphorous as can be seen in Figure 5 at the point 75 for the I E + 16 dopant curve 77 It is a key principle of the invention that the teinpeiature is used to pin the Fermi level E , near or at the majority dopant level E,, in Figure 4, a known small distance from the majority carrier band edge where it is ready to cause conduction with the smallest of applied surtace fields The onset ot gate voltage for conduction is then the band bending at 79 which is equal to about E.,/2 volts, a much smaller value than the2φ volts required by the conventional CMOS devices as shown in Figure 2 The following equation shows the components tor the threshold voltage in a conventional MOS transistor Vτ - 2 Φ rø + - + V WF Eq. ( 1) ( -ox The first term is the band bending voltage drop which for an NPN transistor is about 0.8 volts. The second term is the space charge voltage drop which is typically about 1 volt. The final term is the work function difference voltage drop which can be made negligible with proper adjustment of the gate metal or polysilicon work function. Thus, the threshold voltage for the typical conventional MOS device can be as high as about 1.8 volts. For an NNN device in accordance with the invention, the threshold voltage for conduction is: F - F V; - c 2 d Eq. (2) Comparing Equation 2, to Equation 1 above, it can be seen that the second and third terms of Equation 1 are absent in an NNN or PPP device and the first term, 2φ of Equation 1 , is replaced in Equation 2 by only the minuscule band bending associated with the small movement of the Fermi level from E d to the conduction band edge E c , a few tens of millivolts. It should be noted that the imposition of the oxide layer 45, 67 between the gate 55, 69 and the bulk region 5 1 , 65 usually doubles this contribution for oxides as thin as 2θA or so. Thicker oxide layers can be deleterious to a small threshold voltage. Thus, it is expected that a thin oxide NNN device with threshold voltages on the order of the donor energy, E d , can be achieved, yet it can still be expected, with low oxide fields, to drive the Fermi level into the conduction band where high currents and high speeds occur. In Figure 6a is shown the results 81 of a graphical calculation of the mobile carriers in an NNN transistor versus gate voltage where the oxide layer 53 was 20A thick and the temperature 77K. The bulk region 5 1 was doped to l Elό/cm 1 and 200A thick. Note that the current starts almost immediately from the origin , with a non-linearity that seems to indicate a threshold gate voltage of about 20 millivolts at 83. As important as the low threshold is the fact that at only 60 millivolts total on the gate a channel electronic conduction layer of 3E1 1 carrier/cm2 is achieved at 84, a large value for such a low gate voltage. Contrast this behavior with the curve 85 in Figure 6b for a 20A thick oxide layer and temperature of 77K for a l Elό/cm 1 conventional thick bulk region NPN device. Curve 81 for the NNN device is also included in Figure 6b for comparison. The 2φ plus the space charge term of Equation 1 drives the turn-on voltage of the conventional thick bulk region NPN device, curve 85, to the right in Figure 6b resulting in a difference in threshold voltage of about 880 millivolts, even with a 2θA thin oxide in the NPN device. This essentially ruins the NPN/PNP system for being able to achieve 100 millivolt supply voltage logic. There are ways in the literature to adjust threshold voltages in MOST devices. However, adjusting the threshold voltage to an accuracy of around a fraction of tens of millivolts with either 1 ) ion implantation, or 2) separate substrate voltage manipulation (as is recently known in the art), will not effectively permit the precise control of the overall chip threshold voltages to such accuracy as the NNN/PPP devices discussed herein where the discussion is in terms of eliminating the root causes of the large threshold voltages and especially their dependance on the inevitable non- uniformity of substrate doping that occurs across the wafer during fabrication. Both the fact that an N/N/N structure is utilized, and that both the oxide and the silicon layers are so thin greatly decreases the sensitivity of the threshold voltage to the substrate doping. Figure 7 which is a plot of the electron concentration versus temperature for three levels of doping of the bulk region, deals briefly with the fact that at 77K, l Elό/cm 1 material shown by the trace 87 partially deionizes at the point 89. This helps in two ways: I) it is this deionization which helps pin the Fermi level near E d , close to the conduction band edge "ready to go" , 2) the bulk region 51 in Figure 3 is now less conducting, raising the on-to-off ratio of the device. As mentioned above, this is not of extreme importance when the l E I ό/cm 1 material is so thin ( lOOA to 200A) such that a few negative millivolts on the gate completely depletes the substrate shutting off the current and making the on-to-off ratio extremely high. Additionally, note that when the silicon thickness of layer 45 in Fig. 3 is made much thinner than the Debye length associated with the dopant N 0 of the bulk layer of the NNN device, where the Debye length is well-known in the semiconductor literature, then the threshold voltage ot the NNN devices becomes rather insensitive to both the thickness of layer 45 and its exact n doping level . This makes the device significantly easier to fabricate reproducibly than might be expected from fabrication of thick base bulk region MOS devices ( ~ 1000A + ) presently known to the art The following is a calculation of the operating capabilities (drain current I, transconductance g , capacitance C and operating frequency f^) of an N+/N/N + transistor having an N type channel mobility μ n of 2000 cm 2 /volt sec (at 77°K), a charge q, a channel length L of 0.25 microns, a channel width W of 5.0 microns and a g cate oxide with a thickness W n O r X of 20 A and dielectric constant e oχ of .33E- 12 farads/cm with a Vsupply of 0. 100 volts W 1 I =4*n x Q mMt {60mv) x - x V^ p≠y Eq. 3 V L = 192 microamperes (taking the vtilut of β,.. A( , from point 84 in Fig 6a). dl 192 X 10 " s n = 4 8 X 10 "3 mhos Eq 4 dVg v . 4 volts supply * const C = -^ = 2.1 X 10 _ F Eq 5 f oper ~ -^- = 36GHZ E 6 2π C Assuming a fan-out of 3 so that the capacitance of the load C lθjd equals 3 X C paU ., then for an operating frequency of about 12GHz Power = I V ' , y = 19 2 X 10 6 watts Eq 8 PT = 2 5 X lO ' i6 Joules Eq 9 This is an impressively low value lor silicon technology, a value that is this low because with the invention disclosed herein one can operate at very low supply voltages due to the low and well-matched thieshold voltages and the very thin gate oxides employed in the logic Finally, Figure 8 illustrates competitive P x TAU products for other devices Note that CMOS 91 and cooled CMOS 93 have P x TAU products of about 1 to 2E- 13 joules, whereas the logic proposed herein 95 has P x TAU products, assuming a fan out of 3, of 2E- I 6, about 1000X smaller than present silicon devices 91. Note that the 50 ps delays of the proposed devices are nicely matched to the 10 ps delays of the Josephson Junction Latching Logic Series 97. In other words, a stage or two of the transistors described in this invention can amplify the JJ signals up from I millivolt to the 40 millivolts needed to drive these devices whereas the difference in delay of a factor of 5 can be made up by a simple 5 X multiplexer, again using the 3 Ghz transistors from the proposed invention Figure 8 also illustrates the performance of Josephson Junction Single Quantum Flux (JJSFQ) devices 99, as well as gallium arsenide MESFETs 101 , cooled MODFETs 103, and silicon bipolar devices 105. The low power NNN/PPP technology of the invention, offers very attractive silicon-based P x TAU products and speed A low temperature environment has been described; however, use of the teaching herein should also be beneficial at higher temperatures, although to a lesser degree. A preferred SOI embodiment is described since such a structure offers attractive DC isolation between the NNN and PPP devices as well as a low total device-to-physical -substrate capacitance Non-SOI configurations are also possible that take advantages of the teaching herein It is important to get the work function difference between the gate 13 and the channel region 9 in Figure 1 as low as possible. This suggests that the polysilicon gate 13 and the background doping of the P channel region 9 be simultaneously-doped with the same implantation, the voltage of the implantation being chosen to be low enough that the doping ot the gate is enough higher than that of the channel so as to guarantee that there is not a voltage drop across the gate due to the (depleting) gate oxide field This would raise the threshold voltage of the NNNMOST A compromise is necessary: Heavily doped gates mean no depletion but a larger effect due to work function differences The thin 2θA oxide layei should not be particularly susceptible to tunnelling since the fields are low ( I L 5 v/cni) Note that the oxide can be increased to 2θA to 30A without af fecting the speed (Cm and the Capacitance both essentially increase with Wox) only the power increases, which can be nicely traded against gate leakage due to direct gate oxide tunnelling it needed. Taktng full advantage of the speed of this technology may require using low capacitance lines, perhaps suspended in air as is known m the art. While specific embodiments ot the invention have been described in detail, it will be appreciated by those skilled in the art that various modifications and alternatives to those details could be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements disclosed are meant to be illustrative only and not limiting as to the scope of invention which is to be given the full breadth of the claims appended and any and all equivalents thereof.

Claims: What is Claimed is: 1. A semiconductor device adapted to be operated at a temperature less than about 150° K comprising: a substrate; an active layer on said substrate having a source region and a drain region each of a same conductivity type and a bulk region of said same conductivity type between said source region and drain region and having a thickness of no more than about 500A; an oxide layer of no more than about lOOA in thickness over said bulk region; a gate electrode on said oxide layer; and electrodes for said source and drain regions. 2. The semiconductor device of Claim 1 wherein said active layer is selected from a group consisting of silicon, silicon carbide, and gallium arsenide. 3. The semiconductor device of Claim 1 including an insulating layer between said active layer and said substrate. 4. The semiconductor device of Claim 3 in which said bulk region of said active layer is about I00A thick. 5. The semiconductor device of Claim 3 wherein said bulk region is about 20θA thick. 6. The semiconductor device of Claim 5 wherein said oxide layer is no greater than about 20A thick. 7. The semiconductor device of Claim 6 wherein said oxide layer is about 5 to about lOA thick 8 The semiconductor device of Claim 7 wherein said bulk region has a dopant/thickness pi duct of about 3 to about 30EI0 charges/cm 2 9 The semiconductor device of Claim 8 wherein said bulk region has a length between said source and drain regions of about 500 to about 2500A 10 The semiconductor device of Claim 9 wherein said bulk region has a length of about 1000 to 1500A 1 1 The semiconductor device of Claim 5 wherein said bulk region has a length between said source and drain regions of about 500 to about 2500A. 12 The semiconductor device of Claim 1 1 wherein said bulk region has a length of about 1000 to about 1500A. 13 The semiconductor device of Claim 5 wherein said bulk region has a dopant/thickness product of about 3 to about 30E10 charges/cm 14 The semiconductor device of Claim 1 wherein said active layer has a first source region, a first dram region and a first bulk region all of a first conductivity type and a second source region, a second drain region and a second all of a second conductivity type, said first and second bulk regions each having a thickness of no more than about 500A, a said oxide layer of no more than about lOOA in thickness is provided over both said first bulk region and said second bulk region, a said gate electrode is provided on each oxide layer, and electrodes are provided for each of said first and second source and drain regions 15 The semiconductor device of Claim 14 wherein said active layer is selected from a group consisting of silicon, silicon carbide, and gallium arsenide and an insulating layer is provided between said active layer and said substrate 16 The semiconductor device of Claim 15 wherein said first and second bulk regions are about 300A thick and have a dopant/thickness product of about 3 to about 30E10 charges/cm 17 The semiconductor device of Claim 16 wherein said oxide layers are about 5 to I A thick 18 The semiconductor device of Claim 17 wherein said first and second bulk regions each have a length ol about 500 to about 2500A

Inventors: NATHANSON HARVEY N, NATHANSON, HARVEY, N.
Applicants: NORTHROP GRUMMAN CORP, NORTHROP GRUMMAN CORPORATION
Application year: 1997
Main classification: H01L27
IPC codes: H01L21, H01L27, H01L29