Power supply circuit

Abstract: A resistor is inserted between the gate of an FET and a feedback winding to produce a delay in a voltage applied to the gate of the FET in comparison with a voltage of the feedback winding due to the influence of an input capacitance existing at the gate of the FET. Thus, a current does not flow before a drain voltage of the FET reaches zero volt, thereby making it possible to reduce the switching loss.

Description: The present invention relates to a power supply circuit. As a prior art power supply circuit of the type associated with the subject matter of the present invention, there is a charging circuit for charging a battery as described in United States Patent 5,333,104. Fig. 8 illustrates this prior art circuit which comprises a series circuit of an LC resonance circuit formed of a parallel circuit of a resonance capacitor C 1 and a primary winding L 1 , a parallel circuit of a diode D 1 and a resistor R 1 , and an FET Q 1 , which is a voltage driven switching element, connected to a direct current power supply E; a series circuit of a resistor R 2 and a capacitor C 2 connected to the direct current power supply E; a feedback winding L 3 magnetically coupled with the primary winding L 1 and arranged between a connection point of the resistor R 2 and the capacitor C 2 and the gate of the FET Q 1 to constitute a oscillating transformer T; and a series circuit of a resistor R 3 and a diode D 2 through which a connection point of the resistor R 2 and the capacitor C 2 is connected to a connection point of the primary winding L 1 and a diode D 1 , thus constituting an invertor. The resistor R 2 and R 3 , the capacitor C 2 , and the diode D 2 constitute a starting circuit for stabilizing oscillation, a bias circuit, and a bias control circuit. A secondary winding L 2 , which has a median tap magnetically coupled to an oscillating transformer T for generating a secondary output, has both ends connected to a plus pole of a secondary battery B, subjected to charging, through diodes D 3 , D 4 , and the median tap connected to a minus pole of the secondary battery B subjected to charging, such that the secondary battery B subjected to charging is charged with a secondary output. Next, the operation of this exemplary circuit of the prior art will be described. When the direct current power supply E is now turned on, the capacitor C 2 is charged by a current Is 1 passing through the resistor R 2 . By this charging, the voltage of the capacitor C 2 is increased, and when this voltage reaches a threshold voltage of the FET Q 1 , the FET Q 1 becomes active and turns on. The FET Q 1 in on-state causes a current IL 1 illustrated in Fig. 9(b) to flow through the primary winding L 1 , leading to a voltage induced across the feedback winding L 3 to perform a feedback operation, thus starting oscillations. Here, during a period in which a drain voltage V D of the FET Q 1 is lower than the voltage across the capacitor C 2 , charges on the capacitor C 2 is discharged by a circuit including the capacitor C 2 , the resistor R 3 , a diode D 2 , the diode D 1 , and the resistor R 1 , the FET Q 1 , and the capacitor C 2 , causing a discharge current Is 2 to flow, as illustrated in Fig. 8. This discharge current Is 2 reduces the voltage on the capacitor C 2 lower than the threshold voltage at the gate of the FET Q 1 , whereby an on-period becomes shorter. As the on-period is shorter, the current Is 2 for discharging the charges on the capacitor C 2 is reduced so that the voltage across the capacitor C 2 is increased to apply a negative feedback in a direction in which a vias voltage V G2 is stabilized, as illustrated in Fig. 9(g), thereby achieving a stable self-excited oscillating operation. Fig. 9(a) illustrates a voltage V C across both ends of the resonance capacitor C 1 , and Fig. 9(b) illustrates a current IL 1 flowing through the primary winding L 1 . Fig. 9(c) illustrates a voltage V F at a connection point of a resonance circuit formed of a parallel circuit of a capacitor C 1 and the primary winding L 1 and the diode D 1 . The diode D 1 between the FET Q 1 and the LC resonance circuit serves to block an inverse current from passing through a parasitic diode of the FET Q 1 . In the exemplary circuit of the prior art illustrated in Fig. 8, a sinusoidal voltage V G induced by the feedback winding L 3 is applied to the gate of the FET Q 1 , as illustrated in Fig. 9(f), and a peak value of the sinusoidal wave is near the threshold voltage of the FET Q 1 . A current I D flowing through the FET Q 1 , illustrated in Fig. 9(e), begins to flow before the drain voltage V D of the FET Q 1 , illustrated in Fig. 9(d) reaches zero volt, and the current I D does not yet decrease to zero even after a drain voltage V D of the FET Q 1 begins to increase. This causes a problem that a switching loss occurs in the FET Q 1 . Document JP-A-2 241 362 discloses a driving circuit for a self-excited single converter in which a base resistor R 1 is used in connection with an inductor L to change the shape of the base current from a rectangular shape to a triangular shape so as to reduce the loss of the base resistor due to a reduced effective base current. Further, this document discloses a current-driven switching element, i.e. a bipolar transistor, wherein the driving current is reduced in order to reduce the loss of the base resistor R 1 . However, such a base resistor necessarily is provided as a current limiting element for the current-driven switching element. Moreover, according to the teaching of this document an inductor L is suggested to be introduced in order to change the wave form of the base current flowing through the base resistor, to thereby reduce the loss of the base resistor. Furthermore, document JP-A-60 204 261 shows a self-excited oscillator circuit with which the power loss is reduced and a switching transistor is prevented from damaging by increasing the bias amount of the base current of the transistor when the collector current of the transistor increases. The present invention has been made in view of the problem mentioned above, and its object is to provide a power supply circuit comprising a highly efficient and reliable invertor circuit which is capable of suppressing the switching loss of a voltage driven switching element. According to the present invention, this object is solved by a power supply circuit as defined in the appended claim 1. Advantageous modifications are as set out in the appended dependent claims. Thus, the present invention provides a power supply circuit which comprises an LC resonance circuit, a feedback winding, a voltage driven switching element, a bias circuit for applying a bias voltage to a control terminal of the switching element, and a bias control circuit for controlling the bias voltage, thus constituting an invertor adapted to operate in a self-excited oscillation, wherein a first resistor is connected between the feedback winding and the control terminal of the switching element for delaying the phase of an alternate current voltage generated in the feedback winding, thus making it possible to effectively realize a highly efficient and reliable power supply circuit which eliminates a switching loss of the switching element and suppresses undesired losses. The aforementioned invention additionally includes a series circuit of a second resistor and a first diode connected between a connection point of the LC resonance circuit and the switching element and the bias circuit as the bias control circuit, so that more stable oscillations can be provided by the bias control circuit while suppressing undesired losses. Furhter the invention may includes a circuit for controlling the bias voltage with a current flowing through the switching element as the bias control circuit, so that more stable oscillations can be provided by the bias control circuit while suppressing undesired losses. The above invention additionally includes a second diode connected in parallel with the first resistor, thus making it possible to suppress a delayed voltage at the control terminal of the switching element, when it is turned off, by a forward voltage of the second diode to prevent losses of the switching element from increasing. The above invention additionally includes a transistor which turns on to control the bias voltage when a current flowing through the switching element reaches a predetermined value, and a delay capacitor connected to the base of the transistor for delaying an off-operation of the transistor, so that an off-operation of the transistor can be delayed to thereby rapidly decrease a current flowing through the switching element, making it possible to suppress the losses of the switching element. In the accompanying drawings: Fig. 1 is a circuit diagram of a first embodiment of the present invention; Figs. 2(a) to 2(d) are waveform charts for explaining the operation of the first embodiment; Figs. 3(a) to 3(d) are waveform charts for explaining the operations of the first and third embodiments; Fig. 4 is a circuit diagram of a second embodiment of the present invention; Fig. 5 is a circuit diagram of a third embodiment of the present invention; Fig. 6 is a circuit diagram of a fourth embodiment of the present invention; Figs. 7(a) and 7(b) are waveform charts for explaining the operation of the fourth embodiment; Fig. 8 is a circuit diagram of a prior art example; and Figs. 9 (a) to 9(g) are timing charts for explaining the operation of the prior art example. The present invention will hereinafter be described in connection with several embodiments. 1st Embodiment Fig. 1 illustrates a circuit diagram of a first embodiment. This embodiment is characterized by a resistor R 4 inserted between the gate of an FET Q 1 , which is a voltage driven switching element, and a feedback winding L 3 for suppressing a switching loss, and therefore differs from the exemplary circuit of the prior art of Fig. 8 in this respect. In Fig. 1, circuit elements, circuit voltages, and circuit currents identical to those in the exemplary circuit of the prior art are designated by the same reference letters and numerals. Next, the operation of this embodiment will be described with reference to Figs. 2(a) to 2(d) and 3(a) to 3(d). Figs. 3(a) to 3(d) are enlarged views of main portions in Figs. 2(a) to 2(d). Since the circuit of this embodiment operates basically in the same manner as the exemplary circuit of the prior art, a characteristic operation will only be described below. First, in this embodiment, by inserting the resistor R 4 between the gate of the FET Q 1 and the feedback winding L 3 , a delay occurs in a voltage V G (illustrated by broken lines in Figs. 2(d) and 3(c)) applied to the gate in comparison with a voltage V G ' (illustrated by solid lines in Figs. 2(d) and 3(c)) of the feedback winding L 3 due to the influence of an input capacitance existing at the gate of the FET Q 1 . Thus, a current I D before a drain voltage V D of the FET Q 1 illustrated in Fig. 2(b) or Fig. 3(b) reaches zero, stops flowing as illustrated in Fig. 2(c) (or as illustrated by a broken line in Fig. 3(d)), thereby making it possible to reduce the switching loss. A flat portion in the gate voltage V G , as illustrated in Fig. 3(c), is produced by the influence of a mirror effect. Fig. 2 (a) and Fig. 3 (a) illustrate a voltage V F at a connection point of an LC resonance circuit formed of the capacitor C 1 and the primary winding L 1 and a parallel circuit of the diode D 1 and the resistor D 1 . X in Fig. 2(d) indicates a threshold value for the gate of the FETQ 1 . 2nd Embodiment As shown in Fig. 4, this embodiment replaces the bias control circuit of the first embodiment formed of the resistor R 3 and the diode D 2 with a bias control circuit which is formed by connecting a series circuit of resistors R 5 , R 6 to the source of an FET Q 1 , connecting a series circuit of a diode D 5 and a transistor Q 2 in parallel with a circuit including a gate-to-source path of FET Q 1 and the resistors R 5 , R 6 , and connecting a connection point of the two resistors R 5 , R 6 to the base of the transistor Q 2 . Since the remaining configuration is the same as the first embodiment, the same circuit elements, circuit currents, and circuit voltages are designated by the same reference letters and numerals. Next, the operation of this embodiment will be described. Since the circuit of this embodiment operates basically in the same manner as the circuit of the first embodiment except for a circuit for controlling a bias, a characteristic operation only will be described below. In the circuit of this embodiment, when a voltage generated at the connection point of the resistors R 5 , R 6 is increased to a predetermined value by a current I D flowing through the FET Q 1 , the transistor Q 2 begins to operate to discharge charges on a bias capacitor C 2 through a circuit including the capacitor C 2 , feedback winding L 3 , resistor R 4 , diode D 5 , transistor Q 2 , and capacitor C 2 to control a bias voltage V G2 of the FET Q 1 . Here, circuit constants of the resistors R 5 , R 6 , and so on are set at values so as to balance the charging and discharging for the bias capacitor C 2 . The resistor R 4 serves to reduce a switching loss of the FET Q 1 as is the case of the first embodiment. 3rd Embodiment This embodiment differs from the circuit of the first embodiment in that a diode D 6 is connected in parallel with a resistor R 4 for reducing a switching loss, as illustrated in Fig. 5. Since the remaining configuration is the same as the first embodiment, the same circuit elements, circuit currents, and circuit voltages are designated by the same reference letters and numerals. While the circuit of the first embodiment eliminates the switching loss of the FET Q 1 when it turns on by adding the resistor R 4 , the switching loss is increased to the contrary, when the FET Q 1 turns off, because the gate voltage V G falls with a delay. To solve this problem, this embodiment has the diode D 6 connected in parallel with the resistor R 4 to suppress the delay of the gate voltage V G by a forward voltage of the diode D 6 when the FET Q 1 turns off, thereby making it possible to prevent the switching loss from increasing. The gate voltage V G of this embodiment is illustrated by V G " in Fig. 3(c), and a current I D is illustrated by a one-dot chain line in Fig. 3(d). 4th Embodiment This embodiment differs from the circuit of the second embodiment in that a capacitor C 3 is connected in parallel with a resistor R 6 , and a diode D 6 is connected in parallel with a resistor R 4 like the third embodiment, as illustrated in Fig. 6. Specifically, with the resistors R 5 , R 6 connected to the source of the FET Q 1 , a current flowing through the FET Q 1 reaches a predetermined value, and the transistor Q 2 for performing a bias control begins to operate. Thus, when the FET Q 1 turns off, the current is also reduced to cause a base voltage Vs of the transistor Q 2 to decrease, so that the threshold voltage of the FET Q 1 , viewed from the ground, also becomes reduced. In other words, since the threshold voltage lowers to prevent the FET Q 1 from turning off even if the gate voltage V G becomes reduced, the current I D gradually lowers as illustrated in Figs. 2, 3. This gradually lowering current I D causes the switching loss. In this embodiment, by adding the capacitor C 3 in parallel with the resistor R 6 , the base voltage Vs of the transistor Q 2 delays in time until charges on the capacitor C 3 are discharged. As a result, an apparent threshold voltage, viewed from the ground, does not lower, and the current I D vertically drops as illustrated by a solid line in Fig. 7(b), so that the switching loss can be prevented from occurring. Fig. 7(a) illustrates a voltage V F . While the respective foregoing embodiments employ the direct current power supply E, any voltage from a commercially available power supply may be rectified to produce a flat voltage usable in the present invention. In addition, similar effects can be produced when a voltage driven switching element such as IGBT is employed in place of FET. According to the present invention, a resistor is inserted between the gate of an FET and a feedback winding to produce a delay in a voltage applied to the gate of the FET in comparison with a voltage of the feedback winding due to the influence of an input capacitance existing at the gate of the FET. Thus, a current does not flow before a drain voltage of the FET reaches zero volt, thereby making it possible to reduce the switching loss.

Claims: A power supply circuit comprising: a power supply (E); a power transformer (T) connected on its secondary side (L2) to a circuit (D3, D4, B) which is to be fed by the power supply circuit; a voltage driven switching element (Q1) having a control terminal; an LC resonance circuit (L1, C1) connected in series to said switching element (Q1), wherein the inductive part of said LC resonance circuit is the first winding of said power transformer (T); a feedback winding (L3) for applying a feedback voltage according to a high frequency current of said LC resonance circuit (L1, C1) to said control terminal of said switching element (Q1); a bias circuit (R2, C2) connected in parallel to said series connection of said LC resonance circuit (L1, C1) and said switching element (Q1), and further connected to said feedback winding (L3) so as to apply a bias voltage to said control terminal via said feedback winding (L3); and a bias control circuit (R3, D2; R5, R6, Q2, D5) for controlling the bias voltage, and connected between said bias circuit (R2, C2) and said series connection of said LC resonance circuit ( L1, C1 ) and said switching element ( Q1 ), characterized by a resistor (R4) connected to said control terminal of said switching element ( Q1 ), wherein the bias voltage and the feedback voltage are applied to said control terminal of said switching element ( Q1 ) via said resistor ( R4 ); wherein said resistor (R4) is selected so as to delay the feedback voltage by a predetermined time. A power supply circuit according to claim 1, characterized by a diode (D6) connected in parallel with said resistor ( R4 ). A power supply circuit according to claim 1, characterized in that said bias control circuit comprises a transistor (Q2) which turns on to control the bias voltage when a current flowing through said switching element ( Q1 ) reaches a predetermined value; and a delay capacitor (C3) connected to a base of said transistor ( Q2 ) for delaying an off-operation of said transistor ( Q2 ).

Inventors: ABE HIDEAKI, TAMURA HIDEKI, ABE, HIDEAKI, TAMURA, HIDEKI
Applicants: MATSUSHITA ELECTRIC WORKS LTD, MATSUSHITA ELECTRIC WORKS, LTD.
Application year: 1997
Main classification: H02M3
IPC codes: H02M3, H02J7, H02M7