Photoelectric conversion apparatus

Abstract: In an amplification photoelectric conversion apparatus which amplifies charges generated in a photoelectric conversion area by inverting amplification and outputs the charges to an output line, two or more load MOS transistors having different sizes for setting the gain are arranged on each output line, and control is performed by applying a pulse to the gate of the load MOS transistor. In the photoelectric conversion apparatus, a pixel in the photoelectric conversion area is constituted only by a photodiode and a MOS transistor. The photoelectric conversion apparatus incorporates a memory cell constituted by a MOS transistor and a capacitor.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a photoelectric conversion apparatus capable of amplifying charges in a photoelectric conversion area of a sensor and changing the gain of the amplification. Related Background Art An inverting amplification CMOS sensor is one of amplification photoelectric conversion apparatuses for removing noise on chip. Such a photoelectric conversion apparatus is described in, e.g.; Japanese Laid Open Patent Publication No. JP-A-9200629 (Application No. 8-7329) and has an arrangement shown in Fig. 8. Referring to Fig. 8, a photodiode 1 as a photoelectric conversion device, an amplification MOS transistor 2 for performing inverting amplification, a selection switch MOS transistor 3, and a reset MOS transistor 4 constitute a photoelectric conversion sensor cell S. A storage MOS transistor 9, an amplification MOS transistor 10, a selection switch MOS transistor 11, and a reset MOS transistor 12 form a memory cell M. One unit of a transfer system circuit is constituted by a feedback MOS switch 18 for feeding back charges to the sensor cell S, a transfer switch 19 for sending charges to the transfer circuit, a transfer switch 20 for sending charges to the memory cell M, a feedback MOS switch 21 for feeding back charges to the memory cell M, a clamp MOS switch 22, a clamp capacitor 23, and an amplification MOS transistor 24 for a source follower, and this unit is arranged for each line. This apparatus also includes a horizontal transfer MOS switch 15, an output amplifier 16, and a reset MOS transistor 17. Transmission gates 5 and 6 control pulses SL1 and PS1, respectively. Transmission gates 13 and 14 control pulses SL2 and PS2, respectively. Fig. 9 is a drive timing chart of the photoelectric conversion apparatus. Line outputs V11 and V21 from vertical scanning circuits 1 and 2 are set at "H". At time T 0 , pulses RS, PS1, FT1, FT2, and PS2 are set at "H" to reset the sensor cell S, the memory cell M, and the transfer circuit. At time T 1 , pulses SL1 and LS are set at "H" to turn off a reset MOS transistor 7 and turn on the transmission gate 5, thereby inverting and amplifying the signal from the photodiode 1 as a sensor. The selection switch MOS transistor 3 is turned on to send the signal to the clamp capacitor 23 of the transfer circuit. Thereafter, the transfer pulse FT1 is set at "H" to turn off the transfer switch 19. The reset pulse RS is set at "H" to turn on the reset MOS transistor 17, thereby resetting the output line of the sensor cell S. At time T 2 , the pulses PS1 and FB1 are set at "H" to feed back the signal from the transfer circuit to the gate of the amplification MOS transistor 2 of the sensor cell S. At this time, the initial variation (noise) in the sensor cell S is removed due to the antiphase effect between the gain of the inverting amplifier 2 and that of the clamp circuit of the transfer circuit. In this case, letting G S be the inverting amplification gain, G T be the clamp circuit gain, and N init be the initial noise, noise N after the feedback operation is given by: N = N init (1 + G S × G T ) The inverting amplification gain that minimizes noise is given by G S = -1/G T . When the clamp gain is 0.98, the inverting amplification gain can be -1/0.98 = - 1.02. At time T 3 , the signal is sent from the sensor cell S to the transfer circuit again and clamped. At time T 4 , pulses FB2 and PS2 are set at "H" to write a voltage proportional to charges held by the clamp capacitor 23 in the memory cell M. The above operation is performed for all lines while performing vertical scanning, thereby completing the reset operation. After an arbitrary storage time, the signal is read out from the sensor cell S. At time T 5 , the pulse SL1 is set at "H" to invert and amplify the signal and read out the signal from the sensor cell S. At time T 6 , the pulse SL2 is set at "H" to read out an initial signal stored in the memory cell M and obtain a voltage difference from the sensor signal. At time T 7 , the voltage difference is written in the memory cell M. After that, the horizontal scanning circuit performs scanning and outputs the signal to the vertical output terminal through the amplifier 16. Finally, the noise N becomes: N = N init (1 + G M × G T ) When the inverting gain of the memory unit is G M = - 1/G T , the noise is minimized. The gain of the inverting amplifier 10 depends on the ratio of a conductance gm of the amplification MOS transistor 10 to a conductance gm' of the load MOS transistor 11. For this reason, when a gate length L or a gate width W of a load MOS transistor 8 is changed to change the conductance gm', the inverting amplification gain can be set to minimize the noise component. This applies not only to noise reduction by the load MOS transistor 8 of the memory cell M but also to noise reduction by the load MOS transistor 7 of the sensor cell S. However, in the above-described photoelectric conversion apparatus, small variations in well concentration, oxide film thickness, or processing size among lots, wafers, or chips may change the conductance gm of the MOS transistor, resulting in deviation of the inverting amplification gain from its optimum value. If the gain deviates from the optimum value, the noise correction effect degrades, and the output variation among cells, i.e., so-called FPN (Fixed Pattern Noise) increases. This may increase the ratio of defective chips having noise larger than the prescribed value to result in a low yield. The problem of suppressing increase in fixed pattern noise has been addressed and a solution has been found as will be detailed hereinafter. The photoelectric conversion apparatus considered herein is of the type such as disclosed, for example, by Japanese Laid Open Patent Publication No. JP-A-9200629 (Application No. 8-7329) already mentioned herein, comprising: a plurality of pixels, each including photoelectric conversion means and amplification means for amplifying charges generated in said photoelectric conversion means and outputting the amplified charges to an output line. This apparatus is, in accordance with the present invention, characterized by: a plurality of load means connected to the output line and provided to the amplification means, the plurality of load means having different characteristics respectively; and selection means for selecting any one of the plurality of load means, whereby the amplification means in any one of the pixels and the load means selected by the selection means function together as inversion amplification means for said one of said pixels. With the above arrangement, when the inverting amplification gain is set to be optimum by selecting a load means with an appropriate characteristic, a signal free from fixed pattern noise can be obtained. Alternatively, an appropriate gain can be set, so a high S/N ratio, high sensitivity, and a wide dynamic range can be obtained. Other features and advantages of the present invention will be apparent from the following specification and drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of the first embodiment of the present invention; Figs. 2A and 2B are views showing the output waveforms of a signal from a pixel of a sensor cell of the first embodiment; Figs. 3A and 3B are views showing the output waveforms of the signal from the pixel of the sensor cell of the first embodiment; Fig. 4 is a circuit diagram of the second embodiment of the present invention; Fig. 5 is a circuit diagram of the third embodiment of the present invention; Fig. 6 is a circuit diagram of the fourth embodiment of the present invention; Fig. 7 is a selection control chart of a load MOS transistor in the third or fourth embodiment of the present invention; Fig. 8 is a circuit diagram of a related art; and Fig. 9 is a drive timing chart of the related art. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 1 shows the first embodiment of the present invention. For the descriptive convenience, an area sensor consisting of 2 × 2 pixels is shown. Referring to Fig. 1, a photodiode 1 as a sensor device, an amplification MOS transistor 2 for performing inverting amplification, a selection switch MOS transistor 3, and a reset MOS transistor 4 make up a photoelectric conversion sensor cell S (to be referred to as a sensor cell S hereinafter). A storage MOS transistor 9, an amplification MOS transistor 10, a selection switch MOS transistor 11, and a reset MOS transistor 12 construct a memory cell M. One unit of a transfer system circuit, arranged in each column line is constituted by a feedback MOS switch 18 for feeding back charges to the sensor cell S, a transfer switch 19 for transferring charges to the transfer circuit, a transfer switch 20 for transferring charges to the memory cell M, a feedback MOS switch 21 for feedback to the memory cell M, a clamp MOS switch 22 for the transfer circuit, a clamp capacitor 23, and an amplification MOS transistor 24 for a source follower. The photoelectric conversion apparatus also includes a horizontal transfer MOS switch 15 for outputting a signal to an output line 34 when a scanning signal H11 from a horizontal scanning circuit 31 is at "H", an output amplifier 16 for amplifying the signal on the output line 34, and a reset MOS transistor 17 for resetting the residual signal on a sensor output line 37. Load MOS transistors 71, 72, and 73 for the amplification MOS transistor 2 of the sensor cell S as a photoelectric conversion cell change their conductances gm by changing gate lengths L and gate widths W. This embodiment is characterized in that several load MOS transistors are arranged. Similarly, a plurality of load MOS transistors 81, 82, and 83 having different conductances gm are arranged for the memory cell M. When the variation in conductance gm of a MOS transistor due to process variations is ±5%, the set value of the conductance gm of each MOS transistor is also preferably ±5%. Although load MOS transistors have been described above, the present invention is not limited to this, and any transistor capable of serving as a load resistor can be used. The operation and timing of the above photoelectric conversion apparatus are basically almost the same as the contents described above with reference to Fig. 8, and a difference will be described below in detail. Figs. 2A, 2B, 3A, and 3B show the output waveforms of each pixel in the sensor cell S or memory cell M. In Figs. 2A, 2B, 3A, and 3B, the abscissa represents each pixel, and the ordinate represents the output voltage of each pixel. FPN PP represents the peak-to-peak value of the output voltage of each pixel. In Figs. 2A, 2B, 3A, and 3B, adjustment pulses LS1, LS2, LS3, LM1, LM2, and LM3 are driven. Since the amplification MOS transistors 2 and 10 have different gains, the noise removal rates are also different, and this changes the magnitudes of noise. These data are obtained upon inspection using a tester or the like. Of the adjustment pulses LS1, LS2, LS3, LM1, LM2, and LM3, an adjustment pulse for minimizing the noise may be recorded and used in actual use. For example, for lot A shown in Fig. 2A, the adjustment pulse LS3 is used. For lot B shown in Fig. 2B, the adjustment pulse LS2 is used. For lot A shown in Fig. 3A, the adjustment pulse LM2 is used. For lot B shown in Fig. 3B, the adjustment pulse LM1 is used. The adjustment pulse can be changed not in units of lots but in units of wafers or chips, as a matter of course. As described above, when an adjustment pulse for minimizing noise is used, the yield in respect of FPN can be improved. In this embodiment, the three load MOS transistors 71 to 73 and three load MOS transistors 81 to 83 are arranged for the sensor cell S and the memory cell M, respectively. However, the number of load MOS transistors can be two or four or more, as a matter of course. In addition, PMOS transistors or NMOS transistors, or both of them can be used as far as they can serve as load MOS transistors for the amplification MOS transistors 2 and 10. Fig. 4 shows the second embodiment of the present invention. In this embodiment, one load MOS transistor is arranged for a sensor cell, as in the prior art, and several load MOS transistors are arranged for a memory cell. When the inverting gain of a memory cell M has an optimum value (= -1/G T ), noise in the sensor can be removed. Therefore, this embodiment can be applied to an application which requires only a memory output. The basic operation of the photoelectric conversion apparatus of this embodiment is the same as that shown in the timing chart of Fig. 9, and a difference will be described below. In this embodiment, the yield in respect of FPN can be improved without largely increasing the chip size and the number of drive pulses. The operation is the same as that described with reference to the circuit diagram of Fig. 8 and the contents described in the first embodiment. Adjustment pulses LM1 to LM3 are applied in the wafer or chip state to determine an adjustment pulse for minimizing FPN. When the photoelectric conversion apparatus is to be activated, the adjustment pulse is set at "L" to operate a specific load MOS transistor for the memory cell M. Fig. 5 shows the third embodiment of the present invention. An inverting amplification CMOS sensor of this embodiment removes noise using not a memory cell but signal and noise storage capacitors. In Fig. 5, the photoelectric conversion apparatus has a dark output potential storage capacitor C TN 40, a signal output storage capacitor C TS 41, a transfer MOS switch 42 for the dark output potential storage capacitor C TN , a transfer MOS switch 43 for the signal output storage capacitor C TS , transfer MOS switches 44 and 45 for outputting a signal to a signal line 47 and a noise line 48, respectively, and a differential amplifier 46 for subtracting the dark output from the signal. A photodiode 1, an amplification MOS transistor 2, a selection switch MOS transistor 3, and a reset MOS transistor 4 of a sensor cell S and load MOS transistors 71 to 73 of the sensor cell S are the same as those described in the second embodiment. The read timing of this embodiment will be described. An image signal from the sensor cell is stored in the signal output storage capacitor C TS 41. Next, the noise component of the sensor cell itself is stored in the dark output potential storage capacitor C TN 40. The transfer MOS switches 44 and 45 are turned on in accordance with a read scanning signal H11 from a horizontal scanning circuit 31 to read out the charges to the output lines 47 and 48, respectively. An image signal from which the noise component has been removed can be obtained as an output from the differential amplifier 46. In this embodiment as well, since several load MOS transistors are arranged, the gain can be changed. A load MOS transistor that minimizes FPN is determined in the wafer or chip state, and one of adjustment pulses LS1 to LS3 is applied to control the operation of the load MOS transistor in actual use. In this embodiment, when a signal and a dark output can be read out using the same inverting gain, noise can be removed by the differential amplifier at the final stage. For this reason, the condition for noise removal in a memory cell, i.e., inverting gain = - 1/G T need not be satisfied. The inverting gain may be set to be -1, -2, or -4. Conventionally, charges are amplified in an external circuit. In this case, the signal is vulnerable to noise and cannot attain a high S/N ratio. In this embodiment, however, charges can be amplified in the sensor cell S of the pixel unit, so the signal is robust against noise, and a high S/N ratio can be obtained. In this embodiment, a gain variable photoelectric conversion apparatus which reads out a signal by increasing the gain in case of low illuminance and by decreasing the gain in case of high illuminance can be obtained. As shown in Fig. 7, the light amount is detected by a sensor 101, and a pulse generation circuit 103 is controlled by a CPU 102, thereby selecting a load MOS transistor in a sensor chip 104. A pn junction sensor or a photoconductive sensor can be used as a sensor for detecting the light amount. In this embodiment, 2 × 2 pixels have been described. However, a signal can also be read out by a plurality of area sensors or a line sensor. In a line sensor, outputs V11 and V12 from a vertical scanning circuit 33 may always be set at "H"; the vertical scanning circuit 33 can be omitted. Fig. 6 shows the fourth embodiment of the present invention. In this embodiment, the circuit arrangement is the same as that of the third embodiment, and the pixel arrangement is changed. In this embodiment, a transfer gate 49 is arranged between a photodiode 1 and an amplification MOS transistor 2, and charges generated in the photodiode 1 are completely depleted and transferred to the gate of the amplification MOS transistor 2. The gate potential changes due to the charges which are completely depleted and transferred. This change in potential is inverted and amplified to read out the signal. The present invention is characterized in that the inverting amplification gain can be changed by load MOS transistors 71 to 73, so FPN can be minimized. According to this embodiment, a gain variable photoelectric conversion apparatus having a high S/N ratio and high sensitivity can be obtained. The functions and operations of remaining constituent elements are the same as those of the first to third embodiments. In the above embodiments, a plurality of load MOS transistors are arranged to change the gain. These load MOS transistors can be manufactured following the same patterning process as that for other MOS transistors. In addition, an increase in area for the manufacture does not largely affect the chip size because the dedicated area also has a MOS structure. As has been described above, according to the first or second embodiment, the inverting amplification gain is always set to be optimum. Since a signal free from noise can be obtained, the yield in terms of FPN is improved, and the cost can be reduced. According to the third or fourth embodiment, the gain is set in correspondence with the light amount, so a photoelectric conversion apparatus having a high S/N ratio, high sensitivity, and a wide dynamic range can be realized. Many widely different embodiments of the present invention may be constructed without departing from the scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.

Claims: A photoelectric conversion apparatus comprising: a plurality of pixels (S), each including photoelectric conversion means (1) and amplification means (2) for amplifying charges generated in said photoelectric conversion means and outputting the amplified charges to an output line (37), characterized by : a plurality of load means (71-73) connected to said output line (37) and provided to said amplification means, said plurality of load means having different characteristics respectively; and selection means (LS1, LS2, LS3) for selecting any one of said plurality of load means, whereby said amplification means in any one of said pixels and the load means selected by said selection means function together as inversion amplification means for said one of said pixels. An apparatus according to claim 1, wherein said photoelectric conversion means, said amplification means, and said load means are arranged on the same chip. An apparatus according to claim 1 which also includes: dark output storage means (40) for storing dark charges (C TN ) generated in said photoelectric conversion means and received via said output line; and signal output storage means (41) for storing signal charges (C TS ) generated in said photoelectric conversion means and received via said output line. An apparatus according to claim 3, wherein noise is removed by obtaining a difference between an output from said signal output storage means and an output from said dark output storage means. An apparatus according to any of claims 1 to 4, wherein each said load means (71-73) comprises a transistor. An apparatus according to claim 5, wherein said transistor comprises a MOS transistor. An apparatus according to claim 6, wherein said selection means selects one of said load means by applying a pulse to a gate of said MOS transistor. An apparatus according to any of claims 1 to 7, wherein one of said plurality of load means has as characteristic, one for minimizing noise of the output signal from said output line, when it is selected by said selection means and used. An apparatus according to any preceding claim, wherein each pixel comprises as photoelectric conversion means and as amplification means, respectively, a photodiode and a MOS transistor respectively. An apparatus according to any preceding claim, further comprising a plurality of memory cells (M) each including a MOS transistor (10) and a capacitor (9).

Inventors: TAKAHASHI HIDEKAZU, TAKAHASHI, HIDEKAZU
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1997
Main classification: H04N3
IPC codes: H04N5, H04N3, H01L31