INTER-BUS BRIDGE CIRCUIT

Abstract: The present invention provides for a bus bridge circuit (206) having a memory port (4) integrated therewith for upstream memory access independent of the activity on a primary bus (252) connected to the bridge circuit. In a preferred embodiment, the present invention adds a memory port (4) to a PCI bridge circuit (206) usable for upstream data transfers to an attached cache memory subsystem. The memory port (4) of the present invention is preferably 64 bits wide to permit high speed data access to the shared cache memory subsystem. An alternative embodiment of the present invention implements a 128 bit wide data path to an attached high speed cached memory subsystem. The memory port (4) of the present invention utilizes FIFO devices (310) to isolate the memory port transactions from the secondary bus transactions. This FIFO design of the memory port (4) allows bursting of high speed transfers to the shared memory, independent of activity on the primary bus (252), while minimizing the performance impact on a secondary bus (256).

Description: INTER-BUS BRIDGE CIRCUTT The present invention relates to a bus bridge circuit. The present application relates to the subject matter of International patent application PCT/GB97/01474 filed 30 May 1997 and entitled Cache Memory Controller and commonly assigned, co-pending, United States Patent Application serial number 08/357,847, filed December 16, 1994 by Steward et al., entitled (as amended) Disk Array Storage System Architecture for Parity Operations Simultaneous with other Data Operations, which corresponds to EP-A-0,717,357 and all of which are hereby incorporated by reference. Bridge circuits are known that connect a first electronic bus to a second electronic bus. The bridge circuit serves to adapt the signals of the two busses to enable data ejXchan e between the two bus signal standards. Frequently, bridge circuits are used to convert between different signalling standards defined for the first and second busses. Another common application of bus bridge circuits, and as discussed in the above mentioned application PCT/GB97/01474 hereby incorporated by reference, is to connect multiple, often hierarchical, busses to common devices or memory subsystems. In RAID storage subsystems control applications, for example, a Peripheral Computer Interconnect (PCI) bus is used to connect various peripheral I/O devices through a bridge circuit to a centralized PCI bus for the overall control of all I/O devices in the subsystems as well as the cache memory subsystem. It is common in the prior art that a bridge circuit is used to connect the various devices in the RAID subsystem both for purposes of I/O control and data exchange and for direct access to the cache memory subsystem. In such a centralized, hierarchical bus structure, the bus connected to the bridge circuit in common with other connections of other bridge circuits is referred to herein as the primary side or primary bus. The bus connected to the bridge circuit on the opposite side of the bridge relative to the primary side is referred to herein as the secondary side or secondary bus. Data flowing through the bridge circuit from the primary side to the secondary side is referred to herein as downstream data or downstream flow. Data flowing through the bridge circuit from the secondary side to the primary side is referred to herein as upstream data or upstream flow. It is a problem in such bridge circuit designs that if the secondary bus requires a transaction to be passed through the bridge circuit to access a shared resource on the primary bus, and the primary bus is unavailable due to other access unrelated to the shared resource, the request of the secondary bus is delayed until the primary bus is again available. For example, if a storage device connected to one of several secondary (PCI) busses is desirous of exchanging data with a centralized high speed cache memory subsystem connected to the primary bus, then the data exchange may be delayed if other data transfers are occupying the primary (PCI) bus, despite the potential availability of the centralized high speed cache memory subsystem. Typical hierarchical PCI bus systems within RAID subsystem controller designs exhibit the problems inherent in the prior art. When a secondary PCI bus requires access to the shared cache memory subsystem via the primary PCI bus, the cache memory access will be delayed while the primary PCI bus is in use for normal system control functions by the main processor of the RAID controller. Such delays in performing data exchange requests can disadvantageously affect the overall performance of the RAID storage subsystem in processing I/O requests. It is evident from the above discussion that a need exists for an improved bus bridge circuit design which reduces the potential for such delays in processing of I/O requests. The present invention seeks to provide for a bus bridge circuit having advantages over known circuits. Summary of the Invention According to one aspect of the present invention there is provided a bus bridge comprising, a primary bus port arranged for connecting said bus bridge to a primary I/O bus. a secondary bus port arranged for connecting said bus bridge to a secondary I/O bus and adapted for bi-directional exchange of data elements with said primary bus port, and a shared memory bus port arranged for connecting said bus bridge to a shared memory bus adapted for bi-directional exchange of data elements with said secondary bus port regardless of the state of said primary I/O bus. According to another aspect of the present invention there is provided a bus bridge comprising, primary PCI bus port means for connecting said bridge to a central processing unit through a primary PCI bus. secondary PCI bus port means for connecting said bridge to peripheral I/O devices through a secondary PCI bus, PCI bridge flow control means for controlling the bi-directional exchange of data elements between said secondary PCI bus port and said primary PCI bus port, shared memory port means for connecting said bridge to a shared memory device through a shared memory bus, and shared memory flow control means for controlling the bi-directional exchange of data elements between said secondary PCI bus port and said shared memory bus port independent of activity on said primary PCI bus. The invention also provides for a bus bridge circuit having a memory port integrated therewith for upstream memory access independent of the activity on a primary bus connected to the bridge circuit. In a preferred embodiment, the present invention adds a memory port to a PCI bridge circuit usable for upstream data transfers to an attached cache memory subsystem. The memory port of the present invention is preferably 64 bits wide to permit high speed data access to the shared cache memory subsystem. An alternative embodiment of the present invention implements a 128 bit wide data path to an attached high speed cached memory subsystem. The memory port of the present invention utilizes FIFO devices to isolate the memory port transactions from the secondary bus transactions. This FIFO design of the memory port allows bursting of high speed transfers to the shared memory, independent of activity on the primary bus, while minimizing the performance impact on a secondary bus. The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing an improved bridge circuit design which integrates a memory port usable by the secondary bus to access an attached memory subsystem regardless of the present availability of the primary bus and independent of any activity on the primary bus. Specifically, the present invention adds a memory port to a PCI bridge circuit usable for upstream data transfers to an attached cache memory subsystem. The memory port of the present invention is preferably 64 bits wide to permit high speed data access to the shared cache memory subsystem. An alternative embodiment of the present invention implements a 128 bit wide data path to an attached high speed cached memory subsystem. The memory port of the present invention utilizes FIFO devices to isolate the memory port transactions from the secondary bus transactions. This FIFO design allows bursting of high speed transfers to the shared memory while minimizing the performance impact on the secondary bus. The present invention advantageously provides a bus bridge circuit integrated with a memory port, and in particularly a bus bridge circuit with an integrated memory port for upstream access to a memory subsystem without requiring access to the primary bus of the bridge circuit. Further the present invention can provide for a memory port integrated with a PCI to PCI bus bridge circuit. In particular, the invention advantageously integrates a 64 bit memory port with a PCI to PCI bus bridge circuit for upstream access to a shared memory subsystem without requiring access to the primary PCI of the bridge circuit. Brief Description of the Drawings The invention is described further hereinafter, by way of example only, with reference to the accompanying drawings in which: Fig. 1 is a block diagram of a bridge circuit embodying the present invention and with a memory port integrated therewith; Fig. 2 is a block diagram of a RAID controller architecture in which a bridge circuit embodying the present invention may be advantageously applied; Fig. 3 is a block diagram providing additional details of the bus bridge circuit of Fig. 1 ; Fig. 4 is a block diagram of one embodiment of the shared memory bus connectable to the present invention as a 64-bit-wide parallel bus; and Fig. 5 is a block diagram of another embodiment of the shared memory bus connectable to the present invention as a 128-bit-wide parallel to byte serial bus. Detailed Description of the Preferred Embodiments Fig. 1 is a block diagram of a bus bridge circuit 206 having a memory port 4 in accordance with an embodiment of the present invention. PCI bus bridge circuit 206 includes PCI bridge flow control circuit 2 which directs the bi-directional exchange of data between secondary PCI bus 256 and primary PCI bus 252. For example, a CPU (not shown) connected to primary PCI bus 252 may access peripheral devices (not shown) connected to secondary PCI bus 256 and vice versa. However, regardless of the busy/idle status of primary PCI bus 252 due to other control operations by a CPU (not shown), devices on secondary PCI bus 256 may access a memory subsystem (not shown) connected to shared memory bus 250 via memory port 4. Fig. 2 is a block diagram describing the structure of a RAID storage subsystem 200 in which a bus bridge circuit embodying the present invention can be advantageously applied. CPU 122, L2 cache 124, CDC 126, RAM 128, and DPU 130 in RAID controller 200 of Fig. 2 are connected through processor bus 156. Other system I/O peripheral devices are connected to the primary PCI bus 252 via System I/O (SIO) 140 and bus 154. NVRAM 142, serial port 144, and debug/maintenance port 146 are used in development, debug, and maintenance of the RAID controller 200 and for persistent storage of configuration parameters. Cache DRAM controller (CDC 126) and data path unit (DPU 130) exemplify such standard chip sets known (together with system I/O (SIO 140)) as the "Saturn 11" chip set manufactured as part number 82420 by Intel Corporation. w i sh i ng to excπaπge data with hign speed cache buffer 214 Othe- components w.th i n RAID subsystem 200 requ.πng tne exchange of data WKΠ h,cn soeed cache buffer 214 througn shared memory bus 250 are connec t - tnereto tnrougn a bus bridge circuit Eacn bus bridge c i rcu i t 206 203 , and 210 adapts the s i gnals apphed to tner respective un i que, conne bus arcnnscture to the shared memory bus 250 Soec cally, bus bπdge αrcu i t 20δ adaots s.gnals on bus 25δ (e g , a 32-b,t or 64-bιt PCI bus) to aoproonat * s.gπe-s on snared memory bus 250 (and vce versa) for purposes of exchangmg cata betv / eεn an attached host computer 108, througn bus 120 and h,gn soe-d host i nterface 204, and tne h i gn speed cacne bufrer 21 A under tne control of mam memory controller 212 In like manner, bus bπdge circu i ts 208 and 210 adaot s.cnals on busses 258 and 260 resoecuvely, for aooHcafoπ to snared memory bus 250 (and v i ce versa) Bus bπdge circuits 208 and 210 thereoy prov.ee fcr the e cnaπge of formation between RAID array 104 (throuch d « v.c* i nterfaces 138 1 , 138 2) and h i gn soeed cache bufrer 214 under the control of ma memory controller 212 αa > .a exchange bandwidth Ma,n memory controller 212 also may pr0 v,de RA.D par i ty ss.s, lo g ,c (RPA) to prov i de centred high speed assistance for tne generator, and β - αng of RA.D redundancy mformation (parity) Tn.s feature of the present i nvent i on se.n,es to i solate tne RAID panty transfers from the ,nd,v,dua, .egacy bus structures Tn,s further ennances the distribution of the memory access toad HOT a plural i ty of legacy systems to a central.zad h,gh speed bus structure i nd i v i dual legacy busses are tnerefore ,ess like.y to be saturated by such Panty accesses Alternat i vely, the ma n memory controller 212 may be o,r=cted t a»o,v the dev i ce attacπed to a bus bridge αrcu.t to manage all redunoancy i π i ormation generation and cnecking Tne RAID panty ass i st c i rcuits wi.hiπ mam memory controller 212 operate on data stored ,n a .ocal memory (no. shown, associated therew i tn ,, calculates P-. y a burst at a t,me utn.z i ng an interna, 128 byte F.FO (no, snown) to store Prance tne contro! log.c for tne panty ass.st eno.ne ma i nta.ns po i nter, to «n needed data block Tne RAID parity assist operates at tne lull soeeo of th* local memory bus 254 to provide the fø '- * ' „„ « „. μ uvι « -.. ;πe τas l= s, possiDle performance for th° memory banαwidth Tne parity assist engine contains , separate sections that allow additional tas K s to be ςueued up while one task executes. Each task maintains its own control and status register so that task scheduling does no. interfere with , he current.y executing task. Several configuration options are provided to taNor the RPA to the array organization. The engine can be configured as a single engine w i cn works on wide arrays up to 22+1 rives in.. „ απves wιde . or as a four engine machine wh i ch operates with arrays as wide as 4+1 dri es Δ , H * τ ι cπves. Another mode provides a two eng i ne machine with up to 10+1 drives. The parity engine includes exclusive-OR logic providing RAID 5 and RAID 3 par i ty generation/checking as well as move and zero check modes. One of the most important parts of the RPA architecture is the time i ndependent operation it provides. Blocks of data are not required to be accessed simultaneously for parity calculations. Disk operations which span several drives may be scheduled and executed as soon as possible by each dev i ce. Unrelated disk operations may continue even thouoh all drive operations for a single task are not yet complete. This independence improves tne performance of the slowest pan of the system, the disk drive it also s.mplmes the software task of managing concurrent hardware resource requirements. Further details regarding the structure and operation of RPA circuits wi th in ma in memory controller 212 are contained in the co-pending applications identified above. CPU 122 is connected to primary PCI bus 252 throuch processor bus 156 nd CDC 125 with DPU 130. This connection gives CPU 122 access to the h i erarchical cache memory architecture of the present invention to permit methods operable within CPU 122 to control the operations of the bus bridαe c i rcu i ts 205, 208, and 210, and of the main memory controller 212. This aspect °' tne present invention enables methods operable within processor 122 to access an individual one of busses (e.g., 25δ, 258, and 260) without imoactinα cont i nued high speed data access and processing by the other busses The higher bandwidth capacity of tna cacne memofy arcnitecture of present invention permits the RAID controller 201 to be scaled up , or higher perrormance while minimizing the needs for redesign of older legacy control systems within the RAID controller 201. For example, host interface 204 may' be easily scaled up to Fibre Channel host system connections. The higher data bandwidth availabie in the cache memo^ architecture of the present invention provdes sufficient bandwidth therefor while permitting easier re-use of legacy control systems in the controller. Likewise, device interfaces 138.1 and 138 2 may be scaled up to higher performance disk drive control architectures (e g l ast SCSI, wide SCSI, SCSI 3, Fibre Channel (FCAL), etc.). The data bandwidth ava i lable in the cache architecture of the present invention enables the use of such h,gh performance connections while minimizing the re-design necessary for legacy control structures. FIG. 3 is a block diagram providing additional details of the structure of bπdge circuit 206 having a memory port 4 integrated therein in accordance with tne present invention. PCI bridge flow control circuit 2 includes data paths normally contained within a standard PCI bridge circuit . Data transfers therethrough may include upstream transfers from the secondary bus 255 to the Primary PCI bus 252 as well as downstream transfers from the primary PCI bus 252 to the secondary bus 256. Upstream data transfers are controlled by upstream flow control circuit 306 and downstream transfers are controlled by downstream flow control circuit 308, both within PCI bridge flow control circuit 2 Data transfers are clocked at the PCI bus speed, preferably 33 megane z. Primary PCI bus 252 and secondary PCI bus 256 may be either 32 cr 64 bit wide PCI busses. Upstream and downstream flow control circuits 306 an 308 manage any conversions required to transfer between a 32 bit wide bus and a 64 bit wide bus. Configuration control circuit 302 in bridge circuit 206 contains registers and related logic which oversee and coordinate the functions of the bridge "circuit /00789 10 1. The configuration blocks and values are as defined by industry standard PCI bus design specifications. The PC! bus standards allow for addition of custom application specific control and configuration values. The present invention therefore includes configuration register values within configuration control circuit 302 to control the operation of memory port 4 of bridge circuit 1. In particular, control and configuration registers are used to define a 64 bit address range used for transfer to and from the memory port 4. Accesses addressed to the range from the secondary PCI bus 256 are re-routed to the memory port 4 rather than the upstream flow control circuit 306. As noted above, the shared memory bus 250 is a high speed, 64 bit wide, bus to which a plurality of bus bridge circuits 206 may be connected for shared access to a high speed shared cache memory subsystem. The shared memory bus is preferably operable at 66 megahertz. Memory port 4 includes FIFO devices 310 to enable speed matching for high speed burst access to the shared memory bus 250. The FIFO devices 310 serve to isolate the slower secondary PCI bus 256 from the high speed shared memory bus 250. This architecture prevents the slower secondary PCI bus 256 from pacing the data transfers on the shared memory bus 250. As noted above, in an alternative embodiment the shared memory bus may be implemented as a 128 bit wide bus using parallel to serial transceivers. A plurality of FIFO devices may be used to implement a particular bus width for a particular embodiment of the shared memory bus 250 and memory port 4. Shared memory control circuit 304 uses register values defined within configuration control circuit 302 to establish threshold values for the filling and emptying of the FIFO devices 310. The threshold values are used to pace the data transfer operations between the secondary PCI bus 255 and the shared memory bus 250. Data transfers are stored in the FIFO devices 310 until the intended receiver empties the data from the FIFO devices. This permits both busses (secondary PCI bus 256 and shared memory bus 250) to operate independently at their optimal speed for bursts of data. There are three threshold values useful in ,,ow control of the presen, i nvention. A first threshold value is the ir= n =<=, ■ τ ,_ , S ,rans, sr ,n P^Sress (TIP) threshold The TIP value represents the minimum number o, bytes the, must be presen. in ,hl FIFO devices 310 before the shared memo, bus 2S0 is revested for ct wπ,„g ,ha data from the F,FO devices 3,0 to the shared cache memory I second threshold value is the shared memory write (SMW) transfer l™ , threshold. The SMW threshold value determines the „ ., t uecermmes the maximum number of bytes hat m ay be transferred to the shared memory bus 250 from the F,FO devices 310 followng mitial acquisition of shared memory bus 250 based upon the TIP threshold value discussed above. If the SMW value is smaller than the selected TIP value, then the TIP value is reset to the SMW value to prevent a deadlock in request i ng the shared memory bus 250. Finally, a third threshold value is the shared memory read (SMR) transfer limit threshold. The SMR threshold value determ i nes the maximum number of bytes that may be transferred from the shared memory bus 250 to the FIFO devices 310 following initial request of the read from the secondary PC. bus 255. One of ordinary skill in the art will readily recognize that the threshold values may be expressed in byte sized units or any other un i t of measure convenient to the particular application design For example, the threshold values may be in units of queued words where a oueu-d worα i s the combined width of the FIFO devices 310 as noted below. The number of FIFO devices 310 may reflect the relative ratio of the bus w i dths of the secondary PCI bus 256 and the shared memory bus 250 As noted above, the secondary PCI bus 256 is preferably 32 or 64 bits wide while the shared memory bus 250 is preferably 64 or 128 bits wide If, for example the shared memory bus 250 is twice the width of the secondary PCI bus (e o 32 bit w i de PCI bus and 64 bit shared memory bus), two FIFO devices 310 are used eacn matching tne width of the narrower secondary PCI bus 256 Transfers rrom/to the secondary PCI bus 256 to the shared memory bus 250 then fill/empty tne two FIFO devices 310 in alternation. Clearly, if the secondary PCI bus 255 =πd tne shared memory bus 250 are of equal widths, there need b * no subdivisions of the FIFO device 310 to adapt the relative width of the busses. Other design considerations may also impact the selection of the number of FIFOs. For example, certain sizes and geometries of FIFO devices may be unavailable in the desired depths or the desired speeds. Such design choices are well known and easily resolved by those of ordinary skill in the art. In particular on write data transfers, data flows from the 32 bit wide secondary PCI bus 256 into two FIFO devices 310 of memory port 4 in alternation. In read data transfers, data is loaded from the wider 64 bit shared memory bus 250 directly into the two FIFO devices 310. The data is then read in alternation from the two FIFO devices 310 and applied to the secondary PCI bus 256. As noted above, the best presently known mode of implementing the shared memory bus of the present invention is as a 64-data-bit-wide parallel bus clocked at 66 megahertz. FIG. 4 is a block diagram depicting this best presently known structure for shared memory bus 250 of FIG. 2. Shared memory bus 250 of FIG. 4 is connected to FIFO 310 of shared memory flow 4 (of FIG. 3) of bus bridge circuits 206, 208, or 210 of FIG. 2. FIG. 5 is a block diagram of an alternative embodiment of the shared memory bus 250 of the present invention in which eight, high speed, 16-bit-wide parallel to bit serial transceivers 500 are integrated into shared memory flow 4 connected to FIFO 310. This structure provides a 128-bit-wide internal bus structure connected to FIFO 310 but an 8-bit-wide (byte) serial interface as applied to shared memory bus 250. A similar byte serial, 128-bit wide bus structure is implemented in ail devices connected to the shared memory bus 250. This alternate embodiment of the present invention serves to reduce the external pin count required for interconnect of bus bridge circuits 205, 203, and 210 and main memory controller circuit 212 via shared memory bus 250. The transceivers 500 are capable of data transfer speeds of at least 1 gigabit per second each to thereby provide bandwidth of 1 gigabyte per second over shared memory bus 250. While the invention has been illustrated and described in detail i π the drawings and foregoing description, such illustration and description is to be considered as exemplary and not restrictive in character, it being understood that only the preferred embodiment and minor variants thereof have been shown an d d escribed and that the invention is not restric t e d to the d e t a i ls of the foregoing embodimen t s.

Claims: CLAIMS 1. A bus bridge (206) comprising: a primary bus port arranged for connecting said bus bridge (206) to a primary I/O bus (252); a secondary bus port arranged for connecting said bus bridge (206) to a secondary I/O bus (256) and adapted for bi-directional exchange of data elements with said primary bus port; and a shared memory bus port arranged for connecting said bus bridge (206) to a shared memory bus (250) adapted for bi-directional exchange of data elements with said secondary bus port regardless of the state of said primary I/O bus (252). 2. A bus bridge as claimed in Claim 1 , wherein said primary I/O bus (252) comprises a PCI compliant bus. 3. A bus bridge as claimed in Claim 1 or 2, wherein said secondary I/O bus (256) comprises a PCI compliant bus. 4. A bus bridge as claimed in Claim 1, 2 or 3, wherein said shared memory port (4) further comprises: a FIFO (310) for storing data elements exchanged between said secondary bus port and said shared memory bus port (4); and a shared memory control device for controlling the exchange of data elements between said FIFO (310) and said shared memory bus (250). 5. A bus bridge as claimed in Claim 4, wherein said shared memory port (4) has a data path at least 64-bits wide and said secondary bus port has a 32-bit wide data path, wherein data elements exchanged between said secondary bus port and said shared memory port (4) comprise an alternating sequence of evenly numbered data elements and odd numbered data elements, and wherein said FIFO (310) includes: a first FIFO element for the exchange of evenly numbered data elements between said secondary bus port and said shared memory port (4); and a second FIFO element for the exchange odd numbered data elements between said secondary bus port and said shared memory port (4). 6. A bus bridge as claimed in Claim 4, wherein said shared memory port (4) has a data path width which is an integral multiple of a data path width of said secondary bus port and wherein said FIFO (310) includes: a plurality of FIFO elements where the number of said plurality of FIFO elements is equal the ratio of the said data path width of said shared memory port (4) over said data path width of said secondary bus port. 7. A bus bridge as claimed in Claim 4, 5 or 6, wherein said shared memory control device includes: a TIP threshold value indicative of the minimum number of data elements present in said FIFO (310) before a request is generated for control of said shared memory bus (250) through said shared memory port (4). 8. A bus bridge as claimed in Claim 7, wherein said shared memory control device further includes: an SMW threshold value indicative of the maximum number of data elements to be written from said FIFO (310) to said shared memory bus (250) before relinquishing control of said shared memory bus (250) through said shared memory port (4). 9. A bus bridge as claimed in any one of Claims 4 to 8, wherein said shared memory control device includes: an SMR threshold value indicative of the maximum number of data elements to be read from said shared memory bus (250) into said FIFO (310) following initial request of a read operation from said secondary bus port. 10. A bus bridge as claimed in any one of claims 4 to 9, wherein said shared memory control device includes: a base address parameter value indicative of the base starting address of said shared memory port (4); and a size parameter value indicative of the size of said shared memory port (4). 1 1. A bus bridge comprising: primary PCI bus port means for connecting said bridge to a central processing unit through a primary PCI bus (252); secondary PCI bus port means for connecting said bridge to peripheral I/O devices through a secondary PCI bus (256); PCI bridge flow control means (2) for controlling the bi-directional exchange of data elements between said secondary PCI bus port and said primary PCI bus port; shared memory port means (4) for connecting said bridge to a shared memory device through a shared memory bus (250); and shared memory flow control means for controlling the bi-directional exchange of data elements between said secondary PCI bus port and said shared memory bus port (4) independent of activity on said primary PCI bus (252). 12. A bus bridge as claimed in Claim 1 1 , wherein said shared memory control means includes: FIFO means (310) for storing data elements exchanged between said secondary PCI bus port means and said shared memory port means (4). 13. A bus bridge as claimed in Claim 12, wherein said shared memory port means (4) has a data path at least 64-bits wide and said secondary PCI bus port means has a 32-bit wide data path, wherein data elements exchanged between said secondary PCI bus port means and said shared memory port means (4) comprise an alternating sequence of evenly numbered data elements and odd numbered data elements, and wherein said FIFO means (310) includes: a first FIFO element to store evenly numbered data elements exchanged between said secondary PCI bus port means and said shared memory port means (4); and a second FIFO element to store odd numbered data elements exchanged between said secondary PCI bus port means and said shared memory port means (4). 14. A bus bridge as claimed in Claim 12, wherein said shared memory port means (4) has a data path width which is an integral multiple of a data path width of said secondary PCI bus port means and wherein said FIFO (310) means includes: a plurality of FIFO elements where the number of said plurality of FIFO elements is equal the ratio of the said data path width of said shared memory port means (4) over said data path width of said secondary PCI bus port means. 15. A bus bridge as claimed in Claim 12, 13 or 14, wherein said shared memory control means includes: a TIP threshold value indicative of the minimum number of data elements present in said FIFO means (310) before a request is generated for control of said shared memory bus (250) through said shared memory port means (4). 16. A bus bridge as claimed in Claim 15, wherein said shared memory control means further includes: an SMW threshold value indicative of the maximum number of data elements to be written from said FIFO means (310) to said shared memory bus (250) before relinquishing control of said shared memory bus (250) tlirough said shared memory port means (4). 17. A bus bridge as claimed in any one of Claims 12 to 16, wherein said memory control device includes: an SMR threshold value indicative of the maximum number of data elements to be read from said shared memory bus (250) into said FIFO means (310) following initial request of a read operation from said secondary bus port means. 18. A bus bridge as claimed in any one of Claims 12 to 17, wherein said shared memory control device includes: a base address parameter value indicative of the base starting address of said shared memory port (4); and a size parameter value indicative of the size of said shared memory port (4).

Inventors: CORRIGAN BRIAN E III, RYMPH ALAN D, CORRIGAN, BRIAN, E., III, RYMPH, ALAN, D.
Applicants: GILL DAVID ALAN, SYMBIOS LOGIC INC, GILL, DAVID, ALAN, SYMBIOS LOGIC INC.
Application year: 1997
Main classification: G06F13
IPC codes: G06F12, G06F13