SYSTEM AND METHOD FOR CONTROLLING AN ACTIVE MATRIX DISPLAY

Abstract: A smart controller chip for controlling an active matrix display. Within the controller chip, circuitry for generating analog reference levels is incorporated alongside circuitry for generating digital timing and control signals. The combination of D/A analog circuitry and standard digital logic makes the controller uniquely suited for addressing all the panel control needs both for the normal digital functions but also for control of the analog aspects of the panel, like display gamma. The analog reference levels and the digital signals are made programmable using registers internal to the controller chip. The contents of these registers are programmed initially by digital values stored in an external PROM or in flash memory integrated into the controller chip. In addition, software in a host system is able to program these registers via an interface between the host system and the controller chip.

Description: SYSTEM AND METHOD FOR CONTROLLING AN ACTIVE MATRIX DISPLAY I. BACKGROUND OF THE INVENTION 5 1. Technical Field This invention relates to active matrix display controllers. An active matrix display controller is typically an application specific integrated circuit (ASIC) and is one of the support chips accompanying an active matrix flat panel display. The controller takes display data from the host system and provides it, along with control and timing signals, to the column and row l o drivers of the display panel. 2. Description of Related Art With recent progress in various aspects of active matrix display technology, the proliferation of active matrix displays has been spectacular in the past several years. In an active matrix display, there is one transistor or switch corresponding to each display cell. An 15 active matrix display is operated by first applying select voltages to a row electrode to activate the gates of that row of cells, and second applying appropriate analog data voltages to the column electrodes to charge each cell in the selected row to a desired voltage level. To date the controller chips (integrated circuits) used in active matrix displays have been purely digital. However, controlling an active matrix display also requires analog circuitry. 20 Specifically, the column drivers on the periphery of the display panel which supply the analog data voltages to the column electrodes typically need analog reference levels to do digital-to-analog conversion, and these analog reference levels may need to be changed to invert the polarity across the liquid crystal of the display. Because of the large size, power consumption, and heat generation of the analog circuitry, the analog circuitry is not incorporated in the purely digital 25 controller chips of the prior art and must be handled with external circuitry. The presence of external circuitry increases the complexity of manufacturing and assembling the active matrix display system. In addition, the controller chips to date are very specific to a particular system. The controller chips are typically designed for an active matrix display of a certain resolution and for 30 peripheral drivers of certain manufacturers. The specificity of the design of the controller chips leads to problems and inefficiencies. For example, if a flat panel display manufacturer decides to switch to a different type of column driver, the controller ASIC (application specific integrated circuit) must usually be redesigned. Furthermore, controller chips to date are rather limited in their ability to dynamically modify operating characteristics of a display. One such characteristic is the display gamma. The display gamma is the functional relationship defined by the amount of light emitted by the display cell, or pixel, as a function of the voltage used to produce it. In an active matrix display this voltage is the analog output of the column drivers. The gamma formula is Light out = voltage g . Typically display software assumes a linear gamma, that is the amount of light emitted is proportional to the voltage. However both CRTs and active matrix displays have inherent non-linearity in the light response to the voltage. In an active matrix display, the nonlinear gamma is corrected by the analog reference levels sent to the column drivers. If the ability to modify the display gamma exists, it is typically implemented with a color look-up table (CLUT) method which is rigid and inefficient. In a system using a CLUT, the digital value that will define the desired analog voltage, is actually used as an index to the CLUT. At each indexed location in the CLUT there is stored a new digital value. It is this value that, when converted to an analog voltage, gives the desired display gamma. Using color look-up tables to achieve non-linear display gammas results in a large number of digital values that correspond to the same transmission value. This is a large price to pay in flat panel displays where the digital values are typically limited to 6 bits (i.e. 64 levels). A more flexible and efficient method for modifying the display gamma is needed so that dynamic adjustments may be made in order to suit the display requirements of particular applications or to compensate for temperature changes which alter the transmission behavior of the display panel. For the foregoing reasons, there is a need for a flat panel display controller that combines digital and analog circuitry to reduce the complexity of manufacturing and assembling the display system, that is flexible enough to apply to different systems without being redesigned, and that can dynamically modify operating characteristics of the display to suit particular applications and compensate for temperature changes which alter display panel transmission behavior. II. SUMMARY The present invention relates to a system and method for controlling an active matrix display that satisfies the above described needs. The system and method includes the use of a "smart" controller chip. Analog circuitry for generating analog reference levels is incorporated alongside the digital circuitry within the smart controller chip. The combination of D/A analog circuitry and standard digital logic makes the controller uniquely suited for addressing all the panel control needs both for the normal digital functions but also for control of the analog aspects of the panel, like display gamma. Putting this .analog control circuitry directly in a programmable control ASIC enables the analog functions of the panel to be controlled by software. Furthermore the elimination of the external reference circuitry reduces the complexity of manufacturing and assembling the display system. In addition, the smart controller chip includes internal programmable registers that may contain digital values that correspond to analog reference levels. The contents of these registers may be programmed initially by digital values stored in an external PROM. This design enables the smart controller chip to be flexible enough to apply to different systems without being redesigned. Instead of having to redesign a controller ASIC for each specific display system, the same smart controller chip is used in conjunction with an appropriate PROM whose programming matches the specific display system. Alternatively, these registers may be programmed initially by digital values stored in flash memory integrated into the smart controller chip. Software in the host system is also able to program the internal registers of the smart controller chip via an interface between the host system and the smart controller chip. By programming these registers with digital values which correspond to analog reference levels, the system software is able to dynamically modify operating characteristics of the display, such as the display gamma curve. Thus, dynamic adjustments may be made to suit particular applications being run on the host or to compensate for changes in the environment of the display panel. This method of controlling the display gamma has substantial advantages over controlling the display gamma by the CLUT method. Whereas in the CLUT method a large number of digital values typically correspond to the same transmission value, in this method each of the digital values corresponds to a unique transmission value. Ill . BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a conventional control system for an active matrix display. Figure 2 is a block diagram of a first display control system including a smart controller outputting relatively high-power analog reference levels in a first and preferred embodiment of the present invention. Figure 3 A is a block diagram of a second display control system including a smart controller outputting relatively low-power analog reference levels and buffers external to the smart controller in a second and alternate embodiment of the present invention. Figure 3B is a block diagram of a third display control system including a smart controller outputting relatively low-power analog reference levels and column drivers capable of utilizing the relatively low-power analog reference levels in a third and alternate embodiment of the present invention. Figure 4A is a block diagram of a first smart controller chip in a first and preferred embodiment of the present invention. Figure 4B is a block diagram of a second smart controller chip in a second and alternate embodiment of the present invention. Figure 5 is a schematic diagram of the inputs and outputs of a conventional column driver. Figure 6 is a graph of a transfer curve of a liquid crystal. Figure 7A is a block diagram including registers, multiplexers, and analog output circuitry within a smart controller in a first and preferred embodiment of the present invention. Figure 7B is a block diagram including registers, multiplexers, and analog output circuitry within a smart controller in a second and alternate embodiment of the present invention. Figure 8A is a graph of a linear display gamma. Figure 8B is a graph of a first non-linear display gamma. Figure 8C is a graph of a second non-linear display gamma. IV. DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention are now described with reference to the figures. Figure 1 is a block diagram of a conventional control system 100 for an active matrix display including a conventional controller chip 102. Display data and synchronization (sync) signals are input to the controller 102 via lines 104 from a host system 105 which is typically a computer system. The controller 102 sends the column control signals via lines 106 and display data via lines 107 to column drivers 108 which are connected via lines 109 to the column electrodes of an active matrix display 1 10. The controller 102 also sends row control signals via lines 1 12 to row drivers 114 which are connected via lines 1 15 to the row electrodes of the active matrix display 1 10. External to the controller 102, there is reference circuitry 1 16 which receives reference control signals via lines 118 from the controller 102 and sends analog reference levels via lines 120 to the column drivers 108. When the column drivers 108 are low- voltage column drivers, then the reference circuitry 116 may also switch the analog reference levels between two fixed voltage levels in order to invert the polarity of the liquid crystal in the display 110. The liquid crystal (LC) material requires that the voltage applied across it switch in polarity over time, otherwise there will be image quality problems with the liquid crystal material. This is called LC inversion. The LC material is sandwiched between two plates of a capacitor. One plate is connected by a matrix switch to the outputs of the column drivers. The other plate is common between all the capacitors of the matrix. This common potential is typically called VCOM. High voltage column drivers have sufficient voltage range on their outputs that they can switch the polarity of the liquid crystal from voltages positive with reference to VCOM to voltages that are negative referenced to VCOM. These high voltage drives also have enough analog reference levels that both the positive and negative voltage levels are input to the column driver. Therefore the column driver itself can handle all the aspects of the LC inversion. When low voltage column drivers are used, the polarity across the LC material can only be switched if the VCOM potential is also switched. In this case, the column driver only takes one set of reference levels on its input. To drive a positive polarity, VCOM is switched to a lower voltage than the column outputs and the positive reference levels must be input to the column driver. To drive negative polarity VCOM must be switched higher than the column outputs and negative reference levels must be input to the column driver. Figure 2 is a block diagram of a first and preferred display control system 200. The first display control system 200 includes a first "smart" controller chip 202, a first serial bus 204, a programmable read-only memory (PROM) chip 206, and a second serial bus 208. Display data and sync signals are input to the first smart controller 202 via lines 104 from a host system 105 which may be a computer system or another machine such as a television or video system. The first smart controller 202 sends the column control signals via lines 106 and display data via lines 107 to the column drivers 108 which are connected via lines 109 to the column electrodes of the display 1 10. The display 1 10 may be an active matrix display or another similarly driven display. The first smart controller 202 also sends row control signals via lines 1 12 to row drivers 1 14 which are connected via lines 1 15 to the row electrodes of the display 1 10. The first smart controller 202 in this system 200 drives relatively high-power programmable analog reference levels via lines 120 to the column drivers 108 without using the external reference circuitry 116 which is required in the conventional system 100. The elimination of the external reference circuitry 116 reduces the complexity of manufacturing and assembling the active matrix display system. In addition, the relatively high-power analog reference levels and the column and row control signals which are output by the first smart controller 202 are programmed initially via the first serial bus 204 by the external PROM 206. A typical industry standard serial bus and protocol which may be used for first serial bus 204 is the I-^C bus. The programmability of the outputs of the first smart controller 202 by the external PROM 206 gives the first smart controller 202 the flexibility to work in different display systems without being redesigned for the characteristics of each specific one. Furthermore, the second serial bus 208 is used to communicate information between the first smart controller 202 and the host system 105. Using this communication channel, software in the host system 105 is able to dynamically modify the analog reference levels .and the column and row control signals output by the first smart controller 202. Note that the first and the second serial buses (204 and 208) need not be separate buses and can instead be the same bus. The ability of the first smart controller 202 to dynamically modify its outputs enables it to adjust operating characteristics of the display to suit particular applications and compensate for environmental changes. Figure 3 A is a block diagram of a second and alternate display control system 300. The second display control system 300 includes a second smart controller chip 302 and drive buffers 306. Like in the first display control system 200, display data and sync signals are input via lines 104 to the second smart controller 302 from the host system 105 which may be a computer system or another machine such as a television or video system. The second smart controller 302 sends column control signals via lines 106 and display data via lines 107 to the column drivers 108 which are connected via lines 109 to the column electrodes of the display 1 10. The display 1 10 may be an active matrix display or another similarly driven display. The smart controller 302 also sends row control signals on lines 1 12 to row drivers 1 14 which are connected via lines 1 15 to the row electrodes of the display 1 10. Also like in the first display control system 200, the column and row control signals which are output by the second smart controller 302 are programmed initially via the first serial bus 204 by the PROM 206 which is external to the second smart controller 302. A typical industry standard serial bus and protocol which may be used for the first serial bus 204 is the I-^C bus. Alternatively, the initial programming may be supplied by flash memory 303 integrated into the second smart controller 302 (in which case the external PROM 206 would not be necessary). Further like in the first display control system 200, the second serial bus 208 is used to communicate information between the second smart controller 302 and the host system 105. Using this communication channel, software in the host system 105 is able to dynamically modify the column and row control signals output by the smart controller 302. Note again that the first and the second serial buses (204 and 208) need not be separate buses and can instead be the same bus. Unlike in the first display control system 200, the external drive buffers 306 are required in the second display control system 300 to drive relatively high-power analog reference levels on lines 120 to the column drivers 108. The second smart controller 302 outputs relatively low- power analog reference levels via lines 304 to the external drive buffers 306. The external drive buffers 306 receive the low-power analog reference levels and drive the high-power analog reference levels on lines 120 to the column drivers 108. Like the first display control system 200, the second display control system 300 has lower cost and complexity than the conventional display system 100 and outputs analog reference levels that are programmable by the controller 302 or the host system 105. An advantage of the second display control system 300 over the first display control system 200 is that the external buffers 306 may be readily changed in order to match their drive capability to the drive requirements of the particular column drivers 108 used. Figure 3B is a block diagram of a third and alternate display control system 350. The third display control system 350 includes the second smart controller chip 302 and column drivers 354 that require only relatively low-power analog reference levels. As in the second display control system 300, display data and sync signals are input via lines 104 to the second smart controller 302 from the host system 105 which may be a computer system or another machine such as a television or video system. The second smart controller 302 sends column control signals via lines 106 and display data via lines 107 to the column drivers 108 which are connected via lines 109 to the column electrodes of the display 1 10. The display 1 10 may be an active matrix display or another similarly driven display. The smart controller 302 also sends row control signals on lines 1 12 to row drivers 1 14 which are connected via lines 115 to the row electrodes of the display 1 10. Also as in the second display control system 300, the column and row control signals which are output by the second smart controller 302 are programmed initially via the first serial bus 204 by the PROM 206 which is external to the second smart controller 302. A typical industry standard serial bus and protocol which may be used for the first serial bus 204 is the I^C bus. Alternatively, these registers may be programmed initially by flash memory 303 integrated into the smart controller chip (in which case the PROM 206 would not be necessary). Further as in the second display control system 300, the second serial bus 208 is used to communicate information between the second smart controller 302 and the host system 105. Using this communication channel, software in the host system 105 is able to dynamically modify the column and row control signals output by the smart controller 302. Note again that the first and the second serial buses (204 and 208) need not be separate buses and can instead be the same bus. Unlike in the second display control system 300, the external drive buffers 306 are not required to drive relatively high-power analog reference levels on lines 120 to the column drivers 108. Instead, the second smart controller 302 outputs relatively low-power analog reference levels directly via lines 120 to the column drivers 354 which are capable of utilizing the low-power analog reference levels. Figure 4A is a block diagram showing a more detailed view of the first smart controller 202 which is embedded in the first display control system 200. The first smart controller 202 includes data/sync input circuitry 402, data output circuitry 404, chip control circuitry 406, register input circuitry 408, programmable registers 410, multiplexer circuitry 412, column control circuitry 419, row control circuitry 421, high-power analog output circuitry 416, and optionally flash memory 303. Data/sync input circuitry 402 receives display data and sync signals via lines 104 from the host system 105. The data/sync input circuitry 402 is connected via lines 403 to data output circuitry 404 and via lines 405 to the chip control circuitry 406. Register input circuitry 408 may receive digital values via the first serial bus 204 from the external PROM 206 and via the second serial bus 208 from the host system 105. The register input circuitry 408 is connected via lines 409 to the registers 410. Alternatively, the register input circuitry 408 may receive digital values from the flash memory 303. The registers 410 are connected via lines 411 to the chip control circuitry 406. The registers 410 are also connected via lines 412 to multiplexer (MUX) circuitry 413 which is in turn connected via lines 414 to the chip control circuitry 406 and via lines 41 to the high-power analog output circuitry 416. The chip control circuitry 406 receives information via lines 405 from the data/sync input circuitry 402 and via lines 41 1 from the programmable registers 410. Using the information thus received, the chip control circuitry 406 sends timing and control signals via lines 417 to the data output circuitry 404, via lines 418 to the column control circuitry 419, via lines 420 to the row control circuitry 421 , and finally via lines 422 to the high-power analog output circuitry 416. The data output circuitry 404 receives display data signals via lines 403 from the data/sync input circuitry 402 and timing and control signals via lines 417 from the chip control circuitry 406. The data output circuitry 404 sends the display data signals via lines 107 to the column drivers 108. The column control circuitry 419 receives timing and control signals via lines 418 from the chip control circuitry 406. The column control circuitry 419 sends timing and control signals via lines 106 to the column drivers 108. The row control circuitry 421 receives timing and control signals via lines 420 from the chip control circuitry 406. The row control circuitry 421 sends timing and control signals via lines 1 12 to the row drivers 1 14. Finally, the high-power analog output circuitry 416 receives timing and control signals via lines 422 from the chip control circuitry 406 and digital values via lines 415 from the MUX circuitry 413. The high-power analog output circuitry 416 sends relatively high-power analog reference levels via lines 120 to the column drivers 108. Figure 4B is a block diagram showing a more detailed view of the second smart controller 302 which is embedded either in the second display control system 300 or the third display control system 350. Like the first smart controller 202, the second smart controller 302 includes data/sync input circuitry 402, data output circuitry 404, chip control circuitry 406, register input circuitry 408, programmable registers 410, multiplexer circuitry 412, column control circuitry 419, and row control circuitry 421. Unlike the first smart controller 202. the second smart controller 302 includes low-power analog output circuitry 450. Data/sync input circuitry 402 receives display data and sync signals via lines 104 from the host system 105. The data sync input circuitry 402 is connected via lines 403 to data output circuitry 404 and via lines 405 to the chip control circuitry 406. Register input circuitry 408 may receive digital values via the first serial bus 204 from the external PROM 206 and via the second serial bus 208 from the host system 105. The register input circuitry 408 is connected via lines 409 to the registers 410. Alternatively, the register input circuitry 408 may receive digital values from the flash memory 303. The registers 410 are connected via lines 41 1 to the chip control circuitry 406. The registers 410 are also connected via lines 412 to multiplexer (MUX) circuitry 413 which is in turn connected via lines 414 to the chip control circuitry 406 and via lines 415 to the low-power analog output circuitry 450. The chip control circuitry 406 receives information via lines 405 from the data/sync input circuitry 402 and via lines 41 1 from the programmable registers 410. Using the information thus received, the chip control circuitry 406 sends timing and control signals via lines 417 to the data output circuitry 404, via lines 418 to the column control circuitry 419, via lines 420 to the row control circuitry 421 , and finally via lines 422 to the low-power analog output circuitry 450. The data output circuitry 404 receives display data signals via lines 403 from the data/sync input circuitry 402 and timing and control signals via lines 417 from the chip control circuitry 406. The data output circuitry 404 sends the display data signals via lines 107 to the column drivers 108. The column control circuitry 419 receives timing and control signals via lines 418 from the chip control circuitry 406. The column control circuitry 419 sends timing and control signals via lines 106 to the column drivers 108. The row control circuitry 421 receives timing and control signals via lines 420 from the chip control circuitry 406. The row control circuitry 421 sends timing and control signals via lines 1 12 to the row drivers 1 14. Finally, the low-power analog output circuitry 450 receives timing and control signals via lines 422 from the chip control circuitry 406 and digital values via lines 415 from the MUX circuitry 413. If the second smart controller 302 is used in the second display control system 300, the low-power analog output circuitry 416 sends low-power analog reference levels via lines 304 to the drive buffers 306. If the second smart controller 302 is used in the third display control system 350. the low-power analog output circuitry 416 sends low-power analog reference levels via lines 120 to the column drivers 354 which are capable of utilizing low- power analog reference levels. Figure 5 is a schematic diagram showing the input/output of a column driver (108 or 354). The column driver (108 or 354) receives as input X+l analog reference levels (V0, VI, ..., VX) (either high-power or low-power) via lines (120 or 304), digital display data via lines 107, and control and timing signals via lines 106. The column driver (108 or 354) outputs a large number (p+1) of analog voltages that are applied via lines 109 to the column electrodes of the display 1 10. Each of the n-bit display data values is latched and converted using the X+l analog reference levels to one of the p+1 analog voltages. In the conversion process, the X+l analog reference levels are typically used to approximate a non-linear transfer curve 602 of a liquid crystal display (LCD). Figure 6 is a graph of a typical non-linear LCD transfer curve 602. Transmission of a display pixel is plotted against voltage applied across the pixel. For purposes of illustration, ten reference voltages, V0 through V9 (X=9), are shown that correspond to linear steps in transmission. These reference voltages are the analog reference levels used by the column drivers (108 or 354) to convert the n-bit data values to the analog voltages that are applied via lines 109 to the column electrodes of the display 110. Figure 7A is a diagram of a first and preferred embodiment 700 including either the high-power analog output circuitry 416 in Figure 4A or the low-power analog output circuitry 450 in Figure 4B. This first embodiment requires that the size of the D/A converters 702 is small enough for several of them to be easily integrated onto the smart controller chip (202 or 302). As shown in Figure 7 A, X+l internal digital-to-analog (D/A) converters 702 output analog reference levels (A0, Al, ..., AX). For low-power analog output circuitry 450, the outputs of the D/A converters 702 are relatively low power. For high-power analog output circuitry 416, the outputs of the D/A converters 702 must be higher power. The D/A converters 702 receive their input via lines 415 from the X+l 2:1 multiplexers 704 in MUX circuitry 413. Each 2:1 multiplexer 704 is controlled by a polarity (POL) signal and selects between either of two reference values, REF+ or REF-. The POL signal is received by the MUX circuitry 413 via lines 414 from the chip control circuitry 406. Each of these reference values, REF+ and REF-, is selected via lines 412 from among multiple digital values stored in one of 2(X+1) register files in programmable registers 410. The selection from among the multiple digital values in each register file may be performed by various means. For example, as shown in Figure 7A,-2(X+1) 5: 1 multiplexers 706 may be used where five is the number of digital values stored in each register file. These 5: 1 multiplexers 706 are controlled by a curve selection (CUR) signal that is received via lines 414 from the chip control circuitry 406. Each of the digital values in a register file may correspond to a different transfer curve. Thus, taken as a whole, the register files allow the smart controller (202 or 302) to store multiple transfer curves, denoted by curve A, curve B, curve C, etc. As illustrated in Figure 7A, two versions of each transfer curve, denoted by plus and minus signs, may be stored in two associated register files. The 2: 1 MUXes 704 select whether the plus or the minus version of the transfer curve is used as the input to the D/A converters 702 depending on the value of the POL signal. The POL signal may be caused by the chip control circuitry 406 to switch between the plus or minus versions of the transfer curve at any point during a display line time, or to fix the selected reference value to the plus or minus version of the transfer curve. One use of switching between the plus and minus versions of a transfer curve is to invert the polarity of the LC (liquid crystal) material between the addressing of the rows. The analog outputs of the D/A converters 702 should be of a resolution high enough to properly compensate for the non-linearity of the transfer curve of the liquid crystal. That is, the digital values in the register files should have a sufficient number of bits so that the analog outputs of the D/A converters 702 may be adjusted to greater precision than the precision of the output of the column drivers (108 or 354). Modem column drivers have precisions typically on the order of 20 mV. The voltage range necessary nowadays for the analog outputs is about 10V because the full transfer curve (both positive and negative) of the liquid crystal must be spanned. For the case where the D/A converters 702 convert digital values to analog values linearly, the digital values must have at least 9 bits of precision because 10V/20mV = 500 and 2 9 = 512. In Figure 7A. the number of bits for each of the digital values is m. Thus, using the above calculations, m should be at least 9. If non-linear D/A converters 702 are used, then the number of bits may be reduced by concentrating the highest analog precision to the sections of the transfer curve where the transmission changes rapidly with voltage, and by allowing greater error tolerances on the sections of the transfer curve where the transmission changes less rapidly. Figure 7B is a diagram of a second and alternate embodiment including either the high- power analog output circuitry 416 in Figure 4A or the low-power analog output circuitry 450 in Figure 4B. This second embodiment is preferable if the size of a D/A converter 702 is too large for several of them to be easily integrated onto the smart controller chip (202 or 302). Unlike in the first embodiment 700, in the second embodiment 750 a single D/A converter 752 is used to drive all of the X+l analog reference levels (A0, Al, ... AX). The input into the D/A converter 752 comes from (X+l ): 1 MUX 754. The (X+l ): 1 MUX 754 selects one of the X+l digital reference values output by the 2:1 MUXes 704. The (X+l): l MUX 754 is controlled by a selection (SEL) signal that is received via lines 414 from the chip control circuitry 406. Each analog output of the D/A converter 752 is fed by a refresh circuit 756 into a particular one of X+l sample and hold (S/H) circuits 758. The particular S H circuit 758 into which the analog output is fed corresponds to the digital reference value selected by the (X+l): 1 MUX 754. Since S/H circuits 758 typically use dynamic storage, the refresh circuit 756 must continually run to refresh the stored analog values in the S/H circuits 758. At the output of each S/H circuit 758 is a buffer 760 to boost the drive capability of the analog reference level which is output. For high-power analog output circuitry 416, the buffers 760 must be of relatively high power. For low-power analog output circuitry 450, the buffers 760 may be relatively low power. Like in the first embodiment 700, in the second embodiment 750 each of the 2:1 MUXes 704 selects between either of two reference values, REF+ or REF-. Each of these reference values is selected from among multiple digital values stored in one of a pair of register files in registers 410. The selection from among the multiple digital values in each register file may be performed by various means. For example, in Figure 7B 5: 1 multiplexers 706 are used. Also like in the first embodiment 700, in the second embodiment 750 each of the multiple digital values in a register file may correspond to a different transfer curve. Thus, taken as a whole, the register files allow the smart controller (202 or 302) to store multiple transfer curves, denoted by curve A, curve B, curve C, etc. For example, in Figure 7B the total number of transfer curves shown is five. Again like in the first embodiment 700, in the second embodiment 750 the smart controller (202 or 302) stores two versions of each transfer curve in two associated register files. The plus and minus signs denote the two different versions. The 2:1 MUXes 704 select whether the plus or the minus version of the transfer curve is used as the input to the (X+l):l MUX 754. The 2:1 MUXes 704 are controlled by the internal polarity (POL) signal which is received via lines 414 from the chip control circuitry 406. The POL signal may be programmed to cause the 2: 1 MUXes 704 to switch between the REF+ and the-REF- reference values at any point during a display line time, or to fix the selected reference value to the plus or minus version of the transfer curve. Finally, like in the first embodiment 700, the analog reference levels (A0, Al . ..., AX) should be of sufficiently high resolution in order to be able to properly compensate for the non- linearity of the transfer curve of the liquid crystal. That is, the digital values in the register files should have a sufficient number of bits so that the analog outputs of the D/A converters 702 may be adjusted to greater precision than the precision of the output of the column drivers (108 or 354). Modern column drivers have precisions typically on the order of 20 mV. The voltage range necessary nowadays for the analog outputs is about 10V because the full transfer curve (both positive and negative) of the liquid crystal must be spanned. For the case where the D/A converters 702 convert digital values to analog values linearly, the digital values must have at least 9 bits of precision because 10V/20mV = 500 and 2 9 = 512. In Figure 7B. the number of bits for each of the digital values is m. Thus, using the above calculations, m should be at least 9. If non-linear D/A converters 702 are used, then the number of bits may be reduced by concentrating the highest analog precision to the sections of the transfer curve where the transmission changes rapidly with voltage, and by allowing greater error tolerances on the sections of the transfer curve where the transmission changes less rapidly. Three graphs of display gammas are shown in Figures 8A, 8B and 8C. A plot of transmission of a display versus the DAC value is known as the display gamma. Figure 8A shows a linear display gamma. To get a linear display gamma, the analog reference levels are chosen to achieve linear steps in transmission as a function of the DAC value. For certain types of display images, display gammas other than linear gammas are often desirable. For example, non-linear gammas are useful for imaging work where precise control over the tonal reproduction of the image is needed in order to match print outputs. Such imaging work will be important as flat panel displays, which are more capable of a wider color gamut than cathode ray tube (CRT) displays, begin to replace CRTs on the desk top for use in desktop publishing and graphic arts. Figures 8B and 8C shows two non-linear display gammas for purposes of illustration. Controlling the gamma display through the analog reference levels for the column drivers is a superior way to control the display gamma and has a big advantage over control by the color look-up table (CLUT) method. Using color look-up tables to achieve non-linear gammas results in a large number of DAC values that have the same transmission value. This is a big price to pay in flat panel displays where the DAC value is typically limited to 64 levels. Instead, by adjusting the analog reference levels, all DAC values correspond to unique transmission values. Furthermore, using the method of adjusting the analog reference levels allows the analog reference levels to be set by software in the host system 105 so that the user may adjust the display gamma depending on the application in use. Various gamma curves may also be preprogrammed into the smart controller chip (202 or 302) by the manufacturer (see curve A, curve B, etc. in Figures 7 A and 7B), and the software in the host system may simply select between the different preprogrammed curves. Adjusting the analog reference levels may also assist in compensating for temperature changes in the display. As temperature changes, the transfer curve for the liquid crystal (see Figure 6) may shift to higher or lower voltages. This results in the display characteristics changing, especially for gray scale images. The smart controller (202 or 302) has the ability to compensate for such temperature changes since it can adjust the analog reference levels. An external signal input into the smart controller (202 or 302) may be used by the smart controller (202 or 302) to select between preprogrammed temperature-compensated gamma curves, or the system software in the host system 105 may change the analog reference levels.

Claims: What is claimed is: 1. An integrated circuit device for controlling column and row drivers of an active matrix display comprising: row control circuitry for generating digital timing and control signals to the row drivers; column control circuitry for generating digital timing and control signals to the column drivers; and analog output circuitry for outputting analog reference levels used by the column drivers to determine analog voltages to apply to column electrodes of the active matrix display. 2. The device of claim 1 , where drive buffers increase the power of the analog reference levels before the analog reference levels are used by the column drivers. 3. The device of claim 1, where the analog reference levels are relatively low power and the column drivers are designed to use relatively low power analog reference levels. 4. In an integrated circuit device, a system for controlling column and row drivers of an active matrix display comprising: data/sync input circuitry for receiving display data from an interface to a host system; chip control circuitry receiving signals from the data/sync input circuitry; row control circuitry for receiving digital timing and control signals from the chip control circuitry and for providing control signals to the row drivers; column control circuitry for receiving digital timing and control signals from the chip control circuitry and for providing control signals to the column drivers; and analog output circuitry for receiving digital timing and control signals from the input circuitry and for producing analog output signals that determine analog reference levels for the column drivers. 5. The system of claim 4, further comprising: registers connected to the analog output circuitry for storing digital values that determine the analog output signals. 6. The system of claim 5, where the digital values are initially received from a programmable read-only-memory external to the integrated circuit device. 7. The system of claim 5, where the digital values are received from the interface to the host system. 8. The system of claim 5, where the digital values are initially received from flash memory internal to the integrated circuit device. 9. The system of claim 7, where the digital values are determined dynamically by software in the host system in order to adjust a display gamma function for the flat panel display. 10. The system of claim 5, wherein the registers include first and second register files and the analog outputs include first analog output, further comprising: a multiplexer for selecting between a first digital value from the first register file and a second digital value from the second register file; and a digital-to-analog converter within the analog circuitry for receiving the digital value selected by the multiplexer and driving the first analog output. 11. The system of claim 10, where the first digital value is positive, the second digital value is negative, and further comprising: a polarity signal applied to the multiplexer to switch the selection made by the multiplexer between the first and second digital values in synchronization with the timing signals provided to the column drivers, where the switching between the first and second digital values causes inversion of a liquid crystal material in the flat panel display. 12. The system of claim 10, where the first register file contains a plurality of digital values which correspond to a plurality of display gamma functions. 13. The system of claim 4, further comprising: registers connected to the analog output circuitry for storing digital values that determine the analog output signals, the registers including first, second, third, and fourth register files; a first multiplexer for selecting between a first positive digital value stored from the first register file and a second positive digital value from the second register file, where the first positive digital value relates to a first display gamma function for the flat panel display, and the second positive digital value relates to a second display gamma function for the flat panel display; a second multiplexer for selecting between a first negative digital value from the third register file and a second negative digital value from the fourth register file, where the first negative digital value relates to the first display gamma function and the second negative digital value relates to the second display gamma function; a third multiplexer for selecting between the digital value selected by the first multiplexer and the digital value selected by the second multiplexer; and a digital-to-analog converter within the analog circuitry for receiving the digital value selected by the third multiplexer and driving the analog reference level to a voltage corresponding to the digital value received. 14. The system of claim 4, further comprising: registers connected to the analog output circuitry for storing digital values that determine the analog output signals, the registers including first, second, third, and fourth register files; a first multiplexer for selecting between a first digital value from the first register file and a second digital value from the second register file; a second multiplexer for selecting between a third digital value from the third register file and a fourth digital value from the fourth register file; a third multiplexer for selecting between the digital value selected by the first multiplexer and the digital value selected by the second multiplexer; a digital-to-analog converter within the analog circuitry for receiving the digital value selected by the third multiplexer and outputting an analog level corresponding to the digital value received; and a refresh circuit for receiving the analog level and distributing the analog level to either a first sample and hold circuit or a second sample and hold circuit; a first buffer for receiving a first held level from the first sample and hold circuit and driving a first analog reference level to the first held level; and a second buffer for receiving a second held level from the second sample and hold circuit and driving a second analog reference level to the second held level. 15. The system of claim 4, further comprising: registers connected to the analog output circuitry for storing digital values that determine the analog output signals, the registers including first, second, third, fourth, fifth, sixth, seventh, and eighth registers; a first multiplexer for selecting between a first positive digital value stored in the first register and a second positive digital value stored in the second register, where the first positive digital value relates to a first display gamma function for the flat panel display and the second positive digital value relates to a second display gamma function for the flat panel display; a second multiplexer for selecting between a first negative digital value stored in the third register and a second negative digital value in the fourth register, where the first negative digital value relates to the first display gamma function and the second negative digital value relates to the second display gamma function; a third multiplexer for selecting between a third positive digital value stored in the fifth register and a fourth positive digital value stored in the sixth register, where the third positive digital value relates to the first display gamma function and the fourth positive digital value relates to the second display gamma function; a fourth multiplexer for selecting between a third negative digital value stored in the seventh register and a fourth negative digital value in the eighth register, where the third negative digital value relates to the first display gamma function and the fourth negative digital value relates to the second display gamma function; a fifth multiplexer for selecting between the digital value selected by the first multiplexer and the digital value selected by the second multiplexer; a sixth multiplexer for selecting between the digital value selected by the third multiplexer and the digital value selected by the fourth multiplexer; a seventh multiplexer for selecting between the digital value selected by the fifth multiplexer and the digital value selected by the sixth multiplexer; a digital-to-analog converter within the analog circuitry for receiving the digital value selected by the seventh multiplexer and outputting an analog level corresponding to the digital value received; a refresh circuit for receiving the analog level and distributing the analog level to either a first sample and hold circuit or a second sample and hold circuit; a first buffer for receiving a first held level from the first sample and hold circuit and driving a first analog reference level to the first held level; and a second buffer for receiving a second held level from the second sample and hold circuit and driving a second analog reference level to the second held level. 16. In an integrated circuit device, a method for controlling column and row drivers of an active matrix display comprising: receiving display information from an interface to a host system; determining from the information received first digital timing and control signals for the row drivers; determining from the information received second digital timing and control control signals for the column drivers; determining from the information received analog levels for the column drivers; outputting the first digital timing and control signals to the row drivers; outputting the second digital timing and control signals to the column drivers; and outputting the analog levels to the column drivers. 17. The method of claim 16, further comprising: storing digital values used to determine the analog levels. 18. The method of claim 17, further comprising: initially receiving the digital values from a programmable read-only memory external to the integrated circuit device. 19. The method of claim 17, where the digital values are received from the interface to the host system. 20. The method of claim 19, where the digital values are determined dynamically by software in the host system. 21. The method of claim 17, further comprising: selecting with a multiplexer between a first digital value from a first register file and a second digital value from a second register file; converting the digital value selected into one of the analog levels. 22. The method of claim 21, where the first digital value is positive, the second digital value is negative, and further comprising: applying a polarity signal to the multiplexer. 23. The method of claim 21 , where the first register file contains a plurality of digital values. 24. The method of claim 17, further comprising: selecting with a first multiplexer between a first digital value from a first register file and a second digital value from a second register file; selecting with a second multiplexer between a third digital value from a third register file and a fourth digital value from a fourth register file; selecting with a third multiplexer between the digital value selected by the first multiplexer and the digital value selected by the second multiplexer; converting the digital value selected by the third multiplexer into the analog level; distributing the analog level to either a first sample and hold circuit or a second sample and hold circuit; receiving a first hold level from the first sample and hold circuit into a first buffer which drives a first analog reference level; and receiving a second held level from the second sample and hold circuit into a second buffer which drives a second analog reference level.

Inventors: COSTA VICTOR M DA, DA COSTA, VICTOR, M.
Applicants: SILICON IMAGE INC, SILICON IMAGE, INC.
Application year: 1997
Main classification: G09G3
IPC codes: G09G3