Current reference circuit with low power supply voltage and active feedback for PLL

Abstract: A current reference circuit includes a first, current mirror transistor having a gate coupled to a first feedback node, a source coupled to a first supply terminal and a drain forming a first reference node. A second, current mirror transistor has a gate coupled to the first feedback node, a source coupled to the first supply terminal and a drain forming a second reference node. A third transistor has a gate coupled to a second feedback node, a source coupled to a second supply terminal and a drain coupled to the first reference node. A fourth transistor has a gate coupled to the second feedback node, a source coupled to the second supply terminal and a drain coupled to the second reference node. A first operational amplifier has a first input coupled to the first reference node, a second input coupled to a bias node and an output forming the first feedback node. A second operational amplifier has a first input coupled to the second reference node, a second input coupled to the bias node and an output forming the second feedback node. The operational amplifiers are active elements which allow the current reference circuit to operate at a very low voltage and have a very low sensitivity to changes in the supply voltage.

Description: The present invention relates to current reference circuits: and, for example , to a current reference circuit having a low power supply sensitivity and which operates with a very low power supply voltage. Current reference circuits are used in many applications, including phase locked loops (PLLs). Current reference circuits preferably operate at a low voltage and preferably provide a reference current which is relatively insensitive to changes in the supply voltage. Advancements in semiconductor integrated circuit fabrication technology enable the geometries of circuit devices to be progressively reduced so that more devices can fit on a single integrated circuit. Power supply voltages are being reduced to reduce overall power consumption and to prevent damage to the devices having small feature sizes. For example, power supplies are now being reduced from 5.0 volts to 3.3 volts and from 3.3 volts to 2.5 volts and below. Reducing the power supply voltage presents a challenge when implementing traditional circuit configurations, such as a current reference circuit since the supply voltage must be large enough to provide for the necessary threshold voltages of the transistors in the circuit. G. Alvared et al., "A Wide-Bandwidth Low-Voltage PLL for PowerPC™ Microprocessors," IEEE J. Solid-State Circuits, Vol. 30, No. 4, pp. 383-92 (April 1995), discloses a current reference circuit formed of a pair of ratioed P+ to nwell diodes, a pair of ratioed NMOS transistors, a PMOS current mirror load and a start-up circuit. Although this current reference circuit has several advantages, it has a relatively large sensitivity to changes in supply voltage and requires a supply voltage of higher than 2.0 volts. Therefore, the circuit cannot be used with recent advances process technologies which require supply voltages of less. than 2.0 volts. There is a continuing need for improved current reference circuits having low sensitivity to changes in supply voltage and which operate with very low supply voltages. Reference may be made to US 4 689 581 which describes an integrated circuit device including a timing apparatus arranged to produce timing signals whose frequency is a multiple of that of a clock signal. The timing apparatus, which includes a phase locked loop, is formed on a single chip and no external components are said to be necessary. The phase locked loop includes a convertor and filter circuit, the convertor including two transistor current sources whose current magnitude is determined by a current reference circuit including current mirror transistors. The current sources are controlled by increase and decrease output signals from a phase and frequency comparator such that the output of the convertor depends upon the mark space ratio of the comparator output signals. The output of the convertor is filtered and then fed as a control voltage to a voltage controlled oscillator. The oscillator output is fed by way of a divider to the phase comparator and also provides the high frequency input timing signal for a logic device, such as a microcomputer. As the timing apparatus is fabricated using MOS technology, it is not possible to forecast its performance accurately. The timing apparatus is said to be capable of exhibiting closed loop stability without further trimming. However, to ensure that such closed loop stability can always be obtained, additional components, for varying the parameters of the circuits may be provided, said components being connectible into the circuit by programmable switches, such as laser fuses. Reference may also be made to US 4 890 052 which describes a temperature constant Gm current reference circuit which is also independent of voltage across the circuit. The current reference circuit includes a circuit for applying a substantially identical voltage to a semiconductor diode as well as to a branch circuit comprising a polysilicon resistor of predetermined doping level in series with plural unidirectional current carrying devices connected in parallel, preferably in the form of a multi-electrode transistor. From eight to twelve such unidirectional current carrying devices are required in the preferred embodiment. Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. A current reference circuit according to the present invention includes a first current mirror transistor having a gate coupled to a first feedback node, a source coupled to a first supply terminal and a drain forming a first reference node. A second, current mirror transistor has a gate coupled to the first feedback node, a source coupled to the first supply terminal and a drain forming a second reference node. A third transistor has a gate coupled to a second feedback node, a source coupled to a second supply terminal and a drain coupled to the first reference node. A fourth transistor has a gate coupled to the second feedback node, a source coupled to the second supply terminal and a drain coupled to the second reference node. A first operational amplifier has a first input coupled to the first reference node, a second input coupled to a bias node and an output forming the first feedback node. A second operational amplifier has a first input coupled to the second reference node, a second input coupled to the bias node and an output forming the second feedback node. In one embodiment, the current reference circuit further includes a bias generator having a fifth, current mirror transistor and a sixth, bias transistor. The fifth, current mirror transistor has a gate coupled to the first feedback node, a source coupled to the first supply terminal and a drain. The sixth, bias transistor has a gate and a drain coupled to the drain of the fifth, current mirror transistor and to the bias node and has a source coupled to the second supply terminal. The sixth, bias transistor sets the voltage on the bias node and thereby sets the operating state of the current reference circuit. The operational amplifiers are active feedback elements which allow the current reference circuit to operate at a very low supply voltage and have a very low input offset sensitivity to changes in the supply voltage. When the supply voltage increases, the voltages on the first and second reference nodes tend to increase slightly relative to the voltage on the bias node. The operational amplifiers sense the difference in voltage and adjust the voltages on the feedback nodes to adjust the operating states of the first and second mirror transistors and thereby restore the voltages on the first and second reference nodes. Exemplary embodiments of the invention are described hereinafter, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a schematic diagram of a current reference of the prior art. Figure 2 is a schematic diagram of an embodiment of a current reference circuit according to the present invention. Figure 3 is a schematic diagram of an operational amplifier used in the current reference circuit shown in Figure 2. Figure 4 is a schematic diagram of another operational amplifier used in the current reference circuit shown in Figure 2. Figure 1 is a schematic diagram of a current reference circuit of the prior art. Current reference circuit 10 includes voltage supply terminals VDD and GND, PMOS current mirror.load transistors MP1 and MP2, a pair of ratioed NMOS transistors MN1 and MN2, and a pair of diodes D1 and D2. Transistors MP1 and MP2 are coupled together to form a current mirror which generates substantially equal currents I1 and I2 through nodes N1 and N2, respectively. Transistors MN1 and MN2 are ratioed with respect to one another such that the gate length of transistor MN1 is greater than the gate length of transistor MN2, and/or the gate width of transistor MN2 is greater than the gate width of transistor MN1. A start-up circuit (not shown) injects a current into node N1 to initiate current flowing in the reference circuit. A further current mirror transistor can be coupled to transistors MN1 and MN2 to mirror either current I1, or I2 to an output-stage as a reference current. Current reference circuit 10 requires a relatively large minimum supply voltage to turn on the transistors in the circuit. The minimum turn on voltage at the gate of transistor MP2 is, V GS,MP2,MIN = V T,MP2 + V DS,SAT,MP2 Where V T,MP2 is the gate to source threshold voltage of transistor MP2 and V DS,SAT,MP2 is the drain to source saturation voltage of transistor MP2. Looking at the voltage drops in the right hand branch of the circuit, the minimum supply voltage VDD MIN required to turn on transistor MP2 and thus operate the branch equals the gate to source voltage V GS,MP2,MIN of transistor MP2 plus the drain to source saturation voltage, V DS,SAT,MN2 of transistor MN2 plus the voltage drop V D2 across diode D2. Therefore, substituting the righthand side of Equation 1 for V GS,MP2,MIN , VDD MIN = V DS,SAT,MP2 + V T,MP2 + V DS,SAT,MN2 + V D2 Which, in one embodiment, result in, VDD MIN = 0.3 + 0.9 + 0.3 + 0.5 = 2.0 Since the minimum supply voltage is 2.0 volts, current reference circuit 10 shown in Figure 1 cannot be used in advanced fabrication processes which have supply voltages lower than 2.0 volts. Also, current reference circuit 10 is relatively sensitive to changes in supply voltage. The voltage on reference node N2 tends to follow changes in VDD, which creates an imbalance between the voltages at nodes N1 and N2, and thus the currents through diodes D1 and D2. For example, currents I1 and I2 may change by up to 50% per volt change in the supply voltage. Figure 2 is a schematic diagram of an embodiment of a current reference circuit 50 according to the present invention. Current reference circuit 50 includes a bias generator 52, a reference generator 54 and an output circuit 56. Bias generator 52 includes P-channel current mirror transistor MP3 'and N-channel bias transistor MN3. Current mirror transistor MP3 has a source coupled to supply terminal VDD, a gate coupled to a feedback node FB1 and a drain coupled to the drain and gate of bias transistor MN3. The source of bias transistor MN3 is coupled to voltage supply terminal GND. The drain of current mirror transistor MP3 generates a bias current I BIAS which flows through bias transistor MN3, which generates a bias voltage V BIAS on bias node BIAS. The voltage on bias node BIAS sets the operating state of reference generator 54. Reference generator 54 is similar to the circuit shown in Figure 1 in that the generator includes P-channel current mirror transistors MP4 and MP5, N-channel transistors MN4 and MN5 and diodes D2 and D3. However, N-channel transistors MN4 and MN5 are not required to be ratioed in the same manner as transistors MN1 and MN2 and current generator 54 further includes operational amplifiers OP1 and OP2 which provide active feedback for current mirror transistors MP4 and MP5 and for transistors MN4 and MN5, respectively. Current mirror transistor MP4 has a gate coupled to feedback node FB1, a source coupled to supply terminal VDD and a drain coupled to reference node N3. Current mirror transistor MP5 has a gate coupled to feedback node FB1, a source coupled to supply terminal VDD and a drain coupled to reference node N4. Transistor MN4 has a gate coupled to feedback node FB2, a source coupled to diode D2 and a drain coupled to reference node N3. Diode D2 is coupled between the source of transistor MN4 and supply terminal GND. Transistor MN5 has a gate coupled to feedback node FB2, a source coupled to diode D3 and a drain coupled to reference node N4. Diode D3 is coupled between the source of transistor MN5 and supply terminal GND. Operational amplifier OP1 has a first input 60 coupled to reference node N3, a second input 62 coupled to bias node BIAS, an output 64 coupled to feedback node FB1 and a reference voltage input 66 coupled to feedback node FB2. Operational amplifier OP2 has a first input 68 coupled to reference node N4, a second input 70 coupled to bias node BIAS, an output 72 coupled to feedback node FB2 and a reference voltage input 74 coupled to feedback node FB1. Output circuit 56 includes a P-channel current mirror transistor MP6 having a gate coupled to feedback node FB1, a source coupled to supply terminal VDD and a drain coupled to supply terminal GND. Current I 3 is mirrored into the drain of current mirror transistor MP6 as reference current I REF . Current reference circuit 50 further includes transistor MN6 having its gate coupled to bias node BIAS and its source and drain coupled to supply terminal GND. Transistor MN6 provides a filter for bias node BIAS. Resistor R1 and N-channel transistor MN7 provide frequency compensation for feedback node FB2. Resistor R1 is coupled between feedback node FB2 and the gate of N-channel transistor MN7. The source and drain of N-channel transistor MN7 are coupled to supply terminal GND. Similarly, resistor R2 and P-channel transistor MP7 provide frequency compensation for feedback node FB1. Resistor R2 is coupled between feedback node FB1 and the gate of P-channel transistor MP7. The source and drain of P-channel transistor MP7 are coupled to supply terminal VDD. In a preferred embodiment, all cransistors in current reference circuit 50 are implemented in metal oxide field-effect semiconductor transistor (MOSFET) technology. During operation, operational amplifiers OP1 and OP2 receive bias voltage V BIAS on bias node BIAS at inputs 62 and 70, respectively and adjust the voltages on feedback nodes FB1 and FB2 until the voltages on reference nodes N3 and N4, and thus inputs 60 and 72, are substantially equal to bias voltage V BIAS . Increasing or decreasing the voltages on feedback nodes FB1 and FB2 changes the operating states of transistors MP4 and MN5, which changes the drain-source voltage drops across transistors MP4 and MN5 and thus the voltages on reference nodes N3 and N4. The use of operational amplifier OP1 as an active feedback for the current mirror formed by current mirror transistors MP4 and MP5 allows current reference circuit 50 to have a very low sensitivity to changes in supply voltage VDD. If supply voltage VDD increases, operational amplifier OP1 will hold the voltage on reference node N3 equal to the voltage on bias node BIAS by adjusting the voltage applied to feedback node FB1. Similarly, operational amplifier OP2 holds the voltage on reference node N4 equal to the voltage on bias node BIAS by adjusting the voltage on feedback FB2 to thereby adjust the operating state of transistor MN5 and thereby adjusting the voltage drop across the transistor. Therefore, the voltages on reference nodes N3 and N4 do not follow changes in the supply voltage VDD. In the embodiment shown in Figure 2, the current through nodes N3 and N4 vary only 0.02% for each one volt change in supply voltage VDD. Increasing or decreasing the voltage of feedback node FB1 has the same effect on the operation of current mirror transistors MP3, MP5 and MP6. The bias voltage supplied by bias transistor MN3 is therefore also insensitive to changes in supply voltage VDD. As supply voltage VDD increases, operational amplifier OP1 adjusts the voltage on feedback node FB1, which adjusts the operating state of transistor MP3 in a similar manner as transistor MP4, to thereby maintain the bias voltage on bias node BIAS. Another advantage of the current reference circuit shown in Figure 2 is that the circuit can operate with a very low supply voltage VDD. As shown in Figure 2, current mirror transistor MP5 does not have its gate coupled to its drain as is the case with transistor MP2 in the circuit shown in Figure 1. Therefore, the threshold voltage of transistor MP5 is not added to the minimum supply voltage VDD. Looking at the right hand branch of the circuit shown in Figure 2, the minimum supply voltage is, VDD MIN = V DS,SAT,MP5 + V DS,SAT,MN5 + V D3 Where V DS,SAT,MP5 and V DS,SAT,MN5 are the drain to source saturation voltages of transistors MP5 and MN5, respectively, and V D3 is the voltage drop across diode D3. In one embodiment, this results in, VDD MIN = 0.3V +0.3V + 0.5V = 1.1V The current reference circuit shown in Figure 2 therefore has a much lower minimum supply voltage than does the circuit shown in Figure 1. The following tables provide examples of gate lengths and gate widths of the transistors shown in Figure 2 according to one embodiment of the present invention: Transistor Length (Microns) Width (microns) MP3 5 20 MP4 5 20 MP5 5 20 MP6 5 20 MP7 5 20 MN3 10 6 MN4 5 12 MN5 5 12 MN6 5 12 MN7 5 12 Figure 3 is a schematic diagram of operational amplifier OP1 shown in Figure 2 . Operational amplifier OP1 includes inputs 60 and 62, output 64, reference voltage input 66, P-channel transistors MP10-MP18, N-channel transistors MN10-MN18 and diodes D10-D12. Operational amplifier OP1 receives the voltages on reference node N3 and bias node BIAS on inputs 60 and 62, respectively, and generates an output voltage on output 64 which is proportional to a difference between the voltages applied to inputs 60 and 62. Reference voltage input 66 receives the voltage on feedback node FB2, which sets the gain of operational amplifier OP1. Figure 4 is a schematic diagram of operational amplifier OP2. Operational amplifier OP2 includes inputs 68 and 70, output 72, reference voltage input 74, P-channel transistors MP20-MP28, N-channel transistors MN20-MN30 and diodes D20 and D21. Input 68 is noninverting and input 70 is inverting. Operational amplifier OP2 generates an output voltage on output 72 in response to a difference between the voltages applied to inputs 68 and 70. The voltage on reference voltage-input 74 sets the gain of operational amplifier OP2. The schematic diagrams shown in Figures 3 and 4 are shown as examples only. Various other operational amplifiers or circuit configurations can also be used in 'embodiments of the present invention. Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the scope of the invention. For example, an embodiment of a current reference circuit according to the present invention can be implemented with various technologies other than MOSFET technology and with various circuit configurations. Also, the voltage supply terminals can be relatively positive or relatively negative, depending upon the particular convention adopted and the technology used. In addition, this circuit can be inverted by replacing the P-channel transistors with N-channel transistors replacing the N-channel transistors with P-channel transistors and making other modifications. As such, the terms "drain" and "source" used in the specifications and the claims are arbitrary terms and can be interchanged. Likewise, the term "coupled" can include various types of connections or couplings and can include a direct connection or a connection through one or more intermediate components.

Claims: A current reference circuit comprising: first and second supply terminals (VDD;GND); a first, current mirror transistor (MP4) having a gate coupled to a first feedback node (FB1), a source coupled to the first supply terminal (VDD) and a drain forming a first reference node (N3); a second, current mirror transistor (MP5) having a gate coupled to the first feedback node (FB1), a source coupled to the source of the first, current mirror transistor (MP4) and a drain forming the second reference node (N4); a third transistor (MN4) having a gate coupled to a second feedback node (FB2), a source coupled to the second supply terminal (GND) and a drain coupled to the first reference node (N3); a fourth transistor (MN5) having a gate coupled to the second feedback node (FB2), a source coupled to the second supply terminal (GND) and a drain coupled to the second reference node (N4); a first feedback means (OP1) having a first input (60) coupled to the first reference node (N3), a second input (62) coupled to a bias node (BIAS) and an output (64) forming the first feedback node (FB1); and a second feedback means (OP2) having a first input (68) coupled to the second reference node (N4), a second input (70) coupled to the bias node (BIAS) and an output (72) forming the second feedback node (FB2). A current reference circuit according to Claim 1, wherein: the first feedback means (OP1) provides a first feedback voltage on the first feedback node (FB1) as a function of a bias voltage at the bias node (BIAS) and a voltage on the first reference node (N3); and the second feedback means (OP2) provides a second feedback voltage on the second feedback node (FB2) as a function of the bias voltage at the bias node (BIAS) and a voltage on the second reference node (N4). A current reference circuit according to claim 1 or 2 wherein said bias node (BIAS) is a bias voltage input to said circuit. A current reference circuit according to any preceding Claim, comprising: a first diode (D2) coupled between the source of the third transistor (MN4) and the second supply terminal (GND); and a second diode (D3) coupled between the source of the fourth transistor (MN5) and the second supply terminal (GND). A current reference circuit according to any preceding Claim, comprising a bias generator which comprises: a fifth, current mirror transistor (MP3) having a gate coupled to the first feedback node (FB1), a source coupled to the source of the first, current mirror transistor (MP4) and a drain; and a sixth, bias transistor (MN3) having a gate and drain coupled to the drain of the fifth, current mirror transistor (MP3) and to the bias node (BIAS) and having a source coupled to the second supply terminal (GND). A current reference circuit according to any preceding Claim, wherein the third and fourth transistors (MN4,MN5) have equal gate widths and equal gate lengths. A current reference circuit according to any preceding Claim, wherein each of the first and second feedback means (OP1,OP2) has a reference voltage input (66,74) which is coupled to the output of the other of the first and second feedback means. A current reference circuit according to any preceding Claim, comprising: an output transistor (MP6) having a gate coupled to the first feedback node (FB1), a source coupled to the source of the first, current mirror transistor, (MP4) and a drain providing a reference current output (I REF ). A current reference circuit according to any preceding Claim, wherein: the first feedback means comprises a first operational amplifier (OP1) having a first input (60) coupled to the first reference node (N3), a second input (62) coupled to the bias node (BIAS) and an output (64) forming the first feedback node (FB1); and the second feedback means (OP2) comprises a second operational amplifier having a first input (68) coupled to the second reference node (N4), a second input (70) coupled to the bias node (BIAS) and an output (72) forming the second feedback node (FB2).

Inventors: FIEDLER ALAN, TORGERSON PAUL, WEI SHURAN, FIEDLER, ALAN, TORGERSON, PAUL, WEI, SHURAN
Applicants: LSI LOGIC CORP, LSI LOGIC CORPORATION
Application year: 1997
Main classification: G05F3
IPC codes: G05F3