Adaptive signal detection method and apparatus

Abstract: A circuit and method for adaptively calculating a decision error of a digital signal in a digital modulation system. The circuit includes a digital filter (102) for Hilbert transform filtering I channel data to generate Q channel data which differs in phase from the I channel data, a delayer (100) for delaying the I channel data for a filtering time of the digital filter (102), a reference signal interval processor (104) for receiving the I channel data and generating a reference signal pulse for detecting a slope, an estimation and adaptive decision error detector (106) for receiving the I channel data delayed from the delayer (100) during a detected interval of the reference signal pulse, deciding symbol data and generating an adaptive decision error signal according to a detected slope, and a slope detector (108) for receiving the decision error signal generated from the estimation and adaptive decision error detector (106) and the Q channel data generated from the digital filter (102), detecting the slope during the detected interval of the reference signal pulse and generating the accumulated slope.

Description: The present invention relates to a circuit and method for calculating a decision error of a digital signal in a digital modulation system and, more particularly, to a circuit and method for adaptively calculating a decision error by limiting a phase detecting decision region. Colour TV has been developed from black-and-white TV, and since then consumers have moved on to desire TVs with larger-sized screens, higher resolution and generally more real sound and picture quality. With the active development toward such a recent trend, the first HDTV (High Definition TV) broadcasting is in progress on the basis of an analog transmission system. The HDTV transmission system developed in Japan is called MUSE (Multiple Sub-Nyquist Sampling Encoding) transmission system. The U.S. has used a VSB (vestigial sideband) modulation system adopted by the GA (Grand Alliance) committee as a modulation system of the HDTV system, and has proposed schematic configurations therefor. VSB modulation is used as one form of modulation of an analog video signal in existing TV broadcasting. The GA-HDTV proposed by the GA committee transmits a digital modulation signal by using a VSB signal. In an initial DSC (Digital Spectrum Compatible) HDTV, 2-level and 4-level VSB modulation systems using 2 and 4 levels have been adopted. However, in the GA-HDTV, an 8-level VSB modulation system using 8 levels and a 16-level VSB modulation system applied to a high speed cable mode have been adopted. To demodulate the VSB signal, the GA committee has proposed a VSB receiver of the HDTV having the following features. That is, the VSB receiver of the HDTV proposed by the GA committee implements sampling by a unit of symbol rate by detecting data by only a signal of an I (In-phase) channel unlike other demodulators of the digital modulation signal. Therefore, the VSB receiver of the HDTV proposed by the GA committee has a very simple structure compared with a receiver of QAM (Quadrature Amplitude Modulation) etc. using both an I channel and a Q (quadrature) channel. Moreover, since received data is processed by a unit of symbol rate, it is possible to detect the data even though a processing speed is relatively lower than a fractional rate receiver. The proposed VSB receiver uses synchronous detection for recovering a carrier wave when detecting digital data from the VSB modulation signal. The synchronous detection has an advantage in that it is possible to detect the data with a lower error rate than a synchronous detection at the same signal-to-noise ratio. However, a structure of the VSB receiver is complicated due to a carrier wave recovery circuit. Therefore, the proposed VSB receiver uses a FPLL (Frequency and Phase Locked Loop) and a PTL (Phase Tracking Loop) circuit in detecting the phase of a transmission signal for the synchronous detection. The FPLL performs phase tracking of the transmission signal by using a pilot signal contained in the VSB signal. This FPLL can be easily achieved by a frequency error detecting circuit of a conventional PLL (Phase Locked Loop) and is described in GA-HDTV system recommendations. An output of the FPLL passes though a channel equalizer and is further applied to an input of the PTL circuit. The PTL circuit eliminates phase noise, that is, phase error which is not eliminated in the FPLL. The structure of the PTL circuit of the GA-HDTV receiver is not greatly different from that of a DDCR (Decision Directed Carrier Recovery) circuit. However, the PTL circuit estimates rotation components of signal points by using sampling data of an input I channel and compensates a phase error value. In data of the I channel, information to be actually transmitted is contained. The Q channel has no function for transmitting actual information but reduces a spectrum of the modulation signal. If there is a phase error during demodulation, not only data of the I channel but also data of the Q channel is contained in the sampling data of the I channel. Therefore, in order for the PTL circuit to correct the phase error, information of the Q channel is also needed. The information of the Q channel can be easily obtained by filtering the data of the I channel by use of a Hilbert transform filter. Figure 1 is a block diagram showing a GA-HDTV receiver proposed as standardization by the GA committee. The overall operation for the VSB receiver of Figure 1 is described in Autumn Synthesis Science Publication Paper Collection issued in 1994 by the Korean Institute of communication Science, entitled "DESIGN AND PERFORMANCE ANALYSIS OF PHASE TRACKER FOR SYNCHRONOUS VSB RECEIVER". As shown in Figure 1, a system using the digital VSB modulation decides a digital signal through an equalizer 50 and a PTL 60 and utilizes a decision error value. For digital signal decision through the equalizer 50 and the PTL 60, the digital signal is decided to the nearest symbol by using a received I signal as shown in Figure 2. To improve wrong decision due to the phase error etc., there is used an adaptive decision method calculating a slope indicated by an oblique line in Figure 2 by using a Q signal obtained from the I signal. The slope represents phase error. While a fixed decision region is liable to an incorrect decision even by a small vestigial phase error, an adaptive decision region can reduce a decision error by obtaining the slope from data of a constant number. However, a circuit for deciding the digital signal to both I and Q axes becomes complicated. The paper "Hardware efficient algorithm for the phase tracking loop in Grand Alliance VSB HDTV system" by Wonho Lee, Kyungwhoon Cheun and Seokrim Choi published at pages 306-307 of the Proceedings of the 1996 IEEE International Conference on Consumer Electronics describes a hardware efficient algorithm for a phase tracking loop which tracks out the residual phase noise at the output of an equaliser in a VSB HDTV receiver. It is an aim of preferred embodiments of the present invention to provide a circuit and method for calculating a decision error according to the state of an input signal by adaptively limiting a decision region in a digital modulation system. It is another aim of preferred embodiments of the present invention to provide a circuit and method for simplifying a hardware construction and performing a stable operation. According to a first aspect of the present invention, there is provided a circuit arranged to adaptively calculate a decision error of a digital signal by limiting a decision error region in a digital modulation system, said circuit comprising: an estimation and adaptive decision error detector arranged to receive I channel data, identify symbol data according to a detected phase error and adaptively generate a decision error signal; a slope detector arranged to receive the decision error signal generated from the estimation and adaptive decision error detector, to receive Q channel data, to detect the phase error, and to generate an accumulated phase error; and characterised by: a reference signal interval processor arranged to receive the I channel data and generate a reference signal pulse, wherein the estimation and adaptive decision error detector is arranged to receive the I channel data and adaptively generate a decision error signal during a detected interval of the reference signal pulse, and wherein the slope detector is arranged only to detect the phase error and generate an accumulated phase error during the detected interval of the reference signal pulse. Preferably, the circuit comprises: a digital filter arranged to Hilbert transform filter the I channel data to generate Q channel data which differs in phase from said I channel data; a delayer arranged to delay said I channel data for a filtering time of the digital filter; and wherein the estimation and adaptive decision error detector is arranged to receive the I channel data delayed from the delayer during the detected interval of the reference signal pulse, and the slope detector is arranged to receive the Q channel data generated by the digital filter. Preferably, the slope detector (108) detects a slope a by the following equations: Ie = I' - I'' where I' is an input signal, I" is a symbol data value of a decision result, Ie is a decision error signal, and N is the number of symbols within the detected interval of said reference signal pulse. Preferably, the estimation and adaptive decision error detector includes: a decider arranged to receive the I channel data delayed from the delayer and identify symbol data by comparison to a reference level value; a region limiter arranged to compare the I channel data delayed from the delayer with a decision region corresponding to the detected phase error and to generate a limited region decision signal; a multiplexer arranged to receive the symbol data decided from the decider and the delayed I channel data, and selectively output either the symbol data decided from the decider or the delayed I channel data according to the limited region decision signal generated by said region limiter; and a subtracter arranged to subtract a signal generated from said multiplexer from the delayed I channel data to generate the decision error signal. Preferably, the circuit comprises: a digital filter arranged to digitally filter the I channel data to generate Q channel sign data which differs in phase from said I channel data; a delayer arranged to delay said I channel data for a filtering time of the digital filter; and wherein the estimation and adaptive decision error detector is arranged to receive the Q channel sign data and the I channel data delayed from the delayer during the detected interval of the reference signal pulse, and the slope detector is arranged to receive the Q channel sign data generated by the digital filter. Preferably, the estimation and adaptive decision error detector is arranged to receive Q channel sign data during the detected interval of the reference signal pulse, and, the slope detector is arranged to receive Q channel sign data. The circuit as set forth in claim 5 or 6, wherein said estimation and adaptive decision error detector includes: a decider arranged to receive the I channel data delayed from the delayer and identify symbol data by comparison to a reference level value; a first region limiter arranged to compare the I channel data delayed from the delayer with an I channel decision region corresponding to the detected phase error, and to generate a limited I channel region decision signal; a second region limiter arranged to compare the Q channel sign data generated from said digital filter with a Q channel decision region corresponding to the detected phase error, and to generate a limited Q channel region decision signal; a logic gate arranged to OR said limited I and Q channel region decision signals generated from said first and second region limiters (212, 214); a multiplexer arranged to receive the symbol data generated from said decider and said delayed I channel data and selectively generate one of the received data by a region decision signal generated from the logic gate; and a subtracter arranged to subtract a signal generated from the multiplexer from the delayed I channel data to generate the decision error signal. The circuit as set forth in claim 5, 6, or 7, wherein the slope detector detects a slope a by the following equations: Ie = I' - I'' where I' is an input signal, I" is a symbol data value of a decision result, Ie is a decision error signal, N is the number of symbols within the detected interval of said reference signal pulse, and sgn(Q) is Q channel sign data. According to a second aspect of the present invention there is provided a method for adaptively calculating a decision error of a digital signal by limiting a decision error region in a digital modulation system, the method comprising the steps of: receiving I channel data, identifying symbol data according to a detected phase error and generating a decision error signal; generating an accumulated phase error according to the decision error signal and received Q channel data; the method being characterised by: generating a reference signal pulse from the received I channel data, identifying symbol data according to a detected phase error and generate a decision error signal during a detected interval of the reference signal pulse, and, generating the accumulated phase error generated only during the detected interval of the reference signal pulse. Preferably, the step of receiving Q channel data comprises receiving Q channel sign data. For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figure 1 is a block diagram of a GA-HDTV receiver proposed by the GA committee of U.S.; Figure 2 is a scattering diagram showing a conventional signal decision method and an input signal having an error; Figure 3 is a block diagram of a circuit for adaptively calculating a decision error according to one preferred embodiment of the present invention; Figure 4 is a detailed block diagram of an estimation and adaptive decision error detector shown in Figure 3; Figure 5 is an operational waveform chart of Figure 3; Figure 6 shows a signal format of a GA-VSB system; Figure 7 is a block diagram of a circuit for adaptively calculating a decision error according to another preferred embodiment of the present invention; Figure 8 is a detailed block diagram of an estimation and adaptive decision error detector shown in Figure 7; and Figure 9 is an operational waveform chart of Figure 7. Figure 3 is a block diagram showing a circuit for adaptively calculating a decision error. A digital filter 102 Hilbert transform filters input I channel data to generate first Q channel data, for example, Q1 channel data which differs in phase from the I channel data. A delayer 100 delays the input I channel data for a filtering time of the digital filter 102. A reference signal interval processor 104 receives the input I channel data and generates a reference signal pulse for detecting a slope. An estimation and adaptive decision error detector 106 receives the delayed I channel data during the detected interval of the reference signal pulse, decides symbol data according to the slope and generates a decision error signal Ie. A slope detector 108 receives the decision error signal Ie generated from the estimation and adaptive decision error detector 106 and the Q' channel data generated from the digital filter 102, accumulates the slope during the detected interval of the reference signal pulse and supplies the accumulated slope to the estimation and adaptive decision error detector 106. Figure 4 is a detailed block diagram of the estimation and adaptive decision error detector 106 shown in Figure 3. A decider 110 receives the I channel data delayed from the delayer 100 and decides the symbol data to a reference level value. A region limiter 112 compares the I channel data delayed from the delayer 100 with a decision region corresponding to the slope and generates a limited region decision signal. A multiplexer (MUX) 114 receives the symbol data decided from the decider 110 and the delayed I channel data and selectively generates either the symbol data or the delayed I channel data in response to the limited region decision signal generated from the region limiter 112. A subtracter 116 subtracts a signal generated from the MUX 114 from the delayed I channel data to generate the decision error signal Ie. Figure 5 shows an operational waveform of Figure 3 and Figure 6 shows a signal format of a GA-VSB system. One preferred embodiment of the present invention will now be described with reference to Figures 3 to 6. To decide the symbol data is to limit a value of an input signal according to a slope a. If a reference signal is used in the GA-VSB system, segment synchronization or field synchronization may be used and an equalizer or a PTL using an estimator may be applied. The signal format of the GA-VSB system has the field synchronization corresponding to one segment per field and the segment synchronization of 4-symbol data per segment. Since these data are fixed values, they may be used in calculating the slope a. For example, data segment has forms of +S, -S, -S and +S. In this case, if level values of the symbol data defined from a transmitting side and a receiving side are defined as -7, -5, -3, -1, +1, +3, +5 and +7, +S and -S correspond to +5 and -5. In the GA-VSB system, since only the I channel signal is received when deciding the symbol data, Q channel information is needed to extract phase information from the I channel signal. The Q channel signal is recovered from the I channel signal by using the I channel signal and the digital filter 102 which is a Hilbert transform filter. The digital filter 102 shown in Figure 3 recovers the Q' channel data by Hilbert transform filtering the input I channel data. The delayer 100 delays the input I channel data for the filtering time of the digital filter 102. The reference signal interval processor 104 detects the reference signal pulse for detecting the slope from the I channel data and supplies the reference signal pulse to the estimation and adaptive decision error detector 106 and the slope detector 108. The estimation and adaptive decision error detector 106 decides the I channel symbol data and generates the decision error signal Ie. In the estimation and adaptive decision error detector 106 of Figure 4, the region limiter 112 compares the I channel data with the limited region to limit the decision region. If the I channel data exists within the range of limited region, the region limiter 112 supplies "0" to a select terminal of the MUX 114. If the I channel data is beyond the range of the limited region, the region limiter 112 supplies "1" to the select terminal of the MUX 114. The decider 110 decides the symbol value of the I channel data to a setting reference level. If there are 8 levels and if the I channel data is between 0 and 2, the decision output is "1". If the I channel data exists at a boundary portion, for example, 2, 4 or 6 etc., the same rule of rounding it up or down is applied. The MUX 114 selectively generates either the decision output decided from the decider 110 or the I channel data in response to a signal generated from the region limiter 112. Therefore, if the output signal of the region limiter 112 is "1", the MUX 114 generates the I channel data since the input signal of the region limiter 112 exists beyond the range of the limited region corresponding to the calculated slope. The subtracter 116 subtracts the I channel data of the same input signal from the I channel data to generate the decision error signal Ie of "0". Meanwhile, if the output signal of the region limiter 112 is "0", the MUX 114 generates the decision output of the decider 110 since the input signal of the region limiter is within the range of the limited region corresponding to the calculated slope. The subtracter 116 subtracts the decision signal decided to the setting reference level value from the I channel data to generate the decision error Ie. In an initial state, the decision region is a general decision region as indicated by P2 of Figure 5. The slope detector 108 calculates the slope value a by the following equations (1) and (2) with respect to the levels +S and -S while the reference signal pulse is detected from the reference signal interval processor 104: I e = I' - I'' where I' is the input signal, I" is the symbol data value of a decision result and N is the number of symbols within the detected interval of the reference signal pulse. If the detected interval of the reference signal pulse is over, the decision region for detecting the decision error by the estimation and adaptive decision error detector 106 is changed to P1 shown in Figure 5 by using the accumulated slope value. In the above equation (1), 1 / N may be eliminated for the simple hardware. Further, Q may use only its sign. In many cases, since Q estimated by the order of the digital filter is not reliable, the sign of Q is used. This method operates irrespective of the order of the digital filter. That is, the slope a may be calculated by the following equation (3) : where 1 / N may be eliminated, and sgn(Q) is sign data of the Q channel. Until the next reference signal is received, the estimation and adaptive decision error detector 106 operates with the fixed slope. The decision region for obtaining the decision error is limited according to the calculated slope as shown in Figure 5. The input signal beyond the range of the decision region is not used since the decision error is "0". In Figure 5, a part of a signal having a degree is beyond the range of the decision region. In a related circuit, if the slope is calculated by using a random signal, the reference signal interval processor 104 may be replaced with a pulse generator for generating an interval signal in order to calculate the slope. Figure 7 shows another circuit for adaptively calculating the decision error. In Figure 7, the decision region is limited by using the Q channel data as well as the I channel data to improve the reliability of the decision error. A digital filter 202 digitally filters the input I channel data to generate Q channel sign data which differs in phase from the I channel data. A delayer 200 delays the input I channel data for the filtering time of the digital filter 202. A reference signal interval processor 204 receives the I channel data and generates the reference signal pulse for detecting the slope. An estimation and adaptive decision error detector 206 receives the delayed I channel data during the detected interval of the reference signal pulse and the Q channel data, decides the symbol data and generates the decision error value according to the slope. A slope detector 208 receives the decision error value generated from estimation and adaptive decision error detector 206 and the Q channel sign data generated from the digital filter 202, accumulates the slope during the detected interval of the reference signal pulse, and supplies the accumulated slope to the estimation and adaptive decision error detector 206. Figure 8 is a detailed block diagram of the estimation and adaptive decision error detector 206 shown in Figure 7. A decider 210 receives the I channel data delayed from the delayer 200 and decides the symbol data to the reference level value. A first region limiter 212 compares the I channel data delayed from the delayer 200 with an I channel decision region corresponding to the calculated slope and generates a limited I channel region decision signal. A second region limiter 214 compares the Q channel sign data generated from the digital filter 202 with a Q channel decision region corresponding to the calculated slope and generates a limited Q channel region decision signal. An OR gate 216 receives the I and Q channel region decision signals generated from the first and second region limiters 212 and 214. A MUX 218 receives the symbol data generated from the decider 210 and the delayed I channel data and selectively generates one of the input signals in response to the region decision signal generated from the OR gate 216. A subtracter 220 subtracts a signal generated from the MUX 218 from the delayed I channel data to generate the decision error signal Ie. Figure 9 shows an operational waveform of Figure 7. Another preferred embodiment of the present invention will now be described with reference to Figures 7 to 9. The digital filter 202 shown in Figure 7 recovers the Q channel sign data from the input I channel data. The delayer 200 delays the input I channel data for the filtering time of the digital filter 202. The reference signal interval processor 204 detects the reference signal pulse for detecting the slope from the I channel data and supplies the reference signal pulse to the estimation and adaptive decision error detector 206 and the slope detector 208. The estimation and adaptive decision error detector 206 decides the I channel symbol data and generates the decision error signal Ie. In the estimation and adaptive decision error detector 206 of Figure 7, the first region limiter 212 compares the I channel data with the decision region to limit the I channel decision region. If the I channel data is within the range of the limited region, the region limiter 212 generates "0". If the I channel data is beyond the range of the limited region, the region limiter 212 generates "1". The second region limiter 214 compares the Q channel data generated from the digital filter 202 with the decision region to limit the Q channel decision region. If the Q channel data is within the range of the limited region, the second region limiter 214 generates "0", and if not, it generates "1". The I and Q channel decision region limit signals generated from the first and second region limiters 212 and 214 are supplied to the OR gate 216. The output of the OR gate 216 is applied to the select terminal of the MUX 218. The decider 210 decides the symbol value of the I channel data to the setting reference level. If there are 8 levels and if the I channel data is between 0 and 2, the decision output is "1". In case of a boundary portion, for example, 2, 4 or 6 etc., the same rule of rounding it up or down is applied. The MUX 218 selectively generates either the decision signal decided from the decider 210 or the I channel data in response to signals generated from the first and second region limiters 212 and 214. Therefore, if the output signals of the first and second region limiters 212 and 214 are "1", the MUX 218 generates the I channel data since the input signals of the first and second region limiters 212 and 214 do not exist within the range of the limited region. The subtracter 220 subtracts the I channel data of the same input signal from the I channel data to generate the decision error signal Ie of "0". Meanwhile, the outputs of the first and second region limiters 212 and 214 are "0", the MUX 218 generates the output signal of the decider 210 since the input signals of the first and second region limiters 212 and 214 are within the range of the limited region corresponding to the calculated slope. The subtracter 220 subtracts the decision signal decided to the setting reference level from the I channel data to generate the decision error Ie. The slope detector 208 calculates the slope value a by the above equations (1), (2) and (3) with respect to the levels +S and -S while the reference signal pulse is detected from the reference signal interval processor 204. If the detected interval of the reference signal interval is over, the decision region for detecting the decision error by the estimation and adaptive decision error detector 206 is limited as shown in Figure 9. Until the next reference signal is received, the estimation and adaptive decision error detector 206 operates with the fixed slope. The decision region is limited according to the calculated slope as shown in Figure 9. The input signal beyond the range of the decision region is not used. It is preferable to limit the decision region by not only the I channel but also the Q channel since an actual channel circumstance has an effect on both the I and Q channels. Therefore, the decision region of the I and Q channels is limited according to the slope obtained by the slope detector 208 as shown in Figure 9. In a related circuit, when calculating the slope a from the random signal, the reference signal interval processor 204 may use the interval signal pulse generator, and the slope is calculated by using all the random data. In the above embodiments of the present invention, the Q channel data is calculated from the I channel data to adaptively limit the region for deciding the digital data. However, the digital data can be directly decided from the I channel data and the Q channel data separated from the received data. In this case, the decision error can be obtained by limiting the region for calculating the digital data without the delayers 100 and 200 and the digital filters 102 and 202 used in Figures 3 and 7. As described above, in order to improve the accuracy of the decision error, a signal error is detected by the slope. The region for calculating the decision error is adaptively limited on the basis of the slope. Therefore, a reliable decision error can be obtained. When using the coding for the Q channel data, the phase error can be obtained only by the direction without estimating an accurate Q value. Consequently, the accurate digital filter is not demanded and the hardware construction of the digital filter can be simplified. Furthermore, the accurate decision can be given by limiting the decision region of the I and Q channel values. It should be understood that the present invention is not limited to the particular embodiment disclosed herein as the best mode contemplated for carrying out the present invention, but rather that the present invention is not limited to the specific embodiments described in this specification except as defined in the appended claims.

Claims: A circuit arranged to adaptively calculate a decision error of a digital signal by limiting a decision error region in a digital modulation system, said circuit comprising: an estimation and adaptive decision error detector (106,206) arranged to receive an I channel signal, identify symbol data according to a detected phase error and adaptively generate a decision error signal; a slope detector (108,208) arranged to receive the decision error signal generated from the estimation and adaptive decision error detector (106,206), to receive a Q channel signal, to detect the phase error, and to generate an accumulated phase error; and characterised by : a reference signal interval processor (104,204) arranged to receive the I channel signal and generate a reference signal pulse only during the reception of a reference signal received in the I channel signal, wherein the estimation and adaptive decision error detector (106,206) is arranged to receive the I channel signal and adaptively generate a decision error signal during a detected interval of the reference signal pulse, and wherein the slope detector (108,208) is arranged only to detect the phase error and generate an accumulated phase error during the detected interval of the reference signal pulse. The circuit as set forth in claim 1, comprising: a digital filter (102) arranged to Hilbert transform filter the I channel signal to generate a Q channel signal which differs in phase from said I channel data; a delayer (100) arranged to delay said I channel signal for a filtering time of the digital filter (102); and wherein the estimation and adaptive decision error detector (106) is arranged to receive the I channel signal delayed from the delayer (100) during the detected interval of the reference signal pulse, and the slope detector (108) is arranged to receive the Q channel signal generated by the digital filter (102). The circuit as set forth in claim 1 or 2, wherein the slope detector (108) detects a slope a by the following equations: Ie = I' - I'' where I' is an input signal, I" is a symbol data value of a decision result, Ie is a decision error signal, and N is the number of symbols within the detected interval of said reference signal pulse. The circuit as set forth in claim 1, 2 or 3, wherein the estimation and adaptive decision error detector (106) includes: a decider (110) arranged to receive the I channel signal delayed from the delayer (100) and identify symbol data by comparison to a reference level value; a region limiter (112) arranged to compare the I channel signal delayed from the delayer (100) with a decision region corresponding to the detected phase error and to generate a limited region decision signal; a multiplexer (114) arranged to receive the symbol data decided from the decider (110) and the delayed I channel signal, and selectively output either the symbol data decided from the decider (110) or the delayed I channel signal according to the limited region decision signal generated by said region limiter (112); and a subtracter (116) arranged to subtract a signal generated from said multiplexer (114) from the delayed I channel signal to generate the decision error signal. The circuit as set forth in claim 1, comprising: a digital filter (202) arranged to digitally filter the I channel signal to generate Q channel sign signal which differs in phase from said I channel data; a delayer (200) arranged to delay said I channel signal for a filtering time of the digital filter (202); and wherein the estimation and adaptive decision error detector (206) is arranged to receive the Q channel sign signal and the I channel signal delayed from the delayer (200) during the detected interval of the reference signal pulse, and the slope detector (208) is arranged to use only the Q channel sign signal generated by the digital filter (202). The circuit as set forth in claim 1, wherein the estimation and adaptive decision error detector (106,206) is arranged to receive Q channel sign signal during the detected interval of the reference signal pulse, and, the slope detector (108,208) is arranged to use only Q channel sign signal. The circuit as set forth in claim 5 or 6, wherein said estimation and adaptive decision error detector (206) includes: a decider (210) arranged to receive the I channel signal delayed from the delayer (200) and identify symbol data by comparison to a reference level value; a first region limiter (212) arranged to compare the I channel signal delayed from the delayer (200) with an I channel decision region corresponding to the detected phase error, and to generate a limited I channel region decision signal; a second region limiter (214) arranged to compare the Q channel sign signal generated from said digital filter (202) with a Q channel decision region corresponding to the detected phase error, and to generate a limited Q channel region decision signal; a logic gate (216) arranged to OR said limited I and Q channel region decision signals generated from said first and second region limiters (212, 214); a multiplexer (218) arranged to receive the symbol data generated from said decider (210) and said delayed I channel signal and selectively output either the symbol data generated from said decider (210) or the delayed I channel signal according to a region decision signal generated from the logic gate (216); and a subtracter (220) arranged to subtract a signal generated from the multiplexer (218) from the delayed I channel signal to generate the decision error signal. The circuit as set forth in claim 5, 6, or 7, wherein the slope detector (208) detects a slope a by the following equations: Ie = I' - I'' where I' is an input signal, I" is a symbol data value of a decision result, Ie is a decision error signal, N is the number of symbols within the detected interval of said reference signal pulse, and sgn(Q) is Q channel sign signal. A method for adaptively calculating a decision error of a digital signal by limiting a decision error region in a digital modulation system, the method comprising the steps of: receiving an I channel signal, identifying symbol data according to a detected phase error and generating a decision error signal; generating an accumulated phase error according to the decision error signal and a received Q channel signal; the method being characterised by : generating a reference signal pulse only during the reception of a reference signal received in the I channel signal, identifying symbol data according to a detected phase error and generate a decision error signal during a detected interval of the reference signal pulse, and, generating the accumulated phase error generated only during the detected interval of the reference signal pulse. The method as set forth in claim 9, wherein the step of receiving a Q channel signal comprises receiving only a Q channel sign data.

Inventors: LEE MYEONG-HWAN, LEE, MYEONG-HWAN
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1997
Main classification: H04L1
IPC codes: H04L1, H04L27, H04N7, H04N5, H04B7, H04L25