Apparatus for decoding variable length coded data

Abstract: An apparatus for decoding compressed image data which is variable length coded. In the apparatus, just a single segment memory (100) is used. An input data processor (10) counts the effective AC data and generates an address of where to write the AC data. An MR/VR flag write processor (12) counts all the MR/VR flags existing in one segment synchronous section stored in the segment memory (100) and generates an address of where to write MR/VR flags existing in the respective DCT blocks. An MR/VR flag memory (112) stores the address of where to write the MR/VR flag generated in the MR/VR flag write processor (12). An MR/VR flag read address generator (116) generates the address of from where to read the MR/VR flag stored in the MR/VR flag memory (112). An AC data read address generator (14) generates the address of from where to read the AC data stored in the segment memory (100) with reference to a start absolute address. A run/amplitude buffer (16) latches the run/amplitude data read from the segment memory (100). An address reducer (118) clears the latched run and amplitude data before the data of the next area is read, and reduces the address increased due to the run and amplitude in the case where the run does not exist and only amplitude data exists in the data read from the segment memory (100). A DCT block counter (124) counts the DCT blocks in order to find in which DCT block the MR/VR data latched in the run/amplitude buffer exist. A zero flag processor (18) controls a process of filling the data before the next DCT block to be latched. A run length decoder (130) run length decodes the data latched in the run/amplitude buffer.

Description: The present invention relates to an apparatus for decoding compressed image data, and more particularly, to an apparatus for decoding compressed image data which is variable length coded to be recorded or transmitted in a format having fixed area, macroblock remainder (MR) data and video segment remainder (VR) data. In digital video cassette recorders, one frame of picture is divided into a plurality of segments, each segment is divided into five macroblocks. Also, each macroblock includes four DCT blocks for luminance signal and two DCT blocks for color difference signal. A code whose length exceeds the length of the specified fixed area as a result of the variable length coding is called a macroblock remainder (MR). The MR is recorded in the blank area of another DCT block which belongs to the same macroblock. Data remaining after being recorded in the blank area of the other DCT block is video segment remainder (VR) data. The VR data is recorded in the blank area of another macroblock which belongs to the same segment. Any code remaining after being recorded in the blank area of the other macroblock is thrown away. This is because a video segment whose length is fixed is processed independently of other segments during the coding. During the decoding of compressed data of the video segment unit recorded as above, fixed data of a DCT block unit is completely decoded, first. Then, the MR data and the VR data are decoded if they exist. EP-A-0727907 discloses the decompression of compressed video data which are stored on a tape as a plurality of segments which can be decompressed independently. Each segment comprises a plurality of macroblocks having a plurality of DCT blocks. Code data which exceed the length of the fixed area available for recording respective DCT blocks are stored in available blank areas of other DCT blocks belonging to the same macro block. Remaining code data are stored in blank areas of another macroblock belonging to the same segment. However, in a conventional decoding apparatus, two memories for storing compressed data to be decoded are required so that data of a segment unit which is being processed at present is stored in one memory and data of a segment unit to be processed next is stored in the other memory. Therefore, hardware costs increase since two segment memories are used. It is an aim of preferred embodiments of the present invention to provide an apparatus for storing effective fixed data, MR data and VR data of a segment unit and an end flag which indicates the end of the respective data in a memory, for decoding data of a fixed area of a DCT unit, for reading compressed data stored in a memory, using an MR/VR flag which shows whether there is continuous MR/VR data, and for run length decoding the compressed data. The aim is achieved by the apparatus specified in appended claim 1. Preferably, said input data processor comprises an A/C data write address generator and an input truncating portion, the A/C data write address generator being arranged to count the effective A/C data to write to the segment memory and to generate the address for writing the counted A/C data, and the input truncating portion being arranged to convert input data into data of a predetermined bit length and output said predetermined bit length data to the segment memory. Preferably, said MR/VR flag write processor comprises an MR/VR flag counter for counting all the MR/VR flags existing in one segment sync period stored in the segment memory and an MR/VR flag write address generator for generating the address to write the MR/VR flags existing in respective DCT blocks among the MR/VR flags counted by the MR/VR flag counter . Preferably, the AC data read address generator includes a start absolute address buffer for storing the start addresses of a fixed area, the MR area, and the VRM area which are to be read first from the segment memory and an AC data read address generator for receiving the absolute address from the start absolute address buffer and generating an address for reading the AC data stored in the segment memory. Preferably, the run/amplitude buffer includes a run buffer for latching the run data read from the segment memory and an amplitude buffer for latching the amplitude data read from the segment memory. Preferably, the zero flag processor comprises a flag mode portion for determining the presence of the MR/VR data in the DCT block which is latched in the MR/VR flag memory and a zero flag portion for controlling a processor filling the data before the next DCT block is latched with bits having a "zero" value when the MR/VR flags are determined not to exist by the flag mode portion. For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figure 1 is a block diagram of a decoding apparatus according to an embodiment of the present invention; Figure 2A shows the data input to a segment memory shown in Figure 1; Figure 2B shows the format of data stored in the segment memory shown in Figure 1; Figure 3 describes a case in which run exists in data input to a run/amplitude buffer shown in Figure 1; Figure 4 describes a case in which run does not exist in the data input to the run/amplitude buffer shown in Figure 1; and Figure 5 describes the operation of a zero flag portion shown in Figure 1. Figure 1 shows a decoding apparatus according to a preferred embodiment of the present invention. The decoding apparatus includes a segment memory 100, an input data processor 10, an MR/VR flag write processor 12, an MR/VR flag memory 112, an MR/VR flag read address generator 116, an AC data read address generator 14, a run amplitude/buffer 16, an address reducer 118, a DCT block counter 124, a zero flag processor 18 and a run length decoder 130. The segment memory 100 stores input data of a fixed area of one segment unit and MR and VR areas, an end flag, and an address corresponding thereto, and continuously stores data of another segment unit which is continuously input. The input data processor 10 counts the effective AC data to write such data to the segment memory 100, generates an address for writing the AC data, processes input data, and outputs the processed data to the segment memory. The input data processor 10 includes an AC data write address generator 102 for counting the effective AC data to write to the segment memory 100 and generating the address for writing the counted AC data, and an input truncating portion 104 for converting input data (the AC data, the DC data, and the end flag) into 18-bit data and outputting them to the segment memory 100. The MR/VR flag write processor 12 counts all the MR/VR flags which exist in one segment synchronous section and are stored in the segment memory 100 and generates an address for writing the MR/VR flags which exist in the respective DCT blocks. The MR/VR flag write processor 12 includes an MR/VR flag counter 106 for counting all the MR/VR flags existing in one segment sync period stored in the segment memory 100, and an MR/VR flag write address generator 108 for generating the address to write the MR/VR flags existing in the respective DCT blocks among the MR/VR flags counted by the MR/VR flag counter 106. The MR/VR flag memory 112 stores the MR/VR flags generated by the MR/VR flag write processor 12 and an address for writing the MR/VR flags. The MR/VR flag read. address generator 116 generates an address for reading the MR/VR flags stored in the MR/VR flag memory 112. The AC data read address generator 14 generates an address for reading AC data stored in the segment memory 100 with reference to a start absolute address. The AC data read address generator 14 includes a start absolute address buffer 110 for storing the start addresses of a fixed area, the MR area, and the VR area which are to be read first from the segment memory 100, and an AC data read address generator 114 for receiving the absolute address from the start absolute address buffer 110 and generating an address for reading the AC data stored in the segment memory 100. The run/amplitude buffer 16 latches the run/amplitude data read from the segment memory 100. The address reducer 118 clears the latched run and amplitude before reading data of the next area and reducing the address increased by the run and amplitude when run does not exist and only amplitude data exist in the data read from the segment memory 100. The run/amplitude buffer 16 includes a run buffer 120 for latching the run data read from the segment memory 100, and an amplitude buffer 122 for latching the amplitude data read from the segment memory 100. The DCT block counter 124 counts DCT blocks in order to find which DCT block includes the MR/VR data latched in the run/amplitude buffer 16 among the MR/VR flags counted by the MR/VR flag write processor 12. The zero flag processor 18 controls a process of filling the data before the next DCT block is latched with bits having a "0" value when the MR flag or the VR flag does not exist as a result of determining the presence of the MR/VR data in the DCT block which is being latched in the MR/VR flag memory 112. The zero flag processor 18 includes a flag mode portion 126 for determining the presence of the MR/VR data in the DCT block which is latched in the MR/VR flag memory 112, and a zero flag portion 128 for controlling a process of filling the data before the next DCT block is latched with bits having a "0" value when the MR/VR flags are determined not to exist by the flag mode portion 126. The run length decoder 130 run length decodes the data latched in the run/amplitude buffer 16 and fills the data before the next DCT block with "0" under the control of the zero flag processor 18. The detailed operation of the apparatus shown in Figure 1 is as follows. Figure 2A shows the pattern of data input to the segment memory 100 shown in Figure 1. Figure 2B shows the format of data stored in the segment memory 100. The run and amplitude data shown in Figure 2A, which is effective data, are stored in the segment memory 100 at the address generated by the AC data write address generator 102 for receiving an AC flag. The end flags are recorded on the respective ends of the fixed area, the MR area and the VR area in order to indicate the end of each data. Also, an MR_PRC and a VR_PRC are signals for showing the effective sections of the MR area and the VR area, and a DC flag is a signal showing the start of a DCT block. As shown in Figure 2B, the segment memory 100 is a memory of a size such that some space remains after data of one segment unit is stored. Data of other segments is continuously stored in the space remaining after the effective data of one segment unit is stored. Therefore, it is possible to reduce the hardware costs by using one segment memory unlike in a conventional decoding apparatus in which two segment memories are used. Data output by the input truncating portion 104 includes a DC data of 9 bits, a mode data of 1 bit, a CLASS data of 2 bits, a QNO data of 4 bits, a DC-flag, and an end flag when the DC-flag is low, while the data includes a dummy bit, a run data of 6 bits, an amplitude data of 9 bits, the DC-flag, and the end flag when the DC-flag is high. A start absolute address buffer 110, which stores the start address of the fixed area, the MR area and the VR area, includes two buffers for storing the absolute address of the segment memory which is processed at present and the absolute address to be recorded, respectively. When the data read from the segment memory 100 by the AC data read address generator 114 is latched to the run/amplitude buffers 120 and 122, the run/amplitude buffers 120 and 122 hold the address, count the run, and increase the address when the run exists (namely, when the run is not 0). At this time, an address hold signal is output to the AC data read address generator 114. The AC data read address generator 114 reads data stored in the segment memory 100 using the absolute address of the first fixed area. Then, the AC data read address generator 114 jumps to the absolute address of the MR/VR area depending on the presence of the MR/VR flag read from the MR/VR flag memory 112 by the MR/VR flag read address generator 116, and reads the MR data at the corresponding address stored in the segment memory 100 using the absolute address of the MR area. At this time, the absolute address of the fixed area is updated immediately before being changed to the address of the MR area. The above processes are performed when the processing is changed from the MR area to the VR area. Through the above processes, only fixed data, or the fixed data and the MR data, or the fixed data and the VR data, or the fixed data, the MR data and the VR data can exist in the data decoded by the run length decoder 130. The run/amplitude buffers 120 and 122 store the data read from the segment memory 100 according to the state of the data, using 4 internal buffers. At this time, new data from the segment memory 100 is stored in the respective buffers according to the address change. The absolute address reducer 118 processes the data of the fixed area when the run exists in the data of the fixed area read from the segment memory 100, and latches the data of the increased address before the address hold signal reaches the AC data read address generator 114 when the data of the MR area or the VR area are processed. For example, when the address is changed from the fixed area to the MR area or from the fixed area to the VR area, one undesired data unit of the next fixed area is read and then the address is changed to the MR area or the VR area. Such a case is shown in Figure 4. The DC, the amplitude data 32 and the run data 1 shown in Figure 4 are negligible. At that time, the address reducer 118 reduces already increased address and removes the redundant run that is generated by use of a DEL flag. As shown in Figure 5, the zero flag portion 128 commands the run length decoder 130 to fill the data before the next DCT block with bits having a "0" value when the flag mode portion 126 determines that the MR flag or the VR flag does not exist. The run length decoder 130 fills the data before the next DCT block with bits having a "0" value under the control of the zero flag portion 128 and run length decodes the data latched in the run/amplitude buffers 120 and 122.

Claims: A decoding apparatus for decoding compressed image data which is variable length coded and recorded or transmitted in segment units, each segment unit comprising a fixed area, a macro block remainder area MR and a video segment remainder area VR, the decoding apparatus comprising: a segment memory (100) for storing the data of the fixed area, the data of the area MR and the area VR of an input one segment unit, an end flag, and an address corresponding thereto and continuously storing data of other segment units which are input; an input data processor (10) for counting the effective AC data to be written to said segment memory (100), generating an address of where to write the AC data, processing input data, and outputting the input data to said segment memory (100); an MR/VR flag write processor (12) for counting all the MR/VR flags existing in a [one] segment synchronous section stored in said segment memory and generating an address of where to write in said segment memory MR/VR flags existing in the respective DCT blocks; an MR/VR flag memory (112) for storing the address of where to write the MR/VR flag generated in said MR/VR flag write processor (12); an MR/VR flag read address generator (116) for generating the address of from where to read the MR/VR flag stored in said MR/VR flag memory (112); an AC data read address generator (14) for generating the address of from where to read the AC data stored in said segment memory (100), with reference to a start absolute address; a run/amplitude buffer (16) for latching [the] run/amplitude data read from said segment memory (100); an address reducer (118) for clearing the latched run and amplitude data before the data of the next area is read, and for reducing the address increased due to the run and amplitude in the case where the run does not exist and only amplitude data exists in the data read from said segment memory (100); a DCT block counter (124) for counting the DCT blocks in order to find in which DCT block the MR/VR data latched in the run/amplitude buffer exist, among the MR/VR flags counted by said MR/VR write processor (12); a zero flag processor (18) for controlling a process of filling the data before the next DCT block to be latched, with bits having a "0" value, when the MR flag or the VR flag does not exist as determined by the presence of the MR/VR data, in the DCT block which is currently latched, in said MR/VR flag memory (112); and a run length decoder (130) for run length decoding the data latched in said run/amplitude buffer (16), and decoding the data before the next DCT block is decoded by filling the data according to the control of said zero flag processor (18). An apparatus according to claim 1, wherein said input data processor (10) comprises an A/C data write address generator (102) and an input truncating portion (104), the A/C data write address generator (102) being arranged to count the effective A/C data to write to the segment memory (100) and to generate the address for writing the counted A/C data, and the input truncating portion (104) being arranged to convert input data into data of a predetermined bit length and output said predetermined bit length data to the segment memory (100). An apparatus according to claim 1 or 2, wherein said MR/VR flag write processor (12) comprises an MR/VR flag counter (106) for counting all the MR/VR flags existing in one segment sync period stored in the segment memory (100) and an MR/VR flag write address generator (108) for generating the address to write the MR/VR flags existing in respective DCT blocks among the MR/VR flags counted by the MR/VR flag counter (106). An apparatus according to claim 1, 2 or 3, wherein the AC data read address generator (14) includes a start absolute address buffer (110) for storing the start addresses of a fixed area, the area MR, and the area VR which are to be read first from the segment memory (100) and an AC data read address generator (114) for receiving the absolute address from the start absolute address buffer (110) and generating an address for reading the AC data stored in the segment memory (100). An apparatus according to any of claims 1 to 4, wherein the run/amplitude buffer (16) includes a run buffer (120) for latching the run data read from the segment memory (100) and an amplitude buffer (122) for latching the amplitude data read from the segment memory (100). An apparatus according to any of claims 1 to 5, wherein the zero flag processor (18) comprises a flag mode portion (126) for determining the presence of the MR/VR data in the DCT block which is latched in the MR/VR flag memory (112) and a zero flag portion (128) for controlling a processor filling the data before the next DCT block is latched with bits having a "zero" value when the MR/VR flags are determined not to exist by the flag mode portion (126).

Inventors: JEON JONG-GU, JEON, JONG-GU
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1997
Main classification: H04N7
IPC codes: H04N7, G06T9, H03M7, H04N5