METHOD IN CONNECTION WITH SERIAL DATA TRANSFER TO RECOGNIZE A FIXED PATTERN

Abstract: The present invention relates to a method in connection with serial data, to recognize a frame synchronization pattern, and for the sake of providing a fast and reliable search algorithm especially for V.110 synchronization pattern, the present invention suggests a method characterized by examining two successive bytes by performing a binary AND operation between the first byte and a check byte made up from the value of the second byte, examining if the AND operation is zero for thereby establishing whether said first byte and second byte qualify as candidates for the synchronization pattern, and further verifying said candidates by checking further criteria given by the frame in question.

Description: METHOD IN CONNECTION WITH SERIAL DATA TRANSFER TO RECOGNIZE A FIXED PATTERN Field of the invention The present invention relates to a method in connection with serial data transfer to recognize a fixed synchronization bit pattern. Although the present invention has been developed in connection with the V.110 protocol, it is to be understood that the general principle of the invention can also find its application in connection with similar systems . Background of the invention For serial data transfer with rate adaption a commonly used protocol is the V.110. When developing equipment for this protocol one will be faced to the problem of how to recognize the V.110 frame synchronization pattern. One can choose to solve it either in hardware, software or by a combination of both hardware and software. Often the hardware solution is preferred because the software al- ternative is considered to take too much of the CPU-capacity. However, with the present algorithm the sync-detection is quite easy to handle in software. Compared to the rest of the V.110 processing that usually is done in software, this extra load is very small. Before the present method or algorithm is described, reference should be made to Fig. 1 illustrating how the 80 bits V.110 frame appears. Octet zero contains all binary 0, whilst octet 5 consist of binary 1 followed by seven E bits. Octets 1-4 and 6-9 contain a binary 1 in bit number one, a status bit (S- or X-bit) in bit number 8 and six data bits (D-bits) in bit positions 2-7. The order of bit transmission is from left to right and top to bottom. The 17 frame synchronization bits (*) consist of all eight bits set to binary 0 in octet zero and a binary 1 in bit position 1 in the following nine octets. Through this document special attention should be focused on these synchronization bits (*). At a first glimpse the finding of the synchronization pattern may be considered as quite easy. This would, it is true, obviously be easy if the ten octets always arrive byte-aligned in the computer memory in question. But here is where the problem starts. When the serial bit stream "ticks" into the receive-buf- fer in the computer memory, one has no guarantee that the octets in the frame fall into corresponding byte- addressable locations. Fig. 2 illustrates how odd the serial bit stream may arrive in a byte-addressable computer memory store. Consequently, the V.110 frame octets included in the bit stream appearing in Fig. 2 will not necessarily be byte- aligned as compared with Fig. 1. Hence, each octet may be split between or partly cover two consecutive addresses as regards byte-alignment. Prior Art From US patent publication 5 204 883 (Blanc) there is known a method and an apparatus for recognition of a framing pattern distributed in a serial bit stream. The framing pattern comprises single bits distributed at intervals of a fixed number, N of bits, as measured from the start of one framing bit to the start of the next, in an incoming serial bit stream. The prior art system makes a computation following each reception of an arbitrary group of N incoming data, and will after a minimum number of computation steps to distinguish between a ' look alike' framing pattern and a 'true' framing pattern, point out with no ambiguity the very position of the 'true' pattern within the bit stream, thus allowing synchronization over that stream. This prior art describes a method for synchronizing in relation to a bit pattern, wherein each individual bit in the pattern is distributed with randomly arranged user data therebetween. However, this prior art technique is silent about finding a bit pattern which is not "bit-distributed", and would consequently not be able to use for the recognition of such bit patterns. US patent publication 5 177 738 (Dell'Oro et al . ) discloses a process and a monolithically integrated device for speed adaption for integrated services digital networks (ISDN), which process relates to synchronizing and decomposing asynchronous data frames of different lengths of a serial bit stream structured in octet-rows of bits containing frame synchronization bits and data bits, for rate adaption of synchronous and asynchronous terminals of said ISDN during data reception from said network. EP 0 727 886-A2 (Anderson/Wandel & Golterman Technologies Inc.) discloses a method related to digital data sequence pattern filtering, which method is octet/byte oriented. In practice this will involve that the method is operated on a byte stream, and that a byte alignement can be assumed. However, this prior art does not give any instructions about a method related to a bit stream, let alone any solution to the problem enfaced with not being byte aligned in relation to the bit pattern to be recognized. US 5 412 754 (Newley et al . ) relates to a pattern recognizing system, comprising a transmitter and receiver for transmitting and receiving a serial stream of bits that includes data bits and a predetermined bit pattern, the system being adapted for recognizing said bit pattern. The system checks each received bit and compares this with the state value of previous bits until the predetermined bit pattern is recognized. This system is a slow system since it requires a comparison or checking operation for each received bit. In other words, this system is silent about conducting a comparison or checking operation only for each 8th received bit. US 5 412 610 (Suzuki) relates to a serial data transfer device, wherein serial data are transfered to/from an FIFO buffer. However, there is no information in this publication concerning how a special bit pattern can be recognized in such a buffer, for example data which have been received from a serial communication link. In conclusion, none of the cited references give any instructions regarding how to recognize a synchronization pattern in a frame according to V.110 protocol, let alone that this recognition can be effected by a fast search algorithm for such V.110 synchronization pattern. Summary of the invention The main object of the present invention is to provide a fast search algorithm for V.110 synchronization pattern. It is also an object of the invention to provide a fast search algorithm for a FAX application in which the aim is to recognize eleven zeros (0) followed by a single one (1) in a bit stream (known as EOL, i.e. End-Of-Line) . Another object of the present invention is to provide an appropriate CheckBitMaskTable to be used in connection with such a fast search algorithm. A further object of the present invention is to provide an algorithm in which two arbitrary bit groups or bytes are compared with each other and the result thereof compared with further criteria given by the V.110 frame. Still another object of the present invention is to provide an algorithm which is easy to handle in software, and which represents only a very small load compared with the related processing in software. Yet another object of the invention is to provide an algorithm for finding a bit pattern which is not bit distributed. A still further object of the invention is to provide an algorithm conducting a comparison or checking operation only for each 8th received bit in a bit stream and thereby increasing the speed at which the algorithm can operate . Brief disclosure of the invention The above objects are achieved in connection with a method as stated in the preamble, which according to the invention is characterized by examining two successive elements, by performing a binary AND operation between the first element and a check element made up from the second element, then examining if the binary AND operation is zero for thereafter establishing whether said first element and second element qualify as candidates for the synchronization pattern, and further verifying said candidates by checking further criteria given by the frame in question. Further features and advantages given by the present invention will appear from the following description taken in conjunction with the enclosed drawings and appendices, as well as from the enclosed patent claims. Brief disclosure of the drawings and appendices Fig. 1 shows the layout of a 80 bits CCITT V.110 frame. Note the bit numbering scheme used as compared to Fig.2. When referring octets in V.110 frames the bits are nor- mally numbered 1 through 8 from left to right . The bits in a byte are numbered 0 through 7 starting from right to left as in Fig. 2. The asterisks (*) mark out the frame synchronization bits. Fig. 2 is a table illustrating the arbitrary serial bit stream as it may have been received into a buffer in a computers memory. Note the asterisks (*) and how odd the octets are aligned with respects to the byte addressable buffer. Appendix A illustrates an embodiment of a table which can be used to generate the check value used in connection with the method according to the invention. Appendix B is a print out of a computer program which can be used for realizing the method according to the present invention. Detailed description of embodiments of the invention As explained previously in connection with Fig. 1, a V.110 frame synchronization pattern appears as 80 bits, one frame always starting with 8 zero (0) bits followed by a one (1) bit. As illustrated in Fig. 2 the serial bit stream may have a sequential but arbitrary position in the byte-addressable locations, and an embodiment of the present method will be explained in connection with such an arbitrary location in a buffer/array. While still referring to Fig. 2 the following assumptions should be observed. The received bit stream is stored in a byte-addressable buffer/array. The bytes in the buffer are filled from left to right when the bits are ticking in from the serial line, it here being assumed that the most significant bits (MSB) are received first. However, the least significant bits (LSB) can be used as well, but the check byte (explained later) would then have to be mirrored. When the above assumptions are fulfilled, an embodiment of the present invention may comprise the following steps for each received byte to be examined: 1. Check the byte in question by doing a binary AND operation between the examined byte and a special check byte. The check byte is to have the same number of leading zero bits as there are leading zero bits in the byte that follows the byte in question. The rest of the bits in this check byte has to be set to ones (1 ' s) . 2. If the result of the AND operation is zero and the byte that follows the byte in question is not zero itself, then 8 consecutive zero (0) bits followed by at least one one (1) bit have been found. The following example making references to Fig.2 may better explain how it works. During the example the notation byteO, bvtel , bvte2 and so on refer to the bytes at respective memory offset 0, 1, 2 and so on: If byteO should be a candidate for the start of the eight consecutive zero bits, bit bO through b5 have to be zero since bvtel that follows byteO contains only 2 leading zero bits (b7 and b6). A binary AND with byteO and a byte that has only 2 leading zeros and the rest of the bits set to ones (1's), will give result zero if byteO is a candidate: 01010000 AND 00111111 = 00010000 non-zero result- > bvteO is not a candidate If bytel should be a candidate for the start of the eight consecutive zero bits, bit bO through b3 have to be zero since byte2 contains four leading zero bits (b7 through b4). A binary AND with bvtel and a byte that has four leading zeros and the rest of the bits set to ones (1's), will give result zero if bytel is a candidate: 00110000 AND 00001111 00000000 zero result-> bytel is a candidate Eight consecutive zero (0) bits have been found. The first four are found in bvtel bit b3-b0 and the rest follow in the byte2 bit b7-b4. Since byte2 is non-zero the first sync bit that is set (bit 8 in octet 1 fig.1) must be contained in byte2 at bit position b3. But since b3 is not set in all eight bytes bvte3 ..byteδ, bytel can not be part of the sync pattern, thus continue checking bvte2. The binary AND with byte2 and a byte that has 8 leading zeros (same number of leading zeros as in byte3 ) will always give zero result, but since byte3 is zero itself the 8 consecutive zero bits followed by a one (1) bit can not start within byte2, thus byte2 is discarded too. Continuing binary AND'ing byte3 with a byte that has 2 leading zeros (same number of leading zeros as in byte4) give zero result, thus we must check the remaining ones (1) sync bits. Since first leading one (1) bit in byte4 is found at bit position b5, bit b5 has to be checked in the remaining bytes byte5..bytel 2. Since such b5 positions are all set in these bytes, a valid start has been found . Appendix B shows a C-implementation of the algorithm above. Appendix A (1/4) CheckBitMaskTable Entry Binary Entry Binary number contents number contents 000 00000000 032 00111111 001 0000000 033 00111111 002 000000 034 00111111 003 000000 035 00111111 004 000001 036 00111111 005 000001 037 00111111 006 000001 038 00111111 007 000001 039 00111111 008 000011 040 00111111 009 000011 041 00111111 010 000011 042 00111111 011 000011 043 00111111 012 000011 044 00111111 013 000011 045 00111111 014 000011 046 00111111 015 000011 047 00111111 016 000111 048 00111111 017 000111 049 00111111 018 000111 050 00111111 019 000111 051 00111111 020 000111 052 00111111 021 000111 053 00111111 022 000111 054 00111111 023 000111 055 00111111 024 000111 056 00111111 025 000111 057 00111111 026 000111 058 00111111 027 000111 059 00111111 028 000111 060 00111111 029 000111 061 00111111 030 000111 062 00111111 031 000111 063 00111111 continue on next page.. Appendix A ( 2/4 ) . CheckBitMaskTable continue Entry Binary Entry Binary number contents number contents 064 01111111 096 01111111 065 01111111 097 01111111 066 01111111 098 01111111 067 01111111 099 01111111 068 01111111 100 01111111 069 01111111 101 01111111 070 01111111 102 01111111 071 01111111 103 01111111 072 01111111 104 01111111 073 01111111 105 01111111 074 01111111 106 01111111 075 01111111 107 01111111 076 01111111 108 01111111 077 01111111 109 01111111 078 01111111 110 01111111 079 01111111 111 01111111 080 01111111 112 01111111 081 01111111 113 01111111 082 01111111 114 01111111 083 01111111 115 01111111 084 01111111 116 01111111 085 01111111 117 01111111 086 01111111 118 01111111 087 01111111 119 01111111 088 01111111 120 01111111 089 01111111 121 01111111 090 01111111 122 01111111 091 01111111 123 01111111 092 01111111 124 01111111 093 01111111 125 01111111 094 01111111 126 01111111 095 01111111 127 01111111 continue on next page . . Appendix A ( 3/4 ) ...CheckBitMaskTable continue Entry Binary Entry Binary number contents number contents 128 11111111 160 129 11111111 161 130 11111111 162 131 11111111 163 132 11111111 164 133 11111111 165 134 11111111 166 135 11111111 167 136 11111111 168 137 11111111 169 138 11111111 170 139 11111111 171 140 11111111 172 141 11111111 173 142 11111111 174 143 11111111 175 144 11111111 176 145 11111111 177 146 11111111 178 147 11111111 179 148 11111111 180 149 11111111 181 150 11111111 182 151 11111111 183 152 11111111 184 153 11111111 185 154 11111111 186 155 11111111 187 156 11111111 188 157 11111111 189 158 11111111 190 159 11111111 191 continue on next page.. Appendix A ( 4/4 ) ...CheckBitMaskTable continue Entry Binary Entry Binary number contents number contents 192 11111111 224 193 11111111 225 194 11111111 226 195 11111111 227 196 11111111 228 197 11111111 229 198 11111111 230 199 11111111 231 200 11111111 232 201 11111111 233 202 11111111 234 203 11111111 235 204 11111111 236 205 11111111 237 206 11111111 238 207 11111111 239 208 11111111 240 209 11111111 241 210 11111111 242 211 11111111 243 212 11111111 244 213 11111111 245 214 11111111 246 215 11111111 247 216 11111111 248 217 11111111 249 218 11111111 250 219 11111111 251 220 11111111 252 221 11111111 253 222 11111111 254 223 11111111 255 Appendix B (1/3) /**************************************************************************** * * Routine: V110SyncSearch * * Description: Search through an array in order to find a correct V.110 * frame synchronization pattern. If routine return zero * an error free frame has been found. Note that RxSynBitPos * return bit positions within 1-8. 1 correspond to bit 0, SB * and 8 means bit 7 MSB within a byte. * Also note that this routine expects the serial stream to * fill the bytes from MSB towards LSB before moving to next * byte. That means MSB is sent/received first. * Input and output are passed using global variables. * * * Input: unsigned char RxDataStream[ ] Array containing received * bit stream * unsigned char *RxSyncByte Pointer where to start * searching * unsigned int BytesInRxDataStream Number of received bytes * Output: unsigned char *RxSyncByte Points at start of frame * if any found * unsigned char RxSyncBitPos Bit position within * RxSyncByte at where frame * begin if any found * unsigned int BytesInRxDataStream Number of bytes left in * serial stream * * * Return: = 0 Sync error-free frame found, RxSyncByte and * RxSyncBitPos tells where the frame is located * <> 0 : No start of frame found * * * Copyright : Ericsson AS * * Written: 1996-09-25 Bjoern Birkeland * * ***************************************************************************/ int V110SyncSearch(void) { /* Define look up table for V.11 0 synchronization search */ static const struct SYNCTEST_STR SyncTestTablef256] = { {0x00,0x08}, {0x01,0x01}, {Ox03,0x02}, {0x03 ,0x02}, {0x07,0x03}, {0x07,0x03}, {0x07,0x03}, {Ox07,0x03}, {OxOF,0x04}, {OxOF, 0x04}, {0x0F,0x04}, {0x0F,0x04}, {Ox0F,0x04}, {OxOF,0x04}, {OxOF, 0x04}, {0x0F,0x04}, {0x1F,0x05}, {Ox1F,0X05} {OxiF,0x05}, {0x1F,0x05}, {0X1F,0X05}, {0x1F,0x05}, {Ox1F,0X05}, {0x1F,0x05}, {0x1F,0x05}, {0X1F,0X05}, {0x1F,0x05}, {Ox1F,0X05}, {0x1F,0x05}, {0x1F,0x05}, {0X1F,0X05}, {0x1F,0x05}, {Ox3F,0x06}, {0x3F,0x06}, {0x3F,0x06}, {0x3F,0x06}, {0x3F,0x06}, {Ox3F,0x06}, {0x3F,0x06}, {0x3F,0x06}, Appendix B ( 2/3 ) 0x3F, 0x06} 0x3F, 0x06} 0x3F, 0x06} 0x3F, 0x06} 0x7F, 0x07} 0x7F, 0x07} 0x7F, 0x07} 0x7F, 0x07} 0x7F, 0x07} 0x7F, 0x07} 0x7F, 0x07} 0x7F, 0x07} 0x7F, 0x07} 0x7F, 0x07} 0x7F, 0x07} 0x7F, 0x07} Ox7F, 0x07} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} xFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} OxFF, 0x08} xFF, 0x08} xFF, 0x08} OxFF, 0x08} Appendix B (3/3) unsigned char *current_byte; unsigned char *next byte; unsigned char *tmp_Eyte; unsigned int sync errors; unsigned char chk_Eit; struct SYNCTEST_STR sync_test; current byte = RxSyncByte; do { sync_errors = 17; next byte = current_byte+1 ; /* cHeck for buffer-wrap around condition */ if (next byte > &RxDataStream[ RX_BUF_SIZE-1 ] ) { next Eyte = &RxDataStream[ 0 ]; } /* Look up check byte and bit position */ sync_test = SyncTestTablef *next_byte] ; /* Check current byte */ if /* Leave loop at first sync bit that is not set, or */ /* when sync_errors has counted down to zero */ } while( (*tmp_byte & ch_bit) && { —sync_errors) ) ; /* Did sync_errors reach zero? */ if ( ! sync_errors) { /* Yes, error free frame! Update new sync position */ /* and return with "no sync errors" */ RxSyncByte = current_byte; RxSyncBitPos = sync_test.bit_pos; return(sync errors) ; } } } current_byte = next_byte; } while (( —BytesInRxDataStream > V110_FRAME_SIZE) && sync_errors) ; return(sync_errors) ;

Claims: P a t e n t c l a i m s 1. Method in connection with serial data to recognize a fixed pattern, c h a r a c t e r i z e d b y - examining two successive elements by performing a bit operation between the first element and a check element computed from the second element, - examining the bit operation for thereafter establishing whether said first element and second element qualify as candidates for the pattern. 2. Method as claimed in claim 1 , c h a r a c t e r i z e d b y the following steps: - examining a first byte in a buffer/array in which a bit stream of said serial data has been received, - examining a second byte following said first byte, - computing a check byte based on said next byte, - performing a binary AND operation between values of said first byte and said check byte, - examining said AND operation to check whether 8 consecutive zero bits ('0's) are found, - examining the bit position of a first ' 1 ' bit in said second byte, - checking corresponding ' 1 ' bit positions in each remaining byte, respectively, to verify correct synchronization pattern. 3. Method as claimed in claim 1 or 2, c h a r a c t e r i z e d b y - examining two successive elements by performing an AND operation between the first element and a CheckBitMask for the second element. 4. Method as claimed in claim 1, 2 or 3, c h a r a c t e r i z e d b y the following steps: - initializing a first CurrentPtr to point at a first byte in a buffer, that might contain the start of a frame, - initializing a NextPtr to point at the next byte that follows the byte at which the CurrentPtr points, - using the value of the byte at which the NextPtr points, to look up the CheckBitMask from a CheckBitMaskTable array, - effecting a binary AND operation of the value of the byte at which the CurrentPtr points with the value of the CheckBitMask found in CheckBitMaskTable, and check whether result is zero, - if result is not zero, discard byte at which CurrentPtr points and advance said CurrentPtr to the next byte to be examined (set CurrentPtr = NextPtr), and advance NextPtr to the next byte in the buffer, - if more bytes exist in the buffer then use the value of the byte at which NextPtr points, else terminate search with no hit, - if NextPtr points at a zero byte then discard said byte, else check whether at least 8 consecutive zero bits (O's) followed by a one bit ('1') is found. 5. Method as claimed in claim 4, c h a r a c t e r i z e d i n checking whether the next eight bytes contain a one bit ( ' 1 ' ) at the same bit- position as the left-most one bit ( ' 1 ' ) in the byte at which the NextBytePtr points, for thereby verifying that a correct synchronization pattern has been found. 6. Method as claimed in any of the preceding claims, c h a r a c t e r i z e d b y using a CheckBitMaskTable having 256 entries, each of which containing a CheckBitMask which is a 8-bit wide pattern, and each entry containing a pattern made up of leading zero bits ('0'-bits) corresponding to leading zero bits ('O'-bits) in the entry's position number itself, whereas the rest of the entry's bits are set to one bit ('1'-bits), respectively. 7. Method as claimed in any of the preceding claims, c h a r a c t e r i z e d b y using a CheckBitMaskTable adapted to be used in connection with bit streams wherein the most significant bits (MSB) are received first. 8. Method as claimed in any of the preceding claims, c h a r a c t e r i z e d b y using a CheckBitMaskTable adapted to be used in connection with bit streams wherein the least significant bits (LSB) are received first.

Inventors: BIRKELAND BJOERN, BIRKELAND, BJOERN
Applicants: BIRKELAND BJOERN, ERICSSON TELEFON AB L M, BIRKELAND, BJOERN, TELEFONAKTIEBOLAGET LM ERICSSON
Application year: 1997
Main classification: G06F13
IPC codes: G06F7, H04J3, H04L7, H04L29