HIGH VOLTAGE LEVEL SHIFTING CMOS BUFFER

Abstract: A voltage level shifting complementary metal-oxide-silicon (CMOS) buffer (30-47) is arranged and configured to operate in two distinct modes - one of which is high voltage and the other low voltage - depending on the level of the supply voltage (40) to the buffer relative to the operating voltage (VDD) of a device in which the buffer is integrated. In the high voltage mode, in which the supply voltage level exceeds the operating voltage level, the buffer is constrained to perform as a high voltage level shifter. In the low voltage mode, in which the supply voltage level is equal to or less than the operating voltage level, the buffer is constrained to perform as a CMOS logic gate.

Description: HIGH VOLTAGE LEVEL SHIFTING CMOS BUFFER Cross-Reference to Related Applications This application is related to co-pending applications titled "Switched Ground Read for EPROM Memory Array" (U.S. Application Serial No. 08/723,927), "Voltage Reference Generator for EPROM Memory Array" (U.S. Application Serial No. 08/723,924), and "Overcharge/Discharge Voltage Regulator for EPROM Memory Array" (U.S. Application Serial No. 08/723,926), filed on the same day and assigned to the applicant, and the disclosures of which are incorporated herein by reference. Background of the Invention The present invention relates generally to buffer circuits which are useful across a wide voltage range, and more particularly to a high voltage level shifting CMOS buffer which has the capability to perform as a level shifter with shared breakdown in a high voltage mode and as a non-contending CMOS (complementary metal-oxide-silicon) logic gate in a low voltage mode. One application of a high voltage level shifting CMOS buffer according to the invention is in an erasable programmable read-only memory (EPROM) device. EPROM devices are fabricated using semiconductor process technology. As line widths are reduced in progression of the process technology it may be desirable not only to design and fabricate entirely new versions of products but to "shrink" or scale existing products to a smaller size with the new technology. This requires review and analysis of the design and architecture of the product and the manner in which the attempted scaling of its size may adversely affect its operation. The task presented is to shrink an EPROM product according to a new process technology, in a cost-effective and operation-feasible manner. In undertaking such a task for an EPROM program memory embedded in a microcontroller, for example, the scaling process imposes restrictions which, when coupled with the device requirements, makes the task extremely difficult. Some of the issues encountered in implementing a scaling process for such a device are wide voltage range, low program read margins, high speed, and low current. In particular, the read margins of the scaled EPROM are typically lower than the operating voltage range of the device. In a classic implementation of an EPROM array embedded in a microcontroller, the supply voltage of the microcontroller is used to control the EPROM memory element so as to enable reading of the data stored in the element. To read the data, a measurement of the programmed threshold voltage of the memory element is required. The memory element is said to be erased if the threshold voltage of the EPROM cell is low, and to be programmed if the threshold voltage is high. The cell is read by applying a voltage to the control gate of a transistor comprising the cell. If the applied voltage is higher than the threshold, current flows through the cell. The programming margin of the cell is the voltage difference between the maximum applied control gate voltage and the programmed threshold voltage of the programmed cell. A programmed EPROM cell will not conduct current when read by application of a control gate voltage of lower magnitude than the high threshold voltage of the cell. In most implementations, the control gate voltage used to read the memory array is the supply voltage of the system. If the programmed threshold of the memory cell is lower than the maximum value of that supply voltage, a programmed cell cannot be detected using the classic techniques. Scaling the device to smaller size also has the effect of reducing the voltage range which is used to operate the EPROM. When an EPROM memory cell is shrunk, the programmed threshold voltage is decreased and the effective programming margin is lowered. Also, a smaller EPROM cell typically dictates a lower read current. All of this makes it difficult to read the data in a scaled EPROM cell by means of standard techniques. Lowering the read margin voltage below the supply voltage requires that the row voltage (i.e., the voltage that controls the gate of the EPROM memory element) be regulated to a lower value. If the control gate voltage is not reduced to a level below the magnitude of the programmed threshold voltage, the contents of the EPROM memory cell cannot be read. Regulating the read voltage usually requires the consumption of significant amounts of current, especially if the electrical node being driven requires high speed operation or is heavily loaded with capacitance. A typical solution to regulate the row voltage would be to clamp the row voltage by bleeding off current proportional to the supply voltage to limit the final voltage that is applied to the EPROM element. In the classic EPROM read architecture, the row drive circuitry is also required to be high speed and has a significant amount of capacitive loading. This makes the job of regulating the final voltage very difficult when given the constraints of low current consumption and high speed operation. In the prior art, the EPROM architecture has used a high voltage supply applied directly to the sense amplifier and the X-decoder of the EPROM array. Either the X-decoder, which translates into a row in the array, or the sense amplifier, which translates into a column in the array, is driven, which brings both devices to high voltage. A transistor is present at the intersection of a row with a column, and current flows through the memory cell that comprises the transistor, to program it. As the EPROM program memory device associated with a microcontroller, for example, undergoes a shrink to smaller size, the maximum voltage that may be applied to the device is less than the value that was used with the previous larger-sized device. Nevertheless, the device requires a magnitude of voltage for programming which is determined by a requirement that does not undergo a comparable size reduction. The programming threshold of the memory cell may be exceeded, and equally or more important, the relatively high voltage levels present for programming the EPROM cell may damage the transistor in the cell. It has been industry-wide common practice to place two transistors in series circuit to share a breakdown voltage, because it is unlikely that both will suffer breakdown simultaneously. Rather, since the voltage is split between them, the two transistors are subjected to lower voltage levels than they would otherwise experience. Not only does this have the effect of causing the sharing transistors to be very slow speed devices in the low voltage mode, but the programming voltage is still sufficiently high to damage the transistors. It is a principal aim of the present invention to provide a high voltage buffer which overcomes this disadvantage of the prior art circuitry to enable high voltage level shifting of a signal while still yielding full CMOS (non-contending) operation of the buffer when the "high voltage" level is lowered to or below the device operating voltage V DD . Summary of the Invention The present invention provides a high voltage level shifting CMOS buffer circuit that operates differently, and effectively, in high voltage and low voltage modes. Among other things, the buffer circuit of the invention assists in solving the problem of implementing a high speed, low power EPROM array in a scaled process technology. Despite high programming voltages, transistor damage is prevented by use of the buffer, which in its high voltage mode, provides conventional shared voltage operation with gated breakdown protection, in which two transistors are connected with their source-drain paths in series to share the high voltage applied to the circuit. In its low voltage mode, the buffer acts as a CMOS logic gate with no contention, i.e., with no digital contention between NMOS and PMOS transistors, to provide very high speed and low voltage operation. This assures that the device provides high speed operation over the wide voltage range of interest. Brief Description of the Drawings The above and still further aims, objects, features, aspects, and attendant advantages of the invention will become apparent from a consideration of the best mode presently contemplated for practicing the invention, as implemented in a preferred embodiment and method, taken in conjunction with the accompanying drawings, in which: FIG. 1 is a circuit diagram of an EPROM array circuit embedded in a microcontroller device, as an exemplary application utilizing a high voltage level shifting CMOS buffer according to the present invention; and FIG. 2 is a simplified circuit diagram of a presently preferred embodiment of the high voltage level shifting CMOS buffer of the invention. Detailed Description of the Preferred Embodiment and Method The circuit of FIG. 1 is presented solely as an example of an EPROM device application in which the high voltage buffer of the invention may be used. EPROM array 12 is embedded as a program memory in a microcontroller 10. The memory array has conventional rows and columns, at each intersection of which the state of a transistor (i.e., presence or absence of a device) represents the value ("0" or "1") of the bit stored at that array location. The EPROM has as its operating voltage supply, the voltage V DD of the microcontroller. An X-decoder 13 is the row driver circuit for EPROM array 12, generating the control gate voltage and the control programming voltage for the array. High voltage buffer 15 is coupled for translation of the supply voltage V DD to a voltage sufficiently high to program the EPROM memory element. The buffer is also used with a sense amplifier 17 for the array. A voltage reference 18 employed in the array 12 limits the read voltage of the control gate and the drain of the EPROM memory element. A row precharge circuit in the EPROM improves the time for accessing array locations to read data, and reduces DC power dissipation. In FIG. 1, the row precharge 20 is performed in the regulator circuit and is passed to X-decoder 13 to drive the control gate. Sense amplifier 17 senses the current in the memory element, and determines the threshold of the EPROM element. A switched ground circuit 21 further speeds up the access time of the EPROM array. Current will flow in the memory element only if the control gate of the element is high, the drain of the element is connected to the sense amplifier, and the source of the element is connected to ground. During setup of the row voltage, the source is removed from ground until the voltage has reached a predetermined proper value, and, at that point, the source is grounded and current flows to read the memory element. The high voltage buffer of the present invention used in the exemplary EPROM circuit application of FIG. 1 is illustrated in the simplified circuit diagram of FIG. 2. By means of this buffer circuit, high programming voltages are more effectively dealt with. In the high voltage mode, the buffer uses two transistors to share the burden of the high programmed voltage, similarly to what has been shown in the prior art. But in the low voltage mode, the buffer circuit constitutes a CMOS logic gate. The shared voltage operation of the dual transistor high voltage mode provides high voltage breakdown protection, and in the low voltage mode the invention provides high speed CMOS gate operation over a wide CMOS voltage range. Referring to FIG. 2, the overall buffer circuit includes PMOS (p-channel MOS) transistors 30, 31, 32, and 33, NMOS (N-channel MOS) transistors 35 and 36, and inverter 38. Essentially, the buffer circuit comprises two parallel circuit paths between the voltage source terminal 40 (Z) labeled "high voltage/ V DD " and the analog ground terminal (reference potential). Each transistor has source, drain, and gate electrodes or nodes, as well as a substrate connection. The source-drain current paths of the transistors 30, 31, and 35 are connected in series circuit in one of the two parallel paths, and the source-drain paths of transistor 32, 33, and 36 are connected in series in the other of the two parallel paths. The substrate connections for PMOS transistors 30, 31, 32, and 33 are tied to voltage source terminal 40, and the substrate connections (not shown) for NMOS transistors 35 and 36 are tied to ground. The gate node of each of transistors 30 and 31 is connected to the other parallel path (i.e., to the series circuit containing the source-drain path of the other of those two transistors), and the gate nodes of the other two transistors in each series path are connected together (i.e., the gates of transistors 31 and 35, and separately, the gates of transistors 33 and 36). The inverter 38 is connected between the gates of NMOS transistors 35 and 36 (and thus, also between the gates of PMOS transistors 31 and 33). An input (X) to the buffer circuit is applied at terminal 43 which is connected to the gates of transistors 31 and 35, and outputs (X 0 , nXJ of the buffer are taken at terminals 45 and 47 which are connected to separate ones of the parallel paths. In operation, in the high voltage mode the voltage applied at terminal 40 (Z) is greater than V DD . But the voltage applied to the inverter 38 is V DD . In this case, if a "0" is applied to input terminal 43, then transistors 30, 31, and 36 will be "on", so that a "0" output is present at terminal 45 (X 0 ) and a high voltage output is present at terminal 47 (nXJ. The high voltage is shut off through transistors 32 and 33, which share the breakdown voltage by applying V DD from the output of inverter 38 to the gate of transistor 33. If a "1" is applied to input terminal 43, then transistors 32, 33, and 35 will be "on", so that a high voltage output appears at terminal 45 (X 0 ) and a "0" output is present at terminal 47 (nX 0 ). In that case, transistors 30 and 31 will hold the high voltage off and will share the breakdown voltage relatively equally between them. In operation in the low voltage mode, when terminal 40 (Z) is at or below V DD , transistors 31, 33, 35, and 36 act completely as a CMOS gate by virtue of the interconnection of the gate nodes of each pair of those opposite conductivity type transistors in each of the two parallel circuit paths, and the presence of the inverter 38 in the path interconnecting those gate connections. Hence, the circuit of the invention works at the normal power supply levels as a non-contending CMOS gate; that is, as a true CMOS logic gate without digital contention between the PMOS and NMOS transistors. Accordingly, in its overall operation the buffer circuit fulfills a dual role; namely, as a high voltage level shifter with gated breakdown protection at voltage levels above V DD , and as a true CMOS logic gate when used at normal power supply levels at or below V DD . Although a presently contemplated best mode of practicing the invention has been described herein, it will be understood by those skilled in the art to which the invention pertains, from a consideration of the foregoing description, that variations and modifications of the preferred embodiment and method of the invention may be made without departing from the true spirit and scope of the invention. Accordingly, it is intended that the invention shall be limited only to the extent required by the appended claims and the rules and principles of the applicable case law.

Claims: What is claimed is: 1. A voltage level shifting complementary metal-oxide-silicon (CMOS) buffer for operating in two distinct modes depending on the level of a supply voltage to the buffer relative to the operating voltage of a device in which the buffer is integrated, comprising: means connected to the device operating voltage for constraining the buffer to perform as a high voltage level shifter in response to the level of said supply voltage exceeding the level of the device operating voltage; and means connected to the device operating voltage for constraining the buffer to perform as a CMOS logic gate in response to the level of said supply voltage being equal to or less than the level of the device operating voltage. 2. The buffer of claim 1, wherein said means for constraining the buffer to perform as a high voltage level shifter includes a pair of parallel circuit paths between a terminal connected to the device operating voltage and a node connected to a point of reference potential, each of said circuit paths including first and second stacked MOS transistors with their source-drain paths connected in series circuit and arranged and connected to hold off a supply voltage level that exceeds the level of the device operating voltage and to share substantially equally a breakdown voltage imposed across its respective circuit path by such supply voltage level. 3. The buffer of claim 2, wherein said means for constraining the buffer to perform as a CMOS logic gate includes a third transistor stacked with the other two in each of said pair of parallel circuit paths, so that its source-drain path is connected in series circuit with the source-drain path of the other two, said third transistor being of opposite conductivity type from the first two, and having its gate node to connected to the gate node of one of the two transistors in its circuit path to which its source-drain path is directly connected, and an inverter connected between the gate nodes of the third transistors in the pair of parallel paths, so as to act as a CMOS logic gate without digital contention between the transistors of opposite conductivity type whose gate nodes are connected in the two circuit paths in response to the level of said supply voltage being equal to or less than the level of the device operating voltage when a logic level input is applied to said connected gate nodes. 4. The buffer of claim 3, wherein said first and second stacked MOS transistors in each of the parallel circuit paths are p-channel MOS (PMOS) transistors, and the third transistor in each of the parallel circuit paths is an n-channel MOS (NMOS) transistor. 5. The buffer of claim 4, wherein logic outputs of the buffer are taken from each of the parallel circuit paths, and a logic input is applied to an input of the inverter. 6. A device-implemented method of voltage level shifting in a complementary metal-oxide-silicon (CMOS) buffer to accommodate operation in two distinct modes depending on the level of a supply voltage to the buffer relative to the operating voltage of a device in which the buffer is integrated, said method comprising: constraining the buffer to perform as a high voltage level shifter in response to the level of the supply voltage exceeding the level of the device operating voltage; and constraining the buffer to perform as a CMOS logic gate in response to the level of the supply voltage being equal to or less than the level of the device operating voltage. 7. The method of claim 6, including stacking a pair of PMOS transistors in each of two parallel circuit paths between a terminal connected to the device operating voltage and a ground terminal to enable a sharing of breakdown voltage between the two PMOS transistors in each of said circuit paths when the supply voltage level exceeds the level of the device operating voltage, and interconnecting the gate node of one of the PMOS transistors in each of the two parallel circuit path to the gate node of an NMOS transistor in the same circuit path and connecting an inverter between those interconnections of gate nodes from one of the parallel circuit paths to the other. 8. The method of claim 7, including applying a logic input to an input of the inverter and taking logic outputs of the buffer from each of the parallel circuit paths. 9. An erasable programmable read-only memory (EPROM) having a memory array in which rows and columns of the array are used to program data to be stored and to read data stored in the array as 0's and l's according to the presence or absence of a device at each intersection of a row and a column of the array, the EPROM comprising: a source of operating voltage for the EPROM; a source of supply voltage for programming data in and reading data from the array; and a buffer having a high voltage mode and a low voltage mode of operation, wherein the configuration of the buffer for use in the high voltage mode includes a pair of parallel circuit paths connected between said source of supply voltage and ground, each of said parallel circuit paths including a pair of MOS transistors having series connected source-drain paths for substantially equally sharing breakdown voltages during programming of the array with a supply voltage level exceeding the level of the operating voltage; and the configuration of the buffer means for use in the low voltage mode during reading of the array with a supply voltage level equal to or less than the level of the operating voltage includes an opposite conductivity type MOS transistor in each of the pair of parallel circuit paths, with source-drain path thereof series connected with the source-drain paths of the respective pair of MOS transistors in the same parallel circuit path, and an inverter connected between the gate nodes of the opposite conductivity type MOS transistor in the parallel circuit paths, said gate nodes being interconnected with respective gate nodes of one of the first-named pair of MOS transistors in the parallel circuit paths. 10. The EPROM of claim 9, wherein a terminal for a logic input to the buffer is connected to an input of the inverter, and terminals for logic outputs of the buffer are connected to respective ones of each of the parallel circuit paths.

Inventors: HULL RICHARD L, YACH RANDY L, HULL, RICHARD, L., YACH, RANDY, L.
Applicants: MICROCHIP TECH INC, MICROCHIP TECHNOLOGY INCORPORATED
Application year: 1997
Main classification: H03K19
IPC codes: G11C16, H03K3, H03K17, H03K19