Floating point number data processing means

Abstract: The floating point number data processing means is for use in microprocessor systems and finds application in AC motor drive technology. The format used includes a sign bit, a seven bit signed exponent and an eight bit mantissa. The mathematical functions are performed in a gate array using registers which are mapped into a memory of the microprocessor system, the particular mathematical function being dependent upon a particular choice of registers. An unsigned integer comparison of floating point numbers is used to give a correct result.

Description: The present invention relates to floating point number data processing means for use with microprocessor systems and in particular to a low precision floating point number format. The present invention finds application in AC motor drive technology where, for example, a small motor may draw half an amp of current and a large motor may draw 200 amps of current, and the frequency range of such motors is very large. Many known floating point systems are realised in pure software. This is a slow process, typically taking tens or hundreds of micro-seconds per operation. Existing microcontrollers use integer arithmetic. In many control applications, the range of variables results in a scaling calculation at every calculation step in order to maintain accuracy while avoiding overflow. Floating point variables and arithmetic solve this problem. Floating point mathematics hardware is available to the universally accepted IEEE format. The standard precision for this format requires 4 or 5 bytes storage as mentioned above. The range and accuracy of these numbers far exceeds most control requirements. The hardware to implement mathematic functions is complex and operates slowly. Several memory operations are required to load each operand into the floating point unit and the result out. A floating point comparison, e.g. the control statement if (A < B) then, requires a full floating point subtraction and inspection of the sign of the result. This very common control function becomes rather time consuming. An aim of the present invention is to provide means for performing operations on a floating point number format which does not suffer from the above disadvantages experienced in the prior art. According to the present invention there is provided an apparatus according to claim 1. In accordance with another aspect of the invention, there is provided a method according to claim 5. An embodiment of the invention will now be described, with reference to the accompanying drawings, in which: Figure 1 shows a block diagram of a system including a microcontroller, gate array and a flash floating point processor, Figure 2 shows a block diagram of one implementation of a flash floating point processor, Figure 3 shows a block diagram of an arithmetic unit, and Figure 4 shows a table of the arithmetic unit functions. The floating point format has a sign bit, a 7 bit signed exponent, and an 8 bit mantissa. The mantissa has an assumed 9th bit. The resultant 16 bits is a single memory location or data transfer operation in a 16 bit microcontroller. When one further requires that an unsigned integer comparison of floating point numbers should be correct, this leads to the following format: where bit 15 is a sign bit, 1 = positive. If 0, invert all other bits bit 14 is an exponent sign, 1 = positive bits 13-8 is the exponent, note whole exponent is 2's complement with sign bit inverted, and, bits 7-0 is the mantissa, note effective 9 bit mantissa. Add 256 to this number. Examples of this format are as follows: FFFF is +(255 + 256)/256 * 2 63 = +1.841E19 (largest possible number); C000 is +(0 + 256)/256 *2 0 = +1; 8000 is +(0 + 256)/256 * 2 -64 = +5.421E-20 (smallest possible number); -1 would be 3FFF II would be C192 = +(146 + 256)/256* 2 1 = 3.140625 (0.03% error). The range of numbers which can be calculated is: +/- 5.4x10 -20 to 1.84x10 19 with an accuracy of 0.2% All numbers and calculation results are correct to between 1/512 and 1/1024 thus giving a basic accuracy of 0.2%. An implementation of this floating point format is performed by a range of mathematical functions in a gate array with registers mapped into the memory range of an associated microcontroller. This implements all functions combinatorially and the function is determined by register choice. For example, to add two numbers, write operand 1 to the floating point A accumulator, write operand 2 to the floating point B add register, read the result from the floating point A accumulator. These registers are memory mapped leading to very fast data throughput. Because of the reduced accuracy, only approximately 3K gates are required to perform +-*/ functions. Additionally, floating point to integer and integer to floating point conversion functions are integrated. To speed up multi-step calculations, if the A accumulator is not written between calculations, the previous calculation result is latched into the A accumulator so calculations are executed at the rate at which the B register can be written to. Thus, a sustainable 5 megaflop performance is achieved. Referring to Figure 1, there is shown a microcontroller (2) having a highway connection (4) to a motor drive system. The microcontroller (2) is connected to a gate array (6) which includes a flash floating point processor. The connection to the gate array (6) is made by a four bit address highway (8) and a sixteen bit data highway (10). Two further control signals, NRD and NWR are provided by the microcontroller (2) to the gate array (6). The gate array including the flash floating point processor unit is mapped into the memory space of the microcontroller, and as this is a combinatorial system no clock connection is needed between the microcontroller and the flash floating point processor. Referring to Figure 2 there is shown an implementation of a flash floating point processor. A data bus 22 is connected to a first converter 24, inputs of a first multiplexer 26 and a B register 28. The first converter 24 has its output connected to further inputs of the first multiplexer 26. The output of the first multiplexer 26 is connected to inputs of a second multiplexer 30, and the outputs thereof are connected to an A register 32. The outputs of the registers 28 and 32 are connected to an arithmetic unit, the output of which is fed back to further inputs of the second multiplexer 30. The output of the arithmetic unit 34 is also fed to a second converter 36 and to inputs of a third multiplexer 38. The output of the second converter 36 is applied to further inputs of the multiplexer 38. Output signals from the third multiplexer 38 are fed out to a data bus 40 under control of a READ A signal. WRITE A and B signals are applied to the A and B registers 32, 28 and the second multiplexer 30 by means of associated latching and gating circuitry 42-46. An A-INT/A-FLO control signal is applied over line 48 to the first multiplexer 26 and the third multiplexer 38. Address information is passed over a highway 50 to a function register 52, which receives the WRITE B control signal and generates two output signals MULDIV, SUBDIV, which are applied to the arithmetic unit 34. The converter 24 designated INT/FLO is a hardware converter between the 16 bit unsigned integers on highway 22 and the floating point number format multiplexer 26 which uses the address information (A-INT/A-FLO) on line 48 to determine whether to choose a floating point number from the data bus or an integer from the INT/FLO, converter 34 thus allowing unsigned integers to be written directly to the flash floating point processor. The multiplexer 30 selects either the data bus contents or the previous floating point output to be written into the A register 32. If the B register 28 is written twice in succession, the previous floating point output is written into the A register 32 at the same time as the new operand is written into the B register 28. The output of floating point arithmetic unit 34 does not need to be latched because its inputs are latched, and therefore the output remains stable until one of registers 28, 32 are written into. The FLO/INT converter 36 is a hardware converter positioned between the floating point number format and the 16 bit unsigned integers. This converter 36 and the arithmetic unit 34 are fully combinatorial, containing no latches, flip-flops or loop structures of any kind. Referring to Figure 3 there is shown a block diagram of the arithmetic unit 34 in Figure 2. The arithmetic unit comprises a floating point adder 60, a floating point subtractor 62, a floating point multiplier 64 and a floating point divider 66, all of which receive respective A operand signals on highway 68 and B operand signals on highway 70. The outputs from the adder 60 and the subtractor 62 are applied to a multiplexer 72, and the outputs of the multiplier 64 and divider 66 are applied to the inputs of a multiplexer 74. The outputs of the multiplexer 72 and 74 are applied to a further multiplexer 76 which generates the output signals of the arithmetic unit. The multiplexers 72 and 74 receive the SUBDIV control signal and the multiplexer 76 receives the MULDIV control signal. These signals are shown in the table of Figure 4, and together determine the function of the arithmetic unit and the required output from the arithmetic unit. It will be appreciated by those skilled in the art that there are other ways of implementing the present invention which fall within the scope of the following claims.

Claims: Apparatus for performing operations with respect to numbers in a floating point format, said apparatus comprising: a microprocessor (2); and an associated floating point gate array (6) coupled in data communication (8, 10) with said microprocessor, said gate array including a floating point arithmetic unit which operates combinatorially on said numbers in a floating point format; wherein the floating point format comprises sixteen bits of data, where bit 15 is a sign bit 1= positive; If 0, invert all other bits bit 14 is an exponent sign 1 = positive bits 13-8 is the exponent, note whole exponent is 2's complement with sign bit inverted, and, bits 7-0 is the mantissa; and when said sign bit is zero, all other bits in said sixteen bits of data are inverted, such that an unsigned integer comparison of said floating point numbers yields a correct result. Apparatus for performing operations with respect to numbers in a floating point format according to claim 1, wherein mathematical functions are performed in the gate array using registers (28, 32) which are mapped into a memory of the microprocessor system. Apparatus for performing operations with respect to numbers in a floating point format according to claim 2, wherein the mathematical functions are performed by a particular choice of registers. Apparatus for performing operations with respect to numbers in a floating point format according to claim 4 or 5 wherein, subsequent to a previous calculated result, if a first register is not written to between a first calculation and a second calculation, the first calculation is latched into the first register, so that calculations are executed at a rate at which a second register can be written to. A method of performing operations with respect to numbers in a data processor which includes a microprocessor (2) and an associated logic gate array (6), said method comprising: expressing said numbers in a floating point format; said logic gate array implementing mathematical manipulations of said numbers in said floating point format; and said data processor performing unsigned integer comparison of said floating point numbers; wherein said logic gate array operates combinatorially on said numbers according to said floating point format; and said floating point format comprises sixteen bits of data wherein said floating point format is constituted as follows: bit 15 is a sign bit 1 = positive; if 0, invert all other bits bit 14 is an exponent bit 1 = positive bits 13-8 are an exponent wherein whole exponent is 2's complement with sign bit inverted, and bits 7-0 are a mantissa; add 256 to this number. and is structured, wherein, when said sign bit is zero, all other bits of said sixteen bits of data are inverted, such that said unsigned integer comparison of said numbers in said floating point format consistently yields a correct result.

Inventors: CARTER ROBERT, CARTER, ROBERT
Applicants: SIEMENS PLC
Application year: 1997
Main classification: G06F7
IPC codes: G06F7, G06F9