Method of writing data to a single transistor type ferroelectric memory cell

Abstract: The invention is directed to a writing method which suppresses inter-cell interference when writing data to a single transistor type ferroelectric memory. In this memory stripelike conducting electrodes form row electrodes, and semiconductor strips form column electrodes. The writing method includes a first procedure based on a V/3 rule and a succeeding second procedure. In the first procedure, when a voltage of +V is applied to the row electrode of a selected cell while a voltage of zero is applied to the respective column electrode, and voltages of +V/3 are applied to the other row electrodes, and voltages of +(2/3)V are applied to the other column electrodes, then in the second procedure, a voltage of zero is applied to the electrode of the selected cell, while a voltage of +V/3 is applied to the column electrode, and voltages of +V/3 are applied to the other row electrodes, and voltages of zero are applied to the other column electrodes. In the first procedure, when a voltage of -V is applied to the row electrode of the selected cell while a voltage of zero is applied to the respective column electrode, and voltages of -V/3 are applied to the other row eiectrodes, and voltages of -(2/3)V are applied to the other column electrodes, then in the second procedure, a voltage of zero is applied to the row electrode of the selected cell while a voltage of -V/3 is applied to the respective column electrode, and voltages of -V/3 are applied to the other row electrodes, and voltages of zero are applied to the other column electrodes.

Description: The present invention relates to a method of writing data to a single transistor type ferroelectric memory. Known non-volatile memories which use a ferroelectric material generally have a two element per cell construction with a normal MOS transistor and a ferroelectric capacitor per cell. With such memories, however, there is the drawback that when reading stored information, the information (data) is destroyed (destruction reading). Moreover, in contrast to the EEPROM which uses two transistors of a normal MOSFET and a floating gate type FET per cell, the known flash memory is a single transistor type non-volatile memory which uses one floating gate type FET per cell. However, in cases where a floating gate type FET is used, writing of data cannot be accomplished during the normal operation time of the computer, and with the flash memory, erasure for each cell, that is to say for each bit, is not possible. Although the flash memory has the above drawback, since there is one element per cell, area effectivity is good. Japanese Patent Publication No. JP 606 8288 (Self Learning Type Sum of Products Operation Circuit Element and Circuit) also discloses a single transistor type non-volatile memory, in this case a single transistor type ferroelectric memory which is described later in detail. The essential difference between this memory and the former is that instead of the requirement for erasing information prior to writing at the floating gate type FET of each cell of the flash memory, with the ferroelectric type FET the erasing operation is not necessary. That is to say, the saturation phenomenon in the polarization of a ferroelectric film is used, giving the advantage that problems do not arise as with the floating gate type FET, where an excessive charge is injected to the floating gate and an excessive charge is extracted. The single transistor type ferroelectric memory differs from DRAM, or the capacitance type FRAM (ferroelectric RAM) currently under investigation, in that the capacitance is ferroelectric memory there is an advantage of high densification, since via-holes for interconnections are not necessary. Consequently, in addition to the non-volatility characteristics, this memory is expected to find favour as a future high integration low power consumption device. The above single transistor type ferroelectric memory has a three layer construction in which a ferroelectric film is sandwiched with single-crystal semiconductor stripes and stripe-like conducting electrodes placed approximately perpendicular to the (bottom) semiconductor stripes. When a writing voltage is applied from a peripheral circuit to a selected cell of the memory, the influence of the writing voltage also extends to the other cells along the upper and lower stripes, presenting the problem of a large mutual interference such that the stored data in the non-selected cells are inverted during writing. It is an aim of the present invention to provide a method of writing data to a single transistor type ferroelectric memory having the advantages of non-volatility, high integration ability, and low power consumption, which method can suppress inter-cell writing interference. According to the invention, there is provided a method of writing data to a memory device having a matrix of storage cells formed by a plurality of pnp or npn semiconductor structures arranged in columns to form column electrodes at a first level, a plurality of conductors arranged as row electrodes at a second level, and a ferroelectric film at an intermediate level between the semiconductor structures and the row electrodes such that field-effect transistors are formed where the row electrode overlie the semiconductor structures, each storage cell comprising one such transistor, characterised in that the method comprises writing data to a selected cell by: in a first step, applying respective voltages to the row electrode and the column electrode which are those of the selected cell, the voltages being such as to produce at the selected cell a potential difference of a magnitude V and of a predetermined sign between the first level and the second level, and simultaneously applying to the other row and column electrodes further respective voltages such as to produce at the other cells along the selected row and column electrodes a potential difference of a magnitude in the region of a V/3 and of the said predetermined sign and at the cells which are not along the selected row and column electrodes a potential difference of a magnitude in the region of V/3 but of the sign opposite to the said predetermined sign, and in a second step, immediately following the first step, applying to the selected row and column electrodes respective voltages such as to produce at the selected cell a potential difference of a magnitude in the region of V/3 and of the said opposite sign, and simultaneously applying to the other row and column electrodes further respective voltages such as to produce at the other cells along the selected row and column electrodes a potential difference in the region of zero and at the cells which are not along the selected row and column electrodes a potential difference of a magnitude in the region of V/3 and of the said predetermined sign. The invention will now be described by way of example with reference to the drawings in which:- Figures 1A and 1B are, respectively, a cross-section and a diagrammatic plan view of the structure of a single transistor type ferroelectric memory to which the method of the present invention may be applied; Figures 2A and 2B are diagrams for explaining first and second procedures, respectively, of a method in accordance with the invention; Figure 3 is a graph illustrating polarization changes of a ferroelectric thin film (SrBi 2 Ta 2 O 9 ) for various pulse application methods; Figure 4 is a graph illustrating the polarization/voltage hysteresis characteristic of the ferroelectric thin film (SrBi 2 Ta 2 O 9 ) used in Figure 3; and Figure 5 is a diagram showing an equivalent circuit for the single transistor type ferroelectric memory to which the method to be described below is applied. Throughout Figures 1 to 5, the reference numeral 1 indicates an insulator substrate, 2 a plurality of mutually parallel stripe-like single-crystal semiconductor thin film elements electrodes a potential difference of a magnitude in the region of V/3 but of the sign opposite to the said predetermined sign, and in a second step, applying to the selected row and column electrodes respective voltages such as to produce at the selected cell a potential difference of a magnitude in the region of V/3 and of the said opposite sign, and simultaneously applying to the other row and column electrodes further respective voltages such as to produce at the other cells along the selected row and column electrodes a potential difference in the region of zero and at the cells which are not along the selected row and column electrodes a potential difference of a magnitude in the region of V/3 and of the said predetermined sign. The invention will now be described by way of example with reference to the drawings in which:- Figures 1A and 1B are, respectively, a cross-section and a diagrammatic plan view of the structure of a single transistor type ferroelectric memory to which the method of the present invention may be applied; Figures 2A and 2B are diagrams for explaining first and second procedures, respectively, of a method in accordance with the invention; Figure 3 is a graph illustrating polarization changes of a ferroelectric thin film (SrBi 2 Ta 2 O 9 ) for various pulse application methods; Figure 4 is a graph illustrating the polarization/voltage hysteresis characteristic of the ferroelectric thin film (SrBi 2 Ta 2 O 9 ) used in Figure 3; and Figure 5 is a diagram showing an equivalent circuit for the single transistor type ferroelectric memory to which the method to be described below is applied. Throughout Figures 1 to 5, the reference numeral 1 indicates an insulator substrate, 2 a plurality of mutually parallel stripe-like single-crystal semiconductor thin film elements with npn or pnp regions, 3 a ferroelectric thin film, and 4 a plurality of mutually parallel stripe-like conducting electrodes. Referring to Figures 1A and 1B, a single transistor type ferroelectric memory has a plurality of single crystal semiconductor thin film elements 2 having an npn sequence structure in the transverse direction. Elements 2 are formed in columns on an insulator substrate 1 as, for example, a silicon single-crystal thin film in a mutually parallel strip formation. A ferroelectric thin film 3 is deposited on top of these thin film elements 2 so as to cover at least the semiconductor stripe structure. Furthermore, a plurality of mutually parallel stripe-like conducting electrodes 4 (for example metal strips) are deposited on top of the above structure in a direction at least approximately perpendicular to the semiconductor film elements 2. Transistors are formed at the intersections of the semiconductor elements 2 and the conducting electrodes 4, the n regions on both sides forming the source and the drain regions, and the intermediate p regions forming the channels of the transistors. Moreover, the transistors in each column formed by the elements 2 are all connected in parallel (as shown in Figure 5) due to the source and the drain regions being connected as semiconductor stripes. Each such transistor forms a cell of the memory. The above-described component is referred to as a single transistor type ferroelectric memory and is known, for example, from Japanese Patent Publication No. 7-31705 (Self Learning Type Sum of Products Operation Circuit Element and Circuit). In the structure of this component, a field effect transistor is formed with the ferroelectric thin film 3 as a gate insulator. If a positive voltage is applied, for example, to a word line, i.e. to one of the stripe-like conducting electrodes 4 forming the upper layer, and a negative voltage is applied to a stripe-like silicon element 2 or, alternatively, voltages are applied in accordance with the first procedure of claim 1 below, then a large potential difference can be applied solely to the ferroelectric thin film located at the point of intersection. Hence selective writing of data becomes possible. This is because even though the potential difference to the ferroelectric thin film is removed, a charge corresponding to the remanent polarization remains on the semiconductor surface, and hence the data are retained in a written condition. If, in the selective writing, a positive voltage V applied to the conducting row electrode 4 is made to correspond to data 1, and an opposite polarity is made to correspond to data 0, then digital data writing becomes possible. Moreover, in reading the data, the conducting row electrode 4 on top of the ferroelectric thin film corresponding to the selected cell of the memory is made the gate electrode, a voltage which is relatively low compared to voltage V is applied to this gate electrode, and a voltage is applied from the peripheral circuit between the source and drain of the underlying npn semiconductor element 2. If the drain current flowing at this time is then read from the peripheral circuit, data of 0 or 1 depending on the magnitude thereof can be read. In order to carry out such a reading operation, the transistor structure and the polarization of the ferroelectric film may be adjusted so that at the time of writing 0, the threshold voltage for the transistor becomes sufficiently high, while at the time of writing 1, this becomes sufficiently low. Next is a description of a first procedure and an immediately following second procedure, with reference to Figures 2A and 2B, for effectively controlling inter-cell interference when writing to the ferroelectric memory described above. A first example of writing to a non-volatile memory in accordance with the method of the present invention is based on the following procedure. A voltage V is applied to a selected word line 4 while voltages V/3 are applied to the non-selected word lines 4. Moreover a voltage 0 is applied to a selected silicon element 2, while voltages 2V/3 are applied to the non-selected silicon elements 2. As a result, as shown in Figure 2(a), a potential difference of V occurs only across the gate insulator (ferroelectric layer) of the selected cell, while potential differences of + or -V/3 occur across the gate insulators of all the other cells. Selective polarization control thus becomes possible due to this difference. Since with the writing of the information, the threshold voltage of the FET changes, a gate voltage suitable for reading can be applied to detect the presence of a drain current, and information once written is not lost at the time of reading. The above covers the first procedure. If immediately after carrying out the writing by applying the voltages as shown in Figure 2A, voltages as shown in Figure 2B are applied, then for the cells which were not selected, voltages of +V/3 are applied to the cells which were subjected to the voltages of -V/3 at the time of writing. As a result, the inter-cell mutual interference during writing can be significantly reduced. The above covers the second procedure. What should be noted here is that for non-selected cells in the same line or the same column as the selected cell, in the first procedure voltages of V/3 are applied, for example, in the row direction, and in the second procedure voltages of zero are applied, and hence there is not complete cancellation. Likewise, in the column direction, in the second procedure voltages of zero are applied relative to the V/3 voltages of the first procedure and hence, again, there is not complete cancellation. However, the number of relevant cells in the case where the total cell number is for example 500 x 500, is of low probability at approximately 1/250 of the total cell number. Furthermore, as will become apparent from the experimental results referred to below, the significant mutual interference occurs only when a number of interference voltage pulses of -V/3 are successively applied to the ferroelectric film after writing with a voltage of V. Therefore, considering that the memory carries out a random access operation, then overall this is not a problem. In the above-mentioned example, writing is performed with a positive voltage V. However, a negative voltage -V can also be used. In this case, all the signs for the voltages applied in the first procedure and in the second procedure are reversed. Experimental clarification that the inter-cell mutual interference at the time of writing can be greatly reduced by means of the first procedure and the second procedure is illustrated by Figure 3. Figure 3 represents measurements of polarization change of a ferroelectric thin film after effecting writing by application of a +V pulse to an experimental sample, described below, equivalent to one cell of the ferroelectric memory. In Figure 3, the horizontal axis shows the number of applied pulses while the vertical axis shows the amount of change in the polarization charge (Pr/Pro; where Pro is the initial value). The sample used here was an MFM (metal/ferroelectric/film /film metal) capacitor described hereafter. Plot a in Figure 3 is for the case where a positive interference pulse (+V/3) only is applied, plot b is for the case where a positive pulse (+V/3) and a negative pulse (-V/3) are applied alternately, while plot c is for the case where a negative pulse (-V/3) only is applied. With the writing method described above with reference to Figures 2A and 2B, the great majority of the cells corresponded to the experimental results of Figure 3 plot b. Accordingly, these experimental results show that, if the above-described writing method is used, then if the ferroelectric gate insulator of a selected cell is written with information, and if this cell is not subsequently selected, then even after carrying out 10 10 writing operations to the other cells, approximately 80% of the polarization of the selected cell is maintained. Considering that discrimination between 0 and 1 of the written data becomes impossible when the vertical axis value in Figure 3 becomes 50%, it can be concluded that the present method of writing effectively suppresses inter-cell interference at the time of writing. An approximately 250nm thick SrBi 2 Ta 2 O 9 film was deposited on a Pt/Ti/SiO 2 /Si substrate using the sol-gel method. The substrate was silicon crystal bulk with SiO 2 formed thereon, and platinum on titanium electrodes on top of this as lower electrodes. Platinum electrodes of 200µm diameter were used as top electrodes, the ferroelectric coating of SrBi 2 Ta 2 O 9 being subjected, both before and after forming the upper platinum electrodes, to a heat treatment of 750°C for 30 minutes. Figure 4 shows the characteristic of the ferroelectric hysteresis curve for the film. The experimental pulse V applied to the sample was 1.5 volt. Consequently, V/3 was 0.5 volts and the pulse width was 3µs. The invention has been described above in relation to one embodiment but is not limited to this embodiment, and it will be apparent that various modifications and changes are possible within the scope of the claims. For example, while above-described embodiment has a silicon single crystal thin film as the single crystal semiconductor thin film, single crystal thin films of other semiconductors such as GaAs and InSb may also be used. Moreover, for the ferroelectric film, films other than SrBi 2 Ta 2 O 9 also exhibiting ferroelectric characteristics may be used. As will be clear from the above description, application of the above methods of writing data to a single transistor type ferroelectric memory allows inter-cell interference at the time of writing to be effectively suppressed, offering a high quality non-volatile memory with high integration and low power consumption.

Claims: A method of writing data to a memory device having a matrix of storage cells formed by a plurality of pnp or npn semiconductor structures arranged in columns to form column electrodes at a first level, a plurality of conductors arranged as row electrodes at a second level, and a ferroelectric film at an intermediate level between the semiconductor structures and the row electrodes such that field-effect transistors are formed where the row electrodes overlie the semiconductor structures, each storage cell comprising one such transistor, characterised in that the method comprises writing data to a selected cell by: in a first step, applying respective voltages to the row electrode and the column electrode which are those of the selected cell, the voltages being such as to produce at the selected cell a potential difference of a magnitude V and of a predetermined sign between the first level and the second level, and simultaneously applying to the other row and column electrodes further respective voltages such as to produce at the other cells along the selected row and column electrodes a potential difference of a magnitude in the region of a V/3 and of the said predetermined sign and at the cells which are not along the selected row and column electrodes a potential difference of a magnitude in the region of V/3 but of the sign opposite to the said predetermined sign, and in a second step, immediately after the first step, applying to the selected row and column electrodes respective voltages such as to produce at the selected cell a potential difference of a magnitude in the region of V/3 and of the said opposite sign, and simultaneously applying to the other row and column electrodes further respective voltages such as to produce at the other cells along the selected row and column electrodes a potential difference in the region of zero and at the cells which are not along the selected row and column electrodes a potential difference of a magnitude in the region of V/3 and of the said predetermined sign. A method according to claim 1, characterised in that pnp or npn semiconductor structures are formed in a silicon crystal or in silicon thin film stripes provided on an insulator substrate. A method according to claim 1 or claim 2, characterised in that said plurality of conductors arranged as the row electrodes are metal electrodes. A method according to any preceding claim, characterised in that in the first step the voltages applied to the selected row and column electrodes are respectively of magnitude V and zero while those applied to the other row and column electrodes are respectively of magnitude V/3 and 2V/3 and of the same sign as that applied to the selected row electrode, and in that in the second step the voltages applied to the selected row and column electrodes are respectively of magnitude zero and V/3, while those applied to the other row and column electrodes are respectively V/3 and zero, the sign of the voltages applied to the selected column electrode and those applied to the said other row electrodes being the same as the sign of the voltage applied to the selected row electrode in the first step. A method according to any preceding claim, characterised in that , in writing a plurality of data bits of logic level "1" and logic level "0" to the memory device, the sign of the potential difference applied at each selected cell during the said first step of any one writing operation is either positive if the respective data bit to be written is of one of the logic levels or negative if the data bit is of the other of the logic levels.

Inventors: ISHIHARA HIROSHI, TOKUMITSU EISUKE, ISHIHARA, HIROSHI, TOKUMITSU, EISUKE
Applicants: TOKYO INST TECH, TOKYO INSTITUTE OF TECHNOLOGY
Application year: 1997
Main classification: G11C11
IPC codes: H01L29, H01L21, G11C14, G11C16, G11C11, H01L27