SIX-INPUT MULTIPLEXER WITH TWO GATE LEVELS AND THREE MEMORY CELLS

Abstract: A six-input multiplexer is disclosed using only two transistors in the signal path from an input port to the output port. The multiplexer uses control signals that are not decoded. The multiplexer uses three control signals and requires that the control signal combinations 000 and 111 not be used. The other six control signal combinations 001, 010, 011, 100, 101, and 110 can be used to select between six input signals by placing only two transistors in the signal path, taking advantage of the fact that two of the three control signals are the same and the third is different from the other two. A compact layout results when two multiplexers use common input signals.

Description: SIX-INPUT MULTIPLEXER WITH TWO GATE LEVELS AMD THREE MEMORY CELLS FIELD OF THE INVENTION The invention relates to integrated circuits, more particularly to multiplexers implemented in integrated circuit devices . BACKGROUND OF THE INVENTION In the field of integrated circuit devices, particularly programmable devices, it is desirable to move a signal as fast as possible along its path to a destination. It is also desirable to minimize the area of an integrated circuit device needed to implement a function. Thus speed should be maximized and area should be minimized. In the case of multiplexers, memory cells are frequently used to control a multiplexer. It is widely known that two memory cells can select between up to four input signals and three memory cells can select between up to eight input signals. Figs. 1-3 show three prior art structures for controlling six-input multiplexers. In Fig. 1, the selection is done by providing a transistors tree, each memory cell selecting a branch of the tree. Memory cell Ml controls N-channel transistors Tl, T3, and T5 from its inverting output and transistors T2, T4, and T6 from its noninverting output. A logical 0 in memory cell Ml causes transistors Tl, T3, and T5 on and thus forwards input signals INO, IN2, and IN4 to the next level. Memory cell M2 selects between transistors T7 and T8. If memory cell M2 holds a logical 0, the signal from one of INO and INI is forwarded to the next level and if memory cell M2 holds a logical 1, the signal from one of IN2 and IN3 is forwarded to the next level. Finally, memory cell M3 controls transistors T9 and T10, and selects between the signal forwarded from one of INO through IN3 and the signal forwarded from one of IN4 and IN5. In this embodiment, a signal on INO must pass through three transistors, Tl, T7, and T9 to reach the OUT terminal. Thus the signal path is slower than desirable. Alternatively, in Fig. 2, the selection is done by providing one decoder for each input line and turning on a different transistor to enable a different input signal in response to a different combination of signals from the memory cells. For example, AND-gate decoder Dl provides a high output signal when all three of memory cells M1-M3 hold logical 0, turning on transistor T21 and providing the signal on INO to OUT. Other memory cell combinations provide one of the other input signals IN0-IN5 as the output signal. Only one transistor is in the signal path, but the control signal must pass through a decoder, and silicon area must be used to provide the decoders . Thus the structure of Fig. 2 is faster but larger than the structure of Fig. 1. Fig. 3 shows a six-input multiplexer that uses four memory cells and requires the input signal to pass through two transistors to reach the output terminal. Memory cells M1-M3 each select between three input signals. Only one of memory cells Ml through M3 is permitted to hold a logical 1 at one time. When memory cell Ml holds logical 1, it turns on transistors T31 and T34. A logical 1 in memory cell M2 turns on transistors T32 and T35, A logical 1 in memory cell M3 turns on transistors T33 and T36. Memory cell M4 chooses which of the selected input signals is provided to the OUT terminal. This prior art multiplexer places two transistors into each signal path. It uses no decoders, but requires four memory cells. Other multiplexers are also known. For example, six memory cells can select between six input signals placing only one transistor into the signal path. Three memory cells can control an 8:1 multiplexer with only one transistor in the signal path using decode logic, but this decode logic typically takes more area than an additional memory cell. Larger multiplexers can be formed by combining structures similar to those shown in Figs. 1-3. It has not been known in the past that a six input multiplexer can be provided without decoders to select between more than four input signals using only two transistors in a signal path. SUMMARY OF THE INVENTION The present invention controls a multiplexer from an odd number of signal sources, for example memory cells, and places into the signal path a number of pass devices equal to (n+l)/2 where n is the number of signal sources. The number of inputs available is 6 for three signal sources and 20 for five signal sources. In one embodiment, the invention results in a six-input multiplexer using only two transistors in the signal path from an input port to the output port. The multiplexer uses three control signals and requires that the control signal combinations 000 and 111 not be used. The other six control signal combinations 001, 010, 011, 100, 101, and 110 can be used to select between six input signals by placing only two transistors in the signal path, taking advantage of the fact that two of the three control signals are the same and the third is different from the other two. A transistor that would be controlled by the signal known to be different is not placed into the signal path. For example, on the signal path identified by the signal combination 001, N-channel transistors controlled by the complement of the first and second signals are placed in the path. These transistors turn on when the first two signals are 00. Since the third signal is known to be 1 (because the value 000 is not allowed) , no transistor is used to indicate the third signal. For another example, on the signal path identified by the signal combination 011, N-channel transistors controlled by the noninverted values of the second and third signals are placed in the path. These transistors turn on when the second and third signals are 11. Six paths respond to six different combinations of the three control signals. The resulting structure is both small and fast, even when the control signals are switching, because no logic gates are needed to decode the control signals. And using only two transistors rather than three in the signal path makes this path faster than structures having three transistors in the signal path. The above description refers to transistors connecting portions of a path from an input port to an output port. Transmission gates may alternatively be used. The above description also relates to a six-input multiplexer. Other numbers of inputs may also be used. In particular, a 20-input multiplexer with three pass devices in each path and five control memory cells can be formed according to the invention, requiring that 2 or 3 0' s be present in the five memory cells. Layout of the multiplexer structure benefits from shared source and drain wells and from the fact that two gates (for the six-input multiplexer) may be placed in series without allowing space for a contact to the conductor extending between the two gates. Also, two paths which connect to the same output terminal may use the same well for the output signal. In an even more efficient layout, two multiplexers which share input signals may be laid out even more efficiently by alternating gates of the two multiplexers so that input signal wells are also shared. BRIEF DESCRIPTION ON THE DRAWINGS Figs. 1-3 show three prior art structures for controlling six-input multiplexers. Fig. 4 shows a circuit diagram of a 6-input multiplexer according to the invention. Fig. 5 is a plan view indicating the physical relationship of the elements in the circuit of Fig. 4. Fig. 6 shows an interconnection structure 60 in an FPGA with two interconnect multiplexers in which most multiplexer input signals are shared but which are controlled separately. Fig. 7 shows a circuit in which the two multiplexers 61 and 62 share five of their six input signals. Fig. 8 shows a layout of the structure of Fig. 7. DETAILED DESCRIPTION OF THE DRAWINGS Fig. 4 shows a circuit diagram of a 6-input multiplexer according to the invention. In Fig. 4, three memory cells, MA, MB, and MC provide the multiplexer control signals. It is not necessary according to the invention that the control signals come from memory cells. The invention also works with switching control signals. However, both the control signals and their complements must be available or made available in order to control the circuit. In the embodiment of Fig. 4, the inverted outputs of memory cells MA and MB are applied on lines A and B to the gates of transistors TOA and TOB and thus control whether input line INO is connected to OUT. The inverted outputs of memory cells A and C determine whether input line INI is connected to OUT. The noninverted outputs of memory cells B and C control whether IN2 is connected to OUT. The inverted outputs of B and C control whether IN3 is connected to OUT. The noninverted outputs of A and C control whether IN4 is connected to OUT. Finally, the noninverted outputs of A and B control whether IN5 is connected to OUT. Memory cell combinations of 000 and 111 are not allowed since they would cause multiple inputs to be selected. With this combination of transistors and control signals, only one input line will be connected to the output line at any one time, and the following truth table results: B OUT 0 0 0 Not allowed 0 0 1 INO 0 1 0 INI 0 1 1 IN2 1 0 0 IN3 1 0 1 IN4 1 1 0 IN5 1 1 1 Not allowed Other combinations similar to Fig. 4 and the above truth table can also be prepared using the principles of the invention. The invention has been described as controlling transistors in the signal path to turn on only when a particular pair of control signals matches. The equivalent result would occur if a value in one of the memory cells was inverted and the connections from that memory cell's output leads were also inverted. And, of course, naming of the input signals and positioning of the six input paths can be different from that shown. Layout Since a goal of the invention is to minimize area, the layout of the resulting structure is also considered. Fig. 5 shows a general layout map of the structure. Fig. 5 is a plan view indicating the physical relationship of the elements in the circuit of Fig. 4. Source and drain wells are indicated by shading lines leaning to the left and poly gates are indicated by shading lines leaning right. Three wells are labeled OUT and are connected together by metal lines, not shown, to provide the output signal OUT shown in Fig. 4. The six input signals INO through IN5 are connected through metal vias, not shown, to the six wells labeled INO through IN5 in Fig. 5. Also labeled in both Fig. 4 and Fig. 5 are transistors T4A, T4C, T5B, and T5A. Poly regions A, B, C, A, B, and C are labeled to correspond to lines of the same label in Fig. 4 which connect memory cells Ml - M3 to transistor gates. Thus the labels allow the reader to determine the correspondence between the circuit diagram of Fig. 4 and the layout diagram of Fig. 5. As can be seen in Fig. 5, it is possible to place two transistor gates on the same signal path closer together when no space is needed for metal contacts. For example two gates 45 and 46 are positioned between the input signal well INO and one of the output signal wells OUT. Similarly, two gates 47 and 48 are placed between input signal well INI and this same output signal well OUT. The space between transistors 45 and 46 is able to be smaller than the space which must be allowed for INO or OUT because no contact region must be provided between region INO and OUT. Four transistors are shown in Fig. 5. The transistor gate regions, labeled T4A, T4C, T5B, and T5A correspond to transistors of the same labels in Fig. 4. Poly regions A, B, and C in Fig. 5 correspond to lines A, B, and C in Fig. 4. This layout requires small area because of the advantageous placement of poly regions for connecting together two gates to be controlled by the same signal. This layout also requires a small silicon area because no contact must be placed between gates 55 and 56 or between gates 57 and 58. Also area is saved by the sharing of the OUT regions with two sets of transistors . Application In some applications, it is desirable to provide two multiplexers which are controlled separately but in which most input signals are shared. Fig. 6 shows an interconnection structure 60 in an FPGA for which this is the case. Interconnection structure 60 selectively connects several interconnect lines to lines A and B and also selectively connects A and B to each other through a bidirectional buffer. The bidirectional buffer comprises two buffers BUFA and BUFB which are controlled to drive signals onto line A and line B, respectively. (Buffers BUFA and BUFB may be either always on or tristate buffers.) Multiplexer 61 can be programmed to apply any of the signals from lines Ll through L5 and line B to buffer BUFA, which buffers the selected signal and applies it to line A. Likewise, multiplexer 62 can be programmed to apply any of the signals from lines Ll through L5 and line A to buffer BUFB, which buffers the selected signal and applies it to line B. Thus five of the six input signals to multiplexers 61 and 62 are the same. The layout is even more efficient when two multiplexers share input signals. Fig. 7 shows a circuit in which the two multiplexers 61 and 62 share five of their six input signals. Multiplexer 61 generates the signal OUT1 and multiplexer 62 generates the output signal OUT2. Input signal INO is used only by multiplexer 61 and input signal IN6 is used only by multiplexer 62. The structure and transistor arrangement in multiplexer 61 is the same as that in Fig. 4. Thus the transistors have the same labels. Multiplexer 62 also has the same arrangement. Only transistors T6A and T6B for controlling the connection of input signal IN6 to OUT2 are labeled. The two multiplexers are separately controlled. Multiplexer 61 is controlled by lines Al, BI, Cl, Al, Bl and Cl from memory cells MAI, MA2, and MA3 in a manner analogous to the control of the multiplexer of Fig. 4. Multiplexer 62 is controlled by memory cells MA2, MB2, and MC2. As in the discussion of Fig. 4, neither set of memory cells may hold the combinations 000 or 111. (Of course, the two signals INO and IN6 may also be the same signal.) Fig. 8 shows a particularly efficient layout of this structure. The layout of Fig. 8 is particularly compact because of the shared wells for both input and output terminals. A comparison of Figs. 5 and 8 shows that the second multiplexer can be had for an area increase of less than 50%. The control lines Al, Bl, Cl, Al, Bl and Cl are partly formed in poly, as shown, and have a comb shape with the comb spine to the left of the transistor region and teeth extending to the right to form transistor gates . Interspersed between gate pairs of multiplexer 61 are control lines A2, B2 , C2, A2, B2 and C2 of multiplexer 62, which also have a comb shape with the comb spine to the right of the transistor region and teeth extending to the left to form transistor gates. Positioned to the left of Fig. 8, but not shown, are memory cells MAI, MBl, and MCI. Positioned to the right of Fig. 8 (not shown) are memory cells MA2 , MB2 , and MC2. Metal lines, also not shown, connect appropriate points in the memory cells to the poly gates. To minimize resistance, multiple metal contacts to a single poly region may be used. Larger Devices The principles described above also apply to a 20-input multiplexer, controlled by five memory cells A, B, C, D, and E. Of the 32 possible combinations of values, only those having two or three O's are allowed. Thus the following 20 combinations can be applied to five memory cells A, B, C, D, and E to select between 20 input signals. A B C D E 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 0 4 0 0 1 1 1 5 0 1 0 0 1 6 0 1 0 1 0 7 0 1 0 1 1 8 0 1 1 0 0 9 0 1 1 0 1 10 0 1 1 1 0 11 1 0 0 0 1 12 1 0 0 1 0 13 1 0 0 1 1 14 1 0 1 0 0 15 1 0 1 0 1 16 1 0 1 1 0 17 1 1 0 0 0 18 1 1 0 0 1 19 1 1 0 1 0 20 1 1 1 0 0 If three of the like values are looked at, then the other two must be different, and they don't have to be looked at. Thus a multiplexer can be constructed in which each signal path includes only three transistors. From the above list, the first path includes transistors controlled by the inverted outputs of the left-most memory cells A, B, and C. This first path will be enabled when these left-most memory cells carry logic 0. The second path is enabled by transistors connected to the inverting outputs of memory cells A, B, and D. The fourth path is enabled by the noninverting outputs of memory cells C, D, and E. The general rule is that when a path is enabled by three O's and two l's, the three O's are looked at and the inverting memory cell outputs are used to control the three transistors in the path. When a path is enabled by two O's and three l's, the three l's are looked at and the noninverting memory cell outputs are used. Other numbers of multiplexer inputs may also be accommodated. A six-input multiplexer can also accommodate five inputs. A 20-input multiplexer can also accommodate fewer inputs. Such variations are intended to fall within the scope of the claims .

Claims: CLAIMS 1. A multiplexer comprising: an output port,- a plurality of input ports; a plurality of paths, each path connecting one input port to the output port; an odd number of signal sources, each signal source providing a control signal for controlling the multiplexer; for each path, a number of pass devices placed in series such that all pass devices must be turned on to connect the corresponding input port to the output port, the number of pass devices on each path being equal to (n+l)/2 where n is the number of signal sources; each pass device being controlled by a selected one of the signal sources such that when the control lines carry a selected number of logical 0 or logical 1 values, a unique input port is connected to the output port. 2. A multiplexer as in Claim 1 wherein the plurality of input ports comprises six input ports, the number of signal sources is three, and the number of pass devices on each path is two. 3. A multiplexer as in Claim 1 wherein the pass devices are transistors. 4. A multiplexer as in Claim 1 wherein each signal source is a memory cell. 5. A multiplexer as in Claim 4 wherein each memory cell drives a pair of control lines, one of which carries the true and and one of which carries the complement of the value stored in the memory cell. 6. A multiplexer comprising: an output port; a plurality of input ports; a plurality of paths, each path connecting one input port to the output port; a number of true control lines, each true control line carrying a control signal for controlling the multiplexer; a number of complementary control lines, each complementary control line carrying the opposite signal of a corresponding true control line; for each path, a number of pass devices placed in series such that all pass devices must be turned on to connect the corresponding input port to the output port, the number of pass devices on the path being between the number of true control lines and the number of true plus complementary control lines; each pass device being controlled by a selected one of the control lines such that when the true control lines carry a selected number of logical 0 or logical 1 values a unique input port is connected to the output port. 7. An interconnect structure for an FPGA comprising: a first interconnect line driven by a first buffer, said first buffer receiving an input signal from a first multiplexer; a second interconnect line driven by a second buffer, said second buffer receiving an input signal from a second multiplexer; a plurality of input lines; said first multiplexer receiving input signals from said plurality of input lines and said second interconnect line, and said second multiplexer receiving input signals from said plurality of input lines and said first interconnect line. AMENDED CLAIMS [received by the International Bureau on 17 September 1997 (17.09.97); original claims 1 and 6 amended; remaining claims unchanged (2 pages)] 1. (Amended) A multiplexer comprising: an output port; a plurality of input ports; a plurality of paths, eacn path connecting one input port to the output port,- an odd number of signal sources, each signal source providing a control signal across a control line for controlling the multiplexer; for each path, a number of pass devices placed in series such that all pass devices must be turned on to connect the corresponding input port to the output port, the number of pass devices on each path being equal to (n+l)/2 where n is the number of signal sources; said plurality of paths comprising at least twice the number of said signal sources; each pass device being controlled by a selected one of the signal sources such that when the control lines carry a selected number of logical 0 or logical 1 values, a unique input port is connected to the output port. 2. A multiplexer as in Claim 1 wherein the plurality of input ports comprises six input ports, the number of signal sources is three, and the number of pass devices on each 3. A multiplexer as in Claim 1 wherein the pass devices are transistors. 4. A multiplexer as in claim 1 wherein each signal source is a memory cell. 5. A multiplexer as in Claim 4 wherein each memory cell drives a pair of control lines, one of which carries the true and one of which carries the complement of the value stored in the memory cell. AMENDEDSHEET(ARTICLE19) (Amended) A multiplexer comprising: an output port; a plurality of input ports; a plurality of paths, each path connecting one input port to the output port; a number of true control lines, each true control line carrying a control signal for controlling the multiplexer; a number of complementary control lines, each complementary control line carrying a signal opposite to a corresponding true control line; for each path, a number of pass devices placed in series such that all pass devices must be turned on to connect the corresponding input port to the output port, the number of pass devices on the path being equal to (n+l)/2, where n is the total number of true control lines; said plurality of paths comprising at least twice the number of true control lines; each pass device being controlled by a selected one of the control lines such that when the true control lines carry a selected number of logical 0 or logical 1 values a unique input port is connected to the output port. An interconnect structure for an FPGA comprising: a first interconnect line driven by a first buffer, said first buffer receiving an input signal from a first multiplexer; a second interconnect line driven by a second buffer, said second buffer receiving an input signal from a second multiplexer; a plurality of input lines; said first multiplexer receiving input signals from said plurality of input lines and said second interconnect line, and said second multiplexer receiving input signals from said plurality of input lines and said first interconnect line. AMENDED SHEET (ARTICLE 19)

Inventors: YOUNG STEVEN P, YOUNG, STEVEN, P.
Applicants: XILINX INC, XILINX, INC.
Application year: 1997
Main classification: H03K17
IPC codes: H03K17, H03K19