DPSK DEMODULATOR

Abstract: A differentially phase shift keyed demodulator (52) for use in an interrogator of a remote intelligent communication system. The demodulator includes a quadrature combiner (64) delaying one of the quadrature signals and thereafter combining the delayed and undelayed signals along with a FIR matched filter (66), which filters the combiner output whereby the differentially phase shift keyed data on a sub-carrier can be demodulated using a simple delay and multiplying scheme (68, 70) in response to the filtered output.

Description: DPSK DEMODULATOR RELATED APPLICATIONS This application is related to provisional application number 0/033,829 filed December 23, 1996 for which priority pursuant to 35 SC 119(e) is claimed. FIELD OF THE INVENTION The presently disclosed subject matter relates to differential phase shift keyed demodulators for use in an interrogator in a remote intelligent communication system. BACKGROUND OF THE INVENTION In a remote intelligent communication system, with reference to Fig. 1 , a host computer 10 communicates across a given communication medium 18 with a selected remote intelligent communications device 14,, for example, of a plurality of remote intelligent communication devices 14 0 , 14,, 14 2 . An interrogator 12 is employed intermediate the host computer TO and communications medium 18 for appropriately coupling the host computer to the medium. Host computer 10 has a library of commands 11 available for configuring and operating the interrogator 12, the remote intelligent communications device 14, and itself. In an exemplary application, host computer 10, via appropriate programming, retrieves appropriate commands from within its library of commands 11 and sends associated command data to interrogator 12 by way of a digital interfacing link 16. Digital interfacing link 16 is an enhanced parallel port (EPP) digital interface. The command forwarded from host 10 to interrogator 12 can be a command for configuring the interrogator, a command for operating interrogator 12, or a command for configuring or operating a a remote intelligent communications device 14. Upon receiving the command, interrogator 12 configures itself appropriately in accordance with the command instructions and/or forwards appropriate data along a forward RF communications link 18 to a remote intelligent communications device 14. Depending upon the type of command, the remote intelligent communications device 14 * may respond with an appropriate return RF transmission 18. If such a reply is received, interrogator 12 extracts digital data from the RF reply signal and forwards the reply message to host computer 10 for further analysis. Remote intelligent communications device 14 may comprise an Ambit™ remote intelligent communications device, available from Micron Communications Inc. of Boise, Idaho. Interrogator 12 receives digital data by way of digital interfacing port 16, which may be an enhanced parallel port. Certain commands of the "Micron RFID Library" 11 are associated with configuring interrogator 12. For example, interrogator 12 may receive a command for structuring appropriate transmit and receive antenna structures. In this regard, a receive antenna structure may include two or more separate antennas selectively configurable for receiving an RF signal. Likewise, transmitting antennas are selectively configurable for enabling two or more transmissions of RF signals away from interrogator 12. Moreover, diversity switches of the transmit and receiver communication paths are respectively configurable in accordance with configuration data received from a digital controller. The diversity switches configure the respective antenna structures of the receiver and transmitter communication links of interrogator 12. Further details of the above-noted communication system can be found in co-pending commonly assigned Application Serial No.08/656, 530, which is hereby incorporated by reference in its entirety. SUMMARY OF THE INVENTION The present invention pertains to a novel differential phase shift keyed demodulator an exemplary use for which is in an interrogator of a remote intelligent communication system of the above-noted type. In accordance with an exemplary embodiment, I and Q outputs are obtained from a quadrature downconverter which are converted to digϊtaf signals and input into a quadrature combiner operating at a single frequency sensed through the use of differential phase shift keyed modulation. Thus, there is only a single frequency present in the sub-carrier. Moreover, the use of the quadrature combiner is important in a backscatter communication system since the phase of the incoming signal is unknown. That is to say, it is impossible to predict whether the recovered signal will appear on the I or Q of the downconverter output. It is also not possible to predict whether the I and Q channels will be in or out of phase with one another. The use of the quadrature combiner eliminates these uncertainties since the output will be the same amplitude regardless of whether the signal is entirely on the I or Q channel or any combination of the two. Moreover, the single signal output is thereafter passed through a FIR matched filter having a square time envelope with taps at the sub-carrier frequency wherein tap values are all of the same magnitude, thus simplifying the implementation of the matched filter. Thereafter, demodulation can be obtained through the use of a simple delay and multiplication scheme. BRIEF DESCRIPTION OF THE DRAWINGS The above-noted and other features of the present invention will be better and more completely understood by studying the following detailed description of presently preferred embodiments together with the appended drawings, of which: FIGURE 1 is a simplified block diagram of a remote communications system for selectively communicating with a particular remote intelligent communication device; FIGURE 2 is a simplified block diagram of an interrogator; FIGURE 3 is a more detailed illustration of the DPSK circuitry of FIGURE 2; FIGURE 4 is a more detailed illustration of the RF circuitry of FIGURE 2; and FIGURE 5 is an illustration of the square envelope of the data and tap values of the FIR matched filter. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The interrogator 26 of Fig. 2, which may be used in a communications system as in Fig. 1 , includes enhanced parallel port (EPP) circuitry 50, DPSK (differential phase shift keyed) circuitry 52, and RF (radio frequency) circuitry 54, as well as a power supply (not shown) and a housing or chassis (not shown). In the illustrated embodiment, the enhanced parallel port circuitry 50, the DPSK circuitry 52, and the RF circuitry 54 respectively define circuit card assemblies (CCAs). The interrogator uses an IEEE-1284 compatible port in EPP mode to communicate with the hose computer 48. The EPP circuitry 50 provides all the digital logic required to coordinate sending and receiving a message with a transponder 14. The EPP circuitry 50 buffers data transmitted from the host computer 10, converts the data to serial data, and encodes it. The EPP circuitry 50 then waits for data from the transponder 14, converts it to parallel, and transfers it to the hose computer 10. In one exemplary embodiment, messages include up to 64 bytes of data. The EPP mode interface provides an asynchronous, interlocked, byte wide, bi-directional channel controlled by a host device. The EPP mode also allows the host computer to transfer, at high speed, a data byte to/from the interrogator within a single host computer CPU I/O cycle (typically 0.5 microseconds per byte). The DPSK circuitry 52 of Fig. 3 receives signals I and Q from the RF circuitry 54 (described below), which signals contain the DPSK modulated sub-carrier. The DPSK circuitry 52 includes anti-aliasing filters 56 and 58 filtering the I and Q signals, respectively, and analog to digital (A/D) converters 60 and 62 respectively coupled to the filters 56 and 58 and respectively converting the filtered signals from analog to digital signals. The DPSK circuitry 52 further includes a combiner 64 coupled to the A D converters 60 and 62, for combining the digital signals. The DPSK circuitry 52 still further includes a FIR matched filter 66, coupled to the combiner 64, which filters the combined signals. The DPSK circuitry 52 also includes delay circuitry 68 and multiplier circuitry 70 coupled to the FIR matched filter 66 for delaying the signal and multiplying the signal with the delayed signal to remove the sub-carrier. Moreover, the DPSK circuitry 52 further includes low pass filter circuitry 72, coupled to the multiplier 70, for filtering the output of the multiplier 70 to remove the 2 times the sub-carrier frequency component. The DPSK circuitry 52 further includes a bit synchronizer 74 coupled to the filter 72 for regeneration of the data clock as well as including lock detect circuitry 76 coupled to the low pass filter 72 and generating a lock detect signal. The data, clock, and lock detect signals are sent to the EPP circuitry 50. The RF circuitry 54 of Fig. 4 interfaces with the transmit and receive antennas X1 , X2, R1 , and R2. Operationally, the RF circuitry modulates the data for transmission to a transponder 14, provides a continuous wave (CW) carrier for communications with the transponder, receives and downconverts the signal received from the transponder unit (which is atiackscatter signal in one preferred embodiment). The RF circuitry 54 also includes a power divider 73, and a frequency synthesizer 75 coupled to the power divider 73. The frequency synthesizer 75 tunes the RF continuous wave carrier for frequency hopping and band selection. The RF circuitry defines a transmitter, and receives data from the EPP circuitry 50. The RF circuitry 54 also includes an amplitude modulation (AM) switch 77 that receives the data from the EPP circuitry 50 and amplitude modulates the data onto a carrier. More particularly, the AM switch 77 turns the RF on and off (ON/OFF KEY). The RF circuitry 54 further includes a power amplifier 79, coupled to the AM switch 77, which amplifies the signal. Additionally included in the RF circuitry 54 is a diversity switch 78, coupled to the power amplifier 79, for transmission of the amplified signal through a selected one of the two transmit antennas X1 and X2. In an alternative embodiment, the switch 78 is coupled to more than two antennas and provides for switching from among the multiple antennas. During continuous wave (CW) transmission for the backscatter mode, the AM switch 77 is left in a closed position. When the interrogator 26 is transmitting in the CW mode, the transponder backscatters the signal with a DPSK modulated sub carrier. This signal is received via one of the two diversity receive antennas R1 and R2. More particularly, the RF circuitry 54 further includes a diversity switch 80 coupled to the receive antennas R1 and R2. In an alternative embodiment, the switch 80 is coupled to more than two antennas and provides for switching from among the multiple antennas. In another alternative embodiment, such as when backscatter communications are not employed, the RF circuitry uses common antennas for both transmission and reception, and selects from multiple available send/receive antennas. The RF circuitry 54 further includes a low noise amplifier (LNA) 82 coupled to the switch 80 for amplifying the received signal. The RF circuitry 54 also includes a quadrature downconverter 84, coupled to the LNA 82, for coherently downconverting the received signal. The RF circuitry 54 still further includes automatic gain controls (AGCs) 86 and 88 coupled to the quadrature downconverter 84. The amplitude of the signals are set using the automatic gain controls 86 and 88 to provide the signals I and Q. The I and Q signals, which contain the DPSK modulated sub-carrier, are passed on to the DPSK circuitry 52 for demodulation. The return link data from the transponder 14 is differential phase shift key (DPSK) modulated onto a 600 KHz sub-carrier wherein 0 data corresponds to one phase and 1 data corresponds to another shifted 180 ° from the first phase. As previously noted, the I and Q signals are lowpass filtered to prevent aliasing in the analog to digital converters and the subsequent digital circuitry. The filtered signals are sampled by the analog to digital converter and thereafter inputted to the quadrature combiner 64. In this regard, the quadrature combiner is implemented by delaying one of the channels a quarter sub-carrier cycle which is summed with the undelayed channel. Since DPSK modulation is used it will be noted that there is only a single frequency present in the sub-carrier. Thus, element 64 is a quadrature combiner at only a single frequency. Moreover, although the data modulation causes some spreading of the signal energy this relatively simple circuit closely approximates a quadrature combiner. It will be noted that the quadrature combiner is important since in a backscatter communication system the phase of the incoming signal is unknown. Nevertheless performing an I and Q downconversion of the RF received signals ensures that the signal is recovered regardless of the phase of the signals. In this regard however, it is impossible to predict whether the recovered signal will appear on the I or Q output or some combination of the two. Moreover, it is equally impossible to predict whether the I and Q channel signals will be in phase or out of phase with one another. By using the above-noted quadrature combiner these uncertainties no longer matter. That is to say, the output will be the same amplitude regardless of whether the signal is entirely on the I or Q channel or any combination of the two. Thereafter, this single signal is processed through a FIR matched filter. Since the data is square in time, the ideal matched fiiferliaving the characteristics illustrated in Fig. 5 is one with a square time envelope and taps at the sub-carrier frequency. Due to the square envelope of the data, the tap values are all the same magnitude, namely, +1 or -1. Such characteristics simplify the implementation of the matched filter to merely inverting or not inverting the sign bit and then doing a summation. As an additional feature since the data is differentially phase shift keyed on a sub-carrier, demodulation can be obtained using a simple delay and multiply scheme as noted above. Thus, if the current bit is of the same phase as the preceding bit, a positive DC value will appear at the multiplier output. On the other hand, if the phase of the current bit is opposite to that of the previous bit, a negative value will appear at the multiplier output. Still further, since the multiplier also generates a 2 times the sub-carrier frequency signal, a low pass filter is used to remove the undesired signal. Thereafter, the demodulated output data is input to bit synchronizer 74, wherein the data clock is recovered. Further details of the above noted bit synchronizer can be found in our co-pending commonly assigned application Serial No. 08/781 ,884, filed December 21 , 1996 which is hereby incorporated by reference in its entirety. While the invention has been described in what is presently considered to be the most practical and preferred embodiments, it is understood that the appended claims are not to be limited to the disclosed embodiments, but on the contrary, are intended to cover modifications, variations and/or equivalent arrangements which would retain any of the novel features and advantages of the invention.

Claims: WHAT IS CLAIMED IS: 1. A differential phase shift keyed demodulator comprising: quadrature input signals supplied to and converted to quadrature digital outputs by analog to digital converters; a quadrature combiner responsive to the quadrature digital outputs for combining said outputs, wherein one of the quadrature digital outputs is delayed with respect to another undelayed output, and wherein the delayed and undelayed quadrature digital outputs are summed to produce combined output signals; a FIR matched filter coupled to the quadrature combiner for filtering the combined output signals, and a time delay and multiplier circuit wherein a current filtered combined output signal is multiplied by a delayed filtered combined output signal to produce a demodulated output signal. 2. A demodulator as in claim 1 wherein the quadrature input signals are differentially phase shift keyed onto a single frequency sub- carrier. 3. A demodulator as in claim 1 wherein the FIR matched filter has a square time envelope 4. A demodulator as in claim 2 wherein the FIR matched filter has a square time envelope and taps at the sub-carrier frequency. 5. A demodulator as in claim 2 wherein the multiplier circuit generates a two times the sub-carrier frequency signal. 6. A demodulator as in claim 5 further including a low pass filter responsive to the multiplier circuit for removing the two times the sub- carrier frequency signal. 7. A demodulator as in claim 1 further including a synchronization circuit of recovering a data clock from the demodulated output signal. 8. In a remote intelligent communication system including a programmable computer and a plurality of remote communication devices connected to the computer via an interrogator and a communications medium, said interrogator including a differential phase shift keyed demodulator, the demodulator comprising: quadrature input signals supplied to and converted to quadrature digital outputs by analog to digital converters; a quadrature combiner responsive to the quadrature digital outputs for combining said outputs, wherein one of the quadrature digital outputs is delayed with respect to another undelayed output, and wherein the delayed and undelayed quadrature digital outputs are summed to produce combined output signals; a FIR matched filter coupled to the quadrature combiner for filtering the combined output signals, and a time delay and multiplier circuit wherein a current filtered combined output signal is multiplied by a delayed filtered combined output signal to produce a demodulated output signal. 9. A system as in claim 8 wherein the remote communication devices are transducers which produce backscatter signals and the system further includes a downconverter for producing said quadrature input signals. 10. A system as in claim 9 wherein the quadrature input signals are differentially phase shift keyed onto a single frequency sub-carrier. 11. A system as in claim 9 wherein the quadrature input signals are filtered prior to being input to the analog to digital converters. 12. A system as in claim 8 wherein the FIR matched " filter has a square time envelope. 13. A system as in claim 9 wherein the FIR matched filter has a square time envelope and has taps at the sub-carrier frequency. 14. A system as in claim 9 wherein the multiplier circuit generates a two times the sub-carrier frequency signal. 15. A system as in claim 14 further including a low pass filter responsive to the multiplier circuit for removing the two times the sub- carrier frequency signal. 16. A system as in claim 8 further including a synchronization circuit for recovering a data clock from the demodulated output signal.

Inventors: OVARD DAVID K, PAX GEORGE E, OVARD, DAVID, K., PAX, GEORGE, E.
Applicants: MICRON TECHNOLOGY INC, MICRON TECHNOLOGY, INC.
Application year: 1997
Main classification: H03D3
IPC codes: H04L1, H04L27