Semiconductor memory device capable of preventing malfunction due to disconnection of column select line or word select line

Abstract: A semiconductor memory device comprises a plurality of column select lines (CSL) and a column decoder (3) for selecting the column select lines and each of the column select lines includes a first column select line (CSLB1) and a second column select line (CSLB2) arranged in parallel to the first column select line and connected to the first column select line at any point.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device. It particularly relates to a column select line having a two layer structure and a clamping circuit which prevent malfunction when a column select line or a word line is disconnected by foreign matters or the like. Description of the Background Art Fig. 10 is a block diagram showing a configuration of a dynamic random access memory (referred to as a "DRAM" hereinafter), a conventional semiconductor memory device. As shown in Fig. 10, the semiconductor memory device is provided with subarrays 1 into which a memory cell array is divided, a row decoder 2 arranged at each subarray 1 for selecting a word line WL, and a column decoder 3 arranged at each subarray 1 for selecting a column select line CSL. Furthermore, the semiconductor memory device shown in Fig. 10 is a DRAM of x4 configuration and has a memory cell array consisting of four subarrays 1. Each subarray 1 has a plurality of word lines WL including a redundant word line, a plurality of pairs of bit lines (not shown) arranged to cross the plurality of word lines WL and including a redundant pair of bit lines, a plurality of column select lines CSL arranged parallel to the plurality of pairs of bit lines and including a redundant column select line for sending a signal for selecting a pair of bit lines, and memory cells (not shown) connected to intersections of word lines WL and the pairs of bit lines. One end of column select line CSL is connected to column decoder 3 and the other end is open. Thus, when column select line CSL is disconnected due to foreign matters or the like, a redundant column select line is substituted for the column select line CSL while the disconnected portion is floating, causing multiselection of memory cells and hence malfunction of the device. Furthermore, a word line WL also has one end connected to row decoder 2 while the other end open. Thus, when word line WL is disconnected due to foreign matters or the like, a redundant word line is substituted for the disconnected word line WL while the disconnected portion is floating, causing multiselection of memory cells and hence malfunction of the device. From Patent Abstracts of Japan, Vol. 16, No. 398, August 19, 1992 a semiconductor memory device is known, comprising a plurality of word lines, wherein each memory cell is connected to two word lines WL1 and WL2 through two gates for a transfer in each cell, the two word lines being short-circuited every 16 bits of memory cells and the short-circuited sections being connected to an auxiliary word line made of a low-resistance material. From Patent Abstracts of Japan, Vol. 13, No. 304, July 12, 1989, a semiconductor memory device is known, comprising a first metal interconnection layer and a second metal interconnection layer, running in parallel in such a way that they are separated in vertical direction and connected via a through-hole, the first and second metal wiring layers being used as bit lines. An object of the present invention is to provide a semiconductor memory device free from malfunction even when a column select line is disconnected due to foreign matters or the like. This object is achieved by a semiconductor memory device according to claim 1. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a configuration of a semiconductor memory device according to a first embodiment of the present invention. Fig. 2 shows a configuration in cross section of one example of the column select line shown in Fig. 1. Fig. 3 shows another example of the configuration of the column select line shown in Fig. 1. Fig. 4 shows a configuration of a semiconductor memory device according to a second embodiment of the present invention. Figs. 5 and 6 are circuit diagrams showing configurations of the clamping circuits shown in Fig. 4. Fig. 7 is a circuit diagram showing a configuration of a circuit for generating a signal RXn. Figs. 8A and 8B are timing charts illustrating a relation between a signal /RAS and signal RXn. Fig. 9 is a circuit diagram showing a configuration of a circuit for generating signals p and /p. Fig. 10 shows a configuration of a conventional semiconductor memory device. DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Fig. 1 shows a configuration of a semiconductor memory device according to a first embodiment of the present invention. As shown in Fig. 1, the semiconductor memory device includes a column decoder 3, and a column select line connected to column decoder 3 and having a two aluminum layer structure. The column select line includes a first layer column select line CSLB and a second layer column select line CSLA connected to the first layer column select line CSLB at any point. Fig. 2 is a cross sectional view of the column select line having a two layer structure shown in Fig. 1. As shown in Fig. 2, the first and second layer column select lines CSLB and CSLA overlaps in the column select line having the two layer structure, and thus its parasitic capacitance is larger than that of a conventional column select line having a one layer structure. Thus, to minimize its parasitic capacitance, the second column layer select line CSLA is overlapped exactly above the first layer column select line CSLB and a width A of the second layer column select line CSLA does not exceed a width B of the first layer column select line CSLB. Thus, even when one layer of the column select line is disconnected by foreign matters or the like, as shown in Fig. 1, the other layer of the column select line can substitute for the disconnected layer and thus multiselection of memory cells due to floating of a disconnected column select line can be avoided. Other than the above two-layer structure, two column select lines CSLB1 and CSLB2 may be arranged in parallel and connected to each other by a connection 5 at any portion, as shown in Fig. 3. Such a structure also allows one column select line CSLB1 or CSLB2 disconnected by foreign matters or the like to be substituted with the other column select line CSLB2 or CSLB1 and thus multiselection of memory cells due to floating of the disconnected column select line can be avoided. It should be noted that the description above is not limited to examples in which the material of each of column select lines CSLA, CSLB, CSLB1 and CSLB2 is aluminum. (Second Embodiment) Fig. 4 shows a configuration of a semiconductor memory device according to a second embodiment of the present invention. As shown in Fig. 4, the semiconductor memory device includes a main pair of word lines MWL and /MWL transmitting complementary signals, a row decoder 2 for selecting the main pair of word lines MWL and /MWL, a secondary word line SWL, a clamping circuit 7 for pulling down a main word line MWL to a ground potential, a clamping circuit 9 for pulling up a main word line /MWL to a power supply potential, and N channel MOS transistors NT1-NT3. Fig. 5 is a circuit diagram showing a configuration of clamping cirucit 7. As shown in Fig. 5, clamping circuit 7 includes an N channel MOS transistor NT4 connected between main word line MWL and a ground node, an N channel MOS transistor NT5 connected between the gate of N channel MOS transistor NT4 and a ground node and having its gate connected to main word line MWL, and a p channel MOS transistor PT1 connected between the gate of N channel MOS transistor NT4 and a power supply node and having its gate receiving a signal /p. Fig. 6 is a circuit diagram showing a configuration of clamping circuit 9. As shown in Fig, 6, clamping circuit 9 includes a p channel MOS transistor PT2 connected between main word line /MWL and a power supply node, and a p channel MOS transistor PT3 connected between the gate of p channel MOS transistor PT2 and a power supply node and having its gate connected to main word line /MWL, and an N channel MOS transistor NT6 connected between the gate of p channel MOS transistor PT2 and a ground node and having its gate receiving a signal p. A signal RXn applied to the drain of n channel MOS transistor NT2 is generated from a signal /RAS, as shown in Fig. 7, and a relation between signal /RAS and signal RXn is illustrated in a timing chart shown in Figs. 8A and 8B. The signal /p applied to the gate of p channel MOS transistor PT1 shown in Fig. 5 and the signal p applied to the gate of N channel MOS transistor NT6 shown in Fig. 6 are complementary signals and generated from signal RXn, as shown in Fig. 9. Furthermore, it is difficult in manufacturing a semiconductor memory device having a main pair of word lines MWL and /MWL and a secondary word line SWL such as a semiconductor memory device according to the present embodiment to backline a word line formed of polysilicon with aluminum. Thus, clamping circuits 7 and 9 are provided at ends of paired main word lines MWL and /MWL opposite to row decoder 2, as shown in Fig. 4. Operation of a semiconductor memory device according to the present embodiment will now be described. When signal /p input to the gate of p channel MOS transistor PT1 in clamping circuit 7 shown in Fig. 5 is activated (low level), p channel MOS transistor PT1 is turned on and the potential of a node f1 attains high level. This causes N channel MOS transistor NT4 to be turned on and the potential of a node e1 attains low level. Then, when signal /p attains inactive high level, p channel MOS transistor PT1 is turned off and thus the potential of node e1 is held at low level. Thus, main word line MWL is pulled down to low level. On the other hand, while signal p attains active high level in clamping circuit 9 shown in Fig. 6, N channel MOS transistor NT6 is turned on and the potential of a node h1 attains low level. This causes p channel MOS transistor PT2 to be turned on and the potential of a node g1 attains high level. Then, when signal p attains inactive low level, n channel MOS transistor NT6 is turned off and thus the potential of node g1 is held at high level. Thus, main word line /MWL is pulled up to high level. The main word line /MWL pulled up to high level causes n channel MOS transistor NT3 shown in Fig. 4 to be turned on and thus secondary word line SWL is clamped at low level. Thus, floating of paired main word lines MWL and /MWL can be avoided even when they are disconnected by foreign matters or the like. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.

Claims: A semiconductor memory device comprising: a plurality of column select lines (CSL); and a column decoder (3) for selecting said column select lines (CSL); characterized in that : each of said column select lines (CSL) includes a first column select line (CSLB1), and a second column select line (CSLB2) arranged in parallel to said first column select line (CSLB1) and connected to said first column select (CSLB1) line at any point.

Inventors: HAYASHIKOSHI MASANORI, OKIMOTO HIROMI, TOBITA YOUICHI, HAYASHIKOSHI, MASANORI, OKIMOTO, HIROMI, TOBITA, YOUICHI
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1997
Main classification: G06F11
IPC codes: G11C29, G11C8