Method for handling interrupts in a high speed I/O controller

Abstract: A method to reduce the rate of interrupts by the central processing unit (CPU) without any loss of interrupts. The method uses two parameters. The first parameter sets the event threshold, which is the maximum value of consecutive events allowed to occur, for example, the maximum number of received data packets before an interrupt is posted (for example, a receive interrupt) to the CPU. The second parameter sets the event time-out time, which is the maximum time an event can be pending before posting an interrupt to the CPU. The second parameter is needed since the flow of events in the system is unpredictable and without the time-out limit, handling of the event can be delayed indefinitely.

Description: Background of the Invention The present invention relates to high speed input/output (I/O) controllers, and more particularly, to a method of handling interrupts using an interrupt mitigation method. As is well known in the art, the function of I/O processing has grown increasingly complex. Users of computer systems and network systems compete for resources simultaneously. This competition, for example, is sometimes by order of request and sometimes based on priority basis. And through it all, it is the CPU function that must arbitrate the momentary allocation of resources to a specific user, provide synchronization and control over the various devices involved, and keep track of the actual data transfer so that the job may ultimately be "put back together", and so that the user can be assured that his or her program actually receives all inputs and transmits all outputs-each to or from the proper place and in the proper order. As is also known in the art, in normal operating environments, a central processing unit (CPU) may be simultaneously communicating with one or more of its external devices (of same or different types), but seldom with all and usually not in any predictable pattern. This requires the establishment of timing and control procedures to effect a proper connection and to provide "momentary interface synchronization" for individual message pulses. For communication (or transmissions) initiated by devices, the device must signal the processor to interrupt the program flow and alert the operating system that an external device needs attention, much like a doorbell rings or a telephone signals that someone outside wishes to communicate with those within. In both cases, action must be taken in a timely fashion to ensure that no signal is unintentionally disregarded and no data are lost, a distinct possibility that occurs when the CPU is simultaneously communicating with several high speed devices. An I/O controller, such as a disk controller or a network controller, typically moves data between a disk subsystem or a network subsystem, and other units of a computer system. When inbound data is received from the subsystem, the controller typically transfers the data to a main memory unit, to await further processing. The memory unit may be connected to a system bus, which is shared by other units of the computer connected thereto. Outbound data, retrieved from the memory unit, are subsequently transferred by the controller to the subsystem. A direct memory access (DMA) function located on the controller directs movement of data through the controller. The I/O controller manages its input and output data streams by moving the data streams from/to a memory via DMA. The I/O controller reports an event on completion of a DMA operation by posting an interrupt. For example, the event may be the completion of transmitting a packet of data or receiving a packet of data. As data rates handled by the I/O controller increases, the amount of interrupts increases. The overall result may be system performance degradation. As is also known, when the CPU receives an interrupt, it does an operation, called "context switching", before executing an interrupt handler program or scheduling the interrupt for future processing. The context of switching operation is time consuming, since the CPU typically stores all data needed to continue execution of the program once it returns from the interrupt routine. As a result, the CPU is utilized in a less effective manner, since normal flow of the program is disrupted causing instruction cache misses to occur. In a system that includes I/O controllers that send a high interrupt rate, the CPU may be overwhelmed, since it will be using a high percentage of its time for interrupt handling. The result is degradation of overall system performance. An example of a system in which interrupts to the CPU are limited, in order to minimise performance degradation, is described in US 5301275. The system comprises one or more host adaptors which serially communicate with a host CPU, using a rate based I/O transfer protocol which reduces interrupts by limiting the number of times per second the CPU may be interrupted. Host adaptors use two system parameters to control I/O latency and memory usage, the first D_INTRPS being the number of interrupts per second, and the second D_IOSIZE which determines how much data may be transferred for each interrupt. To vary the number of interrupts, the parameter D_INTRPS can be selected to be between 0 to a maximum of 20 per second. Summary of the Invention This invention, in its broad form, resides in a method to reduce transmit interrupts in a central processing unit, as recited in claim 1. Another aspect of the invention in a method to reduce receive interrupts as recited in independent claim 6. In accordance with one embodiment of the present invention, a method to reduce transmit interrupt includes the steps of providing a central processing unit (CPU), providing an input/output (I/O) device connected to the CPU, the I/O device having a system bus interface circuit to provide connection to a system bus, a network interface circuit to provide connection to a network system, a buffer memory coupled to the interface circuits to handle a plurality of input and output data streams therebetween, and a direct memory access, (DMA) function device coupled to the interface circuits and the buffer memory implementing in the DMA function device steps including, setting a transmit count limit variable to a threshold of consecutive transmit packets transmitted before posting a transmit interrupt to the CPU, setting a transmit time limit variable to a time-out time before posting the transmit interrupt to the CPU, initializing a transmit count counter and a transmit time counter to zero, waiting for a transmission of a packet of data, upon a transmission of a packet of data, waiting for a predetermined event to occur corresponding to one of the counters being equal to the respective set variable, determining whether the transmit interrupt should be posted to the CPU in response to a predetermined event, and returning to the step of initializing after posting of the transmit interrupt to the CPU. With such a method, the time that a CPU wastes on context switching as a result of interrupts is reduced and overall system performance is enhanced. In accordance with another embodiment of the present invention, a method to reduce receive interrupts includes the steps for providing a central processing unit (CPU), providing an input/output (I/O) device connected to the CPU, the I/O device having a system bus interface circuit to provide connection to a system bus, a network interface circuit to provide connection to a network system, a buffer memory coupled to the inferface circuits to handle a plurality of input and output data streams therebetween, and a direct memory access (DMA) function device coupled to the interface circuits and the buffer memory, implementing in the DMA function device steps including, setting a receive count limit variable to a threshold of packets received before posting a receive interrupt to the CPU, setting a receive time limit variable to a time-out time before posting the receive interrupt to the CPU, initializing a receive count counter and a receive time counter to zero, waiting for a reception of packet data, upon the reception of a packet of data, waiting for a predetermined event to occur corresponding to one of the counters being equal to a respective set variable, determining whether the receive interrupt should be posted to the CPU in response to a predetermined event, and returning to the step of initializing after posting of the receive interrupt to the CPU. Further embodiments of the invention are specified in the dependent claims. Brief Description of the Drawings A more detailed understanding of the invention may be had from the following description of a preferred embodiment, given by way of example, and to be understood in conjunction with the accompanying drawing, wherein: Fig. 1 is a block diagram illustrating a local area network connected through an I/O controller to a system bus; Fig. 2 is a block diagram of the controller of Fig. 1; and Figs. 3A-3B are flowcharts detailing the process performed by the controller in accordance with an embodiment of the invention. Description of the Preferred Embodiments Fig. 1 illustrates a subsystem, such as a local network 10, connected to a node 12 that includes an I/O controller 14, a main memory 16, a central processing unit (CPU) 18, all of which are connected by a system bus 20. For the embodiment of Fig. 1, the I/O controller 14 connects to the system bus 20 through a bi-directional path 22, and connects to the network subsystem 10 through a bi-directional path 24. During a receive operation, data are transferred from the network subsystem 10 into the I/O controller 14 and eventually transferred to the main memory 16 to await processing. Data transferred between the I/O controller 14 and the main memory 16 is performed in accordance with a direct memory access (DMA) transfer on the system bus 20. During a transmit operation, data retrieved from the main memory 16 is transferred from the I/O controller 14 to the network system 10. Upon completion of the DMA operation, for example, completion of transmitting a packet of data or receiving a packet of data, the I/O controller 14 reports an event by posting an interrupt to the CPU 18. When the CPU 18 receives the interrupt, it does an operation called context switching, before executing an interrupt handler program or scheduling the interrupt for future processing. During the context switching, time is consumed because the CPU 18 stores all data needed to continue execution of the program once it returns from the interrupt routine and loads the interrupt routine into its instruction cache (not shown). If the instruction cache is too small, the CPU 18 may need to evict the current program from the instruction cache and load it back on returning form the interrupt routine. Referring now to Fig. 2, the I/O controller 14 is shown to include a buffer memory 30, a DMA function block 31, a system bus interface circuit 32, and a network interface 34. The system bus interface circuit 32 allows data streams to flow from the buffer memory 30 to/from the system bus 20. The network interface circuit 34 allows data streams to flow from the buffer memory 30 to/from the network subsystem 10. The I/O controller 14 manages the input and output of data streams by moving them to/from its buffer memory 30 via DMA 31. Upon completion of each DMA operation, the I/O controller 14 reports the event as an interrupt to the CPU 18. Implementation of the present method resides, for example, in the DMA function block 31 of the I/O controller 14. It may also be implemented in a DMA function block of a system bus adapter (not shown). An objective of the present invention is to reduce the rate of interrupts by the CPU 18 without any loss of interrupts. The invention uses two parameters. The first parameter sets the event threshold, which is the maximum value of consecutive events allowed to occur, for example, the maximum number of received data packets before an interrupt is posted (for example, a receive interrupt) to the CPU 18. The second parameter sets the event time-out, which is the maximum time an event can be pending before posting an interrupt to the CPU 18. The second parameter is needed since the flow of events in the system is unpredictable and without the time-out limit handling of the event can be delayed indefinitely. For example, if only one data packet is received and the event threshold is greater than one, the I/O counter 14 will wait the time specified in the time-out parameter before posting an interrupt to the CPU 18. The interrupt mitigation process employed by the I/O controller 14 in accordance with the invention may be better understood from the flowcharts of Figs. 3A-3B, wherein the following variable are utilized: RCV_CNT_LIMIT: the parameter defines the threshold (N1) of consecutive receive packets before posting a receive interrupt (RI); RCV_TIME_LIMIT: the parameter define the time-out time (N2) following a reception, before posting a receive interrupt (RI); RCV_CNT: counter that counts the amount of consecutive packets before issuing a RI; RCV_TIME: counter that counts the amount of unit times before issuing a RI; WAIT_RCV: state in which the present method waits until the first packet after a RI or reset has been received; WAIT_EVENT: state in which the present method waits until some event occurs (receive a packet or a time unit passes); TX_CNT_LIMIT: the parameter defines the threshold (N3) of consecutive transmit packets before posting a transmit interrupt (TI); TX_TIME_LIMIT: the parameter define time-out time (N4) following a transmission, before posting a TI; TX_CNT: counter that counts the amount of consecutive packets that were transmitted before a TI is issued; TX_TIME: counter that counts the amount of unit times passed after transmission of a packet before a TI is issued; WAIT_TRAN: state in which the present method waits until a packet is transmitted after a TI or reset occurred; WAIT_EVENT: state in which the present method waits until some event occurs (a packet is transmitted or a time unit passed). Referring to Fig. 3A, at step 50, RCV_CNT_LIMIT is set equal to N1 and RCV_TIME_LIMIT set equal to N2. At step 52, the RCV_CNT counter is initialized to zero. At step 54, the process moves to the WAIT_RCV state and continues to wait until a packet of data is received. When a packet of data is received, the process continues at step 56 to the WAIT_EVENT state, wherein it increments RCV_CNT by one at step 58. At step 60, if the RCV_CNT value does not equal the threshold value N1, the process returns to step 56. If the RCV_CNT value equal the limit of N1, an interrupt is posted at step 62, and the process returns to step 52. If, while in the WAIT_EVENT state at step 56, a specified time unit is reached, the process increments RCV_TIME by one step at 64. At step 66, if RCV_TIME value does not equal the threshold value N2, the process returns to step 56. If the RCV_TIME value equals the limit of N2, an interrupt is posted at step 62, and the process returns to step 52. Referring now to Fig. 3B, at step 80, TX_CNT_LIMIT is set equal to N3 and TX_TIME_LIMIT set equal to N4. At step 82, the TX_CNT counter is initialized to zero, and the TX_TIME counter is initialized to zero. At step 84, the process moves to the WAIT_TRAN state and continues to wait until a packet of data is transmitted. When a packet of data is transmitted, the process continues at step 86 to the WAIT_EVENT state, wherein it increments TX_CNT by one at step 88, if a transmission occurs. At step 90, if the TX_CNT value equals the limit of N3, an interrupt is posted at step 92, and the process returns to step 82. If, while in the WAIT_EVENT state at step 86, a specified time unit is reached, the process increments TX_TIME by one at step 94. At step 96, if the TX_TIME value does not equal the threshold value of N4, the process returns to step 86. If the TX_TIME value equals the limit of N4, an interrupt is posted at step 92, and the process returns to step 82. Having described a preferred embodiment of the invention, it will now become apparent, to one skilled in the art, that the other embodiment incorporating its concepts may be used. It is felt, therefore, that this embodiment should not be limited to the disclosed embodiment.

Claims: A method to reduce transmit interrupts comprising the steps of: providing a central processing unit (CPU) (18); providing an input/output (I/O) device (14) connected to the CPU, the input/output (I/O) device having a system bus interface circuit (32) to provide connection to a system bus (20), a network interface circuit (34) to provide connection to a network system (10), a buffer memory (30) coupled to the interface circuits to handle a plurality of input and output data streams therebetween, and a direct memory access (DMA) function device (31) coupled to the interface circuits and the buffer memory; the method being characterized by implementing in the DMA function device, steps including: setting (80) a transmit count limit variable to a threshold of consecutive transmit packets transmitted before posting a transmit interrupt (T1) to the CPU; setting (80) a transmit time limit variable to a time-out time before posting the transmit interrupt to the CPU; initializing (82) a transmit count counter and a transmit time counter to zero; waiting (84) for a transmission of a packet of data; upon a transmission of a packet of data, waiting (86) for a predetermined event to occur, corresponding to one of the counters reaching the respective set variable; determining whether the transmit interrupt should be posted to the CPU in response to the predetermined event; and returning to the step of initializing (82) after posting (92) of the transmit interrupt to the CPU. The method to reduce transmit interrupts according to claim 1, wherein the input/output (I/O) device is an input/output (I/O) controller (14). The method to reduce transmit interrupts according to claim 1, wherein the input/output (I/O) device is a system bus adapter. The method to reduce transmit interrupts according to claim 1, wherein the step of determining whether the transmit interrupt (T1) should be posted to the CPU (18) in response to the predetermined event comprises the steps of: transmitting the data packet; incrementing (88) the transmit count counter by one; returning to the step of determining if the transmit count counter does not equal the transmit count limit variable; and posting (92) the transmit interrupt to the CPU if the transmit count counter equals the transmit count limit variable. The method to reduce transmit interrupts according to claim 4, wherein the step of determining whether the transmit interrupt (T1) should be posted to the CPU (18) in response to the predetermined event comprises the steps of: waiting (86) for a specified time unit; incrementing (94) the transmit time counter by one; returning to the step of determining if the transmit time counter does not equal the transmit time limit variable; and posting (92) the transmit interrupt to the CPU if the transmit time counter equals the transmit time limit variable. A method to reduce receive interrupts comprising the steps of: providing a central processing unit (CPU) (18); providing an input/output (I/O) device (14) connected to the CPU, the input/output (I/O) device having a system bus interface circuit (32) to provide connection to a system bus (20), a network interface circuit (34) to provide connection to a network system (10), a buffer memory (30) coupled to the interface circuits to handle a plurality of input and output data streams therebetween, and a direct memory access (DMA) function device (31) coupled to the interface circuits and the buffer memory; the method being characterized by implementing in the DMA function device, steps including: setting (50) a receive count limit variable to a threshold of consecutive packets received before posting a receive interrupt to the CPU; setting (50) a receive time limit variable to a time-out time before posting the receive interrupt to the CPU; initializing (52) a receive count counter and a receive time counter to zero; waiting (54) for a reception of a packet of data; upon a reception of a packet of data, waiting (56) for a predetermined event to occur, corresponding to one of the counters reaching a respective set variable; determining whether the receive interrupt should be posted to the CPU in response to the predetermined event; and returning to the step of initializing (50) after posting (62) of the receive interrupt to the CPU. The method to reduce receive interrupts according to claim 6, wherein the input/output (I/O) device is an input/output (I/O) controller (14). The method to reduce receive interrupts according to claim 6, wherein the input/output (I/O) device is a system bus adapter. The method to reduce receive interrupts according to claim 6, wherein the step of determining whether the receive interrupt should be posted to the CPU (18) in response to the predetermined event comprises the steps of: receiving the data packet; incrementing (58) the receive count counter by one; returning to the step of determining if the receive count counter does not equal the receive count limit variable; and posting (62) the receive interrupt to the CPU if the receive count counter equals the receive count limit variable. The method to reduce receive interrupts according to claim 9, wherein the step of determining whether the receive interrupt should be posted to the CPU (18) in response to the predetermined event comprises the steps of: waiting (86) for a specified time unit; incrementing (64) the receive time counter by one; returning to the step of determining if the receive time counter does not equal the receive time limit variable; and posting (62) the receive interrupt to the CPU if the receive time counter equals the receive time limit variable.

Inventors: KLEIN PHILIPPE, PAUL GIDEON, WERTHEIMER AVIAD, KLEIN, PHILIPPE, PAUL, GIDEON, WERTHEIMER, AVIAD
Applicants: HEWLETT PACKARD DEVELOPMENT CO, HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Application year: 1997
Main classification: G06F13
IPC codes: G06F13