A METHOD OF AND AN ARRANGEMENT FOR CONTROLLING AN OSCILLATOR

Abstract: A method and an arrangement for controlling a radar oscillator for use in the traffic field, in particular for a car radar, for generating a linear frequency sweep. A phase-locked linearisation loop generates a linear frequency sweep controlling a phase-locked oscillator loop, which has a considerably broader bandwidth than the linearisation loop.

Description: A METHOD OF AND AN ARRANGEMENT FOR CONTROLLING AN OSCILLATOR The present invention relates to a method and an arrangement for controlling a radar oscillator for gene ¬ rating a linear frequency sweep by employing a phase- locked loop. The method and the arrangement are intended for use in the traffic field, preferably in radar of the FM/CW type, and can, for example, be part of a car radar system. In the application fields mentioned above, it is desirable to be able to achieve extremely linear fre- quency sweeps within a broad bandwidth area. Inadequacies of the controlled oscillator must not damage the linear sweep. The object of the present invention is to provide a method and an arrangement which fulfil the desirable characteristics mentioned above. The objecc of the invention is achieved by a method and an arrangement which employ at least two phase-locked loops, one of the phase- locked loops, the linearisation loop, being utilised to generate a linear frequency sweep and the other phase- locked loop, the oscillator loop, utilising the linear sweep generated in the linearisation loop as a reference signal . According to the invention, two phase-locked loops are employed. One of the phase-locked loops, the lineari- sation loop, has a narrov; bandwidth and provides considerable suppression of undesirable signals. The oscillator signal generated in the linearisation loop is subsequently utilised in the second phase-locked loop, the oscillator loop, which has a much broader bandwidth. By virtue of the broad bandwidth of the oscillator loop, phase noise, among other things, is suppressed in the controlled oscillator. According to the invention, the linearisation loop advantageously has a bandwidth in the kHz range, typically between about 10 and about 100 kHz. Furthermore, according to the invention the oscil- lator loop advantageously has a bandwidth in the MHz range, typically between about 5 and about 20 MHz, specifically about 10 MHz. The oscillator frequency is preferably n the GHz range, typically between 70 and 80 GHz. According to an advantageous method, the linear frequency sweep generated in the linearisation loop is generated at a lower frequency than the oscillator frequency for the controlled oscillator. Thereby, the linearisation loop is allowed to work more slowly, which puts less demand on the components which are included in the linearisation loop. Said lower frequency for the linearisation loop is advantageously between about 100 and 1000 MHz, preferably between about 500 and about 700 MHz. According to an advantageous embodiment, the linea- risation loop comprises a phase detector, whose output by the intermediary of a loop filter is coupled to a control input on the oscillator of the linearisation loop and whose one input is coupled to a clock reference and whose other input is connected to the output on the oscillator of the linearisation loop by the intermediary of a variable frequency divider. In this connection, the variable frequency divider advantageously consists of an 1/n counter. The introduction of digital means allows an extremely linear ramp to be generated on the output of the oscillator of the linearisation loop. According to a suitable embodiment, the counting interval n of the 1/n counter is adapteα to be changed in a set pattern. According to yet another embodiment of the arrange- ment according to the invention, the oscillator loop comprises a phase detector, whose output is coupled to the controlled oscillator by the intermediary of a loop fil- ter and whose one input is connected to the output on the oscillator of the linearisation loop by the intermediary of a first frequency divider and whose other input is connected to the output on a mixer by the intermediary of a second frequency divider, which mixer on the input side is connected to the output on the controlled oscillator and the output on another oscillator. Because of the large bandwidth of the oscillator loop, high suppression of phase noise in the oscillator is achieved. In addition, the oscillator frequency becomes independent of variations in the load impedance, so-called pulling. The invention will be described in more detail below by way of an embodiment with reference to the accompanying drawings, in which Fig. 1 shows a schematic block diagram of a radar arrangement with an arrangement according to the invention for controlling an oscillator, Fig. 2 shows, in the form of a schematic block diagram, an embodiment of an oscillator control arrangement according to the invention, Fig. 3 shows the embodiment according to Fig. 2 in the form of a more detailed block diagram, Fig. 4 shows an example of an ideally linear frequency sweep obtained from the linearisation loop of the oscillator control arrangement to be used as a reference signal for the oscillator loop of the oscillator control arrangement, and Fig. 5 shows a table with examples of frequency values for an included voltage-controlled oscillator and the corresponding division factors. The radar arrangement 4 shown in Fig. 1, which is suitable for use in car radar equipment, comprises an antenna 6, a transmitter part 7 and a receiver part 8. The radar arrangement preferably operates with FM/CW technology. The antenna 6 is preferably installed in the front of the vehicle. The transmitter part includes an oscillator control arrangement 9 and an oscillator 10. Preferably, the oscillator generates a signal in the gigahertz range, e.g. 77 GHz, which by the intermediary of a directional coupler 11 and a circulator 12 is supplied to the antenna 6. The oscillator 10 can consist of a Gunn diode oscillator or another oscillator which is suitable m these circumstances. The reflected signal received by the antenna is led by the intermediary of the circulator 12 to a mixer 13, where the siqnal received is mixed with the signal transmitted. After amplification 14, filtration 15 and signal processing 16, the distance r and the direction α to the vehicle in front, among other things, can be obtained according to known radar principles, as well as information about the speed and acceleration of the vehicle in front if needed. The oscillator control arrangement 9 in Fig. 2 comprises two phase-locked loops 20, 40, henceforth called linearisation loop 20 and oscillator loop 40. The linearisation loop 20 includes a phase detector 21. The one input of the phase detector is connected to a reference signal F ref supplied by the block 22 and the other input is connected to the output of a voltage-controlled oscillator 23 by the intermediary of a frequency divider 24 in the form of an 1/n counter. The output signal on the phase detector 21 controls the voltage-controlled oscil- lator 23 by the intermediary of a loop filter 25. The 1/r counter 24 functions as a variable frequency divider. In coaction, the components included in the linearisation loop generate a signal in the form of linear frequency sweeps on the output of the voltage-controlled oscillator 23 whicn ideally can have the appearance shown in Fig. 4. According to Fig. 4, which shows the frequency f of the output signal on the voltage-controlled oscillator 2 as a function of time, ideally, a linear frequency sweep which starts at the time t 0 and ends at the time ti is achieveα. At the time ti, the signal returns to the starting level which applied at the time t 0 and then remains at this starting level until the time t 2 when a new frequency sweep is started which lasts until the time t . Henceforth, the process is repeated in a corresponding manner. The signal on the output of the voltage-controlled oscillator 23 is employed as a reference signal in the oscillator loop 40 and is supplied to the input on a phase detector 42 by the intermediary of a frequency divider 43. The other input on the phase detector 42 is connected to a mixer 45 by the intermediary of another frequency divider 44. One input of the mixer 45 is connected to the oscillator 10 and the other input is connected to a permanently tuned oscillator 46. An intermediate frequency signal IF is achieved on the output of the mixer 45. The phase detector 42 controls the oscil- lator 10 by the intermediary of a loop filter 47. The oscillator control arrangement will be described below in more detailed block diagram form with reference to Fig. 3. In accordance with Fig. 3, the output signal of the Gunn diode oscillator 10 is mixed with the output signal from the oscillator 46 in order to generate an intermediate frequency signal IF. The output signal of the oscillator 10 is suitably m the gigahertz range and the intermediate frequency signal generated is given a fre- quency below 1 GHz. The intermediate frequency signal is divided by Nl in the frequency divider 44 and is fed to the phase detector 42 where the signal is compared with a signal from the voltage-controlled oscillator 23 functioning as a reference oscillator. The phase detector 42 generates an output signal in the form of an error signal which corrects the frequency of the Gunn diode oscillator. Prior to reaching the Gunn diode oscillator, the output signal of the phase detector 42 goes through filtration in a loop filter amplifier 53 and is isolated through a buffer amplifier stage 54. In order to maximise the Q value of the oscillator 23, the oscillator circuit is based on a tuned L-C resonant circuit. A buffer amplifier 48 isolates the voltage- controlled oscillator 23 from the phase detector 42 and amplifies the output signal from the voltage-controlled oscillator. In this way, so-called pulling is prevented. A frequency divider 43 divides the output signal from the voltage-controlled oscillator by N2. A sample and hold circuit 49 senses the control vol- tage on a capacitor 50 before the frequency sweep starts and charges the voltage back onto the capacitor when the frequency sweep is finished. The circuit 49 also opens the contact 51 when the sweep is over and closes the contact when the linearisation loop has been locked in. By the use of the circuit 49 a quick return of the frequency of the Gunn diode oscillator is achieved and the transmission of unwanted frequencies during the locking period of the linearisation loop is avoided. In order to protect the Gunn diode oscillator against high transient voltages, there is a safety circuit 52 which earths the voltage if the voltage of the Gunn diode oscillator becomes too high. In the linearisation loop, the frequency sweep is achieved as follows. The oscillator signal isolated by the buffer amplifier 48 is fed to the frequency divider 24 in the form of an 1/n counter which counts n steps (n=Nmin) and then gives a pulse to the phase detector 21. The phase detector compares the pulse with a clock reference from a crystal-controlled reference oscillator 26. In the embodiment shown, the reference oscillator 26 generates a high-frequency clock reference which is subsequently frequency divided to 1 MHz in a frequency divider 36. Subsequently, the counter 24 again counts tc n=Nmin and gives off a pulse to the phase detector 21. The second pulse from the counter loads a new value into the counter, n=Nmin+l. Now, the counter counts an extra cycle before giving off the pulse to the phase detector, i.e. the voltage-controlled oscillator is forced to a higher frequency according to a set pattern. A number of other examples of set patterns are possible. This process continues until the timer 27 stops the process and subsequently loads the 1/n counter with a pattern of bigger steps, which in a quick and controlled manner return the counter to the starting value n=Nmιn. This value is maintained until the timer receives a synchronisation signal on the input 39 and once again starts the counting procedure. In this context, it will be noted that the logic which controls the division factor n must be fast enough for the value n to be changeable without losing a cycle from the voltage-controlled oscillator. This means that a new value for n has to be loaded while the counter is counting. Fig. 5 shows a table with an example of some values of the desired oscillator frequency, the VCO frequency, and the division factor n. The first value of n in the table corresponds to the value N m mentioned above. The output of the phase detector 21 consists of a charging pump with an output current lo which corrects the output voltage sweep of the error amplifier 29. The output signal is subsequently filtered in amplif iters and elliptic filters 30 to remove remainders of the clock reference from the reference oscillator 26 in the input voltage of the voltage-controlled oscillator. When studying the table in Fig. 5, third line, one finds that the ratio between the desired VCO frequency and the division factor n is not 1 MHz. The counter 24 counts one quarter of a VCO period too little before giving off an output pulse to the phase detector 21. In order to compensate for this error, another charging pump 28 has been added to the block diagram. The charging pump 28 is adapted to be active during a VCO period with an output current lo/4. The compensation signal is supplied to every other output pulse from the counter 24. The sup- ply of the compensation signal is controlled by the timer 27 in coaction with a counter 35 (1/N4 counter). The loop bandwidth required depends on the linearity of the voltage-controlled oscillator 23, but 50 kHz is considered sufficient. An alternative method for quickly restoring the frequency to the starting value is to employ a sample and hold circuit 31 which senses the voltage of a capacitor 32 when the frequency sweep starts. When the frequency sweep ends, a contact 33 is opened and the capacitor 32 is discharged until it reaches the voltage of the sample and hold circuit 31. Then, the contact 33 is closed and the loop tries to lock in the voltage-controlled oscillator 23. The circuit 31 supports the linearisation loop during the frequency restoration after the frequency sweep and facilitates quick locking. A ramp generator 34 integrates a direct current voltage Uref in order to generate a voltage ramp which is added to the control voltage. The voltage ramp is gene- rated during the frequency sweep. When the sweep ends, a contact 37 is closed in order to discharge a capacitor 38 lying above the ramp generator 34. When the sweep starts, the contact should be open. The purpose of this ramp is to reduce the error signal from the phase detector 21 and to reduce the transient when the sweep starts.

Claims: CLAIMS 1. A method for controlling a radar oscillator for use in the traffic field, in particular for a car radar, for generating a linear frequency sweep by the use of a phase-locked loop, c h a r a c t e r i s e d in that least two phase- locked loops are formed, the one phase-locked loop, the linearisation loop, being utilised to generate a linear frequency sweep and the other phase-locked loop, the oscillator loop, utilising the linear frequency sweep generated in the linearisation loop as a reference signal, and the linearisation loop being limited to a lower bandwidth than the oscillator loop. 2. A method as set forth in claim 1, c h a r a c t e r i s e d in that the linearisation loop is limited to a bandwidth in the kHz range, preferably between about 10 and about 100 kHz, specifically about 50 kHz, and the oscillator loop is limited to a bandwidth in the MHz range, preferably between about 5 and about 20 MHz, specifically about 10 MHz. 3. A method as set forth in any one of the preceding claims, c h a r a c t e r i s e d m that the linear fre- quency sweep generated in the linearisation loop is generated at a lower frequency than the oscillator frequency for the controlled oscillator. 4. An arrangement for controlling a radar oscillator, for use in the traffic field, in particular for a car radar, for generating a linear frequency sweep by employing a phase-locked loop, c h a r a c t e r i s e d in that the arrangement comprises at least two phase- locked loops, the one phase-locked loop, the linearisation loop, being adapted to generate a linear frequency sweep and the other phase-locked loop, the oscillator loop, being adapted to utilise the linear frequency sweep generated in the linearisation loop as a reference sig- nal, and the linearisation loop having a lower bandwidth than the oscillator loop. 5. An arrangement as set forth in claim 4, c h a r a c t e r i s e d in that the linearisation loop has a bandwidth in the kHz range, preferably between about 10 and about 100 kHz, specifically about 50 kHz, and that the oscillator loop has a bandwidth in the MHz range, preferably between about 5 and about 20 MHz, specifically about 10 MHz. 6. An arrangement as set forth in any one of claims 4 or 5, c h a r a c t e r i s e d m that the linearisation loop comprises a phase detector whose output by the intermediary of a loop filter is coupled to a control input on the oscillator of the linearisation loop and whose one input is coupled to a clock reference and whose other input is connected to the output on the oscillator of the linearisation loop by the intermediary of a variable frequency divider. 7. An arrangement as set forth in claim 6, c h a r a c t e r i s e d m that the variable frequency divider consists of an 1/n counter. 8. An arrangement as set forth in claim 7, c h a r a c t e r i s e d in that the counting interval n of the 1/n counter is adapted to be changed in a set pat- tern. 9. An arrangement as set forth in any one of claims 4-8, c h a r a c t e r i s e d in that the oscillator loop comprises a phase detector whose output is coupled to the controlled oscillator by the intermediary of a loop filter and whose one input is connected to the output of the oscillator of the linearisation loop by the intermediary of a first frequency divider and whose other input s connected to the output of a mixer by the intermediary of a second frequency divider, which mixer on the input side in connected to the output on the controlled oscillator and the output of another oscillator.

Inventors: ECKERSTEN CHRISTER, OLOFSSON JOAKIM, ECKERSTEN, CHRISTER, OLOFSSON, JOAKIM
Applicants: CELSIUSTECH ELECTRONICS AB, ECKERSTEN CHRISTER, OLOFSSON JOAKIM, ECKERSTEN, CHRISTER, OLOFSSON, JOAKIM
Application year: 1997
Main classification: H03L7
IPC codes: G01S7, G01S13, H03B23, H03L7, H04B1