Code multiplexing/reading apparatus

Abstract: A code multiplexing/reading apparatus includes a first register (22a-22g). Two codes that reside in a predetermined relationship are outputted from the first register (22a-22g), which are superimposed on a video signal to be recorded by operation of switches (SW1-SW7). Consequently, a video recording device (26) records a code-multiplexed video signal on a recording medium (28). When the code-multiplexed video signal is reproduced from the medium (28) by a video reproducing device (26), two codes taken out of the reproduced video signal are compared with each other by a comparator (42). When the two codes are "1001101" and "0110010", the inversion of the former code agrees with the latter code. Therefore, the former code is outputted as a predetermined code from a second register (46).

Description: This invention relates to code multiplexing/reading apparatuses, and more particularly to a code multiplexing/reading apparatus adapted to multiplex on an video signal a code, for example, for distinguishing from which monitor camera a video signal is outputted or representing a time hour at which a video signal is outputted, as well as read that code out of the video signal multiplexed therewith. There is shown in Figure 8 and Figure 9 one example of a conventional code multiplexing/reading apparatus of this kind. Referring to Figure 8, during recordation a code stored by registers 2a-2g is multiplexed on respective predetermined two horizontal lines within a vertical blanking period contained in a composite video signal so that the code is thereafter recorded on a video tape (not shown) by a VTR3. During reproduction, the composite video signal is reproduced by the VTR3 as shown in Figure 9, and then outputted through a drop-out detection circuit 3a. That is, where it is impossible to properly reproduce a signal due to damages or marks on a video tape, the signal is subjected to addition at its drop-out portion with using a signal corresponding to that of the preceding line, thereby being outputted. The two codes multiplexed on the composite video signal are detected through a comparator 4 and a code fetching circuit 5, and they are then compared by a comparing circuit 6. If they are coincident with each other, the first multiplexed code is outputted through a register 7. When reproducing the composite video signal that is multiplexed with a code, e.g., "1001101", even if a code first recorded is partly lost as shown in Figure 10(A), the detected two codes will not coincide with each other as shown in Figure 10(E) and Figure 10(F). In this manner, an erroneous code, i.e. a code "1000001" is prevented from being outputted through the register 7. In the prior art, however, if the first code is partly lost and further the next code be disappeared of its entirety as shown in Figure 11(A), the first code with partly lacking is utilized for addition to a drop-out period in the latter half. In such a case, there happens coincidence between the two detected codes as shown in Figure 11(E) and Figure 11(F), resulting in outputting an erroneous code through the register 7. A similar device is disclosed in EP-A-0 515 014 in which the same code is written twice during recording such that the reproduced codes are coincident with each other. It is therefore a primary object of the present invention to provide a code multiplexing/reading apparatus which is capable of preventing against outputting an erroneous code even when both of two codes are lost partly or in the entirety thereof. It is another object of the present invention to provide a code reading device that can prevent against erroneously outputting a code therefrom even when both two codes are lost partly or in the entirety thereof. It is further object of the present invention to provide a video reproducing device that can prevent against erroneously outputting a cede therefrom even when both two codes are lost partly or in the entirety thereof. It is still further object of the present invention to provide a video recording and reproducing apparatus that can prevent against erroneously outputting a code therefrom even when both two codes are lost partly or in the entirety thereof. These objects are achieved by a reading device as defined in claim 1; the dependent claims are related to further developments of the invention. The two codes that are different are multiplexed during a vertical blanking period of the video signal by the multiplexing means. Here, the two codes involve for example a first code that is not inverted and a second code that is inverted in bit partly or in the entirety thereof. The video signal multiplexed with these two codes is recorded on the recording medium by means of the signal record means. The video signal multiplexed with codes is reproduced out of the recording medium by the signal reproducing means and determined by the code determining means whether the two codes involved are in the predetermined relationship or not. That is, the first code is stored by a storing means, the second code is inverted in bit partly or the entirety thereof, and an output of the storing means and an output of the inverting means are compared each other by a comparing means. If the two codes are determined that they are in the predetermined relationship, that is, these codes are determined coincident with each other,-the-code output means outputs a predetermined code. Here, the predetermined code refers, for example, to the first code. In accordance with the present invention, since a predetermined code is outputted by the code output means only when the two reproduced codes reside in a predetermined relationship. Therefore, it is possible to prevent against outputting an erroneous code even when both two codes are lost partly or in the entirety thereof. The above described objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. Figure 1 is a block diagram showing one part of an embodiment of the present invention; Figure 2 is a waveform diagram showing a signal during a vertical blanking period; Figure 3 is a block diagram showing another part of the embodiment of the present invention; Figure 4 is a block diagram showing part of the Figure 1 embodiment; Figure 5(A) is a waveform diagram showing a horizontal synchronization signal, Figure 5(B) is a waveform diagram showing a timing pulse, Figure 5(C) is a waveform diagram showing codes multiplexed on a composite vide signal, Figure 5(D) is a waveform diagram showing a composite video signal recorded by or reproduced from a VTR, Figure 5(E) is a waveform diagram showing a code contained in the composite video signal reproduced, Figure 5(F) is a waveform diagram showing an enable signal, Figure 5(G) is an illustrative diagram showing a code outputted from a register 38, Figure 5(H) is an illustrative diagram showing a code inverted by an inverting circuit, and Figure 5(J) is an illustrative diagram showing an output code; Figure 6(A) is a waveform diagram showing a drop-out detecting signal, Figure 6(B) is a waveform diagram showing a code contained in the reproduced composite video signal, Figure 6(D) is a waveform diagram showing an enable signal, Figure 6(E) is an illustrative diagram showing a code outputted from a register 38, Figure 6(F) is an illustrative diagram showing a code inverted by an inverting circuit, and Figure 6(G) is an illustrative diagram showing an output code; Figure 7(A) is a waveform diagram showing a drop-out detection pulse, Figure 7(B) is a waveform diagram showing a reproduced composite video signal, Figure 7(C) is a waveform diagram showing a code contained in the reproduced composite video signal, Figure 7(D) is a waveform diagram showing an enable signal, Figure 7(E) is an illustrative diagram showing a code outputted from the register 38, Figure 7(F) is an illustrative diagram showing a code inverted by an inverting circuit, and Figure 7(G) is an illustrative diagram showing an output code; Figure 8 is a block diagram showing one part of a prior art; Figure 9 is a block diagram showing another part of the prior art; Figure 10(A) is a waveform diagram showing a drop-out detection pulse, Figure 10(B) is a waveform diagram showing a reproduced composite video signal, Figure 10(C) is a waveform diagram showing a code contained in the reproduced composite video signal, Figure 10(D) is a waveform diagram showing an enable signal, Figure 10(E) is an illustrative diagram showing a code outputted from the register 38, Figure 10(F) is an illustrative diagram showing a code inverted by the inverting circuit, and Figure 10(G) is an illustrative diagram showing an output code; and Figure 11(A) is a waveform diagram showing a drop-out detection pulse, Figure 11(B) is a waveform diagram showing a reproduced composite video signal. Figure 11(C) is a waveform diagram showing a code contained in the reproduced composite video signal, Figure 11(D) is a waveform diagram showing an enable signal, Figure 11(E) is an illustrative diagram showing a code outputted from the register 38, Figure 11(F) is an illustrative diagram showing a code inverted by the inverting circuit, and Figure 11(G) is an illustrative diagram showing an output code. Referring to Figure 1, a code multiplexing/reading apparatus 10 of this embodiment includes a synchronization pulse separation circuit 12 where separation is done for a vertical synchronization pulse and a horizontal synchronization signal contained in a composite video signal as shown in Figure 2. Receiving the vertical synchronization pulse, the pulse generation circuit 14 delivers, based on that pulse as a reference, to switches SW1-SW7 timing pulses that serve as a timing signal having rise portions fallen within a predetermined 1H time period of a time duration A in a vertical blanking period excepting an equalizing period and vertical synchronization period. The pulse generation circuit 14 also provides respective timing pulses, that rise within a predetermined 1H period and the following 1H period, as a read-out-switching signal and an enable signal to registers 22a-22g, a switch SW8 and a counter 18. Therefore, the timing pulses delivered to the registers 22a-22g, the switch SW8 and the counter 18 vary as shown in Figure 5(B) with respect to the horizontal synchronization signal as shown in Figure 5(A). Meanwhile, a PLL circuit 16 receives the horizontal synchronization signal from the synchronization pulse separation circuit 12, and delivers to the counter 18 a pulse obtained by frequency-dividing the horizontal synchronization signal by 7 and having a phase locked to a phase of the horizontal synchronization signal. The counter 18 repeats increment from "0" to "6" according to a clock supplied from the PLL circuit 16. The registers 22a-22g are each stored with 1 bit of a 7-bit code "1001101" so that the code is read out twice based on a timing pulse as shown in Figure 5(B). The switches SW1-SW7 are put into connection to the registers22a-22g for the first half one 1H period of the successive 2H period, and connected to inverting circuits 24a-24g for the following 1H period. Consequently, the selector 20 is supplied with the code "1001101" as a first code during the first 1H period, and supplied with a code "0110010" as a second code during the following 1H period. The selector 20 selects, one by one, bit data respectively supplied from the switches SW1-SW7 depending on a count value given from the counter 18. The selector 20 firstly outputs, bit by bit, the first code "1001101", and then outputs, bit by bit, the second code "0110010". That is, the selector 20 outputs codes as shown in Figure 5(C). Since the switch SW8 is placed into connection to the selector side when the timing pulse as shown in Figure 5(B) is at a high level, the two codes outputted from the selector 20 are multiplexed over the composite video signal as shown in Figure 5(D). In this manner, the composite video signal multiplexed with the codes is supplied to a recording apparatus such as a VTR 26 where it is recorded on a recording medium such as a video tape 28 by means of a signal record circuit 26a. Referring to Figure 3, during reproduction the VTR 26 reproduces the signal out of the video tape 28 through a signal reproducing circuit 26b so that a drop-out portion is added by the signal. Specifically, a drop-out portion is detected on the reproduced signal by a drop-out detection circuit 26d as shown in Figure 4 so that a switch SW9 is controlled by a drop-out detection signal. By doing so, the switch SW9 is connected to the side of a demodulation circuit 26e for a period that no dropping out is found, while the switch SW9 is connected to the side of a 1H delay circuit 26f for a period of detecting dropping out. Therefore, the drop-out portion is added by a signal that corresponds to a portion on the preceding line. For example, if a drop-out detection pulse is outputted as shown in Figure 6(A) or Figure 7(A), a composite video signal as shown in Figure 6(B) or Figure 7(B) is outputted through the switch SW9. The composite video signal outputted from the VTR 26 is then compared by a voltage signal at a level of 50IRE, so that the first code and the second code contained in the composite video signal are detected as shown in Figure 5(E), Figure 6(C) and Figure 7(C). On the other hand, the synchronization pulse separation circuit 30 detects a vertical synchronization pulse contained in the composite video signal. A pulse generation circuit 36 in turn supplies, based on the detected vertical synchronization pulse as a reference, two kinds of timing pulses and a latch signal to a code fetching circuit 34, a register 38 and a latch circuit 44. Specifically, the code fetching circuit 34 is supplied with pulses of totally 14 in number, as an enable signal, that are superimposed with the first and second codes to have rise portions within a period shown in Figure 5(F), Figure 6(D) and Figure 7(D). The register 38 is supplied with 7 pulses as a writing signal that have rise portions within a period of being superimposed by the first code. The latch circuit 44 is supplied with a latch signal for latching an output of the comparing circuit 42 after the 14 pulses are outputted to the code fetching circuit 34. The code fetching circuit 34 converts the first code and the second code from the comparator 32 into parallel data according to the enable signal given from the pulse generation circuit 36, thereby supplying the respective parallel data to the register 38 and the inverting circuit 40. The register 38 stores only the first code according to the writing signal from the pulse generation circuit 36, to output the first code in synchronization with outputting of the second code from the code fetching circuit 34, i.e., at timing as shown in Figure 5(G), Figure 6(E) and Figure 7(E). On the other hand, the inverting circuit 40 outputs an inverted version of the second code at timing as shown in Figure 5(H), Figure 6(F) and Figure 7(F). Consequently, the comparator 42 compares the first code supplied from the register with the inversion of the second code from the inverting circuit 40. The comparator 42 outputs a high level signal when they are coincident, and a low level signal when not coincident. In the latch circuit 44, the output from the comparator 42 is latched by the latch signal from the pulse generation circuit 36, and a latch output is delivered as an enable signal to the register 46. Consequently, the first code outputted from the register 38 is stored by the register 46 only when the latch circuit 44 has a high level output, and simultaneously the first code is outputted therefrom. On the other hand, when the output of the latch circuit 44 is at a low level, the first code from the register 38 is not stored by the register 46 so that no output is supplied from the register 46 or otherwise the first code already stored therein is outputted. That is, if the first code and the inversion of the second code are coincident with each other as shown in Figure 5(G) and Figure 5(H), the first code is outputted from the register 46 as shown in Figure 5(J). However, when the first code and the inversion of the second code are not coincident as shown in Figure 6(E) and Figure 6(F) as well as Figure 7(E) and Figure 7(F), no outputting is made from the register 46 as shown in Figure 6(G) and Figure 7(G) or otherwise the first code already stored is outputted therefrom. In this manner, during recordation the pulse generation circuit 14 performs control on the switch SW8 to thereby multiplex a first code and a second code that is an inversion of the first code on a composite video signal within a vertical blanking period thereof. The multiplexed signal is then recorded on a video tape 28 by means of the VTR 26. On the other hand, during reproduction the first code and the second code are outputted from the code fetching circuit 34 so that the comparator 42 is supplied with the first code and the inversion of the second code in synchronism with each other. Only when these codes are coincident, the comparator 42 outputs a high level signal, whereby the first code supplied from the register 38 is outputted through the register 46. Meanwhile, if the first code and the inversion of the second code are not coincident, the latch circuit 44 outputs a low level signal so that no output is delivered by the register 46. In this case, however, if the register 46 is already stored with the first code, that code is outputted therefrom. That is, the latch circuit outputs one latch signal per one field. Consequently, if the latch signal is at a high level, the content or the output code of the register 46 is updated in that timing. However, if the latch signal is at a low level, the register 46 outputs the first code that is already stored therein. According to the present embodiment, since the first code is outputted when the first code and the second code reside in a predetermined relationship, an erroneous code is prevented from being outputted. Incidentally, in the present embodiment, the second code is created by inverting the entire bits of the first code. However, the second code may be created by inverting parts of bits of the first code such as even numbered bits or odd numbered bits in the first code. Furthermore, although in the present embodiment, the code multiplexing/reading apparatus 10 is connected outside of the VTR 26, it is also possible to install the code multiplexing/reading apparatus inside of the VTR. Also, the first code and the second code are multiplexed continuously within the period A contained in the vertical blanking period. However, these two codes may be multiplexed within the equalizing period or the vertical blanking period by increasing two times the clock rate. Alternatively, two codes may be multiplexed within the equalizing period or the vertical blanking period. Further, the two codes may be multiplexed spaced in timing apart from each other. Although in this embodiment the first code is outputted when the first code and the inversion of the second code are coincident with each other, it is possible to output an inversion of the second code. That is, when the first code and the second code are in a predetermined relationship, the second code may be turned into the first code for being outputted. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.

Claims: A reading device adapted to read codes multiplexed on a video signal to be reproduced by a video reproducing apparatus (26) wherein the reproduced video signal that is reproduced by the video reproducing apparatus is a signal for which a dropout compensation has been performed by replacing a portion in which a dropout occurs with a signal of a portion of the preceding line, comprising: a code determining means (42) for determining whether two codes taken out of the reproduced video signal are in a predetermined relationship and not coincident with each other; and a code output means (46) for outputting a predetermined code when said determining means determines the two codes are in the predetermined relationship. A code multiplexing/reading apparatus adapted to multiplex codes on a video signal to be recorded by a recording device and read the codes multiplexed on the video signal to be reproduced by a reproducing device, comprising: a reading device according to claim 1; and a multiplexing means (20, SW8) for multiplexing on the video signal said two codes that are in a predetermined relationship and not coincident with each other. A code multiplexing/reading apparatus according to claim 2, wherein the predetermined code comprises one of the two codes. A code multiplexing/reading apparatus according to claim 3, wherein said multiplexing means is arranged to multiplex the two codes on the video signal within a vertical blanking period thereof. A code multiplexing/reading apparatus according to claim 2, wherein the two codes include a non-inverted first code and a second code that is inverted in bit partly or the entire of the first code, and the predetermined code being the first code. A code multiplexing/reading apparatus according to claim 5, wherein said determining means includes a storing means (42) for storing the first code, and inverting means (40) for inverting bits partly or in the entire of the second code, and a comparing means (42) for comparing an output of said storing means with an output of said inverting means. A code multiplexing/reading apparatus according to claim 6, wherein said code output means outputs as the predetermined code the output of said storing means.

Inventors: AMINO TADASHI, MIYAZAKI YOSHIYUKI, AMINO, TADASHI, MIYAZAKI, YOSHIYUKI
Applicants: SANYO ELECTRIC CO, SANYO ELECTRIC CO., LTD.
Application year: 1997
Main classification: H04N5
IPC codes: H04N5, H04N7, G11B20