BIPOLAR SOI DEVICE HAVING A TILTED PN-JUNCTION, AND A METHOD FOR PRODUCING SUCH A DEVICE

Abstract: In a bipolar semiconductor-on-insulator transistor device (1) comprising an emitter region (4), a base region (5), a collector region (2) and a collector contacting region (6) in a semiconductor wafer, e.g. a monocrystalline silicon wafer (2), on top of an insulator (3), the base-emitter and collector-base junctions are tilted relative to the interface between the semiconductor wafer (2) and the insulator (3). The device can be made by anisotropic etching in order to produce a tilted surface (7) at an edge of the device or equivalently a V-groove having tilted sidewalls. The base and emitter regions (5, 4) are then produced by diffusing suitable donor and acceptor atoms into the material inside the tilted surface. Such a bipolar semiconductor-on-insulator transistor combines the high speed features of a lateral semiconductor device and the high voltage features of a vertical semiconductor device.

Description: BIPOLAR SOI DEVICE HAVING A TILTED PN-JUNCTΪON. AND A METHOD FOR PRODUCING SUCH A DEVICE TECHNICAL FIELD The invention relates to a bipolar semiconductor-on-insulator sdevice as well as to a method of producing such a device. BACKGROUND AND PRIOR ART A large number of bipolar semiconductor devices be designed without heavily doped, buried layers on semiconductor substrates has been proposed. There are two basic types of such bipolar 10 semiconductor devices, namely lateral devices and vertical devices . Lateral devices (see e.g. Stephen A. Parke, Chenming Hu, Ping K. Ko: "A High-Performance Lateral Bipolar Transistor Fabricated on Simox", IEEE Electron Dev. Lett., vol. 14, pp. 33-35, Jan. 1993, isand R. Dekker, W.T.A. v.d. Einden and H.G.R. Maas: "An Ultra Low Power Lateral Bipolar Emitter Technology on SOI", 1993 IEDM Conference Digest, pp. 75-77), are intended for high speed applications but are able to support only quite small voltages. Vertical devices (see e.g. Andrej Litwin and Torkel Arnborg: 20 "Compact Very High Voltage Compatible Bipolar Silicon-On- Insulator Transistor", ISPSD'94, Davos, June 1994, and U.S. Patent No. 4,868,624) are intended more for high voltages and moderate switching velocities. Isolating shallow lateral devices can be achieved more easily 25than isolating vertical devices since a simple LOCOS or mesa isolation can be utilized instead of a trench or junction isolation. However, the control of base and emitter doping is difficult, since lateral diffusion has to be utilized. The lateral devices exhibit lower breakdown voltages BV ceo than 3overtical devices, in which BV ceo = BV cbo . On the other hand, vertical devices which are capable of supporting high voltages, suffer from low switching speeds, limited by the transit time for lateral carrier transport along the semiconductor-insulator interface below the base due to potential lock-up (see Torkel asArnborg: "Modelling and Simulation of High Speed, High Voltage Bipolar SOI Transistor with fully Depleted Collector" presented in 1994 IEDM Conference Digest) . SUMMARY The object of the invention is to provide a bipolar semicon¬ ductor-on-insulator device which combines the high speed s features of a lateral semiconductor device and the high voltage features of a vertical semiconductor device. This object is attained by a bipolar semiconductor-on-insulator device having base-emitter and collector-base junctions which are tilted. ιoThis object is also attained by a method of producing a bipolar semiconductor-on-insulator device comprising that the base region and the emitter region are produced to have a tilted con¬ figuration. BRIEF DESCRIPTION OF THE DRAWINGS isThe invention will be described in detail by way of a non- limiting embodiment with reference to the accompanying drawings in which: - Fig. 1 is a schematic cross-sectional view of a bipolar semi¬ conductor-on-insulator device, 20- Figs . 2 and 3 are diagrams illustrating calculated dopant profiles at the emitter of a bipolar device according to Fig. 1, - Fig. 4 is a diagram illustrating measured dopant profiles at the emitter of a bipolar device according to Fig. 1. DETAILED DESCRIPTION 25Figure 1 schematically shows an embodiment of a bipolar semi¬ conductor-on-insulator device 1, where the semiconductor is a monocrystalline silicon wafer, the device 1 thus being a silicon-on-insulator (SOI) semiconductor device. The silicon wafer is denoted 2, whereas the insulator, e.g. a silicon oxide 30 layer, is denoted 3 and is located underneath the silicon wafer as seen in the figure. The device as illustrated has a generally rectangular cross-section. The silicon wafer 2 includes an emitter region 4, a base region 5, and a collector contacting region 6, the collector being the region of the bulk silicon material 2 located between the base region 5 and the collector contacting region 6. In an npn- transistor the emitter region 4 has an n-doping of e.g. arsenic, the base region has a p-doping of e.g. boron, the bulk silicon 5material has a n doping of e.g. arsenic and the collector con¬ tacting region 6 has a heavy n-doping of e.g. arsenic. In the silicon wafer 2, the base-emitter junction and the collector- base junction are parallel to each other and they are both tilted in relation to the interface between the silicon wafer 2 ιoand the insulator 3. This is accomplished by the fact that the thin emitter region or layer 4 and the thin base region or layer 5 are tilted in relation to said interface between the silicon wafer 2 and the insulator 3. The angle of tilt of the base-emitter and collector-base isjunctions in relation to the interf ce between the silicon wafer 2 and the insulator 3, is typically in the range of 45° ± 20°, i.e. between 25 and 65°. The emitter and base regions 4, 5 are located at an upper edge line of the wafer structure where the structure has a tilted 20surface 7, the configuration being obtained by cutting away a corner region of the generally rectangular cross-section. The emitter and base regions are located at this tilted surface 7, the emitter region 5 being a thin layer located directly inside the tilted surface and the base region 4 being a thin layer 25located directly inside the emitter region, the emitter and base regions thus extending in parallel to the tilted surface 7. The tilted surface 7 is only a surface of the silicon layer 2 and does not extend into the insulator layer 3. The collector con¬ tacting region 6 is located at the upper edge line of the 30structure which is opposite the edge where the tilted surface 7 is located. A method of producing the semiconductor device 1 shown comprises etching anisotropically an SOI film, having a (100) silicon crystal orientation of the plane along its surface. The etching 5is made with a solution of KOH in order to produce the tilted surface 7 achieving that this surface will always be located along a (111) crystal plane of the silicon wafer 2. T he etc h ing is made only at one of the lateral edges of the SOI film, re¬ quiring that a suitable mask is applied before the etching step. Thereupon a base region 5 and an emitter region 4 are doped so that they will be parallel to the tilted surface 7 and thus to a s (111) crystal plane in the silicon wafer 2, which is supposed to already include a collector contacting region 6 made in some earlier processing step. The angle of tilt of the parallel base- emitter and collector-base junctions will thus correspond to the angle of tilt of the (111) crystal plane of the silicon wafer 2 ιoin relation to its upper surface. Emitter-, base- and collector contacts, not shown, are finally produced in some conventional way such as by making heavily doped contacting regions at suitable places and by producing metallizations on top of these regions or by making polysilicon structures at suitable con- istacting places. The method can also be used for producing transistors on a wafer such as for an integrated circuit having several different com¬ ponents on the same chip. Then the anisotropic etching is made to produce V-grooves having sides walls located along (111) 2oplanes of the silicon monocrystalline material. In the V- grooves, from the sides thereof suitable dopants are diffused into the silicon material to produce the base and emitter regions. This method will then differ from conventional methods of producing transistors mainly in the step of producing the V- 25grooves before the diffusion steps or in producing V-grooves having tilted sidewalls instead of rectangular cross-section grooves having sidewalls perpendicular to the surface of the wafer. The diagram of Fig. 2 shows a one-dimensional simulation of the 30doping profiles as taken perpendicularly to the tilted surface 7 of the emitter 4 for a typical embodiment of a transistor as described with reference to Fig. 1. The various lines drawn illustrate the concentrations of arsenic, boron and phosphorous as functions of the distance from the surface 7. Also, the net 35dopant concentration is shown. In the diagram of Fig. 3 the net donor concentration and the net acceptor concentrations are illustrated as functions of the same distance. Also here, the net dopant concentration is shown. In Fig. 4 measured values of the actual concentrations of dopant atoms are shown for a npn-transis or doped with arsenic and boron, also as functions of the same perpendicular distance from the tilted surface of the emitter region. sit is to be understood, however, that other methods in addition to etching as described above may be used to produce tilted parallel base-emitter and collector-base junctions. Also, another crystal surface than the (111) crystal plane of the silicon wafer may be exposed for producing the tilted surface to ιo e doped to achieve a base region and an emitter region parallel to the exposed crystal surface. The dimensions of the SOI film are chosen in such a way that the electric field perpendicular to the emitter-base junction will be reduced. This will increase the breakdown voltage of the issemiconductor device. Due to its geometry, the charge is injected into the collector space charge region in the direction of the electric field. Since no potential lock-up is present, and thus, the lateral field is never zero, the transport will be by drift and not by diffusion as in the case of a semiconductor 20device having a fully depleted collector. This feature will make the semiconductor device as described above faster having a per¬ formance comparable to a lateral semiconductor device. Moreover, it is to be understood that the invention is not re¬ stricted to the use of silicon as a semiconducting material in 25the semiconductor-on-insulator device. Instead of silicon, e.g. GaAs or SiC may equally well be used.

Claims: CLAIMS 1. A bipolar semiconductor-on-insulator device (1) comprising an emitter region (4), a base region (5), and a collector region in a semiconductor wafer (2) on an insulator (3), characterized in sthat the base-emitter and collector-base junctions are tilted in relation to the interface between the semiconductor wafer (2) and the insulator (3). 2. A device according to claim 1, characterized in that the angle of tilt of the base-emitter and collector-base junctions ιois in the range of 45° ± 20°. 3. A device according to claim 1 or 2, in the case where the semiconductor wafer is made of monocrystalline silicon (Si), characterized in that the angle of tilt of the base-emitter and collector-base junctions corresponds to the (111) crystal plane isof the silicon wafer (2). 4. A method of producing a bipolar semiconductor-on-insulator device from a semiconductor wafer (2) on an insulator (3), chaxacterized by doping the wafer to produce a base region (5) and an emitter region (4) which are tilted in relation to the 20interface between the semiconductor wafer (2) and the insulator (3). 5. A method according to claim 4, characterized in that the base-emitter and collector-base junctions are tilted in an angle in the range of 45° ± 20°. 256. A method according to claim 4 or 5, in the case where the semiconductor wafer is made of monocrystalline silicon (Si), characterized by anisotropically etching the silicon wafer (2) to expose a (111) crystal plane at one of lateral edges thereof before doping the base region (5) and the emitter region (4) 30parallel to the exposed (111) crystal plane of the silicon wafer (2).

Inventors: ARNBORG TORKEL, LITWIN ANDREJ, ARNBORG, TORKEL, LITWIN, ANDREJ
Applicants: ARNBORG TORKEL, ERICSSON TELEFON AB L M, LITWIN ANDREJ, ARNBORG, TORKEL, LITWIN, ANDREJ, TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
Application year: 1997
Main classification: H01L29
IPC codes: H01L21, H01L29