Image pickup apparatus having different processing rates for still and moving images

Abstract: In order to provide an image pickup apparatus and an image pickup recording/reproducing apparatus capable of obtaining high-picture-quality still images and interlaced moving images, when an operational-mode switch sets a still-image mode, a CCD is driven by a driving circuit which outputs a signal having a frequency obtained by dividing the frequency of an output of an oscillator by a 1/2 frequency divider, and three signals shifted by one horizontal period from each other are obtained from a line memory block. When the operational-mode switch sets a moving-image mode, the CCD is driven by the driving circuit which outputs a signal having the frequency of the oscillator, and four signals, capable of being interlaced, shifted by one horizontal period from each other are obtained from the line memory block.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an image pickup apparatus for converting an image signal (which represents an image picked up using a solid-state image pickup device) into a digital video signal in one of a plurality of modes, and to an image pickup recording/reproducing apparatus for recording/reproducing an output from the image pickup apparatus. Description of the Related Art In accordance with recent progress in digital signal processing techniques, many image pickup recording/reproducing apparatuses, in which an image signal representing a picked-up image is subjected to digital processing and the resultant signal is recorded in/reproduced from a tape or a disk device as a digital video signal, have been proposed. In these methods, an output signal from an image pickup device, such as a CCD (charge-coupled device) or the like, is subjected to an analog-to-digital conversion by an A/D (alanog-to-digital) converter, and a resultant signal is processed by a digital-signal processing circuit to obtain a digital video signal, which is converted into recording data by a digital recording processing circuit, and the recording data is recorded on a tape or a disk device. A digital reproducing processing circuit forms a digital video signal from an output of the tape or the disk device, and outputs the formed signal to an external apparatus as a reproduced digital video signal. However, the above-described conventional approach has the following problems. That is, a reproduced digital video signal, in the conventional approach, is supplied to various kinds of external apparatuses. For example, after performing D/A (digital-to-analog) conversion, the obtained signal may be supplied to an ordinary television monitor, a still-image input apparatus or a moving-image input apparatus of a personal computer, a color printer, a video conference system, or the like. These apparatuses may be grossly classified into apparatuses which deal with still-image data (still-image input apparatuses such as personal computers and color printers in the above-described examples), and apparatuses which deal with moving-image data (such as television monitors, video conference systems, and moving-image input apparatuses of personal computers in the above-described examples). In apparatuses which deal with still-image data, data having a number of pixels per frame as large as possible is required. Among apparatuses which deal with moving-image data, for example, NTSC-system television monitors deal with 2:1 interlaced images of 60 fields/sec and 240 lines in the vertical direction, and some other apparatuses deal with noninterlaced images of 30 frames/sec and 240 lines in the vertical direction although these values depend on the system, and the processing capability of a CPU used in the apparatus. Recording/reproducing units used in the above-described conventional approach can record/reproduce only interlaced images of 60 fields/sec and 240 lines in the vertical direction. Hence, when a signal from such a unit is input to an apparatus which deals with a still image, particularly, resolution in the vertical direction is low, so that it is impossible to display or print an image in a large size, or only an image having a low picture quality is displayed or printed. When intending to improve resolution by synthesizing interlaced images for two fields, if an object is moving, a moving portion becomes indented or blurred. In the Patent Abstracts of Japan, vol. 1995, no. 3, &JP-A-6 339 080 a solid-state image pickup device and a method of obtaining a clear X-ray still image without using an image intensifier is described. It is proposed to slow down the reading speed of electric charge stored in a CCD image sensor by performing n frequency division for the clock of a prescribed frequency from an original oscillation circuit by a 1/n counter and supplying the clock to the CCD image sensor. As a result, the electric charge storage time of the CCD image sensor is prolonged and, thus, an image pickup signal with a high level can be obtained. In other words, an image pickup apparatus comprising image pickup means is shown which can be driven with different frequencies. As it is derivable from this document, in a still image mode the driving frequency of the CCD sensor is lowered down. Moreover, in the US-A-5 206 730 a digital still video camera having a plurality of photographing modes is disclosed. The camera includes a circuit for processing a digital image signal output from a CCD sensor in synchronization with a clock signal, wherein the frequency of the clock signal can be changed in accordance with a selected photographing mode so that the circuit changes its processing speed in accordance with the selected photographing mode. SUMMARY OF THE INVENTION It is an object of the present invention to provide an image pickup apparatus which can obtain high-picture-quality still images and moving images capable of being interlaced, and an image pickup recording/reproducing apparatus which uses such a device. According to the present invention, this object is achieved by an image pickup apparatus according to claim 1 and an image pickup recording/reproducing apparatus according to claim 7. Further features of the present invention are defined in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating the configuration of a camcorder (a video camera integrated with a VCR (video cassette recorder)) according to an embodiment of the present invention; FIGS. 2(a) and 2(b) are diagrams illustrating output waveforms from the camcorder shown in FIG. 1; and FIGS. 3(a) and 3(b) are diagrams illustrating the detail of a line memory block shown in FIG. 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail for use with a camcorder (image pickup recording/reproducing apparatus). The present invention is not limited to a camcorder, but may also be applied to an image pickup apparatus which omits a recording/reproducing unit and provides a line output or a wireless output. FIG. 1 is a block diagram illustrating the configuration of a camcorder according the embodiment. In FIG. 1, reference numeral 1 represents a CCD, serving as an image pickup device, in which very small color filters are disposed on respective pixels on an image pickup surface, and which adopts a method of sequentially reading out charges accummulated in respective pixels without adding the charges of the respective pixels (an all-pixel reading-out method). There are also shown a driving circuit 2 for the CCD 1, a switch for changing the driving voltage for the driving circuit 2, a crystal oscillator 4, an oscillation circuit 5, a 1/2 frequency divider 6, a switch circuit 7, a sample-and-hold circuit 8 for converting the output signal of the CCD 1 into a continuous signal, and an A/D converter 9 for performing an analog-to-digital conversion. A line memory block 10 incorporates a plurality of line memories, and forms a delayed digital image signal from an input digital image signal. A signal processing circuit 11 forms a digital video signal including a digital color signal and a digital luminance signal from the output signal of the line memory block 10 using digital signal processing. A frame memory 12 stores input image data for one frame, and performs non-interlacing or interlacing conversion. Reference numeral 13 represents a switch circuit. In a recording operation, a VCR-signal processing circuit 14 adds an error-correcting code after compressing an input digital video signal, converts the resultant signal into codes adapted to recording, and records the obtained codes on a tape. In a reproducing operation, the VCR-signal processing circuit 14 reproduces a digital video signal by performing code conversion, error correction and expansion, in a sequence reverse to the above-described sequence. Reference numeral 15 represents a tape. The operator sets an operational mode using a switch 16, i.e., sets one of a "still-image mode" of outputting image data adapted to a still image, and a "moving-image mode" of outputting image data adapted to a moving image. A control circuit 17 controls the operation of each unit in accordance with an output from the switch 16. As for setting of an operational mode using the switch 16, the still-image mode is set when using a picked-up image as a still image, and the moving-image mode is set when using an picked-up image as a moving image. The control circuit 17 controls the switches 3 and 7, the line memory block 10, and the switch 13 based on this setting. Each of the crystal oscillator 4 and the oscillator 5 generates a clock signal serving as reference for operational timings for the respective units, and the frequency divider 6 divides the frequency of the clock signal by two. The switch 7 selects the output of the frequency divider 6 and the output of the oscillator 5 when the switch 16 is set to the still-image mode and the moving-image mode, respectively, by the control of the control circuit 17. The output from the switch 7 is supplied as a clock signal for the driving circuit 2, the A/D converter 9, and the line memory block 10. The switch circuit 3 selects a necessary voltage so as to drive the CCD 1 with a driving voltage suitable for the still-image mode or the moving-image mode by the control of the control circuit 17. The driving circuit 2 generates operational pulses for vertical transfer and horizontal transfer, and reading out of charges to a vertical transfer line of the CCD 1, and for the sample-and-hold circuit 8. Next, a description will be provided of the flow of an image signal representing a picked-up image. The image of an object (not shown) is focused onto the photsensiving surface of the CCD 1 (after passing through very small color filters disposed thereon) by an image pickup optical system (not shown), and is converted into electric charges for each pixel according to photoelectric conversion. Since the CCD 1 adopts an all-pixel reading-out method, the charges are first read out on a vertical transfer line without being added and are vertically transferred. The charges are then subjected to charge-to-voltage conversion in an output unit after passing through a horizontal transfer line, and the obtained signal is output as the image signal representing the picked-up image. These transfer operations are effected by driving pulses from the driving circuit 2. Accordingly, when the output of the oscillator 5 is supplied to the driving circuit 2 via the switch 7, the transfer speed is twice the transfer speed when the output of the frequency divider 6 is supplied. The image pickup signal is converted into a continuous signal by the sample-and-hold circuit 8, is then converted into a digital image signal by the A/D converter 9, and is input to the line memory block 10. The line memory block 10 is controlled by the control circuit 17 so as to delay the input signal without being modified when the switch 16 sets the still-image mode, and to delay the input signal by halving the delay rate when the moving-image mode is set. At that time, interlacing processing is also performed by changing the number of delaying operations for an output signal for every field. The output of the line memory block 10 is input to the signal processing circuit 11, which performs processing, such as color separation, contour emphasis, gamma correction, luminance/color-difference matrix processing, and the like, to form a digital video signal including a color signal and a luminance signal. The digital video signal is input to the frame memory 12, where, in the still-image mode, a noninterlaced image is converted into an interlaced image, and the obtained signal is input to the VCR-signal processing circuit 14 via the switch circuit 13. In the moving-image mode, the digital video signal output from the signal processing circuit 11 is directly input to the VCR-signal processing circuit 14. The VCR-signal processing circuit 14 performs the above-described processing, and records the resultant signal on the tape 15. In a reproducing operation, a reproduced digital video signal is generated from data of the tape 15 according to VCR signal processing, and is output to an external apparatus directly or by being converted into an analog video signal by a D/A (digital-to-analog) converter (not shown). The frame memory 12 is necessary when displaying an image picked up in the still-image mode on an apparatus which deals with an interlaced image, such as a television monitor or the like. However, the frame memory 12 may be omitted when outputting the image to a personal computer or a printer as data. A description will now be provided of the operation of the switch circuit 3. Usually, in order to operate the CCD 1 at a high speed, it is necessary to increase the voltage of the CCD driving pulses for the purpose of obtaining a sufficient transfer efficiency. When generating driving pulses for realizing a high speed operation, a voltage loss in the output of the driving circuit 2 tends to increase as the frequency increases. In order to solve this problem, the voltage of the power supply for the driving circuit 2 is simultaneously changed when changing the driving frequency, so that a desired operation of the CCD 1 can be obtained even if the driving frequency is changed. The signal processing circuit 11 always operates with a clock signal subjected to 1/2 frequency division. In order to perform the above-described processing, the signal processing circuit 11 is configured by a considerably large-scale logic circuit. Hence, power consumption greatly increases if this circuit is operated at a high speed. In the present embodiment, however, since the circuit is operated with a low clock frequency, it is possible to reduce power consumption. FIGS. 2(a) and 2(b) are diagrams illustrating output waveforms in the camcorder shown in FIG. 1. FIG. 2(a) illustrates the output waveform of the CCD 1 in the moving-image mode. In this case, the period of output of one horizontal line is 1/2 of one ordinary horizontal period (1/2 H), and the number of effective scanning lines in one picture frame is 480. The output of one picture frame is obtained during one ordinary vertical period (1 V). FIG. 2(b) illustrates the output waveform of the CCD 1 in the still-image mode. In this case, the period of output of one horizontal line equals one ordinary horizontal period (1 H), and the number of effective scanning lines in one picture frame is 480. The output of one picture frame is obtained during two ordinary vertical periods (2 V). FIGS. 3(a) and 3(b) are diagrams illustrating the detail of the line memory block 10 shown in FIG. 1. FIG. 3(a) is a block diagram of the line memory block 10. In FIG. 3(a), there are shown line memories 21, 22, 25 and 26. Each of the line memories 21 and 22 has a write control terminal (WEN). There are also shown a control circuit 23, and switch circuits 24, 27 and 28. A signal CLK1, serving as the output of the above-described switch circuit 7, a signal CLK2, serving as the output of the above-described frequency divider 6, a signal F1, serving as a field discrimination signal from a synchronizing-signal generator (not shown), and a signal MODE, serving as the output of the above-described control circuit 17, are input to the control circuit 23. FIG. 3(b) illustrates the relationship between the respective operational modes, and the control states of the respective switches and the write control terminals of the line memories 21 and 22. First, a description will be provided of the "still-image mode". An input digital image signal SI which is the output of the A/D converter 9 is written in the line memory 21 because the terminal WEN of the line memory 21 is ON. The output of the line memory 21 is output as a signal SO1 via the switch circuit 28, and is also input to the line memory 25 to be delayed for one horizontal period. The output of the line memory 25 is output as a signal SO2 via the switch circuits 27 and 28, and is also input to the line memory 26 via the switch 24 to be further delayed for one horizontal period. The output of the line memory 26 is output as a signal SO3 via the switch circuits 27 and 28. That is, the signals SO1, SO2 and SO3 become outputs shifted by one horizontal period from each other. Next, a description will be provided of an operation when setting the moving-image mode. The input signal SI is first simultaneously input to the line memories 21 and 22. In the moving-image mode, as shown in the table of FIG. 3(b), since the write control terminals WEN's of the line memories 21 and 22 become ON in the first half and the second half of 1 H, respectively, the signal SI is written in the line memories 22 and 21 in the first half and in the second half of 1 H, respectively. Since the write clock signal at that time is CLK1, it has a frequency twice the frequency of the read clock signal CLK2. The output of the line memory 21 is read in accordance with the above-described CLK2. At that time, since a writing operation is performed at the second half of 1 H, read data is data preceding the data of the current line by 1 H. The input signal SI is written in the line memory 22 in the first half of 1 H, and the written data is read without being modified. Hence, the read data is data of the current line. The output of the line memory 21 is first input to the switch circuit 28 as well as to the line memory 25. The output of the line memory 22 is first input to the switch circuit 28 via the switch circuit 27, as well as to the line memory 26 via the switch circuit 24. The output of the line memory 25 is input to the switch circuit 28 via the switch circuit 27. The output of the line memory 26 is input to the switch circuit 28. As described above, four signals are input to the switch circuit 28. These signals are shifted by one pixel from each other in the vertical direction. As shown in the table of FIG. 3(b), the switch circuit 28 selects one group of contacts A and B for these signals in accordance with the field discriminating signal FI. When the contacts A have been selected, the outputs of the line memories 21, 22 and 25 are output to the terminals SO1, SO2 and SO3, respectively. When the contacts B have been selected, the outputs of the line memories 22, 25 and 26 are output to the terminals SO1, SO2 and SO3, respectively. When the contacts A are selected, the signal is shifted by one pixel in the vertical direction compared with when the contacts B are selected. By thus switching the switch 28 in accordance with the FI in the above-described manner, signals output to the terminals SO1, SO2 and SO3 are interlaced. In FIG. 3, three outputs are provided from the line memory block 10, because signal processing using 3-line correlation using a CCD having color filters with Bayer arrangement is considered. When using, for example, a signal processing circuit for forming a digital video signal output only from an output for one line, the line memory 26 is unnecessary. On the other hand, when using a signal processing circuit using 5-line correlation, it is necessary to add another line memory. In the still-image mode, in the configuration shown in FIG. 3(a), it is possible to obtain five outputs without increasing the number of line memories by using the input signal and by further delaying the output of the line memory 26 by one line by switching the input of the line memory 22. For example, it is possible to perform higher-performance signal processing, such as a 5-tap vertical filter or the like, using these five outputs. As described above, according to the present embodiment, it is possible to record/reproduce a high-picture-quality still image, and moving images capable of being interlaced. As described above, according to the present invention, it is possible to obtain a high-picture quality still image, and moving images capable of being interlaced. The individual components designated by blocks in the drawings are all well-known in the image pickup apparatus arts and their specific construction and operation are not critical to the operation or the best mode for carrying out the invention. While the present invention has been described with respect to what is presently considered to be the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment. To the contrary, the present invention is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims. In order to provide an image pickup apparatus and an image pickup recording/reproducing apparatus capable of obtaining high-picture-quality still images and interlaced moving images, when an operational-mode switch sets a still-image mode, a CCD is driven by a driving circuit which outputs a signal having a frequency obtained by dividing the frequency of an output of an oscillator by a 1/2 frequency divider, and three signals shifted by one horizontal period from each other are obtained from a line memory block. When the operational-mode switch sets a moving-image mode, the CCD is driven by the driving circuit which outputs a signal having the frequency of the oscillator, and four signals, capable of being interlaced, shifted by one horizontal period from each other are obtained from the line memory block.

Claims: An image pickup apparatus for converting a signal representing an image picked up using a progressive-scanning-type image pickup device (1), performing predetermined processing on the digital signal, and outputting a resultant signal, said apparatus comprising: an operational-mode switch (16); and a driving circuit (2,7) capable of setting a horizontal transfer frequency for the image pickup device (1) to a first frequency or to a second frequency higher than the first frequency; said apparatus being characterized by comprising: a memory block (10) for delaying an output of the image pickup device by a predetermined number of lines; and control means (17) for causing, when a first operational mode has been set by said operational-mode switch (16), said driving circuit (2,7) to drive the image pickup device with a horizontal transfer frequency equal to the first frequency to cause a writing operation and a reading operation with respect to said memory block (10) to be performed at the same frequency, and for causing, when a second operational mode has been set by said operational-mode switch, said driving circuit to drive the image pickup device with a horizontal transfer frequency equal to the second frequency to cause a writing operation with respect to said memory block to be performed at the second frequency and to cause a reading operation with respect to said memory block to be performed at the first frequency so as to cause signals output from said memory block to be interlaced. An image pickup apparatus according to claim 1, wherein said memory block includes output terminals (SO1-SO3) for outputting a plurality of signals shifted by one horizontal period from each other. An image pickup apparatus according to claim 1, further comprising signal processing means (11), coupled to said memory block, for performing signal processing using line correlation. An image pickup apparatus according to claim 3, wherein said signal processing means performs signal processing using a vertical filter. An image pickup apparatus according to claim 1, wherein the first frequency is one half of the second frequency. An image pickup apparatus according to claim 1, wherein the first operational mode is a still image mode and the second operational mode is a moving-image mode. An image pickup recording/reproducing apparatus, comprising an image pickup apparatus according to any one of claims 1 to 6, for recording/reproducing an output of said image pickup apparatus.

Inventors: HIEDA TERUO, HIEDA, TERUO, HIEDA, TERUO, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1997
Main classification: H04N5
IPC codes: H04N5