Improvements in or relating to electronic systems

Abstract: A selectable memory module (10) is provided. The memory module (10) has a first plurality of pins (16) for communicating information to and from memory devices on the memory module (10), and a second plurality of pins (22) for receiving a module address. Module select logic (14) is connected to receive the module address and is operable to generate module select signals based upon the module address. The module select signals have a selected state and a not-selected state. A plurality of gates (18) are connected between the first plurality of pins (16) and the memory devices and are connected to receive the module select signals. The gates (18) are operable, when the module select signals are in the selected state, to connect the first plurality of pins (16) to the memory devices, and, when the module select signals are in the non-selected state, to disconnect the first plurality of pins from the memory devices (16).

Description: TECHNICAL FIELD OF THE INVENTION This invention relates in general to the field of electronic systems, and more particularly to selectable integrated circuit modules. BACKGROUND OF THE INVENTION Systems requiring memory modules, such as DRAMS and synchronous SDRAMs operating at clock frequencies of greater than 100 MHz can require a different type of memory module than standard single in-line memory modules (SIMM). Conventional SIMMs have problems with interconnect, noise and physical space which are augmented by such high operating frequencies. A bus system clocked at a 100 MHz needs minimal load per driver to reduce noise and improve integrity of the signal. However, eight memory devices on a single bus driver can add forty picofarads of capacitance to a base of approximately twenty picofarads. Many computer system manufacturers contemplate having five gigabytes of main memory which may require as many as thirty two memory devices per bus. It is clear that this number of memory devices will produce problems with respect to the load on the bus drivers at high operating frequencies. In this context, reference is made to US-A-5 216 637, which discloses a hierarchical busing architecture for a very large semiconductor memory. The semiconductor memory is comprised of a plurality of memory modules, arranged in a memory array of N columns of n modules each. A global data bus, a global address bus and a global control bus extend through the memory array in close proximity to the column of modules. A column data bus, a column address bus and a column control bus for each column of the modules extend in close proximity to the modules in each column. Each of a plurality of N column disable blocks is connected to provide an interface between the column data, address and control buses and the global data, address and control buses. Each column disable block includes a column disable register, to disable output from selected data lines of the column data bus to which the column disable block is connected, in the event of the detected areas. Each column disable block further includes a hard-wired column address uniquely identifying the column, a column address comparator, and means for enabling loading of the disable register upon detection of a match between the hard-wired column address and a column address supplied to all of the column disable blocks. SUMMARY OF THE INVENTION The present invention provides an integrated circuit module is provided which comprises the features of claim 1. Preferably, the at least one integrated circuit device is a memory device. A technical advantage of the present invention is the mounting of memory devices on a modular board similar to existing SIMMs but with an input/output (I/O) integrated circuit for interface control to the outside. The interface control handles signal integrity at the board level and isolates the memory module when not being addressed. Thus, by isolating the memory module, the load on the bus is reduced thereby allowing more efficient driving of signals on the bus especially at high frequency. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be further described, by way of example, with reference to the accompanying drawings in which: FIGURES 1A and 1B are block diagrams of an embodiment of an apparatus for a memory module according to the teachings of the present invention; FIGURE 2 is a block diagram of an embodiment of the pins of a memory module constructed according to the teachings of the present invention; FIGURE 3 is a block diagram of an embodiment using module address pine to determine whether or not to select a given memory module according to the teachings of the present invention; FIGURE 4 is a block diagram of an embodiment of a memory module within a bus scheme according to the present invention; and FIGURE 5 is a block diagram of an embodiment of a memory module socket constructed according to the teachings of the present invention. DETAILED DESCRIPTION OF THE INVENTION FIGURES 1A and 1B are a block diagram of an embodiment of an apparatus for a selectable memory module. As shown, a memory module 10 is connected to a bus 12 for communicating with other components of a computer system. Memory module 10 includes module select logic 14 and a plurality of pins 16. A plurality of, for example, T-gates 18 are connected to pins 16 to allow disconnection from and connection to bus 12. One conventional use of T-gates are to multiplex pins of integrated circuit chips to allow different sources to be selected to drive the pins, such as selecting between operation under test or under application. However, T-gates 18 allow each I/O and address pin of memory module 10 to be connected to or disconnected from bus 12 such that memory module 10 can both appear on and load bus 12 and be disconnected from and not load bus 12. Thus, memory module 10 is selectable and can be isolated using T-gates 18. Thus memory module 10 adds more to the load on bus 12 (e.g., about ten picofarads) when selected from it adds to the load on bus 12 (e.g., about 0.1 picofarads) when not selected. This selectability helps both drive current and reduces reflections at lower power and higher speed. As shown in FIGURES 1A and 1B, module select logic 14 provides two signals. These signals operate to turn "ON" all T-gates 18 which connect all the I/O and address pins to bus 12 when memory module 10 is selected. Conversely, these signals operate to turn "OFF" all the T-gates 18 to disconnect memory module 10 from bus 12 when memory module 10 is not selected. FIGURE 2 is a block diagram of an embodiment of pins of a selectable memory module 10. As shown, memory module 10 includes a plurality of pins 20 which provide gunning transistor logic (GTL) and power/ground pins for memory module 10. In addition, a plurality of pins 22 are LVTTL (low voltage transistor-transistor logic) pins which provide addressing of memory module 10. The address pins 22 can be used five or six at a time to provide either a 32 or a 64 module address. The address pins 22 can provide a five or six bit module address that allows memory module 10 to be selected and the rest of the interface pins 20 available for that memory module 10 while other memory modules are not selected. With the 5-pin module address, one of 32 modules can be selected, and with the 6-pin module address, one of 64 modules can be selected. Memory module 10 further includes a broadcast refresh pin, as shown. This pin allows memory module 10 to receive a broadcast refresh signal even though memory module 10 is not currently selected. In this manner, all memory modules can be signalled to refresh without having to be selected. FIGURE 3 is a block diagram of an embodiment using module address pins to determine whether or not to select a given memory module. As shown in FIGURE 3, memory module 10 can include module address compare logic 14 which receives a system clock as well as the memory module address pins. Module address compare logic 14 then operates to analyze the memory module address and drive a select signal, SELECT, and a select bar signal, SELECT_. These signals are provided to the T-gates on memory module 10 in order to connect or disconnect memory module 10 from the bus. The module address is gated by the system clock, to insure that turn-OFF and turn-ON of the next module occurs such that only one module is active at the same time, depending on loads. FIGURE 4 is a block diagram of embodiment of a selected memory module within a bus scheme. As shown, a plurality of memory modules 26 are connected to memory sockets 24 which connect to a memory bus 12. In this embodiment, memory bus 12 is terminated by a resistor 28 connected to ground. As shown, the middle memory module 26 is currently selected and connected to memory bus 12. The other memory modules 26 are isolated from bus 12 and are not seen by the system. The only memory module seen by the system is the middle memory module 26, and the other memory modules 26 appear to be a small load on bus 12 (e.g., about 1.1 picofarads). FIGURE 5 is a block diagram of an embodiment of a module socket 24. Module socket 24 includes an LVTTL module 30 which receives memory module address pins and provides the selection signals. Module selection can thereby be handled by each socket location. The particular address for module socket 24 can be, for example, burned into a PC board at build time or can be hardwired to the board. Thus, the only signal going to the memory module, itself, can be the select and select bar signals. This reduces the number of pins needed on the memory modules. Although certain embodiments have been described in detail, it should be understood that various changes, substitutions and alterations can be made thereto without departing from the scope of the teachings disclosed.

Claims: An integrated circuit module (10) comprising: a first plurality of terminals (20) for connecting the module (10) to a system bus (12), the first plurality of terminals (20) coupled to a plurality of terminals of at least one integrated circuit located on the module (10); a second plurality of terminals (22) for receiving a module address; module select logic (14) having at least one input coupled to the second plurality of terminals (22) and generating at least one select signal in response to the module address received at the second plurality of terminals (22); and a plurality of switches (18) connected between the first plurality of terminals (20) and the plurality of terminals of the at least one integrated circuit, the switches (18) connecting the plurality of terminals of the at least one integrated circuit to the first plurality of terminals (20) in response to a selected state of the at least one select signal and the switches (18) disconnecting the plurality of terminals of the at least one integrated circuit from the first plurality of terminals (20) in response to a not-selected state of the at least one select signal. The integrated circuit module of Claim 1, wherein the at least one integrated circuit is a memory device. The integrated circuit module of Claim 2, wherein the memory device is a dynamic random access memory device. The integrated circuit module of Claim 3 further comprising a broadcast refresh pin connected to receive a broadcast refresh signal. The integrated circuit module of Claim 3, wherein the first plurality of terminals (20) comprise input/output pins and address pins of the integrated circuit module. The integrated circuit module of Claim 1, wherein the integrated circuit module is isolated from the system bus (12) when the integrated circuit module is not selected. The integrated circuit module of Claim 1, wherein the plurality of switches (18) are T-gates. The integrated circuit module of Claim 1, wherein the at least one select signal comprises a SELECT and a SELECT signal.

Inventors: VOGLEY WILBUR C, WARD ROBERT L, VOGLEY, WILBUR C., WARD, ROBERT L.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1997
Main classification: G11C5
IPC codes: G11C8, G11C5, G11C11, G06F13, G06F12