Method and apparatus for testing counter and serial access memory containing it

Abstract: In a method for testing a counter, the counter is first set at a predetermined initial value. Then, the counter is incremented in response to the clocks. The number of the clocks is counted until a carry is outputted from the counter to provide an actual counted value. The actual counted value is compared to a reference value, which is calculated in advance. And then, the counter is decided whether to be operating normally or not on the basis of the result of the comparison.

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method and an apparatus for testing a counter, used for a serial access memory, and to a serial access memory itself. BACKGROUND OF THE INVENTION In general, a serial access memory is a kind of computer memory in which data are available only in the same sequence as originally stored. The serial access memory includes an address counter, which generally increments an initial memory address as a block of data is being transferred into the memory locations indicated by the counter. Conventionally, a test of the address counter has been performed using a read-modify-write scheme to find degeneration of memory cells. In the test, predetermined data are written in every memory cell, then different data are rewritten in the same address of the memory cell. For example, data of "0" are written in every memory cell while incrementing the address counter, then the address counter is reset to "0", and then data of ''1'' are rewritten in the same address of the memory cell while incrementing the address counter. In this case, if the address counter is not incremented in order when the data are read for rewriting, some memory cells store data "1" and the other memory cells store data "0." The data in the memory cells are again read in the same sequence as the rewriting. If all the read data are "1," the address counter is decided to be operating normally; however, if some data of "0" are included in the read data, the address counter is decided not to be operating normally and some addresses are degenerated. A serial access memory containing an address counter with degenerated addresses is rejected as a defective product. Recently, such a serial access memory is becoming increasingly to have a large capacity, and therefore, it takes long time to perform the read/write test for each memory cell. As a result, it becomes difficult to improve productivity of the serial access memory. In addition, when the serial access memory is decide to be defective, it can not be known whether the problem is on the address counter or on other devices in the memory. US 4,991,185 describes a method of testing an n-bit programmable counter and such a counter configured for testing, wherein each bit of the counter is set to an initial state (0), a different state is loaded into a carry-in bit of the counter and the counter is iteratively doubled until carry-out of said counter assumes the different state to thereby allow the counter to be fully tested in n+1 iterations. In order to save costs the counter is provided with the testing configuration without requiring external hardware components. OBJECTS OF THE INVENTION Accordingly, an object of the invention is to provide a method for testing a counter, by which the counter can be tested easily and accurately in a short time. Another object of the invention is to provide an apparatus for testing a counter, which tests the counter easily and accurately in a short time. Another object of the invention is to provide a serial access memory in which an address counter can be tested easily and accurately in a short time without performing a read/write process to a memory array. Still another object of the invention is to provide a combination of a serial access memory and a tester, in which an address counter can be tested easily and accurately in a short time without performing a read/write process to a memory array. Additional objects, advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims. SUMMARY OF THE INVENTION According to the present invention a method for testing a counter as defined in claim 1, a counter testing apparatus as defined in claim 3 are provided. BRIEF OF THE DRAWINGS Fig. 1 is a block diagram showing a serial access memory and a memory tester, according to a first preferred embodiment of the invention. Fig. 2 is a block diagram showing the memory tester. Fig. 3 is a flow chart showing the operation of the first preferred embodiment. Fig. 4 is a timing chart showing the operation of the first preferred embodiment. Fig. 5 is a block diagram showing a serial access memory and a memory tester, according to a second preferred embodiment of the invention. Fig. 6 is a block diagram showing a serial access memory and a memory tester, according to a third preferred embodiment of the invention. DETAILED DISCLOSURE OF THE INVENTION Fig. 1 shows a serial access memory 101 and a memory tester 102, according to a first preferred embodiment of the invention. The serial access memory 101 includes an address counter 111, a memory array 112 and an output circuit 113. The serial access memory 101 further includes a reset terminal RESET, a carry out terminal COUT, a data out terminal DOUT, a test terminal TEST and a clock terminal CLK. The reset terminal RESET is connected to the memory tester 102 and the address counter 111. Each of the carry out terminal COUT and data out terminal DOUT is connected to the memory tester 102 and the output circuit 113. The test terminal TEST is connected to the memory tester 102 and the output circuit 113. The clock terminal CLK is connected to the memory tester 102 and the address counter 111. The output circuit 113 is connected to the address counter 111 and the memory array 112. The memory array 112 supplies data to the output circuit 113. The address counter 111 addresses the memory array 112 when performing a reading process and a writing process. The address counter 111 is of 10-bit type, which is incremented from zero value in synchronization with clocks, supplied from the clock terminal CLK. The address counter 111 outputs a carry signal CARRY in response to 1024 th clock (CLK). In response to a test signal supplied through the test terminal TEST from the memory tester 102, the output circuit 113 selects, one from two output signals of the carry (CARRY), supplied from the address counter 111, and data (DATA), supplied from the memory array 112. In more detail, for example, the test terminal TEST is set at low when the address counter 111 is to be tested, and the carry signal CARRY outputted from the address counter 111 is supplied from the carry out terminal (COUT) to the memory tester 102. On the other hand, the test terminal TEST is set at high when the address counter 111 is not tested, and the data (DATA) outputted from the memory array 112 are supplied from the data out terminal DOUT to the memory tester 102. Fig. 2 shows the structure of the memory tester 102, which includes a reset circuit 120, a test enable circuit 122, a clock generator 124, a counter circuit 126 and a comparator 128. The reset circuit 120 is connected to the reset terminal RESET of the serial access memory 101 to supply a reset signal thereto. The test enable circuit 122 is connected to the test terminal TEST of the serial access memory 101 to supply a test enable signal thereto. The clock generator 124 is connected to the clock terminal CLK of the serial access memory 101 and the counter circuit 126, so that clock signals are supplied to both of them. The counter circuit 126 is connected to the carry out terminal COUT of the serial access memory 101 and the comparator 128. The counter 126 is designed to count the number of the clocks since the address counter 111 is set at an initial value until the carry signal CARRY is supplied therefrom. The value counted by the counter circuit 126 is hereinafter called "actual counted value (An)." The comparator 128 is designed to compare the actual counted value with a reference value "Rn," which is calculated in advance. The reference value "Rn" is obtained by previously calculating the number of clocks to be provided from the initial value of the address counter 111 until the carry is outputted from the counter 111. Next, the operation of the address counter 111 is described in conjunction with a flow chart and a timing chart, respectively shown in Figs. 3 and 4. First, for starting the test of the address counter 111, the test terminal (TEST) is set at low. Next, the reset terminal (RESET) is changed in status high to low to reset the address counter 111 to zero. After that, the memory tester 102 supplies the clocks to the serial access memory 101 to increment the address counter 111 one by one in synchronization with the clocks. As mentioned before, the address counter 111 outputs the carry signal CARRY in response to 1024 th clock, because the address counter 111 is of 10-bit type. The carry signal CARRY is outputted from the carry out terminal COUT to the counter circuit 126 of the memory tester 102. In the memory tester 102, the counter circuit 126 counts up the clocks supplied from the clock generator 124 to provide the actual counted value "An," which is obtained by counting the clocks until the carry signal CARRY is outputted from the carry out terminal COUT. The comparator 128 compares the actual counted value "An," supplied from the counter circuit 126, to the reference value "Rn," which is obtained by calculating the number of the clocks since the initial value (zero) is set in the address counter 111 until the carry signal (CARRY) is outputted therefrom. On the basis of the result of the comparison, the memory tester 102 decides whether the address counter 111 is normally operating or not. If the address counter 111 is normally operating, the actual counted value "An" is identical to the previously-calculated reference value "Rn." On the other hand, if the address counter 111 is not operating normally, the actual counted value "An" is different from the previously-calculated reference value "Rn." Accordingly, the address counter 111 can be tested easily in a short time without performing a read/write process to the memory array 112. Fig. 5 shows a serial access memory 201 and a memory tester 202, according to a second embodiment of the invention. The serial access memory 201 includes an address counter 211, a memory array 212 and an output circuit 213. The serial access memory 201 further includes a reset terminal RESET, a data out terminal DOUT, a test terminal TEST and a clock terminal CLK The serial access memory 201 is not provided with a carry out terminal. The reset terminal RESET is connected to the memory tester 202 and the address counter 211. The data out terminal DOUT is connected to the memory tester 202 and the output circuit 213. The test terminal TEST is connected to the memory tester 202 and the output circuit 213. The clock terminal CLK is connected to the memory tester 202 and the address counter 211. The output circuit 213 is connected to the address counter 211 and the memory array 212. The difference between the first and second embodiments is that a carry signal CARRY and data signal DATA, which are to be selected by the output circuit 213, are outputted from the common data out terminal DOUT. The basic operation of the second preferred embodiment is the same as the first preferred embodiment, shown in Fig. 1. The address counter 211 is reset to zero in response to a reset signal, and is incremented one by one in synchronization with clocks. Then, the actual counted value is compared with the previously-calculated reference value to decide whether the address counter 211 is operating normally or not. For starting a test of the address counter 211, in the second embodiment, a low level signal is supplied from the memory tester 202 to the test terminal TEST of the serial access memory 201 to disable the output circuit 213. In response to the test signal, the output circuit 213 performs switching operation to allow the carry signal CARRY to be outputted from the data out terminal DOUT. In other words, the carry signal CARRY is outputted from the data output terminal DOUT during the test to the memory tester 202. When the test of the address counter 211 is not performed, the data (DATA) outputted from the memory array 212 are supplied from the data out terminal DOUT to the memory tester 202. In the second embodiment, the carry signal CARRY, which is to be outputted during the test, and the data (DATA), which are to be outputted during not testing, are transmitted through the same terminal DOUT. As a result, the total number of terminals of the serial access memory 201 can be decreased. Fig. 6 shows a serial access memory 301 and a memory tester 302, according to a third preferred embodiment of the invention. The serial access memory 301 includes an address counter 311, a memory array 312, an output circuit 313 and an address register 314. The serial access memory 301 further includes a reset terminal RESET, a preset terminal PRESET, a data out terminal DOUT, a test terminal TEST and a clock terminal CLK. The serial access memory 301 is not provided with a carry out terminal. The reset terminal RESET is connected to the memory tester 302 and the address register 314. The preset terminal PRESET is connected to the memory tester 302 and the address register 314. The data out terminal DOUT is connected to the memory tester 302 and the output circuit 313. The test terminal TEST is connected to the memory tester 302 and the output circuit 313. The clock terminal CLK is connected to the memory tester 302 and the address counter 311. The output circuit 313 is connected to the address counter 311 and the memory array 312. The basic operation of the third preferred embodiment is the same as the first and second preferred embodiments, shown in Figs 1 and 5. The address counter 311 (including the address register 314) is reset in response to a reset signal to zero, and is incremented one by one in synchronization with clocks. Then, the actual counted value of clocks, which is counted until the carry signal (CARRY) is outputted, is compared with the previously-calculated reference value to decide whether the address counter 311 is operating normally or not. In the third embodiment, the address counter 311 can be preset to values other than zero. The memory tester 302 supplies an initial address to the preset terminal PRESET of the serial access memory 301, so that the initial address is held in the address register 314. The address counter 311 is incremented from the initial address, supplied from the address register 314, in synchronization with the clocks (CLK). For example, the address register 314 is supplied at addresses A9 to A0 with a signal of "1100000000," the address counter 311 is preset at addresses A9 to A0 to "1100000000." The memory tester 302 calculates the number of clocks (256) to be provided from the value of "1100000000" until a carry signal (CARRY) is outputted from the address counter 311. The memory tester 302 compares the previously-calculated reference value to the actual counted value. If the actual counted value is identical to the previously-calculated reference value, it is decided that the address counter 311 was operating normally for the period of time since the counter was preset until the carry signal (CARRY) was outputted. On the other hand, if the actual counted value is different from the previously-calculated reference value, it is decided that the address counter 311 was not operating normally. According to the third embodiment, the memory tester 302 is designed to preset the address counter 311 using the address register 314, so that the preset circuit can also be inspected. As described above, a method for testing a counter and a serial access memory according to the invention provides the following advantages: The counter can be tested easily in a short time without a read/write process to the memory. Further, the source of the detective can be found clearly from the test of the counter, because no reading and no writing process are performed to the memory array. In the above described embodiments, the address counter (111, 211 and 311) contained in the serial access memory (101, 201 and 301) is tested, however, the invention is applicable to other kinds of devices that include an address counter, which is to output a carry signal (CARRY). The memory tester (102, 202 and 302) can be realized not only by hardware but also software, for example stored in a ROM. It will be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations.

Claims: A method for testing an address counter (111) in a serial access memory (101) comprising an external reset terminal (RESET), an external clock terminal (CLK) and an external output terminal (COUT), using an external memory tester (102), the method comprising the steps of: supplying a reset signal from the memory tester (102) to the counter (111) via the reset terminal (RESET) setting the counter at a predetermined initial value, supplying clock signals from the memory tester (102) to the counter (111), via the clock terminal (CLK), counting the number of clock signals until a carry is outputted from the counter to the memory tester (102) via the output terminal (COUT) to provide an actual counted value, comparing the actual counted value to a reference value, which has been calculated in advance, and deciding on the basis of the result of the comparison whether the counter operates normally or not. The method according to claim 1, wherein the reference value is obtained by previously calculating the number of clock signals to be provided from the initial value until the carry is outputted from the counter. A system comprising a serial access memory comprising an address counter (111), an external reset terminal (RESET), an external clock terminal (CLK) and an external output terminal (COUT) which outputs a carry via the output terminal when it is overflowed, and an external memory tester (102) for testing the address counter (111), the memory tester (102) comprising: a reset circuit (120) for providing a reset signal to the counter (111) via the reset terminal (RESET) at a predetermined initial value, a clock generator (124) for providing clock signals to the counter (111) via the clock terminal (CLK), a counter circuit (126) which counts, in response to the signals, the number of the clock signals until the carry is outputted from the counter to the memory tester (102) via the output terminal (COUT) to provide an actual counted value, and a comparator (128) which compares the actual counted value with a reference value which is calculated in advance, wherein it is decided on the basis of the result of the comparison whether the counter (111) operates normally or not.

Inventors: IWAKIRI ITSURO C O, IWAKIRI, ITSURO, IWAKIRI, ITSURO C/O
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1997
Main classification: G11C29
IPC codes: G11C29, G01R31, G06F11, H03K21