SCALABLE TESTER ARCHITECTURE WITH I-CACHED SIMD TECHNOLOGY

Abstract: A high-speed semiconductor tester system with Single Instruction-stream Multiple Data-Stream (SIMD) organization, incorporating an event generator array, a plurality of pin channels for connecting to a device under test (DUT), a reconfigurable allocator switch for assignement of event generators to individual DUT pin channel connections, multi-clocking, and SIMD instruction cache. The result is a tester digital system exhibiting a maximum ratio of performance to hardware cost.

Description: SCALABLE TESTER ARCHITECTURE WITH I-CACHED SIMD TECHNOLOGY BACKGROUND OF THE INVENTION Field of the Invention This invention relates to parallel computers, semiconductor test equipment, and in particular to the engineering of such equipment for use in production of semiconductor devices for purposes of design and quality control. Description of the Related Art The predominant application of test during chip production is to determine whether a processed die conforms to the chip designer's expectations of its functional and electrical performance. A tester is a piece of capital equipment that allows the chip maker to perform this comparison at the "back end" of the semiconductor manufacturing pipeline. During test, a chip is referred to as a "device under test", or DUT. As is well known, such a chip has a plurality of electrical contact pins which serve as paths for input and output signals communicating with associated circuitry for controlling the chip and receiving responses therefrom. A tester studies a DUT by driving waveforms into its inputs while simultaneously observing its outputs during the test process. The requirements of a tester are stringent: A tester must be able to produce and measure waveforms whose transition rates are an order of magnitude greater than the DUT clock rate, and the tester must be able to accurately maintain timing precision that is an order of magnitude finer than the resolution of the DUT specifications. The results of test are used in a variety of ways. During production, the observations of output waveforms are used to establish that there is an absence of electrical faults within the chip. In failure analysis, the tester may stimulate the chip in an indefinitely repeating pattern while engineers probe internal nodes. An individual input signal transition or output signal measurement during a test is called a "pin event" or simply an "event". For characterization of a recently designed chip, the tester varies the times at which events occur so as to measure setup and hold margins for input signals with respect to input latch-control signals and to measure propagation delays from inputs to outputs. During the chip's design phase, test results validate the principles of operation of key circuits. The electrical characteristics generated for input waveforms and expected for output waveforms are created from the chip maker's voltage, current, and slew rate specifications. The collection of sub-circuits that produces input waveforms and measures output waveforms is a PE (Pin Electronics circuit). PEs are analog devices whose accuracy, flexibility, and power-bandwidth product are among the tester's key specifications. The internal design of the PEs is outside the scope of this invention. During a functional test, the sequence of logical states to be produced in an input waveform or expected to be present in an output waveform is created algorithmically from a test program. The heart of a modern tester is a digital system that generates a sequence of events for every DUT pin. A drive event on a pin directs that pin's PE driver to change the input waveform. A strobe event on a pin is a measurement of the pin's logical value as translated from its electrical value by the pin's PE comparator. Each drive event consists of a precisely timed change in the control signals going to the PEs, and each strobe event is a precisely timed measurement of the pin's output level against expectation. The digital representation of an event specifies a type (action, value, etc.) and a time. The event type is a digital code word that names one of the possible events. Some example events are "drive input to logic 0", "stop driving input", "check output for logic 1", and "stop checking output". The event time is typically specified as an integer multiple of some pre-determined time interval which corresponds to a least significant bit of event time code. Each digitally coded event is translated to an event that occurs close to the specified time. The tester's guaranteed closeness to the specified event time, known as the "edge placement accuracy", is among the tester's key specifications. With the advent in 1982 of IBM's Tester-per-Pin architecture, and its subsequent adoption in some form by nearly every tester manufacturer, the digital systems of testers have become very similar to SIMD (Single mstruction-Stream/Multiple Data-Stream) computers. A SIMD computer typically comprises one or more single-chip processing element modules, each having one or more processing elements and interfaces to multi- chip subsystems (MCSs). The processing elements bear the brunt of a SIMD computation's workload, while MCSs provide coordination among processing elements. An example of a conventional tester digital system 10 having a SIMD computer architecture is shown in Figs. 1-5. The system controller 20 runs a number of programs including the tester's operating system, test program development environment (compiler and debugger), results analysis tools, and DUT failure analysis tools. The primary function performed by the system controller 20 for the purposes of the digital system is storing and sequencing the test program. The digital system 10 (otherwise known as the high-speed system) is the tester's primary algorithmic component. The digital system 10 comprises an array of timing generators 70 (TGs, sometimes referred to as event generators) shown in Figs 4 and 5 that are collectively supervised by a single system controller 20. A group of timing generators 70 connects to each DUT pin's PE 80 circuit via a pin channel 82. The PE 80 circuit comprises a driver that produces input waveforms and a comparator that measures output waveforms against reference levels. The pin channel 82 fans in the TGs' 70 drive control outputs to the PE's drive control inputs, and the pin channel 82 fans out the PE's comparator outputs to the TGs' 70 measured pin value inputs. Individual events fall into the following four classes of precisely timed actions: (1) a change of the state of the PE driver driving the pin input (driver on/driver off), (2) a change of the value driven onto the pin by the PE driver (logic 1 /logic 0), (3) a change of the observation status of the pin output (begin comparing/stop comparing),or (4) an instantaneous observation of the pin output value (compare logic 1 /compare logic 0). During a test run, the system controller 20 executes a test program. The system controller 20 broadcasts a sequence of instructions to the array of TGs 70, which in response produces an event sequence for each DUT pin. A TG 70 is primarily a digital circuit that represents event types and application times as digital codes. In response to an instruction broadcast from the system controller 20, the TG 70 digitally calculates an event type, as well as the precise time of the application of that event to the DUT pin. These digital event codes are converted at the TGs' periphery to precisely timed driver control signal transitions (for input events) or to precisely timed pin value measurements (for strobe events). The conversion circuit is commonly called an event converter (or formatter) 74. The event converter 74 performs a digital-to-analog conversion of drive events and an analog-to-digital conversion of strobe events. The event converter's 74 time-domain digital-to-analog converter sub-circuit is called a vernier. The linearity, jitter, and re-trigger interval of the vernier contribute directly to a tester's most important performance characteristics. Fig. 2 shows some detail of the system controller 20. Via the operator console 31, the system controller 20 displays logged data to the operator, allows the operator to vary test parameters (pertaining to electrical, thermal, and timing characteristics of the DUT), and allows the operator to monitor and alter the test flow. The system controller's 20 disk storage device 32 is the ultimate repository of test programs. The system controller 20 generates a system clock and, on each cycle of that clock, an instruction which is distributed through a global instruction broadcast network 40, shown in Fig. 1. The globally broadcast instruction specifies the logical DUT activity for a tester machine instruction cycle in addition to DUT clock phase information. The globally broadcast instruction specifies one of a known set of collections of per-pin event sequences, one event sequence per DUT pin. The global instruction broadcast network 40 conveys the system clock and instructions to an array of TGs 70. The TGs 70 are embodied within Timing Generator Building Blocks 50 (TGBBs). The TGBBs 50 occupy the preponderance of the circuits included in the digital system. The TGs 70 respond to the system controller 20 with FAIL information indicating whether some DUT output pin strobe value differed from expectation on some vector. The TGs 70 also provide RDBACK information allowing the system controller to monitor the state of each system element. Fig. 3 schematically shows a conventional tester's TGBB 50. It contains an array of Timing Generator Modules 60 (TGMs), each of which in turn contains an array of TGs 70, associated with local memory 62 for storing TG configuration information including pattern data and local test result information including log data. As shown in Fig. 3, a conventional tester's TGMs 60 are associated on a 1-to-l basis with DUT pin channels. A conventional tester immutably associates the collection of TGs 70 within a TGM 60 with a uniquely determined DUT pin channel 82. Fig. 4 is a block diagram showing a conventional tester's TGM 60 containing K TGs 70 and a K-to-1 TG-to-pin aggregator 64 which functions as a parallel-to-serial converter. In a conventional tester, the value K is common among all TGMs 60. The TG- to-pin aggregator 64 in a conventional tester combines a plurality of drive events from the TGs 70 within the TGM 60 to send to the DUT pin channel 82 in a time sequential manner. Further, the TG-to-pin aggregator 64 fans out the measured pin value to all TGs 70 within the TGM 60 for reference in strobe events. The TGM 60 also contains a response network interface 65 and a local external memory interface 66. The local controller 68 shown in Fig. 4 serves the function of electrically standardizing the clock received from the globally broadcast instruction for re-broadcast within the TGM 60. The local controller 68 also may provide pipeline stages for the globally broadcast instruction for subsequent re-distribution within the TGM 60 via the local instruction broadcast network 69. Fig. 5 shows a conventional TG 70. The TG 70 contains a number of storage elements that are read-only during functional test and are used to construct the event sequence. The storage elements are writable only when the local storage write enable signal, generated by context mannger 72, is asserted. The context manager 72 allows selective initialization and querying of the TG 70 by the system controller 20. The event converter 74 converts digitally coded drive events to PE driver control signal transitions that occur at the desired point in time. The event converter 74 further converts digitally coded strobe events to fail outputs that are achieved by sampling the logical value of the DUT pin (as represented by the PE comparator outputs) at the desired points in time. The conventional TG 70 also contains a fail pipeline 78 through which log data is synchronized with the data logging requirements indicated in ensuing globally broadcast instructions. As noted above, IBM introduced the "timing-per-pin" organization, wherein the TG 70 associated with each DUT pin channel 82 contained a timing generator circuit. This organization had the flexibility advantage of providing each DUT pin with potentially unique timing characteristics. In the 1980s and into the 1990s, a number of tester manufacturers expanded on the timing-per-pin organization to include a collection of TGs 70 per pin. The TGs 70 in such systems are not necessarily replications of a single circuit design, but instead may be special-purpose circuits. The TGs 70 do not function independently, but produce events per tester machine instruction cycle as directed by a waveform memory associated with each DUT pin. This architecture is widely used in test equipment sold today. In 1988, Schlumberger developed the "sequencer-per-pin" organization [West and Napier, "Sequencer Per Pin™ Test System Architecture", International Test Con/erence Proceedings, pp. 355-361, 1990]. This digital system architecture provided for each DUT pin channel 82 a fixed-size collection of timing generators 70 and a sequencer for assigning events to timing generators 70 for application to the DUT pin channel 82. This organization had the advantage of a high degree of flexibility in the timing characteristics of the waveform generated independently for each DUT pin. In 1989, ASTX proposed a digital system organization wherein the TGs 70 were inter-connected via a linear array network [Lesmeister, "The Linear Array Systolic Tester (LAST)", International Test Con/erence Proceedings, pp. 543-549, 1989]. This digital system organization allowed the TGs 70 to share access to a common pattern memory, thus decreasing the memory bandwidth requirement, thereby decreasing the cost of the test system. In 1992, LTX/Trillium proposed a single-chip TG 70 design that contained an on- chip phase-lock loop (PLL)-based clock generator [Alton, "TGEN: Flexible Timing Generator Architecture", International Test Con/erence Proceedings, pp. 439-443, 1992]. The PLL output oscillated at 4 times the system clock rate but was not used to multiply the event rate above the system clock rate. Rather, the high-rate reference clock was used to simplify the implementation of a sub-clock-interval vernier (edge converter 74), whose linearity is critical to the tester's overall timing accuracy. Linearity tends to decrease as the length of clock interval spanned increases, so the high-rate on-chip clock was used to shorten the interval spanned by the vernier. In 1992, Hewlett-Packard developed the "processor-per-pin" organization [Schoettmer and Minami, "Challenging the Ηigh Performance - High Cost' Paradigm in Test", International Test Con/erence Proceedings, pp. 870-879, 1995]. This digital system architecture provided for each DUT pin channel 82 an independently programmed test processor for generating sequences of logical values and controlling the generation of successive events for application to the DUT pin channel 82. This organization had the advantage of reducing the amount of information delivered through the global instruction broadcast network 40, thus reducing its cost. By moving sequencing from the system controller 20 into the TG 70, the HP invention surmounts the global instruction broadcast bottleneck, which limits the flexibility and scalability of a test system and therefore tends to increase its cost. Although a SIMD computer architecture has an inherent advantage of low cost, the conventional semiconductor test systems in the foregoing are unsuccessful in reducing the manufacturing cost. In fact, the portion of a tester's manufacturing cost represented by this digital system has grown over the last 25 years to approximately 60%, and signs are that portion will continue to increase as provision is made for per-pin ALPG (Algorithmic Pattern Generation) or DSP (Digital Signal Processing). In the conventional test systems noted above, although each group of several timing generators 70 are allocated to a corresponding pin of the DUT to combine the events and form a high speed test pattern, such a relationship is fixed between the group of timing generators 70 and the DUT pin. The manufacturing cost is high because each tester variant requires a unique combination of timing generators 70, since it is not possible to freely reconfigure the timing generators-pin relationship. In the SIMD based semiconductor tester, each of the timing generators includes a generally programmable processor element. However, in the conventional tester, there is no data communication among the timing generators 70. Consequently, the conventional tester is not able to achieve sufficient flexibility in the event generation, such as performing a digital signal processing function or algorithmic pattern generation per pin. The conventional tester includes an expensive system controller 20 to achieve high speed operations performed by a high frequency system clock. Moreover, such a high system clock rate requires a high speed global instruction broadcast network 40 as well as a high speed system controller 20, resulting in high cost in the tester hardware. SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a semiconductor tester incorporating a Single Instruction-stream Multiple Data-stream (SIMD) computer architecture which can be commonly used from low end to high end semiconductor tester systems, achieving high manufacturing efficiency and associated low cost throughout this spectrum. It is another object of the present invention to provide a semiconductor tester incorporating a SIMD computer architecture which is capable of flexibly and freely allocating timing (event) generators (TGs) to any pins of a semiconductor device under test (DUT). It is a further object of the present invention to provide a semiconductor tester incorporating a SIMD computer architecture which is capable of flexible event generation by communicating test information among a plurality of TGs to achieve a sophisticated and high level performance with relatively low-cost hardware resources. It is a further object of the present invention to provide a semiconductor tester incorporating a SIMD computer architecture in which a system controller can be formed of a low cost computer such a personal computer, even for a high end semiconductor tester. It is a further object of the present invention to provide a semiconductor tester incorporating a SIMD computer architecture which is capable of efficient test vector generation by using high speed timing generators without requiring a high speed system controller or a high speed global instruction broadcast network. It is a further object of the present invention to provide a semiconductor tester incorporating a SIMD computer architecture which is capable of efficient test vector generation by using a combination of a multiple clock generator and an instruction cache. In one aspect of the present invention, the semiconductor tester for testing a DUT includes a plurality of pin electronics circuits corresponding to a plurality of pins of the DUT for operative connection thereto in one-to-one relationship, a plurality of pin channels individually coupled to corresponding pin electronics circuits for communication with corresponding DUT pins, a digital system controller for generating a system clock and for storing and sequencing at least one test program, a plurality of timing generator modules responsive to the digital system controller, and a plurality of multi-chip subsystems for controlling, coordinating, and memory-augmenting the timing generator modules. Each timing generator module is a single semiconductor chip having an array of timing generators formed thereon for creating predetermined sequences of precisely timed drive events and strobe events for testing the DUT. The timing generators are operatively associatable with selected ones of the pin channels. Each timing generator module further includes interface connections between the multi-chip subsystems and each of the timing generators in the module. In the present invention, timing generators (TGs) are flexibly allocated to the DUT pins under software control. The timing generators are inter-connected so as to exchange intermediate data therebetween. According to the present invention, standard timing generators of relatively low cost can be used in a variety of testers since the timing generators are freely allocated to meet the requirements or specifications of the tester. Further, complicated test pattern generation such as algorithmic patterns or a complicated processor operation such as digital signal processing can be performed by the pattern generators of the present invention by the intermediate data exchange. In another aspect of the present invention, a semiconductor tester having a SIMD computer architecture includes a global instruction broadcast network regulated by a system clock signal oscillating at a system clock rate, a multi-chip subsystem regulated by a second clock signal, a timing generator module implemented on a single chip and coupled to the global instruction broadcast subsystem and to the multi-chip subsystem, and a multi-clock generating circuit for generating, responsive to the system clock signal, a plurality of clock signals whose clock rates are higher than the system clock rate, and an instruction cache element for storing instructions and retrieving the instructions at a clock rate higher than the system clock rate. The multi-clocking of the present invention allows the local generation of high-rate clocks within the TG modules, and the instruction cache eliminates the need for high-speed global instruction broadcast. According to the present invention, the timing generator modules include the instruction cache and utilize a clock signal generated by the multi- clock generation circuit whose frequency is higher than that of the system clock to access the memories. Therefore, the semiconductor tester of the present invention can achieve high speed test generation with relatively low cost hardware. BRIEF DESCRIPTION OF THE DRAWINGS A better understanding of the present invention may be realized from a consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which: Fig. 1 is a schematic block diagram showing a conventional semiconductor tester architecture described hereinabove. Fig. 2 is a schematic block diagram showing a system controller 20 in the conventional technology of Fig. 1. Fig. 3 is a schematic block diagram showing a timing generator building block (TGBB) 50 in the conventional technology of Fig. 1. Fig. 4 is a schematic block diagram showing a timing generator module (TGM) 60 in the conventional technology provided in the TGBB 50 of Fig. 3. Fig. 5 is a schematic block diagram showing a timing generator (TG) 70 in the conventional technology provided in the TGM 60 of Fig. 4. Fig. 6 is a schematic block diagram showing a preferred embodiment of the semiconductor tester architecture of the present invention. Fig. 7 is a schematic block diagram showing an example of a timing generator building block (TGBB) 150 of the present invention of Fig. 6 with reconfigurable allocator circuit elements. Fig. 8 is a schematic block diagram showing an example of structure in a timing generator module (TGM) 160 of the present invention. Fig. 9 is a schematic diagram showing an example of an event calculator 176 of the present invention provided in the timing generator. Fig. 10 is a schematic diagram showing an example of an event converter 174 of the present invention provided in the timing generator. Fig. 11 is a circuit diagram showing an example of a drive decoder provided in the event converter circuit 174 of the present invention. Fig. 12 is a circuit diagram showing an example of a linear delay element provided in the event converter circuit 174 of the present invention. Fig. 13 is a circuit diagram showing an example of a strober provided in the event converter circuit 174 of the present invention. Fig. 14 is a schematic block diagram showing a basic concept of a reconfigurable allocator circuit 152 of the present invention. Fig. 15, 15A and 15B are circuit diagrams showing an example of a reconfigurable allocator circuit 152 of the present invention. Fig. 16 is a schematic circuit diagram showing a topological example of a reconfigurable allocator circuit 152 of the present invention which is a 64-to-8 allocator circuit. Fig. 17 is a schematic block diagram showing an example of a structure of a local controller 168 including a multi-clock generator and a SIMD instruction cache. Fig. 18 is a schematic diagram showing an example of timing generators and pin electronics combined together to be mounted in a test head of a semiconductor tester. Fig. 19 is a schematic diagram showing a hardware image of the semiconductor tester of the present invention. Fig. 20 is a schematic diagram showing a hardware image of the semiconductor tester of the present invention based on the configuration of Fig. 18. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 6 is a schematic block diagram showing a configuration of a digital system 100 in the semiconductor tester of the present invention incorporating a SIMD computer architecture. The inventor named this architecture "STAR-I (Scalable Tester Architecture with I-Cached SIMD Technology)". This application incorporates by reference the disclosure of the same inventor's patent called "I-Cached SIMD" (U.S. Patent No. 5,511,212, issued April 23, 1996, Multi-Clock SIMD Computer and Instruction-Cache- Enhancement Thereof). That invention relates to Single Instruction-stream Multiple Data- stream (SIMD) computer architecture. This disclosure of STAR-I teaches means that allow the tester digital system to exploit the construction flexibility and programming scalability advantages of SIMD computer architecture. In a further aspect, STAR-I contains a circuit that allows the event- generation circuits to be flexibly allocated to DUT pins, thus reducing the cost of constructing a system capable of achieving required event rates when the event rate requirement varies across pins. In a further aspect, STAR-I applies Multi-Clock SIMD computer architecture to allow the multi-chip and intra-chip circuits within the tester digital system to operate each at its maximum rate as determined by the circuit structure and the signaling characteristics of the VLSI-based technology in which the circuits are realized. STAR-I maximizes the tester digital system's performance-to-hardware-cost ratio by applying what is taught in the I-Cached SIMD patent. In the digital system 100 of Fig. 6, a system controller 120 sends a system clock and instructions to a global instruction broadcast network 140 based on the test program. The digital system 100 includes an inter-TG communication network 112 allowing exchange of data among the timing generator building blocks (TGBBs) 150. The system controller 120 transmits the system clock and the instructions to the TGBBs 150 through the global instruction broadcast network 140. The TGBB 150 contains an array of timing generators 170 whose architecture is that of a generally programmable processing element which will be described in more detail later. Such an inter-TG communication subsystem 112 is absent from conventional testers because production test as it is commonly realized requires no inter-TG communication. The advantage of including an inter-TG communication network 112 is that it enables the TGs 170 to share intermediate results, such as are generated during the execution of ALPG (Algorithmic Pattern Generation) or DSP (Digital Signal Processing) algorithms. The inter-TG communication system of the present invention is unique in that it has higher-dimensional interconnections (including 2-D and 3-D meshes) as well as bidirectional communication links, and it allows for exchange of TG register file data under control of the global broadcast instruction stream transmitted via the global instruction broadcast network 140. The events generated by the TGs 170 in the TGBBs 150 are freely allocated to pin electronics (PE) 180 through DUT pin channels 182. This enhancement over the conventional tester's somewhat-configurable TG 70 increases flexibility and scalability, for example allowing the TG design cost to be amortized over a larger number of instances sold. A response network 190 transmits the test results, such as fail information, to the system controller 120. Fig. 7 is a block diagram showing an example of the TGBB 150 with a reconfigurable allocator circuit 152. The TGBB 150 contains an array of timing generator modules 160 (TGMs), each of which in turn contains an array of TGs 170, associated with local memory 162 for storing TG configuration information including pattern data and local test result information including log data. An inter-TG network & interface 154 interconnects between the TGMs 160 within the TGBB 150 and provides an interface to the inter-TG network 112. The reconfigurable allocator circuit 152 is a software-configurable reconfigurable circuit, through which a subset of the set of TGs 170 is associated with one member of a subset of the set of DUT pin channels 182. The association achieved by the reconfigurable allocator circuit 152 is to multiplex the drive events produced by each member of the subset of TGs onto the corresponding drive control input of the pin channel, and also to fan out that pin's observed logical value for use by strobe events within each member of the subset of TGs. More details of the reconfigurable allocator circuit 152 will be described later with reference to Figs. 14-16. Fig. 8 is a block diagram showing the TGM 160 containing an array of TGs 170 of the present invention. Each of the TGs 170 contains an event calculator 176 and an event converter 174. The event calculator 176 produces coded event data based on the instructions from the system controller 120. The event converter 174 converts the digitally coded drive events from the event calculator 176 to PE driver control signal transitions that occur at the desired points in time. The event converter 174 further converts digitally coded strobe events to fail outputs that are achieved by sampling the logical value of the DUT pin (as represented by the PE comparator outputs) at the desired points in time. The system clock and the instructions from the system controller 120 are transmitted to the TGs 170 through a local controller 168 and a local instruction broadcast network 169. The TGM 160 also contains a response network interface 165 and a local external memory interface 166, as well as an inter-TG communication network interface 154. In addition to the conventional functions, one of the features of the local controller 168 shown in Fig. 8 is to generate multiple clocks derived from the system clock which regulates high speed event generation by TGs 170 using clock signals whose frequency is higher than that of the system clock. The local controller 168 controls such high speed event generation by including an instruction cache element having a cache controller and a cache memory. More details of the local controller 168 are described below with reference to Fig. 17. Fig. 9 shows an example of structure of the event calculator 176 of the present invention. In this example, the event calculator 176 includes a function unit 211, a register file 212, a instruction map/parameter store 213, a context manager 214, an external memory interface 216, an inter-TG communication interface 217, a fail network interface 218, and a bus interface 219. The event calculator 176 of Fig. 9 operates as follows: Operation of all components during each clock cycle is controlled by an instruction received via the local instruction broadcast network 169. The bus interface 219 provides a low-speed pathway for initialization of the storage elements within the event calculator 176 prior to a test run, and for extraction of results after a test run. The function units 211 perform the calculations necessary to create digitally coded events that are transmitted to the event converter. The constituents of the function units 211 are such circuits as are necessary to perform the required functions, including ALU, rotate/shifter, and possibly a multiplier or divider unit. The bit width of the calculation units is a non-critical parameter, w. The function units 211 also perform calculations to process strobe fail information received from the event converter 174. The function units 211 calculate addresses for access to the register file 212. The function units 211 operate on values stored in the register file 212, and results of function unit 211 calculations may be stored in the register file 212. The values that are contained in the register file 212 include the values typically associated with waveform definitions, including programmed event times and calibration offsets. Such storage as is needed to delay fail results prior their storage or transmission is provided by the register file 212. The instruction map 213 is a memory element that provides parameters for use in event calculations. The instruction map 213 provides an indirect way to specify timing parameters, which is convenient for testing devices with complex timing. The instruction map 213 allows the timing parameters of the calculated event to depend upon a field of the broadcast instruction that designates the type of device activity occurring at each step of the test run. One way to use the parameters stored in the instruction map 213 is as an address offset into the timing values stored in the register file 212. The external memory interface 216 provides a path for pattern values into the function units 211 as well as a path for captured fail values out of the function units 211. The inter-TG communication interface 217 provides a path for the exchange of data with topologically neighboring event calculators 176. One application of the inter- TG communication interface 217 is to provide current pin state information for use by the function units 211 in calculating the next event. In addition, the change to the pin state effected by the event calculated by the function units 211 is output via the inter-TG communication interface 217, where it may be referenced by other event calculators 176. The fail network interface 218 provides a path for fail information to be signaled to the system controller 120. The system controller 120 uses fail information to control the sequencing of a test program during a test run. The context manager 214 produces an output signal that inhibits or enables state changes within the event calculator 176. The context manager 214 determines whether state changes are allowed within the event calculator 176 in response to broadcast instructions and dependent upon conditional results produced by the function units 211. The context manager 214 provides a fully general means by which data-dependent operation of the event calculator is achieved. Fig. 10 is a schematic diagram showing an exemplary configuration of the event converter 174 of the present invention. In this example, the event converter 174 includes a decoder 221, a drive encoder 222, a strober 223 and a linear delay element 224. The decoder 221 receives the drive events described by the digital code such as "ACT" indicating event actions (Drive, Strobe, or Window), "VAL" indicating logical values of the events (0, 1, X, or Z). The decoder 221 interprets the codes and produces corresponding event signals, for example DRV (Drive Action), STB (edge Strobe Action), OPN (Window Open Action), CLS (Window Close Action), ONE (Logic Value 1), ZRO (Logic Value 0), EX (Don't Care), and ZEE (High Impedance). The drive encoder 222 receives the event signals and produces set and reset signals corresponding to the event signals to be provided to PE 180 drivers via the reconfigurable allocator circuit 152. The strober 223 receives signals from PE 180 comparator (not shown) via the reconfigurable allocator circuit 152 and compares the signals with expected logic values defined by the decoder 221 at the timing of the strobe. The linear delay element 224 produces, based on the time code from the event calculator 176, a delayed pulse DP whose timing resolution is smaller than the period of the system clock. Fig. 11 is a circuit diagram showing an example of the drive encoder 222 of the present invention. The drive encoder 222 operates as follows: Each of the outputs is leading edge active. The outputs are transmitted via the reconfigurable allocator circuit 152 to the pin electronics 180 driver circuit (not shown). The outputs are gated derivatives of the DP pulse, so the DP pulse determines the timing of the active edges. The DHS (Drive High Set) signal is enabled when the action is DRV and the value is ONE. The DHR (Drive High Reset) signal is enabled when the action is DRV and the value is ZRO. The DIS (Drive Inhibit Set) signal is enabled either 1) when the action is DRV and the value is neither ONE nor ZRO, or 2) when the action is not DRV. The DIR (Drive Inhibit Reset) signal is asserted when the action is DRV and the value is either ONE or ZRO. Fig. 12 is a circuit diagram showing an example of the linear delay element 224 in the event converter 174 of the present invention. The linear delay element 224 includes a plurality of series connected delay elements 242ι-242 n and a multiplexer 245. An example of such a delay element 242 is a pair of CMOS inverters connected in sequence. Each output of the delay element 242 is connected to a unique input of the multiplexer 245. Based on the code TIM (offset of event within tester period) from the event calculator 176, the multiplexer 245 selects an appropriate output of the delayed element as the delay pulse DP. Fig. 13 is a circuit diagram showing an example of the strober 223 provided in the event converter 174 of the present invention. In operation, the strober 223 captures the results of device output as compared against expectations at specific times determined by the leading edge of the DP signal. The inputs ACH (Above Compare High) and BCL (Below Compare Low) from the pin electronics 180 comparators are mutually exclusive (not both can be asserted at any given time). The inputs ZRO, ONE, and ZEE from the event calculator are mutually exclusive, providing a one-hot indication of the expected value. The inputs CLS, OPN, and STB from the event calculator are mutually exclusive, indicating the specific strobe action, if any. To perform edge strobes, the strober evaluates comparisons at precise times. To perform window strobes, the strober opens and closes a window at precise times. Comparisons are evaluated continually during the period of time in which the window is open; comparison failures occurring when the window is open are captured in a storage element. In Fig. 13, the SFL (Strobe Fail) output is produced by OR 275. The upper input to OR 275 comes from the edge strobe fail D-FF 271, while the lower input to OR 275 comes from window strobe fail latch 274. Edge strobe failure (EFL) signal is captured in D-FF 271 by the leading edge of circuit input DP. EFL signal is generated by OR 264 as the disjunction of three edge strobe conditions: 1) expected value is ONE and pin value is not ACH (generated by AND 257), 2) expected value is ZRO and pin value is not BCL (generated by AND 258), or 3) expected value is ZEE and pin value is either ACH or BCL (generated by AND 259). Window strobe fail latch 274 is set by a signal generated by AND 272. AND 272 evaluates the conjunction of the window fail (WFL) signal and the output of window open latch 268. The output of latch 268 is asserted if and only if the strobe window is open. WFL signal is generated by OR 265 as the disjunction of three window strobe conditions: 1 ) expected value is ONE and pin value is not ACH (generated by AND 262), 2) expected value is ZRO and pin value is not BCL (generated by AND 263), or 3) expected value is ZEE and pin value is either ACH or BCL (generated by AND 261). The expected value for comparison during a strobe window is indicated by the 3 D- FFs 253, 254, and 256, whose values are mutually exclusive. AND 251 generates a latch control signal so that these values are captured on the rising edge of DP when OPN is asserted. Window open latch 268 is set by the conjunction of OPN and DP generated by AND 266. Window open latch 268 is reset by the conjunction of CLS and DP generated by AND 267. Window strobe fail latch is reset by the conjunction generated by AND 273 of DP and the disjunction generated by OR 269 of OPN and STB. Figs. 14-16 show examples of reconfigurable allocator circuits of the present invention. One of the features of the present invention resides in the fact that the digital system 100 includes the software-configurable reconfigurable allocator circuit 152, through which a subset of the set of TGs is associated with one member of a subset of the set of DUT pin channels. Fig. 14 shows a basic concept of the reconfigurable allocator circuit 152. The association achieved by the reconflgurable allocator circuit 152 is to multiplex the drive events produced by each member of a subset of TGs onto the corresponding drive control input of the pin channel and also to fan out that pin's observed logical value for use by strobe events within each member of the subset of TGs. The appropriate size and hierarchical decomposition of the reconfigurable allocator circuit 152 is determined by the geometries of the elements composing the integration hierarchy used in the physical realization of the tester digital system. The most general reconfigurable allocator circuit 152 is an NxM cross-bar through which any of the tester's N TGs 170 is associated with any of the DUT's M pins. The simplest way of deciding how to configure a reconfigurable allocator circuit 152 restricts the subsets of TGs connected to each DUT pin to be strictly disjoint subsets of the set of TGs 170. In other words, the simplest method of configuring a reconfigurable allocator circuit 152 imposes a many-to-one mapping from TGs to DUT pins. At the maximally complex other end of the spectrum, a reconfigurable allocator circuit 152 implements a many-to-many mapping, so that each TG 170 in the tester digital system 100 is associated with some number of DUT pins, and each DUT pin is associated with a plurality of TGs 170. This more complex TG-to-DUT-pin allocation method is able to take advantage of scenarios wherein a single TG's outputs may be shared among a plurality of DUT pins. The simpler method, on the other hand, allows for a circuit interconnect topology that requires relatively few active elements for its realization. Figs. 15, 15A and 15B illustrate a circuit that realizes the full crossbar topology of the reconfigurable allocator circuit 152. The configuration of the reconfigurable allocator circuit 152 is controlled via the values in the set of configuration bits 400, for example those labeled All u-a, All u-b, All v-a, and All v-b, etc. in Fig. 15 where "All x- d" indicates -Allocate Timing Generator x to Pin Channel d— . A given configuration bit 400 All u-c being asserted indicates that TG 170 index u is allocated to DUT pin index c. The system controller 120 determines the values of all configuration bits 400 in the reconflgurable allocator circuit 152. The configuration bits 400 may be initialized via the system bus prior to a test run, or they may be changed dynamically in response to globally broadcast instructions during a test run. During any given step of the test run, the set of configuration bits 400 associated with a given TG 170 index u is one-hot encoded. Therefore, at most a single member of the set of configuration bits 400 All u-a, All u-b, All u-c, and so on is asserted at any given time. The reconfigurable allocator circuit 152 synthesizes the drive control inputs for each DUT pin and selects a single pin's measurements for each event converter 174. The DHI (Drive High) signal for a given DUT pin's pin electronics 180 driver is generated in latch 405 (Fig. 15B). The DHS pulse from any of the event converters 174 associated with that pin sets the DHI latch 405. The aggregation of DHS pulses is achieved by OR 410. The input pulses to OR 410 are generated by AND 420, AND 421, and so on, each of which gates the DHS pulse from a given event converter 174 with the corresponding configuration bit 400. Similarly, the DHR pulse from any of the event converters 174 associated with that pin resets the DHI latch 405. The aggregation of DHR pulses is achieved by OR 411. The input pulses to OR 411 are generated by AND 422, AND 423, and so on, each of which gates the DHR pulse from a given event converter 174 with the corresponding configuration bit 400. The DINH (Drive Inhibit) signal for a given DUT pin's pin electronics driver is generated in latch 406. The DIS pulse from any of the event converters 174 associated with that pin sets the DINH latch 406. The aggregation of DIS pulses is achieved by OR 412. The input pulses to OR 412 are generated by AND 424, AND 425, and so on, each of which gates the DIS pulse from a given event converter 174 with the corresponding configuration bit 400. Similarly, The DIR pulse from any of the event converters 174 associated with that pin resets the DINH latch 406. The aggregation of DIR pulses is achieved by OR 413. The input pulses to OR 413 are generated by AND 426, AND 427, and so on, each of which gates the DIR pulse from a given event converter 174 with the corresponding configuration bit 400. The ACH signal to a given event converter 174 is aggregated in OR 430 (Fig. 15 A). The ACH signal from the single pin electronics 180 comparator circuit associated with that event converter 174 is enabled by one of AND 441, AND 442, and so on, depending upon which of the one-hot configuration bits 400 is asserted. The BCL signal to a given event converter 174 is aggregated in OR 431. The BCL signal from the single pin electronics 180 comparator circuit associated with that event converter 174 is enabled by one of AND 443, AND 444, and so on, depending upon which of the one-hot configuration bits 400 is asserted. A further enhancement of the reconfigurable allocator circuit 152 is to allow reconfiguration during functional test. This enhancement allows a given TG 170 to be connected successively to members of a group of DUT pins. This "run-time TG 170 re- allocation" capability caters to the applications such as edge search, wherein a single member of a group of pins receives a relatively large number of events during some interval of the test. By varying the assignments to the configuration bits 400 of the reconfigurable allocator circuit 152 during a test run, a relatively small number of timing generators 170 is able to meet the edge rate requirement that, in a conventional tester's digital system's fixed allocation of timing generators 170 to DUT pins, would require many more timing generators 170 and thus greater expense. Fig. 16 shows other example of a reconfigurable allocator circuit 152 implementation that is appropriate for the simple (many-to-one) allocation method, and which is less costly than a full cross-bar. In the example of Fig. 16, the reconfigurable allocator circuit 152 is capable of realizing many-to-one associations between 64 TGs 170 and 8 pin channels 182. The topology of the reconflgurable allocator circuit 152 sketched in Fig. 16 illustrates the concept of exploiting asymmetry to minimize implementation cost. In Fig. 16, not all DUT pins are connectable to a common number of TGs 170. The idea is that, since only one DUT pin can be allocated all 64 of the TGs 170 in the subset, then designate a single pin (in this case pin 0) that is capable of being allocated all TGs 170 in the subset. Similarly, since only two DUT pins can be allocated 32 TGs 170 each, then designate a second pin (in this case pin 7) that is capable of being allocated the half of the subset of TGs 170 that is not being used by pin 0. Similar reasoning applies to allocating 16 TGs 170 to each of 4 DUT pins, and finally to allocating 8 TGs 170 to each of the 8 DUT pins composing the subset of DUT pins included in the example of Fig. 16. A general mathematical formulation for the topology of the reconfigurable allocator circuit 152 shown in Fig. 16 with an interconnection for a set of I TGs 170 numbered from 0 up to 1-1 and a set of J pin channels 182 numbered from 0 up to J-l may be described with the following two principles: (1) the number of TGs 170 in the subset that may be associated with the pin channel 182 whose index is j is given as I/(ceiling(log2(j+l))- (2) the subset of TGs 170 associated with pin channel j is disjoint from the subsets of TGs 170 associated with each of the 2 ce,lmg(log 2 (,+1) - 1) pin channels 182 whose indices lie in the following range: 2ceιhng(log ( j +l)-l)_ | _ι 2 ce,lm g( lo g <J + l)-l) + 2 As suggested by the presence of a K-to-1 TG-to-pin aggregator 64 in Fig. 4, conventional tester digital systems allocate a fixed number of TGs to each pin by performing aggregation within the TGM 160. In the conventional tester, a common number of TGs is associated with each DUT pin, unless expensive measures, fixed at the time of system manufacture, are taken so as to bring to bear on a high-event-rate pin the TG resources that would otherwise have served multiple pins. However, it can readily be shown that not all DUT pins require a common event rate. The event rate required for a pin is determined by the design objectives of the DUT and by the objectives of a given test. At any given point during the testing of a DUT, some pins need higher event rates while other pins need lower event rates. In a conventional tester, when a pin requires a higher event rate (and thus more TGs), considerable hardware expense is incurred. Should a pin actually require a lower event rate, then the excess TGs allocated to the pin represent hardware expense that is wasted. The advantages of connecting TGs to pins via a reconfigurable allocator circuit 152 of the present invention include reducing the hardware cost required to achieve the required per-pin event rate. Fig. 17 is a schematic block diagram showing an example of the local controller 168 in the event generator module 160 of the present invention. The local controller 168 comprises a multi-clock generator 300, a SIMD instruction cache 310, a broadcast instruction latch 320, and a collection of local instruction latches, including TG control 330, LEM (Local External Memory) control 341, RAC (Reconflgurable Allocator Circuit) control 342, Response control 343, and Inter-TG communication control 344. The multi-clock generator 300 includes a clock multiplier circuit such as may be realized using a phase lock loop to generate an individual clock regulating each circuit within or connected to the TGM 160. The clocks generated by the multi-clock generator 300 regulate each circuit at its maximum rate. The maximum rate of operation of each circuit is determined by its geometry and by the VLSI implementation technique: signaling through longer wires is slower and or more expensive than signaling through shorter wires, all else being equal. The global instruction broadcast network 140 extends across the entire digital system and is therefore expected to operate at the lowest rate of any of the circuits in the digital system. Therefore, the CLK input to the multi-clock generator 300 will be the lowest-rate clock signal in the digital system. It is expected that the TGs 170, realized entirely within the confines of a single- chip TGM 160, operate at the highest rate of any of the circuits in the digital system. Therefore, TG CLK will be the highest-rate clock signal output by the multi-clock generator 300. In the simplest embodiment, all clock rates are sub-multiples of the TG CLK rate and all phases are aligned. More elaborate circuits would allow rational multiples of the TG CLK rate and arbitrary (although deterministic) phase relationships. The response network 190 is similar to the global instruction broadcast network 140 in that it extends system-wide. Therefore, the response network 190 is expected to be as slow as the global instruction broadcast network 140, although it may operate at a higher rate. Correspondingly, the RESPONSE CLK output by the multi-clock generator 300 may be as slow as CLK, but it may be faster. The reconflgurable allocator circuit 152 would likely be implemented in components that have connectivity that is restricted to single printed circuit boards. Therefore, its operation rate would lie somewhere between that of the global instruction broadcast network 140 and the TG 170. Correspondingly, the frequency of the RAC CLK output by the multi-clock generator 300 may be as slow as that of CLK, as high as that of TG CLK, or some point in between. The local external memory circuit, including the local external memory interface 166 and memory chips, contains only short inter-chip connections between the TGM 160 and the memory chips 162. Therefore, the local external memory circuit may operate at a rate very near that of the TG 170. Correspondingly, the LEM CLK output by the multi- clock generator 300 may be nearly as fast as TG CLK, perhaps only slower by a factor of 2. The system clock CLK regulates the broadcast instruction latch 320. The broadcast instruction latch 320 stores globally broadcast instructions. TG CLK regulates TG control 330. TG control 330 stores cycle-by-cycle instructions for the TGs 170. LEM CLK regulates LEM control 341. LEM control 341 stores cycle-by-cycle instructions for the local external memory circuit. RAC CLK regulates RAC control 342. RAC control 342 stores cycle-by-cycle instructions for the reconflgurable allocator circuit 152. INTER-TG COMM CLK regulates inter-TG communication control 344. Inter-TG communication control 344 stores cycle-by-cycle instructions for the inter-TG communication network 112. RESPONSE CLK regulates response control 343. Response control 343 stores cycle-by-cycle instructions for the response network 190. The SIMD instruction cache 310 is regulated by TG CLK. The SIMD instruction cache 310 stores sequences of instructions that are executed repeatedly. The SIMD instruction cache comprises a cache memory 314 and a cache controller 312. The cache memory 314 is an instruction storage element that is controlled by the cache controller 312. In response to cache control protocol instructions embedded in the sequence of globally broadcast instructions, the cache controller 312 writes instructions into the cache memory 314. Instructions are written into the cache memory 314 in this manner at the low rate of global instruction broadcast. In response to further globally broadcast instructions, the cache controller 312 extracts sequences of instructions from the cache memory 314 at the high rate of TG CLK. If a tester digital system is a SIMD computer, then it is subject to the global instruction broadcast bottleneck which is a fundamental limitation of conventional SIMD computer architectures. Therefore, the techniques of multi-clocking and instruction- caching that overcome the global instruction broadcast limitation for SIMD computers in general also overcome the global instruction broadcast limitation for tester digital systems in particular. It has been established that I-Cached SIMD technology increases the performance-to-cost ratio of SIMD computers by factors of 2 to 5 or more. It is reasonable to expect a proportionate decrease in tester cost at constant performance by applying the enhancements described in the I-Cached SIMD patent to the tester digital system. Consequently, the STAR-I tester digital system allows sequences of event generation instructions that are repeated during functional test to be delivered to the DUT at the TG's highest rate of operation. Fig. 18 is a schematic diagram showing an example of timing generators TGs 170 and pin electronics PEs 180 combined together to be mounted in a test head of a semiconductor tester. Future increases in BiCMOS ASIC integration densities will make it possible to migrate the SIMD array cage (containing the TGs 170) shown in Fig. 8 into the test head (containing the Pes 180) while migrating the PEs 180 into the reconfigurable allocator circuits 152 which would allow further manufacturing cost reduction. Fig. 19 is a schematic diagram showing a hardware image of the semiconductor tester of the present invention incorporating the digital system of Fig. 6 in a SIMD array cage 200. Similarly, Fig. 20 is a schematic diagram showing a hardware image of the semiconductor tester of the present invention based on the configuration of Fig. 18. The present invention has a number of advantages over the conventional architecture. A conventional tester's system controller is expensive, comprising typically an engineering workstation, an internal Ethernet, a RISC processor board, a custom CPU bus interface (for example, VME), and a custom high-speed sequencer, which is typically a multi-custom-PCB circuit containing several ASICs. In stark contrast to this expensive implementation, the system controller as embodied in the present invention comprises only an inexpensive standard microcomputer (for example, an x86-based PC) equipped with disk drive, high-quality display, and a standard system bus interface (for example, PCI). A conventional tester's global instruction broadcast network consists of a workstation bus (for example, VME), a custom CPU bus controller, a signal fan-out network conveying on the order of 100 bits of instruction to the TGBBs at very high speed (for example, 500MHz), a digital system clock generator, and trimmed and balanced transmission lines for distribution of the collection of high-speed signals. In stark contrast to this expensive implementation, the global instruction broadcast network as embodied in the present invention comprises only a standard microcomputer system bus, with fewer than 100 signals bussed at low signaling rate to the array of TGBBs. The tester's response network contains a FAIL tree, for rapid detection by the system controller of a failure having been detected by any TG for any DUT pin, and a slower, wider path for reading the contents of any storage location. In addition to a conventional FAIL tree, the response network embodied in this invention contains a standard microcomputer bus which is less expensive than the semi-custom engineering workstation bus incorporated in conventional testers. The present invention incorporates a compilation method for analyzing the event rate requirements of test programs. By determining at the time the test program is created how many TGs 170 need to be associated with each pin to achieve the required event rate for that pin, STAR-I minimizes the total number of TGs 170 included in the tester provided to a customer for specific test purposes, thereby minimizing the cost of the tester. This method restricts the topology by which the collection of DUT pin PEs is associated with tester TGBBs 150, because it would be most cost-effective to evenly distribute the high- event-rate pins across the set of TGBBs 150. The present invention is a SIMD computer and therefore enjoys an inherently lower implementation cost: A SIMD processing element is known to cost as little as 20% as much as its MIMD counterpart. I-Cached SIMD tester digital system 100 provides control over the TGs 170 at a moderate granularity via the global instruction broadcast network 140. The conventional test system allocates a fixed processing resource to each pin of the DUT; the present invention, by contrast, allocates a number of TGs to each DUT pin as dictated by the requirements of the test program. Although there have been described hereinabove various specific arrangements of the present invention for the purpose of illustrating the manner in which the invention may be used to advantage, it will be appreciated that the invention is not limited thereto. Accordingly, any and all modifications, variations or equivalent arrangements which may occur to those skilled in the art should be considered to be within the scope of the invention as defined in the annexed claims.

Claims: WHAT IS CLAIMED IS: 1. A Single Instruction-stream, Multiple Data-stream (SIMD) semiconductor chip tester apparatus for testing a Device Under Test (DUT) which has a plurality of electrical contact input and output pins to serve as input and output signal paths for coupling to tester circuitry, said semiconductor tester comprising: a plurality of pin electronics circuits corresponding to said plurality of pins of a DUT for operative connection thereto in one-to-one relationship; a like plurality of pin channels individually coupled to corresponding pin electronics circuits for communication with corresponding DUT pins; a digital system controller for generating a system clock and for storing and sequencing at least one test program; a plurality of timing generator modules responsive to said digital system controller, each module being a single semiconductor chip having an array of timing generators formed thereon for creating predetermined sequences of precisely timed drive events and strobe events for testing the DUT, said timing generators being operatively associatable with selected ones of said pin channels; and a plurality of multi-chip subsystems for controlling, coordinating, and memory- augmenting the timing generator modules, each timing generator module further comprising interface connections between said multi-chip subsystems and each of the timing generators in said module. 2. The tester apparatus of claim 1 further including a digital system which comprises a global instruction broadcast subsystem for distributing clock information and instructions from the system controller to said timing generator modules, a response subsystem for collecting and returning test status information from said timing generator modules to said system controller, and a DUT input/output subsystem incorporating an interface realized within the timing generator module, said interface providing connections between said timing generators and said pin channels. 3. The tester apparatus of claim 1 wherein each timing generator includes at least one event calculator circuit and at least one event converter circuit, wherein said event calculator circuit is realized using digital circuit design technique and wherein said event generator circuit comprises a dynamically reconfigurable programmable delay circuit which is realized using analog circuit design technique. 4. The tester apparatus of claim 3 wherein each of said timing generator event calculator circuits is a programmable processing element for increased flexibility and scalability of the timing generator. 5. The tester apparatus of claim 4 wherein said programmable processing element is capable of general-purpose calculations. 6. The tester apparatus of claim 5 wherein said programmable processing element contains an arithmetic logic unit, a register file having a read port and a write port, a plurality of function-unit-equivalent interfaces to said multi-chip subsystems, and a context management unit; whereby said processing element is capable of conditionally executing register-to-register operations and exchanges of register file data via said multi- chip subsystems. 7. The tester apparatus of claim 2 further including a communication subsystem interconnecting said timing generator modules to enable various pairs of timing generators within said digital system to exchange intermediate test information and other data. 8. The tester apparatus of claim 1 wherein said timing generator module comprises a local controller capable of decoding globally broadcast instructions into an instruction for re-broadcast within said timing generator module to each of said multi-chip subsystem interfaces and to each timing generator in said array. 9. The device of claim 2, further including a plurality of local external memory subsystems for providing the timing generators with memory capacity exceeding that which is realizable within a single-chip timing generator module, each local external memory subsystem comprising a plurality of memory modules having at least one memory chip, wherein each of said local external memory subsystems is associated with a unique one of said timing generator modules in a one-to-one association. 10. The tester apparatus of claim 2 wherein said digital system comprises a reconfigurable timing generator-to-pin channel allocator circuit, whereby a plurality of software-specified subsets of said timing generators is associated with said pin channels, wherein each of said software-specified subsets is in one-to-one association with a unique one of said pin channels in order to multiplex the events produced by each timing generator of each of said software-specified subsets onto said unique one of said pin channels and to distribute the observed pin value output of each of said pin channels to each member of each associated software-specified subset of timing generators. 11. The tester apparatus of claim 10 wherein said software-specified subsets of said timing generators are mutually disjoint. 12. The tester apparatus of claim 10 wherein said reconfigurable allocator circuit is adapted for run-time reallocation by allowing reconfiguration of said reconfigurable allocator circuit during the conducting of a functional test, wherein said reconfiguration is achieved in response to globally broadcast instructions. 13. The tester apparatus of claim 12 wherein said reconfigurable allocator circuit comprises a cross-bar switch capable of providing connecting paths between each of said timing generators and every one of said pin channels. 14. The tester apparatus of claim 10 wherein said reconfigurable allocator circuit comprises a first configuration providing a many-to-one mapping from each of said timing generators to each of said pin channels. 15. The tester apparatus of claim 14 wherein said reconfigurable allocator circuit further comprises a second configuration providing a many-to-many mapping, whereby each of said timing generators is associated with at least one of said pin channels and each of said pin channels is associated with a plurality of said timing generators. 16. The tester apparatus of claim 10 wherein said reconfigurable allocator circuit comprises a circuit topology providing selected proper subsets of the set of possible connections between said timing generators and said pin channels. 17. The tester apparatus of claim 10 wherein said reconfigurable allocator circuit comprises a cross-bar switch in one-to-one association with each of said timing generator modules, said cross-bars providing a plurality of pathways between every timing generator within said array and every one of said pin channels associated with said timing generator module. 18. The tester apparatus of claim 10 wherein said reconfigurable allocator circuit further comprises: a selectively enabled electrical path between each of said timing generators and a plurality of said pin channels, a memory-based configuration control circuit for enabling exactly one of the available paths from each of said timing generators, at least one time-domain edge multiplexer for combining control signals from the timing generators associated with each of said pin channels as determined by the contents of said control memory, and at least one analog de-multiplexer for distributing the measured pin value to the timing generators associated with each of said pin channels as determined by the contents of said control memory. 19. A timing generator module for use in a Single Instruction stream, Multiple Data-stream (SIMD) semiconductor tester, said timing generator module comprising: an array of generally programmable timing generators; at least one multi-clock generator having a multi-clock generator circuit responsive to applied tester system clock signals for generating a plurality of high-rate clock signals; and means for receiving and storing program instructions for controlling said timing generators; wherein the generated plurality of high-rate clock signals regulates the various subsystems within and connected to the timing generator module, each at its maximum rate of operation as determined by its physical implementation. 20. The timing generator module of claim 19 further including a cache element for instruction storage and a cache controller associated therewith, wherein said cache controller is responsive to globally broadcast instructions for the purposes of storing selected instructions in the cache element and for retrieving designated instruction sequences from the cache element for local re-broadcast within the timing generator module. 21. A multi-clock Single Instruction stream, Multiple Data-stream SIMD semiconductor tester digital system comprising: a global instruction broadcast network regulated by a system clock signal oscillating at a system clock rate; a multi-chip subsystem regulated by a second clock signal; and a timing generator module coupled to said global instruction broadcast subsystem and to said multi-chip subsystem, said timing generator module being implemented on a single chip and including: a first internal subsystem regulated by a third clock signal; a second internal subsystem regulated by a fourth clock signal; and a multi-clock generating circuit, responsive to said system clock signal, for generating a plurality of clock signals including said second, third, and fourth clock signals, wherein one of said third and fourth clock signals is a timing generator module clock signal oscillating at a timing generator module clock rate which is higher than said system clock rate, and wherein said second clock signal oscillates at a multi-chip subsystem clock rate which is higher than said system clock rate but no higher than said timing generator module clock rate.

Inventors: ROCKOFF TODD E, ROCKOFF, TODD, E.
Applicants: ROCKOFF TODD E, SIMD SOLUTIONS INC, ROCKOFF, TODD, E., SIMD SOLUTIONS, INC.
Application year: 1997
Main classification: H01L
IPC codes: G01R31