Static semiconductor memory device with precharging circuits having similar configuration of memory cells

Abstract: In a static semiconductor memory device including a plurality of word lines (wl 1 , WL 2 , ···), a plurality of bit line pairs (BL 1 , BL 1 , ···), at least one precharging line (PRL 1 , PRL 2 , ···), a plurality of static memory cells (C 11 , ···) connected to one of the word lines and one of the bit line pairs, and a plurality of precharging circuits (PR 11 ', ···), connected to the precharging line and one of the bit line pairs, thus charging the one of the bit line pairs, each of the precharging circuits has a similar configuration to one of the static memory cells.

Description: Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a static random access memory (SRAM) device. DESCRIPTION OF THE RELATED ART A prior art SRAM device includes a plurality of word lines, a plurality of bit line pairs, at least one precharging line, a plurality of static memory cells connected to one of the word lines and one of the bit line pairs, and a plurality of precharging circuits connected to the precharging line and one of the bit line pairs, thus charging the one of the bit line pairs. In this device, the density of elements in the memory cell area of the static memory cells is much higher than that in the precharging circuits. This degrades the operation characteristics of the device. For avoiding the degration of the operation characteristics, inactive dummy memory cells having the same configuration as the memory cells are inserted between the memory cell area and the precharging circuits. This will be explained later in detail. In the above-described prior art SRAM device, however, since the inactive dummy memory cells are necessary, the integration of the device is reduced. From US-A-4,972,377 a low-voltage low-power static RAM is known. This memory device has precharging circuits having a configuration similar to that of the memory cells. SUMMARY OF THE INVENTION It is an object of the present invention to enhance the integration of an SRAM device. According to the present invention, this object is achieved by a memory device as defined by claim 1. Since the precharging circuits also serve as inactive dummy memory cells, such inactive dummy memory cells can be omitted. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more clearly understood from the description as set forth below, in comparison with the prior art, with reference to the accompanying drawings, wherein: Fig. 1 is a layout diagram illustrating a first prior art SRAM device; Fig. 2 is a circuit diagram of one column of the device of Fig. 1; Fig. 3 is an equivalent circuit diagram of the memory cell (the dummy memory cell) of Fig. 2; Figs. 4A, 4B, 4C and 4D are plan views of the memory cell (the dummy memory cell) of Fig. 2; Fig. 5 is a layout diagram illustrating a second prior art SRAM device; Fig. 6 is 8 circuit diagram of one column of the device of Fig. 5; Fig. 7 is a layout diagram illustrating a first embodiment of the SRAM device according to the present invention; Fig. 8 is a circuit diagram of one column of the device of Fig. 7; Fig. 9 is an equivalent circuit diagram of the precharging circuit of Fig. 8; Figs. 10A, 10B and 10C are plan views of the precharging circuit of Fig. 8; Fig. 11 is a layout diagram illustrating a second embodiment of the SRAM device according to the present invention; and Fig. 12 is a circuit diagram of one column of the device of Fig. 11. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before the description of the preferred embodiments, prior art SRAM devices will be explained with reference to Figs. 1, 2, 3, 4A, 4B, 4C, 4D, 5 and 6. In Fig. 1, which is a layout diagram illustrating a first prior art SRAM device, reference numeral 1 designates a memory cell area, 2-1 and 2-2 designate dummy memory cell areas, and 3-1 and 3-2 designate precharging circuit areas. In Fig. 2, which is a circuit diagram of one column of the device of Fig. 1, the memory cell area 1 includes memory cells C 11 to C n1 each connected to one of word lines WL 1 to WL n and complementary bit lines BL 1 and BL 1 . Also, the dummy memory cell area 2-1 (2-2) includes one dummy memory cell DC 11 (DC 21 ) connected to one dummy word line DWL 1 (DWL 2 ) and the bit lines BL 1 and BL 1 . Further, the precharging circuit area 3-1 (3-2) includes one precharging circuit PR 11 (PR 21 ) connected to the bit lines BL 1 and BL 1 . The precharging circuit PR 1 (PR 2 ) is controlled by a precharging clock signal  PR . That is the bit lines BL 1 and BL 1 are precharged at V cc after each read or write operation, thus increasing the read or write operation speed. The memory cell such as C 11 is provided at each intersection between the word line WL 1 and the bit lines BL 1 and BL 1 . The memory cell C 11 is constructed by a flip-flop formed by two cross-coupled inverters and two transfer transistors Q t1 and Q t2 between nodes N 1 and N 2 of the flip-flop and the bit lines BL 1 and BL 1 . The transfer transistors Q t1 and Q t2 are controlled by the voltage at the word line WL 1 . Each of the inverters is formed by a load resistor R 1 (R 2 ) and a drive transistor Q d1 (Q d2 ) between a power supply line denoted by V cc and a ground line denoted by GND. The node N 1 is connected to a gate of the drive transistor Q d2 , so that the drive transistor Q d2 is driven by the voltage at the node N 1 . Also, the node N 2 is connected to a gate of the drive transistor Q d1 , so that the drive transistor Q d1 is driven by the voltage at the node N 2 . The dummy memory cell such as DC 21 has the same configuration as the memory cell C 11 of the memory cell area 1. However, note that the dummy word line DWL 2 is grounded, so that the dummy memory cell DC 2 is completely inactive. The precharging circuit such as PR 21 is constructed by a transistor Q PR1 connected between the power supply line V cc and the bit line BL 1 and a transistor Q PR2 connected between the power supply line V cc and the bit line BL 1 . The density of elements in the memory cell area 1 is much higher than that in the precharging circuit areas 3-1 and 3-2. This degrades the operation characteristics of the device. For avoiding the degration of the operation characteristics, the inactive dummy memory cells such as DC 11 and DC 21 having the same configuration as the memory cells are inserted between the memory cell area 1 and the precharging circuit areas 3-1 and 3-2. The memory cell such as C 11 and the dummy memory cell such as DC 21 are actually symmerical with respect to a center location thereof, so that the memory cells and the dummy memory cells are balanced. As a result, data retention characteristics and soft error resistance characteristics can be improved. For this purpose, the circuit diagram of the memory cell C 11 (the dummy memory cell DC 21 ) is actually as illustrated in Fig. 3, where the power supply line V cc is replaced by two power supply lines V cc1 and V cc2 whose voltages are the same as each other; the word line WL 1 (the dummy word line DWL 1 ) is replaced by two word lines WL 1 and WL 1 '(DWL 1 and DWL 1 ') whose voltages are the same as each other; and the ground line GND is replaced by two ground lines GND 1 and GND 2 whose voltages are the same as each other. An example of the memory cell C 11 (the dummy memory cell DC 21 ) of Fig. 2 is illustrated in Figs. 4A, 4B, 4C and 4D. First, referring to Fig. 4A, a P-type monocrystalline silicon substrate (not shown) is thermally oxidized to form a field silicon oxide layer F by using a local oxidation of silicon (LOCOS) process. Thereafter, a gate silicon oxide layer GOX is formed by thermally oxidizing the substrate. Then, gate electrodes of the transistors Q t1 , Q t2 , Q d1 , and Q d2 are formed. In this case, the gate electrodes of the transistors Q t1 and Q t2 also serve as the word lines WL 1 and WL 1 ' (the dummy word lines DWL 1 and DWL 1 '), respectively. Then, N-type impurity ions are implanted into the substrate using the gate electrodes as a mask to form N-type impurity diffusion regions as indicated by shaded portions. In Fig. 4A, the field silicon oxide layer F, the gate electrodes and the N-type impurity diffusion regions are symmetrical with respect to the center location thereof as indicated by Z. Next, referring to Fig. 4B, a metal (tungsten or the like) layer is formed on an insulating layer (not shown), and is patterned to form the ground lines GND 1 and GND 2 . In this case, the ground lines GND 1 and GND 2 are connected via contact holes CONT 1 and CONT 2 to sources of the drive transistors Q d1 and Q d2 , respectively. In Fig. 4B, the ground lines GND 1 , and GND 2 are symmetrical with respect to the center location thereof as indicated by Z. Next, referring to Fig. 4C, a metal (tungsten or the like) layer is formed on an insulating layer (not shown), and a patterned to form the power supply lines V cc1 , and V cc2 . In this case, the ground lines V cc1 and V cc2 are connected via contact holes CONT 3 and CONT 4 to the nodes N 1 and N 2 , respectively. Also, the load resistors R 1 (R 2 ) are formed between the power supply lines V cc1 (V cc2 ) and the contact holes CONT 3 (CONT 4 ). In Fig. 4C, the power supply lines V cc1 and V cc2 are symmetrical with respect to the center location thereof as indicated by Z. Finally, referring to Fig. 4D, an aluminum layer (not shown) is formed on an insulating layer (not shown) and is patterned to form the bit lines BL 1 and BL 1 (not shown). In this case, the bit lines BL 1 and BL 1 are connected via contact holes CONT 5 and CONT 6 to the drains of the transfer transistors Q t1 and Q t2 , respectively. In Fig. 4D, the bit lines BL 1 and BL 1 are symmetrical with respect to the center location thereof as indicated by Z. In the first prior art SRAM device as illustrated in Figs. 1, 2, 3, 4A, 4B, 4C and 4D, however, since the length L 1 of the precharging circuit area 3-1 (3-2) and the dummy memory cell area 2-1 (2-2) is large, for example, about twenty times the longitudinal length of one memory cell, the integration is reduced, Fig. 5 is a layout diagram illustrating a second prior art SRAM device, and Fig. 6 is a circuit diagram of one column of the device of Fig. 5. In Figs. 5 and 6, in order to homogenize precharging currents in the device of Fig. 1, three precharging circuit areas 3-1, 3-2 and 3-3 are provided. In this case, the memory cell area 1 of Fig. 1 is divided into two memory cell areas 1-1 and 1-2. Therefore, dummy memory cell areas 2-1, 2-2, 2-3 and 2-4 are required between the memory cell areas 1-1 and 1-2 and the precharging circuit areas 3-1, 3-2, 3-3 and 3-4. In the second prior art SRAM device as illustrated in Figs. 5 and 6, however, the length L 1 of the precharging circuit area 3-1 (3-3) and the dummy memory cell area 2-1 (2-4) is large, for example, about twenty times the longitudinal length of one memory cell, and also, the length L 2 of the precharging circuit 3-2 and the dummy memory areas 2-2 and 2-3 is larger than the length L 1 . Therefore, since 2L 1 + L 2 >2L 1 (first prior art), the integration is further reduced. In Fig. 7, which is a layout diagram illustrating a first embodiment of the SRAM device according to the present invention, the dummy memory cell areas 2-1 and 2-2 of Fig. 1 are deleted, and the precharging circuit areas 3-1 and 3-2 are modified to precharging circuit areas 3-1' and 3-2', respectively. In Fig. 8, which is a circuit diagram of one column of the device of Fig. 7, the precharging circuit area 3-1' (3-2') includes one precharging circuit PR 11 ' (PR 21 ') connected to the bit lines BL 1 and BL 1 . The precharging circuit PR 1 ' (PR 2 ') is connected to a precharging line PRL 1 (PRL 2 ) which controlled by a precharging clock signal  PR . The precharging line PRL 1 (PRL 2 ) corresponds to the word line such as WL 1 . The precharging circuit such as PR 21 ' has a similar configuration to the memory cell C 11 . That is, the precharging circit such as PR 21 ', is provided at each intersection between the word line WL 1 and the bit lines BL 1 and BL 1 . The precharging circuit PR 2 ' is constructed by a cross-coupled balancer and two transfer transistors Q t1 ' and Q t2 ' between nodes N 1 ' and N 2 ' of the balancer and the bit lines BL 1 and BL 1 . The transfer transistors Q t1 ' and Q t2 ' are controlled by the voltage at the precharging line PRL 2 . Each element of the balancer is formed by a load resistor R 1 ' (R 2 ') and a drive transistor Q d1 ' (Q d2 ') connected to the power supply line V cc . The node N 1 ' is connected to a gate of the drive transistor Q d2 ', so that the drive transistor Q d2 ' is driven by the voltage at the node N 1 '. Also, the node N 2 ' is connected to a gate of the drive transistor Q d1 ', so that the drive transistor Q d1 ' is driven by the voltage at the node N 2 '. Thus, since the precharging circuit PR 11 ' (PR 21 ') has a similar configuration to the memory cell such as C 11 , the precharging circuit PR 11 ', (PR 21 ') can also serve as the dummy memory cell DC 11 (DC 21 ) of Fig. 2. The precharging circuit such as, PR 21 ' is actually symmetrical with respect to a center location thereof, so that the precharging circuit PR 21 ' is balanced. For this purpose, the circuit diagram of the precharging circuit PR 21 ' is actually as illustrated in Fig. 9, where the power supply line V cc is replaced by two power supply lines V cc1 and V cc2 whose voltages are the same as each other; the precharging line PRL 2 is replaced by two word lines PRL 2 and PRL 2 ' whose voltages are the same as each other; and the ground line GND is replaced by two ground lines GND 1 and GND 2 whose voltages are the same as each other. An example of the precharging circuit PR 2 ' is illustrated in Figs. 10A, 10B, 10C and 10D. First, referring to Fig. 10A, a P-type monocrystalline silicon substrate (not shown) is thermally oxidized to form a field silicon oxide layer F by using a LOCOS process. Thereafter, a gate silicon oxide layer GOX is formed by thermally oxidizing the substrate. Then, gate electrodes of the transistors Q t1 ', Q t2 ', Q d1 ' and Q d2 ' are formed. In this case, the gate electrodes of the transistors Q t1 ' and Q t2 ' also serve as the precharging lines PRL 2 and PRL 2 ', respectively. Then, N-type impurity ions are implanted into the substrate using the gate electrodes as a mask to form N-type impurity diffusion regions as indicated by shaded portions. In Fig. 10A, the field silicon oxide layer F, the gate electrodes and the N-type impurity diffusion regions are also symmetrical with respect to the center location thereof as indicated by Z. Next, referring to Fig. 10B, a metal (tungsten or the like) layer is formed on an insulating layer (not shown), and is patterned to form the power supply lines V cc1 , and V cc2 . In this case, the power supply line V cc1 is connected via contact holes CONT 2 ' and CONT 3 ' to a source of the drive transistor Q d2 ' and the node N 1 '. Also, the power supply line V cc2 is connected via contact holes CONT 1 ' and CONT 4 ' to a source of the drive transistor Q d1 ' and the node N 2 '. Further, the load resistors R 1 (R 2 ) are formed between the power supply lines V cc1 (V cc2 ) and the contact holes CONT 3 ' (CONT 4 '). In Fig. 10B, the power supply lines V cc1 and V cc2 are also symmetrical with respect to the center location thereof as indicated by Z. Finally, referring to Fig. 10C, an aluminum layer (not shown) is formed on an insulating layer (not shown) and is patterned to form the bit lines BL 1 and BL 1 (not shown). In this case, the bit lines BL 1 and BL 1 are connected via contact holes CONT 5 and CONT 6 to the drains of the transfer transistors Q t1 ' and Q t2 ', respectively. In Fig. 4C, the bit lines BL 1 and BL 1 are also symmetrical with respect the center location thereof as indicated by Z. The precharging circuit PR 21 ' as illustrated in Figs. 10A, 10B and 10C can be manufactured simultaneously with the memory cell C 11 as illustrated in Figs. 4A, 4B, 4C and 4D. In this case, ions are implanted into the power supply lines V cc1 and V cc2 only within the precharging circuit areas 3-1' and 3-2', to reduce the resistance values of the load resistors R 1 ' and R 2 ', thus increasing the current supply ability of the precharging circuits to the bit lines such as BL 1 and BL 1 . Also, the amount of ions implanted into channel portions of the transistors Q t1 ', Q t2 ', Q d1 ' and Q d2 ' of the precharging circuits is reduced as compared with the amount of ions implanted into channel portions of the transistors Q t1 , Q t2 , Q d1 and Q d2 of the memory cells. As a result, the threshold voltages of the transistors Q t1' , Q t2' , Q d1' and Q d2' of the precharging circuits are reduced as compared with those of the transistors Q t1 , Q t2 , Q d1 and Q d2 of the memory cells. This also increases the current supply ability of the precharging circuits to the bit lines such as BL 1 and BL 1 . In the first embodiment as illustrated in Figs. 7, 8, 9, 10A, 10B and 10C, since the length L 1 ' of the precharging circuit area 3-1' (3-2') is small, for example, about ten times as the longitudinal length of one memory cell, the integration can be enhanced. The cross-coupled balancer circuit configuration of the precharging circuit such as PR 21 enhances the charging speed of the bit lines BL 1 and BL 1 . For example, assume that the voltages at the bit lines BL 1 and BL 1 are given by V cc -α and V cc -β, respectively. If (V cc -α) - (V cc -β) = β - α > V th where V th is a threshold voltage of the transistors Q d1 ' and Q d2 ', the transistor Q d2 ' is turned ON, so that the bit line BL 1 is charged by V cc . On the other hand, if (V cc - β) - (V cc -α) = α - β>V th , the transistor Q d1 ' is turned ON, so that the bit line BL 1 is charged by V cc . Thus, transistors Q d1 ' and Q d2 ' are alternately turned ON, so that the voltages at the bit lines BL 1 and BL 1 are equalized. Fig. 11 is a layout diagram illustrating a second embodiment of the SRAM device according to the present invention, and Fig. 12 is a circuit diagram of one column of the device of Fig. 11. In Figs. 11 and 12, in order to homogenize precharging currents in the device of Fig. 7, three precharging circuit areas 3-1', 3-2' and 3-3' are provided. In this case, the memroy cell area 1 of Fig. 7 is divided into two memory cell areas 1-1 and 1-2. Also, the dummy memory cell areas 2-1, 2-2, 2-3 and 2-4 of Figs. 5 and 6 are deleted. Since the precharging circuit areas 3-1', 3-2' and 3-3' serve as dummy memory cell areas. In the SRAM device as illustrated in Figs. 11 and 12, the length L 1 ' of the precharging circuit area 3-1' (3-2', 3-3') is small, for example, about ten times as the longitudinal length of one memory cell. Therefore, since 3L 1 ' < 2L 1 + L 2 (second prior art), the integration is enhanced. In the present invention, note that it is possible to introduce only one precharging circuit area as illustrated in Figs. 7 and 11 into an SRAM device. Also, it is possible to introduce four or more precharging circuit areas as illustrated in Figs. 7 and 11 into an SRAM device. As explained hereinabove, according to the present invention, since precharging circuits also serve as dummy memory cells, the dummy memory cells can be omitted, thus enhancing the integration.

Claims: A static semiconductor memory device comprising: a plurality of word lines (Wl 1 , WL 2 , ...); a plurality of bit line pairs (BL 1 , BL 1 ,...); at least one precharging line (PRL 1 , PRL 2 , ...); a plurality of static memory cells (C 11 , ...) connected to one of said word lines and one of said bit line pairs; and a plurality of precharging circuits (PR 11 ', ...), connected to said precharging line and one of said bit line pairs, for charging said one of said bit line pairs, each of said precharging circuits having a similar configuration to one of said static memory cells, first and second power supply lines (V cc , GND), each of said static memory cells comprising; first and second nodes (N 1 , N 2 ); a first transfer transistor (Q t1 ) connected between a first bit line (BL 1 ) of one of said bit line pairs and said first node, said first transfer transistor being controlled by a voltage at one of said word lines; a second transfer transistor (Q t2 ) connected between a second bit line ( BL 1 ) of said one of said bit line pairs and said second node, said second transfer transistor being controlled by the voltage at said one of said word lines; a first load resistor (R 1 ) connected between said first power supply line and said first node; a second load resistor (R 2 ) connected between said first power supply line and said second node; a first drive transistor (Q d1 ) connected between said first node and said second power supply line; and a second drive transistor (Q d2 ) connected between said second node and said second power supply line, each of said precharging circuits comprising: third and fourth nodes (N 1 ', N 2 '); a third transfer transistor (Q t1 ') connected between said first bit line and said third node, said third transfer transistor being controlled by a voltage at said precharging line; a fourth transfer transistor (Q t2 ') connected between said second bit line and said fourth node, said fourth transfer transistor being controlled by the voltage at said precharging line; a third load resistor (R 1 ') connected between said first power supply line and said third node; a fourth load resistor (R 2 ') connected between said first power supply line and said fourth node; a third drive transistor (Q d1 ') connected between said third node and said first power supply line; and a fourth drive transistor (Q d2 ') connected between said fourth node and said first power supply line. The device as set forth in claim 1, wherein each of said static memory cells is symmetrical with respect to a center location thereof, each of said precharging circuits being symmetrical with respect to a center location thereof. The device as set forth in claim 1, wherein each of said precharging circuits is arranged adjacent to and in the vicinity of a memory cell array comprising said static memory cells. The device as set forth in claim 1, wherein said static memory cells are grouped into a plurality of memory cell arrays (1-1, 1-2), said precharging circuits being arranged between gaps separating said memory cell arrays.

Inventors: YOSHINORI UENO, YOSHINORI, UENO, Yoshinori, Ueno, NEX IC Microcomputer Systems Ltd.
Applicants: NEC ELECTRONICS CORP, NIPPON ELECTRIC CO, NEC CORPORATION, NEC ELECTRONICS CORPORATION
Application year: 1997
Main classification: G11C7
IPC codes: H01L21, G11C11, G11C7, H01L27