Control of the output power of a dc-dc converter upon varying the switching frequency

Abstract: The power output of a static DC_DC converter employing a current mode PWM controller is controlled upon the varying of the switching frequency, by detecting the sawtooth signal produced by the local oscillator generating a DC signal with amplitude inversely proportional to the frequency and by alternatively clamping the output voltage of the error amplifier of the PWM controller at a voltage proportional to the amplitude of said DC signal or by offsetting the signal present on the currents sensing resistor by a voltage corresponding to the difference between a constant voltage and said DC signal.

Description: FIELD OF APPLICATION OF THE INVENTION The present invention relates to a current mode PWM control circuit (controller) usable to realize a static DC_DC converter and capable of keeping to a substantially constant level the output power, independently from the switching frequency. DC_DC static converters are widely used in power supplies, actuating systems, displays, signal processing systems and the like. Static DC_DC converters are based upon well known basic circuit topologies or configurations, often used alternatively to one another, as for example the so called "flyback" topology, wherein the primary winding of a transformer is driven by a power switch, controlled by a PWM system, switching at a frequency established, for example, by a saw-tooth local oscillator, whose natural frequency may be fixed upon connecting an external RC network to the integrated circuit of the controller. The switching frequency may be modified in respect to its design nominal value or otherwise set by a system's clock signal or any equivalent synchronizing signal. In the case of a so-called "boost" topology it is an energy storing inductor that is similarly driven. As well known, static converters may function either in a so-called discontinuous current mode (DCM) or in a continuous current mode (CCM). In the former (DCM) mode each cycle begins with the current in the inductor or primary winding of the transformer starting from zero, because the inductance has been allowed to discharge completely during the preceding phase. By contrast, in a CCM mode, the current through the primary winding or the inductor at the beginning of each cycle starts from a value different from zero. The DCM mode is characterized by a regime of triangular shaped currents flowing through the power switch, while the CCM mode is characterized by trapezoidal shaped currents flowing through the power switch. It is important that the respective current-mode control circuits be effective in controlling the output current level so to prevent damages in case of overloads. The generally followed approach consists of using the signal present on a dedicated sensing resistor connected in series to the power switch to activate a current limiting loop, when a certain voltage threshold is exceeded on the sensing resistor. This type of control is commonly referred to as of the peak current type, being also known that in these peak current control systems, the output power of the converter increases as the switching frequency increases. In a DCM mode, the increase of the power that may be output is substantially proportional to the switching frequency, while in a CCM mode such an increase of the output power, function of the switching frequency, is less marked (nonlinear relationship). REVIEW OF THE PRIOR ART Controllers have been marketed for a long time as they constitute an integral part of the majority of current mode PWM system devices and frequently they include also the power switching device. These integrated devices are, for obvious reasons multipurpose, hat is designed for use in different applications, allowing the implementation of supplies and converters of different topology by simply connecting the device in an external circuit which includes components connectable to the respective pins. Often, these integrated devices are produced within a standard package, such as for example the DIP16 and SO16W, both having 16 pins. Amongst these commercial devices we may cite: L4990 manufactured by SGS-THOMSON MICROELECTRONICS; UC3842A/B manufactured by SGS-THOMSON MICROELECTRONICS, TEXAS INSTRUMENTS, MOTOROLA, SAMSUNG, UNITRODE et al.; LT1241 manufactured by LINEAR TECHNOLOGY; UC3801 and UC3828 manufactured by UNITRODE. "Datasheet" of all these devices including their functional schemes and characteristics are readily available. A typical commercial product is the L4990 manufactured by SGS-THOMSON MICROELECTRONICS, a high level block diagram of which is shown in Figure 1. GB-A-2 298 532 discloses an example of a power-controlled switch mode power supply using PWM and having a variable operating frequency. In many applications, the switching frequency may vary within a wide range of frequencies that may be either programmable or synchronized by means of dock signals or pulses that may be generated by deflecting circuits, as in the case of CRT monitors. Often the dependency of the output power from the switching frequency may not be tolerated especially in applications destined to function in a wide range of switching frequencies. In these particularly critical applications use has been made of dedicated circuits capable of implementing an output power compensation so to prevent it to excessively increase upon an increase of the switching frequency. For example, in a CRT monitor the synchronizing pulses derived from the deflection circuit are integrated by an R-C lowpass filter, to generate a DC voltage proportional to the frequency. This DC signal is applied to the pin of the integrated, controller which senses the current crossing the transformers primary winding of a flyback converter. In this way, the controller is deliberately "cheated" to "sense" a current that is in fact higher than the real one as the frequency increases. In this way the maximum current limit is reached with a lower peak current. Nevertheless, these known solutions have drawbacks: a) the amplitude and duration of the synchronizing pulses must be known and constant and the compensation circuit must be necessarily trimmed according to these parameters; b) the compensation circuit is not integrable in the controller's functional circuit because of the need to realize a compensation circuit ad hoc , bearing in mind the characteristics of the specific application; c) the correction effected by the circuit is essentially linear while the required correction may not be so, ideally; d) the design and realization of the compensation circuit imply a non negligeable cost. SCOPE AND SUMMARY OF THE INVENTION The main aim of the present invention is that of providing a method and relative compensation circuit capable of assuring a relatively constant power output by the converter with the varying of the switching frequency, simpler to realize and independently of the characteristics of an eventual synchronizing signal that regulates the switching frequency. A further aim of the invention is to implement these important functions in a integrated multipurpose controller. The invention is defined in the appended claims. These and other advantages, which will become more evident through the ensuing description, are attained through the method of the invention for controlling the power output by a converter that comprises the following steps: a) detecting the signal produced by the local oscillator generating a DC signal whose amplitude is inversely proportional to the frequency; b) alternatively, clamping the output power of the error amplifier of the controller to a voltage proportional to the amplitude of such a DC signal or offsetting the signal existing on the current sensing resistor by a voltage difference between a constant voltage and said DC signal and by employing the relative implementing circuit. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a high level block diagram of a typical PWM controller. Figure 2 is the functional scheme of a current mode control circuit for a flyback DC-DC converter. Figure 3 is a partial scheme showing the synchronization of the oscillating frequency of the sawtooth local oscillator of the device of Figure 1. Figures 4a, 4b, 4c and 4d show the wave forms of the signal generated by the sawtooth local oscillator with and without synchronization and the signal existing on the output pin of the device shown in Figure 1. Figure 5 illustrates the behavior of an equivalent input voltage. Figure 6 shows the relationship between the input power and the input equivalent voltage. Figure 7 shows the trend of the peak current on the flyback primary winding of the transformer in function of the input power. Figure 8 is an electric scheme that shows an embodiment of the compensation circuit of the invention integrated in a controller as that shown in Figure 1. Figure 9 shows the trend of the peak voltage of the signal produced by the sawtooth local oscillator in function of the frequency of the synchronizing signal. Figures 10a, 10b, 10c, 10d, 10e and 10f show the correction performed by the compensating circuit of the invention for different values of the K-parameter. Figure 11 show the comparison between the theoretical and real trend of the correction law of the circuit of the invention following an optimization of the circuit parameters. Figure 12 is a partial electric scheme depicting an alternative embodiment of the circuit of the invention externally to the integrated controller device. DESCRIPTION OF SOME EMBODIMENTS OF THE INVENTION. For a better understanding of the problems associated with the implementation of an output power control in a DC-DC converter, the behavior of a flyback converter, whose functional scheme is shown in Figure 2, may be analyzed. By assuming the use of a state-of-the-art integrated controller, such as the device L4990 of Figure 1, the functional scheme of the sawtooth local oscillator, synchronized by a synchronizing signal applied to the relative pin (sync), is shown in Figure 3. The relative sawtooth waveforms produced by the oscillator, with and without the synchronism signal (sync), as well as the signal produced on the output pin 10 of the integrated device of figure 1, are respectively shown in Figures 4a, 4b, 4c and 4d. Additional basic functions of an integrated PWM controller as the L4990 device, may be recognized, for example, by reading the Application Note: "SMPS with L4990 for MULTISYNC MONITORS", by C.W. Park and G. Gattavari, SGS-THOMSON MICROELECTRONICS, AN89 1/1196. The meaning of the symbols used in the following analysis is indicated in the following Table 1. SYMBOL DESCRIPTION Pin Input power of the converter Vin DC input voltage of the converter Vout DC output voltage of the converter f Switching frequency T Switching period = 1/ f ) Lp Transformer's primary winding inductance n Transformer's turns ratio (primary/secondary) TON Duration of the current flow through the primary winding TFW Duration of the recirculation current through the secondary winding lpkp Primary winding peak current (in general) lpkp(DCM) DCM primary winding peak current lpkp(CCM) CCM primary winding peak current Dlp Primary winding current ripple VE Equivalent input voltage ZE Primary winding impedance PinT Input power at the transition DCM « CCM lpkpT Primary winding peak current at the transition DCM « CCM VET Equivalent input voltage at the transition DCM « CCM fT Switching frequency at the transition DCM « CCM Vcs Peak voltage on the current sense (pin 13, ISEN) of L4990 VCOMP Output voltage of the E/A of L4990 (pin 6, COMP) Vf Direct voltage drop of a diode Rs Sensing resistance on which Vcs is sensed Vo External introduced offset on the current sense (pin 13, ISEN) of L4990 VCTL Voltage on the voltage divider (x3) of the PWM comparator of L4990 VCST Peak voltage on current sense at the transition DCM « CCM fsync External frequency that synchronizes the oscillator fosc Oscillator frequency without synchronism k Ratio between the transition frequency DCMCCM and the natural frequency of the oscillator Vpeak Peak voltage of the oscillator sawtooth Vclamp Clamp voltage VCTL required to obtain a constant Pin upon varying the frequency. Plim Maximum input power obtained with the "Constant Power" function By analyzing the functioning of a flyback converter as shown in Figure 2 and operating in DCM, the peak current in the primary winding is related to the input power by the expression: I pkp ( DCM ) = 2• P in L p • f and the times intervals of conduction in the primary winding, and of recirculation in the secondary winding are respectively: T ON = L p • I pkp ( DCM ) V in T FW = L p • I pkp ( DCM ) n • V out The sum of which is lower than the switching period T . The transition condition between CCM and DCM (and viceversa) is obviously: T ON + T FW = T= 1 f and, by confirming the equations (2) and (3) into (4), we obtain the power PinT , that is the maximum power that the system may deliver in DCM (in other words, the minimum power that the system may deliver in CCM): P inT = 1 2• f • L p • V in 1+ V in n • V out Equation (5) may be rewritten as: P inT = V 2 E 2• Z E by introducing the "equivalent input voltage", VE, and the "primary impedance", ZE , we have: V E = V in 1+ V in n • V out ; Z E = 1 f • L p the shape of VE is function of Vin is shown in Figure 5. The peak primary current, at the transition, becomes: I pkpT = 2• P inT f • L p = 1 f • L p • V in 1+ V in n • V out = V E Z E Equation (5), or similarly equation (6), shows that the transition power for a given system (or for a known values of f and Lp ) depends from the input voltage. Let us then consider the range of values PinT ( PinT min- PinT max) corresponding to that of VE ( VE min- VE max) which, in turn, is tied to the range of input voltage Vin. This relationship is diagrammatically shown in Figure 6. Parallel it is possible to define a transition voltage VET at which, for a given power Pin , the system switches from DCM to CCM and viceversa: V ET = 2• Z E • P in Then, for VE > VET the system will operate in a DCM mode and in a CCM mode for VE < VET. Obviously, it will be VE min< VET < VE max if PinT min < Pin < PinT max. Table 2 shows the possible ranges of VE for typical conditions of the mains voltage and the correspondent values of the ratio PinT max/ PinT min, of significance for the considerations that will be made below. Again, for an assigned Pin power and for a given input voltage (to which corresponds a certain voltage VE ), in a system wherein the operating frequency varies, it is possible to define the frequency that verifies the transition: f T = V E 2• L p • P in We thus have a DCM when f < fT and a CCM when f> fT . Obviously, if fT is outside the variation range of the operating frequency, for that Pin and that VE there will be always only one functioning mode. In CCM, equation (4) is always verified but equations (2) and (3) must be rewritten as follows: T ON = L p •Δ I p V in T FW = T - T ON = L p •Δ I p n • V out The peak current is no longer univocally correlated to the input power but depends also on the input voltage: I pkp ( CCM ) = P in V in • T T ON + 1 2 •Δ I p This relationship may be written as: I pkp ( CCM ) = P in V E + V E 2• Z E It may be demonstrated, by eliminating the derivative in equation (14) that, for a given power Pin > PinTmin the peak current is minimum when VE = VET and therefore will assume the maximum value when VE = VE min (that is for Vin = Vin min). Figure 7 summarizes the behavior of Ipkp including both functioning modes. On the basis of the preceding considerations and for simplicity, we shall classify the flyback converters in terms on their Pin max according to the following criterion: Pin max < PinT min ( VET < VE min): DCM systems; PinT min < Pin max < PinT min ( VE min < VET < VE max): MCM systems (Mixed Conduction Mode); Pin max > PinT max ( VET > VE max): CCM systems. According to the functioning mode of all PWM controllers that implement a peak current control, like for example the L4990, the peak voltage on the ISEN pin, Vcs, is related to the control voltage (that is, the output voltage of the error amplifier E/A), by the following equation: V COMP = 3• V cs + 2• V f In turn, the peak voltage on the ISEN pin depends on the peak current (irrespectively of the operating mode) according to the relationship: V cs = R s • I pkp + V o wherein Vo is an offset voltage externally imposed on the ISEN pin, for instance a "slope compensation" or any other type of correction voltage. According to a fundamental aspect of this invention, the power that may be output by a DC-DC converter that employs a current mode PWM controller, can be controlled in a manner that its maximum value is substantially constant as the frequency varies, regardless of the form, amplitude and duration of the synchronizing pulses, by impressing on a pin (referred to as ISEN) dedicated to the connection of an external resistor or sensing the current, an offset voltage that increases with the frequency or, alternatively, by clamping the output voltage of the error amplifier of the controller to a voltage that decreases with the frequency. While the compensation circuit of the invention may be realizable externally of the controller, a particularly advantageous embodiment of the invention consists in integrating the compensation circuit capable of implementing such important function, within the controller device. In several commercial devices there exist one or more unused pins that can be advantageously used to integrate the circuit of the invention without in any way altering the existing controller layout. An example of this is the device L4990 wherein pin 16 is not used and can then be used to implement the control function of the output power according to the method of the invention. If pins are not available, a simple circuital modification may be sufficient to integrate the circuit of the invention, in a way as to be either enabled or disabled, or eventually another function, unused in the particular application can be sacrified to permit the enabling of the power control function of the invention. A particularly preferred embodiment of the invention requiring a simpler circuit than that needed to inject an offset voltage on the current sensing node, consists in clamping the output voltage of the controller's error amplifier to a voltage level that decreases with the frequency. This preferred embodiment is shown in Figure 8, by highlighting with a thicker line the compensation circuit of the invention. Of course, the same circuit may also be realized externally to the integrated controller. The only inaccessible node being in this case represented by the emitter node of the clamp transistor Q1. However, such a connection may be produced externally of the integrated device by simply connecting two external diodes between the pin 6 (Comp) of the integrated device and the emitter of the external transistor Q1. ANALYSIS OF THE OPERATION OF THE COMPENSATION CIRCUIT OF THE INVENTION The synchronization of the oscillator with an external signal of frequency fsync∈(fmin,fmax) implies in the first place that such an external signal be set with a frequency fosc slightly lower (typically of about 10-20%) than fmin and secondly that the amplitude of the generated sawtooth diminishes as fsync increases. Such a decrease of amplitude is due to the reduction of Vpeak alone, since the bottom value remains unchanged. By neglecting the sawtooth fall time, the following expression holds true: whose characteristic is depicted in Figure 9. This voltage, obtained through a peak detector circuit (basically a diode and a capacitor, properly buffered to avoid influencing the oscillator), is independent from the parameters of the synchronizing pulses and may be used as the clamp voltage level for the E/A output, that is, of the VCLT voltage in the considered case of an integrated embodiment. The available pin 16 is in this case used to connect the external capacitor of the peak detector circuit, since a capacitance in the order of 1 uF non realizable in an integrated form is required. Moreover the use of an external capacitor renders possible to trim the circuit. Two conditions must be fulfilled by the circuit: 1) the correction performed should be close to the ideal one; 2) the compensation circuit should not interfere with the functioning of the converter when the controller's oscillator is not synchronized, that is the clamping should be able to disabled in the case of applications that do not require a control of the output peak power. The peak voltage level of the non-synchronized oscillator is, in the example considered, 3V, the second condition, as shown by equations (17) and (18), may be easily fulfilled. The first condition remains to be verified. From equations (1), (14), (16), where Vo is set to 0, and (17), the clamp voltage required to keep the input power constant to a value Pinmax may be derived to be given by: where fT , from equation (10), is given by: f T = V 2 E 2• L p • P in max Equation (40) represents the ideal correction law. The equation shows its independence from VE and therefore from the input voltage when fsync < fT , that is in DCM operation whereas it is dependent from VE when fsync > fT , that is in CCM operation. fT , that is the frequency at which the ideal correction law changes its expression, is also dependent on VE. By contrast, the theoretical law given by equation (39) has a sole expression and depends only from the ratio foscl fsync. In order to compare (39) with the (40)s and evaluate the relative departure from one another, it may be more convenient to rewrite (40) in a more convenient form. In the first place, we replace (41), explicited in respect to VE, in the second one of the equations (40), thus obtaining: Let us assume to select the primary winding inductance Lp to be equal to: L p = V 2 E min 2• f T • P in max In this way, it is understood that by transition frequency fT we mean the minimum, that is the one that is obtained when VE = Ve min. By introducing a parameter k , represented by a positive value, such that: f T = k • f osc certain important considerations may be simplified as follows. By substituting (43) and (44), in both equations (42) the following expressions are obtained: Since the ratio Fsync / fosc is always greater than 1, the first of the two equations (45) applies if k>1. The resistance Rs is chosen to fulfill condition 2), in other words when fsync / fosc =1, Vclamp = 3V. This is expressed in the following equations. Equation (39) will be now compared with (45), taking into account equation (46), calculated for different values of k. From equation (44) we deduce that the smaller is k the more the system functions in CCM, by contrast, greater values of k indicate a shift towards a DCM. From a practical point of view, the top value of k is limited by fmax / fosc (indeed, from this value onwards the functioning is always discontinuous and thereby the ideal correction law would not change any more). As far as the lower value of k is concerned, it would not make much sense to consider extremely low values since for k-->0 (that is, moving more and more towards a CCM) the primary current tends to become rectangular and therefore Pinmax tends to be come independent from the frequency. It has been found that 0.1 is an appropriate value, whereas for the ratio fmax/fosc a practical value may be assumed equal to 5. The diagrams shown in Figures 10a, 10b,...., 10f, compare the behavior of the equations (39) and (45) as well as the ratios between the maximum power effectively obtained Plim and the desired one Pinmax , with and without the correction (39), for different values of the parameter k. From examining the characteristic curves of Figures 10a to 10f, it may be observed that when the system is "very" CCM (k ≤ 0.2) the correction is marked limiting the high frequency power output well below the desired value. However, under these conditions, even without correction, the increment of power with the frequency is rather contained (< 15%) and thereby these systems do not require any correction in practice. For systems "moderately" CCM (k>>0.5) the most critical situation in encountered: the system does require correction though this is still too heavy (>> 30%). A more acceptable behavior is observed for k>>1: the correction performs a reduction or less than 20% and a power slightly higher than desired at low frequency may be tolerated in order to obtain substantially the required one at high frequency. As the system gets and more close to DCM functioning, for values of k»2, the correction system operates in an ideal situation whereby the correction is almost perfect (<4%) and remains good even for "very" DCM systems (k>>5) wherein the power increment with the frequency remains less than 15%. In conclusion, it is advisable to design the system with the parameter k ≥ 1 in order to exploit at best the control of the maximum output power provided by the compensation circuit of the invention. By referring to the circuit scheme of the embodiment of Figure 8, the group formed by the comparator-buffer(B), by the diode (D) and by the external capacitor (C) of 1 µF, represents the peak detector, while the 47kW resistor (R) permits the discharge of the capacitor (C) when the synchronizing frequency increases. The value of the time constant should be greater than 1/ fos c even if this is not critical, therefore the values shown in the figure may be satisfactory in a large majority of cases, and in particular within the range of the monitors synchronizing frequencies (typically of 25-100 kHz) used in monitors. The PNP transistor (Q) clamps the output voltage of the E/A to a Vbe above the capacitor C voltage, recuperating the drop on the diode D of the detecting circuit. An integrated realization requires the availability of just one pin to connect the external capacitor C. When not required, the function may be disabled by connecting the pin 16 to the reference voltage Vref, that is to pin 4. Finally, what remains to verify is whether the circuit implements the correction law theoretically determined by equation (39). The results of tests undertaken on the circuit of Figure 8, together with the theoretical values, are reported in Table 3 and illustrated in the diagram of Figure 11. Theoretical Actual Diff. % 1 3.000 2.959 -1.37 1,5 2.480 2.500 0.81 2 2.172 2.207 1.61 2,5 1.969 1.983 0.71 3 1.825 1.812 -0.71 3,5 1.719 1.676 -2.50 4 1.636 1.565 -4.34 4,5 1.571 1.479 -5.86 5 1.518 1.410 -7.11 The offset between the theoretical and actual behavior, analytically representable by the following best fit curve V ' peak = 1.717-0.334•log f sync f osc is rather contained. At high frequencies, can be observed a slightly higher correction than the theoretically determined which is advantageous in systems where a DCM (k>1) behavior is prevailing. The real characteristic, resents the effects of the time TOFF which is neglected in an ideal representation of the characteristics of the diodes and the PNP used and could be slightly shifted high through a different selection of the components thus improving correspondence with the theoretical model. An alternative embodiment of the circuit of invention is illustrated in Figure 12. To simplify the illustration, the circuit scheme is in this instance for an embodiment external to the controller integrated circuit, typically represented by the same device L4990. According to this alternative embodiment, the DC signal obtained by detecting the sawtooth signal produced by the oscillator in function of the synchronizing frequency, is not exploited to clamp at a voltage proportional to the DC signal generated by the detector circuit, the output voltage of the controller's error amplifier E/A, but to inject an offset voltage of an amplitude that increases with the frequency of the converter, on the current sensing node (ISEN) (on the pin 13 of Figures 1 and 8, dedicated to the connection of an external current sensing resistor). According to this alternative embodiment, the detector's DC signal must be inverted by employing a buffer in order to change its dependence from the frequency. Furthermore, according to the above analysis, the detected (rectified) and inverted DC signal must be divided by three and suitably shifted, bearing in mind equation (15). This is realized by the operational amplifier OP, provided of a consequent feed-back network formed by the resistors r a and r b , as shown in the diagram, and by using a voltage divider constituted by R1 and R2 to shift the level of output voltage to be applied to the ISEN node (pin 13).

Claims: A method of controlling the power output of a static converter employing a current mode PWM controller, comprising a sawtooth oscillator employing an RC group connected between a node at a reference voltage Vref and ground, an error amplifier (E/A) of the converter output voltage referred to a pre-established voltage and a current control circuit using a current sensing resistor functionally connected in series to a power switch of the converter, characterized in that it comprises the following operations: a) detecting a sawtooth signal produced by said oscillator on the capacitor (C osc ) of said RC group, generating a DC signal having an amplitude inversely proportional to the frequency; b) either clamping the output voltage of said error amplifier (E/A) at a voltage having an amplitude proportional to the amplitude of said DC signal or offsetting the signal present on said current sensing resistor by a voltage corresponding to the difference between a constant voltage and said DC signal. A current mode PWM controller, comprising a sawtooth oscillator using an RC group coupled between a node at a reference voltage V ref and ground, an error amplifier (E/A) of an output voltage referred to a pre-established voltage and a current control circuit using a current sensing resistor functionally connected in series to a power switch of the converter and means for controlling the output power of the converter upon varying the switching frequency, characterized in that said means comprise a detecting circuit (B, D, R, C) of the sawtooth signal produced on the capacitor (C osc ) of said group RC, generating a DC signal of an amplitude inversely proportional to the frequency; and, either a clamp stage (Q) of the output voltage of said error amplifier (E/A) at a voltage level proportional to said DC signal; or an offset circuit (Inv, OP, r a , r b , R1, R2, D3) of the signal present on said current sensing resistor by a voltage corresponding to the difference between a constant voltage and said DC signal. A current mode PWM controller, according to claim 2, characterized in that it is entirely integrated, with the exception of a capacitor (C) that determines the time constant of the detecting circuit, externally connectable to the integrated circuit through a dedicated pin. A current mode PWM controller, according to claim 2, characterized in that said detecting circuit comprises a buffer amplifier (B) functionally connected between said capacitor (C OSC ) of the sawtooth oscillator and the anode of a detecting diode (D) and said clamp stage of the output voltage of the error amplifier (E/A) is constituted by a PNP transistor (Q), the base of which is coupled to the detecting diode cathode (D), the collector of which is coupled to ground and the emitter to the output of the error amplifier, electrically downstream of two directly biased diodes connected in cascade of the output node of the error amplifier. A power supply for a scanning circuit of a cathode tube operating at a varying frequency of synchronization and comprising a static converter DC-DC, employing a current mode PWM controller as defined in claim 2 whose switching frequency is synchronized with said varying frequency.

Inventors: ADRAGNA CLAUDIO, FAGNANI MAURO, GATTAVARI GIUSEPPE, ADRAGNA, CLAUDIO, FAGNANI, MAURO, GATTAVARI, GIUSEPPE
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1997
Main classification: H04N3
IPC codes: H04N3, H02M3