Address generator for display and light modulator including a reconfigurable shift register

Abstract: A spatial light modulator or display comprises pixels (10 11 to 10 mn ), for instance arranged as an active matrix. Addressing the pixels (10 11 to 10 mn ) is controlled by shift registers (12, 24) which are configurable so as to vary the effective resolution of the display. Each shift register (12, 24) comprises a plurality of stages (13 1 to 13 m , 23 1 to 23 n ) which are controlled to operate normally or as "followers", in which latter mode the stage output follows the output of the preceding stage.

Description: The present invention relates to an address generator for a display or spatial light modulator. The invention also relates to a display and to a spatial light modulator. US 5 132 678 discloses a display arrangement for performing non-sequential addressing of rows of pixels. This arrangement supplies scanning pulses to the pixel rows and comprises a first shift register which controls the individual stages of a second shift register. The first shift register contains mask data which determine whether the corresponding stages of the second shift register are bypassed. The outputs of the bypassed stages are inhibited so that consecutive scan pulses may be supplied to non-adjacent pixel rows with the intermediate rows not receiving a scan pulse during any frame refresh cycle. According to a first aspect of the invention, there is provided an address generator for a display or spatial light modulator, comprising a first shift register having a plurality of cascade-connected stages, each of which has an output for controlling a respective first address electrode of the display or spatial light modulator, characterised in that the stages of the first shift register include a first reconfigurable shift register stage which is selectively operable in an alternate mode, in which the output of the first reconfigurable shift register stage follows the output of a preceding stage. The first shift register may be an analogue shift register. As an alternative, the first shift register may be a digital shift register. Each stage of the first shift register may comprise a first memory having a first memory enable input connected to a first phase of a first bi-phase clock line and a second memory having a second memory enable input connected to a second phase of the first bi-phase clock line, the first memory enable input of the first reconfigurable shift register stage of the first shift register being selectively connectable to the second phase of the first bi-phase clock line. Each of the first and second memories may comprise a bistable circuit. Each of the stages subsequent to a first stage of the first shift register may comprise a switch for selectively connecting the first memory enable input to the first or second phase of the first bi-phase clock line. The generator may comprise a first further shift register having a plurality of cascade-connected stages for controlling respective ones of the switches of the first shift register. The first shift register may comprise a first sub-shift register having a first plurality of cascade-connected sub-stages and a second sub-shift register having a second plurality of cascade-connected sub-stages, the first plurality of sub-stages being interlaced with the second plurality of sub-stages. The generator may comprise a second shift register having a plurality of cascade-connected stages, each of which has an output for controlling a respective second address electrode of the display or spatial light modulator, the stages of the second shift register including a second reconfigurable shift register stage which is selectively operable in the alternate mode. The second shift register may be an analogue shift register. As an alternative, the second shift register may be a digital shift register. Each stage of the second shift register may comprise a third memory having a third memory enable input connected to a first phase of a second bi-phase clock line and a fourth memory having a fourth memory enable input connected to a second phase of the second bi-phase clock line, the third memory enable input of the second reconfigurable shift register stage of the second shift register being selectively connectable to the second phase of the second bi-phase clock line. Each of the third and fourth memories may comprise a bi-stable circuit Each of the stages of the second shift register subsequent to a first stage thereof may comprise a switch for selectively connecting the third memory enable input to the first or second phase of the second bi-phase clock line. The generator may comprise a second further shift register having a plurality of cascade-connected stages for controlling respective ones of the switches of the second shift register. According to a second aspect of the invention, there is provided a spatial light modulator including an address generator in accordance with the first aspect of the invention. The spatial light modulator may be of the matrix type, for instance of the active matrix type, and may be of liquid crystal type. According to a third aspect of the invention, there is provided a display including an address generator according to the first aspect of the invention. The display may be of matrix type, for instance of active matrix type, and may be of liquid crystal type. The display may comprise a tracker for determining an observed region of the display at which an observer is looking, and an image data generator responsive to the tracker for generating image data with a first spatial resolution for the observed region and with a second spatial resolution less than the first resolution for another region of the display device. It is thus possible to provide an arrangement which allows variable resolution to be achieved in a display or spatial light modulator. In regions of such a device where the full spatial resolution of the device is not required, the device may be operated at reduced resolution. This allows the addressing speed of the device to be increased while reducing the amount of data required to update each frame. The device itself does not require modification to achieve this. In particular, the address generator or generators supply signals which allow variable resolution to be achieved without modification of the basic device. The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block schematic diagram of a device constituting a preferred embodiment of the invention; Figures 2 and 3 are circuit diagrams of elements of the device of Figure 1; Figure 4 is a diagram illustrating waveforms occurring in the device of Figure 1; Figures 5 and 6 are schematic diagrams illustrating operation of shift registers of the device of Figure 1; Figure 7 is a schematic diagram illustrating variable resolution operation of the device of Figure 1; Figure 8 is a schematic diagram illustrating another embodiment of the device of Figure 1; and Figure 9 illustrates schematically an application of the device shown in Figure 1. Like reference numerals refer to like parts throughout the drawings. The device shown in Figure 1 may be embodied as a spatial light modulator or as a display using any suitable addressing and optical or light emitting technology. However, for convenience of description, the device of Figure 1 will be described as an active matrix liquid crystal display. The display comprises n rows R 1 to R n and m columns C 1 to C m arranged as a rectangular matrix of picture elements (pixels) 10 11 to 10 mn, where the pixel of the ith column and the jth row is referred to as 10 ij . For clarity of illustration, only sixteen of the pixels 10 ij are shown in Figure 1. The columns of the display are addressed by means of column electrodes 11 1 to 11 m which are connected to a shift register 12. The shift register 12 comprises cascade-connected stages 13 1 to 13 m to form a series-in/parallel-out shift register having a data input 14 for receiving serial display row data. Each of the shift register stages 13 1 to 13 m comprises first and second memory devices 15 11, 15 12, to 15 m1, 15 m2. Each of the second memory devices 15 12 to 15 m2 has an output connected to the respective column addressing line 11 1 to 11 m and to the input of the first memory device of the succeeding shift register stage. The second memory devices 15 12 to 15 m2 have clock inputs connected to a second line 17 of a bi-phase clock line which receives clock signals  2 from a clock 18. The first memory device 15 11 of the first stage 13 1 has a clock input connected to a first line 16 of the bi-phase clock line and receives clock signals  1 from the clock 18. The first memory devices 15 21 to 15 m1 of the remaining stages 13 2 to 13 m of the shift register 12 are connected to respective switching elements 19 2 to 19 m, each of which has first and second inputs connected to the lines 16 and 17, respectively. The switching elements 19 2 to 19 m have switch control inputs connected to the outputs of respective stages 20 2 to 20 m of a shift register 21 of the serial-in/parallel-out type. The shift register 21 has an input 22 for receiving configuration data in serial form for determining which of the first and second inputs of each switching element 19 2 to 19 m is connected to its output. Suitable arrangements (not shown) are providing for clocking the configuration data into the shift register 21. The display further comprises row addressing electrodes 22 1 to 22 n which are connected to the outputs of respective stages 23 1 to 23 n of a shift register 24. The stages of the shift register 24 comprise first and second memory devices 25 11, 25 12 to 25 n1, 25 n2 . The shift register 24 is of the same type as the shift register 12 and differs therefrom only in that the input of the first memory device 25 11 is connected to the output of the last memory device 25 n2 so that the shift register 24 operates as a "ring register" continually recirculating the binary data therein. Means (not shown) are provided for presetting the shift register 24 when power is applied to the display such that the memory device 25 12 is set to "1" whereas all of the other memory devices are reset to "zero". The shift register 24 thus supplies a strobe pulse sequentially to the row electrodes 22 1 to 22 n for controlling writing of display data into the pixels 10 ij of the display. The clock 18 supplies clock pulses  3 and  4 to lines 26 and 27, respectively, of another bi-phase clock line. The device further comprises switching elements 28 2 to 28 n and stages 29 2 to 29 n of a shift register 30 having a configuration data input 31, all of which are identical to the switching elements 19 2 to 19 m and the shift register 21 and will not therefore be described further. Each of the memory devices 15 11 to 15 m2 and 25 11 to 25 n2 may be embodied as a complementary latch of the type illustrated in Figure 2. The latch comprises a plurality of complementary metal oxide on silicon field effect transistors arranged to function as a bistable element or flip-flop having normal and inverted inputs I, I , normal and inverted outputs O, O , and a clock input . The switching elements 19 2 to 19 m and 28 2 to 28 n may each be embodied as shown in Figure 3. The switching element comprises an input 31 connected to the sources of metal oxide on silicon field effect transistors 32 and 33, first and second outputs 34 and 35 connected to the drains of the transistors 33 and 32, respectively, and complementary control inputs 36 and 37 connected to the gates of the transistors 32 and 33, respectively. The arrangements shown in Figures 2 and 3 are of known type and will not be described further. Figure 4 is a timing diagram illustrating the two sets of bi-phase clock pulses 1, 2 and 3, 4. The clock pulses 1 and 2 are supplied to the lines 16 and 17 by the clock 18 in synchronism with serial display data supplied to the input 14 of the shift register 12. When a complete row of fresh display data has been written into the shift register 12, the clock pulses  1 and  2 are suspended and the bi-phase clock pulses  3 and  4 are supplied to the lines 26 and 27 by the clock 18 so that the shift register 24 supplies a strobe pulse to the next row or rows of pixels 10 ij . The row of display data is written into the corresponding row of pixels and is displayed until that row is again refreshed. The bi-phase clock pulses 1 and 2 are then supplied to the lines 16 and 17 so as to enter the next row of display data into the shift register 12. This process is repeated continuously so that the display is continuously refreshed on a row-by-row basis. When the last row R n has been refreshed, the process is repeated starting at the first row R 1. Figure 5 illustrates operation of the display using the full spatial resolution of the display. Operation of the shift register 12 is illustrated, the operation of the shift register 24 being substantially identical. The binary display data are represented by the letters A, B, C, D, E. The switching elements 19 2 to 19 4 are controlled by the shift register 21 such that the clock inputs of the memory devices 15 21 to 15 41 are connected to the line 16 so as to receive the first phase clock pulses  1 . The upper row of Figure 5 illustrates the application of a clock pulse  2 which causes the data contained in the memory devices 15 22 to 15 42 to be equated to the data contained in the memory devices 15 21 to 15 41, respectively. The middle row in Figure 5 illustrates the application of a clock pulse  1 to the first memory devices 15 21 to 15 41 to perform a shift operation. This causes the data in each of the second memory devices to be written into the first memory device of the succeeding stage of the shift register. Thus, the bit D contained in the second memory device 15 12 of the stage 13 1 is written into the memory device 15 21 of the stage 13 2 , and so on. The bottom row of Figure 5 illustrates the application of the next clock pulse  2 to perform the equate function. The bit in the first memory device of each stage of the shift register is clocked into the second memory device so as to complete one cycle of operation of the shift register 12. Thus, each stage 13 1 to 13 m of the shift register 12 contains a bit for individually controlling the corresponding pixel of the row of the display which is to be refreshed. Figure 6 is similar to Figure 5 but illustrates operation when reduced horizontal spatial resolution is required. The configuration data in the shift register 21 are such that the switching element 19 3 connects the clock input of the memory device 15 31 to the line 17 so as to receive the clock pulses  2 . The stage 13 3 thus functions as a slave register whereas other stages, such as the stage 13 2, functions as illustrated in Figure 5 as a master register. The operation of the stage 13 3 differs in that it does not perform a shift function. Instead, whenever a clock pulse  2 is supplied to perform the equate operation, both memory devices 15 31 and 15 32 of the stage 13 3 store the bit at the output of the second memory device 15 22 of the preceding stage 13 2. Thus, apart from propagation and parasitic delays through the memory devices 15 31 and 15 32 , the address lines 11 2 and 11 3 receive simultaneously the same address data for the row of the display to be refreshed. The pixels 10 2j and 10 3j of the jth row being refreshed are thus addressed effectively as a single pixel of greater horizontal size and therefore of reduced horizontal resolution. The number of bi-phase clock pulses  1 ,  2 required to refresh a display row is equal to the number of the stages of the shift register 12 acting as master registers. Accordingly, when operation with reduced horizontal resolution is required, the time needed to refresh each row is reduced so that the refresh rate of the display may be increased. Further, the reduced horizontal resolution requires a smaller amount of pixel display data to be calculated, for instance resulting in a reduced burden on a data processor controlling the display. The shift register 24 may be operated in the same way when reduced vertical resolution is required. In this case, each slave register repeats the bit stored in the preceding master register so that a row of display data is written substantially simultaneously to two of the rows of the display. The time required to refresh a frame of display data is proportional to the number of the stages of the shift register 24 acting as master registers so that operation to provide reduced vertical resolution increases the frame refresh rate of the display. Also, as mentioned hereinbefore, the reduced resolution may result in a reduced burden of calculating display data by a data processor controlling the display. It is thus possible to operate a display such that different regions have different effective spatial resolutions. The pixels may effectively be partitioned into "rectangular" groups which receive the same display data and which are addressed as though they were single pixels of lower resolution. This is achieved without requiring any changes in conventional active matrix pixel addressing circuitry since the resolution is defined by the operation of the address generator circuitry. Figure 7 illustrates operation of the display to provide regions of different resolution. The stages of the shift registers 12 and 24 are shown schematically as empty squares representing stages acting as master registers, for instance as shown at 40, and shaded squares acting a slave registers, for instance as shown at 41. The pixels 10 are represented as empty squares corresponding to bright pixels and shaded squares corresponding to dark pixels. The data paths, for instance as shown at 42, indicate the propagation of data through the shift registers for each bi-phase clock pulse. Thus, data from a master register preceding a slave register is clocked substantially simultaneously into the slave register and into the succeeding master register. Although not shown, several consecutive stages may be operated as slave registers so that data from the preceding master register is clocked into all of the slave registers and into the succeeding master register substantially simultaneously. Pixels displaying an image at high resolution, corresponding to the full spatial resolution of the individual pixels, are illustrated at 43 and are located in regions addressed only by master registers in the shift registers 12 and 24. Low resolution regions, such as 44, are provided by pixels which are addressed by a master and one or more subsequent slave registers of both the shift register 12 and the shift register 24. In the region indicated at 44, a master register in each of the shift registers 12 and 24 is followed by a single slave register so that the effective pixel has half the resolution of the actual display pixels in both the vertical and horizontal directions. An intermediate resolution region is illustrated at 45. The pixels of this region are addressed by master registers of the shift register 12 and by a master and at least one slave registers of the shift register 24. Thus, the horizontal resolution is equal to the horizontal resolution of the display pixels but the vertical resolution is equal to half the vertical resolution of the display pixels. During reduced resolution operation, the pixels are addressed by contiguous columns and/or rows so as to form the rectangular groups effectively operating as single pixels. Reduced resolution operation is controlled by the patterns of binary data in the shift registers 21 and 30. The display resolution may therefore be reconfigured by changing the data held in the shift registers 21 and 30. This is achieved by serially entering fresh configuration data. The shift register 21 requires (m-1) bits of data to reconfigure the horizontal resolution whereas the shift register 30 requires (n-1) bits to reconfigure the vertical resolution. In the case where high resolution is needed in certain specific areas (e.g. near the cursor on a computer screen) but not for the majority of the display, a very large display can be run at video rates using the proposed addressing scheme. This is because accessing the high resolution within any part of the display means that the size of the pixels must be small, which in turn necessitates a very large number of pixels in the device. To operate the display conventionally would require N{M τ1 + τ2 } time steps per frame for a display having NxM pixels (N rows, M columns), a column update time of τ1 and a row update time of τ2. If only a fraction x of the pixel rows and y of the pixel columns are required at the highest resolution and the rest at an average of 1/z the resolution, a frame time of only (P τ1 + τ2 )Q+ τ3 is required, where P=Mx+M(1-x)/z,Q=Ny+N(1-y)/z and τ3 is the reconfiguration time which would be approximately (M+N) τ1. These expressions are valid when z is not too large to increase the effective values of τ1 or τ2. For most practical purposes P<N and Q<M. As an example, for z=10 and y=x=0.1, a frame period 0.19N{0.19M τ1 + τ2 }+(M+N) τ1 is required, which for M∼N∼500 could either increase the frame rate by ∼5 or by ∼25 depending on the relative sizes τ 1 of τ 2 (dependent on panel size). This would allow very large displays to be operated at video rates, whereas using conventional addressing would mean an unusable 2Hz frame update for a similar performance display. Savings in addressing time and computation can also be made if only part of a frame is written with a certain column register configuration, and with the remaining parts written with alternative configurations. For example, if a frame can be split into 1 sets of rows each having a column configuration which effectively reduces the line update time to P τ1 + τ2 , and an effective number of rows per part =Q/1, then the frame time is given by (P τ1 + τ2 )Q+1(M+N) τ1 . For small values of 1, this represents a time saving comparable with the case above but with the advantage of varying column resolution as a function of the frame row. In other applications of this addressing scheme, row data may be used instead of the strobing of pixel rows described hereinbefore by a "recirculating" strobe pulse. The arrangement shown in Figure 1 may be modified to achieve this by disconnecting the input of the stage 23 1 from the output of the stage 23 n and connecting it to a data input for receiving serial column data. The row and column data may then be read into the shift registers 12 and 24, respectively, and the whole SLM "strobed" to read the data into the pixels 10 ij simultaneously. Such an arrangement is useful where two dimensionally repeated patterns, such as holographic gratings are to be "displayed" by a SLM. For many computer generated images, each pixel has to be computed separately. This can take a very large amount of time, so typically where coarse resolution produces an adequate image, only a sparse number of pixels are computed to save time. It is known that, to match the coarse resolution of the computed image to that of the display, pixel values may be filled in either by interpolation techniques or simply by replication. This filling in and subsequent need for a very high specification display driver device would be unnecessary with the addressing scheme proposed. Since the proposed effective encoding of the display/SLM device is compatible with sparse computation of pixel points, a low specification display driver can be used, thus reducing hardware cost and physical size. The reduction in computation rate would also result in an energy saving as the energy consumption of microprocessors is roughly proportional to clock rate. In another embodiment of the display device of Figure 1, an interlaced architecture is provided (Figure 8). Such an architecture can be used with any of the above described addressing schemes. Instead of a single shift register 12, an interlaced shift register 60 is provided. The interlaced shift register 60 comprises a first and a second sub-shift register 61, 62, the stages of the first sub-shift register 61 being interlaced with the stages of the second sub-shift register 62. The first and second sub-shift registers 61, 62 are each of the same type as the shift register 12. The stages of the interlaced shift register 60 comprise first and second memory devices 60 11, 60 12 to 60 m1, 60 m2. Each of the second memory devices 60 12 to 60 m2 has an output connected to the respective column addressing line 11 1 to 11 m and to the input of the first memory device 60 11 to 60 m1 of the succeeding shift register stage of the respective one of the sub-shift register 61, 62. The data input 14 comprises a first sub-data input 14a and a second sub-data input 14b. Serial display row data is split and processed in order to produce first and second serial display row data for the first and second sub-data inputs 14a, 14b, respectively. The second memory devices 60 12 to 60 m2 have clock inputs (not shown) connected to the second line 17 of the bi-phase clock line which receives clock signals  2 from the clock 18. The first memory device 60 11 has a clock input (not shown) connected to the first line 16 of the bi-phase clock and receives clock signals  1 from the clock 18. The first memory devices 60 21 to 60 m1 of the interlaced shift register 60 are connected (connections not shown) to the respective switching elements 19 2 to 19 m . A display of the type shown in Figure 1 or 8 may be used to provide a virtual reality (VR) headset as illustrated in Figure 9. Each eye 50 of the observer is provided with a reflective display 51 of the type shown in Figure 1 capable of providing variable resolution. The display is controlled by an image generator 52 which also controls red, green, and blue light emitting diodes 53 which are operated sequentially so as to provide a colour display to each eye. Light from the light emitting diodes 53 is collimated by a lens 54 and reflected by a beam splitter, such as a partially silvered mirror, onto the display 51, which spatially modulates the incident light. The light modulated with the image to be displayed is reflected from the display 51 through the beam splitter 55 and a lens 56 so that the image can be viewed by the eye 50. Light reflected from the eye 50 passes through the lens 56 and is reflected by the beam splitter 55 through a lens 57 to an eye-tracking charge coupled device (CCD) 58 so that an image of the eye 50 is formed on the CCD. The output of the CCD is supplied to an eye tracker 59 which analyses the image of the eye so as to recognise the pupil and the part of the display 51 at which the eye is looking. This information is passed to the image generator 52. The image generator 52 controls the resolution of the display 51 so that the region at which the eye is looking i.e. the region imaged at and around the fovea of the eye, is operated at the full spatial resolution of the display whereas the remainder of the display is operated at reduced resolution. The red, green, and blue components of the colour image are supplied in sequence to the display 51 synchronously with operation of the RGB light emitting diodes 53. The image generator 52 also generates the image data which are to be displayed by the display 51. For synthetically generated images, the image generator 52 effectively contains data concerning the positions of key points of the image to be displayed and software for performing predetermined rules for generating from those points the necessary image data. The image generator 52 thus calculates image data for all of the pixels in the region at which the eye is looking but generates sparse pixel image data corresponding to the reduced resolution for the remainder of the display. It is thus possible to use a display 51 which, if operated at full resolution across the whole of the display, would not be capable of being refreshed sufficiently quickly to prevent disturbing visual artefacts, such as flicker, from being visible. Because it is only necessary to operate the display at its full resolution in the region at which the eye is looking with the remainder being operated at reduced resolution, a relatively slow display can be refreshed sufficiently quickly to avoid or substantially reduce such undesirable visual artefacts. Similarly, the processing power required by the image generator 52 to generate the image data is substantially reduced because it is only necessary to calculate pixels to high spatial resolution in the region which is being viewed by the eye. Other regions can be adequately represented by a reduced spatial density of pixels so that the number of calculations required to refresh each frame of the display can be substantially reduced. It is thus possible for very high resolution displays to be updated at video rates while making substantial savings in computation time and hence in required computation power and electrical power consumption. The display 51 of the type shown in Figure 1 may be replaced by a conventional very high resolution display provided that such a display is capable of being refreshed at normal video rates to avoid the visibility of undesirable visual artefacts. However, where processing power in the image generator 52 is a limiting factor, then the image generator 52 operates in the same way to provide high resolution pixel data in the region of the display being viewed by the eye and reduced resolution image data for the remainder of the display. For instance, image data for a single pixel may be calculated at the middle of a group of pixels with that image data being duplicated in all of the display pixels. It is therefore possible to overcome processing limitations within the image generator 52 whether using a conventional very high resolution display or a variable resolution display of the type shown in Figure 1. It is further possible to reduce the data rate to the display 51 by not supplying colour information to the regions represented by reduced spatial density of pixels. For instance, the green image data may be used effectively as monochrome data and may be split in time between the updating of the 3 RGB subframes by updating every third course pixel with the low resolution green frame information per subframe. In a possible alternative embodiment, the colour sequential display shown in Figure 9 and comprising the display 51 and the light emitting diodes 53 could be replaced by a display in which fixed colour filters are provided as RGB triplets so that all colour data are displayed for each frame. The "coarse resolution" regions automatically amalgamate colours and minimal information is lost because of the colour blindness of the retinal cones in the human peripheral vision. The information of the green pixels would preferably be used to update the low resolution regions because this corresponds to the peak response of the receptors of the human eye. It is possible to provide a virtual reality (VR) headset where eye tracking can be included to track where the eye is looking in order to write to the display in this viewing region at the highest resolution. The periphery can then be written at lower resolution. This is a saving for the display technology allowing very high resolution displays to be updated at video rates and is also compatible with savings in computation where the images need only be computed to high resolution in the region which the eye views. As described above, the modified shift register update scheme can increase frame speeds for devices with very large pixel counts. Large pixel counts and update rates are required in the area of spatial light modulators for encoding coherent beams. This scheme is therefore particularly relevant for this area, especially since variable frame rates (a consequence of efficiently implementing the variable resolution scheme) are tolerated and simple alteration in resolution of a particular pattern can be of benefit (e.g. wavelength selection, angular beam scanning). Applications of coherent beam manipulation by SLMs include beam steering (e.g. laser printing), optical interconnections (e.g. fibre to fibre X-bar switches) and optical computing. By configuring the shift registers such that those used to write pixels in areas not displaying information (dark bands) are grouped together, variable aspect displays are possible that do not require complex data manipulation of the image data. By grouping registers as described, only two extra lines and possibly two pixels per line need be added to the data to display the correct image. This would require small alterations in addressing speed to allow near synchronous operation with the incoming data, thus possibly overcoming the need for local data storage. In all the above applications, a display or SLM using this scheme can be programmed in software to be a conventional display, capable of addressing independently all pixels. This is important when considering compatibility with conventional systems. The techniques disclosed herein do not relate to any specific technologies and can be implemented, for instance, for any device where active matrix addressing is used and mixed resolution update can be used. As described hereinbefore, one possible use is in flat panel display technologies such as active matrix addressed liquid crystal displays. This established technology uses amorphous or polysilicon circuitry on glass substrates to address a 2D modulator array for displaying images. It would be possible to trade off selective area resolution against addressing speed, which in most circumstances allows large fast displays to be realised without significant reduction in picture quality. Alternative displays and coherent optical modulator array technologies include a combination of semiconductor drive circuitry in conjunction with solid state modulators (e.g. PLZT, Deformable mirror devices) or emitters such as in thin plasma and vacuum electrofluorescent displays.

Claims: An address generator for a display or spatial light modulator, comprising a first shift register (12) having a plurality of cascade-connected stages (13 1,..., 13 m ), each of which has an output for controlling a respective first address electrode (11 1,..., 11 m ) of the display or spatial light modulator, characterised in that the stages (13 1,..., 13 m ) of the first shift register (12) include a first reconfigurable shift register stage (13 2 ,...,13 m ) which is selectively operable in an alternate mode, in which the output of the first reconfigurable shift register stage (13 2 ,...,13 m ) follows the output of a preceding stage (13 1,..., 13 m-1 ). A generator as claimed in Claim 1, characterised in that the first shift register (12) is an analog shift register. A generator as claimed in Claim 1, characterised in that the first shift register (12) is a digital shift register. A generator as claimed in any one of the preceding claims, characterised in that each stage (13 1,..., 13 m ) of the first shift register (12) comprises a first memory (15 11,..., 15 m1 ) having a first memory enable input connected to a first phase ( 1 ) of a first bi-phase clock line (16, 17) and a second memory (15 12,..., 15 m2 ) having a second memory enable input connected to a second phase ( 2 ) of the first bi-phase clock line (16, 17), the first memory enable input of the first reconfigurable shift register stage (13 2 ) of the first shift register (12) being selectively connectable to the second phase ( 2 ) of the first bi-phase clock line (16, 17). A generator as claimed in Claim 4, characterised in that each of the first and second memories (15 11,..., 15 m1, 15 12,..., 15 m2 ) comprises a bistable circuit. A generator as claimed in Claim 4 or 5, characterised in that each of the stages (13 2,..., 13 m ) subsequent to a first stage (13 1 ) of the first shift register (12) comprises a switch (19 2 ,...,19 m ) for selectively connecting the first memory enable input to the first or second phase ( 1 , 2 ) of the first bi-phase clock line (16, 17). A generator as claimed in Claim 6, characterised by a first further shift register (21) having a plurality of cascade-connected stages (20 2 ,...,20 m ) for controlling respective ones of the switches (19 2,..., 19 m ) of the first shift register (12). A generator as claimed in any one of the preceding claims, characterised in that the first shift register comprises a first sub-shift register (61) having a first plurality of cascade-connected sub-stages and a second sub-shift register (62) having a second plurality of cascade-connected sub-stages, the first plurality of sub-stages being interlaced with the second plurality of sub-stages. A generator as claimed in any one of the preceding claims, characterised by a second shift register (24) having a plurality of cascade-connected stages (23 1 ,...,23 n ), each of which has an output for controlling a respective second address electrodes (22 1 ,...,22 n ) of the display or spatial light modulator, the stages (23 1 ,...,23 n ) of the second shift register (24) including a second reconfigurable shift register stage (23 2 ,...,23 n ) which is selectively operable in the alternate mode. A generator as claimed in Claim 9, characterised in that the second shift register (24) is an analog shift register. A generator as claimed in Claim 9, characterised in that the second shift register (24) is a digital shift register. A generator as claimed in any one of Claims 9 to 11, characterised in that each stage (23 1,..., 23 n ) of the second shift register (24) comprises a third memory (25 11,..., 25 n1 ) having a third memory enable input connected to a first phase ( 4 ) of a second bi-phase clock line (26, 27) and a fourth memory having a fourth memory enable input connected to a second phase of the second bi-phase clock line, the third memory enable input of the second reconfigurable shift register stage (25 21 ) of the second shift register (24) being selectively connectable to the second phase ( 2 ) of the second bi-phase clock line (26, 27). A generator as claimed in Claim 12, characterised in that each of the third and fourth memories (25 11 ,...,25 n1 ,25 12 ,...,25 n2 ) comprises a bistable circuit. A generator as claimed in Claim 12 or 13, characterised in that each of the stages (23 2 ,...,23 m ) of the second shift register (24) subsequent to a first stage (23) thereof comprises a switch (28 2 ,...,28 n ) for selectively connecting the third memory enable input to the first or second phase ( 3 ,  4 ) of the second bi-phase clock line (26, 27). A generator as claimed in Claim 14, characterised by a second further shift register (30) having a plurality of cascade-connected stages (29 2,..., 29 n ) for controlling respective ones of the switches (28 2,..., 28 n ) of the second shift register (24). A spatial light modulator characterised by an address generator as claimed in any one of the preceding claims. A spatial light modulator as claimed in Claim 16, characterised by being of matrix type. A spatial light modulator as claimed in Claim 17, characterised by being of active matrix type. A spatial light modulator as claimed in any one of Claims 16 to 18, characterised by being of liquid crystal type. A display characterised by an address generator as claimed in any one of Claims 1 to 15. A display as claimed in Claim 20, characterised by being of matrix type. A display as claimed in Claim 21, characterised by being of active matrix type. A display as claimed in any one of Claims 20 to 22, characterised by being of liquid crystal type. A display as claimed in any one of claims 20 to 23, characterised by a tracker (58, 59) for determining an observed region of the display (51) at which an observer is looking, and an image data generator (52) responsive to the tracker (58, 59) for generating image data with a first spatial resolution for the observed region and with a second spatial resolution less than the first resolution for another region of the display device.

Inventors: BROWNLOW MICHAEL JAMES, KAY ANDREW, ROBINSON MICHAEL GERAINT, TOMBLING CRAIG, BROWNLOW, MICHAEL JAMES, KAY, ANDREW, ROBINSON, MICHAEL GERAINT, TOMBLING, CRAIG
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1997
Main classification: G09G3
IPC codes: G09G3, G02F1