ROB BIT COMPENSATION SYSTEM AND METHOD ASSOCIATED WITH A RECEIVER OR CODEC

Abstract: A rob bit compensation system improves the accuracy of the digital signals (112a) received from and transmitted to a digital network (113) (Figs. 1 and 4), such as a telephone network, that employs rob bit signaling (RBS) wherein the network periodically robs a bit for its own use. The system can be employed within a digital modem (101) or a codec/decoder (codec, 106), each of which is interconnected with the digital network that periodically robs a bit every nth frame, where n is, for example, 6 or 24. The system includes a compensation control utilized to detect when a Least Significant bit (LSB) of a particular frame of data consistently exhibits a certain logic state (164 and 156), either a mark (logical 1) or a space (logical 0). When an LSB of a particular frame does consistently exhibit the certain logic state, then the particular frame is considered an RBS. Furthermore, the compensation control (133) causes a quantity (e.g., one-half of an LSB) to be added or subtracted with the data corresponding with the RBS frame via a set of adders (131a and 131b) in order to enhance accuracy of the RBS frame.

Description: ROB BIT COMPENSATION SYSTEM AND METHOD ASSOCIATED WITH A RECEIVER OR CODEC FIELD OF THE INVENTION The present invention generally relates to data communications and, more particularly, to a rob bit compensation system and method for improving the accuracy of digital signals received from a digital network that periodically robs a bit, for example but not limited to, a telephone network. BACKGROUND OF THE INVENTION A telephone network is often used as an interface between a digital modem and an analog modem. Generally, a digital modem is a device that communicates digital data by using digital signals that replicate analog waveforms. An analog modem is a device that commumcates digital data by encoding the data on analog waveforms. Fig. 1 shows a typical telephone network 99 for interconnecting a digital modem 101 and an analog modem 102. The digital modem 101 is usually interconnected with a digital network 113 via digital connections 112a, 112b. For instance, the digital modem 101 may be interconnected to a digital network 113 in the form of a public switch telephone network (PSTN) via a Local Exchange Carrier (LEC) subscriber loop. The digital network 113 may comprise, among other things, a Tl carrier system, a basic rate or primary rate Integrated Services Digital Network (ISDN), a fiber optic cable network, a coaxial cable network, a satellite network, or even a wireless digital communications network. Communications over the digital network 113 are conducted in accordance with a pulse code modulation (PCM) scheme. Channel capacity through these digital facilities is typically between 56 and 64 kilobits per second (kb/s). Coding of the signals is also employed so that compression and a constant signal/distortion performance over a wide dynamic range is achieved for optimal transmission of voice signals. A commonly used coding technique is a nonlinear mu-law coding. The linear amplitude L corresponding with each code word is encoded, or converted to, a mu-law code word by the following equation: M=(L+33)*2 W ' where M is the mu-law magnitude (e.g. , 4 bits), L is the linear amplitude (e.g. , 14 bits), and N is the mu-law segment, or frame (e.g. , 3 bits). The mu-law code word is decoded, or converted to, a linear code word as follows: L={(2M+33)2 N -33} The digital network 113 is in turn interconnected with another LEC subscriber loop that includes a coder/decoder (codec) 106. The codec 106 is interconnected with the digital network 113 via digital connections 114a, 114b. The codec 106 is often situated at a telephone company office or along a street near the analog modem subscriber in a subscriber loop carrier (SLC) device. The codec 106 provides an interface between the digital network 113 and an analog telephone connection 118, sometimes referred to as a copper loop. For communications in the direction from the digital network 113 to the analog modem 102, the codec 106 includes a mu-to-linear digital-to-analog converter (DAC) 109. The converter 109 converts nonlinear mu-law levels to a linear analog signal. For communications in the direction from the analog modem 102 to the digital network 113, the codec 106 includes a linear-to-mu analog-to-digital (ADC) converter 107. The converter 107 converts the linear analog signal to nonlinear mu-law code words. A hybrid 103 is in communication with the DAC and ADC via respective low pass filters (LPFs) 111, 105. The hybrid 103 serves to separate the bidirectional analog signals from the analog telephone connection 118 into unidirectional transmit and receive analog signals sent to and received from the ADC 107 and the DAC 109, respectively. Furthermore, the analog modem 102 is connected to the analog telephone connection 118 and communicates analog signals therewith. Thus, communications occur between the digital modem 101 and the analog modem 102 by way of the digital network 113 and the codec 106. A method known as rob bit signaling (RBS) is oftentimes utilized in the digital network 113 to communicate on-hook/off-hook status between the modems 101 , 102 and the digital network 113. RBS forces the least significant bit (LSB) of every nth frame, where n is typically 6 or 24, to a constant logic level, either logical 1 or 0. Unfortunately, RBS causes the block error rate of data transfers to increase and the peak error to increase from 0.5 LSB to 1.5 LSB, as is illustrated in Fig. 2. More specifically, with reference to Fig. 2, logic states are decoded by a receive subsystem associated with the digital modem 101 in accordance with the decode step function indicated at reference numeral 122. The possible maximum error e resulting from the encoding/decoding process for any given signal level is 0.5 LSB. Further, when an RBS frame occurs, the LSB is driven to a predetermined logical state, either a mark (logical 1) or a space (logical 0)- Therefore, the logic states are decoded as indicated by step functions 123 and 124 for the mark and space, respectively, as shown Fig. 2. The possible maximum error in both the 1-RBS frame and the 0-RBS frame resulting from the encoding/decoding process is 3*e, or 1.5 LSB. Almost needless to say, high speed modem performance is seriously degraded as a result of RBS. Hence, there exists a need in the industry for systems and methods for coping with RBS and for increasing the speed of data transfers through the digital network that periodically robs a bit. SUMMARY OF THE INVENTION The invention provides for a rob bit compensation system and method for improving the accuracy of digital signals received from a digital network, such as a telephone network, that periodically robs a bit. As a result of the inventive system and method, high speed data transfers through the digital network are realized. In general, the invention can be employed within a digital modem or a coder/decoder (codec), each of which is interconnected with a digital network that periodically robs a bit every nth frame, where n is, for example but not limited to, 6, 12, or 24. The rob bit compensation system can be implemented in association with the receive subsystem that is associated with the digital modem or in a subsystem within a codec that is associated with the communication path that receives data from the digital network. In the context of the receive subsystem in a digital modem, the rob bit compensation system is employed as follows. A compensation control of the rob bit compensation system is utilized to receive digital data, such as mu-law coded data, from the digital network. The compensation control detects when a least significant bit (LSB) of a particular frame of the digital data consistently exhibits a certain logic state, either a mark (logical 1) or a space (logical 0). When an LSB of a particular frame does consistently exhibit the certain logic state, then the particular frame is an RBS frame. Furthermore, the compensation control causes a quantity to be mathematically combined with the linear digital data corresponding with the RBS frame via an adder(s) in order to enhance accuracy of the RBS frame. As an example, one-half of an LSB may be subtracted from (i.e. , add 2's complement) the digital data corresponding with the RBS frame when the certain logic state is a logical 1 , or alternatively, one-half of an LSB may be added to the digital data corresponding with the RBS frame when the certain logic state is a logical 0. In the context of a codec, the rob bit compensation system is employed as follows. The codec is configured to convert an analog signal that is directed in a first direction (e.g. , received from an analog modem) from a linear analog signal to mu-law nonlinear digital data and the mu-law digital data that is directed in a second direction (e.g. , received from the digital network) that opposes the first direction from mu-law nonlinear digital data to a linear analog signal. The compensation control of the rob bit compensation system can be utilized to detect when an LSB of a particular frame of the signals received from the digital network consistently exhibit a certain logic state. Furthermore, a quantity can be combined with the particular frame, or the RBS frame, in order to enhance accuracy of the RBS frame. The invention can also be conceptualized as providing a method for improving the accuracy of digital data received from a digital network that periodically robs a bit. The method can be broadly summarized as follows: receiving digital data from the digital network; detecting a frame in the received digital data having a rob bit; and modifying the frame so that error associated with the frame resulting from the rob bit is reduced. The invention has numerous advantages, a few of which are delineated hereafter, as merely examples. An advantage of the invention is that it increases the accuracy of data received from a digital network that periodically robs a bit. Another advantage of the invention is that data transfer rates through the digital network can be increased. Another advantage of the invention is that it reduces the RBS induced peak error in a received signal from 1.5 LSB to 1.0 LSB. Another advantage of the invention is that it can detect any number and frequency of RBS frames, even when the digital network includes a plurality of subnetworks, each of which robs its own bit. Another advantage of the invention is that the data rate of modem communications can be increased from 28,800 b/s to 33,600 b/s. Another advantage of the invention is that for modems operating at 33,600 bits per second (B/S), the invention reduces the block error rate from at least 0.03 to 0.003 and typically achieves at least tenfold improvement. Another advantage of the invention is that it is simple in design, easily implemented in existing digital modems and codecs, and is reliable in operation. Another advantage of the invention is that it can be implemented with software, hardware, or a combination thereof. Preferably, the invention is implemented in software that is stored in memory and that configures and drives a conventional digital signal processor (DSP). Other objects, features, and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional objects, features, and advantages be included herein within the scope of the present invention, as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS The invention can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating principles of the present invention. In the drawings, like reference numerals designate corresponding parts throughout the several views. Fig. 1 is an electronic block diagram of a possible implementation for coupling together digital and analog modems over a digital network; Fig. 2 is a graph comparing the effects of rob bit signaling (RBS) in a prior art decoding system and in a decoding system that employs the rob bit compensation system of the invention; Fig. 3 is an electronic block diagram of a possible implementation of a receive subsystem that employs the rob bit compensation system of the invention within the digital modem of Fig. 1; and Fig. 4 is an electronic block diagram of a possible implementation of a coder/decoder (codec) that employs the rob bit compensation system of Fig. 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention is a rob bit compensation system 130, which will be described hereafter with reference to Figs. 2 through 4. Generally, the rob bit compensation system 130 of the invention can be implemented in connection with a data path in either the digital modem 101 (Fig. 1), in a codec 106 (Fig. 1), or elsewhere, in order to compensate for and minimize the distortion imposed upon data that is received from a digital network 113 (Fig. 1) that periodically robs a bit from every nth frame, where n is typically 6, 12, or 24. When implemented in the digital modem 101, the rob bit compensation system 130 can be employed in connection with a receive subsystem (Fig. 3). When implemented in connection with a codec 106 (Fig. 4), the rob bit compensation system 130 is employed in connection with the data path leading from the digital network 113. Note that the copending commonly assigned application entitled "Rob Bit Compensation System Associated With A Transmitter Or Codec," filed on the same day as the present application by the inventors herein and assigned serial no. (to be assigned) describes a rob bit compensation system that can be utilized in connection with a transmit subsystem or codec for manipulating data that is transmitted to the digital network, as opposed to data that is received from the digital network. A. Receive Subsystem The rob bit compensation system 130, as employed in connection with a receive subsystem 121 within the digital modem 101 (Fig. 1), will now be described with reference to Fig. 3. The general functionality implemented by the receive subsystem 121 of Fig. 3 in combination with the rob bit compensation system 130 can be broadly summarized as follows. Non-RBS Frames For frames of digital data that do not have a rob bit, the rob bit compensation system 130 passes the digital data essentially unchanged to a mu-to-linear converter 138, which converts the mu-law code words to linear code words via the following equation: L={(2M+33)2 N -33} where L is the linear magnitude (e.g. , 14 bits) corresponding with each code word, M is the mu-law magnitude (e.g. , 4 bits), and N is the mu-law segment (e.g., three bits). RBS Frames Having A Mark LSB For frames of digital data that have a rob bit in the form of a mark, the combination of the rob bit compensation system 130 and mu-to-linear converter 138 functions as follows. Each mu-law code word is converted to a linear code word by the following equation: L={(2M+32)2 N -33} RBS Frames Having A Space LSB For frames of digital data that have a rob bit in the form of a space, the combination of the rob bit compensation system 130 and mu-to-linear converter 138 functions as follows. Each mu-law code word is converted to a linear code word by the following equation: L={(2M+34)2 N -33} With reference to Fig. 3, the receive subsystem 121 is configured to receive a serial stream of mu-law code words from the digital network 113, as denoted by connection 112a. When the digital network 113 is a telephone network, the mu-law code words are generally 8 bits each and are pulse code modulated at 8000 hz from, for instance, a Tl carrier connection, a basic rate ISDN connection, or a primary rate ISDN connection. A sampling switch 123 communicates the mu-law code words 112a to a rob bit compensation system 130. Specifically, the switch 123 communicates the mu-law code words 112a to a compensation addition mechanism 131 (adders 131a, 131b) within t ' le rob bit compensation system 130. When an RBS frame is detected by the rob bit compensation system 130, the compensation addition mechanism 131 is controlled to enhance the accuracy of each RBS frame by combining a quantity (i.e. , adding or subtracting an amount) with each RBS frame. Architecturally, the compensation addition mechanism 131 as shown in Fig. 3 includes successive adders 131a, 131b and is controlled by a compensation control 133. Generally, the compensation addition mechanism 131 receives successive 8-bit mu-law code words 126a and to each, it performs one of the following: (a) mathematically combines a zero with the code word 126a to convert the 8-bit code word 126a to a 9-bit code word 137 (i.e. , effectively, forwards the code word 126a unchanged but with an additional bit); (b) adds 0.5 LSB to the code word 126a in order to produce a 9-bit mu- law code word 137; or (c) subtracts 0.5 LSB (i.e. , adds 2's complement of 0.5 LSB, or -0.5 LSB) to the code word 126a in order to produce a 9-bit mu-law code word 137. In order to accomplish the aforementioned functionality, the adder 131a of the compensation addition mechanism 131 is configured to add either nothing or +0.5 LSB to each 8-bit code word 126a in order to generate a 9-bit code word 127, while similarly, the adder 131b is configured to add either nothing or -0.5 LSB to each 9-bit code word 127 in order to generate a 9-bit code word 137. The compensation control 133 controls the adders 131a, 131b, as indicated by respective reference arrows 151a, 161a, to accomplish one of the aforementioned options. Furthermore, the compensation control 133 is configured to receive the LSB 126b of each code word 126. The compensation control 133 detects when an RBS frame occurs and is configured to advise the compensation addition mechanism 131 when to combine a quantity (i.e. , to effectively add or subtract an amount) with the RBS frame in order to enhance the accuracy of the RBS frame. In architecture, the compensation control 133 of the rob bit compensation system 130 has mark RBS logic for detecting an RBS frame having an LSB that is a mark and space RBS logic for detecting an RBS frame having an LSB that is a space. The space and mark RBS logics generate respective control signals 151a, 161a for the compensation addition mechanism 131. The signals 151a, 161a are indicative of whether or not there is an RBS frame and whether the RBS frame either has a space LSB or a mark LSB, respectively. The mark RBS logic includes an AND logic gate 144 and a mark ring counter 146. The AND logic gate 144 receives the LSB 126b from each incoming frame and the output 148 from the mark ring counter 146. The AND logic gate 144 produces a data signal 151 for the mark ring counter 146 based upon its inputs 126b, 148. Based upon its logic state, the signal 151 indicates whether or not an RBS frame having a mark LSB is present. The mark ring counter 146 is a shift register or other suitable mechanism. The mark ring counter 146 is configured to receive its own output at its data terminal (D), by way of the AND logic gate 144 as indicated by successive reference numbers 148, 144, 151. The counter 146 is preset so that all states exhibit a logical 1 via an initialization (INIT) signal 153b and is clocked by a clock signal 155 at a rate of preferably 8000 hz to correspond with the frame frequency rate of the incoming signal 126. In the preferred embodiment, the mark ring counter 146 is an n state device, where n represents the frequency of the RBS frame. Typically, n is 6, 12, or 24. The mark ring counter 146 is shifted one state of n states every frame. In Fig. 3, the mark ring counter 146 shifts to the left so that the most significant bit (MSB) is output at reference arrow 148. When RBS compensation should be applied, the mark ring counter 146 output (i.e. , the most significant bit (MSB) of the stored word) exhibits a logical 1, the LSB 126b exhibits a logical 1, and thus, the AND logic gate output 151 exhibits a logical 1. Hence, the combination of the AND logic gate 144 and the mark ring counter 146 automatically tracks the RBS frames that have a mark LSB. The space RBS logic detects RBS frames having an LSB that exhibits a space. The space RBS logic includes an inverter 163, an AND logic gate 164, and a space ring counter 156. The inverter 163 and the AND logic gate 164 are implemented in succession. The AND logic gate 164 receives the inverse of the LSB 126b from each incoming frame and the output 158 from the space ring counter 146. The AND logic gate 164 produces a data signal 161 for the space ring counter 156 based upon its inputs 126b, 158. Based upon its logic state, the signal 161 indicates whether or not an RBS frame having a space LSB is present. The space ring counter 156 is a shift register or other suitable mechanism. The space ring counter 156 is configured to receive its own output at its data terminal (D), by way of the AND logic gate 164 as indicated by successive reference numbers 158, 164, 161. The counter 156 is preset so that all states exhibit a logical 1 via an initialization (T-NIT) signal 153a and is clocked by a clock signal 155 at a rate of preferably 8000 hz to correspond with the frame frequency rate of the incoming digital data 126. In the preferred embodiment, just as with the mark ring counter 146, the space ring counter 156 is an n state device, where n represents the frequency of the RBS frame, and the space ring counter 156 is shifted one of n states every frame. In Fig. 3, the space ring counter 156 shifts to the left so that the MSB is output at reference arrow 158. When space RBS compensation should be applied, the space ring counter 156 output (i.e. , the most significant bit (MSB) of the stored word) exhibits a logical 1, the LSB 126b exhibits a logical 0, the inverter 163 exhibits a logical 1, and thus, the AND logic gate output 161 exhibits a logical 1. Hence, the combination of the inverter 163, the AND logic gate 164, and the mark ring counter 156 automatically tracks the RBS frames that have a space LSB. As a result of the rob bit compensation system 130 in Fig. 3, the receive subsystem 121 can decode each RBS frame so that the maximum possible error in each RBS frame is no greater than 1.0 LSB ( . e. , 2*e), as is reflected in the step function 125 in Fig. 2. Recall that the possible maximum error in the RBS frame resulting from the encoding/decoding process of the prior art is 1.5 LSB (i.e. , 3*e). Almost needless to say, modem performance is significantly improved by the invention during an RBS frame. Further note that multiple RBS bits can occur as the signal passes through multiple switches, multiplexers, or subscriber loop carriers (SLC) associated with the digital network 113. Thus, the ring counters 146, 156 may need to monitor and compensate for RBS in multiple bit positions. The mu-to-linear converter 138 receives the 9-bit mu-law code words 137 from the compensation addition mechanism 131 of the rob bit compensation system 130. The converter 138 is a well known component and is configured to perform a mu-law expansion operation on the mu-law digital signal 137. In this regard, in the preferred embodiment, the converter 138 converts each 9-bit mu-law code word 137 to a 14-bit linear code word 163, which is passed to a decoder 165. The decoder 165 includes functionality for demodulating and processing the received signal so that it can be communicated to a local DTE. For this purpose, the decoder 165 may include, for example, an echo canceler, a filter, an equalizer, etc. The decoder 165 may be designed to implement any suitable industry standard protocol, for example but not limited to, the V.34 recommendation. When the decoder 165 employs V.34 demodulation and signal processing, the data 167 that is output from the decoder 165 complies with the V.34 protocol so that the data stream corresponds with one of the fourteen possible V.34 speeds between 2400 b/s, and 33,600 b/s, inclusive. As is well known in the art, the V.34 protocol implements a form of quadrature amplitude modulation. After performing the demodulation and other signal conditioning processes, the decoder 165 outputs the receive data 167 in the form of a digital data stream to a DTE, for example but not limited to, a computer with a large data base. The elements of the receive subsystem 121 of Fig. 3, as described previously, can be implemented in software, firmware, hardware, or a combination thereof. In the preferred embodiment, these elements, and particularly, the rob bit compensation system 130, is implemented in software that is stored in memory and that configures and drives a digital signal processor (DSP). The appendix to this document shows the preferred embodiment for the code that can be utilized for driving a DSP to implement the rob bit compensation system 130. When implemented in software, the rob bit compensation system 130 can be stored and transported on any computer-readable medium for use by or in connection with a computer-related system or method. In the context of this document, a computer- readable medium is an electronic, magnetic, optical, or other physical device or means that can contain or store a computer program for use by or in connection with a computer-related system or method. Example In order to further clarify operation of the rob bit compensation system 130, an example with specific data is set forth hereafter. First, it is assumed that the rob bit compensation system 130 receives data 126 in the form of a series of 8-bit frames with bit patterns as set forth in Table A hereafter. Table A FRAME # DATA LSB 1 0110000 1 2 0010111 0 3 1111001 1 4 1010010 1 5 0000100 0 6 0101011 1 1 1111000 1 1010000 0 2 Based upon the frames set forth in Table A, the compensation control 133 will determine that the digital network 113 employs 3 rob bits in the form of a mark in the frames 1 , 3, and 4. Specifically, the mark ring counter 146 will be loaded via the LSBs 126b with the bit pattern "101100", each bit of which corresponds to a frame, and the space ring counter 156 is loaded with the bit pattern "000000", each bit of which corresponds to a frame. These patterns are shifted one bit to the left in each counter 156, 146 during each frame, and the most significant bit (MSB) in each counter 146, 156 is analyzed by being passed to the respective adders 131a, 131b, as indicated by corresponding reference arrows 151, 161 (Fig. 3). When the MSB in mark ring counter 146 is a logical "1 ", then the adder 131b will add -0.5 LSB to the respective frame, and in converse, when the MSB in the mark ring counter 146 is a logical "0", then the adder 131b will add nothing to the respective frame. Similarly, when the MSB in the space ring counter 156 is a logical "1", then the adder 131a will add +0.5 LSB to the respective frame, and in converse, when the MSB in the mark ring counter 146 is a logical "0", then the adder 131b will add nothing to the respective frame. As is apparent from the examples of the bit patterns, the mark ring counter 146 will cause -0.5 LSB to be added (i.e. , subtract 0.5 LSB from) to select frames, while the space ring counter 156 will cause no quantities to be added to any of the frames. Table B set forth hereafter illustrates the shifting of the word in the mark ring counter 146 and the implementation of compensation during RBS frames. Table B FRAME # DATA LSB MARK RING COMPENSATION COUNTER VALUE 1 0110000 1 101100 yes 2 0010111 0 011001 no 3 1111001 1 110010 yes 4 1010010 1 100101 yes 5 0000100 0 001011 no 6 0101011 1 010110 no 1 1111000 1 101100 yes 2 1010000 0 011001 no As illustrated in Table B, with the specific counter bit patterns set forth previously in this example, every first, third, and fourth frame will be compensated by addition of - 0.5 LSB, while the remainder of the frames are left unchanged, regardless of the current state of the LSB in that frame. B. Coder/Decoder (Codec) The codec 106 (Fig. 1) can also be equipped with a rob bit compensation system 130 in connection with one or both of its data streams. The rob bit compensation system 130 may be associated with the communications connection 114b leading from the digital network 113. The rob bit compensation system 130 may also be associated with the communications connection 114a leading to the digital network 113. However, this implementation generally requires some type of feedback in order to know which frames are LSB frames, and accordingly, this design is more complex and more costly, making it undesirable in many cases. The latter configuration is not shown in the figures for simplicity, while the former configuration is illustrated in Fig. 4 and described hereafter. For a discussion of the latter configuration, refer to copending commonly assigned application entitled "Rob Bit Compensation System Associated With A Transmitter Or Codec," filed the same day as the present application by the inventors herein and assigned serial no. (to be assigned). With reference to Fig. 4, in regard to the communications connection 114b, the rob bit compensation system 130 is configured to receive the stream of mu-law nonlinear digital code words on connection 114b from the digital network 113. Further, the system 130 is adapted to combine compensation, when appropriate, to produce a compensated mu-law nonlinear digital code words 114b', which are passed to a mu-to-linear digital-to- analog (DAC) converter 109. The mu-to-linear DAC 109 produces a linear analog signal 115 for the LPF 111. In the preferred embodiment, the rob bit compensation system 130 causes one-half of an LSB to be subtracted from the mu-law nonlinear digital code word 114b corresponding with the RBS frame when the RBS LSB is a mark (logical 1), or alternatively, one-half of an LSB to be added to the mu-law nonlinear digital code word 114b corresponding with the RBS frame when the RBS LSB is a space (logical 0). Note that the elements of the codec 106 of Fig. 4 can be implemented in software, firmware, hardware, or a combination thereof. In the preferred embodiment, the elements 103, 105, 107, 109, and 111 are implemented in hardware, while the rob bit compensation system 130 is implemented in hardware or software/firmware in the DAC 109. In embodiments where the system 130 is implemented in software or firmware, it may be stored and transported on any computer-readable medium for use by or in connection with a computer-related system or method. C. Software The rob bit compensation system 130 of the invention can be implemented in software. One possible implementation of the software version for the receive subsystem 121 is set forth hereafter. mu21in: y=0x00ff /* mask for input Mulaw value */ /* y = 0000 0000 1111 1111 */ a0=a0&y /* mask lower 8 bits of aOh */ if eq a0=y /* Invert if zero */ a0=a0 A y /* invert Mulaw bits since an */ /* inverted Mulaw value is expected */ /* aOh = 0000 0000 Seee cccc */ rl =temp x=33 rO=rbs_ring /* Read RBS identifier bits */ al = *ι0+ + all=*r0~ al =al < < 1 /* Shift next bit to msb */ *K ) + + =al /* Save RBS identifiers */ y = l /* Test Isb of mulaw input */ yl=0x80 /* Set RBS identifier bit */ if pi goto mu21in20 /* No changes if msb=0, detector 1 */ aO&y if ne goto mu21in20 /* No change if lsb= 1 , no RBS */ χ=34 /* Change conversion constant */ al =al |y mu21in20: *rO+ + =all /* Save RBS identifiers */ mu21in30: al =*ιO+ + all=*rO- al =al < < l /* Shift next bit to msb */ *r + + =al /* Save RBS identifiers */ if pi goto mu21in40 /* No changes if msb=0, detector 2 */ aO&y if eq goto mu21in40 /* No change if lsb=0, no RBS *l x=32 /* Change conversion constant */ al =al | y mu21in40: *ι0+ + =all /* Save RBS identifiers */ *rl=x /* Save constant */ al=a0> >4 /* segment into lower 3 bits */ /* alh = 000000000000 Seee */ y =0x0007 /* mask for segment (exponent) */ / * • y * = 0000000000000111 */ al=al&y /* alh = 000000000000 Oeee */ al =-al /* negate the segment number */ c0=al /* set counter to negative segment */ /* number */ y=0x000f /* mask for compressed code word */ /*y= 0000000000001111 */ al =a0&y /* alh = 000000000000 cccc */ al=al<<l /* compressed code word left */ /* alh = 00000000000c cccO */ y = *rl /* put Is before and after the / al=al+y /* compressed code word */ /* alh = 00000000001c cccl */ { /* the formatted compressed */ ifc01tal=al<<l /* code word into place, , ii..ee. */ } /* apply exponent (segment) */ /* alh = 000000001c cccl seg = 0 */ /*alh = 000000 Olcc cclO seg = 1 */ /•alh = 000000 Iccc clOO seg = 2 */ /*alh = 000001 cccc 1000 seg = 3 */ / ♦ alh = 00001c cccl 0000 seg = 4 */ /*alh = 00 Olcc cclO 0000 seg = 5 */ /* alh = 00 Iccc clOO 0000 seg = 6 */ /* alh = 01 cccc 10000000 seg = 7 */ y=33 al=al-y /* alh -= 0x21 subtract bias (33) */ y =0x0080 /* mask for sign bit */ /*y = 0000000010000000 */ a0=a0&y /* aOh = 00000000 S0000000 */ if ne al =-al /* if linear value is negative then */ /* take the 2s complement to make the*/ /* value negative */ a0=al<<l /* the output will be 14 bits left */ /* justified in aOh */ a0=rnd(a0) rεturn /* aOh holds the 14 bit linear value */ END OF CODE Many variations and modifications may be made to the preferred embodiments of the invention. All such modifications and variations are intended to be included herein within the scope of the present invention, as is defined by the following claims. In the claims set forth hereinafter, the structures, materials, acts, and equivalents of all "means" elements and "logic" elements are intended to include any structures, materials, or acts for performing the functions specified in connection with said elements.

Claims: CLAHMS Wherefore, the following is claimed: 1. A system for improving accuracy of a digital signal received from a digital network that periodically robs a bit, comprising: means for receiving digital data from said digital network; means for detecting a frame in said digital data having rob bit; and means for modifying said frame so that error associated with said frame resulting from said rob bit is reduced. 2. The system of claim 1 , wherein said means for modifying comprises a means for combining a value with said frame. 3. The system of claim 1, wherein said means for modifying comprises a means for subtracting one half of a least significant bit to said frame. 4. The system of claim 1, wherein said means for modifying comprises a means for adding one half of a least significant bit to said frame. 5. The system of claim 1, wherein further comprising: logic configured to receive a least significant bit from each frame of said digital data and a ring counter signal, said logic configured to produce a control signal based upon said digital data and said ring counter signal; a ring counter configured to receive said least significant bit of each said frame, said ring counter configured to generate said ring counter signal; and an adder configured to mathematically combine a quantity with said digital data based upon said control signal. 6. The system of claim 1, wherein further comprising: logic configured to receive a least significant bit from each frame of said digital data, a mark ring counter signal, and a space ring counter signal, said logic configured to produce a control signal based upon said digital data and said mark and space ring counter signals; a mark ring counter configured to receive said least significant bit of each said frame, said mark ring counter configured to generate said mark ring counter signal; and a space ring counter configured to receive said least significant bit of each said frame, said space ring counter configured to generate said space ring counter signal; and an adder configured to mathematically combine a quantity with said digital data based upon said control signal. 7. The system of claim 1 , wherein said frame is every nth frame of said digital data, where n is any integer number greater than zero. 8. The system of claim 1 , further comprising a means for transmitting said modified frame to an analog connection. 9. The system of claim 1, wherein said means for receiving, said means for detecting, and said means for modifying are all implemented in software. 10. The system of claim 1, wherein said means for receiving, said means for detecting, and said means for modifying are all implemented in a digital signal processor. 11. The system of claim 1, wherein said digital data is mu-law coded and further comprising a mu-to-linear converter connected to said means for modifying and configured to convert said mu-law digital data to linear digital data. 12. A computer readable medium having a program for improving accuracy of a digital signal received from a digital network that periodically robs a bit, the program comprising: means for receiving digital data from said digital network; means for detecting a frame in said digital data having rob bit; and means for modifying said frame so that error associated with said frame resulting from said rob bit is reduced. 13. The medium of claim 12, wherein said program further comprises a means for transmitting said modified frame to an analog connection. 14. A method for improving accuracy of a digital signal received from a digital network that periodically robs a bit, comprising the steps of: receiving digital data from said digital network; detecting a frame in said digital data having rob bit; and modifying said frame so that error associated with said frame resulting from said rob bit is reduced. 15. The method of claim 14, wherein said modifying step comprises the step of combining a value with said frame. 16. The method of claim 14, wherein said modifying step comprises the step of subtracting one half of a least significant bit from said frame. 17. The method of claim 14, wherein said modifying step comprises the step of adding one half of a least significant bit from said frame. 18. The method of claim 14, further comprising the steps of: detecting when a least significant bit of a particular frame of said digital data consistently exhibits a certain logic state; and combining a quantity with said digital data corresponding with said particular frame when said least significant bit of said particular frame consistently exhibits said certain logic state. 19. The method of claim 14, further comprising the step of modifying every nth frame of said digital data, where n is any integer number greater than zero. 20. The method of claim 14, further comprising the step of, after said modifying step, transmitting said frame of said digital data to an analog connection. 21. The method of claim 18, wherein said certain logic state is a mark. 22. The method of claim 18, wherein said certain logic state is a space. 23. The method of claim 18, further comprising the steps of: evaluating said least significant bit to detect when said bit exhibits a mark; and evaluating said least significant bit to detect when said bit exhibits a space.

Inventors: BETTS WILLIAM LEWIS, SOUDERS KEITH ALAN, BETTS, WILLIAM, LEWIS, SOUDERS, KEITH, ALAN
Applicants: PARADYNE CORP, PARADYNE CORPORATION
Application year: 1997
Main classification: H04L25
IPC codes: H04J3, H04Q11