A power amplifier with bootstrap voltage clamp

Abstract: An amplifier output stage (1) having an output transistor (M1) connected to a high supply voltage (+Vcc) and a bootstrap terminal (5) coupled to a control terminal (Vg) of the output transistor through control means (4), the stage comprising a capacitor (C) arranged between the bootstrap terminal and the output (6) of the stage for elevating the voltage at the bootstrap terminal above the high supply voltage, and means for limiting the voltage at the bootstrap terminal to a predetermined threshold, wherein the means for limiting (10) directly act on the control terminal of the output transistor to reduce the conductivity of the output transistor when the voltage at the bootstrap terminal exceeds the threshold.

Description: The present invention relates to a power amplifier of the type comprising a bootstrap capacitor. A bootstrap capacitor is used, in particular in audio amplifiers, to force full conduction of the high-side transistor of the output stage of the amplifier in order to deliver a maximum power to the load with lower energy dissipation in the amplifier. The invention more particularly relates to a circuit for clamping the bootstrap voltage so that this voltage does not reach the breakdown voltage of transistors of the output stage. Figure 1A partially shows a bootstrapped output stage of a conventional amplifier. Amplifier 1 has a positive supply terminal 2 and a negative supply terminal 3 which are respectively connected to a positive supply line +Vcc and to a negative supply line -Vcc (or ground). The output stage includes a high-side transistor M1 and a low-side transistor M2, for example N-channel MOS transistors, connected in series between terminals 2 and 3. The gate of transistor M1 is coupled to a bootstrap terminal 5 through a current source 4. The source of transistor M1, connected to the drain of transistor M2, constitutes the output terminal 6 of the amplifier 1. The gate of transistor M1 is connected to supply line -Vcc through a series connection of two N-channel MOS transistors M3 and M4. Transistor M3 is diode-connected and transistor M4 is controlled by the drive voltage Vin of the output stage. The gate of transistor M2 is connected to the output of an operational amplifier 7. The inverting input of amplifier 7 is connected to terminal 6, and the non-inverting input is connected to the node N between transistors M3 and M4. With this construction, amplifier 7 drives transistor M2 such that the voltage at terminal 6 equals the voltage at node N. Transistors M1 and M3 act as a current mirror, wherein transistor M1 replicates the current of source 4 with an amplification factor depending on the W/L ratios of transistors M1 and M3. An external high-value bootstrap capacitor C is connected between terminals 5 and 6. This bootstrap capacitor C serves to provide the high-side transistor M1 with enough gate voltage Vg, so that the output voltage may reach the supply voltage +Vcc in any load conditions. Terminal 5 is coupled to line +Vcc through a diode Dl and an NPN transistor Q1. The base of transistor Q1 is coupled to line +Vcc through a current source 8 and to terminal 6 through a Zener diode DZ1. Figure 1B illustrates the operation of the bootstrapped output stage of figure 1A. The output voltage, at terminal 6, is shown at maximum swing, i.e. it varies between the two supply voltages -Vcc and +Vcc. When the output voltage 6 reaches its lowest value -Vcc (transistor M1 is off and transistor M2 is on), capacitor C charges substantially up to the Zener voltage Vz1 of diode DZ1 through diode D1 and transistors Q1 and M2. Zener voltage Vz1, which substantially corresponds to the maximum gate-source voltage of transistor M1, is chosen such that transistor M1 is suitably driven in full load conditions. When the output voltage 6 reaches its highest value +Vcc (transistor M1 is on and transistor M2 is off), the bootstrap voltage 5 is equal to the output voltage (+Vcc), plus the voltage across capacitor C. Since capacitor C, of a high value, hardly discharges, the bootstrap voltage 5 reaches a value substantially equal to +Vcc + Vz1. As shown by hatched areas, the gate voltage Vg of transistor M1 varies between the output voltage 6 and the bootstrap voltage 5, depending on the load conditions. For example, in full load conditions, the gate voltage Vg may be 10 volts higher than the output voltage, while, in no-load conditions, the gate voltage Vg may only be 2 volts higher. In this example, the Zener voltage Vz1 would be chosen above 10 volts. A problem of such an output stage arises in applications where the supply voltage is not regulated. The supply voltage may then unpredictably reach a value close to the breakdown voltage of the components of the amplifier. Although the supply voltage is then still at an acceptable value, the gate voltage Vg of transistor M1 will exceed the supply voltage and cause the destruction of components, for example of transistor M4. Therefore, a large security margin must be taken for the supply voltage, resulting in a power loss of the amplifier. Figure 2 shows a conventional solution for reducing the supply voltage security margin. All the elements of figure 1A, except for capacitor C, are integrated on the same chip 1. An external circuit 9 is used to limit the voltage applied to bootstrap terminal 5. Capacitor C is no longer connected to bootstrap terminal 5. Instead, it is connected to supply line +Vcc through a diode D2. The voltage at terminal 5 is set by the emitter of a bipolar transistor T whose collector is connected to a node A between capacitor C and diode D2. The base of transistor T is coupled to GND through a Zener diode DZ2 and to the collector of transistor T through a bias resistor R. With this construction, when the voltage at node A exceeds the Zener voltage Vz2 of diode DZ2, transistor T limits the voltage at terminal 5 to the Zener voltage Vz2. The gate voltage Vg of transistor M1 will therefore always be below Zener voltage Vz2. Zener voltage Vz2 is preferably chosen close to the circuit's breakdown voltage, in order to obtain maximum power from the amplifier. However, the Zener voltage Vz2 varies with variations of process and temperature. This makes it difficult to accurately control the maximum bootstrap voltage, whereby a security margin is still necessary for the supply voltage. This security margin is however smaller than that needed in the circuit of figure 1A. Another drawback of the circuit of figure 2 is that the bootstrap capacitor C is practically directly connected to supply line +Vcc, which will cause pop-noise on terminal 6 at power-on. In the construction of figure 1A, several measures can be taken to cancel the pop-noise (for example, pulling down the base of transistor Q1 at power-on), but these measures are inoperative in the construction of figure 2. JP-A-60152108 discloses an amplifier having a capacitor bootstrapped output stage and supply voltage sensing means for protecting the stage against overvoltage by pulling down the base of a high-side output transistor when a supply voltage surge is sensed. An object of the present invention is to provide a bootstrapped amplifier stage which reduces the security margin for the supply voltage. Another object of the present invention is to provide such an amplifier stage wherein pop-noise can be cancelled. In order to achieve this object, the present invention provides an amplifier output stage having an output transistor connected to a high supply voltage and a bootstrap terminal coupled to a control terminal of the output transistor through control means, the stage comprising a capacitor arranged between the bootstrap terminal and the output of the stage for elevating the voltage at the bootstrap terminal above the high supply voltage, and means for limiting the voltage at the bootstrap terminal to a predetermined threshold, wherein the means for limiting directly act on the control terminal of the output transistor to reduce the conductivity of the output transistor when the voltage at the bootstrap terminal exceeds the threshold. According to an embodiment of the present invention, the means for limiting the voltage at the bootstrap terminal comprise a dividing bridge connected between the bootstrap terminal and a low supply voltage, and a transistor driven by the output of the dividing bridge and coupled between the control terminal of the output transistor and the low supply voltage. According to an embodiment of the present invention, said transistor driven by the output of the dividing bridge is coupled to the low supply voltage through a source of a reference voltage. The foregoing and other objects, features and advantages of the present invention will be more readily understood and apparent from the following detailed description of illustrative embodiments according to the invention, which should be read in conjunction with the accompanying drawings, but not limited by them. Figures 1A to 2, which have been previously described, are intended to disclose the state of the art and the related problems, and Figure 3 partially shows an embodiment of an amplifier with a clamping circuit according to the invention. For sake of clarity, same elements are designated by same reference characters in the different figures. Moreover, only those elements which are necessary for understanding the invention have been shown in the figures. According to the present invention, the voltage between the bootstrap terminal of an amplifier and the negative supply terminal is detected for limiting the gate voltage of the high-side output transistor of the amplifier. This solution is illustrated in figure 3 which shows an embodiment of a power amplifier associated to a clamping circuit according to the present invention. In figure 3, only the output stage of the amplifier has been shown. This output stage is similar to that of figure 1A. A feature of the present invention is that the gate of the high-side transistor M1 is associated to a clamping circuit 10 comprising a bipolar transistor Q2, a reference voltage source 11, and a dividing bridge including resistors R1 and R2 connected in series between the bootstrap terminal 5 and the negative supply terminal 3. The collector of transistor Q2 is connected to the gate of transistor M1 and its emitter is coupled to the negative supply terminal 3 through source 11. The base of transistor Q2 is connected to the middle point of the dividing bridge. Thus, the bootstrap voltage at terminal 5 is continuously compared through the dividing bridge R1, R2 to the constant reference voltage Vref provided by source 11. As soon as the bootstrap voltage exceeds a threshold set by voltage Vref and the dividing bridge, transistor Q2 turns on and the voltage at the gate of transistor M1 decreases, causing a decrease of the voltage at terminal 6, thus of the bootstrap voltage at terminal 5. The bootstrap voltage decreases until transistor Q2 turns off again. Therefore, the gate voltage Vg of transistor M1 is regulated to a value such that the bootstrap voltage remains equal to the threshold set by reference voltage Vref and the dividing bridge R1, R2. This threshold, equal to voltage Vref divided by the ratio of bridge R1, R2, is set to the desired value by appropriately selecting the values of resistors R1 and R2, according to voltage Vref. The reference voltage source 11 will be accurate and temperature compensated to make the regulation of the bootstrap voltage particularly efficient, whereby the security margin for the supply voltage may be reduced. It is possible, in the invention, to use an accurate reference source, such as a bandgap reference source, because the reference voltage Vref may have any low value. With the clamping circuit according to the invention, the bootstrap capacitor C is connected as in figure 1A, whereby any conventional measure for reducing pop-noise can be taken. When the bootstrap voltage is lower than its threshold, transistor Q2 is off. Thus, the power consumption of the clamping circuit 10 according to the invention is advantageously limited to the periods where the clamping circuit is active. Preferably, clamping circuit 10 is integrated with the amplifier. Thus, only capacitor C is a discrete component. Many alternatives and modifications of the present invention will appear to those skilled in the art. In particular, each of the described components may be replaced by one or several elements achieving the same function. Moreover, the selection of the values of the resistors and of the capacitor and the selection of the components (transistor, current source, voltage source) can be readily carried out by those skilled in the art depending on the desired operating characteristics.

Claims: An amplifier output stage (1) having an output transistor (M1) connected to a high supply voltage (+Vcc) and a bootstrap terminal (5) coupled to a control terminal (Vg) of said output transistor through control means (4), said stage comprising a capacitor (C) arranged between said bootstrap terminal and an output (6) of said stage for elevating the voltage at said bootstrap terminal above said high supply voltage, and means (10) connected to and directly acting on said control terminal of said output transistor to reduce the conductivity of said output transistor, characterized in that said means limit said voltage at said bootstrap terminal to a predetermined threshold as soon as said voltage at said bootstrap terminal exceeds said threshold. The amplifier output stage according to claim 1, wherein the means (10) for limiting the voltage at the bootstrap terminal (5) comprise: a dividing bridge (R1, R2) connected between the bootstrap terminal and a low supply voltage (-Vcc), and a transistor (Q2) driven by the output of the dividing bridge and coupled between the control terminal of the output transistor (M1) and the low supply voltage. The amplifier output stage according to claim 2, wherein said transistor (Q2) driven by the output of the dividing bridge (R1, R2) is coupled to the low supply voltage through a source (11) of a reference voltage (Vref).

Inventors: ELANGO PAKRISWAMY, LOH GEE-HENG, ELANGO, PAKRISWAMY, LOH, GEE-HENG
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS PTE LTD.
Application year: 1997
Main classification: H03F1
IPC codes: H03F3, H03F1