MOS transistors circuit having a transformer/data interface function

Abstract: The invention relates to a MOS transistors substitutive circuit having a transformer/data interface function, in particular for ISDN networks, comprising first (11a) and second (11b) power supply/transmitter blocks, the first power supply/transmitter block (11a) being connected between a voltage reference (V) and a first data interface (RX), and the second power supply/transmitter block (11b) being connected between a ground potential reference (GND) and a second data interface (TX), both power supply/transmitter blocks being connected to a supply voltage reference (VDD). The MOS transistors substitutive circuit according to the invention comprises first (12) and second (12') MOS transistor pairs connected to the voltage reference (V), the MOS transistors being diode configured and held in their saturation range, so as to have a high A.C. impedance and virtually zero D.C. impedance, thereby minimizing power dissipation through the substitutive circuit. The invention also concerns a control and driving switch configuration for a network termination of at least first (11) and second (11') MOS transistors substitutive circuits according to the invention, operating respectively in a first condition ("normal condition") of operation of the network termination characterized by the presence of the polarity reverse control signal (Scrp), and a second condition ("RM emergency condition") of operation of the network termination characterized by the absence of the polarity reverse control signal (Scrp). The control configuration selects the voltage reference being applied to the power supply/transmitter blocks.

Description: Field of the Invention This invention relates to a MOS transistors substitutive circuit having a transformer/data interface function, particularly for ISDN networks, and corresponding control and driving switch configuration. Specifically the invention relates to a MOS transistors substitutive circuit having a transformer/data interface function, particularly for ISDN networks, which circuit comprises first and second power supply/transmitter blocks, said first power supply/transmitter block being connected between a voltage reference and a first data interface, and said second power supply/transmitter block being connected between a ground potential reference and a second data interface, said first and second power supply/transmitter blocks being further connected to a supply voltage reference. The invention also relates to a control and driving switch configuration for substitutive transformer/data transmitter circuits in a network termination, in particular ISDN network terminations, said network termination including first and second converters connected to a ground potential reference, said first converter delivering a supply voltage and an emergency voltage and said second converter delivering a remote supply voltage. The invention particularly, but not exclusively, concerns an ISDN network termination, and the description that follows will make reference to that application for simplicity of illustration. Background Art As is well known, technological advancements in the telephone field have made it necessary to provide telephone terminal units with additional functions. An important additional function is, besides voice transmission, the transmission of information relating to new products and/or services, such as facsimile operations, video communications, network interconnections, etc.. The transmission of data by a telephone terminal unit may utilize special networks. One example of a well known and widely utilized network is the ISDN (Integrated Services Digital Network), originating by natural evolution from the traditional telephone network and employing the same standard cables. This compatibility of transmission with the traditional telephone network allows the ISDN network to use the so-called telephone loops, which are advantageously available throughout the territory. In addition, the ISDN network is to European standard, having a transmit rate of 64 kbit/sec; the ISDN network allows two talk channels plus a control and service channel to be sent over the same line, which channels can be either used by two telephone sets, or one telephone set and a facsimile, or one telephone set and a PC (Personal Computer). Shown by way of example in Figure 1 is a block diagram for basic access to the ISDN network. This diagram is also shown in Figure 2, in greater detail. The following main blocks can be distinguished in these figures: LT -- line termination; NT -- network termination; TE -- terminal apparatus; TA -- terminal adapter. Also shown in Figure 1 are first U, second S and third R reference points, whereat special interface circuits are connected, as detailed in Figure 2 for the references U and S only. In particular, the line termination LT provides for power supply in the remote mode to the network termination NT, and in an emergency condition known in the art as RM (Restricted Mode), for a terminal apparatus TE as well. Furthermore, the line termination LT allows signal data DS to be transmitted and received in suitable formats, such as the 2B1Q or 4B3T formats, through the interface circuits of the reference point U. The terminal adapter TA, connected in the reference point R, allows apparatus designed for different data transmission modes, usually commercially available apparatus, to be also connected to the network termination NT. The network termination NT is connected to the line termination LT by a two-wire telephone loop, whereby the network termination NT can be powered from the line termination LT and can exchange with it data DS simultaneously in either directions. The network termination NT is provided with a DC/DC converter CONV1 capable of delivering a supply voltage VDD, typically of 5V, to the interface circuits at the reference points U and S, as well as an emergency voltage Vem. The emergency voltage Vem, of about 40V, can only be used in an RM emergency condition to power the terminal apparatus TE, with some suitable constraints. Such terminal apparatus TE are normally powered from an AC/DC converter CONV2 provided at the network termination NT and capable of powering up to eight terminal apparatuses TE, according to the standard applied. Under normal operation conditions, the emergency voltage Vem is disconnected by means of a first switch arrangement SW, shown in Figure 2, which is closed at the AC/DC converter CONV2. As shown in detail in Figure 2, the network termination NT has two input terminals A, B and four output terminals A', A'' and B', B'', two for each transformer of the interface circuit at the reference point S, as previously shown schematically in Figure 1. The output terminals A', A'' and B', B'' provide for remote power supply and data transmission through a supply/data transmission block BT comprising a DC/DC converter CONV3, a transmit block TX', and a receive block RX', so as to communicate with the terminal apparatus TE. The transmit and receive blocks, TX', RX' are schematically represented in Figure 2 by simple transformers serving to receive the power supply and allow of the data, present in the transmit and receive blocks TX', RX', conversion. In particular, it should be noted that power to the terminal apparatus TE is supplied from the interface circuits at the reference point S by means of the transformers, shown schematically in Figure 2, which are also utilized for exchanging the signal data DS. These transformers allow a virtually zero DC voltage drop to be obtained, and have an AC impedance which is a function of load and the winding ratio of the transformer. In addition, the supply to the terminal apparatus TE under RM emergency conditions is controlled through the switches SW. The combination of the transformers in the interface circuits at the reference point S and the switches SW controlling the supply to the terminal apparatus TE form a transformer/data interface/switch circuit for effecting a polarity reversal CT according to the prior art. The use of transformers, for powering or effecting the exchange of signal data DS at the interface circuits, is specially convenient from the standpoint of energy dissipation. Minimizing energy dissipation is highly important under RM emergency conditions; in such circumstances, in fact, no mains supply would be available, and the available power would be limited to the small power that the DC/DC converter at the interface circuits of the reference point U can draw on the line. Examples of circuits which employ such transformers are described in European Patents No. 0 160 411 to Northern Telecom Limited. and No. 0 639 021 and No. 0 590 242 to DeTeWe - Deutsche Telephonwerke Aktiengesellschaft & Co.. However, these transformers must be designed to meet specific applicational requirements, thereby producing a manufacturing cost. Also known is to use circuits including active components to provide equivalent coils in place of the transformers. Examples of such circuits are described in US Patents No. 3,649,769 to Pest, No. 4,004,104 to Picandet et al., No. 3,943,432 to Colardelle et al., and No. 4,088,843 to Rogers et al.. The prior art active component circuits are less expensive than transformers. But they are unsatisfactory from the energy dissipation standpoint, and still require suitable switches for supply control. The underlying technical problem of this invention is to provide a transformer/data interface circuit emulating a transformer for an ISDN telephone line, which can transmit the data presented on the line, transmit and control the power supply to the terminal apparatus (reversal of current polarity or direction), and has suitable structural and functional features to afford reduced energy consumption and overcome the drawbacks that are still besetting the prior art devices. Summary of the Invention The idea of solution behind this invention is that circuits, comprising MOS transistors which operate in the saturation range, and are suitably configured as diodes through common resistors, substitutes the transformer/data interface/switch circuit comprising the combined transformers and power supply control switches as provided at the network termination in the prior art, so as to present a high A.C. impedance and virtually zero D.C. impedance, thus minimizing the overall dissipation of power by the network termination, and allowing the power supply to be controlled under any conditions of operation of the network termination, while effecting the reversal in the current direction. Based on this idea of solution, the technical problem is solved by a MOS transistors substitutive circuit having a transformer/data interface function as previously indicated and defined in the characterizing part of Claim 1. The problem is also solved by a control and driving switch configuration for substitutive transformer/data transmitter circuits in a network termination, as previously indicated and defined in the characterizing part of Claim 23. The control configuration selects the voltage reference to be applied to the power supply/transmitter blocks. The features and advantages of the substitutive transformer/data interface circuit and associated control and driving switch configuration according to the invention will be apparent from the following description of embodiments thereof, given by way of non-limitative examples with reference to the accompanying drawings. Brief Description of the Drawings In the drawings: Figure 1 shows a block diagram for basic access to the ISDN network according to the prior art; Figure 2 shows the diagram of Figure 1 in further detail; Figure 3 shows a block diagram of a network termination incorporating a control and driving switch configuration according to the invention; Figure 4 shows a substitutive transformer/data interface circuit according to the invention; Figure 5 illustrates in graphical form an international specification for the impedance values of the interface circuits incorporated to the substitutive circuit of Figure 4; Figure 6 shows in detail an improvement in the substitutive circuit of Figure 4, including reduced voltage drop MOS transistors for a suitable limitation on dissipated power; Figure 7 shows a further improvement in the detail of Figure 6, including additional components that make the substitutive circuit of Figure 4 independent from the temperature and unaffected by process variations or "spread"; Figures 8 and 9 are plots vs temperature of respective parameters of the network termination according to the invention. Detailed Description Referring to the drawings, specifically to Figure 3, generally and schematically shown at 1 is a network termination according to the invention, wherein the transmission of data is not illustrated. Figure 3 illustrates in particular a power supply distribution through the network termination 1, comprising first 2 and second 3 converters, specifically a DC/DC converter and an AC/DC converter. The architecture of the network termination 1 of Figure 3 may also be used for data transmission. The first DC/DC converter 2 is connected to a ground potential reference GND, and delivers a supply voltage VDD, e.g. of either 5V or 3.3V, and an emergency voltage Vem, typically of 40V, similar to the DC/DC converter CONV1 described above in connection with the prior art. The second AC/DC converter 3 is connected to the ground potential reference GND and issues a polarity reversal control signal Scrp and a remote supply voltage VR, typically of 48V, on a signal line BUS1. The first 2 and second 3 converters are also connected to a first RM emergency condition supply block 4 and a second normal condition supply block 5, respectively, comprising P-channel MOS or PMOS transistors. In particular, connected between the first DC/DC converter 2 and the first supply block 4 is a current limiter 6 which is set, for example, to a value in the 9mA to 11mA range, harmonizing with regulations. The first 4 and second 5 supply blocks are connected to a third normal condition supply block 7 and a fourth RM emergency condition supply block 8, respectively, which comprise N-channel MOS or NMOS transistors. The third 7 and fourth 8 supply blocks are also connected to the ground potential reference GND. In addition, the first 4 and fourth 8 supply blocks are connected directly to the signal line BUS1, while the second 5 and third 7 supply blocks are connected thereto through first 9 and second 10 logic inverters. Last, the second 5 and fourth 8 supply blocks are connected to a first data interface RX, and the first 4 and third 7 supply blocks are connected to a second data interface TX. The block RL, schematically shown in Figure 3 as being connected to the data interfaces RX and TX, represents an equivalent DC resistor of a power supply/data transmission receive block connected to these interfaces and needed by the terminal apparatus TE. In essence, the network termination 1 comprises first 11 and second 11' MOS transistors substitutive circuits having a transformer/data interface function, respectively comprising normal condition supply blocks 5, 7 and RM emergency condition supply blocks 4, 8. In particular, the emergency voltage Vem and remote supply voltage VR are respectively applied to the supply blocks 5, 7 and 4, 8 in a first condition of operation, referred to as the normal operation condition, and in a second condition of operation, referred to as the emergency condition, of the network termination 1. A MOS transistors substitutive circuit having a transformer/data interface function, according to the invention, is shown best in Figure 4. The substitutive circuit 11 comprises first 11a and second 11b power supply/transmitter blocks, which essentially correspond to the first supply block 4 in the RM emergency condition, or to the second supply block 5 in the normal condition, and to the fourth supply block 8 in the RM emergency condition, or the third supply block 7 in the normal condition, respectively. This substitutive circuit 11 is implemented by a first pair 12 of P-channel MOS or PMOS transistors, and a second pair 12' of N-channel MOS or NMOS transistors. In particular, the transistors of each pair 12, 12' draw the same DC current in the connection leads to the first RX and second TX data interfaces. In addition, the first 12 and second 12' MOS transistor pairs are easily constructed from basic components made available by conventional mixed technologies of the BCD type. The diagram of Figure 4 shows that either (respectively PMOS and NMOS) transistor pairs 12, 12' are diode connected through suitable connection resistors. In particular, the first transistor pair 12 of the first power supply/transmitter block 11a comprises first M1 and second M2 P-channel transistors which are connected to a voltage reference V corresponding either to the remote supply voltage VR or the emergency voltage Vem, according to the operation condition of the network termination whereto the substitutive transformer/data interface circuit 11 is incorporated. The first M1 and second M2 transistors are also connected to the first data interface RX, and have their gate terminals in common and connected to the respective drain terminals through first R1 and second R2 connection resistors. The drain terminals of the transistors M1 and M2 are connected to the first data interface RX through a suitable decoupling circuit 13 which comprises at least one cross-connection resistor 14 and suitable common mode inductors. The drain terminals of the transistors M1 and M2 are also connected to a voltage/current converter 15 through first C1 and second C2 decoupling capacitors, respectively, which capacitors are further connected to a reference voltage reference VREF through first R3 and second R4 bias resistors. The voltage/current converter 15 is connected between the supply voltage reference VDD and the ground potential reference GND, and further connected to the supply voltage reference VDD via first 16 and second 17 current mirrors. The first 16 and second 17 current mirrors are connected to first 18 and second 19 amplifier circuits which are connected between the supply voltage reference VDD and the ground potential reference GND and connected, in parallel with each other, to a control terminal OUT whereat a voltage value equal to one half the supply voltage VDD is present. Also present between the output terminals A and B of the amplifier circuits 18 and 19 is an output voltage which is proportional to the voltage present on the line, limited to the conditions of the signal AC; this output voltage can be modulated by means of the current mirrors 16 and 17 and the resistors included in the amplifier circuits 18 and 19. Likewise, the second transistor pair 12' of the second power supply/transmitter block 11b comprises first M1' and second M2' N-channel transistors being connected between the ground potential reference GND and the second data interface TX and having their gate terminals in common and connected to the respective drain terminals through first R1' and second R2' connection resistors. The first M1' and second M2' transistors have their source terminals in common and connected, through a suitable sensing resistor Rgnd (unessential to the aim of the invention), to the ground potential reference GND, and have their drain terminals connected to first D1 and second D2 decoupling elements, e.g. two diodes, and connected to the second data interface TX via a suitable decoupling circuit 13' which comprises at least one cross-connection resistor 14' and suitable common mode inductors. The drain terminals of the transistors M1' and M2' are also connected, through the decoupling elements D1 and D2, to first 16' and second 17' current mirrors which are further connected to the supply voltage reference VDD and decoupled from the second data interface TX by means of first C1' and second C2' decoupling capacitors. The decoupling elements D1 and D2 operate in particular supply conditions of the substitutive circuit 11. The first C1' and second C2' decoupling capacitors are also connected to the ground potential reference GND through third 20 and fourth 21 current mirrors. The first 16' and second 17' current mirrors are connected to both the third 20 and fourth 21 current mirrors in crossed manner, thereby forming a "bridge" connection. The first 16' and second 17' current mirrors are also connected to a buffer circuit 22 through first R5 and second R6 decoupling resistors, respectively, and connected to a voltage/current converter 15' which has first C and second D input terminals. The buffer 22 is connected between the supply voltage reference VDD and the ground potential reference GND, and connected to the reference voltage reference VREF. In particular, the buffer 22 sets the output reference voltage VREF for the current mirrors 16', 17', 20 and 21. The decoupling resistors R5 and R6 will then establish an impedance between the current mirrors 17', 21 and 16', 20, respectively, suitable to provide, in a condition of AC current, a higher impedance value than the resistance value of the cross-connection 14' in the decoupling circuit 13'. The buffer 22 thus will, in cooperation with the decoupling resistors R5 and R6, set the working voltage of the current mirrors without altering the line impedance value across the cross-connection resistor 14'. In particular, the reference voltage VREF is one half the supply voltage VDD. The operation of the MOS transistors substitutive circuit according to the invention in the presence of a DC supply signal and a differential type of data signal will now be described. Data Transmission Function A differential data signal, specifically a voltage, presented across the cross-connection resistor 14 of the decoupling circuit 13 associated with the first data interface RX, will "see" a high impedance through the transistors M1 and M2, and especially through the parallel connection of the resistors R1, R2, R3 and R4. This differential data signal then travels through the decoupling capacitors C1 and C2 to the voltage/current converter 15, where it is converted to a current. The differential current data signal then goes through the current mirrors 16 and 17 to be ultimately converted back to a voltage by the amplifier circuits 18 and 19. In this way, the differential data signal associated with the first data interface RX will again be presented, suitably amplified, at the output terminals A and B of the amplifier circuits 18 and 19. In particular, it should be noted that the final amplification value of the differential data signal can be programmed by varying the ratio of the current mirrors 16, 17 and the resistance values used. In a dual manner, a differential data signal, such as a voltage, at the input terminals C and D of the voltage/current converter 15' in the second power supply/transmitter block 11b is converted to a current and transmitted to the bridge configuration of the current mirrors 16', 17', 20 and 21. In particular, if the differential data signal converted to a current has a first polarity, it is input, through the decoupling capacitor C1' connected to the first current mirror 16', to a first terminal of the cross-connection resistor 14' of the decoupling circuit 13' associated with the second data interface TX, to then loop back to ground through the decoupling capacitor C2' and the fourth current mirror 21. Thus, the second power supply/transmitter block 11b can be said to replicate, at the second data interface TX, the differential data signal presented to the input of the voltage/current converter 15'. This differential data signal is output with said first polarity. Otherwise, if the differential current data signal has a second polarity, in particular a reversed polarity form the first, it is input, through the decoupling capacitor C2' connected to the second current mirror 17', to a second terminal of the cross-connection resistor 14' of the decoupling circuit 13' associated with the second data interface TX, to then loop back to ground through the decoupling capacitor C1' and the third current mirror 20. Accordingly, the connection to the cross-connection resistor 14' is the reverse from the previously discussed differential data signal having a first polarity, and the second power supply/transmitter block 11b will replicate the differential data signal, presented to the input of the voltage/current converter 15' and having said second polarity, at the second data interface TX. Transformer Function In the instance of a DC supply, a corresponding DC supply current will be flowing through the transistors M1, M2 toward the decoupling circuit 13, up to the first data interface RX. In a DC supply situation, the transistors M1 and M2 would offer, in fact, a low resistance to the passage of said supply current. The mid-point terminal of the interface transformers in the first data interface RX is suitably connected to the mid-point terminal of the interface transformers in the second data interface TX, thereby allowing the supply current to cross the decoupling circuit 13'. The equivalent resistance of this connection is schematically represented by the block RL in Figure 4. The supply current path then loops back to ground through the transistors M1' and M2'. The MOS transistors substitutive circuit of the invention replaces, therefore, the transformers associated with the interface at the reference point S in the prior art. Switch Function Reference will now be made to the control and driving switch configuration 100 shown schematically in Figure 3. In the normal operation condition, i.e. for a remote supply voltage VR of about 48V, this voltage is crossed through the first normal condition supply block 5 to the first data interface RX. It is then crossed to ground by the second data interface TX through the second normal condition supply block 7. Otherwise, in the absence of the remote supply voltage VR, the polarity reversal control signal Scrp on the signal line BUS1 will activate the emergency condition supply blocks 4, 8 (connected to the emergency voltage Vem of about 40V), and simultaneously deactivate the normal condition supply blocks 5, 7 by means of the inverters 9 and 10. In particular, this control on the supply distribution for the normal and emergency conditions is effected through the transistors of the substitutive circuits 11 and 11'. In fact, these transistors are either connected to the remote supply voltage VR outgoing from the AC/DC converter 3 or the emergency voltage Vem, to activate and deactivate operation of the first and second supply blocks 5, 7 in the normal operation condition, or operation of the first and second supply blocks 4, 8 in the RM emergency condition. The control and driving switch configuration, comprised of a pair of MOS transistors substitutive circuits according to the invention, thus replaces functionally the switches SW of the prior art. Advantageously in this invention, the resistances of the first R1 and second R2 connection resistors for the first pair of MOS transistors M1, M2 are identical (R1=R2). Likewise, the values of the first R1' and second R2' connection resistors for the second MOS transistor pair M1', M2' are identical (R1'=R2'). As such, any differential signal presented to the first RX and second TX data interfaces would be canceled at the common gate terminal of the respective MOS transistor pairs 12 and 12'. In principle, therefore, it would be unnecessary to use a filter capacitor between the common gate terminal and the source terminal of the transistors in the first 12 and second 12' pairs of MOS transistors. Such a filter capacitor may be used, however, in case of any mismatching of the resistors, in order to increase the output impedances of the MOS transistor pairs 12 and 12'. It should be noted that in the substitutive circuit 11 of this invention, even a differential signal on the line (to be regarded as similar to the signals presented to the first RX and second TX data interfaces) would fail to modulate the common gate terminal of the MOS transistor pairs 12 and 12'. These MOS transistor pairs 12 and 12' have, therefore, a high impedance to differential signals, which is equal to the combined output impedances of the MOS transistor pair, 12 or 12', under consideration. The output impedance gd of a single MOS transistor is given as: gd = 1/Rout = delta Id/delta Vds where: Rout is the equivalent output resistance of each MOS transistor; delta Id is the variation in the current flowing through the MOS transistor pairs 12 and 12'; delta Vds is the variation in the voltage across the MOS transistor pairs 12 and 12'. On the other hand, the DC current flowing through the transistor pairs 12 and 12' can easily be looped back within such diode-connected pairs. Under these conditions, the MOS transistors M1, M2, M1' and M2' operate in the saturation range, and the voltage Vgs=Vds will match the appropriate value, for the current present within the host system of the substitutive circuit 11 to be allowed to flow. In fact, a MOS transistor will be operating in the saturation range once the following relations are satisfied: |VGS| > |VT| |VDS| > |VGS| - |VT| where: VGS is the difference in voltage between the gate terminal and the source terminal of the MOS transistor; VT is the threshold voltage of the MOS transistor; VDS is the difference in voltage between the drain terminal and the source terminal of the MOS transistor. To conform with the regulations on interface circuits, specifically the interface circuit at point S, an overall impedance value Z must be in agreement with the graph of Figure 5. This graph is taken from Specification ITU-T I430 and fixes an impedance value of more than 2.5 kOhm in the frequency range of 20kHz to 1106kHz. In relation to the first power supply/transmitter block 11a of Figure 4, the overall impedance value Z across the drain terminals of the transistors M1 and M2 is given as: Z = R1+R2//Rout1+Rout2//R3+R4 where: Rout1 and Rout2 are the equivalent resistances of the transistors M1 and M2; This value should agree with the international specifications expressed by the graph of Figure 5. The impedance for the second power supply/transmitter block 11b can be similarly computed. It follows of necessity that the output impedance of the MOS transistors must be sufficiently high, which would occur when they operate in the saturation range. In the embodiment of Figure 4, the dissipated power Pdiss for the MOS transistor pairs 12, 12' is to be computed, for a given supply current referred to hereinafter as the loop current ILOOP flowing through the substitutive circuit 11, as follows: (VdsPch + VdsNch) x ILOOP = Pdiss where: VdsPch is the difference in voltage between the drain and source terminals of the PMOS transistors in the first pair 12; and VdsNch is the difference in voltage between the drain and source terminals of the NMOS transistors in the second pair 12'. In view of that the MOS pairs operate in the saturation range and are in a diode configuration, it follows that the voltage difference Vds between the drain and source terminals will be the same as the voltage difference Vgs between the gate and source terminals. The latter takes a value equal to the threshold voltage value VT plus an overdrive voltage dependent on the current ILOOP. For example, in a practical situation simulated by the Applicant for a manufacturing process with mixed technology of the BCD type, the voltage Vds = Vgs + Voverdrive in an RM emergency condition (ILOOP ≅ 12mA) is about 2V for the pair 12' and about 1.6V for the pair 12, at room temperature; therefore, the power dissipated through the substitutive circuit 11 at room temperature is of 43mW. The effect of temperature on the threshold voltage VT should be added to this value. A basic requirement of the substitutive circuit 11 with transformer function is that the dissipated power Pdiss be minimized. It is therefore necessary to keep the voltage difference Vds between the drain and source terminals of the MOS transistors employed as low as congruous with the above impedance requirements. It readily follows, from the working conditions in the saturation range set by relations (1.1) and (1.2), that it is possible, in theory, to reduce the voltage difference Vds between the drain and source terminals to a value: Vds = Vgs - VT where: Vds is the voltage difference between the drain and source terminals of the MOS transistors employed; Vgs is the voltage difference between the gate and source terminals of the MOS transistors employed; and VT is the threshold voltage of the MOS transistors employed. A first action toward minimizing the power dissipated through the MOS pairs is to extract or inject an appropriate compensation current Icom (homogeneous with the variations in the connection resistors R1, R2 and R1', R2') so as to obtain a constant voltage drop across these connection resistors R1,R2 and R1', R2' forming the diode connection, which should then be subtracted from the voltage Vds, as shown schematically in Figure 6 in relation to the first 12 and second 12' diode-configured transistor pairs only. This action can be easily implemented by having a suitable compensation current generator Gcom connected across the connection resistors R1, R2 and R1', R2'. In this way, however, it would be difficult to compensate for variation of the threshold VT of the transistors M1, M2 and M1', M2' with temperature, and it therefore becomes necessary to provide a safe margin voltage to maintain the MOS transistors employed within the saturation range. To obviate this, according to the invention, a MOS component of the same type as the transistors used in the PMOS pair 12 and NMOS pair 12' is advantageously provided, in series with the connection resistors R1, R2 and R1', R2' forming the diode connections of transistors M1, M2 and M1', M2'. Specifically, first M3 and second M3' compensation transistors are included, as schematically shown in Figure 7. The first compensation transistor M3 has its gate terminal connected to its drain terminal, and connected to the compensation current generator Gcom, its drain terminal being further connected to the common gate terminal of the first M1 and second M2 transistors in the pair 12 through a first matching resistor RA, and connected to the voltage reference V through a first match current generator GA; the transistor source terminal being connected to the connection resistors R1 and R2. In the same way, the second compensation transistor M3' has its gate terminal connected to its drain terminal, and connected to the compensation current generator Gcom, its drain terminal being further connected to the common gate terminal of the first M1' and second M2' transistors in the pair 12' through a second matching resistor RB, and connected to the ground reference GND through a second match current generator GB; the transistor source terminal being connected to the connection resistors R1' and R2'. Thus, the transistors M3 and M3' are in a diode configuration, and have a voltage drop which is virtually the same as VT. The detail schematic of the substitutive circuit 11 in Figure 7 illustrates a simplification which affords improved relative flexibility while leaving the foregoing concepts, on which the invention stands, unaltered. The additional resistors RA and RB and their associated current generators GA and GB allow the voltages across the connection resistors R1, R2 and R1', R2' to be modulated for optimum adjustment at the manufacturing stage of the substitutive circuit 11. Thus, the voltage Vds at the MOS transistor pairs 12 and 12' can be significantly reduced, resulting in a reduction of the power Pdiss dissipated through the substitutive circuit 11. Also, with the improved scheme of Figure 7, all the effects of temperature on the threshold voltage VT of the transistors employed are inherently canceled. By this expedient, even those variations or "spread" in the manufacturing process which are hard to remove, are inherently canceled, in favor of repeatability of the substitutive circuit 11 and the network termination 1 as a whole. The power dissipated through the pairs 12 and 12' after introducing the transistors M3 and M3', for a loop current ILOOP of 12mA, may be, for example: Pdiss = (VdsPch' + VdsNch') x ILOOP = (1.25+0.75)x12 = 24mW where: VdsPch' is the voltage difference between the drain and source terminals of the PMOS transistors in the first pair 12, as connected to the first transistor M3; and VdsNch' is the voltage difference between the drain and source terminals of the NMOS transistors in the second pair 12', as connected to the second transistor M3'. A reduction of 56% with respect to the simple diode-connection of the basic embodiment schematically shown in figure 4 is thus obtained. A further contribution to reducing the voltage drop Vds across each of the MOS transistor pairs 12, 12' may also come from a suitable dimensioning of the individual transistors M1, M2 and M1', M2' in the pairs 12 and 12'. As the geometries of these transistors are increased, and for a given loop current ILOOP, the voltage Vds can be decreased, while being careful, however, to keep the transistors M1, M2 and M1', M2' within their saturation range, for best compromise size/dissipated power. Figures 8 and 9 show plots versus temperature of the parameter expressing the voltage difference Vds between the drain and source terminals of the PMOS transistors in the first pair 12 and the NMOS transistors in the second pair 12', respectively, as obtained from a suitable simulation carried out by the Applicant under different conditions tied to process variations. The substitutive circuit 11 of this invention allows the gains of both the first RX and the second TX data interface to be matched in a flexible manner compared to the transformers used in the prior art. In fact, this change in gain can be achieved by merely varying the resistances of the resistors used. In addition, the reversal of polarity (in the RM or restricted mode emergency condition) is provided by active components over a different current path, without additional relays. Finally, the substitutive circuit 11 and the control and driving switch configuration 100 of this invention afford control over the loop current ILOOP and a limitation on the latter, by the added provision of dedicated circuits, such as the sensing resistor Rgnd, within the device. In conclusion, the foregoing expedients affecting both the first pair 12 of PMOS transistors and the second pair 12' of NMOS transistors can provide a low voltage drop, high transistor output impedance, and low current consumption by using components of the MOS type, thereby ensuring a low dissipated power which is constant with temperature and unaffected by process variations. Further advantages of the substitutive circuit 11 and the control and driving switch configuration 100 of this invention are: reduced manufacturing costs, in view also of a homogeneous assembly with all the other dedicated circuits; ready elimination of any electromechanical relays for polarity reversal, and replacement thereof with active components, specifically MOS transistors; possible introduction of additional functions, such as matching the gains of the first RX and second TX data interfaces.

Claims: A MOS transistors substitutive circuit having a transformer/data interface function, in particular for ISDN networks, comprising first (11a) and second (11b) power supply/transmitter blocks, said first power supply/transmitter block (11a) being connected between a voltage reference (V) and a first data interface (RX), and said second power supply/transmitter block (11b) being connected between a ground potential reference (GND) and a second data interface (TX), said first and second power supply/transmitter blocks (11a,11b) being further connected to a supply voltage reference (VDD), characterized in that the MOS transistors substitutive circuit comprises first (12) and second (12') MOS transistor pairs respectively connected to said voltage reference (V) and said ground potential reference (GND), said MOS transistors being diode configured and held in their saturation range, so as to have a high A.C. impedance and virtually zero D.C. impedance, thereby minimizing power dissipation through said substitutive circuit. A MOS transistors substitutive circuit according to Claim 1, characterized in that said voltage reference (V) corresponds either to a remote supply voltage (VR) or to an emergency voltage (Vem), respectively in a first condition of operation ("normal condition") characterized by the presence of a polarity reverse control signal (Scrp), and in a second condition ("RM emergency condition") characterized by the absence of the polarity reverse control signal (Scrp). A MOS transistors substitutive circuit according to Claim 2, characterized in that the transistors (M1,M2 - M1',M2') in said first and second pairs (12,12') are diode connected through respective connection resistors (R1,R2 - R1',R2') and are adapted to cross the same D.C. current which is flowing through the connection leads to the first and second data interfaces (RX,TX). A MOS transistors substitutive circuit according to Claim 3, characterized in that said second power supply/transmitter block (11b) comprises the first (M1') and the second transistor (M2') of the second pair (12'), said transistors having their gate terminals connected in common and to the respective drain terminals through the first (R1') and second connection resistors (R2') of the second pair (12'), their source terminals connected to a ground potential reference (GND), and their drain terminals connected to the second data interface (TX). A MOS transistors substitutive circuit according to Claim 4, characterized in that said second power supply/transmitter block (11b) further comprises first (16'), second (17'), third (20) and fourth (21) current mirrors forming a bridge connection between the supply voltage reference (VDD) and the ground potential reference (GND); in particular, said first and second current mirrors (16',17') being connected to the supply voltage reference (VDD) and to the third and fourth current mirrors (20,21), themselves connected to the ground potential reference (GND). A MOS transistors substitutive circuit according to Claim 5, characterized in that the first and fourth current mirrors (16',21) are connected to the first transistor of the second pair (M1') through a first decoupling element (D1) and decoupled from the second data interface (TX) by a first decoupling capacitor (C1'), while the second and third current mirrors (17',20) are connected to the second transistor of the second pair (M2') through a second decoupling element (D2) and decoupled from the second data interface (TX) by a second decoupling capacitor (C2'), said decoupling elements (D1,D2) being utilized under particular conditions of power supply to the MOS transistors substitutive circuit. A MOS transistors substitutive circuit according to Claim 5, characterized in that said second power supply/transmitter block (11b) further comprises a buffer (22) connected to the first and third current mirrors (16',20) through a first decoupling resistor (R5), and to the second and fourth current mirrors (17',21) through a second decoupling resistor (R6). A MOS transistors substitutive circuit according to Claim 7, characterized in that said buffer (22) is connected between the supply voltage reference (VDD) and the ground potential reference (GND), and connected to a reference voltage reference (VREF), thereby being adapted to set an output reference voltage (VREF) for the current mirrors (16',17',20,21), while the decoupling resistors (R5,R6) are adapted to set a suitable impedance for an A.C. signal presented to the second data interface (TX). A MOS transistors substitutive circuit according to Claim 5, characterized in that said second power supply/transmitter block (11b) further comprises a voltage/current converter (15') having first and second input terminals (C,D) and being connected to said first and second current mirrors (16',17'). A MOS transistors substitutive circuit according to Claim 3, characterized in that said first power supply/transmitter block (11a) comprises the first (M1) and the second transistor (M2) of the first pair (12), said transistors having their gate terminals connected in common and to the respective drain terminals through the first (R1) and the second connection resistor (R2) of the first pair (12), their source terminals connected to the voltage reference (V) and their drain terminals connected to the first data interface (RX). A MOS transistors substitutive circuit according to Claim 10, characterized in that said first power supply/transmitter block (11a) further comprises a voltage/current converter (15) connected between the supply voltage reference (VDD) and the ground potential reference (GND), and connected to the drain terminals of the transistors (M1,M2) through first (C1) and second (C2) decoupling capacitors, respectively, which are themselves connected to a reference voltage reference (VREF) through first (R3) and second (R4) bias resistors. A MOS transistors substitutive circuit according to Claim 11, characterized in that said voltage/current converter (15) is further connected to the supply voltage reference (VDD) through first (16) and second (17) current mirrors of the first power supply/transmitter block (11a). A MOS transistors substitutive circuit according to Claim 12, characterized in that said first and second current mirrors (16,17) of the first power supply/transmitter block (11a) are connected to first (18) and second (19) amplifier circuits, themselves connected between the supply voltage reference (VDD) and the ground potential reference (GND) and connected, in cascade with each other, to a control terminal (OUT) of said first power supply/transmitter block (11a). A MOS transistors substitutive circuit according to Claim 13, characterized in that said first and second amplifier circuits (18,19) have respective output terminals (A,B); on said terminals there being present an A.C. signal output voltage which is proportional to the line voltage at the first data interface (RX) and suitably modulable by means of said first and second current mirrors (16,17) and of resistors included in the amplifier circuits (18,19). A MOS transistors substitutive circuit according to Claim 3, characterized in that the values of the first (R1,R1') and second (R2,R2') connection resistors are the same for the first and second transistor pairs (M1,M2 and M1',M2'), respectively, thereby being adapted to cancel, at the common gate terminal of the respective transistor pairs (12,12'), any differential signal at the first and second data interfaces (RX,TX), said transistor pairs (12,12') being adapted to offer, therefore, a high impedance to differential signals. A MOS transistors substitutive circuit according to Claim 3, characterized in that it further comprises a compensation current generator (Gcom) connected across the connection resistors (R1,R2-R1',R2') for extracting and injecting, respectively, a compensation current (Icom) homogeneous with the variation of said connection resistors (R1,R2-R1',R2') and, accordingly, for obtaining a constant voltage drop across said connection resistors (R1,R2-R1'-R2') effective to further reduce the power dissipated through said substitutive circuit. A MOS transistors substitutive circuit according to Claim 16, characterized in that it comprises a first compensation transistor (M3) connected in series with the connection resistors (R1,R2) connected to the transistors in the first pair (M1,M2) and to the voltage reference (V), and having its gate terminal connected to its drain terminal and to the compensation current generator (Gcom), its drain terminal further connected to the common gate terminal of the transistors (M1,M2) in the first pair (12) through a first match resistor (RA), and its source terminal connected to said connection resistors (R1,R2), and a second compensation transistor (M3') connected in series with the connection resistors (R1',R2') connected to the transistors in second pair (M1', M2') and to the ground potential reference (GND), and having its gate terminal connected to its drain terminal and to the compensation current generator (Gcom), its drain terminal further connected to the common gate terminal of the transistors (M1',M2') in the second pair (12') through a second match resistor (RB), and its source terminal connected to said connection resistors (R1',R2') connected to the transistors in the second pair (M1', M2'), said compensation transistors (M3,M3') being thus diode configured and having a voltage drop which virtually equals a MOS transistor threshold voltage (VT), so as to compensate the threshold voltages of the transistors employed, with respect to temperature and process variations. A MOS transistors substitutive circuit according to, Claim 17, characterized in that the first compensation transistor (M3) has its source terminal further connected to the voltage reference (V) through a series of said first match resistor (RA) and a first match current generator (GA), and that the second compensation transistor (M3') has its source terminal further connected to the ground potential reference (GND) through a series of said second match resistor (RB) and a second match current generator (GB), said current generators (GA,GB) thus being adapted to allow the voltages across the connection resistors (R1,R2-R1',R2') of the first and second pairs (12,12') to be modulated through the respective match resistors (RA,RB) for optimum adjustment, at the manufacturing stage, of said substitutive circuit, a further reduction of the dissipated power, and inherent compensation of the effects of temperature and process variations on the threshold voltage (VT) of the transistors employed. A MOS transistors substitutive circuit according to Claim 1, characterized in that said first and second pairs (12,12') comprise MOS transistors of a first and a second type (PMOS,NMOS), respectively. A MOS transistors substitutive circuit according to Claim 19, characterized in that said first and second transistor pairs (12,12') can be constructed from basic components available from conventional mixed technologies of the BCD type. A MOS transistors substitutive circuit according to Claims 17 and 19, characterized in that said first and second compensation transistors (M3,M3') are respectively of the same type as the transistors (M1,M2-M1',M2') in the first and second pairs (12,12'). A MOS transistors substitutive circuit according to Claim 4, characterized in that the source terminals of said first (M1') and second (M2') transistors in the second pair (12') are connected to the ground potential reference (GND) through a sensing resistor (Rgnd). A control and driving switch apparatus for substitutive transformer/data transmitter circuits in a network termination, in particular for an ISDN network, said network termination including first (2) and second (3) converters connected to a ground potential reference (GND), said first converter (2) adapted to deliver a supply voltage (VDD) and an emergency voltage (Vem), and said second converter (3) adapted to deliver a remote supply voltage (VR), characterized in that the control and driving switch apparatus comprises at least first (11) and second (11') MOS transistors substitutive circuits according to any of the preceding claims, which circuits respectively are adapted to operate in a first condition of operation ("normal condition") of the network termination characterized by the presence of the polarity reverse control signal (Scrp), and a second condition of operation ("RM emergency condition") of the network termination characterized by the absence of the polarity reverse control signal (Scrp). A control apparatus according to Claim 23, characterized in that said first and second MOS transistors substitutive circuits (11,11') are connected to a signal line (BUS1) whereon is present a polarity reverse control signal (Scrp) which is generated by the second converter (3) of the network termination, and are connected to first and second data interfaces (RX,TX). A control apparatus according to Claim 24, characterized in that said first MOS transistors substitutive circuit (11) comprises first and second normal supply blocks (5,7), said first normal supply block (5) being adapted to receive said remote supply voltage (VR) from the second converter (3) and being connected to the signal line (BUS1) through a first logic inverter (9) and to the first data interface (RX), and said second normal supply block (7) being connected to the signal line (BUS1) through a second logic inverter (10), and connected to the second data interface (TX). A control apparatus according to Claim 25, characterized in that said second MOS transistors substitutive circuit (11') comprises first and second emergency supply blocks (4,8), said first emergency supply block (4) being adapted to receive said emergency voltage (Vem) from the first converter (2) through a current limiter (6), and being connected to said second normal supply block (7) and to the second data interface (TX), and said second emergency supply block (8) being connected to said first normal supply block (5) and to the first data interface (RX). A control apparatus according to Claim 26, characterized by that, in the first condition ("normal condition") of operation of the network termination, the remote supply voltage (VR) is present, which voltage is crossed through the first normal supply block (5) to the first data interface (RX), and from the second data interface (TX) to ground through the second normal supply block (7). A control apparatus according to Claim 27, characterized by that, in the second condition ("RM emergency condition") of operation of the network termination, the emergency voltage (Vem) is present, and the polarity reverse control signal (Scrp) present on the signal line (BUS1) enables the emergency supply blocks (4,8) and disables the normal supply blocks (5,7) through said first and second inverters (9,10).

Inventors: ANTONINI CARLO, CONSIGLIO PIETRO, LARI FERDINANDO, ANTONINI, CARLO, CONSIGLIO, PIETRO, LARI, FERDINANDO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1997
Main classification: H04M19
IPC codes: H04L12, H04M19, H04Q11