CHARGE PUMP CIRCUIT ARCHITECTURE

Abstract: A charge pump circuit having a fast rise time and reduced physical area is disclosed. The charge pump includes a plurality of stages having an non-uniform series of bootstrap capacitors. By using non-uniform capacitors at the various stages, charging rise time is enhanced while at the same time reducing the overall physical size of the charge pump.

Description: CHARGE PUMP CIRCUIT ARCHITECTURE Field of the Invention The present invention relates generally to charge pumps and, more particularly, to an improved charge pump circuit for use with semiconductor devices having enhanced rise time and reduced physical area. BACKGROUND OF THE INVENTION In semiconductor applications, a charge pump is used to increase a small input voltage (for example, Vcc) into the larger voltages that are passed to the word lines and bit lines of semiconductor memory devices. These voltages affect the reading and writing of data from/to the memory device. The voltage is increased by channeling the relatively small input voltage through a series of stages. The more stages a charge pump has, the greater the resulting output voltage. Rise time, or charge pump-up time (the amount of time necessary to convert the input voltage, Vcc, to the required output voltage) directly affects the time needed to read information from and write information to a particular byte of memory. Currently, charge pumps are constructed using several bootstrap capacitors having the same size (capacitance) C at each respective node of the charge pump. A bootstrap capacitor is defined as the capacitor connected to each respective node of a charge pump. Thus, to reduce rise time, the capacitance at each successive node is increased until the application defined speed requirement is met. with conventional charge pumps, by increasing the capacitance at each stage the time required to generate the necessary output voltage decreases. However, the rise time does not improve significantly with the increase of capacitance. The decrease in rise time reaches a limit that cannot be surpassed. Thus, with conventional charge pumps, there is a limit to the attainable rise time. As the required voltages for applications increases, the number of stages necessary to generate the higher output voltages also increases. Another drawback associated with conventional charge pumps is that with the increased number of stages, all having a common capacitance, the physical area taken up by the charge pump also increases. A further drawback associated with conventional charge pumps is that as the number of stages increases, the power required to drive the charge pumps also increases due to the increased number of capacitors present in the charge pump. Still a further drawback associated with conventional pumps is that as you increase the number of capacitors in a charge pump, the efficiency of the charge pump decreases. Thus, there is a need for a charge pump having reduced rise time while at the same time taking up less physical area on an integrated circuit chip. SUMMARY OF THE INVENTION The present invention solves the aforementioned and related drawbacks associated with conventional charge pumps. The present invention is directed to a novel charge pump circuit where each individual stage of the charge pump is characterized by having a non- uniform bootstrap capacitance value as compared with the other stages. By not having the same amount of capacitance present at each stage, the charge pump rise time is enhanced while at the same time requiring less physical area and less power than conventional charge pumps. These features are provided by a charge pump including input means for providing a signal; output means for delivering a modified signal and multiple stage means, connected between the input and output means which generate the modified signal. The multiple stage means also include a plurality of capacitance means, wherein each respective one of the capacitance means has a different, unique value. An advantage of the present invention is the ability to enhance the rise time as compared to conventional charge pumps. A feature of the present invention is that the charge pump according to the present invention requires less physical space than conventional charge pumps. Another feature of the charge pump of the present invention is that it requires less power than conventional charge pumps. Yet another feature of the charge pump of the present invention is that it is more efficient than conventional charge pumps. BRIEF DESCRIPTION OF THE DRAWINGS These and other advantages and features of the present invention will become apparent from the following description of the embodiments, taken in conjunction with the accompanying drawings, where like numbers represent like elements, in which: Figure 1 illustrates a conventional charge pump architecture. Figure 2 illustrates a schematic diagram of the charge pump according to the present invention. Figure 3 illustrates a partial schematic diagram showing two stages of the charge pump according to the present invention. Figure 4 is a graph representing charging time and speed characteristics between the charge pump according to the present invention and conventional charge pumps. Figure 5 is a graph representing voltage and speed characteristics between an eight stage charge pump according to the present invention and an eight stage conventional charge pump. Figure 6 is a graph representing physical area versus speed characteristics between the charge pump according to the present invention and a conventional charge pump. DETAILED DESCRIPTION OF THE EMBODIMENTS The present invention provides an improved charge pump circuit for use with semiconductor devices. The present invention comprises a charge pump circuit architecture wherein each stage of the charge pump includes a bootstrap capacitor having a non-uniform capacitance value. This is in contrast to conven¬ tional charge pumps having multiple stages, where the bootstrap capacitors have the same value. Figure 1 provides an illustration of a conventional charge pump. As shown, the conventional charge pump 10 has a number of stages (stage 1 - stage N) . The charge pump 10 has at its input, a voltage, Vcc which is transmitted through a diode 12 to a first node (node 1) including a first bootstrap capacitor 22 having a capacitance C. A second node (node 2) is connected to the first node (node 1) via diode 14 and also has a second bootstrap capacitor 24 having a capacitance C. The output of node 2 is then passed through a number of subsequent nodes, identical to previously described nodes 1 and 2, that also include a bootstrap capacitor having a capacitance value C that is identical to the capacitance value C present in nodes 1 and 2. Finally, the conventional charge pump has an output terminal, V out , also having a capacitor 30 having a total capacitance C oul which is defined as being the load capacitance (C : ) of the load connected to the output of the pump and a parasitic capacitance (C p ) inherent in the transmitting means of the conventional pump. As stated above, the bootstrap capacitance of the various nodes of the pump all have value C. With conventional charge pumps, when the rise time needs to be enhanced, all that is necessary is to make the bootstrap capacitor at each respective node larger. However, there are drawbacks to the continual increasing of the capacitances at each node: rise time ceiling; increased power requirements and reduced efficiency. The speed with which charge pumps operate is directly proportional to bootstrap coefficients, k's defined as: c ι (1) C i * C iΛ where C t is the capacitance of the present node and C i+1 is the capacitance of the next successive node. As discussed above, with conventional pumps, in order to decrease the charge pump up time you must increase the amount of capacitance at each successive node. However, when the capacitance at each successive node is increased, the only bootstrap coefficient value (k) that is increased is the bootstrap coefficient value of the last stage, k N . The other bootstrap coefficients k^k^ remain the same and are equal to 0.5 because all the capacitance values are equal as shown below: e % " °' 5 (2) Thus, for conventional charge pumps, the pump-up time can only be increased by a finite amount. Figure 2 illustrates one embodiment of the charge pump according to the present invention. The improved charge pump 100 has an architecture including an input 120 coupled to Vcc. The input 120 is coupled to a first stage, via impedance element 121, having a first node 150 including a capacitor 122 having a capacitance C α . The first stage is further connected to a second stage, via impedance element 123, including a second node 152 having a bootstrap capacitor 124 having a capacitance C 2 , which is different from C α . Coupled to stage 2 via impedance element 125 is stage 3 having a node 154 which includes a bootstrap capacitor 126 having a capacitance C 3 . Coupled to stage 3 via impedance element 127 is stage 4 which includes a node 156 having a bootstrap capacitor 128 having a capacitance C 4 . Stage 5, having a node 158 including a bootstrap capacitor 130 having a capacitance C 5 , is connected to stage 4 via impedance element 129. Stage 6, which includes a node 160 having a bootstrap capacitor 132 having a capacitance C 6 , is connected to stage 5 via impedance element 131. Next, stage 7 which includes a node 162 having a bootstrap capacitor 134 coupled thereto is connected to stage 6 via impedance element 133. The bootstrap capacitor 134 has a capacitance C 7 which is different in value than any of the preceding six capacitors. Stage 7 is coupled, via impedance element 135, to stage 8. Stage 8 includes a node 164 having connected thereto a bootstrap capacitor 136 having a capacitance C B . Stage 9 including a bootstrap capacitor 138 having a capacitance C g , is connected to stage 8 via impedence element 137. Stage 9, the final stage of the charge pump according to the present invention, has a node 168, to which the bootstrap capacitor 138 is coupled to via impedance element 137. The final stage (stage 9) is coupled through diode 139 to the output terminal of the charge pump V oul . The output terminal V oul also has coupled thereto a load capacitor 140 denoted C λ . C λ represents the total capacitance present at the output of the charge pump V out . The capacitors used in the charge pump according to the present invention all have an oxide thickness in the range of about 15θA - 35θA. Also connected to each stage of the charge pump 100 are non-overlapping clocks Φ and Φ which oscillate from 0 to Vcc. In a first embodiment of the present invention, the charge pump shown in Figure 2 contains nine stages and provides an output voltage of about 20 volts. Also, in the first embodiment of the present invention, the impedance elements 121, 123, 125, 127, 129, 131, 133, 135 and 137 are diodes. In a second embodiment of the present invention, the impedance elements are provided by diode connected MOSFETS that are operable to transfer a given current from one stage to another. In the first embodiment of the present invention, the stage bootstrap capacitors have the capacitance values as shown below in Table 1. TAPfrE 1 For purposes of illustration, the bootstrap capacitors 122, 124, 126, 128, 132, 134, 136 and 138 are represented as having capacitance values C α - C 9 . However, in practice, the bootstrap capacitor of a particular stage, n, has the value of the bootstrap capacitance present at node n plus the parasitic capacitance present at node n. For example, the total capacitance present at stage 2, C 3 , comprises the bootstrap capacitance, denoted C B2 , present at node 2 plus the parasitic capacitance denoted C p2 , also present at node 2. The capacitance present at the output V out is equivalent to the capacitance of the load connected to the output, C,,, plus the parasitic capacitance present at the output terminal, C p . Other values associated with the charge pump illustrated in Figure 2 include the initial voltage to the pump v inll ; the voltage swing at node N represented by: vcc ' C un Vsw - ( 2 ) and the voltage drop through each impedance element, which is represented by V pass . For the embodiment shown in Figure 2, v lnlt at every node is equal to Vcc, while V pass = 0. For charge pumps, at a time t, each individual node is either charging a subsequent node or is being charged by a previous node. For purposes of illustration, assume V[n,t] is the voltage at node n at an arbitrary time t. Time, t, is measured at every T/2 clock cycle increments, where T is the period of the clock. Suppose an arbitrary node n (n is neither 0 nor 1) is charged at an arbitrary time t, then the voltage present at node n will increase by an amount ΔV n , represented by: ΔV n -({V[n-l,t-l]+Vsw nΛ )-V[n r t-l])'k nl (4) where v[n-l,t-l] is the voltage present at the previous node at time t-1; Vsw n l is the voltage swing of the previous node; and V[n,t-1] is the value of the present node voltage at a previous time t-1; and k n x represents the bootstrap coefficient which is represented by: c . (5) n-l where C n λ is the bootstrap capacitance of the previous node and C n is the bootstrap capacitance of the present node. If node n is charging a subsequent node within the charge pump, then the node voltage will decrease by an amount of ΔV n represented by: ΔV n -( (V[n,t-l]*Vaw n )-V[n*l,t-l]) » (l-k Λ ) (6) where V[n,t-1] is the value of the present node voltage at a time t-1; Vsw n is the voltage swing of the present node that is doing the charging; V[n+l,t-l] is the voltage present at the subsequent node at a time t-1; and k n is the bootstrap coefficient represented by: c (7) π.l where C n represents the bootstrap capacitance present at node n and C n+1 represents the bootstrap capacitance of the subsequent node. To have a fast rise time, ΔV n should be large if the present node n is being charged, but should be small if node n is charging the next node. Both of these conditions are satisfied when the bootstrap coefficients k (0<k<l) are larger. For conventional pumps, the bootstrap coefficients, k t - k N 1 , have a fixed value of 0.5 because the bootstrap capacitance of the present stage is equal to the bootstrap capacitance of both the previous and subsequent stages. This is not true for the bootstrap coefficient of the last node, k N , due to the fact that the bootstrap capacitance C κ of the last stage will be different from the load capacitance C h at the output, C / C The output voltage, V ouL , is represented as shown below. Assume that V[0,t] = vcc and v[l,t] = vcc, with the change in voltage of the present node being represented by: V cd [n,t) ■ V[n,t-1] ♦ ((V[n-l,t-l] ♦ Vsw nl ) - v[n, t-1]) • * n _. (8) when the node is charged by a previous node, and: V c ,[n, fc] - V[n, fc-1] - ((V[n, fc-1] ♦ Vsw n ) - V[n*l], t * l]) (1-Jt n ) (9) when the present stage n is charging a subsequent node. The output voltage of the charge pump is represented by: v ed [AM, t] - v oat [t] ♦ v oat [t-1] (10) * i (V[N, t-l] ^ Vsw tl -V t ) -V out [t-l]) -k n Iload (2-fCj when the output is being charged by a previous node, and v ncd . [ L w*ι, ' t] J - v out r l t] J - v ou .t. [ 1 - t-1] J M , — r , « — ι f Vi-L-nW when the output is not being charged by the previous node. Thus, the voltage for any node can be determined by the equations shown above. The operation of the improved charge pump will now be described with reference to Figure 3. Figure 3 illustrates a two-stage charge pump 200 having the same operating characteristics as the nine stage charge pump 100 described with respect to Figure 2. In operation, each node of the charge pump 200 is either being charged by a previous node or is charging a subsequent node. Now, consider the two-stage charge pump 200 as depicted in Figure 3. For purposes of illustration, assume that the voltage drop through the diode 220 is about 0. In this case, there are two bootstrap coefficients k 2 and k 2 where k j is represented by: where C : is the bootstrap capacitance present at node 1 and C 2 is the bootstrap capacitance present at node 2, while k 2 is represented by: k 2 ■ -?-*-= ■ (13) C 2 * C L where C 2 is the bootstrap capacitance present at node 2 and C L is the output load capacitance. Suppose the voltage swing at node 1 and at node 2 is equal to Vcc and the initial voltages at node 1, node 2 and V oul are 0. Vcc at the input 211 will pass through diode 221, resulting in charging the capacitor 222 to Vcc . At this point, node 1 has the same voltage present at the input 211, Vcc. The current from node 1 is passed to node 2 via diode 223. Thus, the voltage present at node 2, at the next half-cycle will be: (V{1,0) v cc )' • k. ( K. cc ' k, 1-2 Vc V (14) V oul at a half-cycle later will be: ( v[2 , U ♦ v cc ) . k 2 - 2 v 2 • *. ♦ v cc . k 2 (15) ■ 2 V cc * *, * k 2 * V cc * k 2 The resulting current from node 2 (I OUL ) is passed through diode 220 to the output of the charge pump, thereby providing output voltage V out . For an N stage charge pump according to the present invention, the rise time can be represented by: W ' F 2 l k ι* k 2' •• •Jir n-ι ) (16) where k N is the bootstrap coefficient of the last node of the charge pump; F^kJ is an increasing function with respect to k N and F 2 (k 1 ,k 2 , ...k n l ) is an increasing function with respect to k 2 ,k 2 , ...k n l . As shown, the rise time of the charge pump is directly proportional to the stage bootstrap coefficients. For the charge pump according to the present invention, the bootstrap coefficient value k is equal to 0.574, representing a multiplication factor, m, of 1.35 where the multiplication factor (m) is equivalent to: (17 ) The multiplication factor indicates how much larger the previous stage bootstrap capacitor is, as compared to the current stage bootstrap capacitor. Figure 4 represents a comparison between the rise time of the charge pump according to the present invention (represented by Line 1) and the rise time of the conventional pump (represented by Line 2) . As shown in Figure 4, after the same amount of charging time, the output voltage of the charge pump according to the present invention is 33% greater than that of the conventional pump. Figure 5 represents a comparison of the charging characteristics of an eight stage charge pump according to the present invention (Line A) and the charging characteristics of a conventional pump also having eight stages (Line B) with both the conventional charge pump and the charge pump according to the present invention having the same last stage capacitor size. As shown in Figure 5, after the same elapsed time, the output voltage generated by the charge pump according to the present invention (9.50) is 42% greater than that of the conventional pump (5.50) having the same number of stages. Figure 6 is a graph representing the rise time improvement of the charge pump according to the present invention over that of a conventional pump having the same area. For purposes of illustration, a load capacitance, C x , of 100 pF is coupled to the output of the circuit presented in Figure 2 and a load current, l load , of 20 μA is assumed. The conventional pump is represented as having 13 stages. The charge pump of the present invention is represented as having nine stages. The number of stages was determined by the inventors to have the fastest rise time for a given output voltage of 20V. Note, the curves presented in Figure 6 were generated by application of equations 3-10. As shown, the speed exhibited by the charge pump according to the present invention is much better than the speed of the conventional pump. For example, suppose an application requires a rise time of 1.5 μsec. The conventional charge pump cannot meet this speed requirement no matter how large the bootstrap capacitors are made because of the inherent limit of the bootstrap capacitances. Conventional charge pumps have a maximum limit of about 1.7 μsec, whereas rise times of about 1 μsec are available using the charge pump according to the present invention. Figure 6 also provides the means for determining the bootstrap coefficient, k, necessary to produce an optimized charge pump. The general rule is that the bootstrap coefficient, k, should be chosen according to the speed requirement. Thus, as depicted in Figure 6, if the speed requirement is about 1.5 μsec, a multiplication factor of 1.2 or greater is satisfactory. If the speed requirement is between 1.25 μsec and 1.5 μsec, a multiplication factor of 1.3 or greater is satisfactory. And for a speed requirement of about 1 μsec and less, a multiplication factor of 1.5 or greater is required. Figure 6 is also used to determine the overall area of the resulting charge pump. The steps used to determine the total area required for the charge pump are as follows: 1. Determine the rise time necessary for the particular application. For the embodiments of the present invention, assume the rise time necessary is 2 μsec. 2. Next, draw a vertical line from the required rise time to the curve having the smallest area. This is represented in Figure 6 by line V. Where the vertical line V and the curves intersect, 300, corresponds to the multiplication factor, m, used to determine the size of the capacitors for each stage of the charge pump of the present invention. As shown in Figure 6, the multiplication factor required to meet the rise time of 2μsec is 1.3. 3. Draw a horizontal line (Line NN) from the intersection point 300 to the vertical axis. This corresponds to the ratio of total capacitance to load capacitance of the charge pump. For the particular application contemplated, the ratio equals 10. Next, multiply that value by the user-defined load capacitance. The resulting value represents the total capacitance value of the charge pump. 4. Then, determine the area of the charge pump by dividing the total capacitance determined in step 3 by the conversion value: 2fF μm' resulting in the total area of the charge pump in units of μm 2 . The conversion factor is dependent on the oxide thickness of the capacitors. The conversion value above is applicable when the bootstrap capacitors have an oxide thickness of about 15θA. To convert the total area into mils, multiply the total area determined in step 4 by the conversion factor 1/645. The same procedure can be used to determine the total capacitance needed for a conventional charge pump to meet the 2μsec required rise time. As shown in Figure 6, by drawing a horizontal line (Line CC) from the intersection of the rise time line of the conventional pump and the desired speed, 302, results in a ratio of total capacitance to load capacitance ratio of around 23. This, in turn, results in a total capacitance of about 2300pF assuming a load capacitance of lOOpF. Thus, the total capacitance required for a conventional charge pump is about 2.3 times that required for the charge pump of the present invention. This procedure can be used to determine the total area for a charge pump having any number of stages and required rise times. For the nine stage charge pump illustrated in Figure 2, the total area required for a charge pump having a rise time of about 2 μsec and delivering an output voltage of 20V is about 775 mil 2 . This is in contrast to the about 1,780 mil 2 that is required for the conventional pump to exhibit the same rise time. Thus, as shown above, to have a rise time of about 2 μsec, the conventional charge pump must be 2.3 times larger in size than the charge pump according to the present invention. By determining the multiplication factor and the total capacitance required for a given application (time requirement), the size of the capacitors for each stage of the charge pump can be determined. The steps used to determine the individual capacitor sizes is as follows: 1. Determine the multiplication factor for the charge pump. (See step 2 above). 2. Determine the total capacitance required for the application. The total capacitance for the nine stage charge pump of the present invention is represented as: total \ where C total represents the total capacitance of the charge pump according to the present invention; C N represents the capacitance of the last stage; and m represents the multiplication factor determined above in step 1. (See step 3 above) . 3. Determine the capacitance of the final stage of the charge pump by solving equation 18 below for C 9 : ^1 (19) where C total represents the total capacitance of the charge pump according to the present invention, C 9 represents the bootstrap capacitance value of the final stage of the charge pump and m represents the multiplication factor determined in step 1. 4. After determining the size of the final stage capacitor in step 3, the size of each bootstrap capacitor is determined in reverse order, by multiplying the capacitance value of the capacitor of the previous stage by the multiplication factor. Using the aforementioned method, the capacitors required for the nine stage charge pump of the present invention are presented above in Table 1. The foregoing description of the embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Modifications and variations of the invention are possible in light of the above teaching. A charge pump exhibiting enhanced rise time was chosen and described in order to best explain the principals of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims: CLAIMS What is Claimed Is: 1. A charge pump circuit, comprising: input means for providing a signal; output means for delivering a modified signal; and stage means, coupled between said input and output means, for generating said modified signal, said stage means including a plurality of impedance means, wherein each respective one of said impedance means has a different value. 2. The charge pump circuit of claim 1, wherein said impedance means further comprises a capacitor. 3. The charge pump circuit of claim 1, wherein said stage means includes N number of stages, where N is an integer greater than 2. 4. The charge pump circuit of claim 3 further including impedance elements coupled between said stage means and said output means. 5. The charge pump circuit of claim 4, wherein said impedance elements further comprise a diode. 6. The charge pump circuit of claim 4, wherein said impedance elements further comprise a diode connected MOS transistor. 7. The charge pump circuit of claim 3, wherein the number of stages, N, equals 9. 8. A charge pump circuit architecture, comprising: an input terminal operative to carry an input signal; an output terminal operative to deliver a modified version of said input signal; a first node including a first capacitor having a capacitance C l f said first node coupled to said input terminal; a second node including a second capacitor having a capacitance C 2 , said second node coupled to said first node; and an output node including a capacitor having a capacitance C N , said output node coupled to said output terminal; wherein the output capacitance C N is different from said second capacitance C 2 . 9. The charge pump architecture of claim 8 further including a diode coupled between said output node and said output terminal . 10. The charge pump architecture of claim 8, wherein said output capacitance C N is different from said first capacitance C 2 . 11. The charge pump architecture of claim 8, wherein said second capacitance C 2 is different from said first capacitance C j . 12. The charge pump architecture of claim 11, wherein said second capacitance C 2 is a multiplication factor, k, smaller than first capacitance C 1# where k is a positive integer greater than 0. 13. The charge pump architecture of claim 12, wherein the multiplication factor k is represented as: c n C nΛ where C n represents the amount of capacitance of the present node and C n+1 represents the capacitance present at the next node. 14. A charge pump circuit, comprising: an input terminal operative to provide a signal; an output terminal operative to deliver a modified signal; and a plurality of stages coupled between said input terminal and said output terminal, operative to generate said modified signal, each of said plurality of stages including an impedance element, wherein each respective one of said impedance elements has a different value. 15. The charge pump circuit of claim 14, wherein said impedance element comprises a capacitor. 16. The charge pump circuit of claim 14, wherein said plurality of stages includes N number of stages, where N is an integer greater than 2. 17. The charge pump circuit of claim 16, wherein the number of stages, N, equals 9. 18. The charge pump circuit of claim 14 further including a pass element coupled between each of said plurality of stages. 19. The charge pump circuit of claim 18, wherein said pass element further comprises a diode. 20. The charge pump circuit of claim 18, wherein said pass element further comprises a diode connected MOS transistor. 21. A charge pump circuit, comprising: an input terminal operative to provide a signal; an output terminal operative to deliver a modified version of said input signal; a first node including a first capacitor having a capacitance C l t said first node coupled to said input terminal; a first node coupled between said first node and said input terminal; a second node including a second capacitor having a capacitance C 2 , said second node coupled to said first node, said capacitance, C 2 , having a value smaller than C 1 ; a second diode coupled between said first node and said second node; a third node including a third capacitor having a capacitance C 3 , said third node coupled to said second, node, said capacitance C 3 having a value smaller than C 2 ; a third diode coupled between said second node and said third node; a fourth node including a fourth capacitor having a capacitance C 4 , said fourth node coupled to said third node, said capacitance C 4 having a value smaller than C 3 ; a fourth diode coupled between said third node and said fourth node; a fifth node including a fifth capacitor having a capacitance C 5 , said fifth node coupled to said fourth node, said capacitance C 5 having a value smaller than C 4 ; a fifth diode coupled between said fourth node and said fifth node; a sixth node including a sixth capacitor having a capacitance C 6 , said sixth node coupled to said fifth node, said capacitance C 6 having a value smaller than C c ; a sixth diode coupled between said fifth node and said sixth node; a seventh node including a seventh capacitor having a capacitance C 7 , said seventh node coupled to said sixth node, said capacitance C 7 having a value smaller than C 6 ; a seventh diode coupled between said sixth node and said seventh node; an eighth node including an eight capacitor having a capacitance C β , said eighth node coupled to said seventh node, said capacitance C 8 having a value smaller than C 7 ; an eighth diode coupled between said seventh node and said eighth node; a ninth node including a ninth capacitor having a capacitance C 9 , said ninth node coupled to said eighth node, said capacitance C 9 having a value smaller than C 8 ; a ninth diode coupled between said eighth node and said ninth node; and a tenth diode coupled between said ninth node and said output terminal.

Inventors: CHEN PAU-LING, HOLLMER SHANE, LE BINH QUANG, CHEN, PAU-LING, HOLLMER, SHANE, LE, BINH, QUANG
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1997
Main classification: H02M3
IPC codes: G05F3, H01L27, H02M3