RF phase and/or amplitude control device

Abstract: An RF phase and/or amplitude control device (40) has a digitally controlled attenuator (41) at it input to adjust the overall output level of the output. The device includes an in-phase power divider (43) for splitting up the input signals over two paths (I and Q). The power divided signals in the two paths are further power divided and shifted in relative phase at 180° hybrids (49 and 50). The power divided and phases shifted signals in each path I and Q are selectively switched using switches (51 and 53). The selected and switched output is quadrative combined at a 90° hybrid (55). This provides a single inexpensive device which can provide digitally controlled output signals which are either phase controlled or amplitude controlled or both.

Description: TECHNICAL FIELD OF THE INVENTION This invention relates to RF systems and more particularly to a digitally addressable RF control device for control of an RF signal as defined in the precharacterizing portion of claim 1. BACKGROUND OF THE INVENTION Radio frequency signal (RF) phase and amplitude control devices are used in a wide range of applications such as communication systems, radar systems, antenna systems, etc. It is further highly desirable that these RF control devices used for phase and amplitude control be digitally addressable devices. These RF control devices may include ferrite devices (such as ferrite phase shifters, for example) or semiconductor devices. The ferrite devices are expensive and the performance is limited. Semiconductor devices such as varactors, PIN diodes, and transistors are temperature sensitive, and therefore, resolution limited. It is therefore highly desirable to provide a high resolution RF control device for control using low cost elements. A system as defined in the precharacterizing portion of claim 1 is known from US-A-5,355,103. That documents discloses a fast settling, wide dynamic range vector modulator for use in an interference cancellation system or the like. A quadrature hybrid receives an RF signal and divides the signal into a primary in-phase component signal and a primary quadrature phase component signal. A first 180° hybrid receives the primary in-phase component signal and provides first and second secondary in-phase component signals which are 180° out of phase with each other. A second 180° hybrid receives the primary quadrature phase component signal and provides first and second secondary quadrature phase component signals which are 180° out of phase with each other. A first switching device selects one of the first and second secondary in-phase component signals, and a second switching device selects one of the first and second secondary quadrature phase component signals. First and second coarse attenuators respectively provide a selectable amount of attenuation to the selected in-phase and quadrature phase component signals. First and second fine attenuators provide fine attenuation to the coarse attenuated in-phase and quadrature phase component signals. A signal combiner combines the fine attenuated in-phase and quadrature phase component signals to provide the corresponding output signal. Reference is further made to US-A-5,222,246, which discloses a power amplifier arrangement including a power divider for dividing the signal to be amplified into equal-amplitude components. Each component is amplified by a signal amplifying path. The amplified signals are applied to a phase-sensitive power combiner. The combined signal appears at the sum port and a phase-related difference signal appears at a difference port of the combiner. The difference signal is processed to produce a control signal for controlling the relative phases of the signals passing through the signal amplifying paths. Finally, reference is made to US-A-4,297,641, which discloses an adjustable phase shifting circuit comprising first and second signal paths, each including an output terminal, an input terminal to which the frequency to be shifted is applied, and a variable level signal translating device with a level control terminal. Means are included for effecting a 90° phase shift in one signal path relative to the other and for producing a signal which is the vector sum of the signals appearing at the output terminals. A means is coupled to the control terminal of the variable level signal translating devices for respectively applying control signals to control the level of the signals produced at the output terminals for controlling the phase of the vector sum signal. SUMMARY OF THE INVENTION In accordance with the present invention an improved RF control device for phase shifting and amplitude control of an RF signal is provided. The invention is defined by the features of claim 1. Further embodiments are defined in the dependent claims. This provides a single inexpensive device which can provide digitally controlled output signals which are phase controlled and amplitude controlled. These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings. DESCRIPTION OF THE DRAWINGS The present invention will now be further described, by way of example, with reference to the accompanying drawings in which: Fig. 1 is a block diagram of an RF control device according to one embodiment of the present invention; Fig. 2 is a graph of the settings for the device of Fig. 1 where the I path is represented by solid lines and Q path by dashed lines; Fig. 3 illustrates the phase error using the attenuator setting of Fig. 2; Fig. 4 illustrates the amplitude variation for the attenuator settings of Fig. 3; Fig. 5 illustrates the distribution of phase errors for the results shown in Fig. 3; Fig. 6 illustrates the vector magnitude error distribution for the results shown in Fig. 4; and Fig. 7 shows the comparison of the digital processor calculated I and Q values with the values determined from an ideal weighter circuit. DESCRIPTION OF PREFERRED EMBODIMENTS OF THE PRESENT INVENTION In accordance with an embodiment of the present invention there is provided an RF control device 40 as illustrated in Fig. 1. The RF control device includes an input variable attenuator 41 which is a step attenuator that attenuates in half dB increments from 0 to 31 dB. This attenuator 41 is digitally controlled having nine binary inputs. The attenuator 41 is implemented for example using two cascaded MA/COM AT280 attenuators each having a range of 15.5 dB in 0.5 dB steps. The attenuator 41 adjusts the overall output power level. The output (at A) from the attenuator 41 is power divided by an equal in-phase power divider 43 and applied separately to an I (at B) and a Q (C) path. The in-phase power divider is for example a MA/COM DS-327. A lower cost Wilkinson power divider may also be used. In this particular embodiment, the I path includes 15.5 dB attenuators 45 and 46 cascaded in series. Similarly the Q path has two 15.5 dB attenuators 47 and 48 cascaded in series. These attenuators 45-48 are also digitally controlled by binary inputs. They are also MA/COM T280 attenuators for example. These attenuators are low cost surface mount GaAs (Gallium Arsenide) attenuators. These attenuators can adjust the relative amplitudes of signals in the I and Q paths. The output at D and E are from the separate I and Q attenuators 46 and 48. The output at point D from attenuator 46 is applied to 180° hybrid 49 to produce two equal power (power divided) 180° out of phase shifted signals at 51a and 51b. This 180° hybrid 19 is, for example, MA/COM HH-128 hybrid. This hybrid 19 may also be made at a lower cost using a rat race hybrid in microstrip. Likewise, the output at point E from attenuator 48 is applied to 180° hybrid 50 to produce two equal power signals that are 180° out of phase at 53a and 53b. The hybrid 50 is also on MA/COM HH-128 hybrid, but may be a rat race hybrid. The selected output from points 51a or 51b in path I is applied by a single pole double throw switch 51 to a port 55a of a 90° hybrid 55. This switch, for example, is a MA/COM SW 29. Similarly, the selected output from points 53a or 53b in path Q is applied by single pole double throw switch 53 to the port 55b of 90° hybrid 55. This switch is also, for example, a MA/COM SW29. The 90° hybrid 55, for the example, is a MA/COM JH140. It may be made at a lower cost using a Lange microstrip hybrid coupler or branch line hybrid coupler. The outputs from the I path and the Q path are then combined through the 90° hybrid 55. The output is provided via SPST (single pole double throw switch 56). The 180° hybrids 49 and 50 followed by SP2T switches 51 and 53 establish which quadrant the vector is in while the 90 degree hybrid, 55, vector combines the I and Q magnitudes orthogonally. The mathematics of this vector weighter are summarized below and references are to locations shown on the block diagram of Fig. 1. At point A the value is k 1 * v in where k 1 = 10 (ATT1/20) and ATT1 (41) is negative dB. At points B and C, k 1 * v in 2 . At point D, k 1 * k 2 * v in 2 where k 2 = 10 ((ATT2 + ATT3)/20) and ATT2 (45) and ATT3 (46) are negative. At point E, k 1 * k 3 * v in 2 where k 3 = 10 ((ATT4 + ATT5)/20) and ATT4 (47) and ATT5 (48) are negative. At point 51a(F), k 1 * k 2 * v in 2 . At point 51b(G), - k 1 * k 2 * v in 2 . . At point 53a(H), k 1 * k 3 * v in 2 . At point 53b(I), - k 1 * k 3 * v in 2 . . The selected outputs at point L out of hybrid 55 are: In general, v out = v in * k 1 2 ·[±· k 2 ± jk 3 ]. An optimization strategy is one where k 2 2 + k 3 2 is between 1 (0dB) and 1.059 (+0.5dB) for k 2 and k 3 varying from 0.02818(-31 dB) to 1(0dB) in 0.5 dB steps, then the ideal loss will be between -5.5 and -6 dB. The actual loss will be greater due to component losses. The strategy is to minimize the vector magnitude variation with phase while allowing the minimum possible phase step size for 0.5 dB resolution attenuators. Such an algorithm was developed with the absolute minimum phase step size determined to be 0.8 degrees and the worst case magnitude variation equal to 0.5 dB. The 0.8 degrees step size corresponds to approximately 9 bit resolution. Fig. 2 is a graph of the optimum attenuator setting of ATT2 (45), ATT3 (46), ATT4 (47), and ATT5 (48) for phases from -180 to +180 in 1 degree increments. The switch settings are also shown on Fig. 2. In Fig. 2, SW1-2 is switch 51 providing 51b output, SW2-2 is switch 53 providing 53b output, SW1-1 is switch 51 providing 51a output and SW2-1 is switch 53 providing 53a output. The solid lines is for attenuator settings in path I and the dashed lines is for attenuator setting in path Q. This device is optimized using two criteria. One was to realize the minimum phase error using 0.5 dB increment sizes of the I attenuators and Q attenuators and using the complete 31 dB range. The other optimization criteria was that the vector length have a maximum variation of 0.5 dB over 360 degrees. The phase error using the attenuator setting of Fig. 2 is shown in Fig. 3. The worst case errors of 1.61 degrees occurs at 0, 90, -90, and 180 degree points however, 96% of the errors are less than 0.8 degrees. The amplitude variation of vector for the attenuator settings of Fig. 2 is shown in Fig. 4. Fig. 5 shows the distribution of phase errors for the results shown in Fig. 3. From this graph, about 4% of the errors are greater than 1 degree with the maximum being 1.61 degrees. 96% of the errors are less than 0.8 degrees. Fig. 6 shows the vector length magnitude error distributions for the results shown in Fig. 4. This shape suggests a uniform distribution of errors about the mean value of +0.217 dB (1.0253 magnitude) with a maximum error of + 0.235 dB about this mean value. The digital processor will determine an RF phase () value and an RF magnitude ( k 1 ) value. The desired phase angle will be defined from an I and Q value. The vector magnitude will be established by one value, k 1 . The I and Q values will be calculated as follows. I = +1.0253 * COS () Q = +1.0253 * SIN () where  will be 0 to 90 degrees in 1 degree steps and where the + or - sign will select the proper quadrant for . The vector magnitude will be determined from the following relationship. where attenuation will be from 0 to -31 dB. A lookup table in RAM (Random Access Memory) will establish the corresponding address to the digital RF vector weighting circuit. Fig. 7 shows the comparison of the digital processor calculated I and Q values with the values determined from the ideal vector weighter circuit. Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope of the invention.

Claims: An RF control device for controlling both the amplitude and phase of an RF input signal, including: an input divider circuit (43) operable to divide the RF input signal into first and second component signals; a digitally controlled first component processing circuit operable to control the amplitude and phase of the first component signal in order to generate a first controlled component signal, said first component processing circuit including a digitally controlled first amplitude control circuit (45, 46) and a digitally controlled first phase control circuit (49, 51); a digitally controlled second component processing circuit operable to control the amplitude and phase of the second component signal in order to generate a second controlled component signal, said second component processing circuit including a digitally controlled second amplitude control circuit (47, 48) and a digitally controlled second phase control circuit (50, 53); a combiner circuit (55) for generating an output signal by combining the first and second controlled component signals, the output signal being an amplitude and phase controlled version of the RF input signal; and a digital control circuit operable to effect digital control of said first and second component processing circuits in response to a desired amplitude and phase control for the input signal; characterized in that : said first amplitude control circuit (45,46) is operable to control the amplitude of the first component signal in order to generate a first amplitude controlled signal; said first phase control circuit (49, 51) is operable to control the phase of the first amplitude controlled signal in order to generate said first controlled component signal; said second amplitude control circuit (47, 48) is operable to control the amplitude of the second component signal in order to generate a second amplitude controlled signal; said second phase control circuit (50, 53) is operable to control the phase of the second amplitude controlled signal in order to generate said second controlled component signal; and said digital control circuit is operable to effect control of said amplitude and phase control circuits in response to said desired amplitude and phase control for the input signal, by supplying to each of said amplitude and phase control circuits predetermined digital control information which corresponds to the desired amplitude and phase control for the input signal. An RF control device according to claim 1, wherein said first phase control circuit includes a first signal divider circuit (49) operable to divide the first amplitude controlled signal into first and second divided signals which are of opposite phase, and a digitally controlled first switch circuit (51) for selecting one of the first and second divided signals to be the first controlled component signal; and wherein said second phase control circuit includes a second signal divider circuit (50) operable to divide the second amplitude controlled signal into third and fourth divided signals which are opposite phase, and a digitally controlled second switch circuit (53) for selecting one of the third and fourth divided signals to be the second controlled component signal. An RF control device according to claim 1 or claim 2, including a preliminary amplitude control circuit (41) for controlling the amplitude of the RF input signal in order to generate an attentuated RF input signal which is supplied to an input of the input divider circuit (43). An RF control device according to any of claims 1 to 3, wherein said first and second amplitude control circuits each include a digitally controlled attenuator (45, 46, 47, 48). An RF control device according to any of claims 2 to 4, wherein said input divider circuit (43) includes an in-phase power divider, wherein said first and second signal divider circuits (49, 50) each include a 180° hybrid, and wherein said combiner circuit (55) includes a 90° hybrid. An RF control device according to claim 5, including a digitally controlled third switch circuit (56) coupled to the output of said 90° hybrid. An RF control device according to any of claims 4 to 6, wherein said preliminary amplitude control circuit (41) includes a digitally controlled attenuator which has a 31 dB range and attenuates in steps of 1 dB, and wherein said digitally controlled attenuators (45, 46, 47, 48) of said first and second amplitude control circuits each include two series-coupled attenuators that each have a 15.5 dB range and each attenuate in steps of 0.5 dB.

Inventors: DIXON WILLIAM F, KYLE ROBERT R, MEYER RONALD L, DIXON, WILLIAM F., KYLE, ROBERT R., MEYER, RONALD L.
Applicants: RAYTHEON CO, RAYTHEON COMPANY
Application year: 1997
Main classification: H01P5
IPC codes: H01P1, H01P5