Double sampled switched capacitor low pass multirate filter of a sigma delta D/A converter

Abstract: A ΣΔ digital/analog converter has a signal reconstructing multirate low pass filter realized as a switched capacitor fully differential, double sample structure wherein the input stage of the filter employs only two sampling capacitors, switched alternately on the two inputs of the stage and further includes two delay circuits (z -1 ) in the feed line of the bitstream towards one of the two inputs of the multistage SC filter. The zeroes so introduced in the transfer function reduce the noise energy in the vicinity of frequencies f s /2 n , preserving the SNR even with a relatively large mismatch between the capacitors.

Description: FIELD OF THE INVENTION The invention relates in general to a sigma-delta (ΣΔ) digital-analog (D/A) converter and more in particular to the analog part of the converting system that substantially comprises a low pass filter for reconstructing of the analog signal from the digital output stream of the ΣΔ demodulator. BACKGROUND OF THE INVENTION A ΣΔ digital-analog converter, must be necessarily followed by a low pass filter in order to reconstruct the signal from the output bitstream of the ΣΔ demodulator of the D/A converter. There are many solutions that combine switched-capacitors techniques (SC) with continuous-time (CT) techniques. The typical approach used for implementing the low pass filter in ΣΔ digital-analog converters to use a cascade of two filters. The first filter is realized with a SC technique of an order ≥2 functioning with a clock frequency f s equal to the frequency of the output bitstream data of the ΣΔ demodulator. The second filter is usually realized with a CT technique to eliminate the "imaging" in the vicinity of the f s frequency and, if requested, to drive through the filter's last stage the "off-chip" outputs. The second filter usually occupies a large area because of the high time constants that are normally realized with integrated resistors and capacitors according to the scheme shown in Figure 1, whose spectral response diagrams are illustrated in Figures 1a and 1b. In non-audio applications, wherein rejection of the clock frequency imaging about f s is not required, an efficient solution is to use a "multirate" fully SC filter, that is, a filter of order ≥3 whose first stages operate with a clock frequency f ck equal to f s , whereas the last stages have a fck equal to f s /2 n (n=1,2,3,...). In this way, the last stage of the filter may function simultaneously as an off-chip buffer without an excessive consumption (indeed, the use of an SC buffer with a dock frequency equal to f s which is usually rather high, because of the oversampled nature of the output stream of the ΣΔ demodulator, is prohibitive for low-power applications). The disadvantage of this solution is that in stages with a clock frequency equal to f s /2 n , the noise occurring at those frequencies is brought back into the base band (B) via aliasing. Being the ΣΔ D/A input node one that receives a signal with a high noise energy at frequencies well above the baseband (B) of the signal to be processed, in the vicinity of f s /2 n there is such an energy density that aliasing of this noise in the baseband degrades the signal/noise ratio (SNR) of the reconstructing filter, nullifying the beneficial effect of the ΣΔ conversion, as shown in the Figures 2, 2a, 2b and 2c. Moreover, in order to further reduce the dock frequency and thus the power of the operational amplifiers, facilitating also the functioning of the output buffer, double sampled SC structure are often used. These structures are typically realized duplicating each switched-capacitor and by inverting the associated control phases. However, this realization may introduce a further aliasing error equal to the mismatch among the input capacitances of alternate phases of the first input stage. OBJECTIVE AND SUMMARY OF THE INVENTION An effective solution to the above described problem is based on the placement of zeroes at a f s /2 n frequency as well as at its multiples, before the signal reconstruction filter. In this manner the signal present at the input of the filter's first stage functioning with a clock frequency of f s /2 n has a spectrum that presents notches at the frequencies of purposely introduced zeroes, with a consequent reduction of the noise energy practically nullifying the aliasing in baseband. A possible transfer function that attains this objective, assuming the case of n=2 is the following: 1+z -1 +z -2 +z -3 = (1+z -1 ) (1+z -2 ) This function places zeroes at the frequencies f s /2 and f s /4, as it will be evident to a person conversant in this field. The different aspects and characteristics of the invention among which is the provision of a circuit that efficiently implements the above discussed transfer function, are defined in the annexed claims. The features of the invention will be evidenced in the following description of preferred embodiments, also by referring to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1, 1a and 1b show a typical block diagram of a ΣΔ D/A converter and the respective response spectra at the output of the ΣΔ demodulation stage and at the output of the signal reconstructing low pass filter. Figures 2, 2a, 2b and 2c are respectively a block diagram of a ΣΔ D/A converter using a multirate reconstruction low pass filter of the 4 th order and the respective response spectra. Figures 3, 3a, 3b and 3c show the block diagram and the spectral response diagrams of a ΣΔ D/A converter using a signal reconstruction multirate filter of the 4 th order, according to the present invention. Figures 4a and 4b show respectively the circuit diagram of the input stage of the filter according to a conventional known embodiment and according to an embodiment of the present invention. Figure 5 shows the circuit scheme of a particularly preferred embodiment of the first stage of the signal reconstruction low pass filter. Figure 6, 6a and 6b are respectively a block diagram and the simulated response spectra relative to an embodiment of the invention. DESCRIPTION OF THE CIRCUIT OF THE INVENTION Figure 3 shows the modification introduced in an input stage of a signal reconstruction low pass filter, according to the invention. The circuit diagram highlights the presence of a stage of delay and conversion of the signal from a single-ended (SE) configuration to a fully differential (FD) configuration and the in figures 3a, 3b and 3c are evidenced the respective diagrams of spectral response after the introduction of zeros at f s /2 n frequencies, according to the objectives of the invention. As highlighted in Figure 4b, the fully differential input stage to the multirate signal reconstruction filter is structured in a way to realize a double sampling without duplicating the input capacitors of this first stage, which by contrast is the case in a classical form of realization shown, by way of comparison, in Figure 4a. As more fully illustrated in the circuit diagram of Figure 5, the first stage of the filter uses two delay blocks (z -1 ) of the digital output stream D of the ΣΔ demodulator of the digital/analog converter for introducing zeroes at f s /2 n frequencies. Therefore, the fully differential, double sampled, input structure of the SC signal reconstruction filter of the invention performs double sampling without duplicating the input capacitors of the first stage of the filter, using the capacitors alternately on two inputs of the FD structure and advantageously eliminating the aliasing phenomenon caused by the mismatch among capacitors. Simultaneously, such an input structure also realizes a SC bilinear transformation that automatically introduces a first notch at f s /2. This because of the expression at the numerator of the transfer function of the structure of the invention: 1+z -1 ⇒ notch at f s /2 At this point, in order to introduce a second notch at f s /4, it is simply required to add two delaying blocks z -1 on one of the two inputs of the fully differential structure, thus implementing an expression at numerator of the transfer function given by: V + o - V - o V in = N ( z ) P ( z ) D ( z ) = 1+ z -1 + z -2 + z -3 D ( z ) . P ( z ) where P(z)/D(z) is the transfer function associated to the first stage of the filter. The "in band" specifications of the multirate filter remain always assured by the necessary and sufficient condition for the synthesis of a SC filter, which notably is: f s /2 n >>B where B is the useful band of the signals to be processed. The diagram of a ΣΔ D/A converter realized according to the present invention is depicted in figures 6, 6a and 6b illustrate the simulations for the converter of the invention fed with a bitstream with a frequency f s =2MHz having an SNR=96dB for a signal band B=4kHz (2 nd order ΣΔ). In the illustrated example the reconstructing filter is a double sampled, ladder type, SC low pass filter of the 4 th order with the first two stages functioning with f ck =1MHz and the following two stages functioning with f ck =256kHz. The simulations demonstrate an unchanged SNR at the output of the filter even in presence of a 1% mismatch between the input capacitors.

Claims: A sigma-delta (ΣΔ) digital-analog converter comprising a multirate low, pass filter for reconstructing the analog signal from the output bitstream (D) of the sigma-delta demodulation stage of the converter, the input stage of said filter being a switched capacitor, fully differential, double sampled structure, characterized in that said fully differential input stage uses only two switched capacitors and has means inverting the connection of the terminals of said two capacitors to the two inputs respectively of the first or input stage of the low pass filter; and comprises further two delay blocks (z -1 ) on the feed line of said bitstream towards one of said two inputs. The converter of claim 1, wherein said delay blocks introduce zeroes in the transfer function of the multirate low pass filter at the frequencies f s /2 n where n is an integer number whose value is within the range 1 to n max , being f s /2 max the clock frequency of the last stages of said multirate switched capacitor filter.

Inventors: NAGARI ANGELO, NICOLLINI GERMANO, NAGARI, ANGELO, NICOLLINI, GERMANO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1997
Main classification: H03M3
IPC codes: H03H19, H03M3