DIGITAL PHASE LOCKED LOOP

Abstract: A phase locked loop comprising a phase comparator (32) for receiving an incoming signal with which it is desired to lock, a loop filter (30) to process a current error signal, and an integrator (22, 34) to adjust the output to account for the error, wherein the phase comparator, loop filter and integrator are formed from digital logic elements. The phase comparator (32) may be implemented as a two's complement subtractor, the loop filter (30) as a barrel shifter and the integrator (22, 34) as an accumulator register. The phase locked loop is used to generate an output signal (50) synchronised with an input signal (SI) by providing a plurality of phase shifted signals using a delay line or a shift register and selecting one of said phase shifted signals as the output signal according to a phase comparison between the selected signal and the input signal. The DPLL may be advantageously used for recovery of clock signals in digital data communications systems, in particular in Manchester coded Ethernet data.

Description: Digital Phase Locked Loop The present invention relates to a Phase Locked Loop (PLL) implemented in a digital form. As is well known, a PLL's function is to provide an oscillating output which is synchronised, or locked, with an incoming signal. The generation of me output signal is independent of the incoming signal although its phase is controlled by me incoming signal. Therefore a PLL is useful for, for example, generating a clock signal synchronised with an incoming signal, while the incoming signal may be affected by noise or may be partially corrupted. A typical analog PLL comprises three basic elements: a phase comparator for receiving an incoming signal wim which it is desired to lock- a loop filter to process a current error signaL and an integrator to adjust the output to account for the error. In particular in communication systems it is necessary to recover a correct clock signal from the received data in order mat the received data can be properly understood. In digital communication systems an analogue PLL could be provided for me generation of me clock signal, but implementation of an entirely digital system would be simplified by me provision of a digital PLL (DPLL) such that it can be integrated with other parts of the digital device. The present invention provides a DPLL in which the above elements are implemented digitally such that it can be implemented using standard logic synthesis tools. This means that the invention is not limited to a particular type of chip, for example, but can be easily implemented in many digital environments and different format integrated circuits. The DPLL of the present invention, while advantageously used for recovery of clock signals in a digital data communications system as mentioned above, can also be utilised in other situations where a PLL function is required in a digital environment. The present invention implements a method of generating an output signal synchronised wim an input signal comprising providing a plurality of candidate signals and selecting one of said candidate signals as the output signal according to a phase comparison between the candidate signals and the input signal. The phase comparison is preferably conducted by sampling the candidate signals according to me input signal and utilizing the results of the sampling to generate an error signal indicative of the phase difference between the currently selected output signal and the input signal. The error signal is then fed back to select a new candidate signal as the output signal. To avoid "hunting" in the selection feed-back the method preferably further comprises attenuating me error signals progressively to achieve a satisfactory "lock" with the input signal while being unaffected by noise and jitter in the input signal . The present invention will be better understood from the following description of preferred embodiments given by way of example and in conjunction with the accompanying drawings, in which: Figure 1 illustrates me generation of the candidate signals for use in the preferred embodiment; Figure 2 illustrates the basic operation of the digital phase locked loop according to me preferred embodiment of this invention; Figure 3 illustrates the relationship between signals in Manchester encoded Ethernet data; Figure 4 illustrates the generation of the mid-bit clock from the received Ethernet data; and Figure 5 illustrates the use of the digital phase locked loop according to the preferred embodiment of this invention in the decoding of received Ethernet data. As mentioned above, a typical PLL comprises three basic elements and the present invention implements these digitally, preferably using a hardware descriptor language to describe the behaviour of the elements. As will be described in more detail below, the DPLL comprises a two's complement subtractor as an implementation of a phase comparator, a barrel shifter as an implementation of a loop filter and an accumulator register as an implementation of an integrator. This approach allows the design to use standard logic synthesis tools to create the logic gate representation and does not require hand crafted design or chip layout. The basic purpose of me PLL is of course to generate an output signal, eg a clock signal, which is synchronised with an incoming pulse train. In this digital implementation this is done by providing a series of candidate output signals, these all having a frequency equal to me expected input frequency, but being progressively out of phase wim each other. These are compared with the input signal with which it is desired to synchronise and an appropriate one of the candidate signals is selected for output. One method of generating the candidate signals or phases is illustrated in Figure i. Figure 1 shows a 32-bit shift register r OJ r„ r 2 .... r 30 , r 31 , which is clocked by both edges of a 160MHz clock. As can be seen from the figure the inverted output from phase 15 is applied as the input to r 0 and alternate registers are clocked by the rising and falling edges of the 160MHz clock. Each of phases 0 to 31 is thus a 10MHz signal having a 50% duty cycle, d e phases being successively out of phase and nominally separated by 3.125ns. The phase signals thus generated can be used as candidate signals for a number of PLLs. although in the following only one is described. The high frequency clock may be generated from a 40MHz clock by an analog PLL which is available in many ASIC technologies. Alternatively a 160MHz oscillator may be provided. Alternatively the 32 phases could be generated by a tapped delay line or a high frequency oscillator. Figure 2 illustrates the basic operation of the phase locked loop. The device illustrated in Figure 2 comprises a multiplexer 20 to which the 32 phases generated in Figure 1 are applied. According to the clock address signal currently in clock register 22, multiplexer 20 selects one of me 32 phases and thus provides the output of the device. S 0 . The intention ofthe design is that signal S 0 is synchronised with input signal S,. As shown in Figure 2, the device also comprises a 32-bit register 24 to which the 32 phases generated in Figure 1 are also applied. Register 24 is clocked by input signal S, and thus me data clocked into register 24 is effectively samples ofthe 32 clock phases at the rising edge of signal S,. As will be appreciated diis results in a series of 16 Is and 16 Os being clocked into the register 24, an example of which is illustrated in Figure 2. In the illustrated case phase 5 is the first of the phases numbered 0 to 31 to have its rising edge after the rising edge ofthe signal S,. This is represented by the transition from 1 to 0 in the series of bits in register 24. The outputs of register 24 are gated by gating means 26 to identify d e location of the above mentioned transition. By way of example, gating means 26 may comprise a series of 32 AND gates arranged to "AND" an inverted version of each bit wim the previous bit in order to identify the location ofthe "10" transition in register 24. The outputs of means 26 for the example mentioned above are shown in Figure 2. These outputs are all 0s except for a single 1 corresponding to phase 5. The outputs of means 26 are input to encoder 28 which outputs a number, in this case a 5-bit number, indicative ofthe position ofthe "1" in the outputs from gating means 26. In the simplest implementation of this arrangement the output from encoder 28 could be used directly as die clock address for reading into register 22 and application to multiplexer 20. However in practice input signal- S, is generally subject to jitter and other noise and therefore it is advantageous to introduce some damping into the selection ofthe correct phase as the output signal. In Figure 2 this is provided by bit shifter 30, subtracter 32 and adder 34, under the control of 36. As will be appreciated from die arrangement of Figure 2, the output from encoder 28 is compared wim the current clock address in register 22 by subtracter 32 to generate a phase error signal. This is applied, via shifter 30, to adder 34 and added to die current clock address to generate a new clock address for storage in register 22. In the situation where shifter 30 makes no change in the phase error signal this results in the output of encoder 28 being applied as me new clock address in register 22. In more detail me present invention clock address is subtracted from the data phase from encoder 28 to give a 5 bit error (twos complement). This error is then used to modify me clock address (up or down accordingly) to achieve a closer sampling phase. The modification process incorporates a gain factor by shifting the error before adding it to me clock address. Initially the gain is unity which results in the phase error being added to the clock address to make it the same as the phase of the first data edge (zero phase start). During the next two bits the gain is high (V ) and so large phase errors are quickly averaged out. However in situations where large amounts of jitter are present, such a large gain could result in continuous "hunting" for the correct phase and so for the next few bit times (eg 5) me gain is set to 1/8 to give some damping. The expectation is that the resulting clock address will be within 1 phase ofthe correct sampling point at the end of such a locking period. After this it is desired to accommodate small frequency errors whilst rejecting large amounts of transition jitter. For diis reason the gain is reduced to 1/32 after the initial lock- on period. The gain is implemented as a shift 30 controlled by controller 36 between the phase comparator 36 and me clock address "integrator" 34. The integrator consists of a 10 bit register and an adder. The input phase error is shifted by the gain factor and men added to die 10 bit clock address register. This is also a twos complement number as it has to cope with negative values. Before the resulting address is used to select the clock phase to be used, die value must be converted to a ones complement 5 bit value. This is done by taking the most significant 5 bits and adding lθ(hex) to it. Thus a full scale negative value of lθ(hex) becomes 00 after addition because the sign bi tis lost as overflow. Likewise a mid point 00(hex) becomes 10 after addition and a full scale positive OF becomes IF. As described above me device of this embodiment selects as its output the one of the 32 input phases which is closest in phase to me input signal. The embodiment can however be simply altered such diat the output signal is at a predetermined phase relationship form the input signal. This can be achieved by appropriate shifting of the outputs of the gating means 26 or by incorporating an appropriate addition in or after me encoder 28. The present invention has particular application in providing clock recovery for decoding an incoming data signal in a communications network, eg a LAN. In me following an example of such an application is described in the context of an Ethernet network, which utilizes Manchester encoded data. 10 Mbps Etfiernet uses Manchester encoding for data transmission. In Manchester encoding a transition is placed at me centre of each bit ceil which represents the value of die bit being sent. A positive transition represents a 1 and a negative transition a 0. In a stream of Manchester encoded data mere may or may not be a transition at a bit cell boundary as this depends on the data either side of me boundary. Manchester encoded data is illustrated in Figure 3. As can be seen in diis figure, if a data bit is followed by another of the same value, there is an additional transition at die boundary of die two bit cells. If a data bit is followed by one of me opposite value then mere is no return transition. In order to generate a clock from a Manchester encoded stream it is therefore important to establish which transitions in the data stream are active data and which are return transitions and can be ignored. The clock recovery process for Ethernet involves generating a sampling clock which is centred in one half of me bit cell so that it samples either true or complement data on each active edge. The arrangement described below generates a sampling clock which is centred in the first half cycle ofthe data cells and so latches the complement ofthe true data. This is then inverted to generate true data. The resulting clock which is to be used to clock die recovered data into the next part of the system is the complement of the sampling clock. Thus the data is presented as a NRZ bit stream and the recovered clock is centred in each recovered data bit. In die arrangement described below, a phase locked loop as described above is used to generate a sampling clock in phase with the received data signal. To achieve this a signal is generated from the received data which has a rising edge corresponding to me mid-cell transitions of me Manchester encoded data, and that signal, designated hereafter rxRect, is used as die input to the PLL. Figure 4 illustrates the generation of rxRect from the incoming data rxEncode. This arrangement utilizes the fact that the preamble to each packed in Ethernet comprises a series of alternating Is and 0s. When this is Manchester encoded it is the case mat the only transitions in the received data are at d e mid- cell points. Initially, during the preamble, die PLL is not synchronised with die data and die "locked" signal in Figure 4 is "0". Thus multiplexer 40 supplies a 5ns delayed version of rxEncode to exclusive OR gate 42, which takes as its other input the undelayed rxEncode. Ex-OR gate 42 dius outputs a 5ns pulse corresponding to each transition in rxEncode. This is illustrated at Figure 4A. After the preamble there may be transitions at the data cell boundaries which must be ignored in the generation of rising edges in rxRect. By this stage the PLL will have locked to d e correct phase, as discussed below, and me sampling clock can thus be used togedier wim register 44 to provide an alternative input to ex-OR gate 42. This situation is illustrated by Figure 4B. The negative transition on the mid-bit clock (rxRect) now occurs either when the return transition on die data occurs or, if there is no return transition, when die next data bit is sampled. Positive transitions ofthe mid-bit clock always occur when mere is a mid-bit transition on the received bit stream. Figure 5 illustrates the use of a DPLL as shown in Figure 2 to decode Manchester encoded data as illustrated in Figure 3. As will be seen, many parts of Figure 5 are common widi Figure 2 and d e same reference numerals are used to identify corresponding parts. In Figure 5 the incoming received data is input to decoder 50, which basically comprises the apparatus illustrated in Figure 4. The output of ex-OR gate 42 in Figure 4 is output from decoder 50 and is used as the input to the phase locked loop and thus applied to register 24. The phase locked loop in Figure 5 is arranged to generate as the output of multiplexer 20 the sampling clock illustrated in Figure 3. As is shown in Figure 3 this clock is desired to be one port of wavelength ahead of die mid-bit clock generated by decoder 50. In this embodiment this is achieved by appropriate connection of me AND gates in gating means 26. In particular, the outputs of me AND gates described above in relation to Figure 2 are shifted to the left by 8 bits for input to encoding means 28. The apparatus of Figure 5 is controlled by state machine 52 which takes and inputs die mid-bit clock generated by decoded 50 as well as die sampling clock output by multiplexer 20. One ofthe outputs of state machine 52 is the "locked" signal shown in Figure 4, and diis is one of me inputs to decoder 50. At d e start of a received data packet d e locked signal is set to zero and thus, as described above, die mid-bit clock comprises a series of 5 nanosecond pulses. State machine 52 also controls shifting means 30 in order to provide die damping as described above to ensure that me phase locked loop lock into the required phase relationship witii die input signal by die end of d e received preamble. Once die required synchronisation has occurred die locked signal is set to "1" and decoder 50 is switched to generate die mid-bit clock accordingly as described above. As mentioned above, the sampling clock generated by die PLL is synchronised to be V* wavelength ahead of die mid-bit transition in each received data cell. As illustrated in Figure 4 tiiis means that it can be used to decode die incoming data by way of register 44. As will be appreciated from Figure 3, if the incoming data is sampled according to d e rising edges of me sampling clock, the samples will be me complement ofthe data being transmitted in each cell. As illustrated in Figure 4 these samples generated by register 44 are inverted on their output to generate a signal designated "decode" which represents the decoded data. As will be appreciated therefore the digital phase locked loop of die present invention can be simply be and advantageously used in the decoding of received Ediemet data.

Claims: CLAIMS: 1. A phase locked loop comprising a phase comparator for receiving an incoming signal witii which it is desired to lock, a loop filter to process a current error signal, and an integrator to adjust die output to account for me error, characterised in tiiat die phase comparator, loop filter and integrator are formed from digital logic elements. 2. A phase locked loop according to claim 1, wherein me phase comparator is in the form of a two's complement subtracter. 3. A phase locked loop according to claim 1 or 2, wherein the loop filter is in the form of a barrel shifter. 4. A phase locked loop according to claim 1, 2 or 3, wherein die integrator is in e form of an accumulator register. 5. A phase locked loop according to any one of the preceding claims and comprising means for providing a plurality of possible output signals all of die same frequency but each of a different phase, and means for selecting one of said plurality of input signals for use by the phase comparator. 6. A phase locked loop according to claim 5, wherein the means for providing a plurality of possible output signals comprises an n-bit shift register, the alternate registers of which are arranged to be clocked by die rising and falling edges of an n x m Hz clock signal. 7. A phase locked loop according to claim 6, wherein the clock signal is 40 MHz or an integer multiple thereof. 8. A phase locked loop according to claim 5, wherein me plurality of possible output signals are provided by a tapped delay line. 9. A phase locked loop according to any one of claims 5 to 8 and including means for damping the operation of said selecting means whereby to ameliorate the effect of noise or jutter.

Inventors: OVERS PATRICK, OVERS, PATRICK
Applicants: 3COM IRELAND, OVERS PATRICK, OVERS, PATRICK
Application year: 1997
Main classification: H03L7
IPC codes: H03K5, H03L7, H04L7