Interface apparatus for adapting data width to system bus width

Abstract: According to a method for transmitting data of the invention, a system detects the amount of data which can be transferred, and divides the data to be transferred into a plurality of data blocks so that it forms a list. A transfer device refers to the list and carries out an inputting and outputting processing between a VTR or a network and a memory. Thus, the data can be efficiently transmitted at high speed with high reliability and without depending on a system configuration. Additionally, the data can be rearranged in the course of its transmission.

Description: The present invention relates to a method for transmitting data, and an apparatus for transmitting data and a medium which can be used when for example, data representing video images, data representing sound and auxiliary data except them are inputted and outputted between an information recording and reproducing device and a computer. A device (VTR, video cameras, hard disks, optical disks or the like) for recording or reproducing information such as video images and sound has been connected to a computer through an exclusive interface or a network and data has been transmitted. Thus, an editing operation for the video images, sound or the like has been carried out on the computer. This technique for the recording and reproducing device is proposed by Japanese Patent Application published under No. 8-176934. However, depending on the system configuration of a hardware or a software such as an operating system in a computer, the amount of data capable of being transmitted within a unit time which is assigned to each of various processings of an entire data transfer rate respectively changes. Therefore, there has occurred a problem that if the system configuration changes, a phenomenon in which it is impossible to transmit data or a reproduced video image is dropped out of a frame or the like occurs, or the data of an amount smaller than that which can be actually transmitted can be only transmitted with an efficiency lowered. Further, there has also arisen a problem that each time the system configuration changes, it is necessary to change a hardware or software. In addition, there has occurred a defect that if the data is simultaneously edited while the data is transmitted, the data to be transmitted can not be fetched by mistake. Still further, there has been proposed a method that when an excess transfer amount of the bus of a computer is compared with a requested transfer amount and the requested transfer amount exceeds the excess transfer amount, the request is stood by, and then, when the excess transfer amount recovers, the data is transferred. However, according to this method, even when the excess transfer amount of the bus remains or is left, if the requested transfer amount exceeds the former, the request must be waited for. Therefore, the excess part of the bus is undesirably wasted. WO 94/17476 discloses an interface apparatus, wherein data is transferred between a network and a memory of a data handling device. The data is transferred between the network and the memory by plural FIFO memories arranged in parallel and a data alignment device connected to a controller, the controller being connected to a computer bus which accesses the memory of the data handling device. WO 93/12486 discloses an interface device for regulating a transfer of data between the first and a second device via their respective data bus, wherein the data bus of the first device has a different width than the data bus of the second device. The interface device is connected to each of the two data busses and temporarily stores data to be transferred in a buffer memory for accumulating or decomposing data in accordance with the respective bus width. The present invention was made in order to solve the above-mentioned problems of prior art and it is an object of the present invention to provide an apparatus for transmitting data by which data can be efficiently transmitted to an information recording and reproducing device at high speed without depending on a system configuration. It is an object of the present invention to provide an apparatus for transmitting data capable of more improving a reliability. This is achieved by the features of claim 1 for an apparatus for transmitting data. Further embodiments are the subject-matter of dependent claims. Since the present invention has the above-mentioned construction, the invention can provide an advantage that the transfer capacity of a system inherent in the system can be employed more efficiently, without depending on the system configuration, than conventional apparatus. Further, according to the above-mentioned construction, an apparatus for transmitting data of the present invention can desirably transmit data more efficiently and achieve a high speed transmission with a higher reliability than those of the prior art. Besides, in the method and apparatus and the medium of the present invention, a processing time for arranging or listing data can be desirably much shortened as compared with those of the prior art. The present invention will now be described, by way of examples, with reference to the accompanying drawings, in which: FIG. 1 is a block diagram of a system showing a first embodiment; FIG. 2 is a flowchart showing an example of the operation of a software 6 in the first embodiment; FIG. 3 is a block diagram of a system showing a second embodiment; FIG. 4 is a view showing an example of the form of a list 13 according to the second embodiment; FIG. 5 is a block diagram of a system showing a third embodiment; FIG. 6 is a block diagram of a system showing a fourth embodiment; FIG. 7 is a block diagram of a system showing a first embodiment in accordance with the present invention; FIG. 8 is a timing chart showing a data transfer in the first embodiment; FIG. 9 (A) is a block diagram of a first example illustrating other configuration in the first embodiment; FIG. 9 (B) is a block diagram of a second embodiment illustrating other configuration in the first embodiment; FIG. 10 is a view showing a configurational example of the block of a list in the first embodiment; FIG. 11 is a view showing a configurational example of a transfer command of the list in the first embodiment; FIG. 12 is a view showing a specific example of a list 13 in the first embodiment; FIG. 13 (A) is a block view of data obtained by rearranging data in the first embodiment; and FIG. 13 (B) is a view showing a configurational example of the list 13 in accordance with the rearrangement of data in the first embodiment. A description will be given to embodiments of the present invention by referring to the accompanying drawings. FIG. 1 is a block diagram of a system showing a first embodiment . With reference to FIG. 1, the configuration and the operation of the first embodiment will be described below. In FIG. 1, a VTR 1 is a means for recording and reproducing video data, sound data, and data of a DVC format including other auxiliary data (The DVC format is disclosed in Japanese Patent Application published under No. 8-17693 or the like). An interface 2 is an interface between the VTR 1 and a PCI bus 4 and serves as a means for converting data outputted from the VTR 1 into a PCI bus form. The data on the PCI bus 4 is controlled by a software 6 on a memory 3 and a CPU 5 and transmitted to the data area 7 of the memory 3 in the form of a unit of datablock, which will be described hereinafter. The software 6 has a transfer means 8 for detecting the amount of data which can be transferred through the PCI bus 4 and dividing data receiving a request for transfer into data blocks with the capacity which does not exceed the amount of data capable of being transferred. Further, the data is also transmitted to the VTR 1 from the data area 7 in a sequence opposite to that mentioned above. Further, the data of the data area 7 is processed by the software 6 and then, can be outputted to a monitor 11 through a VGA interface 10 connected to the PCI bus 4. The data can be also inputted to and outputted from a hard disk 12 through an SCSI interface 9 connected to the PCI bus 4. A user can employ a keyboard or a mouse not illustrated so that he or she can carry out the above-mentioned operations. Incidentally, although the PCI bus is employed in the first embodiment, it is to be noted that other bus such as an ISA bus may be used. Further, while, the VTR is used as the recording and reproducing device, it is to be understood that other recording and reproducing device such as an optical disk or a hard disk may be used. Still further, the recording and reproducing device may not be used and a network may be used. Additionally, while, the data of a known DVC format is utilized, it is to be noted that the present invention is not limited thereto, and the data of other format may be utilized. In addition, as the software 6, any one of an application program, a device driver and an operating system may be used. Besides, it is to be recognized that other interface such as IDE, EIDE or the like may be used in place of the SCSI interface to the hard disk 12. FIG. 2 is a flowchart showing an example of the operation of the software 6. When the software 6 receives a transfer request of data (step 21), the software 6 gains the amount of the transfer request for data (step 22) and the amount of data capable of being transferred which is allowable by the bus (step 23). The gaining of the amount of data which can be transferred will be described later. Then, the amount of the transfer request for data is compared with the amount of data which can be transferred in view of their capacity (step 24). When the amount of data which can be transferred is lower than the amount of the transfer request for data, the requested data is divided into data blocks respectively having the size of data which does not exceed the amount of transferable data (step 25). Each block of a plurality of the divided data blocks is regarded as one unit for transferring data (this is called one unit transfer) and transmitted (step 26). Otherwise, all the requested data is transferred at the same time. In this connection, the amount of transferable data may be obtained from a function prepared for an operating system or may be calculated from a memory area secured for transferring data through the bus, that is, the amount of an unused part of the data area 7 illustrated in FIG. 1. Now, the division of the data block will be described in more detail hereinafter. In the above-mentioned embodiment , the amount of data which can be transferred per unit transfer is determined depending on the relation between a period of one unit transfer and a bit rate (this means a data transfer rate) per unit time which are predetermined by a system configuration or the like. Therefore, when the amount of data to be transferred exceeds the predetermined amount of data transferable, the data to be transferred is divided into a plurality of data blocks, as mentioned above. In such cases as mentioned below, it may be possibly necessary to divide the data into the data blocks. Specifically, there is mentioned a first case in which, although the amount of data itself to be transferred is located within a range of the predetermined amount of data which can be transferred, the data transfer rate of the data to be transferred exceeds a reference predetermined by the above-mentioned system configuration or the like. In this case, the bit rate needs to be changed so that the data transfer rate of the data to be transferred reaches not higher than the above-mentioned reference. As a result of a changing treatment, when the period required for transferring the data exceeds the reference of the predetermined period, the data to be transferred is divided into a plurality of data blocks. Thus, the amount of data of one of the divided data blocks satisfies the conditions of the amount of transferable data and can be transferred without difficulty. In addition, when the data to be transferred is divided into a plurality of datablocks, if the unit length of the divided data block is shortened, a plurality of data blocks can be transmitted within one unit transfer. It should be noted that, when the period required for transferring the data does not exceed the reference of the predetermined period, as a result of a changing process, the data to be transferred may not be divided into a plurality of data blocks without a problem. As a second case, when the amount of data itself to be transferred exceeds the predetermined amount of transferable data, the second case is further divided into two instances. As one of the instances, the data transfer rate of the data to be transferred exceeds the reference of the predetermined data transfer rate. In this case, the data to be transferred may be divided into a plurality of data blocks similarly to the first case. As the other of the instances, while the data transfer rate of the data to be transferred does not exceed the above-mentioned reference, the length of the data exceeds the above-mentioned period. In this case, the changing process of the data transfer rate is not needed but the data may be divided into a plurality of data blocks so that they are located within a period of one unit transfer. The above-mentioned division of the data block may be similarly applied to all the embodiments which will be described below. FIG. 3 is a system block diagram showing a second embodiment . The construction and operation of the second embodiment will be described by referring to FIG. 3. In FIG. 3, parts the same as those shown in FIG. 1 are indicated by the same reference numerals as those in FIG.1 and the explanation thereof will be omitted. A list 13 is formed by a software 6. When data needs to be divided into a plurality of data blocks as stated in the first embodiment, the list 13 stores the first addresses (the addresses of the destination of data transfer or the addresses of the start of data transfer) and the sizes (data sizes) of the divided blocks as a list. As a form of the list, for instance, an example as shown in FIG. 4 may be exemplified. However, any form which can be made access to from the software 6 may be employed. The formation of the list will be further explained in other embodiments mentioned below. For example, when data is transferred from a VTR1 to a memory 3, the first addresses (corresponding to addresses in the memory 3 serving as the destination of data transfer) and the sizes of the divided blocks of the formed list 13 are sequentially read by a transfer means 8. In response thereto, a CPU5 transmits the data of the VTR 1 to the memory 3 through an interface 2 and a PCI bus 4 so that the data is stored in the address of the destination of data transfer for each of the divided blocks. On the other hand, when the data is transferred from the memory 3 to the VTR 1, the first addresses (corresponding to addresses in the memory 3 serving as the start of data transfer) and the sizes of the divided blocks of the formed list 13 are sequentially read by the transfer means 8, so that the CPU 5 reads the data block with a relevant size from the relevant address in the memory 3, and transmits it to the interface 2 through the PCI bus 4. FIG. 5 is a system block diagram showing a third embodiment. In FIG. 5, the explanation of parts designated by the same reference numerals as those shown in FIG. 1 will be omitted. A list 14 and a transfer means 15 are provided in an interface 2. Information showing the first addresses and sizes of the divided blocks of data to be transferred is formed in the list 14 in the form of a list by a software 6, so that a list similar to that illustrated in the second embodiment is constituted. For instance, an explanation is given to a case where data is transferred from a VTR 1 to a memory 3. The transfer means 15 refers to the address of the destination of data transfer assigned to each of the divided blocks shown in the list 14 and transfers the data with the size assigned to each of the divided blocks, as one unit, to the above-mentioned address in a data area 7 in the memory 3 through the interface 2 from the VTR 1. Since the data is transmitted by the transfer means 15 (generally, this is referred to as a DMA transfer), the CPU 5 can perform other processings during that time, so that an extremely efficient operation can be provided to a user. Conversely, when the data is transferred to the VTR 1 from the memory 3, operations to be carried out are basically equal to those described in the second embodiment. FIG. 6 is a system block diagram showing a fourth embodiment . In FIG.6, components corresponding to those indicated by the same reference numerals shown in FIG. 1 will not be explained. A list 13 is formed in a memory 3 by a software 6 and can be made access to from a transfer means 15 provided in an interface 2. The contents of the list to be formed are similar to the form of the list shown in the second embodiment. When data is transmitted, the transfer means 15 refers to the contents of the list 13 and transmits the data without using a CPU 5, which is a similar way to that of the third embodiment. FIG. 7 is a system block diagram showing a first embodiment in accordance with the present invention. In the first embodiment in accordance with the present invention, an entire system construction is similar to that of the fourth embodiment illustrated in FIG. 6. The VTR 1 in FIG. 6 corresponds to a 4 × speed DVC deck 71 shown in FIG. 7. The interface 2 shown in FIG. 6 corresponds to a DVC-PCI interface 72 in FIG. 7. The 4 × speed DVC deck 71 can record and reproduce a DVC signal at speed four times as fast as an ordinary speed, and input and output DVC data for four frames for a period of one frame (1/30 second). Further, the 4 × speed DVC deck 71 corresponds to a DVC signal form and the capacity of the DVC signal for one frame is 120000 bytes (expressed as 120 kB, hereinafter). Therefore, the 4 × speed DVC deck 71 can input and output the data with the capacity of 480 kB for the period of one frame. The data supplied and received between the 4 × speed DVC deck 71 and the DVC-PCI interface 72 has a width of 8 bits and is temporarily stored in an FIFO 721 in the course of input and output. A bit width converting interface 722 is an interface interposed between the FIFO 721 for the data of 8-bit width and an FIFO 723 for the data of 32-bit width and converts the bit width of data inputted and outputted into 32 bits from 8 bits and vice versa. A PCI interface 724 is an interface for controlling the input and output of data between a PCI bus 4 and the FIFO 723 in FIG. 7. The PCI interface 724 has a function corresponding to that of the transfer means 15 illustrated in FIG. 6. The PCI interface 724 makes access to information corresponding to that of the list 13 in FIG. 7, so that it can obtains the destination of data transfer and a transfer data size and transmit data, synchronously with the 4 × speed DVC deck 71. The 4 × speed DVC deck 71 further generates a frame synchronizing signal 73 in order to take the synchronization with the transmission.of data. This signal is generated every period of one frame (1/30 second = about 33.3 ms) and inputted to the bit width converting interface 722 of the DVC-PCI interface 72. The bit width converting interface 722 refers to the frame synchronizing signal 73, generates a transfer synchronizing signal 74 as a new synchronizing signal and inputs the transfer synchronizing signal to the PCI interface 724. The PCI interface 724 refers to the transfer synchronizing signal 74 to input data to and output data from a PCI bus, so that the data can be transmitted between a computer operating in an asynchronous manner and a VTR operating in a synchronous manner. The above-mentioned procedure for transmitting the data will be more specifically described by using a timing chart in FIG. 8 and FIG. 7. Herein, a case where data is transmitted from a VTR is described as an example. Incidentally, when the data is transmitted to the VTR, the data can be also transmitted by using a similar procedure to that described above. In this case, it is to be understood that the addresses created in the list 13 are those of the start of data transfer, as stated above. A pulse 81 is equivalent to the frame synchronizing signal 73 and generated every 33.3 ms or so. During this period, data 82 for four frames is outputted from the 4 x speed DVC deck 71 and transferred to the FIFO 723 through the FIFO 721 and the bit width converting interface 722. The bit width converting interface 722 refers to the pulse 81 and generates a pulse 83. The pulse 83 is equivalent to the transfer synchronizing signal 74. When the PCI interface 724 receives a transfer request signal 86 from a CPU 5, the PCI interface 724 transfers data 841 to the PCI bus 4 simultaneously with the detection of the pulse 83. The data 841 shown in FIG. 8 includes a plurality of divided data blocks located within a range of the amount of data which can be transmitted in one unit transfer. At this time, the PCI interface 724 refers to the list 13 in the memory 3 and transfers the data having a prescribed capacity or size assigned to each of the data blocks as one unit to the designated address of the data area 7 in the memory 3. When the transfer of the plurality of data blocks to respective addresses which corresponds to one transfer request signal is completed, the PCI interface 724 generates an interrupt pulse 851. The CPU 5 detects the interrupt signal to thereby complete one transfer corresponding to one transfer request signal. A software 6 recognizes the size of the data whose transfer is completed. When the data having a necessary size or capacity is not completely transmitted, the software 6 forms again a list 13 to carry out a next transfer request. Upon receipt of the next request, data 842 and an interrupt pulse 852 seen in FIG. 8 are transferred in the same way as that described above. This procedure is repeated so that the transmission of data from the VTR 1 can be realized. In FIG. 7, although one FIFO 721 is employed, it is to be recognized that a selector switch 150 and a group of four FIFOs including FIFO 111 to FIFO 114 may be provided, as illustrated in FIG. 9 (A), the FIFOs may be switched for each frame or data may be assigned to the FIFOs 111 to 114 to transfer the data in accordance with a specific procedure. Otherwise, as illustrated in FIG. 9 (B), the FIFOs 111 to 114 may be connected to a plurality of VTRs 101 to 104. At this time, a PCI interface 140 sends information as to which FIFO the data is to be inputted to or outputted from and what bytes of data are inputted to or outputted from, to a bit width converting interface 120 as an FIFO switching command 160. Thus, the data is inputted and outputted between the group 110 of the FIFOs and an FIFO 130. The FIFO switching command 160 may be directly outputted to the bit width converting interface 120 from the PCI interface 140, as shown in FIGS. 9 (A) and 9 (B), or may be outputted to the bit width converting interface 120 through the FIFO 130 from the PCI interface 140 as in the case of the data. Further, although the frame synchronizing signal is outputted once from the 4 × speed DVC deck for the period of one frame, where the bit width converting interface is utilized so as to meet the frame synchronizing signals, it may be outputted a plurality of times for the period of one frame. In the list 13, one block 200 comprises the first address 201 of the end of data transfer, a data transfer size 202 and a transfer command 203 as shown in FIG. 10. The first address 201 and the data transfer size 202 are similar to those shown in FIG. 2 in the second embodiment. The transfer command 203 includes information such as a transfer direction (a direction for transferring data from the VTR 1 to the memory 3 or a direction opposite thereto), as to each time of what kB an interrupt signal is generated, or the switching of the above-mentioned FIFOs. For example, the address 201 of the end of data transfer and the data size 202 are expressed by decimal numbers. In the transfer command 203, as shown in FIG. 11, one bit 211 at the left end indicates a flag showing whether an interrupt is generated or not after a transfer instructed in the block 200 is completed (If the interrupt is generated, 1 is issued, and if the interrupt is not generated, 0 is issued). A second one bit 212 from the left end indicates a flag showing a direction for transmitting data (If the data is transmitted from the VTR to the memory, 1 is issued, and otherwise, 0 is issued). Third and fourth two bits 213 from the left end indicate the numbers (0 to 3)of the FIFOs. At this time, when the data of 60 kB which is the amount of data capable of being transferred at that time is divided into data blocks with the size of 4kB and the divided data blocks are transferred to an area including the addresses of the end of data transfer of 0 to 60000 in the memory 3 from the VTR, such a list as shown in FIG. 12 is to be formed. In this connection, information that a data unit which can be transferred at that time is 60 kB is a value got from the function prepared for the operating system as mentioned before. Parenthetically, the data of 60 kB is divided into the data blocks respectively having the size of 4kB in order to easily understand an instance in which the data is rearranged as will be described below. Since the amount of data which can be transferred is 60 kB, it is to be noted that only one data block of 60kB may be utilized without difficulty. In the above-mentioned example, although the construction of the data block is formed as illustrated in FIG. 11, it is to be understood that the data block may be constructed in any sequence or any form so long as the construction of the data block includes the address of the end of data transfer, the transfer data size and the required command. FIG. 13 is an explanatory view for explaining a method for changing the arrangement of data. The arrangement of the data inputted to or outputted from the VTR and the data inputted to and outputted from the memory can be changed by using the list employed for transferring the data. FIG.13 (A) shows an example of the method for rearranging the data. In FIG. 13 (A), data 130 is inputted to or outputted from the VTR, and data 140 is inputted to or outputted from the memory, respectively. The data 130 comprises video data parts 131 and 133 with the size of 8kB, and sound data parts 132 and 134 with the size of 4kB. The video data parts and the sound data parts are alternately arranged in the form of the data 130. The data 140 comprises a video data part 141 with the size of 16kB and a sound data part 142 with the size of 8kB. At this time, a list as illustrated in FIG. 13 (B) is created, so that the data is temporarily sent to a card memory from the VTR, and when the data is transmitted from the card memory to a main memory, the arrangement of the video data and the sound data can be varied during the transmission of the data. Therefore, since it is not necessary to change the arrangement of the data in the main memory, which is different from the prior art, a processing time after the data is transmitted to the main memory can be saved. Herein, the arrangement of the data shown in FIG. 13 is simplified for readily understanding it. On the other hand, also when the data is transmitted in an opposite direction to the above, in other words, when the data is transmitted from the main memory to the card memory, the arrangement of the video data and the sound data can be modified in the course of its transmission in accordance with a fundamentally equal manner. However, when the data is transmitted in the opposite direction, the above mentioned processing time after the data is transmitted is not saved, but a processing time before the transmission of the data can be saved. Now, a description will be further made from the viewpoint that processing time before the data is transmitted can be decreased. Specifically stated, for instance, when the data is outputted from the computer to the VTR and the arrangement of the data needs to be changed, the data has been conventionally rearranged temporarily in the main memory of the computer, and then, outputted to the VTR through a card memory. Accordingly, before the data is transmitted from the main memory to the card memory, a time for a preparation processing to change the arrangement of the data has been needed. According to the above-mentioned embodiment or the first embodiment, even when the data is transmitted in the opposite direction, that is, from the main memory to the card memory, the processing time for changing the arrangement of the data before its transmission , which has been conventionally required, is not desirably needed. Therefore, as mentioned above, when the data is transmitted in the opposite direction, the processing time before the transmission of the data can be advantageously saved. Incidentally, although in the above mentioned embodiment, the arrangement of the data is varied between the VTR and the memory, it will be noted that the present invention is not limited thereto, and for example, the arrangement of the data transmitted through a network can be varied between the memory and the network. Further, a medium is created on which is recorded a program for carrying out the functions (or steps) of all or a part of the above-mentioned means (or steps) by the computer. The medium is utilized so that the functions of various kinds of means (or steps) mentioned above can be simply performed by the computer. According to the construction of the present invention stated above, the data can be efficiently transmitted at high speed when the data to be transmitted is inputted or outputted through the network, or when the data is inputted or outputted by the recording and reproducing device such as the VTR and so on, without depending on a system configuration. Further when other work such as an editing operation is carried out during the transmission of the data, an error in fetching the data does not occur and therefore, the reliability of the invention is improved. As apparent from the foregoing description, according to the above mentioned embodiments of the present invention, such advantages or effects as described below can be realized. (1) The transfer capacity pertinent to a system can be employed at its maximum without depending on a system configuration. (2) A high speed transmitter can be realized which can be connected to a high speed recording and reproducing VTR, a plurality of VTRs or a network and is high in its efficiency and reliability without dropping data out of frames or the like. (3) The arrangement of data can be changed between the VTR or the network and the memory and the data does not need to be rearranged in the memory, so that a processing time can be shortened.

Claims: An apparatus for transmitting data comprising: an input and output means (2, 72) for inputting and outputting data including at least one of video data, sound data and/or auxiliary data as first data; a memory (3) for storing the first data; a transmitting means (4) for transmitting the data between said input and output means (2, 72) and said memory (3); a first controller (5) for controlling the transmission of the data between said input and output means (2, 72) and said memory (3); a second controller (6) for detecting the amount of data which can be transferred as one unit transfer through said transmitting means (4) when said first data is transmitted, and controlling at least said input and output means (2, 72), said memory (3), and said first controller (5) so as to divide the first data into data blocks respectively having the size or capacity which does not exceed said amount of data and respectively transmit a single or plurality of the divided data blocks as said one unit to be transferred when the first data exceeds said amount of data which can be transferred; a list forming means for forming a list (13, 14) showing at least the respective amount of data of the data blocks, which is used when the data is divided into the data blocks; a transfer means (8, 15) in the input and output means (2, 72) or the second controller (6) for transferring the first data divided into the data blocks to said transmitting means (4) based on the contents of said list (13, 14), characterized in that said apparatus comprises an external data input and output device (1, 71, 100-104) and, said input and output means (2, 72) comprises: a first buffer (721, 110) for temporarily storing said first data; a second buffer (723, 130) for temporarily storing said first data having a bit width different from that of the data in the first buffer (721, 110); a first interface (722, 120) for converting the bit width between the first buffer (721, 110) and the second buffer (723, 130) and inputting and outputting the first data; and a second interface (724, 140) for inputting and outputting the first data between the second buffer (723, 130) and the transmitting means (4) in accordance with a signal from the transmitting means (4); wherein said input and output means (2, 72) is also connected to said external data input and output device (1, 71, 100, 101, 102, 103, 104) and said first data is recorded on said external data input and output device (1, 71, 100, 101, 102, 103, 104) and/or reproduced by said external data input and output device (1, 71, 100, 101, 102, 103, 104); wherein said external data input and output device (1, 71, 100, 101, 102, 103, 104) generates a first synchronizing signal (73, 81); wherein said first interface (722, 120) inputs and outputs the data synchronously with the first buffer (721, 110) in accordance with the generated first synchronizing signal (73, 81) and further generates a second synchronizing signal (74, 83) relative to said second interface (724, 140); and wherein said second interface (724, 140) inputs and outputs the data synchronously with said transmitting means (4) in accordance with the generated second synchronizing signal (74, 83), and further, inputs and outputs the data to said transmitting means (4) when a data transfer is requested from the transmitting means (4). An apparatus for transmitting data according to claim 1, wherein assuming that N is an integer not smaller than 2, said data input and output device (1, 71, 100, 101, 102, 103, 104) generates one synchronizing signal (73, 81) during the period of one frame and further inputs and outputs the first data for N frames during the period of one frame. An apparatus for transmitting data according to claim 1 or 2, wherein said external data input and output device (1, 71, 100, 101, 102, 103, 104) is a recording and reproducing device (71, 100) capable of recording and reproducing the data of a DVC form at a speed four times as fast as an ordinary speed. An apparatus for transmitting data according to any of claims 1 to 3, wherein said input and output means (2, 72) is an interface (72) for converting data of a DVC form into data of a PCI bus form or data of the PCI bus form into data of the DCV form.

Inventors: HAMAI SHINJI, KASE HIROSHI, MORIOKA YOSHIHIRO, HAMAI, SHINJI, KASE, HIROSHI, MORIOKA, YOSHIHIRO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1997
Main classification: G06F13
IPC codes: H04N5, G11B20, G06F13, H04L29