A voltage regulator

Abstract: A voltage regulator circuit includes: a first MOS transistor 12 coupled between a voltage supply line and an output node 44, the first MOS transistor 12 providing a stable voltage on the output node 44; a source follower 24 coupled to a gate of the first MOS transistor 12; an amplifier 38 coupled to a gate of the source follower 24 for controlling the response of the first MOS transistor 12; negative feedback circuitry coupled between the output node 44 and the amplifier 38, the feedback circuitry providing feedback to the amplifier 38; a current conveyer 46 coupled to the first MOS transistor 12; and positive feedback circuitry 26 coupled between the current conveyer 46 and the source follower 24.

Description: FIELD OF THE INVENTION This invention generally relates to electronic systems and in particular it relates to voltage regulators. BACKGROUND OF THE INVENTION The function of a voltage regulator is to take a varying input voltage supply and generate a stable output voltage. The efficiency of modern power supply systems, especially battery operated ones, is directly related to the useable operating voltage and current over head required by the system's voltage regulator. The useable operating voltage is called the "drop-out" voltage, which is the difference between the input and output voltages of the regulator while the regulator still maintains regulation. The smaller this difference, the more efficient the system. Additionally, batteries can supply only a finite amount of charge, so the more quiescent current the regulator uses (which is wasted current as far as the system is concerned), the less life the battery will have and therefore the system will be less efficient. EP-A-0316781 discloses a voltage regulator circuit comprising: a first transistor coupled between a voltage supply line and an output node; an amplifier coupled to a control region of the first transistor; and negative feedback circuitry arranged for providing negative feedback to the amplifier. SUMMARY OF THE INVENTION According to the invention there is provided a voltage regulator circuit comprising: a first transistor coupled between a voltage supply line and an output node, the first transistor being arranged for providing a stable voltage on the output node; a source follower coupled to a control region of the first transistor; an amplifier coupled to a control region of the source follower for controlling the response of the first transistor; negative feedback circuitry coupled between the output node and the amplifier, the negative feedback circuitry being arranged for providing feedback to the amplifier; a current conveyor coupled to the first transistor; and positive feedback circuitry coupled between the current conveyer and the source follower. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be further described by way of example, with reference to the accompanying drawings in which: the only Figure is a schematic circuit diagram of a preferred embodiment low drop-out (LDO) voltage regulator with PMOS pass element. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Referring to Fig. 1, a circuit diagram of a low drop-out (LDO) voltage regulator with PMOS pass element is illustrated. This preferred embodiment allows an LDO voltage regulator to be compensated while only consuming small currents and substantially improving the load regulation. The circuit includes PMOS pass device 12 (PMOS transistor); PMOS transistor 14; PNP transistors 16 and 18; NMOS transistors 20 and 22; NMOS transistor 24; positive feedback circuit 26 which includes NMOS transistor 28, capacitor 30, and resistor 32; current source 34; PMOS transistor 36; error amplifier 38 (operational amplifier), resistors 40 and 42, voltage reference V REF , output voltage V OUT , and input voltage V IN . The operation of the device is explained with reference to the preferred embodiment shown in Figure 1. The output voltage V OUT is regulated by pass transistor 12. The error amp 38, which is an operational amplifier, controls transistor 12 through transistor 24. When the input voltage V IN changes or the current being drawn from an external load at node 44 changes, the output voltage V OUT begins to change causing the voltage across the second resistor 42 to change. The error amp 38 then adjusts the gate voltage of transistor 24 so that the output voltage V OUT is maintained in the desired range. Current mirror transistor 14 monitors the current of transistor 12. In the preferred embodiment, the ratio of transistor 14 to transistor 12 is such that the current in transistor 14 is only a small fraction of the current in transistor 12 (for example 1:1000). PNP transistors 16 and 18 together with NMOS transistors 20 and 22 form a current conveyor 46 which forces the current in PNP transistors 20 and 22 to be the same. The current conveyor ensures that the V DS and V GS of transistors 12 and 14 are the same. Since the V GS of transistors 12 and 14 are the same, the currents in PNP transistors 16 and 18 are the same. The current in the current conveyor 46 is equal to the current in transistor 14. The current conveyor current is mirrored to transistor 28. Transistor 28 is larger than transistors 20 and 22 in order to provide sufficient current for the source follower transistor 24 which drives output transistor 12. Transistor 24 is an isolated natural NMOS with a low V T . Resistor 32 and capacitor 30 provide frequency compensation for the positive feedback to make sure the positive feedback never overcomes the negative feedback so that the circuit does not oscillate. The current conveyor performs two functions. First, it ensures that the external pole and the internal pole remain separated for stability. Second, the positive feedback improves the load regulation by modulating the V GS of transistor 24 proportionately with the V GS of transistor 12. This compensates the output impedance of the circuit. If there is no output current at output node 44, there will be no current mirrored to transistor 28. Therefore, in order to make sure that there is some current in transistor 24, current source 34 pulls on transistor 24 so that the circuit works where there is no load at output node 44. In the preferred embodiment, current source 34 provides only a small current on the order of one micro amp. With this small current, the power consumption of the circuit will be extremely small when there is no load on the output. This is an important feature for battery powered devices. Transistor 36 is used to enhance the slew rate of the circuit. Transistor 36 allows the circuit to come back into regulation quickly when there is a rapid change in load. Transistor 36 turns on and helps the transient response when going from no load at output node 44 to a full load or some load condition at node 44.

Claims: A voltage regulator circuit comprising: a first transistor (12) coupled between a voltage supply line and an output node (44), the first transistor being arranged for providing a stable voltage on the output node; a source follower (24) coupled to a control region of the first transistor; an amplifier (38) coupled to a control region of the source follower for controlling the response of the first transistor; negative feedback circuitry (40,42) coupled between the output node and the amplifier, the negative feedback circuitry being arranged for providing feedback to the amplifier; a current conveyor (46) coupled to the first transistor; and positive feedback circuitry (26) coupled between the current conveyer and the source follower. The circuit of claim 1 further comprising: a current source (34) coupled to the source follower. The circuit of claim 1 or claim 2, wherein the first transistor is a MOS transistor. The circuit of claim 1, claim 2 or claim 3, wherein the current conveyer comprises: a second transistor (14) having a control region coupled to the control region of the first transistor; a first bipolar transistor (16) coupled to the first transistor; a second bipolar transistor (18) coupled to the second transistor, a base region of the second bipolar transistor coupled to a base region of the first bipolar transistor; a third transistor (20) coupled to the first bipolar transistor; and a fourth transistor (22) coupled to the second bipolar transistor and to the base region of the first bipolar transistor, a control region of the fourth transistor coupled to a control region of the third transistor and to the first bipolar transistor. The circuit of claim 4, wherein at least one of the second, third and fourth transistors is a MOS transistor. The circuit of any of claims 1 to 5, wherein the positive feedback circuitry comprises: a positive feedback transistor (28) coupled to the source follower; a resistor (32) coupled between the current conveyer and a control region of the positive feedback transistor; and a capacitor (30) coupled to the control region of the positive feedback transistor. The circuit of claims 1 to 6, wherein the negative feedback circuitry comprises: a first resistor (40) having a first end coupled to the output node and a second end coupled to the amplifier; and a second resistor (42) coupled to the second end of the first resistor. The circuit of any of claims 1 to 7 further comprising: a slew rate enhancement transistor (36) coupled to the source follower, wherein a control region of the skew rate enhancement transistor is coupled to the output of the amplifier.

Inventors: BORDEN ROBERT B, CORSI MARCO, KAY MICHAEL R, RINCON GABRIEL A, SALAMINA NICOLAS, BORDEN, ROBERT B., CORSI, MARCO, KAY, MICHAEL R., RINCON, GABRIEL A., SALAMINA, NICOLAS
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1997
Main classification: G05F3
IPC codes: G05F3, G05F1