Gas discharge lamp ballast circuit with complementary converter switches

Abstract: A ballast circuit for a gas discharge lamp comprises a resonant load circuit incorporating the gas discharge lamp (18) and including a resonant inductance (L R ) and a resonant capacitance (C R ). A d.c.-to-a.c. converter circuit induces an a.c. current in the resonant load circuit. The converter circuit comprises first and second converter switches (S n S p ) serially connected in the foregoing order between a bus conductor (12) at a d.c. voltage and a reference conductor (14), and being connected together at a common node (16) through which the a.c. load current flows. The first and second converter switches comprise respective interconnected control nodes respective reference nodes interconnected together at a common node. The voltage between each control node and associated reference node determines the conduction state of the associated switch. A voltage-limited energy source (34) is connected between first and second nodes (41,42). The first node (41) is connected to the bus conductor through a first bootstrap capacitor (C 1 ), and the second node (42) is connected to the reference conductor through a second bootstrap capacitor (C 2 ). A bridge network (22) is connected between the first and second nodes and has first and second input nodes (26,30) on which respective first and second input signals are applied. First and second output nodes (24,28) are respectively connected to the common and control nodes (16,29) so as to control the switching state of the converter switches. The first and second pairs of gate control switches (P 1 , N 1 ; P 2 , N 2 ) are arranged to cause repetitive cycling through various states the converter switches, so as to allow residual energy from the resonant inductor to cause replenishing of the energy source.

Description: The present invention relates to a ballast circuit for a gas discharge lamp which includes a d.c.-to a.c. converter for supplying a.c. current to a resonant load circuit, and, more particularly, to such a ballast circuit employing a pair of complementary switches in the d.c.-to-a.c. converter. Ballast circuits for gas discharge lamps which include an d.c.-to a.c. converter for supplying a.c. current to a resonant load circuit are known. One such converter can be seen in US S 430 638. Typically, such circuits include a pair of non-complementary switches in the d.c.to-a.c. converter. For example, it is common to use a pair of identical, n-channel enhancement mode MOSFETs as the switches. Each of such non-complementary MOSFETs must be controlled by a separate gate-to- source (or control) voltage. This requires level shifting of voltage to couple a single control signal to each of the gate-to-source voltages of the pair of MOSFETS. Such level shifting can be accomplished by a transformer or by conventional bootstrapping means. The transformer method works well at high speeds, but is costly and hard to control. The bootstrapping method, usually implemented by an Integrated Circuit (IC), has good control capability, but is unable to work at high speeds. Therefore, the invention seeks to provide a ballast circuit for a gas discharge lamp that overcomes the foregoing drawbacks. Accordingly, the invention seeks to provide a gas discharge ballast circuit of the type including a pair of switches of a d.c.-to-a.c. converter, which circuit achieves good control capability as well as the ability to work at high speeds. The invention further seeks to provide a ballast circuit of the foregoing type that is suitable for integration into an IC. According to the invention, there is provided a ballast circuit for a gas discharge lamp, comprising: (a) a d.c.-to-a.c. converter circuit comprising: (i) first and second converter switches serially connected in the foregoing order between a bus conductor at a d.c. voltage and a reference conductor, and being connected together at a common node through which said a.c. load current flows; (ii) said first and second converter switches each comprising a control node and a reference node, the voltage between such nodes determining the conduction state of the associated switch; (iii) the respective control nodes of said first and second converter switches being interconnected; and (iv) the respective reference nodes of said first and second converter switches being connected together at said common node; characterised by (b) a resonant load circuit coupled to said converter circuit said converter circuit inducing an AC current in said load circuit, said load circuit incorporating the gas discharge lamp and including a resonant inductance and a resonant capacitance ; (c) a voltage-limited energy source connected between first and second nodes; (d) said first node being connected to said bus conductor through a bootstrap capacitor, and said second node being connected to said reference conductor through a bootstrap capacitor; and (e) a bridge network being connected between said first and second nodes and having (i) first and second input nodes on which respective first and second input signals are applied; and (ii) first and second output nodes respectively connected to said common and control nodes so as to control the switching state of said converter switches; (f) an oscillator for providing said first and second input signals; (g) said bridge network being arranged to cause repetitive cycling through at least the following states of said first and second converter switches respectively being: (i) on and off; (ii) turned off and already off, and residual energy of said resonant inductance causing a shift in energy from one of said bootstrap capacitors to the other of said bootstrap capacitors via said energy source, thereby replenishing said source with energy; (iii) off and on; (iv) already off and turned off, and residual energy of said resonant inductance causing a shift in energy from said other of said bootstrap capacitors to said one of said bootstrap capacitors via said energy source, thereby replenishing said source with energy. The invention will now be described in greater detail, by way of example, with reference to the drawings, in which: Fig. 1 is a schematic diagram, partially in block form, of a ballast circuit for a gas discharge lamp which employs complementary switches in a d.c.-to-a.c. converter, in accordance with the invention. Figs. 2A and 2B respectively show first and second input signal 0, and 0, used in the circuit of Fig. 1. Fig. 1 shows a ballast circuit 10 in accordance with the invention. A d.c. bus voltage VBus is applied to bus conductor 12 with respect to a reference conductor 14. The potential of reference conductor 14 is not necessarily at ground; it simply is a potential less than that of bus conductor 12. As shown, ballast circuit 10 employs a pair of switches S N and S p for implementing a d.c.-to- a.c. conversion. Switch S N may be an n-channel, enhancement mode MOSFET, while switch S p may be a p-channel, enhancement mode MOSFET. Such switches are, therefore, complementary to each other. The sources of MOSFET switches S N and S P are interconnected at common node 16, which node is alternately connected to bus conductor 12 and then to reference conductor 14, and back to bus conductor 12, and so on. Other source-to-source connected MOSFET pairs, or corresponding Bipolar Junction Transistors, could be used if desired. Converter switches S N and S P supply a.c. current to a resonant load circuit comprised of a resonant inductor L R and a resonant capacitor C R , which capacitor is shunted by lamp 18, such as a fluorescent lamp. A d.c. blocking capacitor 20 is also provided in the resonant load circuit. Converter switches S N and S p are, in turn, controlled by a bridge network 22 preferably formed of drain-connected, complementary conduction mode MOSFETS, which control the gates of the converter switches. Specifically, bridge network 22 may comprise a first pair of such MOSFETs designated P 1 and N 1 to represent p-channel and n-channel, enhancement mode MOSFETs, respectively; and a second pair of such MOSFETs designated P 2 and N 2 for the same reason. As will be appreciated from Fig. 1, each pair P 1 , N 1 and P 2 , N 2 of MOSFETs have respective interconnected drains and interconnected gates. The drains of pair P 1 , N 1 are connected to a first output node 24 of bridge network 22, which is connected to common node 16; the gates of such pair are connected to a first input node 26 of bridge network 22. Similarly, the drains of pair P 2 , N 2 are connected to a second output node 28 of bridge network 22, which is connected to a common control node 29 of the converter switches; the gates of such pair are connected to a second input node 30 of bridge network 22. Preferably, pairs P 1 , N 1 and P 2 , N 2 of bridge network 22 each comprise drain-connected CMOS transistors, which are commonly available. A first input signal is supplied to first input node 26 by an oscillator 32, via a, e.g., non-inverting buffer 32A; the first input signal is designated by  1 in the block for the oscillator. A second input signal is supplied to second input node 30, via a, e.g., non-inverting buffer 32B, the second input signal being designated by  2 in the block for the oscillator. The first and second input signals will be described in detail below. In accordance with an aspect of the invention, an energy source 34 is provided for supplying energy both to power oscillator 32 and to supply, via buffers 32A and 32B, the energy needed to control switch pairs P 1 , N 1 and P 2 , N 2 . As will be detailed below, during certain modes of operation of converter switches S N and S P, residual energy in resonant inductor L R is used to replenish energy dissipated by source 34 in performing these powering functions. Energy source 34 may comprise a capacitor 36 and a Zener diode 38. Beneficially, the circuitry inside of dashed-line box 39 described so far can be incorporated into an integrated circuit (IC), and the converter switches themselves, enclosed in dashed-line box 40 can also be incorporated into the same IC in a hybrid or monolithic form. Each of gate control switch pairs P 1 , N 1 and P 2 , N 2 are connected between a first node 41 at their upper shown-portion, and a second node 42 at their lower-shown portion. A first bootstrap capacitor C 1 and a bias resistor 44 are connected between first node 41 and bus conductor 12. A second bootstrap capacitor C 2 and a bias resistor 46 are connected between second node 42 and reference conductor 14. Bootstrap capacitors C 1 and C 2 preferably perform dual functions. One function is to act as a conventional snubber capacitor for the purpose of causing converter switches S N and S P to switch softly, as opposed to abruptly, which considerably reduces energy dissipation in the switches when they change state. The second function of the bootstrap capacitors is a bootstrapping function, wherein residual energy from resonant inductor L R is used to change the states of charge of the bootstrap capacitors, and in the process to replenish energy of source 34 used in powering oscillator 32 and buffers 32A and 32B. Bootstrap capacitors C 1 and C 2 , therefore, are preferably sized to perform the bootstrap function, which may require a larger size than is required merely to perform the snubbing function. The bootstrap operation of the capacitors is detailed below. Figs. 2A and 2B respectively show first and second input signals  1 and  2 produced by oscillator 32 of Fig. 1. These signals vary between "1" (or high) and "0" (or low), which refer to logic levels, whereby logic level "1" may be 5 volts, for example. In accordance with the invention, oscillator 32 (Fig. 1) provides input signals pairs  1 ,  2 that repetitively cycle through at least the four illustrated states of 1-0, 1-1, 0-1 and 0-0. These states respectively occur during time periods T 1 , T 2 , T 3 and T 4 . As can be seen in Fig. 2B, after time period T 4 , time period T 1 begins again. One or more other time periods could be interposed among time periods T 1 -T 4 , and represent different input signal pairs  1 ,  2 if desired. Operation of ballast circuit 10 of Fig. 1 is now described during each of time periods T 1 -T 4 . The following table identifies operating states for input signals  1 and  2 , and the conduction states of transistors P 1 , N 1 , P 2 and N 2 of bridge network 22. After the table, the conduction states of converter switches S N and S P , and the bootstrap operation of capacitors C 1 and C 2 , are described. During time period T 1 , converter switch S N is on (or conducting) and switch S P is off. During this time, common node 16 is connected to bus conductor 12 so as to be at V BUS , which voltage is impressed across bootstrap capacitor C 2 by virtue of switch N 1 being on. Voltages across the capacitors in Fig. 1 are from top-to-bottom, i.e. the voltage V36 is measured from node 41 to node 42, the voltage for capacitor C1 is measured from node 12 to node 41, and the voltage for capacitor C2 is measured from node 42 to node 14. Additionally, bus voltage V BUS is impressed across the serially connected capacitors C 1 , 36 and C 2 . With voltage V 36 being the top-to-bottom voltage across energy source capacitor 36, the foregoing capacitors then respectively have voltages across them of -V 36 of typically -12 volts for capacitor C 1 , V 36 of typically 12 volts for capacitor 36, and V BUS for capacitor C 2 . During time period T 2 , converter switch S N is turned off, with switch S P remaining off as it was in time period T 1 . Residual energy in resonant inductor L R causes current to flow through such inductor from left to right in Fig. 1, such current passing upwardly through second bootstrap capacitor C 2 , through switch N 1 which is on at this time, and back to resonant inductor L R . Meanwhile, bus voltage V BUS continues to be impressed across the serial combination of capacitors C 1 , 36 and C 2 . As a result, the voltage on capacitor C 2 changes from V BUS to -V 36 of typically -12 volts, while the voltage on capacitor C 1 changes from -V 36 of typically -12 volts to V BUS . In this process, charge from capacitor C 2 is transferred via energy source capacitor 36 to capacitor C 1 . However, some of the charge from capacitor C 2 is retained by capacitor 36, so as to replenish energy used in powering oscillator 32 and buffers 32A and 32B. In the next time period T 3 , converter switch S N remains off and switch S P is turned on. The voltages across serially connected capacitors C 1 , 36 and C 2 remain as set in the preceding time period T 2 . In time period T 4 , switch S N remains off and switch S P is turned off. During this time residual energy in resonant inductor L R causes current to flow through such inductor from right to left in Fig. 1. With switch P 1 being on at this time, such current from resonant inductor L R flows from node 16 to node 24 and upwardly through switch P 1 to pass through bootstrap capacitor C 1 Specifically, the voltage of capacitor C 1 changes from V BUS as set in time period T 2 to -V 36 of typically -12 volts. Since bus voltage V BUS is impressed across the serial combination of capacitors C 1 , 36 and C 2 , the voltage of capacitor C 2 changes in from -V 36 of typically -12 volts set in time period T 2 , to V BUS , while capacitor V 36 remains at a nearly constant voltage (e.g. 12 volts). In the process of capacitor C 2 becoming charged to V BUS , charge is transferred from capacitor C 1 to capacitor C 2 . Some charge from capacitor C 1 is absorbed by energy source capacitor 36 to replenish energy dissipated in powering oscillator 32 and buffers 32A and 32B. In the foregoing manner, energy source 34 is supplied with residual energy from resonant inductor L R during switching periods (e.g., T 2 , T 4 ) when one converter switch is already off and the other is turned off. To produce the waveforms shown in Fig. 2 for first and second input signals  1 and  2 , oscillator 32 may comprise a conventional square-wave generator for first input signal  1 , such as a commonly available 555 IC timer operating in a 50 percent duty ratio mode. To produce second input signal  2 , a delay circuit from first signal  1 , such as an R-C (resistive-capacitive) circuit (not shown) can be used to provide a delay, followed by a Schmitt trigger to square up the signal. Exemplary component values for ballast circuit 10 of Fig. 1 are as follows for a fluorescent lamp 18 rated at 25 watts, with a d.c. bus voltage of 150 volts: Resonant inductor L R 800 micro henries Resonant capacitor C R 7.7 nanofarads D.c. blocking capacitor 20 220 nanofarads Bootstrap capacitors C 1 and C 2 , each 680 picofarads Bias resistors 44 and 46, each 100k ohms Zener diode 38 12 volts Energy source capacitor 36 1 microfarad Additionally, converter switch S N may be an IRF610, n-channel, enhancement mode MOSFET, sold by International Rectifier Company, of El Segundo, California; converter switch S P , an IRF9610, p-channel, enhancement mode MOSFET also sold by International Rectifier Company; gate control switch pairs P 1 , N 1 and P 2 , N 2 , each 4000-series pair of drain-connected CMOS transistors, such as sold by Motorola of Phoenix, Arizona, or available as IRF9Z10-IRFZ10 CMOS pairs sold by International Rectifier Company. Finally, exemplary times T 1 , T 2 , T 3 and T 4 used by oscillator 32 are, respectively, 6.5 microseconds, 1 microsecond, 6.5 microseconds, and 1 microseconds. The foregoing describes a gas discharge ballast circuit of the type including a pair of switches of a d.c.-to-a.c. converter. The ballast circuit achieves good control capability as well as the ability to work at high speeds.

Claims: A ballast circuit (10) for a gas discharge lamp (18), comprising: (a) a d.c.-to-a.c. converter circuit comprising: (i) first (S N ) and second (S p ) converter switches serially connected in the foregoing order between a bus conductor (12) at a d.c. voltage and a reference conductor (14), and being connected together at a common node (16) through which said a.c. load current flows; (ii) said first and second converter switches (S N , S P ) each comprising a control node and a reference node, the voltage between such nodes determining the conduction state of the associated switch; (iii) the respective control nodes of said first and second converter switches (S N , S P ) being interconnected; and (iv) the respective reference nodes of said first and second converter switches (S N , S p ) being connected together at said common node (16); characterised by (b) a resonant load circuit coupled to said converter circuit, said converter circuit inducing an AC current in said load circuit, said load circuit incorporating the gas discharge lamp and including a resonant inductance (L R ) and a resonant capacitance (C R ); (c) a voltage-limited energy source (34) connected between first and second nodes; (d) said first node being connected to said bus conductor through a bootstrap capacitor (C 1 ), and said second node being connected to said reference conductor through a bootstrap capacitor (C 2 ); and (e) a bridge network (22) being connected between said first and second nodes and having: (i) first (26) and second (30) input nodes on which respective first and second input signals are applied; and (ii) first (24) and second (28) output nodes respectively connected to said common and control nodes so as to control the switching state of said converter switches; (f) an oscillator (32) for providing said first and second input signals; (g) said bridge network (22) being arranged to cause repetitive cycling through at least the following states of said first and second converter switches (S N , S P ) respectively being: (i) on and off; (ii) turned off and already off, and residual energy of said resonant inductance causing a shift in energy from one of said bootstrap capacitors to the other of said bootstrap capacitors via said energy source, thereby replenishing said source with energy; (iii) off and on; (iv) already off and turned off, and residual energy of said resonant inductance (L R ) causing a shift in energy from said other of said bootstrap capacitors to said one of said bootstrap capacitors via said energy source, thereby replenishing said source with energy. The ballast circuit of claim 1, wherein said oscillator (32) is arranged to cause repetitive cycling between first input signal-second input signal pairs of at least high-low, high-high, low-high, and low-low states. The ballast circuit of claim 1 or 2, wherein said bridge circuit comprises: (a) a first pair (P 1 , N 1 ) of gate control switches connected between said first and second nodes, having complementary conduction modes which change in response to a first input signal ( 1 ) applied to commonly connected control nodes of said switches, and being connected together serially at said first output node; and (b) a second pair (P 2 , N 2 ) of gate control switches connected between said first and second nodes, having complementary conduction modes which change in response to a second input signal ( 2 ) applied to commonly connected control nodes of said switches, and being connected together serially at said second output node. The ballast circuit of claim 3, wherein said first and second pairs of gate control switches comprise drain-connected CMOS transistors, with like-conduction mode transistors being connected to said first node. The ballast circuit of any preceding claim, further including means (44, 46) to power said oscillator (32) and to supply power to control said bridge network (22) from said energy storage source. The ballast circuit of claim 5, wherein said bridge network (22) and said oscillator (32) are contained in an integrated circuit (39). The ballast circuit of any one of claims 1 to 5, wherein said first and second pairs of control switches (N 1 , P 1 , N 2 , P 2 ) and said oscillator are contained in an integrated circuit (39, 40). The ballast circuit of Claim 6, wherein said energy source contains a Zener diode (38) for voltage limiting purposes, said Zener diode (38) also being contained in said integrated circuit (39). The ballast circuit of Claim 6, wherein said first and second converter switches (N 1 , P 1 , N 2 , P 2 ) are also contained in said integrated circuit (39).

Inventors: NERONE LOUIS ROBERT, NERONE, LOUIS ROBERT
Applicants: GEN ELECTRIC, GENERAL ELECTRIC COMPANY
Application year: 1997
Main classification: H05B41
IPC codes: H05B41