Method of manufacturing a grid array semiconductor package

Abstract: A method for manufacturing a column grid array semiconductor package (10,210) may include the steps of providing a substrate material (14,114,214) having a first side (16,116) and a second side (18), forming a plurality of holes (36,136,236) in the substrate (14,114,214), forming contacts (24,124) on the first surface (16,116) of the substrate (14,114,214), filling the plurality of holes (36,136,236) with a conductive material (32,132,232) to an extent that an extension portion (28,128,228) is formed on the second side (18) of the substrate (14,114,214) to which an electrical contact may be made. The extension portion (28,128,228) may be coated with a capping material (40,140,240). The holes (36,136,236) may be filled with the conductive material (32,132,232) by forming a resist layer (146,246) over the hole (36,136,236) on the first side (16,116) of the substrate (14,114,214) and filling the holes (36,136,236) with the conductive material (32,132,232). The resist (146,246) may then be removed.

Description: TECHNICAL FIELD OF THE INVENTION This invention relates generally to the field of integrated circuits, and more particularly to grid arrays for semiconductor packaging. BACKGROUND OF THE INVENTION Many modern electronic systems incorporate various modular electronic components. For example, personal computers may include modular electronic components in the form of dynamic random access memory units. Each of the modular electronic components may include an integrated circuit fabricated on a semiconductor substrate. Each modular electronic component may be coupled to the electronic system by a series of pins extending in a predetermined sequence from a body of the modular electronic component. The pins may be coupled to leads of a leadframe and external leads or balls may be coupled to the electronic system. As the density of devices on integrated circuits has continued to increase, the number of leads and traces required for an integrated chip have also increased. At the same time, the size of the integrated circuit chips has in many instances decreased. To help handle the increased density and smaller size, ball grid arrays ("BGA's") were developed. A ball grid array is a type of package for integrated circuits in which one or more integrated circuit chips are mounted on a top substrate surface, and electrical connection is made to an electrically conductive material, such as the printed circuit board, by an array of small solder balls located on the surface of the substrate opposite from the integrated circuit chip. Traces on the chip side of the substrate may be electrically connected to the solder balls by through-holes which have been electrically plated. A number of difficulties may be experienced with BGAs because of the different coefficients of thermal expansion of the various components. This and high stresses in some areas have caused some of the solder balls to crack and display other problems. Furthermore, a typical BGA operation requires extreme care in locating and attaching the solder balls to the plating of the through-holes on the side of the substrate opposite the chip. To help alleviate some of the problems with the solder balls cracking and high stress areas, an underfill is sometimes placed around the solder balls and between them. Positioning the underfill around the solder balls, however, presents an extra process step and may involve a difficult operation. EP 0,536,418 disclosed a semiconductor device which is configured so that circuit patterns formed on both sides of a copper-clad double-sided laminated board are connected to each other by through-holes. IC chips are mounted on the front side and external-connection terminals are connected on the reverse side. The devices are manufactured by forming copper core bumps on circuit patterns formed on a circuit board by plating using resist patterns. SUMMARY OF THE INVENTION Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. The invention can provide a column grid array for semiconductor packaging and methods that substantially eliminate or reduce disadvantages and problems associated with the previously developed packaging grid arrays. According to one aspect, a method of manufacturing a column grid array semiconductor package is provided that includes the steps of providing a substrate material; coating the substrate material on a first side with a first conductive material; forming a plurality of holes through the substrate and the first conductive material; laminating a resist over the first conductive material and over the opening of the plurality of holes; exposing the resist to a desired pattern; applying a second conductive material into the plurality of holes from the uncovered second side of the substrate to build columns in each hole with an extension portion formed that extends beyond the second side of the substrate; developing the resist; etching the first conductive material to form the desired contact pattern; and removing the resist. A technical advantage of the present invention is that the column grid array may be manufactured without requiring soldered balls thereby eliminating lead (Pb) in the system. According to another aspect, a flexible substrate may be used which allows reel-to reel processing. According to another aspect, an underfall may be conveniently provided during substrate manufacture. BRIEF DESCRIPTION OF THE DRAWINGS Exemples of the invention are described hereinafter, with reference to the accompanying drawings, in which: FIGURE 1 is a schematic elevational view of a column grid array semiconductor package according to the present invention; FIGURE 2 is a detail of a portion of FIGURE 1 in perspective view; FIGURES 3-7 are schematic diagrams showing steps in manufacturing a column grid array semiconductor package according to the present invention; and FIGURE 8 is a cross-sectional schematic of a column grid array according to the present invention. DETAILED DESCRIPTION OF THE INVENTION The present invention and its advantages are best understood by referring to FIGURES 1 through 8 of the drawings, like numerals being used for like and corresponding parts of the various drawings. FIGURE 1 is a schematic cross-sectional view of a column grid array semiconductor package 10 according to the present invention. Integrated circuit or semiconductor chip or die 12 is attached with an adhesive to a substrate 14. Substrate 14 has a first surface 16 and a second surface 18. Substrate 14 may be any of a number of suitable materials. One suitable material for substrate 14 is a flexible polymer which will allow reel-to-reel processing. Substrate 14 may also be a multilayer substrate. Semiconductor chip 12 may be electrically coupled to a plurality of columns 20 in a number of ways; for example, flip chip mounting may be utilized or traces with a bond pattern may be used. In this embodiment, chip 12 has bonding wires 22 that couple chip 12 to a plurality of traces such as trace 24. Traces 24 are electrically coupled to the plurality of columns 20. Columns 20 are located at predetermined locations according to the desired position of package contacts 26 on the second side 18 of substrate 14. Package contacts 26 may be formed by an extension portion 28 of each column 20. The semiconductor chip 12 and traces 24 may be covered with a molding material or resin 30 to form a completed package. Referring to FIGURE 2, a detail of a portion of the column grid array 10 of FIGURE 1 is shown. Conductive trace 24 is shown on first side 16 of substrate 14. Column 20, which is formed of a conductive material 32 such as copper or nickel, is electrically coupled to a portion of trace 24 proximate reference numeral 34. Conductive material 32 is applied within a hole 36 formed in substrate 14. The hole 36 is one of the plurality of holes that may be formed on substrate 14 according to the number of desired package contact points 26 (FIGURE 1). Holes 36 are formed with interior walls 38 in substrate 14. The column extension portion 28 may be covered with a capping material 40 such as palladium or palladium/nickel or the like. Capping material 40 may enhance the solderability of package contact point 26. Referring to FIGURES 3-7, a method for manufacturing a column grid array is presented. Referring specifically to FIGURE 3, a substrate 114, which may be, for example, a flexible polymeric substrate of about 0.010 inches (254 µm) thickness, has a first conductive material 123 applied or coated thereon, which will eventually be used to form a trace or pad 124 (FIGURE 7). First conductive material 123 is applied to a first surface 116 of substrate 114. First conductive material 123 may be, for example, a copper layer of approximately 0.002 inches (51 µm) in thickness Referring now to FIGURE 4, a plurality of holes 136, which only half of one is shown, may be formed in substrate 114. The plurality of holes 136 may be formed by mechanical drilling, laser drilling, etching or chemical milling, or other means. With reference to FIGURE 5, a resist 146, e.g. a dry film resist, is laminated over first conductive material 123 and over the opening of hole 136 on the first surface 116 of substrate 114. Resist 146 may be exposed with a pattern to contact the backside of an integrated circuit chip for flip chip mounting or with a trace bond pattern for wire bonding. The first conductive material 123 and substrate 114 may be electroplated with a second conductive material 132 (FIGURE 6), such as copper or nickel. Referring to FIGURE 6, second conductive material 132 is applied to fill hole 136 (FIGURES 4-5) completely and to also form an extension portion 128. The resist 146 may be developed and the first conductive material layer 123 etched leaving a pattern for flip chip mounting or trace 124 for wire bonding. Trace 124 is electrically coupled to column 120. Extension portion 128 may be coated with a capping material 140, such as palladium, palladium/nickel or nickel/gold. Traces 124 may also be capped by a capping material, e.g., capping material 140. Capping material 140 provides a thin protective coat to second conductive material 132 and ensures solderability of the resultant package contact point 126. Resist 146 (Figs. 5-6) is stripped leaving a column grid array as indicated in FIGURE 7. Referring now to FIGURE 8, a column grid array semiconductor package 210 is shown for one specific package contact point 226. In this alternative embodiment, which is substantially formed with steps analogous to the steps presented in connection with FIGURES 3-7, an additional step of applying a material 260 is taken. Material 260 may be an underfill to be left in place or may be a resist to be removed after extension 228 is formed. Material 260 is applied before the column 220 is formed. Material 260 is processed to form a hole 262 adding a diameter larger than first hole 236 through substrate 214. In this manner, when second conductive material 232 is applied, the formed extension portion 228 will have a very controlled shape with all but one surface being molded by either substrate 214 or resist 260 or resist 246 or interior walls 238. As an underfill, material 260 allows the underfill to be applied during the substrate manufacturing process and allows the thickness to be readily controlled to obtain desired thermal attributes.

Claims: A method of manufacturing a column grid array semiconductor package comprising the steps of: providing a substrate material (114); coating the substrate material on a first side with a first conductive material (123); forming a plurality of holes (136) through the substrate and the first conductive material; laminating a resist (146) over the first conductive material and over the opening of the plurality of holes; exposing the resist to a desired pattern; applying a second conductive material (132) into the plurality of holes from the uncovered second side of the substrate to build columns in each hole with an extension portion (128) formed that extends beyond the second side of the substrate; developing the resist; etching the first conductive material to form the desired contact pattern; and removing the resist. The method of Claim 1 further comprising the step of: coating an exterior portion of the extension portion that extends beyond the second surface of the substrate with a capping material. The method of Claim 1 or Claim 2, wherein the step of coating the substrate material on a first surface with a first conductive material comprises the step of coating the first surface of the substrate with copper. The method of any of Claims 1 to 3, wherein the step of laminating comprises the step of laminating the first conductive material and the opening of the plurality of holes with a dry film resist. The method of any of Claims 1 to 4, wherein the step of applying a second conductive material comprises the step of applying nickel into the plurality of holes to build columns in each hole with an extension portion that extends beyond the second surface of the substrate. The method of any of Claims 1 to 5, wherein the step of applying a second conductive material comprises the step of applying a conductive material different from the first conductive material. The method of any of Claims 1 to 6, wherein the step of applying a second conductive material comprises the steps of: electroplating interior walls of each of the plurality of holes and filling the holes with nickel. The method of any of Claims 1 to 6, wherein the step of applying a second conductive material comprises the steps of: electroplating interior walls of each of the plurality of holes and filling the holes with copper. The method of any of Claims 1 to 8, further comprising the step of: coating the extension portion of each column with palladium. The method of any of Claims 1 to 9, further comprising: providing a flexible polymeric substrate.

Inventors: ABBOTT DONALD C, ABBOTT, DONALD C.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INC.
Application year: 1997
Main classification: H01L23
IPC codes: H01L23, H05K3, H01L21