LEAD ATTACH FOR CHIP ON BOARD PRINTED WIRING BOARD

Abstract: A leaded printed wiring board for a chip on board device eliminates an intermetallic abutment (19) conventionally between the lead attach finger (16) and conductive traces on the outer layers of the printed wiring board (1). All of the lead attach fingers (16) are electrically connected to conductive traces (2) through vias (21, 22). The vias (21, 22) have an interconnecting trace (23) on an intermediate layer of the printed wiring board (1).

Description: LEAD ATTACH FOR CHIP ON BOARD PRINTED WIRING BOARD The present invention relates to chip on board devices and more particularly to a printed wiring board substrate having an improved lead attach area. The interest of miniaturization of electronic instrumentation has led to the desirability of mounting integrated circuit die directly onto a printed wiring board substrate. Integrated circuit die contacts are wire bonded to conductive traces on the printed wiring board to create a circuit. The die and wire bonds are covered by an encapsulent, colloquially referred to as "glob top". The populated printed wiring board assembly is referred to as a "chip on board" device. in practical use, the chip on board device substrate has a lead attach area comprising a plurality of electrically conductive lead attach fingers around a perimeter of the printed wiring board substrate. Leads of a lead frame are attached to respective lead attach fingers. Attachment of the lead frame to the chip on board device is typically done by means of soldering. Trimming of the lead frame that is attached to the chip on board substrate results in a leaded chip on board device. The leads are then formed according to conventional practice. The leaded device is attached to a larger printed wiring board to create an assembly. It is desirable for the lead attach fingers to be plated with tin-lead. The tin-lead plating provides for a high quality solder joint between the lead frame and the lead attach area and environmentally protects the underlying copper. It is desirable for the conductive traces providing for interconnection between devices and components on the chip on board substrate to be plated with gold. It is also desirable to use gold wire bonding for interconnection between the conductive traces on the chip on board device and the die. A gold wire bond requires soft, high purity gold plating on the conductive traces of the printed wiring board substrate for an optimum interconnect between the trace and the wire bond. The presence of tin-lead plating on the lead attach finger and nickel-gold plating on the conductive traces of the printed wiring board therefore results in an intermetallic abutment at the interface between the two plating materials. With specific reference to Figures 2 and 3 of the drawings, which show outer conductive layers in a printed wiring board of the prior art, the lead attach fingers (16) electrically connect to the outer conductive layers of the printed wiring board and are contiguous with the conductive traces (2) . If the gold were to be plated into the tin-lead lead attach fingers (16) , the gold will alloy with the tin- lead resulting in an embrittled solder joint. It is, therefore, conventional practice to selectively mask the tin-lead areas of the printed wiring board with photoresist material prior to plating the nickel-gold areas. The photoresist material, ideally prevents intermingling of the two metals. The tin-lead plating and the nickel-gold plating provide corrosion protection for the copper circuitry of the printed wiring board substrate. The selective masking of the tin-lead areas while plating the nickel gold areas, presents two major concerns. In the zone of the intermetallic abutment, acid in the gold plating bath degrades the tin-lead plating where the tin-lead is exposed at the edge of the photoresist (18) . See Figure 1 of the drawings. Degradation of the tin-lead plating creates an area of unprotected copper where the tin-lead has been etched away by the acid in the gold bath. The area of unprotected copper presents a potential corrosion point for the chip on board device, thereby affecting reliability. One solution to the degradation of the plating at the intermetallic abutment has been to mask the intermetallic abutment to protect the area from corrosion. With specific reference to Figure 4 of the drawings, a prior solution comprises a thin abutment line of photoimageable soldermask at a distance distal from the perimeter of the printed wiring substrate. The abutment line is applied to cover the intermetallic abutment. The abutment line of soldermask serves to environmentally protect the intermetallic abutment and to prevent solder from flowing into the nickel-gold plating. The chip on board device includes a lid that covers the top of the device. The lid is attached with epoxy to the chip on board device just inside the perimeter of the chip on board device substrate. The abutment line is therefore, just inside and concentric with the area of lid attachment. It is important that the area of lid attach be clear of the abutment line because stresses placed on the lid could exceed the strength of the adhesion of the abutment line to the substrate. If the lid attach overlapped the abutment line, the abutment line could be pulled off the substrate resulting in a defective part. The abutment line is optimally, therefore, only as thick as is required to cover the intermetallic abutment. Challenges associated with the abutment line of soldermask to environmentally protect the intermetallic abutment include proper registration of the abutment line. If proper registration is not achieved and the abutment line is improperly disposed on the lead attach finger side of the intermetallic abutment, other copper remains exposed and the amount of solder volume available for lead attach is reduced. If the abutment line is improperly disposed on the die side of the intermetallic abutment, the copper remains exposed and the tin-lead or solder can alloy with the gold plating and embrittle the solder joints. Another problem with the conventional practice to create the intermetallic abutment is contamination of the gold plating bath with tin-lead as the acid in the gold bath etches away at the tin-lead at the edge of the photoresist. See Figure 1. If the acid in the gold bath completely etches away the tin-lead, it is also possible that the acid will begin to etch the copper trace and reduce the conductive area after the tin-lead has exposed it. There is a need therefore to overcome the disadvantages of the intermetallic abutment and to improve the reliability and manufacturability of a chip on board device having a lead attach area. The aforementioned problems are solved by a chip on board device according to the teachings of the present invention in which a printed wiring board substrate has lead attach fingers wherein all of the lead attaches are electrically connected to conductive traces on the printed wiring board substrate through a via. Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which, Figure 1 is a cross section of an intermetallic abutment and photoresist covered lead finger according to conventional practice showing the attendant degradation after gold plating. Figures 2 and 3 illustrate conductive layers of copper for a top side and a bottom side of a multilayer chip on board device having an intermetallic abutment between lead attach fingers and conductive traces. Figure 4 illustrates the solder mask layers for the top side of the chip on board device of Figures 2 and 3 showing an abutment line. Figure 5 illustrates a cross section of a lead attach finger according to the teachings of the present invention. Showing full coverage of the lead attach finger by photoresist. Figure 6 and 7 illustrate conductive layers of copper for a top side and a bottom side of a multilayer chip on board printed wiring board having lead attach fingers according to the teachings of the present invention. Figure 8 illustrates a solder mask layers for the top side of the chip on board device of Figures 6 and 7. Figure 9 and 10 illustrate cross sections of a leaded chip on board according to the teachings of the present invention cut along lines 9-9 and 10-10 respectively in Figure 6. Figures 11 and 12 illustrate cross sections of a base grid array chip on board device according to the teachings of the present invention. A chip on board device comprises printed wiring board substrate (1) having multiple layers of a polyimide electrically insulating material. The printed wiring board is similar to that disclosed in U.S. patent applications serial no. 08/621,304 and application serial no. 08/620,765, the teachings of which are specifically incorporated by reference herein. Each layer of polyimide has conductive areas or traces (2) thereon. A preferred printed wiring board polyimide and prepreg is the N 7000-1 series manufactured by New England Laminates Company, Inc., a subsidiary of Park Electro Chemical Corporation. The N 7205-1 laminate and N 7305-1 prepreg is preferred. With reference to Figures 6-8 vias (3) on and through the substrate (l) provide electrical conductivity from a top side (4) of the printed wiring board substrate (1) to intermediate layers and/or to a bottom side (5) of the printed wiring board substrate (1) . In operation, a via (3) carries either ground potential, direct current, radio frequency or microwave signal to effect a desired circuit. The via (3) as is conventionally known comprises an annular rim (6) of substrate (1) having an inner cylindrical surface (7) . The inner cylindrical surface (7) is plated with a layer of a conductive material, typically metal and preferably copper. Electrical connection is made to one or more layers of the printed wiring board substrate (1) including, for example ground plane (8) , by contacting a conductive trace (2) to the plated inner cylindrical surface (7) . DC, RF, and microwave signal vias (3) are not electrically connected to a ground plane. The ground plane layers (8) , have an insulating ring surrounding all signal and RF vias (3) . Due to conventional methods for creating a via (3) , the via (3) necessarily creates an evacuated area or plated through hole in the printed wiring board substrate (1) . Due to the aforementioned reliability and manufacturability problems associated with the intermetallic abutment (19) between the lead attach finger (16) and the conductive trace (2) , it is suggested herein to eliminate the intermetallic abutment for all lead attach fingers (16) . In a printed wiring board according to the teachings of the present invention, elimination of the intermetallic abutment is achieved by using first and second lead attach vias (21,22) to interconnect all lead attach fingers (16) to the appropriate conductive trace (2) and/or ground plane (8) . With specific reference to Figures 9 and 10, the first lead attach via (21) electrically communicates with an interconnecting trace (23) on one of the intermediate layers of the printed wiring board (1) . The interconnecting trace (23) connects to the first lead attach via (21) and extends for a distance to electrically connect to the second lead attach via (22) . The second lead attach via (22) interconnects the interconnecting trace (23) to the top side conductive layer. The interconnecting trace (23) , therefore, creates a physical separation between an end of the tin- lead plated lead attach finger (16) distal from a perimeter of the printed wiring board and an end of the nickel-gold plated conductive trace (2) and/or ground the plane (8) proximal to the perimeter of the printed wiring board. The physical separation advantageously obviates the need for an intermetallic abutment, and hence an abutment line and permits complete masking of the tin-lead plated lead attach fingers (16) prior to the gold plating bath. See Figure 5 of the drawings for example. The physical separation further advantageously provides an area within which normal manufacturing tolerances of the mask alignment do not adversely affect or compromise the intended function of the photoresist mask in the lead attach area. The intermediate ground plane layers carry the same electrical potential as outer conductive layers which also have a ground plane thereon. In a printed circuit of a chip on board device according to the teachings of the present invention, the intermediate layers of the printed wiring board substrate are ground planes (8) . Therefore, interconnection of all ground planes (8) in the multilayer printed wiring board as well as all lead attach fingers (16) carrying ground potential is appropriately achieved through the lead attach vias (21,22) without any degradation in high frequency performance. With specific reference to Figures 7, 9 and 10 of the drawings, each lead attach finger (16) has a first width and is electrically connected to a secondary conductive trace (20) . The first width of the lead attach finger (16) is appropriately sized to register with a width of the leads (24) on the lead frame according to conventional practice. The secondary conductive trace (20) has a second width and is electrically connected to a first lead attach via (21) . The second width of the secondary conductive trace (20) is less than the first width of the lead attach (16) . The second width of the secondary conductive trace (20) provides an advantage during the process step of attaching the lead frame to the printed wiring board substrate (1) . In a microwave chip on board device, it is electrically desirable to have a large number of high quality connections to the ground planes (8) . The high quality electrical connection, by its very nature, also conducts heat during the solder process. The smaller width of the secondary conductive trace (20) limits the transfer of heat to the ground plane (8) . Advantageously, the lead attach finger (16) , therefore, gets hotter, faster and minimizes the chip on board device's exposure to temperature extremes. The smaller width of the secondary conductive trace (20) also minimizes the volume of solder wicked toward the first lead attach via (21) which concentrates the solder at the end of the lead attach finger (16) . With specific reference to Figures 11 and 12 of the drawings, an alternate embodiment according to the teachings of the present invention comprises a ball grid array (BGA) attachment method. Rather than leads of a lead frame attaching to lead fingers, a conductive mass or ball (25) is disposed on a bottom side or attachment side of the printed wiring board substrate. Attachment of the chip on board to the larger printed wiring board could be by means of solder reflow. All connections to the chip on board circuit would be made by way of a via (21) and an interconnecting trace (23) . Other advantages of the invention are apparent from the detailed description by way of example, and from accompanying drawings, and from the spirit and scope of the appended claims.

Claims: WE CLAIMt 1. A leaded multilayer printed wiring board substrate comprising a top side and a bottom side having conductive traces and a plurality of lead attach fingers on the top side wherein the improvement comprises: all of the lead attach fingers are electrically connected to the conductive traces through vias, said vias having an interconnecting trace on an intermediate layer of the printed wiring board creating a insulating separation between the vias that connect to the lead attach fingers and the conductive traces in the top side of the printed wiring board substrate. 2. A leaded multilayer printed wiring board as recited in claim 1 wherein a plurality of said lead attach fingers are connected to a single via. 3. A leaded multilayer printed wiring board as recited in claim 1 wherein said lead attach finger having a first width is electrically connected to said via by a secondary conductive trace, said secondary conductive trace having a second width which is smaller than said first width. 4. A leaded multilayer printed circuit board as recited in claim 1 wherein said lead finger is on an attachment side of the printed wiring board and has a conductive mass thereon. 5. A leaded multilayer printed circuit board substrate having a plurality of lead attach fingers wherein the improvement comprises: all lead attach fingers are electrically connected to conductive traces through vias, said vias having an interconnecting trace on an intermediate layer of the printed wiring board, wherein the printed circuit board receives a plurality of signals in different frequency band and each signal is carried on a different one of said intermediate layers.

Inventors: CARON CHRISTOPHER L, SCHWAB PAUL J, WELLS GRAHAM J H, CARON, CHRISTOPHER, L., SCHWAB, PAUL, J., WELLS, GRAHAM, J., H.
Applicants: WHITAKER CORP, THE WHITAKER CORPORATION
Application year: 1997
Main classification: H05K3
IPC codes: H05K1, H05K3