FREQUENCY DIVIDING CIRCUIT

Abstract: A frequency-dividing circuit comprises a digital accumulator capable of performing signed arithmetic and means for adding of a predetermined numerator to the content of the accumulator. Means are provided for subtracting a predetermined denominator from the content of the accumulator and further means detect if the value held in the accumulator has become zero or negative and establishing a delay setting value dependent upon the held value. Further means convert the delay setting value into a time delay inversely proportional to the magnitude of the delay setting value and the yet further means change the state of a digital output signal on expiry of the said time delay. A corresponding method is also disclosed.

Description: FREQUENCY DIVIDING CIRCUIT This invention relates to frequency dividing circuits of the type which provide an output signal representing the division of the frequency of an input signal by a divisor. Many electronic systems require the generation of signals whose frequencies are in some fixed relationship with a master frequency. Where the required relationship between such frequencies takes the form of division by a rational number (that is, a number expressible as a ratio of two integers) , the conventional method of performing the division, when good spectral purity is required in the output signal, makes use of a phase-locked-loop circuit employing a voltage-controlled oscillator to produce the final output frequency. Standard direct division techniques have poor spectral purity because of period jitter in the output signal. In many applications, including, but not restricted to, mobile radio communications, the additional cost and power consumption of an additional voltage-controlled oscillator impose significant design penalties, but good spectral purity is essential. It is an object of the present invention to provide a method and circuit which can divide the frequency of an input signal by a rational factor without the need for the voltage-controlled oscillator associated with known frequency division techniques, yet which still provides good spectral purity. According to the present invention there is provided a frequency-dividing circuit comprising: a digital accumulator capable of performing signed arithmetic; means for adding of a predetermined numerator to the content of the accumulator; means for subtracting a predetermined denominator from the content of the accumulator; means for detecting if the value held in the accumulator has become zero or negative and establishing a delay setting value dependent upon the held value; means for converting the delay setting value into a time delay inversely proportional to the magnitude of the delay setting value; means for changing the state of a digital output signal on expiry of the said time delay. The circuit may further comprise means for setting the components of the circuit to a defined starting condition. The numerator and denominator values may be provided by hard wiring, from separate registers and/or from a microprocessor, for example. The circuit may be arranged so that the subtraction of the divisor denominator from the accumulator is caused by each consecutive active transition of the input signal, and so that detection of a zero or negative value in the accumulator occurs immediately upon its establishment. The circuit may also be arranged so that registration of the delay setting value, together with addition of the divisor numerator to the accumulator and triggering of the delay setting value-to-delay conversion means, occur immediately upon zero or negative value detection, and so that, upon expiry of the said time delay period, the state of the output signal is complemented. The circuit may also be arranged so that the inverse relationship of the time delay period to the delay setting value is constructed to be such that the time delay interpolates the required timing of the output transition appropriately between active transitions of the input signal so as to yield output transitions representing exactly the required frequency division from the input signal at a 50:50 mark: space ratio. The circuit may be realised in hardware, software on a processor, or a combination thereof. A corresponding method is also provided. An example of the present invention will now be described with reference to the accompanying drawing in which: - Figure 1 is a circuit diagram depicting the main circuit elements of an example of the invention and their primary interconnections ; and Figure 2 illustrates a particular embodiment of a time-delay means employed in the example of figure 1. Referring to Figure 1, a binary digital accumulator 1 is arranged to hold at any time the numerical total resulting from the summation of previous denominator subtractions or numerator additions. A denominator register 2 holds the binary representation of the divisor denominator and, in a typical implementation, allows the denominator value to be loaded from a host microprocessor (not shown) . A numerator register 3 holds the binary representation of the divisor numerator and in a typical implementation would allow the numerator value to be loaded from the host microprocessor. On each active transition of an input signal (which may be the rising edge or the falling edge) the divisor denominator value is subtracted from the previous content of the accumulator 1. If the content of the accumulator 1 remains positive, no further action takes place until the next input signal active transition. If the subtraction causes the content of the accumulator to become zero or negative, this underflow is sensed and the value copied immediately to an underflow register 4 which holds the underflow as a delay setting value. Immediately following this action, the underflow to time delay conversion means 5 is triggered, and the numerator value is added to the accumulator 1, so that the accumulator 1 now contains the sum of the previous underflow and the divisor numerator. On expiry of the said time delay, the output of the conversion means 5 triggers the output flipflop 6 to complement the state of the output signal. The time delay is scaled so that an underflow value of zero produces a delay of exactly one period of the input signal; larger underflow values yield smaller delays in inverse proportion to the magnitude of the underflow, such that an underflow of magnitude one greater than the maximum possible denominator value in any particular implementation of the circuit would yield zero time delay. The achievable delay is quantised by the number of bits in the denominator register 2, and during operation of the circuit takes values from that quantised range according to the prevailing denominator and numerator values. This generates the output transition times necessary to carry out the desired rational division of the input frequency with theoretically exact placement of the output transitions. In any particular implementation of this circuit the achievable division ratios are governed by the numbers of binary bits in the numerator and denominator registers 3 and 2. The accumulator 1 must be able to accommodate at least the numerator value as a positive number and the denominator value as a negative number without loss of data. In the embodiment shown the denominator register 2 is offset from the accumulator 1 by one bit (the least significant bit of the denominator register 2 is aligned to the next-to-least significant bit of the accumulator 1) in order to correct for the implicit factor of two in the overall division caused by complementing the state of the output signal on each underflow rather than generating a short pulse. Referring to Figure 2 , an embodiment of the time-delay means 5 employs a digital-to-analog converter (DAC) 7, a ramp generator 8 and a level comparator 9. The underflow value from the underflow register 4 taken as an unsigned number is converted by the DAC 7 to a reference level on the positive input of the comparator 9. The reference level accordingly depends on the magnitude of the underflow, such that a large underflow value causes a high reference level and a small underflow causes a low reference level. The ramp generator 8 produces a linear descending ramp starting at a voltage level corresponding to the level the DAC 7 would produce if it were capable of accepting one digital count above its actual full scale output and ending at the nominal zero-scale output of the DAC 7 exactly one period of the input clock signal later. This ramp begins as the underflow value has appeared on the output of the DAC 7 and forms the second (negative) input to the comparator 9. At the start of the ramp the output of comparator 9 is therefore low. When the descending ramp passes through the reference level from the DAC 7, the comparator output goes high and clocks the flipflop 6. Following the detection of the output transition point the ramp generator 8 is reset for in preparation for the next cycle. An optional refinement of the ramp generator 8 has a further ramp correction element 10 to sample the zero error of the descending ramp and adjust the ramp generator circuit 8 and/or the DAC 7 to produce a more accurate result on the next cycle of operation. In embodiments of this invention using small numbers of binary bits in the registers and accumulator it is possible to fabricate the entire circuit in a manner suitable for operation at very high input frequencies, for instance as an integrated circuit (not shown) . In other embodiments of this invention, equivalent operation may be achieved by reversing the sense of arithmetic operation of the accumulator 1 and using the overflow as a delay setting value, and/or by reversing the sense of operation of the ramp generator 8 and DAC 7.

Claims: CLAIMS 1. A frequency-dividing circuit comprising: a digital accumulator capable of performing signed arithmetic; means for adding of a predetermined numerator to the content of the accumulator; means for subtracting a predetermined denominator from the content of the accumulator; means for detecting if the value held in the accumulator has become zero or negative and establishing a delay setting value dependent upon the held value; means for converting the delay setting value into a time delay inversely proportional to the magnitude of the delay setting value; and means for changing the state of a digital output signal on expiry of the said time delay. 2. A circuit according to claim 1, wherein the circuit comprises means for setting the components of the circuit to a defined starting condition. 3. A circuit according to claim 1 or claim 2, wherein the numerator and denominator values are provided from separate registers. 4. A circuit according to claim 1 or claim 2 , wherein the numerator and denominator values are provided from a microprocessor. 5. A circuit according to any of the preceding claims, wherein the circuit is arranged so that the subtraction of the divisor denominator from the accumulator is caused by each consecutive active transition of an input signal, wherein detection of a zero or negative value in the accumulator occurs immediately upon its establishment. 6. A circuit according to any of the preceding claims, wherein the circuit is arranged so that registration of the delay setting value, together with addition of the divisor numerator to the accumulator and triggering of the delay setting value-to-delay conversion means, occur immediately upon zero or negative value detection, wherein, upon expiry of the said time delay period, the state of the output signal is complemented. 7. A circuit according to any of the preceding claims, wherein the circuit is arranged so that the inverse relationship of the time delay period to the delay setting value is constructed to be such that the time delay interpolates the required timing of the output transition appropriately between active transitions of the input signal so as to yield output transitions representing exactly the required frequency division from the input signal at a 50:50 mark: space ratio. 8. A circuit according to any of the preceding claims, wherein the circuit is arranged as an integrated circuit. 9. A frequency-dividing method comprising the steps of: providing a digital accumulator capable of performing signed arithmetic and holding' a value; adding a predetermined numerator to the content of the accumulator; subtracting a predetermined denominator from the content of the accumulator; detecting if the value held in the accumulator has become zero or negative and establishing a delay setting value dependent upon the held value; converting the delay setting value into a time delay inversely proportional to the magnitude of the delay setting value; and changing the state of a digital output signal on expiry of the said time delay. 10. A method according to claim 9, further comprising the initial step of setting a defined starting condition. 11. A method according to claims 9 or 10, wherein subtraction of the divisor denominator from the accumulator is caused by each consecutive active transition of an input signal, wherein detection of a zero or negative value in the accumulator occurs immediately upon its establishment. 12. A method according to any of claims 9 to 11, wherein registration of the delay setting value, together with addition of the divisor numerator to the accumulator and triggering of the delay setting value-to-delay conversion means, occur immediately upon zero or negative value detection, wherein, upon expiry of the said time delay period, the state of the output signal is complemented. 13. A method according to claims 9 to 12 , wherein the inverse relationship of the time delay period to the delay setting value is constructed to be such that the time delay interpolates the required timing of the output transition appropriately between active transitions of the input signal so as to yield output transitions representing exactly the required frequency division from the input signal at a 50:50 mark: space ratio.

Inventors: FOGG ANDREW, FOGG, ANDREW
Applicants: FOGG ANDREW, TECHNOLOGY PARTNERSHIP, FOGG, ANDREW, THE TECHNOLOGY PARTNERSHIP PLC
Application year: 1997
Main classification: H03K23
IPC codes: G06F7, H03K23