Semiconductor memory device having address transition detection circuit for controlling sense and latch operations

Abstract: In a semiconductor memory device including: an address buffer (2) for generating an address signal (IADD) , a memory cell array (1) for generating a first data signal (D1) in response to the address signal, a sense amplifier circuit (6) for sensing the first data signal to generate a second data signal (D2) in response to a sense activation signal (  S ), a data latch circuit (7) for latching the second data signal to generate a third data signal in response to a latch activation signal (  L ), an address transition detection circuit (8) for detecting a transition of the address signal to generate an address transition detection signal (  ATD ), and a timing generating unit (10', 10'') for generating the sense activation signal and the latch activation signal, the timing generating unit is formed by a plurality of timing generating circuits (10-1, 10-1', 10-2, 10-3, 10-3') for prolonging the address transition detection signal by different delay times ( τ 1 , τ 2 , τ 3 ) to generate pulse width signals (  1 ,  2 ,  3 ). The delay times have different characteristics depending upon a power supply voltage (V CC ). Also, a logic circuit (11) logically adds the pulse width signals to each other to generate a logic signal (  S '). A pulse prolonging circuit (12, 13) prolongs the logic signal by a definite time to generate the sense activation signal, and a pulse generating circuit (14) generates the logic signal in response to a termination of the logic signal.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device such as a dynamic random access memory (DRAM) device having an address transition detection circuit for generating an address transition detection signal to control a sense amplifier circuit and a data latch circuit. Description of the Related Art Generally, in a prior art semiconductor memory device, an address transition detection circuit for detecting a transition of at least one bit of an address signal is incorporated thereinto, and a sense amplifier circuit and a data latch circuit are controlled by a sense activation signal and a latch activation signal, respectively, which are generated in accordance with an address transition detection signal of the address transition detection circuit. A timing generating circuit for generating the sense activation signal and the latch activation signal includes a delay circuit formed by a series of delay elements and an AND circuit connected to the output of the address transition detection circuit and the outputs of the delay elements. In this case, the AND circuit generates the sense activation signal, and one of the delay elements generates the latch activation signal. This will be explained later in detail. Generally, in order to enhance access speed, the memory cell array is divided into a plurality of blocks. However, as the number of blocks of a memory cell array is increased, peripheral circuits such as decoders are increased in size which increases the chip area and reduces the manufacturing yield. Therefore, recently, even when the capacity of devices has been remarkably increased, the increase of the number of blocks in memory cell arrays is suppressed. As a result, the access time is dependent upon a power supply voltage. For example, when the power supply voltage is high, the delay time of the memory cell array is determined by a delay time dependent upon word lines, and when the power supply voltage is low, the delay time of the memory cell array is determined by a delay time dependent upon bit lines. Thus, only when the power supply voltage is within a certain range, is a stable access operation guaranteed. Otherwise, a stable access operation cannot be expected. Further, in order to normally operate the device under a wide range of power supply voltage, the operating speed of the device has to be reduced. In addition, it is difficult to guarantee an operational margin for the power supply voltage. US-A-5 438 550 discloses an address transition detection circuit comprising a variable delay line. A power supply voltage detector adjusts the length of the variable delay according to the detected voltage. SUMMARY OF THE INVENTION It is an object of the present invention to guarantee an access operation of a semiconductor memory device incorporating an address transition detection circuit. Another object is to guarantee a wide range operational margin of the semiconductor memory device for a particular power supply voltage. According to the present invention, in a semiconductor memory device including an address buffer for generating an address signal, a memory cell array for generating a first data signal in response to the address signal, a sense amplifier circuit for sensing the first data signal to generate a second data signal in response to a sense activation signal, a data latch circuit for latching the second data signal to generate a third data signal in response to a latch activation signal, an address transition detection circuit for detecting a transition of the address signal to generate an address transition detection signal and a timing generating unit generating the sense activation signal and the latch activation signal, the timing generating unit is formed by a plurality of timing generating circuits for prolonging the address transition detection signal by different delay times to generate cirtain pulse width signals. The delay times have different characteristics depending upon a power supply voltage. Also, a logic circuit logically adds the pulse width signals to each other to generate a logic signal. A pulse prolonging circuit prolongs the logic signal by a definite time to generate the sense activation signal, and a pulse generating circuit generates the logic signal in response to a termination of the logic signal. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more clearly understood form the description as set forth below, with reference to the accompanying drawings, wherein: Fig. 1 is a block circuit diagram illustrating a prior art semiconductor memory device; Fig. 2 is a detailed circuit diagram of the address transition detection circuit and the timing generating circuit of Fig. 1; Figs. 3A through 3H are timing diagrams showing the operation of the timing generating circuit of Fig 2; Fig. 4 is a graph showing power supply voltage to delay time characteristics of the device of Fig. 1; Figs. 5A through 5H, Figs. 6A through 6H, and Figs. 7A through 7H are timing diagrams showing the operation of the device of Fig. 1; Fig. 8 is a circuit diagram illustrating a modification of the timing generating circuit of Fig. 2; Fig. 9 a block circuit diagram illustrating a first embodiment of the semiconductor memory device; Fig. 10 is a detailed circuit diagram of the timing generating circuit of Fig. 9; Figs. 11A, 11B and 11C are detailed circuit diagrams of the timing generating circuits of Fig. 10; Fig. 12 is a graph showing power supply voltage to delay time characteristics of the device of Fig. 9; Figs. 13A through 13L, Figs. 14A through 14L, and Figs. 15A through 15L are timing diagrams showing the operation of the device of Fig. 9; Fig. 16 a block circuit diagram illustrating a second embodiment of the semiconductor memory device; Fig. 17 is a detailed circuit diagram of the timing generating circuit of Fig. 16; and Figs. 18A and 18B are detailed circuit diagrams of the timing generating circuits of Fig. 17. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before the description of the preferred embodiments, a prior art DRAM device will be explained with reference to Figs. 1, 2, 3A through 3H, 4, 5A through 5H, 6A through 6H, 7A through 7H and 8. In Fig. 1, reference numeral 1 designates a memory cell array including memory cells at intersetions of word lines and bit lines (not shown). Also, an address buffer 2 receives an external address signal ADD to generate an internal address signal IADD. An X address component of the internal address signal IADD is supplied to an X decoder 3 for selecting one of the word lines, and a Y address component of the internal address signal IADD is supplied to a Y decoder 4 so that a Y selector 5 selects one (or a pair) or a predetermined number of the bit lines. Thus, one or a predetermined number of the memory cells are selected. After the bit lines are precharged, data D2 stored in the selected memory cells are sensed by a sense amplifier cirucit 6, so that the sense amplifier circuit 6 generates data D2. The data D2 are latched in a data latch circuit 7, so that the data latch circuit 7 generates an output signal OUT. The sense amplifier circuit 6 is enabled by a sense activation signal  S , and the data latch circuit 7 is enabled by a latch activation signal  L . The sense activation signal  S and the latch activation signal  L are generated by an address transition detection circuit 9 and a timing generating circuit 10. In Fig. 2, which is a detailed circuit diagram of the address transition detection circuit 9 and the timing generating circuit 10 of Fig. 1, the address transition detection circuit 9 includes a plurality of delay circuits 901-1, 901-2, ··· each corresponding to one bit of the internal address signal IADD, a plurality of exclusive OR circuits 902-1, 902-2, ··· each corresponding to one bit of the internal address signal IADD, and a NOR circuit 903. As a result, if at least one bit of the internal address singal IADD is changed, one of the exclusive OR circuits 902-1, 902-2, ··· generates a pulse signal having a pulse width τ determined by the delay circuits 901-1, 901-2, ···, so that the NOR circuit 903 generates an address transition detection signal  ATD having the time period τ. Also, the timing generating circuit 10 includes a delay circuit 101 formed by a series of delay elements 101-1, 101-2, ···, 101-n, and an AND circuit 102 connected to the output of the address transition detection circuit 9 and the outputs of the delay elements 101-1, 101-2,···, 101-n. In this case, the AND circuit 102 generates the sense activation signal  S , and the delay element 101-(n-1) generates the latch activation signal  L . Note that each of the delay elements 101-1, 101-2, ···, 101-n is comprised of two inverters connected in series, and a delay time τ' of each of the delay elements 101-1, 101-2, ···, 101-n is shorter than τ. Thus, if the address transition detection signal  ATD is changed as shown in Fig. 3A, the outputs of the delay elements 101-1, 101-2, 101-3,···, 101-(n-1), 101-n are changed as shown in Figs. 3B, 3C, 3D, 3E and 3F. As a result, the sense activation signal  S generated from the AND circuit 102 is changed as shown in Fig. 3G. Also, the latch activation signal  L is the same as the output of the delay element 101-(n-1) as shown in Figs. 3E and 3H. Generally, in order to enhance the access speed, the memory cell array 1 is divided into a plurality of blocks. However, as the number of blocks of the memory cell array 1 is increased, peripheral circuits such as decoders are increased in size which increases the chip area and reduces the manufacturing yield. Therefore, recently, even when the capacity of devices has been remarkably increased, the increase in the number of blocks in memory cell arrays is suppressed. As a result, the access time is dependent upon a power supply voltage V CC . For example, a delay time τ W depending on the word lines is determined by a time constant CR where C and R are a capacitance and a resistance of one of the word lines, and therefore, is less dependent upon the power supply voltage V CC , as shown in Fig. 4. On the other hand, a delay time τ B depending on the bit lines is affected by the ability to precharge transistors, and therefore, is more dependent upon the power supply voltage V CC , as shown in Fig. 4. Thus, as shown by a shaded discontinuous line in Fig. 4, when the power upply voltage V CC is high, the delay time of the data D2 is determined by the delay time τ W , and when the power supply voltage V CC is low, the delay time of the data D2 is determined by the delay time τ B . Returning to the timing generating circuit 10 of Fig. 2, since the latch activation signal  L is generated through the delay elements 101-1, 101-2,···, 101-(n-1), the delay time τ  L of the latch activation signal  L is determined by capacitances of the gate capacity and impurity diffusion regions of MOS transistors forming the inverters of the delay elements 101-1, 101-2, ···, 101-(n-1). Therefore, as shown in Fig. 4, the delay time τ  L shows a continuous curve with respect to the power supply voltage V CC . Since the delay time τ(D2) of the data D2, i.e., the output of the sense amplifier circuit 6 shows a continuous curve with respect to the power supply voltage V CC , the two curves always cross at points A and B as shown in Fig. 4. Thus, as shown in Figs. 5A through 5H, only when V CCA < V CC < V CCB , is the delay time τ  L larger than the delay time τ (D2) of the data D2, which guarantees a stable access operation. In Fig. 4, note that t ACC shows an access time. Otherwise, a stable access operation cannot be expected. That is, as shown Figs. 6A through 6H, when V CC ≦ V CCA , the delay time τ  L is smaller than the delay time τ (D2) of the data D2, so that the data latch circuit 7 is operated before the determination of the data D2. Therefore, data latched in the data latch circuit 7 may be incorrect. Similarly, as shown Figs. 7A through 7H, when V CC ≧ V CCB , the delay time τ  L is also smaller than the delay time τ(D2) of the data D2, so that the data latch circuit 7 is operated before the determination of the data D2. Therefore, data latched in the data latch circuit 7 may be incorrect. Further, in order to normally operate the device under a wide range of the power supply voltage V CC , the operating speed of the device has to be reduced. In addition, the cross-points A and B fluctuate due to the manufacturing process, so that it is difficult to guarantee an operational margin for the power supply voltage V CC . In Fig. 8, which illustrates a modification of the timing generating circuit 10 of Fig. 2, an RS flip-flop 103 is provided instead of the AND circuit 102, and a one-shot circuit 104 is added to the elements of Fig. 2. The RS flip-flop 103 is reset by a rising or falling edge of the address transition detection signal  ATD and is set by a rising or falling edge of the output of the delay circuit 101-n, thus generating the sense activation signal  S . Also, the one-shot circuit 104 generates the latch activation signal  L . In Fig. 9, which illustrates a first embodiment of the present invention, a timing generating circuit 10' is provided instead of the timing generating circuit 10 of Fig. 1. The timing generating circuit 10' is illustrated in detail in Fig. 10. In Fig. 10, timing generating circuits 10-1, 10-2 and 10-3 are provided and are connected to an AND circuit 11. The output signal  S ' of the AND circuit 11 is supplied to a delay circuit 12 and an AND circuit 13, thus generating the sense activation signal  S . Also, the output signal  S ' of the AND circuit 11 is supplied to a one-shot circuit 14, thus generating the latch activation signal  L . As illustrated in Fig. 11A, the timing generating circuit 10-1 is formed by a delay circuit 10-1A and an AND circuit 10-1B. The delay circuit 10-1A includes a plurality of inverters 1101, a plurality of resistors 1102 and a plurality of capacitors 1103. In this case, the resistance values of the resistors 1102 and the capacitance values of the capacitors 1103 are adjusted so that the delay time τ 1 of the delay circuit 10-1A has greatly sloped characteristics with respect to the power supply voltage V CC . That is, as shown in Fig. 12, the delay time τ 1 + τ' is rapidly changed with respect to the power supply voltage V CC , to correspond to the delay time τ B depending on the bit lines when the power supply voltage V CC is relatively low (V CC ≦ V CCA ). Also, as illustrated in Fig. 11B, the timing generating circuit 10-2 is formed by a delay circuit 10-2A and an AND circuit 10-2B. The delay circuit 10-2A includes a plurality of inverters 1104 connected in series in the same way as in the delay circuit 101 of Fig. 2. In this case, the delay time τ 2 of the delay circuit 10-2A has small sloped characteristics with respect to the power supply voltage V CC . That is, as shown in Fig. 12, the delay time τ 2 + τ' is gradually changed with respect to the power supply voltage V CC . Further, as illustrated in Fig. 11C, the timing generating circuit 10-3 is formed by a delay circuit 10-3A and an AND circuit 10-3B. The delay circuit 10-3A includes a plurality of inverters 1105 serving as wave-shaping means, and a resistor 1106 and a capacitor 1107 therebetween. In this case, the resistance value of the resistor 1106 and the capacitance value of the capacitor 1107 are adjusted so that the delay time τ 3 of the delay circuit 10-3A has almost flat characteristics with respect to the power supply voltage V CC . That is, as shown in Fig. 12, the delay time τ 3 + τ' is almost constant with respect to the power supply voltage V CC , to correspond to the delay time τ W depending on the word lines when the power supply voltage V CC is relatively high (V CC ≧ V CCB ). Thus, as shown in Figs. 13A through 13L, when V CCA < V CC < V CCB , the delay time τ  L is determined by the delay circuit 10-2A of the timing generating circuit 10-2, and is larger than the delay time τ (D2) of the data D2, which guarantees a stable access operation. Also, as shown in Figs. 14A through 14L, when V CC ≦ V CCA , the delay time τ  L is determined by the delay circuit 10-1A of the timing generating circuit 10-1, and is also larger than the delay time τ (D2) of the data D2, which guarantees a stable access operation. Further, as shown in Figs. 15A through 15L, when V CC ≧ V CCB , the delay time τ  L is determined by the delay circuit 10-3A of the timing generating circuit 10-3, and is also larger than the delay time τ (D2) of the data D2, which guarantees a stable access operation. In Fig. 16, which illustrates a second embodiment of the present invention, a pseudo word line WL and a pseudo bit line BL, which are similar to the word lines and the bit lines, respectively, of the memory cell array 1, are added to the elements of Fig. 9, and the timing generating circuit 10' of Fig. 9 is modified into a timing generating circuit 10". That is, the address transition detection signal  ATD is delayed by the pseudo bit line BL, and then is supplied to the timing generating circuit 10". In this case, the delay time τ 1 ' of detection signal  ATD corresponds to the delay time τ B depending on the bit lines. Also, the address transition detection signal  ATD is delayed by the pseudo word line WL, and then is supplied to the timing generating circuit 10". In this case, the delay time τ 2 ' of detection signal  ATD corresponds to the delay time τ W depending on the word lines. In Fig. 17, which is a detalied circuit diagram of the timing generating circuit 10" of Fig 16, the timing generating circuits 10'-1 and 10'-3 are different from the timing generating circuits 10-1 and 10-3, respectively, of Fig. 10. That is, since the signals from the pseudo bit line BL and the pseudo word line WL are already delayed thereby, the timing generating circuits 10'-1 and 10'-3 have no delay functions, as illustrated in Figs. 18A and 18B. In Fig. 18A, an RS flip-flop 1801 is reset by a rising or falling edge of the address transition detection signal  ATD and is set by a rising or falling edge of the signal from the pseudo bit line BL, thus generating the same signal  1 as Fig. 11A. Similarly, in Fig. 18B, an RS flip-flop 1802 is reset by a rising or falling edge of the address transition detection signal  ATD and is set by a rising or falling edge of the signal from the pseudo word line WL, thus generating the same signal  2 as Fig. 11C. Thus, the device of Fig. 16 operates in the same way as the device of Fig. 9, as shown in Figs. 13A through 13L, Figs. 14A through 14L and Figs. 15A through 15L. As explained hereinabove, according to the present invention, since the latch timing of the data latch circuit can be optimized for the power supply voltage, an access operation can be normally carried out without reducing the access speed thereof. In addition, a large operational margin can be obtained over a wide range of the power supply voltage.

Claims: A semiconductor memory device comprising: an address buffer (2) for generating an address signal (IADD); a memory cell array (1), connected to said address buffer, for generating a first data signal (D1) in response to said address signal; a sense amplifier circuit (6), connected to said memory cell array, for sensing said first data signal to generate a second data signal (D2) in response to a sense activation signal ( S ); a data latch circuit (7), connected to said sense amplifier circuit, for latching said second data signal to generate a third data signal (D3) in response to a latch activation signal ( L ); an address transition detection circuit (9) , connected to said address buffer, for detecting a transition of said address signal to generate an address transition detection signal ( ATD ) ; and a timing generating means (10', 10") connected to said address transition detection circuit, said sense amplilifier circuit and said data latch circuit, for generating said sense activation signal and said latch activation signal, said timing generating means characterized by comprising: a plurality of timing generating circuits (10-1, 10-1', 10-2, 10-3, 10-3') for prolonging said address transition detection signal by different delay times (τ 1 , τ 2 , τ 3 ) to generate pulse width signals ( 1 ,  2 ,  3 ), said delay times having different characteristics depending upon a power supply voltage (V CC ); a first logic circuit (11), connected to said timing generating circuits, for logically adding said pulse width signals to each other to generate a logic signal ( s '); a pulse prolonging circuit (12, 13), connected to said first logic circuit, for prolonging said logic signal by a definite time to generate said sense activation signal; and a pulse generating circuit (14), connected to said first logic circuit, for generating said logic signal in response to a termination of said first logic signal. The device as set forth in claim 1, wherein a first one of said delay times corresponds to a first delay time (τ 1 ) of bit lines included in said memory cell array when said power supply voltage is smaller than a first voltage (V CCA ), a second one of said delay times corresponds to a second delay time (τ 3 ) of word lines included in said memory cell array when said power supply voltage is larger than a second voltage (V CCB ) larger than said first voltage, a third one (τ 2 ) of said delay times being an intermediate delay time (τ 2 ) between said first and second delay times. The device as set forth in claim 2, wherein a first one (10-1) of said timing generating circuits corresponding to said first delay time comprises: a plurality of inverters (1101) arranged in series; a plurality of RC circuits (1102, 1103) each connected between said inverters; and a second logic circuit (10-1B) connected to a number of said inverters. The device as set forth in claim 2, wherein a second one (10-1) of said timing generating circuits corresponding to said second delay time comprises: two wave-shaping circuits (1105) arranged in series; an RC circuit (1106, 1107) connected between said inverters; and a third logic circuit (10-3B) connected to inputs and outputs said wave-shaping circuits. The device as set forth in claim 2, wherein a third one (10-2) of said timing generating circuits corresponding to said second delay time comprises: a plurality of inverters (1104) arranged in series; and a fifth logic circuit (10-2B) connected to a number of said inverters. The device as set forth in claim 2, further comprising: a pseudo bit line (BL) similar to one of said bit lines, connected between said address transition detection circuit and a first one (10'-1) of said timing generating circuits; and a pseudo word line (WL) similar to one of said word lines, connected between said address transition detection circuit and a second one (10'-3) of said timing generating circuits. The device as set forth in claim 6, wherein said first one of said timing generating circuits comprises: a waveshaping circuit connected to said pseudo bit line; and a flip-flop (1801) which is reset by one of said address transition detection signals and is set by output of said wave-shaping circuit. The device as set forth in claim 6, wherein said second one of said timing generating circuits comprises: a waveshaping circuit connected to said pseudo bit line; and a flip-flop (1802) which is reset by one of said address transition detection signals and is set by an output of said wave-shaping circuit. The device as set forth in claim 6, wherein a third one (10-2) of said timing generating circuits comprises: a plurality of inverters (1104) arranged in series; and a sixth logic circuit (10-2B) connected to a number of said inverters.

Inventors: SUZUKI KOUICHI, SUZUKI, KOUICHI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1997
Main classification: G11C8
IPC codes: G11C8, G11C7