Test signal generator for a vestigial transmission system and method

Abstract: A test signal generator presents a test signal of pseudorandom data in a format which simulates the Grand Alliance Transmission Layer Signal for the 8- or 16-vestigial sideband (8/16-VSB) signal for Advanced Television (ATV) systems. An actual (non-test) Transmission Layer 8/16-VSB signal for ATV is in a particular format and includes data which have been randomized, Reed-Solomon coded, interleaved, and trellis coded.

Description: The present invention relates to devices and methods for generating test signals which simulate known signals having a specific format, and in particular to a device and method for generating a test signal which includes sync symbols and pseudorandom numbers in specific portions. Some transmission systems transmit highly complex signals which include specific types of information in specified locations. The test signals which are used to test such systems must simulate the highly complex signals in order to provide a realistic test. By way of example, one such transmission system is the 8- or 16-vestigial sideband (8/16-VSB) digital transmission system suitable for data transmission for use with the Grand Alliance Advanced Television (ATV) system. The ATV VSB transmission system is known. The 8-VSB system operates in a broadcast mode with 8-level symbols (3 bits per symbol) and the 16-VSB system may operate in higher data rate cable mode with 1 6-level symbols (4 bits per symbol.) Data are received serially and randomized, forward-error-corrected (FEC) using a Reed-Solomon coding technique, interleaved and trellis coded. The format for this Transmission Layer signal is a data frame which includes sync signals, such as illustrated in Figure 1. A data frame for the Transmission Layer 8-VSB system includes 626 segments which are each 832 symbols long. The first 4 symbols in each segment are segment sync symbols. Segments which convey data are in the format shown in Figure 2, where the data is formatted in the manner discussed above (randomized and coded.) The data segments include the FEC codes. Certain segments (the first and 314th in the 8-VSB format) include field sync information and are in the format shown in Figure 3. Figure 3 shows the field sync segments including the four segment sync symbols followed by 511 symbols of pseudorandom numbers (pseudorandom numbers simulate a random signal in that their density function approaches a Gaussian distribution, but are not entirely random in that the signal is deterministic and is based upon a high order polynomial generating function.) These are followed by three sequences of 63 pseudorandom numbers (the middle sequence being inverted in every other field sync, in other words the middle sequence in field sync #2 in Figure 1 is inverted with respect to the middle sequence of field sync #1), which are followed by 24 symbols that describe the VSB mode, by 92 symbols which have not yet been assigned a purpose, and by 12 symbols which repeat the last 12 symbols of the previous segment. The pseudorandom numbers may be generated by a polynomial generator with a specified preload ( e . g ., X 6 + X + 1 with preload 100111 for the 63 symbols). DATABASE WPI Section El, Week 7947 Derwent Publications Ltd., London, GB; Class W02, AN 79-K9805B XP002045543 & SU 650 248 A (KRIVOSHEEV M I), 28 February 1979 discloses a digital TV test signal generator which inserts a pseudo random sequence into a fixed sync frame received from a real input digital TV signal. BENOIT LEDOUX ET AL: 'ADVANCED TELEVISION SIGNAL GENERATION FOR STUDY OF INTERFERENCE INTO NTSC' IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, vol. 39, no. 3, 1 August 1993, pages 684-690, XP000396349 discloses an arbitrary function generator for advanced television which generates a pseudo random test sequence. A test signal which simulates the Transmission Layer 8/16-VSB signal necessarily includes data frames. For example, each segment must include the segment sync symbols at the beginning, and each field sync segment must include all of the proper symbols in their appropriate location. Further, each data frame should include pseudorandom data. It is an object of the present invention to provide a device and method for generating a test signal which simulates a real signal which has a specified format for generating a test signal which simulates a real signal in a specified format where the data are pseudorandom, and to generate a test signal which simulates an unmodulated, unfiltered, 8/16-level, 8/16-VSB signal for a Grand Alliance ATV television signal transmission system. Another object is to provide a test signal in a format which simulates a real signal of M symbols which has certain of the symbols which are sync symbols and other of the symbols which are data symbols, and in which the test signal generator includes a counter for providing a symbol count at a rate which simulates the real signal, a logic unit for generating instructions upon receipt of predetermined ones of the symbol count, a sync symbol generator for generating the sync symbols upon receipt of predetermined ones of the instructions and a pseudorandom number generator for generating pseudorandom symbols upon receipt of other predetermined ones of the instructions, and a multiplexer for combining the sync symbols and the pseudorandom symbols to provide an output which simulates the real signal. Test signal generators and a method in accordance with the present invention are defined by claims 1, 4, 6 and 9, respectively. The invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 is a diagram of a data frame of a 8-VSB signal of the prior art. Figure 2 is a diagram of a data segment of the data frame of Figure 1. Figure 3 is a diagram of a field sync segment of the data frame of Figure 1. Figure 4 is a block diagram of an embodiment of the present invention. Figure 5 is a block diagram of an embodiment of the counter of Figure 4. Figure 6 is a block diagram of further symbol generators which may be added to the embodiment of Figure 4. Figure 7 is a block diagram of a further embodiment of the present invention illustrating the symbol generators and multiplexers for emulating a 8-VSB signal. A preferred embodiment depicts a test signal generator with a test signal of pseudorandom data in a format which simulates the Grand Alliance 8-vestigial sideband (8-VSB) signal for Advanced Television (ATV) systems. An actual (non-test) Transmission Layer 8-VSB signal for ATV is in a particular format with properly formatted sync information and includes data which have been randomized, Reed-Solomon coded, interleaved, and trellis coded. The test signal generator herein provides data in the particular 8-VSB format which simulates the Grand Alliance transmission signal. The design of the generator may be expanded to simulate the 16-VSB format. Figure 4 is a preferred embodiment of the test signal generator 10 including a counter 12 for providing a symbol count (SYM) at a rate which simulates symbol transmission in the real signal and a segment count (SEG) for each segment, a logic unit 14 for generating instructions upon receipt of predetermined ones of the symbol count, a sync symbol generator 16 for generating the sync symbols upon receipt of segment sync the instructions (SSI), a pseudorandom number generator 18 for generating pseudorandom symbols upon receipt of data instructions (Dl), and a multiplexer 20 for combining the sync symbols and the pseudorandom symbols to provide an output which simulates the real signal. The counter 12 is illustrated in Figure 5. A conventional counter 22 may count clock signals to provide a symbol count, and a conventional counter 24 may count the symbol count to provide a segment count. Logic unit 14 may be any conventional processor capable of receiving count inputs and providing enabling signals at predetermined counts. Operation of the test signal generator may include the provision of a clock signal (CLK) which simulates the rate at which symbols in the real signal are transmitted. Each of the clock signals triggers a symbol count, and the correct number of symbol counts trigger a segment count (that is, where each segment has 832 symbols, a segment count will be triggered and the symbol count reset to zero when the symbol count reaches 832.) Logic unit 14 generates instructions at specific counts. For example, when the segment being simulated is a data segment, a segment sync instruction for causing sync generator 16 to generate four sync symbols may be generated when the symbol count is one, and an instruction for causing pseudorandom number generator 18 to generate plural pseudorandom numbers may be generated when the symbol count is five. Logic unit 14 may include all of the appropriate symbol counts for enabling symbol generators at the appropriate times, and may include specific symbol counts for specific segments to simulate a data frame of any arrangement. Multiplexer 20 may combine the symbols from the symbol generators to thereby present a data frame which simulates the one in the real signal. Some data frames, such as those of the 8-VSB signal, may be more efficiently simulated by providing separate symbol generators for parts of the data frame. For example, and with reference to Figure 6, further pseudorandom number generators 26 and nonrandom number generator 28 may receive specific instruction signals from logic unit 14 and provide appropriate symbols through a second multiplexer 30 to multiplexer 20 for inclusion in the simulated signal. The segments in Figures 2 and 3 may be simulated using a device 40 depicted in Figure 7 which omits counter 12 and logic unit 14 in the interest of clarity. With reference also to Table 1 below, consider first a data segment from Figure 2 (that is, a segment other than field sync segments which are segment numbers 1 and 314 in the 8-VSB signal.) Upon receipt of a symbol count of 1 from counter 12, logic unit 14 provides a segment sync instruction (SSI) to segment sync symbol generator 42 which generates the four sync symbols which comprise the segment sync portion of the segment. A symbol count of five triggers provision of a first data instruction (DI-1) to pseudorandom number generator 44 which generates the 828 symbols of pseudorandom numbers which comprise the data portion of the segment. The sync symbols and the pseudorandom numbers are combined in first multiplexer 46 to provide an output which simulates the data segment of Figure 2. The field sync segment of Figure 3 may be formed using additional number generators. When the segment count is 1 and 314 (the field sync segments) a symbol count of 1 initiates instruction SSI to segment sync symbol generator 42 which provides the first four sync symbols. A symbol count of five triggers data instruction DI-2 which causes pseudorandom number generator 48 to generate 511 pseudorandom numbers, followed by a count of 516 which triggers instruction DI-3 which causes pseudorandom number generator 50 to generate 63 pseudorandom numbers three times, followed by a count of 705 which triggers instruction DI-4 which causes number generator 52 to generate the 24 nonrandom symbols which comprise the mode indication ( e . g ., the 8-VSB, 3 bits per symbol, broadcast mode, or the 16-VSB, 4 bits per symbol cable mode), and followed by a count of 821 which triggers instruction DI-5 which causes number generator 54 to generate the 12 nonrandom symbols which comprise the precode symbols (these are the last 12 symbols from the previous data segment.) The second of the three sequences of 63 numbers may be inverted to match Grand Alliance specifications and a separate inversion instruction DI-3' may be provided for this purpose (in the Grand Alliance, inversion may be used for field sync identification). Instruction DI-3 may be repeated to provide pseudorandom numbers to fill in the "reserved" portion of the field sync segment. Other symbols may be provided as needed, or to meet the symbol requirements of the "reserved" portion if these symbol generators are not adequate. A clock signal CLK may be provided to each component, and a second multiplexer 56 may combine symbols from generators 48-54. INSTRUCTION SYMBOL COUNT SEGMENT COUNT SSI, SEG SYNC 1-4 ALL DI-1, PN GEN 1 5-832 ALL but 1 and 314 DI-2, 511 PN GEN 5-515 1, 314 DI-3, 63 PN GEN 516-704 1, 314 729-820 1, 314 DI-3', 63 PN GEN INV 578-640 314 DI-4, MODE 705-728 1, 314 DI-5, FIFO 821-832 1, 314 In the embodiment of Figure 7, separate instructions may be provided to first multiplexer 46 and to second multiplexer 56 to facilitate proper combination of the symbols. The operation of the separate instructions, FS SEL 1 and 2 and GA SEL 1 and 2, may be seen from Table 2 below. Table 2 also takes into account a two symbol delay that is inserted into segment sync symbol generator 42 to match the timing of the data which is particular to this embodiment and may not be required in other embodiments. INSTRUCTION SYMBOL COUNT SEGMENT COUNT SEG SYNC 1-4 ALL PN GEN 1 ALWAYS ON ALL 511 PN GEN 5-515 1, 314 63 PN GEN 516-704 1, 314 729-820 1, 314 63 PN GEN INV 578-640 314 MODE 705-728 1, 314 FIFO 821-832 1, 313, 314, 626 FS SEL 1 518-822 1, 314 FS SEL 2 707-730 1, 314 823-832 1, 314 1-2 2, 314 GA SEL 1 3-6 ALL GA SEL 2 7-832 1, 314 1-2 2, 315 A test signal generator presents a test signal of pseudorandom data in a format which simulates the Grand Alliance Transmission Layer Signal for the 8- or 16- vestigial sideband (8/16-VSB) signal for Advanced Television (ATV) systems. An actual (non-test) Transmission Layer 8/16-VSB signal for ATV is in a particular format and includes data which have been randomized, Reed-Solomon coded, interleaved, and trellis coded.

Claims: A test signal generator for providing a test signal in a format which simulates a real signal of M symbols which has certain of the symbols which are sync symbols and other of the symbols which are data symbols, the test signal generator comprising: counter means (12) for providing a symbol count at a rate which simulates the real signal; logic means (14) for generating instructions upon receipt of predetermined ones of the symbol count; symbol generator means (16, 18) for generating the sync symbols upon receipt of predetermined ones of the instructions and for generating pseudorandom symbols upon receipt of other predetermined ones of the instructions; and means (20) for combining the sync symbols and the pseudorandom symbols to provide an output which simulates the real signal. A generator as claimed in Claim 1 wherein said symbol generator comprises a sync symbol generator (16) for providing m sync symbols at a beginning of each test signal, in which said symbol generator comprises a first pseudorandom number generator (18) for providing a plurality of pseudorandom numbers following the m sync symbols, and preferably said symbol generator comprises plural second pseudorandom number generators (26), each for providing a plurality of pseudorandom numbers upon receipt of a different one of the instructions. A generator as claimed in Claim 2 wherein said symbol generator further comprises an nonrandom number generator (28) for providing plural nonrandom numbers upon receipt of a different one of the instructions, and wherein said means for combining combines the plural nonrandom numbers with the m sync symbols and the plurality of pseudorandom numbers. A test signal generator for presenting a test signal in a format which simulates a data signal having a multiplicity of data frames, each of the frames with N segments, and each of the N segments with M symbols, m of which are sync symbols, the test signal generator comprising: means for providing clock signals; counter means (12) for providing a symbol count for each of the clock signals and for providing a segment count after M of the symbol count; logic means (14) for generating data instructions upon receipt of predetermined ones of the symbol count and for generating segment sync instructions upon receipt of predetermined ones of the segment count; sync symbol generator means (16) for generating m sync symbols upon receipt of a one of the segment sync instructions; first pseudorandom number generator means (18) for generating a plurality of pseudorandom numbers upon receipt of a one of the data instructions; and a first multiplexer (20) for combining the m sync symbols and the pseudorandom numbers to provide an output which simulates the data signal. A generator as claimed in Claim 4 characterized by plural second pseudorandom number generator means (26), each for providing a plurality of pseudorandom numbers responsive to different ones of the data instructions, including a second multiplexer (30) for combining the pseudorandom numbers from said plural second pseudorandom number generator means (26) and for providing the combination to said first multiplexer (20), and preferably the data signal has ones of the N segments which are field sync segments, and wherein said logic means (14) is further for providing ones of the data instructions which are field sync instructions indicating that the output is to be one of the field sync segments, and further wherein said plural second pseudorandom number generator means (26) are for responding to the field sync instructions. A test signal generator for presenting a test signal in a format which simulates a field sync segment of a data frame which has N segments, where each of the N segments has M symbols, some of which are pseudorandom, and the field sync segment is in predetermined ones of the N segments, the test signal generator comprising: means for providing clock signals; counter means (12) for providing a symbol count for each of the clock signals and for providing a segment count after M of the symbol count; logic means (14) for generating data instructions upon receipt of predetermined ones of the symbol count and for indicating ones of the N segments for which the test signal is to be generated; plural pseudorandom number generators, each for generating a piurality of pseudorandom numbers upon receipt of a different one of the data instructions, when the test signal is generated; and means (46, 56) for combining the pseudorandom numbers to provide an output which simulates the field sync segment. A generator as claimed in Claim 6 wherein the test signal simulates the field sync segment of the data frame of an 8-level vestigial sideband signal for a high definition television system, including a sync symbol generator for generating m sync symbols at a beginning of each of the test signals, and the test signal further comprises nonrandom numbers and wherein the generator further comprises number generator means for generating a plurality of nonrandom numbers upon receipt of ones of the data instructions, when the test signal is generated, and wherein said means (46, 56) for combining is further for combining the nonrandom numbers to simulate the field sync segment. A generator as claimed in claims 6 or 7 wherein the test signal simulates the field sync segment of the data frame of a Transmission Layer 8- or 16-vestigial sideband (8/16-VSB) signal for an Advanced Television (ATV) system, and comprising, two of said plural pseudorandom number generators (48, 50), one (48) for generating a predetermined sequence of 511 pseudorandom numbers upon receipt of a first of the data instructions, and the other (50) for generating a predetermined sequence of 63 pseudorandom numbers upon receipt of second, third and fourth of the data instructions, and further comprising, a sync symbol generator (42) for generating 4 sync symbols at a beginning of each test signal, a number generator (52) for generating 24 nonrandom symbols indicating a 8-VSB or 16-VSB mode upon receipt of a fifth of the data instructions, and wherein said means (46, 56) for combining is for combining, in order, the 4 sync symbols, the 511 pseudorandom numbers, the 63 pseudorandom three times, the 24 nonrandom symbols and 92 further symbols from one of said plural pseudorandom number generators. A method of generating a test signal in a format which simulates a real signal of M symbols which has certain of the symbols which are sync symbols and other of the symbols which are data symbols, the method comprising the steps of: providing a symbol count at a rate which simulates the real signal; generating instructions upon receipt of predetermined ones of the symbol count; generating the sync symbols upon receipt of predetermined ones of the instructions; generating pseudorandom symbols upon receipt of other predetermined ones of the instructions; and combining the sync symbols and the pseudorandom symbols to provide an output which simulates the real signal, and the step of generating the sync symbols comprises the step of providing m of the sync symbols at a beginning of each test signal. A method as claimed in Claim 9 wherein the step of generating pseudorandom symbols comprises the step of providing a plurality of pseudorandom numbers following the m sync symbols, in which the step of generating pseudorandom symbols comprises the step of providing different pluralities of pseudorandom numbers upon receipt of different ones of the instructions, and preferably providing plural nonrandom numbers upon receipt of a different one of the instructions, and combining the sync symbols and the pseudorandom symbols to provide an output which simulates a Transmission Layer signal of an 8/16-VSB signal for a television system. A method as claimed in Claim 10 wherein the step of generating pseudorandom symbols comprises the step of providing 511 pseudorandom numbers upon receipt of a first of the instructions, and providing 63 pseudorandom numbers upon receipt of second, third and fourth of the instructions, and the step of generating the sync symbols comprises the step of providing 4 sync symbols at a beginning of each test signal, further comprising the step of generating 24 nonrandom symbols indicating a 8-VSB mode upon receipt of a fifth of the instructions, and the step of combining combines, in order, the 4 sync symbols, the 511 pseudorandom numbers, the 63 pseudorandom three times, the 24 nonrandom symbols and 92 further pseudorandom numbers.

Inventors: SECCIA JOSEPH L, TWITCHELL EDWIN R, SECCIA, JOSEPH L., TWITCHELL, EDWIN R.
Applicants: HARRIS CORP, HARRIS CORPORATION
Application year: 1997
Main classification: H04N17
IPC codes: H04L27, H04L1, H04N17