Process for realizing cross-point memory devices with cells having a source channel that is self-aligned to the bit line and to the field oxide

Abstract: The invention relates to a process of manufacturing cross-point matrix memory devices which have floating gate memory cells having the source channel self-aligned to the bit line and the field oxide. The process comprises the steps of: growing a thin layer (3) of tunnel oxide on the matrix region; depositing a stack structure comprising a first conductive layer (4), an intermediate dielectric layer (5), and a second conductive layer (6); photolithographing with a Poly1 mask to define a plurality of parallel floating gate regions (13) in said stack structure; self-aligned etching of said stack structure (4,5,6), above the active areas, to define continuous bit lines; implanting, to confer predetermined conductivity on the active areas (10). Advantageously, the self-aligned cascade etching step for removing parallel strips from multiple layers, down to the active areas of the substrate (1), is discontinued before the field oxide (2) is removed, and the implantation step is carried out in the presence of field oxide (2) over the source active areas (10).

Description: Field of the Invention This invention relates to a process of manufacturing cross-point memory devices which have cells with the source channel self-aligned to the bit line and to the field oxide. Specifically, the invention relates to a process of manufacturing cross-point matrix memory devices which have floating gate memory cells formed on a semiconductor substrate by a plurality of continuous bit lines laid across the substrate into discrete parallel strips, separated by active areas having the source channel self-aligned to the bit line and/or an isolation field oxide, the process comprising the steps of: growing a thin layer of tunnel oxide on the matrix region; depositing a stack structure comprising a first conductive layer, an intermediate dielectric layer, and a second conductive layer; photolithographing with a Poly1 mask to define a plurality of parallel floating gate regions in said stack structure; self-aligned etching of said stack structure, above the active areas, to define said continuous bit lines; implanting, to confer predetermined conductivity on the active areas. The invention concerns in particular, but not exclusively, a process of manufacturing semiconductor integrated memories of the contact-less type which are provided with virtual ground circuitry, and reference will be made, throughout this specification, to that particular field of application for convenience of explanation. Background Art As is well known, electronic memory devices of the EPROM or FLASH-EPROM type require that a matrix type of layout be produced on a semiconductor substrate wherein a plurality of bit lines, formed of floating gate regions, are crossed over by a plurality of conductive strips, or word lines. A known process of manufacturing memory devices of the EPROM or E 2 PROM type, more particularly EPROM, FLASH EPROM and EEPROM memory devices of the virtual ground, cross-point type, is described in European Patent No. 0 573 728, for example. This prior document discloses an integrated device of the EPROM or FLASH EPROM type, wherein individual memory blocks include a matrix of cells comprising a plurality of word lines and a plurality of bit lines, lying orthogonally to each other. The multiple cross-points between the word lines and the bit lines define the memory cells. A structure of this kind is known in the art as a "tablecloth" or cross-point matrix, and is peculiar in that the bit lines are formed in the semiconductor substrate by parallel, continuous diffused strips. The novel aspect of this particular arrangement resides in the absence of metal contacts from the substrate area which is to accommodate the integrated memory cells; this feature greatly expands the capacity for integration on the semiconductor substrate. Metal contacts are only formed at the opposite ends of the bit lines, and provide termination pads for each memory block. For the present invention to be more readily understood, the conventional processing steps involved in defining, on a semiconductor substrate, the matrix layout of a virtual ground EPROM device having bit lines with floating gate regions will be recalled briefly herein below. Starting with a semiconductor substrate 1, such as that shown in Figure 1, which has been provided with a pattern of active areas and an optional layer 2 of field separation oxide, multiple depositions are performed over the entire substrate surface. A thin layer 3 of tunnel oxide is deposited first. Thereafter, a first layer 4 of polysilicon, referred to as the Poly1, is deposited. This is followed by the deposition of a second dielectric layer 5 of the interpoly type, e.g. of ONO, which is then topped with a further deposition of a second layer 6 of polysilicon, the latter being also referred to as the poly cap. At this stage, a photolithographic step using a mask 16, also referred as the Poly1 mask or 556 mask hereinafter, is carried out to define the layouts of the gate regions and their associated bit lines. A self-aligned cascade etching step is carried out next to remove parallel strips from multiple layers, down to the active areas of the substrate 1. This cascade etching operation will remove the poly cap layer 6, ONO layer 5, Poly1 layer 4, tunnel oxide layer 3, and field oxide 2 from the unprotected areas by the 556 mask. As a result, a spatial geometry is defined on the semiconductor substrate 1 which includes a plurality of parallel lines, e.g. bit lines of memory cells and corresponding gate regions 13. Figure 2 is a schematic plan view of the pattern created by the etching step. The gate regions 13 are formed of the stack or stacked structure of poly cap-ONO-Poly1-tunnel oxide and an optional field oxide, as shown in Figure 1A. After completion of the self-aligned etching, the 556 mask is removed and a second mask, referred to as the 585 mask, is formed to allow for a source implantation to be performed. The 585 mask comprises long strips running parallel to the bit lines and fully covering drain lines 17, and in part the poly cap layer 6 as well. Subsequent implantations are performed with phosphorus P and arsenic As in the active area regions which form the source lines 10, where they are needed to provide a gradual profile junction, specially adapted for erasing the memory cell. The phosphorus implantation results in a well 9 being formed which accommodates a smaller well 8 on its interior. P and As implants are also provided in the source regions or lines 10, where the field oxide 2 was present. In these regions, the phosphorus and arsenic implantation wells are denoted by the numbers 7 and 14, respectively. This is followed by a re-oxidation thermal treatment. Subsequently, a dielectric layer, e.g. of TEOS, is deposited to evenly cover the whole structure. This dielectric layer is then etched back to define isolation spacers 12 which are laterally contiguous to each gate region 13. This etching step is an anisotropic process conducted to simultaneously form the spacers 12 as well as openings 11 having a slight flare-out. Figure 1B shows the resultant structure, at the end of this TEOS back etching step and the start of an arsenic implantation step for both the source lines 10 and drain lines 17. This step is customarily referred to as the source and drain implantating step. The processing steps described above are listed in sequential order herein below for convenience of illustration and of comparison to the inventive process to be described: 1) deposition of layers 3, 4, 5 and 6; 2) 556 masking (bit lines); 3) poly cap 6 etching; 4) ONO etching; 5) Poly1 etching; 6) field oxide etching (self-aligned source and drain etching; 7) removal of 556 mask; 8) 585 masking (source implantation); 9) P implant & As implant; 10) re-oxidation thermal treatment of cell; 11) TEOS deposition and etching; 12) source and drain (S&D) arsenic implantation. Turning back to the process step of implanting phosphorus and arsenic, it will be appreciated that the phosphorus implant diffuse more than the arsenic implant in consequence of the thermal treatment. Accordingly, the effective length Leff of the cell will be the distance separating the well 9, formed in implanting the phosphorus on the source line 10 side, from the well 8, formed in implanting the arsenic on the drain line 17 side. Figure 2 is a schematic top view, drawn to an enlarged scale, of the layout of a semiconductor portion as subjected to conventional processing steps. Shown in that Figure is a section line a-a' which lies parallel to the word lines of the cell matrix, in the active area zones unoccupied by field oxide. Figure 2A is a schematic, vertical section view of the semiconductor, taken along said line a-a'. Figure 2B is a schematic, vertical section view of the semiconductor, taken along a second line b-b' and highlighting regions where the field oxide is present. From a comparison of Figures 2A and 2B, it can be appreciated that in the zone of the bit line 13 underlying the field oxide 2, the distance Lpar between wells 7 and 14, as respectively formed by a phosphorus implant and an arsenic implant, is equal to Leff. The distance Lpar is a mere parasitic distance between the wells 7 and 14, and the distance Leff is the spacing of the drain and source implant wells, both under the field and under the active area. Electrical data from analyses of memory cell performance show that as the length Leff decreases, the number increases of the devices that fail the test due to a leakage current 15 flowing beneath the bit line to communicate the source line 10 to the drain line 17. These leakage current paths may occur both under the active area zone of the bit line (region F in Figure 2) and under the zone underlying the field of the bit line (region G in Figure 2). Such a problem obviously imposes a dimensional constraint whereby the width of the bit line, and with it the overall dimensions of the memory device, cannot be reduced. The underlying technical problem of this invention is to provide a process of manufacturing cross-point memory devices which include cells having a source channel self-aligned to the bit line and the field oxide, which process would concurrently manufacture leakage currents less likely to occur, even where the width of the bit lines is reduced. Summary of the Invention The solution idea behind this invention is one of discontinuing the etching step with a Poly1 mask, upon the field oxide being reached, and of performing the phosphorus and arsenic implantations while field oxide is still present over the source lines. Based on this solution idea, the technical problem is solved by a process as previously indicated and defined in the characterizing part of Claim 1. The features and advantages of a process according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings. Brief Description of the Drawings In the drawings: Figure 1 is an enlarged vertical section view showing schematically a portion of a semiconductor as subjected to certain conventional process steps which result in the formation of bit lines in a memory matrix of the cross-point type; Figures 1A and 1B are respective enlarged vertical section views showing schematically the semiconductor portion of Figure 1 as subjected to further conventional process steps; Figure 2 is an enlarged top view showing schematically the layout of a semiconductor portion subjected to conventional process steps; Figure 2A is an enlarged vertical section view showing schematically a portion of the semiconductor in Figure 2 and taken along the line a-a'; Figure 2B is an enlarged vertical section view showing schematically a portion of the semiconductor in Figure 2 and taken along the line b-b'; Figures 3, 3A and 3B correspond to Figures 1, 1A and 1B, but relate to the process of this invention; Figure 4 is an enlarged vertical section view, taken along the line a-a' and showing schematically a portion of the semiconductor in Figure 2 as subjected to the process steps of this invention; Figure 5 is an enlarged vertical section view, taken along the line b-b' and showing schematically a portion of the semiconductor in Figure 2 as subjected to the process steps of this invention. Detailed Description Referring to the drawing views, in particular to the examples of Figure 3 foll., the process of this invention goes at first through the same steps as are provided in conventional processes. This process will be referred to as the SASFOX (Self-Aligned Source Field OXide) process, for brevity hereinafter. Specifically, the first five steps previously described in connection with the background art are also carried out in the SASFOX process of this invention, and will be described no further herein. Figure 3 shows schematically the semiconductor as delivered from the aforesaid five process steps, and corresponds essentially to Figure 1. At this stage, the SASFOX process according to this invention diverges from the conventional process in that the self-aligned cascade etching step, resulting in the removal of parallel strips from multiple layers down to the active areas of the substrate 1, is discontinued before the field oxide 2 is removed. This cascade etching will remove, from the unprotected areas by the 556 mask, the poly cap layer 6, ONO layer 5, and layer 4 of Poly1. The next steps of the SASFOX process consist, of removing the 556 mask, providing the 585 mask for the source implantation, implanting with phosphorus and arsenic, and removing the 585 mask, in this order. As best shown in Figure 3A, for some portions of the memory device, the phosphorus and arsenic implanting step is carried out in the presence of field oxide 2 over the source lines 10. It is only after completion of this etching step that the field oxide 2 will be removed. The etching away of the field oxide 2 is carried out without the use of a mask. A breakdown list of the successive steps in the SASFOX process according to this invention is given here below for convenience: 1a) deposition of layers 3, 4, 5 and 6; 2a) 556 masking; 3a) poly cap 6 etching; 4a) ONO etching; 5a) Poly1 etching; 6a) 556 mask removal; 7a) 585 masking (source implantation); 8a) P implant & As implant; 9a) 585 mask removal; 10a) field oxide etching (self-aligned source and drain etching); 11a) re-oxidation thermal treatment of cell; 12a) TEOS deposition and etching; 13a) source and drain arsenic implantation. The SASFOX process being highly selective to the poly, the loss in thickness of the poly cap 6 during the field oxide etching can be limited to less than 300Å, and would not affect the electric characteristics of the device. The etching of the field oxide 2 entails partial removal of the silicon from the active area, which also results in partial removal, from the source region at C in Figure 2, of arsenic dopant not yet diffused. This potential problem can be avoided by an increase of implantation energy, thereby sinking the arsenic to greater depth. In the SASFOX process according to the invention, the implantation of phosphorus and arsenic using the 585 mask only affects the source active area regions (region C in Figure 2), since the region D would still be covered with unetched field oxide 2. The SASFOX process steps then continue in the same manner as previously described in connection with the background art, and on completion of the last source and drain arsenic implanting step, the profile of the doped areas of the bit lines will be that shown in Figures 4 and 5. It can be appreciated from the Figures that the distance Lpar between implant wells in the region G of the bit line visibly exceeds the effective length Leff, thereby manufacturing a leakage current in that area less likely to occur. It should be noted that this result is obtained without changing the electrical dimensions of the cell. In essence, the SASFOX process of this invention can lower the likelihood of current leaking into the bit line region (G) over the field oxide, by providing for an increased length Lpar while leaving the length Leff unchanged. The application of a SASFOX process according to the invention brought out by the structure of the end product, and can be recognized by a SEM analysis of the dopant profiles at the cross-sections a-a' and b-b'.

Claims: A process of manufacturing cross-point matrix memory devices which have floating gate memory cells formed on a semiconductor substrate (1) by a plurality of continuous bit lines laid across the substrate (1) into discrete parallel strips, separated by active areas having the source channel self-aligned to the bit line and/or an isolation field oxide (2), the process comprising the steps of: growing a thin layer (3) of tunnel oxide on the matrix region; depositing a stack structure consisting of a first conductive layer (4), an intermediate dielectric layer (5), and a second conductive layer (6); photolithographing with a polysilicon mask to define a plurality of parallel floating gate regions (13) in said stack structure; self-aligned etching of said stack structure (4,5,6), above the active areas, to define said continuous bit lines; implanting, to confer predetermined conductivity on the active areas (10); characterized in that the self-aligned cascade etching step for removing parallel strips from multiple layers, down to the active areas of the substrate (1), is discontinued before the field oxide (2) is removed, and said implantation step is carried out in the presence of field oxide (2) over the source active areas (10). A process according to Claim 1, characterized in that said mask of Polyl is removed after said etching step. A process according to Claim 1, characterized in that the field oxide (2) is removed after said implantation step. A process according to Claim 1, characterized in that the etching of the field oxide (2) is performed without a mask.

Inventors: COLABELLA ELIO, COLABELLA, ELIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1997
Main classification: H01L21
IPC codes: H01L21