BANDWIDTH REGULATION SYSTEM FOR MULTICHANNEL MEMORY ARRAYS

Abstract: A multichannel information system includes a plurality of input/output devices coupled to a plurality of array controllers through a rotating commutator. Each array controller is coupled to and controls a plurality of disk groups operating as memory arrays. Each input/output device communicates data to and from the array controllers in a plurality of data channels. A bandwidth regulation system is operative within each array controller to authorize channel bandwidths for each application run in the system and to prevent transitory bandwidth demands within any channel from interfering with previously authorized channel bandwidths.

Description: Bandwidth regulation system for multichannel memory arrays. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generally to plural user memory arrays and particularly to those processing data in a plurality of data channels. 2. Description of Related Art In many information systems, a need arises to store and retrieve large amounts of data from memory arrays utilizing a plurality of commonly controlled memory devices while providing high speed data flow rates. The amount of data and the speed with which the data is to be stored and retrieved within any given data channel is typically expressed as a channel bandwidth. This bandwidth in turn is usually quantified in terms of the number of bytes of data per second flowing through the channel. Many high speed, high bandwidth data systems are operative to serve a plurality of simultaneous users. In addition, such systems often process different types of data simultaneously within the various data channels. One environment in which such high speed, high bandwidth data storage and retrieval systems are operative to serve a plurality of users is found in video server systems. The basic operation of video servers is relatively simple to identify in that a large array of memories is provided with a plurality of input/output systems which are operative to store input data within the memory array and retrieve output data from the memory array. In a typical video server, the memory array is formed of a plurality of disk drive memories operating under the control of an array controller. Each user or viewer served by a video server system is actually utilizing a plurality of data channels for processing various forms of data such as video data, audio data, and control or timing code information which combine to form the program material. While early video servers were, in essence, multiple channel players and recorders, more recent video server systems have provided interactive capability for the user. Such interactive systems are usually referred to as video-on-demand systems. In interactive systems, each user is able to independently control the data flow by exercising various options or features such as fast forward, reverse, pause and program switching. These features are similar to features which users of individual videotape recorders enjoy. These various features are extremely advantageous and desirable for the user. However, such features also place great performance burdens upon the video server system. For the most part, video servers are well suited to steady normal play or record operation but are often hard pressed to accommodate accelerated data demands and rapid changes such as fast forward or the like. Such changes require generally substantial increases in the data flow rate or bandwidth of the various channels serving the user. In attempting to meet increased channel bandwidth demands of users exercising features such as fast forward or the like, video systems may allow other channels to suffer data interruption. As a result, the cost of interactive capability for many video servers may be a reduction in the quality of overall system performance. In the video art, interruption of normal steady-state "play" operations is a serious system malfunction and should be avoided if possible. One of the most effective and innovative systems for providing a video server is set forth in the related United States Patent 5,539,660, which is assigned to the assignee of the present application. The system set forth therein utilizes a plurality of input/output modules, usually referred to as VR cards, which communicate with a plurality of array controllers through a rotating commutator. The commutator functions to sequentially couple each VR card to each array controller in a repeating sequential coupling. Each array controller in turn is coupled to a disk manager which operates and controls a plurality of disk drive memories. Data flows to and from the array controllers and their respective pluralities of disk drive memories in response to requests made by the VR cards for access to the array controller. Each VR card simultaneously processes a plurality of individual data streams usually referred to as channels. Thus, as an application is run, the VR card running the application is sequentially coupled to each array controller within the plurality of array controllers for a brief interval during which the VR card presents requests for access to the disk drive memories through the array controller. Each VR card makes a sufficient number of requests during its coupling to an array controller to meet the data flow needs of its plurality of channels. This system has proven advantageous and effective due, in part, to the effective distribution of bandwidth across the plural array controllers. When operating in a substantially steady state mode in which a plurality of users are viewing various program materials, the above system is extremely effective. Data is moved quickly and efficiently from the pluralities of disk drive memories with sufficient speed (bandwidth) to maintain apparent continuous data flow to the users. This continuous flow of data is of extreme importance in a video server because of the annoying or even disastrous consequences of data interruption in video systems. Unlike computing systems in which the user is accustomed to delays due to processing time, video system users demand uninterrupted program flow. Thus, in video server systems, failure to maintain steady state data flow to users is to be avoided at all costs. Unfortunately, providing interactive capability requires that video servers must maintain steady state users while also responding to various transitory conditions which often prove disruptive. For example, under certain conditions, such as the initiation of a fast forward mode of operation or during transitions between different programs, the channels within a given VR card may experience a need for increased bandwidth. Unfortunately, the increased bandwidth demands by the VR card in such circumstances together with the bandwidths needed to sustain other channels may exceed the available array controller bandwidth and may cause other channels within the VR card to suffer bandwidth loss or "starve" for data as requests for array controller access begin stacking up at the array controller faster than the system can accommodate. In an application, such as a video server system, this problem may result in a substantial number of users (viewers) having interrupted program material as the system attempts to supply the increased demands of the transitory condition. As a result, there arises a continuing need in the art for an improved system for managing the data flow within multichannel memory arrays which facilitate interactive operation by a plurality of users without interrupting steady-state users. SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide an improved system for operating multichannel memory arrays serving plural users. It is a more particular object of the present invention to provide a bandwidth regulation system for such multichannel memory arrays serving plural users in an interactive mode of operation. It is a still further particular object of the present invention to provide a bandwidth regulation system for use within multichannel memory arrays serving plural users interactively which effectively prioritizes access to the memory array among competing users to maintain data flow to steady-state users despite transitory bandwidth demands. The present invention meets these objectives by providing a system of bandwidth management in which transfers of data to and from the memory array are made in response to requests made by the VR cards. Further, the system operates within the above- described type of video server to maintain existing bandwidths for current normal or steady state channels by forcing channels having increased bandwidth demands due to operational changes to have their requests for access denied by the array controller if an interruption of steady state channels would result. This is accomplished by providing each array controller with a plurality of downcounting timers (one per channel) each of which stores a timer value referred to as the "police timer value" which is peculiar to that channel. Each array controller also includes a request inhibitor controlled by the timer state for each channel. A bandwidth manager and resource manager are provided which process all VR card requests for access to the array controllers. The bandwidth manager monitors various system operating conditions such as total system bandwidth available and current bandwidth in use. The bandwidth manager also computes the police timer value in the form of a time interval for each channel. Each downcounting timer for each channel is set to its police timer value. This police timer value is an inverse function of authorized bandwidth for the channel. Thus, the greater the authorized bandwidth for a channel, the shorter its police timer value. The invention further provides a bandwidth regulation system for use in an information system which stores and/or retrieves data, formatted into a plurality of data channels, to and/or from a memory in response to access requests, the bandwidth regulation system comprising: means for authorizing a channel bandwidth for each of the data channels; means for determining an interval for each data channel inversely related to each respective channel bandwidth; means for timing each interval for each data channel; means for restarting the means for timing within a data channel each time access to the memory is granted within the data channel; and means for inhibiting access to the memory within a data channel unless the means for timing has completed timing of that channel's interval. In the operation of the present invention system within a multichannel information system storing and/or retrieving data to and/or from a memory array, a method of bandwidth regulation is implemented which includes the steps of: receiving access requests within the channels; attempting to place each of the access requests directly into a main queue; placing each access request not directly placed into the main queue in the attempting step into a channel buffer; timing an interval for each channel; transferring an access request from the channel buffer to the main queue after the interval; and restarting the timing interval of each channel when an access request is transferred to the main queue. The multichannel system processes data as access requests made for access to the memory array. When a request for access is granted for a channel, its counter is reset to the channel police timer value and begins downcounting. Thereafter, the bandwidth manager inhibits all further requests for access to the array controller on behalf of that channel until its police timer value has timed out unless unused bandwidth is available within the system. As a result of this system, the authorization process for each application which allocates its initial authorized bandwidth also through the action of the bandwidth manager establishes its police timer value. Under normal operating conditions, the requests for access within a channel will not be affected by the inhibiting action of the bandwidth manager because the channel's police timer value will have timed out before the next request is presented. If, however, a channel begins demanding greater bandwidth, its requests for access will begin occurring faster than the police timer value times out and the access will be inhibited by the bandwidth manager. As requests for access are inhibited, they begin stacking up at the array controller and may only be granted if additional unused bandwidth exists within the system. Most importantly, however, the remaining channels operating within their authorized bandwidths continue to receive timely access to the array controller and are not affected by the increased bandwidth demands of any other channel. Thus, in accordance with the present invention, there is provided a bandwidth regulation system for use in a multichannel information system storing and/or retrieving data to and/or from a memory array, the bandwidth regulation system comprising: means for establishing a time interval for each channel; means for inhibiting access to the memory array for each channel during its time interval; and means for resetting the time interval of a channel following access to the memory array having been given within the channel. Also in accordance with the present invention, there is provided for use in a multichannel information system storing and/or retrieving data to and/or from a memory array, a method of bandwidth regulation comprising the steps of: receiving access requests within the channels; attempting to place each of the access requests directly into a main queue; placing each access request not directly placed into the main queue in the attempting step into a channel buffer; timing an interval for each channel; transferring an access request from the channel buffer to the main queue after the interval; and restarting the timing interval of each channel when an access request is transferred to the main queue. BRIEF DESCRIPTION OF THE DRAWINGS The invention, together with further objects and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in the several figures of which like reference numerals identify like elements and in which: Figure 1 sets forth a block diagram of a bandwidth regulation system for multichannel memory arrays constructed in accordance with the present invention; and Figure 2 sets forth a flow diagram illustrating the operation of the present invention bandwidth regulation system. DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 sets forth a block diagram of a video server system utilizing the present invention bandwidth regulation system and generally referenced by numeral 10. System 10 includes a plurality of VR cards 11, 12, 13 and 14 coupled to a plurality of array controllers 16 through 20 by a commutator 15. Array controllers 16 through 20 are fabricated in the same manner and thus the more detailed illustration of array controller 16 shown in Figure 1 should be understood to be representative of and apply equally well to array controllers 17 through 20. It should also be noted that while Figure 1 shows a video server having four VR cards (11 through 14) and five array controllers (16 through 20), other numbers and combinations of VR cards and array controllers may be utilized in the present invention system. Within array controller 16, a plurality of buffers 24 are provided for receiving multiple channel incoming data to array controller 16. The plural data channels are each coupled to one of buffers 24, the outputs of which are coupled through channels 25 to a requestor 26. Buffers 24 also provide buffering of multiple channel output data through channels 25 from array controller 16 when data is being stored with disks 29 through 34. Requestor 26 is coupled to a disk manager 27 which in turn is coupled to a plurality of disk arrays 29 through 34 via a corresponding plurality of communication busses 28. In their preferred form, communication busses 28 are Small Computer System Interface (SCSI) busses. However, it will be apparent that other communication bus systems may be used. Array controller 16 also includes a delay manager 46 which includes an internal clock providing a timer downcounting signal and a processor operative in the manner shown in Figure 2 below for controlling the communication of access requests to and from disk array manager 27 and requestor 26. Thus, delay manager 46 is coupled to and controls buffers 24, requestor 26 and disk manager 27. Array controller 16 further includes a plurality of down counters 42, one for each of data channels 25, which are all clocked in response to the timer downcounting signal provided by delay manager 46. Each of down counters 42 define a set input which is coupled to bandwidth manager 22 and which, in the manner described below, is used to individually set each down counter to a starting number. The output count number of each of down counters 42 is coupled to delay manager 46. A welfare task 45 is coupled to bandwidth manager 22. A global number register 44 is coupled to welfare task 45 and to delay manager 46. Welfare task 45 and global number 44 cooperate in response to unused bandwidth information provided by bandwidth manager 22 to supply a global number to array controllers 16 through 20 used in the manner described below. As mentioned above, array controllers 17 through 20 should be understood to be identical to array controller 16. Thus, bandwidth manager 22 is coupled to array controllers 17 through 20 in the same manner as is shown for array controller 16. However, to avoid unduly cluttering Figure 1, these couplings are not shown in the figure. Also, each of array controllers 17 through 20 includes a corresponding array of disk groups 50 through 53 respectively. It should be noted that the preferred embodiment of the present invention is provided largely in computer software form. Thus, Figure 1 should not be considered as being limited to hardware implementation, but rather, representative of the functions and operations of such software implementation. In operation and by way of overview, each channel is initially set during the system boot-up process to have either a preset bandwidth or a zero bandwidth. Preset bandwidths are assigned to channels having predictable data bandwidths such as control and time code information. Zero bandwidths are assigned to channels having bandwidths which are initially unknown such as those used for video and audio data. An application is launched or implemented by operation of work station 23. In response, resource manager 21 makes a bandwidth request to bandwidth manager 22. Bandwidth manager 22 then checks for available transport bandwidth and disk bandwidth. Transport bandwidth refers to bandwidth available within the communication paths from the VRs to array controllers via commutator 15. Disk bandwidth refers to the array controller to disk drive memory group communication path. In the event the available bandwidth of either is insufficient, the request is denied and the application is not run. If, however, both are available, the application request is granted. Once an application is granted, the bandwidth manager computes a number referred to as "police timer value" for each channel. The police timer value is computed by dividing the data segment size within the channel by the bandwidth required to support the channel. The police time value is then set within the appropriate one of down counters 42 for that channel. This process takes place for each channel within array controller 16 and results in setting each of down counters 42 at a police timer value. To avoid undue restrictions on bandwidth use, delay manager 46 initially attempts to place each access request directly into the main queue of requestor 26. If the request cannot be placed directly into requestor 26, delay manager 46 places the request within the one of buffers 24 associated with the requesting channel. Once a request is transferred to one of buffers 24, it will be processed in accordance with the police timer value as delay manager 46 cycles through each of the data channels. Delay manager 46 looks for accumulating requests within buffer 24 and moves requests to requestor 26 within each data channel in response to the downcount of each channel police timer value. Once the police timer value is set within each channel down counter, delay manager 46 begins decrementing each of down counters 42 from their respective police timer values and a request inhibitor within requestor 26 is active for each channel to inhibit further access within that channel to array controller 16. Once the down counter associated with a given channel has counted down completely or "timed out", the access inhibitor is deactivated and a request for access to array controller 16 is permitted and passed on to requestor 26 for that channel. From requestor 26, which functions as a "main queue" for access requests, requests are transferred to disk array manager 27 and access to disk groups 29 through 34 is provided. Because the police timer value for each channel is inversely related to the channel bandwidth being authorized, the resulting request inhibit for the police timer value for each channel is short enough in duration to assure that, under normal (authorized bandwidth) operations, requests within the channel are seldom, if ever, inhibited. That is to say, so long as the channel bandwidth needed is within the authorized bandwidth, the channel down counter will normally count to zero, or time out, before the next request is presented. Thus, the bandwidth management system has no effect upon normally operating channels which remain within their authorized bandwidths. It is only during increased bandwidth demands such as those which occur during fast forward or transitory modes of operation which risk the presentation of access requests more rapidly than the police timer value number is down counted for the channel. As a result, the channel having increased bandwidth requirements suffers the consequences of such increased demands in the form of ungranted requests which accumulate within the channel buffer while the remaining channels remain fully operative. This is the overall objective of the bandwidth regulation system. An additional aspect of the present invention bandwidth regulation system is provided to further ensure that the total available bandwidth within the system is efficiently used. This additional aspect referred to as the "welfare system" provides a second mechanism by which access to the array controllers may be granted within a channel having increased bandwidth requirements despite an access inhibit as the down counter continues decrementing. Because bandwidth manager 22 tracks the total system bandwidth as well as current bandwidth use, it is able to determine whether additional unused system bandwidth is available. This additional available bandwidth is communicated to welfare task 45 which computes a global number indicative of the amount of available unused bandwidth. Thus, channels presenting access requests which cannot be placed directly into requestor 26 and are inhibited by the action of the police timer value are nonetheless able to receive additional allocated bandwidth using the welfare task within the bandwidth manager. This welfare system is carried forward by delay manager 46 and is in essence an "override" of the inhibiting action within requestor 26. The welfare system is described below in greater detail. Suffice it to note here that each channel having an inhibited request then attempts to obtain a request for access using the welfare system and, if successful, decrements the global number within global number register 44. More specifically, work station 23 provides an interface for user input which communicates with resource manager 21 to facilitate the user's ability to instance or begin new applications, adjust running applications, or terminate applications as the user needs. Basically, work station 23 is illustrative of virtually any user interface to the video server system. Resource manager 21 responds to work station 23 and the user inputs provided thereby to provide all bandwidth requests to bandwidth manager 22 necessary for ,each of the plurality of data channels required to run an application and obtain authorization for the respective bandwidths therein. As indicated by the dashed-line enclosure for array controller 16, bandwidth manager 22 is actually part of array controller 16 and is coupled to resource manager 21. Thus, it will be understood that array controllers 17 through 20 also include respective bandwidth managers. Bandwidth manager 21 responds to application requests and determines available transport bandwidth and disk bandwidth to make an initial determination as to whether the system is able to run a particular application. As mentioned above, if available bandwidth is sufficient, bandwidth manager 22 authorizes the application and allocates the respective bandwidths which are authorized for each of the data channels within the application. In addition, bandwidth manager 22 utilizes the allocated bandwidth for each channel and computes a police timer value for each channel. As mentioned above, the police timer value is determined by dividing the data segment size by the authorized bandwidth. As a practical matter, it is usually best to provide a small "cushion" in authorizing bandwidth and computing the corresponding police timer value. Bandwidth manager 22 then installs the police timer value computed for each data channel within down counters 42 and updates the available unused bandwidth within the system for communication to welfare task 45. Welfare task 45 computes a global number based upon the available unused bandwidth of array controller 16 which is then stored within global number register 44 for use by delay manager 46. In computing the global number, welfare task 45 subtracts the bandwidth presently used from the total bandwidth of array controller 16 to determine available unused bandwidth and divides the results by the data segment size processed within the system. In this manner, the global number tends to be an integer which indicates the available unused bandwidth within array controller 16. Delay manager 46 responds to bandwidth manager 22 in performing a plurality of tasks which are set forth in the flow diagrams of Figure 2 in greater detail. Basically, delay manager 46 operates to control the transfer of access requests presented to array controller 16 by either placing the request directly in requestor 26 which functions as a main queue for access to disk array manager 27 or, alternatively, to place access requests, if necessary, within the appropriate channel buffer of buffers 24. Delay manager 46 operates in the manner set forth below in Figure 2 in greater detail to decrement each channel down counter and to monitor the police timer value of each of down counters 42 for each data channel and to inhibit transfers of access requests from buffers 24 to requestor 26 until the respective police timer value has down counted within the channel down counter. Additionally, delay manager 46 administers the welfare task in response to the global number provided by global number register 44. In this operation, delay manager 46 uses a simple rotating priority among the data channels beginning a welfare cycle through the data channels starting at the next data channel following the last channel to have received a welfare access grant. Delay manager 46 then looks for waiting requests within buffers 24 of each channel and for each waiting access request found, moves the request to requestor 26 and decrements global number 44. This process continues until the global number has been decremented to zero. In its preferred form, delay manager 46 operates in a periodic cycle through the request granting process as shown in Figure 2 on a periodic basis. Requestor 26 is coupled by data channels 25 to channel buffers 24 and functions as a main queue in transferring access requests to disk array manager 27. In this function, requestor 26 is controlled by delay manager 46. Disk array manager 27 operates to transfer access requests and data to and from disk groups 29 through 34. In the preferred fabrication of the present invention, data is transferred between the respective disks within disk groups 29 through 34 in a fixed size segment format. As mentioned above, array controllers 17 through 20 are identical to array controller 16 and thus include respective bandwidth managers, welfare tasks, global number registers, delay managers and police timer value down counters. By way of further similarity, it will be understood that array controllers 17 through 20 operate in the identical fashion as that described for array controller 16. Further, disk groups 50 through 53 shown coupled to array controllers 17 through 20 should be understood to indicate pluralities of disk groups such as disk groups 29 through 34 shown for array controller 16. Figure 2 sets forth a diagram illustrative of the operation of the present invention bandwidth regulation system. In the operation of the present invention system shown in Figure 2, the system is initially activated and performs certain initialization functions at step 60 after which the system moves to step 61 and sets initial channel bandwidths. As mentioned above, data channels having predictable or known bandwidths such as time code or other similar information are given a preset bandwidth while the remaining channels not capable of such prediction are initially given a zero bandwidth. The system then awaits the implementation of an application at step 62 and once an application is launched moves to step 63 in which the required bandwidth for each data channel necessary to perform the application is requested. Thereafter, a determination is made at step 64 as to whether sufficient bandwidth is available. If bandwidth is not available, the application is denied. If, however, the bandwidth is available, the system authorizes the application at step 65 and each array controller within the system is operative to compute the police timer values for each data channel at step 66. Thus, from step 66 and following, it will be understood that each array controller within the system is simultaneously performing the sequence of operational steps which follow with respect to the data channels and disk memory groups within each array. Accordingly, at step 67, each police timer value is installed within the respective down counter for each data channel after which the application is run at step 68. Within each data channel of each array controller, the sequence of steps enumerated at steps 69 through 76 are carried forward as requests for access to the disk array are presented and are moved through the present invention bandwidth regulation system. Thus, as indicated by dashed-line boxes 77 and 78, it will be understood by those skilled in the art that the sequence of operations set forth in steps 69 through 76 are simultaneously occurring within the plurality of data channels in each array controller. Accordingly, at step 69, a request for access to the disk array is presented and an initial determination is made by the delay manager as to whether the request may be placed directly within the main queue of requestor 26 (seen in Figure 1). If such direct placement can be accomplished, the system moves through step 76 to step 73 to move the request to the main queue and set the channel down counter to the police timer value. After moving the request to the main queue, the request is moved to the disk array manager at step 74 and transferred to the appropriate disk memories. At step 75, the system completes the transfer request and returns to step 69 to process the next request for access. Within steps 72 and 73, the system operates in accordance with the cyclic periodic operation of delay manager 46 (seen in Figure 1) described above. This cyclic operation is set forth in the remainder of the diagram of Figure 2 at steps 90 through 106. It should be understood by those skilled in the art that within the main flow diagram shown in Figure 2, the repeated cycling of the delay manager operations within each channel is best understood as operation of the delay manager sequentially through each of the data channels within the array controller. This operation begins at step 90 in which the delay manager cycle is started. The delay manager operates in accordance with a periodic cycle and begins each cycle at the data channel following the data channel which last received a welfare access grant. This next channel is selected at step 91 and a determination is made at step 92 as to whether a request is waiting within the channel buffer. If no request is waiting, the system moves to step 100 and increments the channel after which a determination is made at step 101 as to whether all channels have been processed. If all channels have been processed, the system moves to a timer 102 which times out to initiate the start of the next delay manager cycle. If all channels have not been processed, the system returns to step 91 selecting the incremented channel and again determines whether there is a request waiting in that channels buffer. If a request is waiting, the system moves to step 93 and determines whether the police timer value has counted down to zero within the channel down counter. If a zero count has been achieved, the system moves to step 103 and moves the request to the main queue within requestor 26 (seen in Figure 1). Once the request has been moved to the main queue, the system resets the police timer value at step 104, increments the channel at step 105 and at step 106 determines whether all channels have been processed within the cycle. If all channels have been processed, the system returns to timer step 102 and awaits the initiation of the next delay manager cycle. If, however, all channels have not yet been processed within the cycle, the system returns to step 91 and again moves through steps 91, 92, 93 and for each channel having a zero police timer value, processes through steps 103 through 106. If, however, a determination is made for the channel at step 93 that the police timer value has not down counted to zero, the system moves to step 94 and decrements the police timer value. At step 95, following a determination that the channel having a request in buffer has not downcounted through its police timer interval, the delay manager then attempts to utilize the welfare task and make use of available unused bandwidth. At step 95, a determination is made as to whether the global number, indicative of unused bandwidth, is greater than zero. If the global number is not greater than zero, this indicates that unused bandwidth is not available and the system returns to step 100 incrementing the channel and moving through step 101 to either timer step 102 or step 91 selecting the next channel for processing. If, however, a global number greater than zero is available, the system then moves to step 96 in which the request is moved to the main queue of requestor 26 (seen in Figure 1) and at step 97, the police timer value of the channel is reset. Following police timer value reset, the global number is decremented at step 98 and a marker is set at the channel indicating the last welfare access grant as applied to this channel. The system then returns to step 100 and 102 incrementing the channel number and either completing the cycle and returning to timer 102 or selecting the next channel for processing at step 91. Thus, this delay manager cycle continues to sequence through each channel managing the access requests therein and, upon completion of a cycle through all channels, the delay manager then waits a predetermined period and initiates the next delay manager's cycle. What has been shown is a novel bandwidth regulation system in which priority is given to maintain the steady state or "normal" operations of a video server while managing and regulating available bandwidth to accommodate to the extent possible without disturbing steady state operations additional bandwidth demands imposed upon the various channels within the system. The bandwidth regulation system, in essence, operates to meet bandwidth demands within a given channel which exceed the previous authorized channel bandwidths. Channels which remain within their authorized bandwidth are not affected by the operation of the bandwidth manager. The welfare task within the system ensures that effective use of the available system bandwidth is made and provides the system with substantial flexibility to meet changing or transistory conditions. While particular embodiments of the invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from the invention in its broader aspects.

Claims: CLAIMS: 1. A bandwidth regulation system for use in a multichannel information system storing and/or retrieving data to and/or from a memory array, said bandwidth regulation system comprising: means for establishing a time interval for each channel; means for inhibiting access to said memory array for each channel during its time interval; and means for resetting said time interval of a channel following access to said memory array having been given within the channel. 2. The bandwidth regulation system as set forth in claim 1 wherein each of said channels defines an authorized bandwidth and wherein said time interval of each of said channels is inversely related to said channel bandwidth. 3. The bandwidth regulation system as set forth in claim 2 further including a main queue for accumulating requests for access to said memory array and a plurality of buffers each associated with one of said plurality of channels. 4. The bandwidth regulation system as set forth in claim 3 wherein said means for inhibiting includes transfer means, operative in response to the expiration of said time interval, for transferring a one of said accumulated requests for access from said buffer to said main queue. 5. The bandwidth regulation system as set forth in claim 4 wherein said transfer means includes means for attempting to first place an access request in a channel directly into said main queue and, if unable to do so, placing said access request within said one of said plurality of buffers associated with said channel. 6. The bandwidth regulation system as set forth in claim 5 further including welfare means having means for determining unused system bandwidth within said information system and means for allowing said transfer means to transfer an access request within a channel during said time interval so long as unused bandwidth is present. 7. For use in a multichannel information system storing and/or retrieving data to and/or from a memory array, a method of bandwidth regulation comprising the steps of: receiving access requests within said channels; attempting to place each of said access requests directly into a main queue; placing each access request not directly placed into said main queue in said attempting step into a channel buffer; timing an interval for each channel; transferring an access request from said channel buffer to said main queue after said interval; and restarting said timing interval of each channel when an access request is transferred to said main queue. 8. The method of claim 7 wherein each of said channels defines a bandwidth and wherein said multichannel information system defines a total bandwidth and wherein said timing step includes the step of: determining a timing interval for each channel inversely related to said bandwidth of said channel. 9. The method of claim 8 further including the steps of: determining unused bandwidth for said multichannel information system; and transferring an access request from said channel buffer to said main queue prior to the expiration of said interval in response to said determining step so long as unused bandwidth is determined. 10. The method of claim 9 wherein data is transferred within said multichannel information system in the form of data segments and wherein said step of determining unused bandwidth includes the steps of: dividing said unused bandwidth by the volume of said data segment to produce a number; and storing said number in a memory. 11. A bandwidth regulation system for use in an information system which stores and/or retrieves data, formatted into a plurality of data channels, to and/or from a memory in response to access requests, said bandwidth regulation system comprising: means for authorizing a channel bandwidth for each of said data channels; means for determining an interval for each data channel inversely related to each respective channel bandwidth; means for timing each interval for each data channel; means for restarting said means for timing within a data channel each time access to said memory is granted within the data channel; and means for inhibiting access to said memory within a data channel unless said means for timing has completed timing of that channel's interval. 12. The bandwidth regulation system as set forth in claim 11 wherein said information system includes a buffer for each of said data channels and a main queue for providing access to said memory and wherein said bandwidth regulation system further includes: means for determining available space within said main queue; and delay means operative in response to said determining step to either grant access requests within a data channel by direct placement of an access request into said main queue or, in the absence of space in said main queue, placing the access request in the one of said buffers within said data channel. 13. The bandwidth regulation system as set forth in claim 12 wherein said means for authorizing includes: means for determining unused bandwidth available in said information system; and means for providing a global number reflective of said unused available bandwidth. 14. The bandwidth regulation system as set forth in claim 13 wherein said delay means includes: welfare means responsive to said global number for transferring an access request from a buffer for a data channel prior to completion of the channel interval if said global number is greater than zero; means for decrementing said global number; means for causing said interval to be reset; and means for setting a welfare marker indicative of the one of said data channels having a request for access transferred by said welfare means. 15. The bandwidth regulation system as set forth in claim 14 wherein said delay means operates on a cycle through said data channels beginning at the next data channel after said welfare marker to attempt first to directly place an access request into said main queue, next to determine the timer interval status and lastly to operate said welfare means. 16. The bandwidth regulation system as set forth in claim 15 wherein said means for timing includes a down counter for each of said data channels and wherein said delay means includes means for providing a clock signal coupled to each of said down counters for decrementing the respective counts therein.

Inventors: HOEG JOSEPH E, HOEG, JOSEPH, E.
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1997
Main classification: G06F13
IPC codes: G06F3, G06F13, H04N7