LIGHT-INSENSITIVE RESISTOR FOR CURRENT-LIMITING OF FIELD EMISSION DISPLAYS

Abstract: A semiconductor device for use in field emission displays includes a substrate (30) formed from a semiconductor material, glass, soda lime, or plastic. A first layer of a conductive material (28) is formed on the substrate. A second resistive layer of microcrystalline silicon (32) is formed on the first layer. This layer has characteristics that do not fluctuate in response to conditions that vary during the operation of the field emission display, particularly the varying light intensity from the emitted electrons or from the ambient. One or more cold-cathode emitters (34) are formed on the second layer.

Description: Description LIGHT-INSENSmNE RESISTOR FOR CURRENT-LIMITING OF FIELD EMISSION DISPLAYS Cross-Reference To Related Application This application is a continuation-in-part of U.S. Patent Application Serial No. 08/543,435, filed October 16, 1995, now pending. Technical Field The present invention relates generally to field emission devices, and more particularly, to field emission displays having current-limiting resistors. Background of the Invention A typical field emission display 8 is shown in Figure 1. The display 8 includes a substrate or base plate 10 having a conductive layer 12 formed thereon. A plurality of emitters 14 are formed on the layer 12. Also formed on the layer 12 is an electrically insulating layer 16 having a conductive layer formed thereon. The conductive layer formed on the insulating layer 16 typically functions as an extraction grid 18 to control the emission of electrons from the emitters 14, and is typically formed from metal. An anode 20, which acts as a display screen and has a cathodoluminescent coating 22 formed on an inner surface thereof, is positioned a predetermined distance from the emitters 14. Typically, a vacuum exists between the emitters 14 and the anode 20. A power source 24 generates a voltage differential between the anode 20 and the substrate 10, which acts as a cathode. Also, a voltage applied to the extraction grid 18 generates an electric field between the grid and the substrate 10. An electrical path is provided to the emitters 14 via the conductive layer 12 such that in response to this electric field, the emitters 14 emit electrons. The emitted electrons strike the cathodoluminescent coating 22, which emit light to form a video image on the display screen. Examples of such field emission displays are disclosed in the following U.S. patents, all of which are incorporated by reference: Patent No. Issue Date 3,671,798 June 20, 1972 3,970,887 July 20, 1976 4,940,916 July 10, 1990 5,151,061 September 29, 1992 5,162,704 November 10, 1992 5,212.426 May 18, 1993 5,283,500 February 1, 1994 5.359.256 October 25. 1994 Field emission displays, such as the field emission display 8 of Figure 1, often suffer from technical difficulties relating to the control of the current flowing through the emitters 14. For example, due to the relatively small dimensions of the components involved, manufacturing defects are common in which an emitter 14 is shorted to the extraction grid 18. Because the voltage difference between the substrate 10 and the anode 20 is typically on the order of 1000 volts or more and a high electric field exists between tip 14 and substrate 10, the above defect can cause a current to flow through the emitter 14 that is sufficient to destroy not only the shorted emitter 14 itself, but other surrounding emitters 14 and circuitry as well. Thus, such a current draw will typically result in damage to, if not complete destruction of, the field emission display. Furthermore, if the current through the emitters 14 is unregulated, it is virtually impossible to control the emission levei of the emitters 14, and thus the brightness level of the field emission display 8. Efforts to solve the above limitations have focused on providing a resistance between the conductive layer 12 and the emitters 14 to limit the current flow through the emitters 14. An example of such a resistance is disclosed in U.S. Patent No. 4,940,916, which was previously incorporated by reference. One limitation to this scheme, however, is that the resistivity (which is the inverse of the conductivity) of the resistive layer often fluctuates in response to conditions that vary during the operation of the field emission display, particularly the varying light intensity resulting from the emitted electrons striking the cathodoluminescent coating 22 or from ambient light. Summary of the Invention According to one aspect of the present invention, a semiconductor structure is provided for use in a field emission display. The structure includes a substrate that may be formed from a semiconductor material. Corning glass, soda lime glass, plastic, or silicon dioxide. A first layer of a conductive material is formed on the substrate. A second layer of microcrystalline silicon is formed on the conductive layer. One or more cold-cathode emitters are formed on the second layer. The second layer forms a current-limiting resistance between the conductive layer and the emitters. In one aspect of the invention the second layer, while exposed to optical energy, exhibits a resistivity that differs less than approximately 10% from the resistivity of the second layer while it is unexposed to optical energy, or "in the dark." In further aspects of the invention, the second layer of microcrystalline silicon is doped with an impurity of either the p-type or the n- type. An advantage provided by one aspect of the present invention is a current-limiting resistor that has a resistivity that remains relatively stable while the resistor is exposed to varying light intensities. Brief Description of the Drawings Figure 1 is a cross-sectional view of a conventional field emission display. Figure 2 is a cross-sectional view of a field emission display according to one aspect of the present invention. Figure 3 is a schematic diagram of a portion of the field emission display of Figure 2. Figure 4 is a schematic diagram of a portion of a field emission display according to another aspect of d e invention. Figure 5 is a plot of the resistance of and current through a sample of undoped amorphous silicon while exposed to light. Figure 6 is a plot of the resistance of and current through the sample of undoped amorphous silicon while unexposed to light. Figure 7 is a plot of the resistance of and current through a sample of doped amorphous silicon while exposed to light. Figure 8 is a plot of the resistance of and current through the sample of doped amorphous silicon while unexposed to light. Figure 9 is a plot of the resistance of and current through a first sample of doped microcrystalline silicon while exposed to light. Figure 10 is a plot of the resistance of and current through the first sample of doped microcrystalline silicon while unexposed to light. Figure 11 is a plot of the resistance of and current through a second sample of undoped microcrystalline silicon while exposed to light. Figure 12 is a plot of the resistance of and current through the second sample of undoped microcrystalline silicon while unexposed to light. Figure 13 is a block diagram of a video receiver and display device that incorporates the present invention. Detailed Description of the Invention Figure 2 is a cross-sectional view of a portion of a cold-cathode field emission display 26 according to one aspect of the present invention. A conductive layer 28 is formed on a substrate 30. In one aspect of the invention, the conductive layer 28 is a metal layer, and the substrate 30 is formed from silicon. In other aspects of die invention, the substrate 30 may be formed in a conventional manner from a glass such as Corning 7059, from soda lime, or from a plastic. A resistive layer 32 is formed on the conductive layer 28. One or more cold-cathode emitters 34 are formed on the resistiv e layer 32. For clarity, only one emitter 34 is shown. An insulating layer 36 is also formed on the resistive layer 32, and cavities are formed in the insulating layer 36 to accommodate me emitters 34. A conductive extraction grid 38 is formed on the insulating layer 36. An anode 40, which acts as a display screen, is spaced a predetermined distance from the extraction grid 38 and has a cathodoluminescent coating 42 formed on an inner surface thereof. In one aspect of the invention, the resistive layer 32 has a level of resistivity which varies less than approximately 10% while exposed to fluctuating optical energy. Typically, the resistive layer 32 provides approximately 1 x IO 6 - 1 x 10 10 ohms (Ω) resistance between the conductive layer 28 and each emitter 34. This range of resistance limits the current passing through each emitter 34 to approximately 1 nanoamp (nA), and limits me total current drawn by the display 26 to approximately 0.1mA. In operation, when a voltage difference of approximately 1000 volts (V) is applied between the anode 40 and the substrate 30, and a voltage of approximately 100 N is applied to the extraction grid 38, electrons will flow from the conductive layer 28, through the resistive layer 32, and out from the tips of the emitters 34. The emitted electrons then strike the cathodoluminescent coating 42, which generates visible light or luminance. Some of this light may strike the resistive layer 32. However, in accordance with the invention, the resistivity of the resistive layer 32 will remain relatively stable even while exposed to varying intensities of light from the cathodoluminescent coating 42 or from other sources. Still referring to Figure 2, certain materials will provide the stable resistivity desired in the layer 32. In one aspect of the invention, the resistive layer 32 is formed from amorphous silicon mat is doped with phosphorous. For example, the layer 32 is typically doped with between approximately 1.0 and 10.0 parts per million (ppm) of phosphorous. Such a layer or film 32 may be formed by conventional semiconductor processes such as glow discharge, thermal, or other deposition processes. For example, the resistive layer 34 may be prepared by a conventional glow discharge using a silane to phosphine ratio of approximately 1% phosphine gas to provide the necessary phosphorus atoms for doping the layer 32. The resistive layer 32 may also be formed from amorphous silicon that is doped with boron, preferably between approximately 10 and 100 ppm of boron. Alternatively, the resistive layer 32 may be formed from amorphous silicon that is doped with nitrogen, preferably between approximately 10.0 and 100.0 ppm nitrogen. The layer 32 may also be formed from either doped or undoped microcrystalline silicon having a preferred grain size of approximately 100 Angstroms (A) and a preferred orientation of either 100, 1 10, or 11 1. The formation of such amorphous and microcrystalline silicon is further discussed in conjunction with Figures 5-12. When formed from one of the above-described materials, the resistive layer 32 exhibits resistivities that are typically in die range of 10 : - 10 6 Ω-cm. Furthermore, the resistivity of such a layer 32 fluctuates very little under various operating conditions of the field emission display 26. For example, the illumination conditions within die field emission display 26 may vary from dark, when the field emission display 26 is not being used, to light, when the cadiodoluminescent coating 42 is activated by the electrons emitted from the emitters 34. It is preferred that as me illumination conditions change from dark to light and vice versa, the resistivity of the layer 32 varies by less dian 10%. A layer 32 formed from one of ie above-described materials meets this criteria. Figure 3 is a schematic diagram of the portion of the field emission display 26 that is shown in Figure 2. In operation, electrons flow from die conductive layer 28, which in one aspect of the invention is a column electrode, to the resistor formed by the resistive layer 32. The electrons then flow from me resistive layer 32 to the emitter 34 and through the vacuum between the extraction grid 38 and the anode 40 until they strike me cathodoluminescent coating 42. Thus, even in the case of a short circuit between the emitter 34 and the extraction grid 38, the resistive layer 32 limits the flow of current, and thus the flow of electrons, through the circuit branch formed by the conductive layer 28, die resistive layer 32, and the emitter 34. Figure 4 is a schematic diagram of another embodiment of the portion of die field emission display 26 that is shown in Figure 2. A resistor representing the resistive layer 32 is coupled to the conductive layer 28, which here is coupled to ground. A column transistor 46 has its gate coupled to a column-select line, its substrate coupled to ground, and its source coupled to the resistive layer 32. A row select transistor 48 has its gate coupled to a row-select line, its substrate coupled to ground, its source coupled to the drain of the transistor 46, and its drain coupled to the emitter 34. In operation, when both the row and column that the emitter 34 occupies are selected, bod the row-select and the column-select lines are driven with active high row-select and column-select signals respectively, thus causing both transistors 46 and 48 to be activated or "turned on." The activated transistors 46 and 48 allow electrons to flow from the conductive layer 28, rough the resistive layer 32. the transistors 46 and 48, and the emitter 34, to the cathodoluminescent coating 42. The resistive layer 32 provides the current- limiting function, as discussed above in conjunction with Figure 3. Figure 5 is a plot showing die resistance of and die cu ent through a sample of undoped amorphous silicon while it is exposed to room lighting conditions. For example, with approximately 100 volts (V) applied across die sample, approximately 2.124 nanoamps (nA) of current flows therethrough, giving a resistance of 46.6 x IO 9 Ω. The resistivity p = Rwt/1. where R equals d e resistance of the sample, w is the width of the sample, t is die thickness of the sample, and 1 is the lengdi of the sample. For e sample of Figure 5, w/1 = 5 and t = 0.5 microns (μm). Thus, the resistivity of the sample while exposed to room lighting, i.e., the light resistivity p L , is approximately 1.1 x IO 7 Ω-cm. Figure 6 is a plot showing the resistance of and die current through the same sample of undoped amorphous silicon while it is unexposed to light, i.e., while in the dark. For example, with 100 N applied across the sample, 49.65 pA of current flows dierethrough, giving a resistance of approximately 2.01 x IO 12 Ω. Thus, the resistivity of the sample while in the dark, i.e., the dark resistivity p D , is approximately 5.02 x 10 8 Ω-cm. As shown, the difference between p L and p D of the sample of undoped amorphous silicon spans approximately a factor of 50, i.e., 5000%. Such a span often renders undoped amorphous silicon an unacceptable material for the resistive layer 32 of Figure 2. The sample of amorphous silicon whose characteristics are plotted in Figures 5 and 6 was formed from SiH 4 at a flow rate of approximately 800 standard cubic centimeters per minute (SCCM), at a temperature of approximately 300°C, a pressure of approximately 1000 milliTor (mT), and a power of approximately 500 Watts (W) for a time of approximately 5 minutes. Figure 7 is a plot showing the resistance of and the current through a sample of boron-doped amorphous silicon while it is exposed to room lighting conditions. For example, with approximately 100 N applied across the sample, a current of approximately 116.8 nA flows therethrough, giving a resistance of approximately 847 x 10° Ω. For this sample, wU = 5 and t = 0.5 μm. Thus, p L is approximately 2.1 xl0 J Ω-cm. Figure 8 is a plot showing the resistance of and the current through the same sample while it is in the dark. For example, with approximately 100 N applied across the sample, a current of approximately 108.4 nA flows merefhrough, giving a resistance of approximately 913 x 10 6 Ω. Thus, p D is approximately 2.3 xlO^ Ω-cm. Referring to Figures 7 and 8, unlike the light and dark resistivities of me sample of undoped amorphous silicon, p D and p L for the sample of boron- doped amorphous silicon differ by merely 8%-10%. Thus, the doping with boron of the amorphous silicon significantly improves the stability of its resistivity with respect to variations in illumination. Furthermore, the doping of the amorphous silicon reduces the overall resistivity of the sample. Thus, boron-doped amorphous silicon is a suitable material for the resistive layer 32 of Figure 2. The sample of boron-doped amorphous silicon, whose characteristics are plotted in Figures 7 and 8, was formed from SiH 4 at a flow rate of approximately 500 SCCM, a temperature of approximately 300°C, a power of approximately 500 W, and a pressure of approximately 1000 mT for a time of approximately 5 minutes. The formed sample has a boron concentration of approximately 10 ppm. An improvement in the stability of the resistivity of amorphous silicon may also be made by doping the amorphous silicon with phosphorous, arsenic, or ammonia. Like the boron doping discussed above, such doping reduces both the resistivity of d e amorphous silicon and the resistivity's sensitivity to light. Thus, by selecting the proper dopant and doping concentration, one can adjust the resistivity and its light sensitivity to the desired levels. It is also important to note, however, that excessive concentrations of dopant (beyond approximately 10% for boron. 1% for phosphorous. 1% for arsenic, and 10% for ammonia) mav act ailv increase both the resistivitv of the amorphous silicon and me light sensitivity of d e resistivity. Figure 9 is a plot showing the resistance of and the current through a sample of boron-doped microcrystalline silicon while exposed to room light. For example, with approximately 100 V applied across the sample, a current of approximately 2.09 microamps (μA) flows therethrough, giving a resistance of approximately 47.7 x IO 6 Ω. For this sample, w\l = 5 and t = 0.5 μm. Thus, p L is approximately 1.2 x IO 4 Ω-cm. Figure 10 is a plot showing the resistance of and the current through d e sample while in the dark. For example, with approximately 100 N applied across the sample, a current of approximately 1.919 μA flows therethrough, giving a resistance of approximately 52.1 x 10 6 Ω. Thus, p D is approximately 1.3 x 10 4 Ω-cm. Figure 11 is a plot of die resistance of and the current through a sample of undoped microcrystalline silicon while exposed to room light. For example, with approximately 100 N applied across the second sample, a current of approximately 43.16 nA flows therethrough, giving a resistance of approximately 2.32 xlO 9 Ω. For mis sample, w\l = 5 and t = 0.5 μm. Thus, p L is approximately 5.8 x IO 5 Ω-cm. Figure 12 is a plot of d e resistance of and the current through the sample while in the dark. For example, with approximately 100 V applied across the sample, a current of approximately 39.5 nA flows theredirough, giving a resistance of 2.53 x IO 9 Ω. Thus, p D is approximately 6.3 x IO 5 Ω-cm. Referring to Figures 9 and 10, the p L and p D of the boron-doped microcrystalline sample respectively differ by approximately 8%-10%. Referring to Figures 11 and 12, the p L and p D of the undoped microcrystalline sample also differ by approximately 8%-10%. Thus, one can see that the resistivity of microcrystalline silicon, whether doped or undoped, exhibits excellent insensitivity to light. That is, the resistivity of microcrystalline silicon is essentially insensitive to variations in illumination. The sample of boron-doped microcrystalline silicon, the characteristics of which are plotted in Figures 9 and 10, was formed from SiH 4 at a flow rate of approximately 10Θ SCCM, H 2 at a flow rate of approximately 3000 SCCM, B 2 H 6 at a flow rate of approximately 10 SCCM, at a temperature of approximately 300°C, a power of approximately 700 W, and a pressure of approximately 1000 mT for a time of approximately 40 minutes. The formed sample has a boron concentration of approximately 1 ppm. The sample of undoped microcrystalline silicon, whose characteristics are plotted in Figures 11 and 12, was formed from SiH 4 at a flow rate of approximately 100 SCCM, H 2 at a flow rate of approximately 3000 SCCM, at a temperature of approximately 300°C, a power of approximately 1500 W, and a pressure of approximately 850 mT for a time of approximately 40 minutes. N-type microcrystalline silicon may be formed by adding to the above chemistry phosphine or arsine flowing at up to 1% of the amount of the saline, i.e., 1 SCCM. The more dopant added to the microcrystalline silicon, the lower the resistivity of die sample. Unlike amorphous silicon, dopants have little effect on the light stability of the resistivity of the microcrystalline silicon. That is, die excellent light stability of the resistivity is due to the microcrystalline silicon itself, and the dopants merely adjust the desired value of the resistivity. As stated above with regard to amorphous silicon, dopants in excess of the amounts specified may increase the resistivity of microcrystalline silicon and degrade the light stability of the microcrystalline silicon's resistivity. Figure 13 is a block diagram of a video receiver and display device 50 that incorporates the present invention. The circuit device 50 includes a conventional tuner 52, which receives one or more broadcast video signals from a conventional signal source such as an antenna 54. An operator (not shown) programs, or otherwise controls, the tuner 52 to select one of these broadcast signals and to output the selected broadcast signal as a video signal. The tuner 52 may generate the video signal at the same carrier frequency as the selected broadcast signal, at a base band frequency, or at an intermediate frequency, depending upon the design of the device 50. The tuner 52 couples the video signal to a conventional video processor 56 and to a conventional sound processor 58. The sound processor 58 decodes die sound component of the video signal and provides this sound signal to a speaker 60, which converts the sound signal into audible tones. The video processor 56 decodes, or o herwise processes, the video component of the video signal, and generates a display signal from this video component. The video processor 56 may generate the display signal as either a digital or an analog signal, depending upon the design of die device 50. The video processor 56 couples the display signal to d e FED 26 (Figure 2), which converts me display signal into a visible video image. In one aspect of the invention, me sound processor 58 and the speaker 60 are omitted such that the device 50 provides only a video image. Furthermore, although shown coupled to the antenna 54, d e tuner 52 may receive broadcast signals from other conventional sources, such as a cable system, a satellite system, or a video cassette recorder (NCR). Alternatively, the tuner 52 may receive a non-broadcast video signal, such as from a closed circuit video system (not shown). In such a case where only one video signal is input to the circuit 50, die tuner 52 may be omitted and the video signal may be directly coupled to the inputs of the video processor 56 and the sound processor 58. It will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without departing from d e spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

Claims: Claims 1. A semiconductor device, comprising: a substrate; a first layer of a conductive material formed on said substrate; a second layer of microcrystalline silicon formed on said first layer; and one or more cold-cathode emitters formed on said second layer. 2. The device of claim 1 wherein said second laver includes an impurity. 3. The device of claim 1 wherein said second layer is P-type. 4. The device of claim 1 wherein said second layer is N-type. 5. The device of claim 1 wherein said second layer exhibits a light resistivity while exposed to optical energy, and exhibits a dark resistivity while substantially unexposed to optical energy, said light resistivity differing from said dark resistivity by less than approximately 10%. 6. A field emission display, comprising: a substrate; a first layer of conductive material formed on said substrate; a second layer of microcrystalline silicon formed on said first layer; a plurality of cold-cathode emitters formed on said second layer; a grid spaced a first predetermined distance from said emitters and having a plurality of openings that are each aligned with one of said emitters; a display screen that is spaced a second predetermined distance from said grid and that has an inner surface facing said grid; and a cathodoluminescent material mat is formed on said inner surface. 7. The field emission display of claim 6 wherein said second layer is doped with between approximately 10 ppm and about 100 ppm boron. 8. The field emission display of claim 6 wherein said second layer is doped with between approximately 1 ppm and approximately 10 ppm phosphorous. 9. The field emission display of claim 6 wherein said second layer is doped with between approximately 1 ppm and approximately 10 ppm arsenic. 10. The field emission display of claim 6 wherein said emitters are arransed in rows and columns. 11. The field emission display of claim 6 wherein said second layer exhibits a first conductivity while exposed to optical energy, and exhibits a second conductivity while substantially unexposed to optical energy, said first conductivity varying from said second conductivity by less than approximately 10%. 12. The field emission display of claim 6 wherein said substrate comprises glass. 13. The field emission display of claim 6 wherein said substrate comprises soda lime glass. 14. The field emission display of claim 6 wherein said substrate comprises plastic. 15. A metiiod for forming a semiconductor structure, comprising: forming on a substrate a conductive layer; forming on said conductive layer a resistive layer of microcrystalline silicon; and forming on said resistive layer at least one cold-cathode emitter. 16. The method of claim 15, furtiier comprising doping said resistive layer with an impurity. 17. The method of claim 15, further comprising doping said resistive layer witii a P-type impurity. 18. The method of claim 15, further comprising doping said resistive layer with an N-type impurity. 19. An apparatus for displaying a video image, comprising: a video processing circuit mat is operable to receive a video signal and to generate a display signal from said video signal; a field emission display operable to receive said display signal and to generate said video image from said display signal, said field emission display including, a substrate, a conductive layer formed on said substrate, a resistive layer of microcrystalline silicon formed on said conductive layer, a plurality of cold-cathode emitters formed on said resistive layer, a grid spaced a first predetermined distance from said emitters and having a plurality of openings that are each aligned with at least one of said emitters, a display screen tf at is spaced a second predetermined distance from said grid and that has an inner surface facing said grid, and a cathodoluminescent material that is formed on said inner surface. 20. The apparatus of claim 19, further comprising a tuner operable to receive a plurality of broadcast signals, select one of said broadcast signals, and provide said selected broadcast signal as said video signal. 21. The apparatus of claim 19 wherein said resistive layer includes an impurity. 22. The apparatus of claim 19 wherein said resistive layer exhibits a light conductivity while exposed to optical energy, and exhibits a dark conductivity while substantially unexposed to said optical energy, said light conductivity differing from said dark conductivity by less than approximately 10%.

Inventors: ALWAN JAMES J, CATHEY DAVID A JR, LEE JOHN K, MORADI BEHNAM, TJADEN KEVIN W, ALWAN, JAMES, J., CATHEY, DAVID, A., JR., LEE, JOHN, K., MORADI, BEHNAM, TJADEN, KEVIN, W.
Applicants: MICRON DISPLAY TECH INC, MICRON DISPLAY TECHNOLOGY, INC.
Application year: 1997
Main classification: H01J1
IPC codes: H01J1, H01J9, H01J29, H01J31