Semiconductor memory device

Abstract: The present invention relates to a semiconductor memory device having a memory cell array of a split-operation mode. The semiconductor memory device comprises a semiconductor ship having first to fourth sides, a first interconnection (56,57) disposed along a first side of the semiconductor chip and supplied with a source potential level (Vdd) or a ground potential level (Gnd), a second interconnection (58,59) disposed along a second side opposed to the first side and supplied with the source potential level (Vdd) or the ground potential level (Gnd), and a plurality of sub-array regions (50-54) disposed between the first interconnection (56,57) and the second interconnection (58,59). A plurality of memory cells and a plurality of sense amplifiers respectively connected to the memory cells are disposed in each of the sub-array regions. The memory cells and the sense amplifiers disposed in one of the sub-array regions (50-54) are activated in response to the potential level supplied to the first interconnection (56,57). The memory cells and the sense amplifiers disposed in another one of the sub-array regions (50-54) are activated substantially simultaneously with the memory cells and the sense amplifiers disposed in the above one of the sub-array regions in response to the potential level supplied to the second interconnection (58,59).

Description: This invention relates to a semiconductor memory device, and particularly to a dynamic random access memory (DRAM) having a memory cell array of a split-operation mode. Description of the Related Art: The following example has heretofore been known as a technique employed in such a field. Fig. 3 is a view showing the configuration of a conventional semiconductor memory device of a block-splitting mode. Fig. 4 is an enlarged view of an A portion shown in Fig. 3. Fig. 5 is a view illustrating a sense amplifier train of the conventional semiconductor memory device shown in Fig. 3. In general, a large-capacity DRAM has a memory array provided so as to be divided into four sub-array regions by X decoders and Y decoders. Sub-array regions 10 and 11 are disposed on the upper half side of a chip, whereas sub-array regions 12 and 13 are disposed on the lower half side of the chip. X decoders are respectively disposed within regions 14 defined between the two. The sub-array regions 10 and 13 are disposed on the left half side of the chip and the sub-array regions 11 and 12 are disposed on the right half side of the chip. Y decoders are respectively disposed within regions 15 defined between the two. Each of the sub-array regions comprises a plurality of cell array regions 23. A plurality of memory cells, a plurality of bit line pairs 26 and a plurality of word lines are disposed within each of the cell array regions 23. As shown in Fig. 5, sense amplifier trains 24 each composed of a plurality of sense amplifier circuits 21 and a sense latch circuit 22 are respectively provided on both sides of the respective cell array regions 23 of the sub-array regions as seen in the left and right directions. Incidentally, each sense latch circuit 22 has an NMOS transistor 22A and a PMOS transistor 22B. The gates of both transistors are respectively controlled by sense latch signals 25 each having a positive phase and an opposite phase. Source wires or interconnections 16, 17, 18 and 19 respectively electrically connected to the plurality of sense amplifier trains 24 are disposed so as to surround the sub-array regions. The source interconnections 16 and 17 are principally used for the plurality of sense amplifier trains 24 in the sub-array regions 10 and 11 provided on the upper half side of the chip, whereas the source interconnections 18 and 19 are principally used for the plurality of sense amplifier trains 24 in the sub-array regions 12 and 13 provided on the lower half side of the chip. When the four sub-array regions 10, 11, 12 and 13 are divisionally operated, the sub-array regions 10 and 11 on the upper half side have heretofore been activated simultaneously as blocks A and the sub-array regions 12 and 13 on the lower half side have heretofore been activated simultaneously as blocks B in timing different from that for the blocks A. In the way of such block division or splitting, however, circuits used as noise sources have been biased toward upper or lower power sources. Namely, when each block A is activated (i.e., when memory cells in the block A are selected), a plurality of cell arrays of each of the sub-array regions 10 and 11 are simultaneously activated (selected) and the sense amplifier trains 24 on both sides thereof are also activated (a sense latch operation is performed). When the PMOS transistor 22B and the NMOS transistor 22A are turned on so that a source interconnection supplied with a power source potential Vdd (e.g., 5V) and its corresponding sense amplifiers SA are electrically connected to one another and a source interconnection supplied with a ground potential Gnd (e.g., 0V) and its corresponding sense amplifiers SA are electrically connected to one another, each sense amplifier train 24 is activated as shown in Fig. 6. When each sense amplifiers SA is activated, electric charges are charged or discharged between the source interconnections and each sense amplifier SA to amplify information stored in each memory cell, which has been transferred to each bit line pair 26 (the arrows show the manner of charge or discharge). However, since the plurality of activated sense amplifier trains 24 are biased toward the source interconnections 16 and 17 as shown in Fig. 7, high noise occurs in the source interconnections 16 and 17 (since the blocks B are not activated on the other hand, no noise is produced in the source interconnections 18 and 19). The speed of amplifying information by each sense amplifier SA becomes slow under the influence of the noise and the semiconductor memory device will eventually lead to a slow operating speed. Therefore, there has been a demand for the improvement in the operating speed of the semiconductor memory device. Another memory device is known from US-A-5321646 which describes a semiconductor chip having four interconnections placed evenly spaced perpendicular to bit lines on the chip. A further memory device is known from US-A-5406526. In this device always one of the sense amplifier circuit arrays is activated. With the foregoing in view, it is an object of the present invention to disperse sense amplifiers and memory cells to be activated. It is another object of the present invention to disperse or reduce noise produced in interconnections each supplied with a source potential level or a ground potential level. It is a further object of the present invention to improve an operating speed of a sense amplifier. It is a still further object of the present invention to provide a semiconductor memory device capable of providing an improvement in access speed. According to one aspect of the present invention, for achieving the above objects, there is provided a semiconductor memory device comprising: a semiconductor chip having a first side, a third side and a fourth side both adjacent to the first side, and a second side opposed to the first side; at least one interconnection extending from a substantially middle point of the third side to a substantially middle point of the fourth side and supplied with a source potential level or a ground potential level; a plurality of sub-array regions, each including a plurality of memory cells and a plurality of sense amplifiers respectively connected to said memory cells and said sense amplifiers being disposed in each of said sub-array regions comprising: first and second sub-array regions disposed along the first side, and third and fourth sub-array regions disposed along the second side; and wherein said sense amplifiers disposed in said first and second sub-array regions are activated substantially simultaneously in response to the potential level supplied to said interconnection, and said sense amplifiers disposed in said third and fourth sub-array regions are activated substantially simultaneously in response to the potential level supplied to said interconnection. While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which: Fig. 1 is a view illustrating a semiconductor memory device according to an embodiment of the present invention; and Fig. 2 is a view depicting the semiconductor memory device shown in Fig. 1. Fig. 3 is a view showing a conventional semiconductor memory device; Fig. 4 is an enlarged view of an A portion shown in Fig. 3; Fig. 5 is a view showing a sense amplifier train of the semiconductor memory device shown in Fig. 3; Fig. 6 is a view for describing current channels at the time of the operation of the semiconductor memory device shown in Fig. 3; Fig. 7 is a view for describing noise produced in source interconnections at the time of the operation of the semiconductor memory device shown in Fig. 3. A preferred embodiment of the present invention will hereinafter be described in detail with reference to the accompanying drawings. Fig. 1 is a view typically showing a block-splitting mode of a semiconductor memory device illustrative of the embodiment of the present invention. The embodiment is similar in basic configuration to the prior art. In the present embodiment, however, the source interconnections, which have been disposed along the peripheral edges of the respective sub-array regions, are eliminated and combined into one (with the width between the interconnections defined as twice the above width). Namely, they are disposed within a region 101 defined between the upper sub-array regions and the lower sub-array regions. The source interconnections are shared between the sub-array regions on the upper and lower sides. The present embodiment is identical in basic operation to the prior art. However, since the source interconnections 102 and 103 are placed within the region 101 alone, electric charges are charged or discharged as shown in Fig. 2. Since the noise sources are biased toward the upper or lower power sources in the conventional circuit, the power sources lying on the opposite side thereof were not used. According to the fourth embodiment, the integration of the upper and lower source interconnections into one and the placement of them in the region 101 will allow the source interconnections to be efficiently used without a change in chip size. It is thus possible to obtain the effect of reducing noise. Incidentally, the present invention is not necessarily limited to the above-described embodiments. It is needless to say that various changes and modifications can be made and will not be excluded from the scope of the present invention as defined by the appended claims. According to the present invention as has been described in detail above, the following advantageous effects can be brought about. (1) Since simultaneously-activated sub-array regions are divided into blocks in grid form, noise sources are prevented from biasing. Further, since the sub-array regions are dispersed over the entire chip, source interconnections can be efficiently used. Thus, noise can be effectively reduced and uniform power consumption can be achieved. Further, the speed of amplifying information by each sense amplifier can be rendered higher than ever. (2) By making only a change in layout of source interconnections without a change in circuit or circuit configuration, noise sources can be dispersed so as to reduce power source noise. Thus, the speed of amplifying information by each sense amplifier can be rendered faster than ever and access times to a chip can be eventually faster. (3) By integrating upper and lower source interconnections into one and disposing it in a predetermined region, the source interconnections can be efficiently used without a change in chip size, thus producing a noise-reduction effect. While the present invention has been described with reference to the illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiment, will be apparent to those skilled in the art on reference to this description.

Claims: A semiconductor memory device comprising:- a semiconductor chip having a first side, a third side and a fourth side both adjacent to the first side, and a second side opposed to the first side; at least one interconnection extending from a substantially middle point of the third side to a substantially middle point of the fourth side and supplied with a source potential level or a ground potential level; a plurality of sub-array regions, each including a plurality of memory cells and a plurality of sense amplifiers (60) respectively connected to said memory cells and said sense amplifiers being disposed in each of said sub-array regions comprising:- first and second sub-array regions disposed along the first side, and third and fourth sub-array regions disposed along the second side; and wherein said sense amplifiers (60) disposed in said first and second sub-array regions are activated substantially simultaneously in response to the potential level supplied to said interconnection, and said sense amplifiers (60) disposed in said third and fourth sub-array regions are activated substantially simultaneously in response to the potential level supplied to said interconnection. A semiconductor memory device as claimed in claim 1 wherein said sense amplifiers disposed in said first and second sub-array regions are activated during a first time and said sense amplifiers disposed in said third and fourth sub-array regions are activated in response to the potential level supplied to said interconnection during a second time.

Inventors: KAI YASUKAZU, KAI, YASUKAZU, Kai, Yasukazu, c/o Oki Micro Design Co. Ltd.,
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1997
Main classification: G11C5
IPC codes: G11C5, G11C7, G11C8