A low power RAM memory cell

Abstract: The invention relates to a RAM memory cell (10) for a memory matrix comprising a plurality of word-lines (WL) and bit-lines (BL), said cell (10) including a first and a second cross-coupled CMOS inverters (12, 13), each including a PMOS pull-up transistor (M3, M4) and an NMOS pull-down transistor (M1, M2), and first and second access transistors (M5, M6) connecting the second (13) and the first inverter (12) to a corresponding bit line respectively, characterized in that the source terminals of the pull-down transistors (M1, M2) are connected to a precharge line (PL) running parallel to each word line. Moreover, the first and second access transistors (M5. M6) are PMOS transistors having their gate terminals connected to the word line (WL).

Description: Background of the invention The present invention relates to a low power RAM memory cell for a memory matrix comprising a plurality of word-lines and bit-lines, said cell including a first and a second cross-coupled CMOS inverters each including a PMOS pull-up transistor and an NMOS pull-down transistor, and first and second access transistors connecting the second and the first inverter to a corresponding bit line respectively. The invention relates to integrated memory circuits and more specifically, but not exclusively, to integrated static random access memories. As is well known, an electronic random access memory device includes a plurality of basic memory cells each comprising six transistors. The enclosed figure 1 shows an example of a basic six transistors memory cell which is realized by CMOS technology. The cell 1 shown in figure 1 includes a pair of cross-coupled CMOS inverters 2 and 3 each of which is coupled to a corresponding bit line 4, 5 of the memory device. The first inverter 2 is coupled to the bit line 4 through a bi-directional access devices 6 while the second inverter 3 is coupled to the adjacent bit line 5 through a second bi-directional access devices 7. During the reading and writing phases of the memory cell, a differential voltage must be applied between the bit lines 4, 5. In this respect, we might consider the cell access to the storage node as "differential". In the reading phase, the bit line swing amplitude depends on how long the cells have been activated. The voltage difference due to the swing can be kept quite small and can be sensed by the sense amplifier of the memory device. This helps to reduce power consumption. In the writing phase, the bit line voltage swing should be as large as possible, even a full CMOS level, in order to toggle the cells. If we consider a RAM memory array or matrix having m rows and n columns, and including six transistors cells, the current consumption can be easily estimated using the following formulas: Iddr = n * m * Cb * ΔVr for the reading phase, and Iddw = n * m * Cb * ΔVw for the writing phase; where: Cb is the bit line capacitance associated to a given cell; ΔVr is the read voltage bit line swing and ΔVw is the write voltage bit line swing. Usually ΔVw corresponds to the supply voltage value Vdd. Some prior art techniques are used to reduce the power dissipation of the memory matrix. For instance, a first prior art solution is disclosed in: N. Kushiyama et al. "A 295 Mhz CMOS 1M (x256) embedded SRAM using I-directional read/write shared sense amplifiers and self-timed pulsed word-line drivers", ISSCC Dig. Tech. Papers Feb. 1995, pp. 182-183. This solution proposes to reduce power dissipation by reducing the number of cells hung on the bit line using a hierarchical bit line scheme. A second prior art solution is disclosed in: B. Amrutur and H. Horowitz "Technique to reduce power in fast wide memories" Dig. Tech. Papers, Oct. 1994, Symp. on Low Power Electronics, pp 92-93. This second solution proposes to reduce power dissipation limiting the read bit line swing by controlling the word line pulse length. A third prior art solution is disclosed in: T. Blalock and R. Jager " A high-speed clamped bit line current-mode sense amplifiers" IEEE J. Solid State Circuits, vol. 26, No. 4, pp. 542-548, April 1991. Even this solution proposes to reduce power dissipation limiting the read bit line swing, but using current-mode sense amplifiers. A further known solution proposes to limit the write bit line swing to a predetermined value, namely Vdd-Vt, using a NMOS transistors precharge phase. One object of the present invention is that of providing a SRAM memory device having a reduced power consumption. Another object of the present invention is that of achieving a reduction in the power dissipation of memory devices having very long wordlenght. A further object of the present invention is that of providing a technique to reduce voltage swing on the memory array bit lines during the writing phase. A further object of the present invention is that of providing an SRAM memory cell which doesn't require special techniques to be written. Summary of the invention The solution idea behind this invention is that of precharging the source terminals of the pull-down transistors forming the inverters pair inside the cell. As an alternative, it would be possible to precharge the source terminals of the pull-up transistors forming the inverters pair inside the cell. According to this solution idea, the technical problem is solved by a RAM memory cell according to the claims 1 or 5. The features and advantages of the RAM memory cell according to the invention will be appreciated by the following description of a preferred embodiment given by way of non-limiting example with reference to the annexed drawings. Brief description of the drawings Figure 1 shows a simplified schematic diagram of a conventional and known CMOS SRAM memory cell; Figure 2 shows a simplified schematic diagram of a CMOS RAM memory cell according to the present invention; Figure 3 shows a schematic diagram of a memory array including a plurality of the memory cells of figure 2; Figure 4 shows a schematic timing diagram of the electric signals inside the memory cell of figure 2 during a write operation; Figure 5 shows a simplified schematic diagram of a second embodiment of the RAM memory cell according to the present invention; Figure 6 shows a simplified schematic diagram of a third embodiment of the RAM memory cell according to the present invention; Figure 7 shows a simplified schematic diagram of a fourth embodiment of the RAM memory cell according to the present invention; Figure 8 shows a 'further schematic diagram of a dual port embodiment of the RAM memory cell according to the present invention. Detailed description With reference to the above figures, a static random access memory cell according to the present invention is globally indicated with 10. The cell 10 is realized by a CMOS process. The SRAM cell according to the present invention is specifically designed for a random access electronic memory device having a six transistors cell. Each cell 10 is integrated in a memory array or matrix (partially shown in figure 3) including a plurality m of memory rows and a plurality n of memory columns. The memory rows are identified as word lines WL of the memory device, while the memory columns are the bit lines BL of the memory device. Each cell 10 may be identified at the intersection between a word line WL and a couple of two adjacent bit lines BL and BLB. The memory cell 10 comprises a couple of CMOS inverters 12 and 13 each including a pull-up PMOS transistor and a pull-down NMOS transistor. The two inverters 12, 13 are cross-coupled since the interconnection node between two transistors of one inverter is connected to the driving terminals of the other inverter. The first inverter 12 comprises a PMOS transistor M3 and an NMOS transistor M1. The second inverter 13 comprises a PMOS transistor M4 and an NMOS transistor M2. The transistors M1 and M3 of the first inverter 12 have their corresponding gate terminals connected to a first circuit internal node N1 which is connected to the drain common terminals of the other inverter 13. The transistors M2 and M4 of the second inverter 13 have their corresponding gate terminals connected to a second circuit internal node N2 which is connected to the drain common terminals of the other inverter 12. The source terminals of the PMOS transistors M3, M4 of the first and second inverters 12, 13 are both connected to a voltage supply line Vdd. According to the present invention, the source terminals of the NMOS transistors M1, M2 of the first and second inverters 12, 13 are both connected to a precharge line PL. This precharge line PL is an extra line which is common to all the cells 10 of a word line. Therefore, according to the present invention the source of the driver transistors M1, M2 , instead of being grounded, are connected to the external precharge line PL. According to a further aspect of the present invention, the second circuit node N2 is connected to the bit line BL through an access PMOS transistor M5. This PMOS transistor M5 has the conduction terminals connected between the circuit node N2 and the corresponding bit line and the gate terminal connected to the word line WL. Accordingly, the first circuit node N1 is connected to the bit line BLB through an access PMOS transistor M6. Even this PMOS transistor M6 has the conduction terminals connected between the circuit node N1 and the adjacent bit line and the gate terminal connected to the word line WL. Figure 3 shows a schematic diagram of the inside structure of the memory matrix including the plurality of cells 10 according to the present invention. When the cell is not accessed, and during the reading phase, the precharge line PL is tied to ground. So, read operation is performed in the conventional manner. The choice of using the PMOS access transistors M5, M6 doesn't effect the data transfer from the memory cell into the bit line. Let's now consider the writing phase of the memory device. The write operation is performed in three steps or phases: 1) a pulse is applied to the precharge line PL. This pulse resets the internal nodes N1 and N2 of the cells 10 of an addressed word line. The node which had been at a low logic value is now brought to the voltage level Vdd - Vtn by either the NMOS driver transistors M1 or M2.The current path to ground is broken. 2) A small voltage difference is applied on to the bit lines BL and BLB. The smaller the voltage difference, the more power is saved. 3) The word line WL is asserted, that is: a negative pulse is due to the PMOS access transistors M5, M6. Since no current path to ground is available, the bit lines can easily pass a small voltage difference onto the internal nodes N1, N2. The PMOS access transistors M5 and M6 allow the transfer of a small voltage difference having a value centered around the supply voltage Vdd. On the contrary, prior art solutions including NMOS access transistors provide a voltage difference between the bit lines which is larger than the threshold voltage of a NMOS transistor. 4) The precharge line PL is disabled and the memory cell 10 now acts as a latch-type sense amplifier. As the potential on the precharge line PL moves back toward zero volts, the symmetric nodes N1 and N2 become unstable and latch in direction of the small voltage difference which appears on them. 5) The word line WL goes to an inactive high logic state. This disconnects the memory cell from the outside world and is the end of the write operation. Figure 4 reports the timing diagrams of the whole write operation. These diagrams relate to the programming or write phase of a couple of memory cells. A second embodiment of the RAM memory cell according to the present invention is shown in the simplified schematic diagram of figure 5. As may be appreciated, in this specific embodiment the access transistors M5 and M6 are NMOS transistors. This means that the provision of PMOS transistors as access transistors is an advantage but not an essential feature of the present invention. According to this second embodiment the bit lines are precharged low between each operation of the memory cell, while the internal nodes N1 and N2 are precharged high before a write operation. Figure 6 shows a simplified schematic diagram of a third embodiment of the RAM memory cell according to the present invention. In this third embodiment the source terminals of the pull-up transistors M3 and M4 are connected to the precharge line PL running parallel to each word line. The source terminals of the pull-down transistors M1 and M2 are connected to the ground voltage reference. According to this third embodiment the bit lines are precharged low between each operation of the memory cell, while the internal nodes N1 and N2 are precharged low before a write operation. Figure 7 shows a simplified schematic diagram of a fourth embodiment of the RAM memory cell according to the present invention. The structure of the memory cell according to this fourth embodiment corresponds substantially to the previous example of figure 6, but with the provision of PMOS transistors as access transistors. So, the source terminals of the pull-up transistors M3 and M4 are connected to the precharge line PL and, as in the first embodiment, the PMOS transistor M5 has the conduction terminals connected between the circuit node N2 and the corresponding bit line and the gate terminal connected to the word line WL. The other PMOS access transistor M6 has the conduction terminals connected between the circuit node N1 and the corresponding bit line and the gate terminal connected to the word line WL. The bit lines are precharged high between each operation of the memory cell, while the internal nodes N1 and N2 are precharged low before a write operation. Figure 8 shows a further schematic diagram of a dual port embodiment of the RAM memory cell according to the present invention. As may be appreciated, this dual port solution provides a memory cell which is interconnected to a pair of word lines, WL_PORT1 and WL_PORT2, and to a double pair of bit lines, BL_PORT1, BL_PORT2; BLB_PORT1, BLB_PORT2. The first word line WL_PORT1 and the first bit lines BL_PORT1, BLB_PORT1 are connected to the memory cell as in the first embodiment of figure 2. A second pair of PMOS access transistors M7 and M8 is provided to connect the cell to the second word line WL_PORT2 and to the second bit lines BL_PORT2, BLB_PORT2. The second circuit node N2 is connected to the second bit line BL_PORT1 through the access PMOS transistor M7. This PMOS transistor M7 has the conduction terminals connected between the circuit node N2 and the corresponding bit line and the gate terminal connected to the second word line WL_PORT2. Accordingly, the first' circuit node N1 is connected to the other second bit line BLB_PORT2 through the access PMOS transistor M8. Even this PMOS transistor M8 has the conduction terminals connected between the circuit node N1 and the adjacent bit line and the gate terminal connected to the second word line WL_PORT2. A simultaneous read and write operation from the two ports PORT1, PORT2 to the same cell is not allowed. The RAM memory cell according to the invention has the' great advantage of allowing a reduction of the power consumption. This advantage is specifically evident for memory structures having a very long wordlenght.

Claims: A RAM memory cell (10) for a memory matrix comprising a plurality of word-lines (WL) and bit-lines (BL), said cell (10) including a first and a second cross-coupled CMOS inverters (12, 13), each including a PMOS pull-up transistor (M3, M4) and an NMOS pull-down transistor (M1, M2), and first and second access transistors (M5, M6) connecting the second (13) and the first inverter (12) to a corresponding bit line respectively, characterized in that the source terminals of the pull-down transistors (M1, M2) are connected to a precharge line (PL) which is common to all the cells (10) of a word line of said memory matrix. A RAM memory cell according to claim 1, characterized in that said first and second access transistors (M5. M6) are PMOS transistors. A RAM memory cell according to claim 2, characterized in that the gate terminals of said PMOS access transistors (M5, M6) are connected to the word line (WL). A RAM memory cell according to claim 1, characterized in that said precharge line (PL) is an extra line which is common to all the cells (10) of a word line. A RAM memory cell (10) for a memory matrix comprising a plurality of word-lines (WL) and bit-lines (BL), said cell (10) including a first and a second cross-coupled CMOS inverters (12, 13), each including a PMOS pull-up transistor (M3, M4) and an NMOS pull-down transistor (M1, M2), and first and second access transistors (M5, M6) connecting the second (13) and the first inverter (12) to a corresponding bit line respectively, characterized in that the source terminals of the pull-up transistors (M3, M4) are connected to a precharge line (PL) which is common to all the cells (10) of a word line of said memory matrix. A RAM memory cell according to claim 5, characterized in that said first and second access transistors (M5. M6) are PMOS transistors. A RAM memory cell according to claim 6, characterized in that the gate terminals of said PMOS access transistors (M5, M6) are connected to the word line (WL). A RAM memory cell according to claim 1, wherein the cell is a static RAM. A RAM memory cell according to claim 2, wherein the cell is a dual port RAM. A RAM memory cell according to claim 9, characterized in that a further pair of PMOS access transistors (M7, M8) is provided between the first and second CMOS inverters and a corresponding second bit line (BL_PORT2, BLB_PORT2).

Inventors: TONELLO STEFANO, TOOHER MICHAEL, TONELLO, STEFANO, TOOHER, MICHAEL
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1997
Main classification: G11C11
IPC codes: G11C11