JUNCTION FIELD EFFECT VOLTAGE REFERENCE AND FABRICATION METHOD

Abstract: A JFET pair (J1, J2) having unequal pinchoff voltages is operated in saturation with equal source-drain current to channel width-to-length ratios to provide a reference voltage output. Positive or negative voltage references can be implemented using either n-channel or p-channel JFETs. The pinchoff voltage difference results from the channel for one JFET having a heavier doping level than that of the other JFET.

Description: JUNCTION FIELD EFFECT VOLTAGE REFERENCE AND FABRICATION METHOD BACKGROTTNΠ OF THE INVENTION Field of the Invention This invention relates to voltage reference circuits and, more particularly, to low noise, linear temperature coefficient voltage reference circuits. Description of the Related Art Voltage reference circuits have been developed to provide precise voltage outputs for use in a variety of analog circuits such as operational amplifiers (op amps) , digital-to-analog converters (DACs) and analog to digital converters (ADCs) . Commonly used references include "Zener" and "bandgap", or ΔVBE, designs. Although such references are suitable for many applications, they are not without their problems. For example, their output voltages vary widely and nonlinearly with temperature, they are not always available in a desired voltage range, some exhibit a "hysteresis" effect, and their noise levels may preclude their use within systems which require a high degree of accuracy, especially low-power systems. Improved noise levels for both Zener and bandgap references may require operation at higher bias currents. As an example, to attain sixteen bit accuracy over an operating temperature range of 100 °C (limiting error to l A least significant bit) , the temperature coefficient of an ADC's voltage reference cannot exceed .08 ppm/°C and its noise density (for a 16 bit ADC with 10V full scale range) , must be limited to 40 nV/v/H: Operating at a bias current of lOOμA a Zener reference may have a noise density of lOOnV/VHz and a bandgap reference 300 Improving this noise performance would require a greater operating current . FIG.l illustrates a basic Zener voltage reference circuit. A voltage +V S is supplied to a resistor R s that is connected in series with a reverse-biased Zener diode Dl, the anode of which is connected to the anode of a forward biased diode D2, whose cathode is connected to ground. The output reference voltage V REF appearing at terminal 9, the junction of the resistor Rs and the cathode of Dl, is the sum of the forward voltage drop of diode D2 and the avalanche voltage drop of diode Dl. The attractive feature of this circuit is that, although the forward voltage drop of diode D2 exhibits a negative temperature coefficient, this offsets, to some degree, the positive temperature coefficient of the avalanche voltage drop of diode Dl. However, since the initial temperature dependency of the diode Dl is relatively large, i.e. approximately 300ppm/°C, establishing an offsetting voltage from the diode D2 which compensates for the variation in output voltage from diode Dl over a wide operating range is somewhat difficult. Additionally, because the avalanche breakdown voltage of diode Dl is typically in the 5 to 8V range, the reference voltage produced by such a circuit is in the 6 to 9V range. Since the reference must be driven from a voltage source higher than 6V, Zener references are not suitable for operation in systems which employ 5V or the increasingly popular lower supplies. In addition, voltage references based upon temperature compensated avalanche diodes tend to be noisy, due to noise generated by the di¬ ode's breakdown mechanism. Band-gap references provide a temperature-compensated reference which could operate from a lower (e.g. 5V or be- low) supply voltage. Band-gap references employ bipolar transistors having emitters of different sizes. Supplying the transistors with equal currents develops a difference in base-emitter voltage ΔV BE between the two transistors. Such references generally produce an output of the form V BE + ΔV BE (A) , where A is a gain factor. The V BE and ΔV BE compo- nents have opposite polarity temperature coefficients (ΔV BE is proportional to absolute temperature and V BE is comple¬ mentary to absolute temperature) which tend to cancel one another out. Numerous variations in bandgap reference cir¬ cuitry have been designed and are discussed, for example, in Fink et al . Ed., Electronics Engineers' Handbook. 3d ed., McGraw-Hill Book Co., 1989, pages 8.48-8.50. Although the output of a bandgap voltage cell is ide¬ ally independent of temperature, the outputs of bandgap cells have been found to include nonlinear temperature de- pendencies which are difficult to compensate. Addition¬ ally, the initial temperature dependency of the ΔV BE compo¬ nent is quite high, approximately 3000ppm/°C, and the dif¬ ficulty of compensating for a temperature coefficient is generally proportional to the magnitude of the initial tem- perature coefficient. Furthermore, a bandgap circuit's basic reference voltage ΔV BE is developed across a fixed resistor and, because of process variations and other lim¬ its upon the accuracy with which an absolute resistance value (as opposed to a ratio of resistances) may be pro- duced, the resistor imparts errors to the voltage refer¬ ence. Amplification of ΔV BE , represented by the gain A, introduces further noise into the reference output . The use of an absolute resistance further degrades the bandgap reference's performance because the resistor value will drift over time, causing the reference's output to simi¬ larly drif . Yet another problem of bandgap references is a "hysteresis effect"; that is, a bandgap reference which produces an initial reference voltage will, after being heated and then returned to its initial temperature, pro- duce a slightly different reference voltage. SUMMARY ΩF THE INVENTION The invention seeks to provide a JFET circuit which may be employed, to produce a low-noise voltage reference that is stable over time and temperature and is available in a wide range of voltages. It does this with a pair of junction field effect transistors (JFETs) that are formed with a precisely controlled difference between their pinchoff voltages. The two JFETs are operated with the same ratio of drain current to size (i.e. channel width- o- length ratio, ID1/W1/L1 = ID2/W2/L2) . Additionally, the JFETs are operated in saturation and, by maintaining the equality of this ratio, the difference in the JFETs' gate- to-source voltages will equal the difference in pinch-off voltage between them (ΔV G≤ = ΔV P ) . In a preferred implementation, equal size JFETs, (i.e. having equal channel width-to-length ratios) are supplied with equal drain currents and their sources are connected to a common voltage. The resulting difference in gate-to- source voltage between them provides a reference voltage. This basic circuit may be produced using p-channel or n- channel and enhancement-mode or depletion mode JFETs to provide positive or negative voltage references . The tem¬ perature coefficient of the reference is linear and, in one implementation, a current source which is proportional to temperature is employed to compensate for the basic refer¬ ence's temperature-dependent drift. The initial temperature coefficient of the basic two- JFET circuit is relatively low, approximately 100 ppm/°C, and linear. Temperature coefficient compensation is there- fore relatively easy and effective. The noise figure for the basic circuit is approximately when operated at a ias current of 6μA. This makes it particularly suit¬ able for low-noise, low-power applications (the noise fig¬ ure may be improved by operating the circuit at a higher bias current) . The circuit does not depend upon absolute resistance values, as with bandgap references, and there- f ore avoi d s the introduction of errors due to initial and time-dependent inaccuracies in resistor values. The cir ¬ cuit d oes not exhibit so severe a hysteresis effect as b and-gap references and, unlike Zener references, it may b e used for low-voltage applications, e.g., with a supply voltage of 5V or less. The invention also includes a method for producing the JFETs with precisely controlled differences between their pinch-of f voltages to make the reference highly accurate. The JFE T s are su b stantially identical except for h eavier ion implantation which alters the pinchoff voltages for some o f the JFETs relative to those that do not receive the heavier implant. These an d other features, aspects and advantages o f the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings. BRTF.F DESCRIPTION OF THE DRAWINGS FIG. l is a schematic diagram of a prior art Zener voltage reference circui . FIG.2 is a sectional view of a conventional p-channel JFET . FIG.3 is a schematic diagram of a pair of JFETs having dif ¬ f eren t pinc h off voltages in accordance with the invention. FIG . 4 is a schematic diagram of a positive voltage refer ¬ ence based upon the circuit of FIG.3. FI G .5 is a schematic diagram of another positive voltage reference circuit based upon the circuit of FI G .3. FIG.s 6 and 7 are schematic diagrams of alternate negative voltage reference circuits in accordance with the inven ¬ tion. FIG.8 is a schematic diagram of the positive voltage refer ¬ ence circuit shown in FIG.4 with an added temperature com ¬ pensation. DET A ILED DF^RTPTTON 0* TH INVENTIO The new JFET circuit and fabrication method are based upon JFET characteristics which can best be explained in the context of JFET device physics, a brief discussion of which is given below in connection with FIG.2. A more de- tailed description may be found in Edward S. Yang, Funda¬ mentals of Sem conductor DeviCPS. McGraw-Hill Book Company, New York 1978, pages 182-195. FIG.2 is a sectional view of a conventional depletion mode p-channel JFET, which is preferable to an enhancement mode device because of biasing considerations . Further discussion of JFETs will therefore refer to depletion mode devices, but the novel circuit could also employ enhance¬ ment mode devices. The JFET of FIG.2 is an ion-implanted device having a p-type substrate 10 with an n-type epitaxial tub 12 formed within the substrate 10. The n- type tub 12 has p-type source 14 and drain 16 regions dif¬ fused within it and a p-type channel 18 between the source 14 and drain 16 regions. An n-type top gate 19 is im¬ planted over the p-type channel 18. In operation, the gate 19/channel 18 junction is reverse-biased. In a depletion-mode JFET maximum drain current is pro¬ duced when the gate 19 is shorted to the source 14. By increasing the gate/channel reverse bias, i.e. increasing the gate-to-source voltage, depletion regions will extend into the channel 18 such that drain current is substan¬ tially "pinched-off" for all values of drain-to-source voltage. The gate-to-source voltage at which this pinchoff occurs is referred to as the JFET's pinchoff voltage. Spe¬ cifically, the pinchoff voltage of a JFET is given by: V P = a 2 [qN , ,(l + N A /N_,)/2e] -Ψ 0 where: a =. channel thickness q electron charge N Λ = effective channel doping N D = effective gate doping e = dielectric constant of the semiconductor material Ψ 0 = built in junction voltage For purposes of illustration, the assumption will be made that the JFET is made of silicon and all device param¬ eters will refer to silicon, e.g. e is the dielectric con¬ stant of silicon and has the value of 1.04E "12 . The built in junction voltage Ψ 0 is very temperature dependent and highly non-linear: undesirable characteristics for a voltage ref¬ erence. This undesirable temperature dependency arises from the built in junction voltage's relation to the JFET intrinsic carrier density: Ψ 0 = kT/q ln(N A N D /n x 2 ) Where: k = Boltzmann's constant T = temperature in K n. = the intrinsic carrier density of silicon Because the intrinsic carrier density n. doubles ap¬ proximately every 8K and is highly non-linear, the built-in junction voltage is also highly temperature dependent and non-linear. However, in the new reference circuit, the reference voltage is a function of the difference in pinchoff voltage between two JFETs. That is, { a 2 [qN A ( l+N A /N D ) /2e ] -Ψ 0 } 1 - { a 2 [qN A ( 1+N A /N D ) /2e ] -Ψ 0 } 2 Using the dif ference between pinchof f voltages of two otherwise identical JFETs which have different channel dop- ing densit ies el iminates the extreme nonlinear temperature dependency of the last term, Ψ 0 . This is illustrated by the f ol lowing equat ion : = kT/q ln Λ - / A2 where : N A1 = is the higher effective channel doping of a first JFET N A _, = is the lower effective channel doping of a second JFET The intrinsic carrier density n. can therefore be eliminated from the expression for the reference voltage by substitut¬ ing this expression for ΔΨ 0 into that for ΔV P : V RE - = Δ V p = {qa 2 /2e [N Al (1+N A1 /N D ) -N„ (1+N^/N ] - kT/q [ln(N A1 /N ω ) ] } To produce JFETs having the desired channel doping relationship, the difference between N ω and N M must be pre¬ cisely controlled. A diffusion process does not provide sufficient control of doping levels to produce the neces¬ sary precision in channel doping differences. An ion i - plantation process provides greater control over channel doping levels than a diffusion process, but this precision is conventionally employed to produce JFETs with precisely matched characteristics, not differences. Nevertheless, a single step ion-implantation process may be employed to provide the relative channel doping levels set forth above. However, employing a single channel-implantation step to produce precisely-controlled differences in channel doping levels (and therefore in pinchoff voltages) presents daunt¬ ing control problems. Suppose, for example, that channel doping levels of 1.10 E 12 and 1.25 E 12 are desired to produce a difference in pinchoff voltages corresponding to a dif- ference in doping levels of .15 E 1 . If the implant process provides 10% accuracy, a single implant step could produce one JFET with 1.10 +.11E 12 and another with 1.25 ± .125 E 12 . Consequently, the differences in channel doping levels could range from -.085 to .385 E 12 clearly an unacceptable result . For this reason, a new two-step channel ion implanta¬ tion process is employed in a preferred method to produce the desired difference in pinchoff voltages. That is, the desired difference in channel doping is produced by first producing JFETs using a conventional ion implantation pro¬ cess, i.e. one which yields substantially identical channel doping levels. Then a novel second channel implantation is performed on selected JFETs to produce the desired differ- ence in pinchoff voltages. Using the same target figures as in the above example, i.e., doping levels of 1.1 E 12 and 1.25 E 12 , and the same 10% variation in doping accuracy, the new method will produce a much lower variation between tar¬ get and actual doping level differences. If, for example, the initial channel doping is too heavy by 10%, both JFET channels will have channel doping levels of 1.21 E 12 . If, in the worst case, the second channel doping, targeted at .15 E 12 , is also 10% too heavy, one of the JFET channels will be doped to a level of 1.21 E 12 and the other will be doped to a level of 1.375 E 12 , yielding a channel doping level difference of .165 E 12 , much closer to the target val¬ ue of .15 E12 than would reliably be provided by a single implantation step. In one implementation a pair of p-channel JFETs are produced using Boron ions accelerated to 180 KeV and im¬ planted and driven to a depth of approximately .95 μm, at a concentration, or "dose", of approximately 1.10 E 12 atoms- /cc. Another 180 KeV Boron implant of 0.15E 12 concentration is then performed on the JFET(s) which is to have the high- er pinchoff voltage, yielding a final doping concentration within that JFET of approximately 1.25E 12 atoms/cc. The top gates of all the JFETs are then implanted with 150KeV Phos¬ phorous driven to a depth of approximately .37μm and con¬ centration of 1.50E 12 atoms/cc. This combination yields a pinchoff voltage difference between the JFETs of approxi- mately .5V. Using JFETs having controlled pinchoff voltage varia¬ tions as described, a novel circuit, illustrated in FIG. 3, develops a low-noise output voltage having a linear temper¬ ature coefficient which may be used, as described in rela- tion to FIGs. 4-7, as a voltage reference. In saturation, the drain current of a JFET is given (approximately) by the following relationship: which can be rearranged to yield: V GS = V p - V p (I D /I DSS )« where: VGS = JFET gate-to-source voltage ID = JFET drain current IDSS = saturation drain current Vp = pinchoff voltage Given this relationship, the pinchoff voltage, an "in¬ ternal" device characteristic, may be "brought outside", or reflected in an the external circuit. The difference in pinchoff voltages between two JFETs may be converted, for example, to a difference in gate-to-source voltage: v Gsl -v GS2 = {v p - I../W) ! - {v p - v p α D /ι DSS ) * ) 2 = v pl - v p2 - V pl (I D1 /l DSS1 )« + V p2 (I D2 /l DSS2 )* Because the difference in pinchoff voltages is well con¬ trolled with the novel process discussed in relation to FIG. 2, the difference in gate-to-source voltage should, ideally, be dependent only upon the first two terms on the right of the equation, i.e. ,V pl -V p2 . To eliminate the other terms on the right of the equation, one may note that a JFET's saturation drain current I DSS can be expressed as a function of the its channel width-to-length ratio and transconductance, as follows: loss = W/L β(Vp) 2 where: W = channel width L = channel length β = transconductance parameter(approximately 7μA/V 2 in a preferred implementation) Substituting this expression for I DSS yields: -V P1 [(I D1 /((w 1 /L 1 )β(V pl ) 2 )] « + V P -[(I D2 /((w 2 /L 2 )β(V p2 ) 2 )]'- for the unwanted terms. These terms cancel one another when: I DI /(W : /L.) = I D: /(W,/L 2 ) In a preferred embodiment, two JFETs are fabricated with equal channel width-to-length ratios and unequal pinchoff voltages. In operation, the JFETs are provided with equal drain currents. Returning to FIG.3, Jl and J2 are p-channel depletion mode JFETs fabricated with equal channel width-to-length ratios. Their respective gates GI and G2 are connected to a ground supply and their drains Dl and D2 are connected to a negative supply V' . Current sources ID1 and ID2 force equal saturation currents from a positive supply V * into Jl and J , respectively. The pinchoff voltage of JFET Jl is higher than that of J2 and, because the JFETs are in satu- raticn, the difference in their pinchoff voltages will be reflected at their source terminals. That is, the differ¬ ence in pinchoff voltages equals the difference in gate-to- source voltages. Because their gate voltages are equal, the source terminal of JFET J2 will therefore be ΔVP higher than that of Jl . A positive voltage reference circuit which employs the novel JFET pair is illustrated by the schematic diagram of FIG.4. A pair of p-channel JFETs Jl and J2 have their re¬ spective drains Dl and D2 connected to ground GND. Their sources SI and S2 are connected to the inverting 22 and noninverting 24 inputs respectively of an op amp 20 and to current sources ID1 and ID2 which provide equal drain- source currents to the JFETs. Since the op amp inputs 22 and 24 will be at substantially the same voltage, current sources IDl and ID2 may be implemented as equal resistors connecting the inputs 22 and 24 to the positive supply V + . The pinchoff voltage of J2 is greater than that of Jl . The output 25 of the op amp 20 is connected through a series combination of resistors Rl and R2 to a return supply GND. In a preferred implementation, resistors Rl and R2 are low temperature coefficient of resistance thin film resistors. The gate G2 of J2 is connected to the op amp output 25 and to the "high" side of resistor Rl. The gate GI of JFET Jl is connected to the junction 27 of resistors Rl and R2, i.e., the resistor Rl is connected across the gates of JFETs Jl and J2. The JFETs Jl and J2 have been fabricated in the manner set forth above, i.e. an extra implantation produces a higher pinchoff voltage for J2 than that of Jl and the width-to-length ratios of Jl and J2 are equal. Conse¬ quently, with equal drain currents forced through them, their gate-to-source voltages differ by the difference be¬ tween their pinchoff voltages and this voltage is impressed across resistor Rl. The current through Rl and R2 is ΔV P /R1 and the total voltage across Rl and R2, appearing at the output 25 of the op amp 20, will be ΔV P (1+R2/R1) . For proper circuit operation, as noted above, the JFETs J l and J 2 must b e operated in saturation, therefore the output reference voltage V REF is greater than the greater of the two JFET pinchoff voltages. Substituting n-channel JFETs for the p-channel Jl and J2 illustrated and reversing the current sources, the circuit of FIG.4 yields a negative voltage reference with an output voltage of -ΔV P ( 1+R2/R1 ) . The novel JFET pair is also employed in the positive voltage reference of FIG.5. P-channel JFETs J3 and J4 are connected from their respective drains D3 and D4 through loads L l and L2 (which could be active loads) to a return supply GND. The JFET drains D3 and D4 are also connected, respectively to the inverting 26 and noninverting 28 inputs of an op amp 30. The JFET sources S3 and S4 are connected to a current source ID4 and the pinchoff voltage of JFET J4 is higher than that of JFET J3. The op amp output 32 pro ¬ vides the circuit's reference voltage output and is con ¬ nected through a series combination of resistors R3 and R4 to the return supply GND and to the gate of J . The junc- tion 31 of series resistors R3 and R4 is connected to the gate of J3. With the loads Ll and L2 equal, the op amp 30 forces the gate-to-source voltages of J3 and J4 to a level which splits the current from the current source ID4 equally between J3 and J4, thereby maintaining substan- tially equal input voltages at the inverting 26 and noninverting 28 inputs of the op amp 30. With equal drain currents and equal source voltages, the difference between VGS4 and VGS3 ( Δ V P ) is impressed across resistor R3 and the current through resistors R3 and R4 is ΔV P /R3 The cir- cuit's output reference voltage V REF therefore is ΔV P (I+R4/R3) . Because this circuit requires more "headroom" to keep the JFETs in saturation, the reference output volt- a 9^ V REF is restricted to values greater than the sum of the load voltage and the pinchoff voltage of JFET J4. Substi- tutmg n-channel JFETs for the p-channel J3 and J4 illus ¬ trated and reversing the current source, the circuit of FIG.5 yields a negative voltage reference with an output voltage of -ΔV P (1+R4/R3) . A negative voltage reference, employing novel p-chan¬ nel JFETs, is illustrated in the schematic diagram of FIG. 6. The drains D5 and D6 of JFETs J5 and J6 are connected to a negative supply V " and their sources S5 and S6 are respectively connected to the inverting 34 and noninverting 36 inputs of an op amp 38. Current sources ID5 and ID6 provide equal drain-source currents for the JFETs J5 and J6, and maintain them in saturation. The pinchoff voltage of JFET J6 is greater than that of J5. Resistors R5 and R6 are connected in series between ground GND and the op amp output 40. The junction 39 of series resistors R5 and R6 is connected to the gate of J5. Consequently, the JFETs' is impressed across R5 and the current through R5 and R6 is ΔV P /R5. The output reference voltage V REF for this circuit is, then, -ΔV P (1+R6/R5) . To maintain the JFETs J5 and J6 in saturation, the magnitude of the output reference voltage must exceed the pinchoff voltage of J6. A positive refer- ence could also be produced using the same circuit by re¬ versing the current sources and substituting n-channel JFETs for the p-channel JFETs J5 and J6. The circuit of FIG.7 produces a lower-noise negative voltage reference V RBF , using new p-channel JFETs. The pinchoff voltage of JFET J8 is higher than that of JFET J7 and the sources S7 and S8 of JFETs J7 and J8 are connected through a current source ID7 to a ground supply GND. The drains D8 and D7 of J8 and J7 are connected respectively through equal loads L3 and L4 (L3 and L4 could be active loads) to a negative supply V " ,and directly to the inverting 42 and noninverting 44 inputs of an op amp 46. A voltage divider composed of resistors R7 and R8 connected in series spans the op amp output 48 and the ground supply GND. The junction 43 of the resistors R7 and R8 is connected to the gate of JFET J7. The op amp 46 establishes a voltage at its output 48 such that the gate-Co-source voltage of J7 steers equal currents through J7 and J8, thus maintaining equal voltages at its inputs 42 and 44. Since the op amp 46 maintains equal drain currents through J7 and J8, the difference between their pinchoff voltages will appear across R7 and the current through R7 and R8 will equal -ΔV P /R7. The output reference voltage therefore equals -ΔV P (I+R8/R7) . A positive reference may also be produced by substituting n-channel JFETs for the p-channel devices and reversing the current sources. The circuits of FIG.s 4-7 yield voltage references having temperature coefficients of approximately -120ppm/°C. This figure is orders of magnitude less than for an uncom- pensated Vbe used in bandgap references, and several times lower than the figure for a Zener reference, but it is still too high for many applications. Because this temper¬ ature coefficient is linear and relatively small, it may be readily compensated by introducing a temperature compensa¬ tion current Ic, as illustrated in FIG.8 (an implementation based upon the circuit of FIG. ) . All components of FIG.8 are identical to those of FIG.4, with the exception that a compensation resistor Re has been added between resistor R2 and ground. The compensation current has a positive tem¬ perature coefficient of 120 ppm/ D C and may be developed from a ΔVbe source, for example. The compensation current Ic develops a positive temperature coefficient voltage across the compensation resistor RC which cancels the negative temperature coefficient of the basic reference circuit . The compensation resistor RC may optionally be eliminated, with the compensation current injected at the junction of resistors Rl and R2. The compensation circuit should be biased so that Ic does not alter the reference voltage out¬ put V REF . The forgoing description of specific embodiments of the invention has been presented for the purposes of illus- tration and description. It is not intended to be exhaus¬ tive or to limit the invention to the precise forms dis- closed , and many modifications and variations are possible in light of the above teachings. For example, enhancement mode JFETs may be used, with proper biasing, to effect the circuits disclosed above. JFETs having differing channel wirdth-to-length ratios may be employed, with corresponding differences in drain currents (as long as the ratio 1 D ./( I /L I ) = I D _/( w 2 /li 2 ) is maintained), within the reference circuits described. Parameters other than the drain cur¬ rents may be forced, e.g. gate-to-source voltages may be forced to be equal, with a resultant difference in drain currents used as a reflection of the difference in pinchoff voltage between the JFETs. The novel JFET circuit pair having a difference in pinchoff voltage and operated with 1 DI /( W I /L I ) = i. / H /I_ ) may be used in applications other than voltage references. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention. It is intended that the scope of the invention be limited only by the claims appended hereto.

Claims: WE CLAIM : 1. A junction field effect transistor (JFET) voltage JFET reference, comprising: a pair of JFETs (Jl,J2) having unequal pinchoff voltages, and current sources (ID1, ID2)connected to provide respective drain-source saturation currents to said JFETs, said JFETs having channel width-to-length ratios in inverse proportion to their respective saturation currents from said current source. 2. The reference circuit of claim 1, wherein said JFETs have equal channel wirdth-to-length ratios. 3. A JFET voltage reference which provides a positive output voltage, comprising: a pair of JFETs (J1,J2) having source, drain and gate terminals, unequal pinchoff voltages, and equal channel width- to-length ratios, said JFETs' sources connected to receive equal currents from current sources (ID1,ID2), said currents being sufficient to maintain said JFETs in saturation, the drains of said JFETs connected to ground and the gates of said JFETs connected across a resistor (Rl)to produce the difference in pinchoff voltages between said JFETs across said resistor. 4. The voltage reference of claim 8, further comprising an amplifier (20) connected to amplify the voltage across said resistor. 5. A JFET voltage reference which provides a negative output, comprising: a pair of JFETs (J6,J5) having source, drain and gate terminals, unequal pinchoff voltages, and equal channel width- to-length ratios, said JFETs' sources connected to receive equal currents from current sources (ID6,ID5) , said currents being sufficient to maintain said JFETs in saturation, the drains of said JFETs connected to a negative supply (V-) and the gates of said JFETs connected across a resistor (R5) to produce the difference in pinchoff voltages between said JFETs across said resistor. 6. The voltage reference of claim 12, further comprising an amplifier (38) connected to amplify the voltage across said resistor. 7. A method for producing a pair of JFETs with unequal pinchoff voltages, comprising: implanting channels for each JFET within a substrate material, said implanted material having charge carriers of opposite polarity from the carriers of said substrate material, the implant level of one of said channels being heavier than that of the other channel, and implanting top gates within said channels, the material of said top gates having charge carriers of the same polarity as said substrate material. 8. The method of claim 7, wherein the channels having different implant levels are implanted in one step. 9. The method of claim 7, wherein the channels are implanted in a heavy implant step applied to both channels, then in a light implant step applied to one of the channels. 10. The method of claim 9, wherein said heavy implant step comprises implanting boron ions to a depth of approximately .95μm at a concentration of 1.1 E* 2 atoms/cc, the light implant step comprises implanting boron ions at a concentration of .15 E i2 atoms/cc, and the top gate implant comprises implanting phosphorous ions to a depth of approximately .37μm at a concentration of approximately 1.5 E 12 atoms/cc.

Inventors: BOWERS DEREK F, TIPPIE LARRY C, BOWERS, DEREK, F., TIPPIE, LARRY, C.
Applicants: ANALOG DEVICES INC, ANALOG DEVICES, INC. (ADI)
Application year: 1997
Main classification: G05F1
IPC codes: G05F3