THRESHOLD ADJUST IN VERTICAL DMOS TRANSISTOR

Abstract: A thick oxide region (64) is provided on an epitaxial layer (54) in turn overlying a semiconductor substrate (50). Base regions are provided on either side of the thick oxide region, and source regions are provided in the respective base regions. After formation of gate oxide portions and a gate, which gate extends over the gate oxide portions and thick oxide region, a threshold adjust implant is undertaken into the channel regions of the device, the thick oxide region blocking ions from reaching the epitaxial layer portion thereunder. In another embodiment, after formation of the gate oxide, gate, sources and drains, a mask portion is provided over a portion of the gate above the epitaxial layer portion between the base regions, so that upon implant of threshold adjust dopant, the mask portion blocks such dopant from reaching the area of the epitaxial layer portion thereunder.

Description: THRESHOLD ADJUST IN VERTICAL DMOS TRANSISTOR FIELD OF THE INVENTION This invention relates to vertical DMOS transistors, and more particularly, to the adjustment of the threshold voltage thereof. BACKGROUND OF THE INVENTION Fig. 1 shows a vertical DMOS transistor as disclosed in U.S. Patent No. 5,248,627, issued September 28, 1993, invented by Richard K. Williams and assigned to Siliconix incorporated, and as also disclosed in U.S. Patent No. 5,465,000, issued November 7, 1995, invented by Richard K. Williams and assigned to Siliconix incorporated, both incorporated herein by reference. As shown in such Fig. 1, the vertical DMOS transistor 20 includes a P- type epitaxial layer 22 on a P+ type silicon substrate 24. Spaced-apart N- base regions 26, 28 are formed in the epitaxial layer 22, and P+ source regions 30, 32 are formed in the respective base regions 26, 28. A gate oxide 34 extends over the channel regions 36, 38 and the portion 40 of the epitaxial layer 22 between the base regions 26, 28. A gate 42 is formed over the gate oxide 34, all in accordance with the disclosure of the above-cited patents. The backside of the substrate 24 acts as the drain 44 of the device 20. A P+ threshold adjust implant is undertaken into the channel regions to adjust the threshold voltage of the device, as shown by the dotted line 46. During such implant step, ions also pass through the gate 42 and gate oxide 34 into the epitaxial layer portion 40 between the base regions 26, 28. The device thus far described is highly effective in use as a low threshold, low on resistance MOSFET. However, in the use of a low threshold MOSFET in a switchable power converter where high switching speed is desirable, the gate-to- drain overlap capacitance is an important factor, i.e., high gate-to-drain capacitance is undesirable. This is so because each time the gate 42 is charged and discharged, power is lost, which decreases the efficiency of the power converter. By having threshold adjust dopant 46 in the portion 40 of the epitaxial layer between the base regions 26, 28, the doping concentration of the epitaxial layer 22 is raised so that in turn the capacitance between the drain 44 and the gate 42 is increased. This makes the device 20 less desirable in the power converter setting because the ideal device in this application would have very low gate to drain capacitance. An advantage of the method of the above-cited U.S. Patents is that the gate oxide can be made thicker than previous with a low threshold voltage still being obtainable, so that gate-to-source and gate-to-body capacitance are fairly low. However, with a fairly large gate-to-drain dimension, unnecessary added capacitance occurs, i.e., by raising doping in the epitaxial layer portion 40 less depletion occurs into the drain from the gate, so that the gate- to-drain overlap capacitance is increased. It would be desirable to provide a device with a low gate-to-drain capacitance and at the same time have a gate oxide that could be optimized to a chosen thickness desirable such that a low threshold voltage could still be achieved. This is particularly relevant, as pointed out above, in the use of such a device for high frequency application in switchable power supplies. SUMMARY OF THE INVENTION In one embodiment of the present invention, a thick oxide region is grown on an epitaxial layer in turn overlying a semiconductor substrate. Base regions are provided on either side of the thick oxide region in the epitaxial layer, and source regions are provided respectively in the base regions. After formation of gate oxide portions and a gate, which gate extends over the gate oxide portions and thick oxide region, a threshold adjust implant is undertaken into the channel regions, the thick oxide region blocking ions from reaching the epitaxial layer thereunder. In another embodiment, after formation of the gate oxide, gate, sources and drains, a mask portion is provided over a portion of the gate above the epitaxial layer portion between the base regions, so that upon implant of threshold adjust dopant, the mask portion blocks such dopant from reaching the area of the epitaxial layer portion thereunder between the base regions. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a prior art vertical DMOS device; Figs. 2-8 are cross-sectional views showing the process steps in fabricating a first embodiment of the invention; Figs. 9-12 are cross-sectional views showing the process steps in fabricating a second embodiment of the invention; Fig. 13 includes Fig. 13a which is a graph of functional characteristics of a representative device, and Fig. 13b which is a schematic of such a representative device; and Fig. 14 is a graph of other functional characteristics of a representative device. DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to Fig. 2, and in accordance with the disclosures of the above-cited United States Patents, the substrate 50 of the device 52 is typically silicon heavily doped with suitable P type dopant such as boron at a resistivity of O.OlΩcm or less and even as low as 0.00 lΩcm. After cleaning and polishing, a P type epitaxial silicon layer 54 is grown on the substrate 50 to a thickness generally from 3 to 60 microns and doped with a suitable P type dopant such as boron at a concentration generally between 5x10 to lxlO 14 atoms/cm 3 . The substrate 50 and epitaxial layer 52 form a semiconductor body 56. The surface 58 of the epitaxial layer is oxidized for a first masking process, forming an oxide 60 of a thickness generally from 50 to 2000A. Oxide 60 is typically thermally grown. Next, a nitride layer 62 of thickness 1 to 5KA is deposited over the oxide layer 60. The nitride layer 62 and oxide layer 60 are then patterned to expose a surface of the epitaxial layer 54. The exposed surface of the epitaxial layer 54 is then oxidized to grow a thick oxide region 64 (Fig. 3), for example, anywhere from 2000A thick to over 1 micron thick, typically in the temperature range of 900° to 1100° C. As an alternative, this thick oxide region 64 can be formed by growing a thick oxide over the entire epitaxial layer 54, and subsequent to appropriate masking, etching the thick oxide layer back to form the thick oxide region 64. In addition to forming the oxide region 64 in any or all of a plurality of cells or stripes, the oxide may also be left in the edge termination of the device. After removal of the nitride layer 62 and oxide layer 60 on either side of the thick oxide region 64, gate oxide portions 66, 67 (Fig. 4), of uniform high integrity, are grown, typically in a dry thermal oxidation to a thickness generally from 1 OOA to 1200A. With reference to Fig. 5, a polysilicon film 68 is deposited on the resulting structure, typically to a thickness of about 5000A but ranging from lOOOA to 7000A. The polysilicon film 68 is heavily doped with a suitable N type dopant such as phosphorous to achieve a sheet resistance of about 35 ohms/square, for example. A mask oxide 70 is formed over the polysilicon 68, typically by low- pressure chemical vapor deposition, followed by the deposition of a photoresist layer (not shown). The photoresist is patterned and the mask oxide 70 is etched to create a mask for the subsequent self-aligned double diffusions. The photoresist is stripped, and the polysilicon 68 is etched through use of the mask oxide 70 to form a gate structure 68 for subsequent double diffusion. As an alternative process, a thinner polysilicon layer, e.g., 600A to 2000A, can be deposited and coated with a thin layer of a refractive metal such as tungsten or titanium. The metal/polysilicon sandwich is then reacted by a high temperature cycle to form a tungsten-silicide or titanium-silicide layer. Any subsequent oxide must be deposited using low temperature chemical vapor deposition. The mask oxide 70 is etched in any suitable manner to remove portions of the oxide 66, 67 not covered by the polysilicon 68. Using the polysilicon 68 as mask features, an implant is undertaken using a suitable N type material such as phosphorous at a dose generally from lxlO 13 to 1x10 atoms/cm 2 and an energy generally from 60 to 120 KeV, and the implant is driven in using a suitable furnace for a time generally from 60 to 600 minutes at a temperature generally from 1000° to 1200°C. The PN junctions of the base regions 72, 74 formed along the surface 58 of the epitaxial layer 54 extend into the epitaxial layer 54 to a depth of about 2.5 microns, for example, and extends laterally under the edges of the polysilicon gate 68 a distance of about 2 microns, for example. A thin oxide 76, 78 also forms over the major part of the base regions 72, 74. Although not shown in the drawings, the thin oxide also extends over the polysilicon 68. In lower voltage devices, the body junction depth may be reduced to around 1.5μm with a lateral diffusion extending 1.2μm. Figs. 7 and 8 represent two P type implant operations, a source region implant and a threshold adjust implant, respectively. Fig. 7 shows the formation of source regions 80, 82 in base regions 72, 74 respectively. A suitable P type dopant such as boron is implanted through the mask provided by the polysilicon gate 68, at a dose generally 3x10 14 to 8x10 5 atoms/cm and an energy generally from 40 to 100 KeV. The source dopant is driven in for a time generally from 20 to 60 minutes at a temperature generally from 950° to 1100°C. to form source regions 80, 82 in the respective base regions 72, 74 along the surface 58. The source regions 80, 82 are self-aligned with the polysilicon gate 68 and form channel regions 84, 86 near the surface 58 of the epitaxial layer 54 under gate oxide 66, 67. The PN junction of the source region 80 extends into the epitaxial layer 54 to a depth of about 1 micron, for example, and extends laterally under the edge of the polysilicon gate 68 a distance of about 0.8 microns, for example. The PN junction of the source region 82 has similar dimensions. Fig. 8 shows the undertaking of a high energy P+ threshold adjust implant through the same mask, the polysilicon gate 68, as is used for the source implant. The general and specific considerations involved in setting the various process conditions for the threshold adjust implant are discussed in the above-cited patents. As the threshold adjust implant is made with higher energy than the source implant, it penetrates more deeply into the epitaxial layer 54 than the source implant. The region of P concentration resulting from the threshold adjust implant is generally shown by the dotted lines 88, 90. As will be noted, the thick oxide region 64 (much thicker than the gate oxide portion) keeps the threshold adjust implant from penetrating into the epitaxial layer portion 92 thereunder defined by and between the base regions 72, 74. Thus, the threshold adjust dopant does not extend continuously from one base region to the other, but in fact the portion 92 of the epitaxial layer 54 is free of threshold adjust dopant. The device is then completed in normal process fabrication, using the backside of the substrate 50 as a device drain 94. As described above, by blocking dopant of the threshold adjust implant from reaching the epitaxial layer portion 92 between the base regions 72, 74, gate-to-drain capacitance of the device is reduced as compared to the device of Fig. 1. In addition, the relatively larger thickness of the oxide region further reduces this capacitance. The present structure and process thus lend themselves to efficient application in switchable power supplies where high speed switching is desirable. With reference to Figs. 9-12, an alternative method and device are shown. Similar to the above, a gate oxide 100 (Fig. 9) is grown on an epitaxial layer 102 in turn grown on a semiconductor substrate 104, the epitaxial layer 102 and substrate 104 making up a semiconductor body 106. A polysilicon film 108 is deposited on the resulting structure, which film is heavily doped with a suitable N type dopant such as phosphorous. A mask oxide 110 is formed over the polysilicon, followed by the deposition of a photoresist layer (not shown). The photoresist is patterned and the mask oxide 110 is etched to create a mask for the subsequent self-aligned double diffusions. The photoresist is stripped, and the polysilicon 108 is etched through use of the mask oxide 110 to form a gate structure for subsequent double diffusion. After forming the base regions 112, 114 (Fig. 10) and source regions 116, 118 (Fig. 11) as described above (forming thin oxide 120, 122 over the major part of the base regions 112, 114), and prior to the threshold adjust implant, a mask portion 124 (Fig. 12) is configured over the polysilicon gate 108, so that this mask portion 124 blocks the threshold adjust implant from penetrating into the epitaxial layer portion 126 thereunder between the base regions 112, 114 (indicated by the dotted lines 128, 130). The device is then completed in normal process fabrication, using the backside of the substrate 104 as a device drain 128. Again, by blocking dopant of the threshold adjust implant from reaching the epitaxial layer portion 126 between the base regions 112, 114, gate-to-drain capacitance of the device is reduced as compared to the device of Fig. 1. The present structure and process again thus lend themselves to application in switchable power supplies where high speed switching is desirable. To understand the benefits of the invention, consider Q g as the charge which must be forced onto the gate to turn the device on. The gate charge Q g is actually divided into the charge needed to charge the gate to source capacitance C gs and the gate-to-drain capacitance C cg (see Fig. 13). The term C gd is more important because its influence is amplified by the gain of the transistor during switching (a type of effect similar to the well known Miller effect in bipolar transistors). Gate charge is convenient since power loss becomes independent of the linearity of the parasitic capacitances. As the gate is charged at a rate of I g the gate voltage V G rises until the drain voltage V D begins to drop. While the drain voltage V D slews downward, the displacement current charging C gd cancels the gate current I g and the gate voltage V G goes constant. In such a mode the transistor is saturated acting as a current source in an amplifier. The effective value of C gd is thereby amplified and takes even more charge to satisfy. Once the voltage of the drain V D collapses to near the source and the device becomes a resistor, the gate voltage V G resumes its upward progress at a slope Con. The on state point (Q g (on), V gs (on)) has an equivalent capacitance Ceq = _Qg(on I = 5 C . ss Vgs(on) roughly 5 times the offstate input capacitance. The remaining terms R DS and Q g are both functions of V G , where roughly the form Q g (on) = Q g ' + (V g (on) -V g ').Con describes the curves shown in Figure 14, where Con is the slope of the Q g , V GS curve after the MOSFET is on i.e., above ZV in the example. In this graph the gate charge curve of Figure 13 has been flipped so that V G becomes the x-axis, and Q g is on the y-axis. Q g is a value which is proportional to gate drive power loss. With V GS on the x-axis, we can now plot the R DS (on) on the y-axis, a term proportional to conduction loss. Notice that since high V GS increases Q g and the drive losses because it reduces Q g without sacrificing on-resistance the electrical characteristics of the inventive device are particularly well suited for low- voltage high-frequency switching operation such as DC/DC conversion. To assess the benefit of this approach we must consider the power loss of a low voltage MOSFET during high speed switching, which can be approximated by a combination of resistive (conduction) losses and capacitive (gate drive) losses, or P t e = rPv D s(on)D + Q g V g F where the duty cycle D can be assumed as 50% and the frequency F may range from 600kH z to 2MH Z . Load currents vary widely but many applications draw currents in the range of 100mA to 1 A. By decreasing the conduction losses by lowering on resistance, the sum of these terms has a minimum signifying a tradeoff between capacitance and on-resistance. Thinning the gate oxide to achieve a low on-resistance necessarily increases Q g . The thinner oxide makes a low threshold easier to achieve if the threshold adjust of the above-cited patents is not employed. Using this invention V t can be lowered without using an extremely thin gate oxide. The V t adjust will result in a high value of C gd since the overlap capacitance is less voltage dependent when the concentration is increased. In other words, the curves of transistor Ml can achieve 300mΩ at 4V=V GS but the device suffers from 2nC of Miller charge. A thick gate high threshold part can reduce the knee of the gate charge curve to InC but doubles the R DS (on). Using the disclosed invention of the terraced gate oxide with the localized V t adjust, the 300mΩ on-resistance and InC charge can be achieved in the same device. The resulting Q g R DS product can be improved over present day solutions by a factor of 2X to 5X.

Claims: CLAIMS 1. A semiconductor device comprising: a semiconductor body of a first conductivity type; first and second spaced apart base regions of a second conductivity type opposite the first conductivity type in said semiconductor body along a surface thereof and defining a semiconductor body portion therebetween; first and second source regions of said first conductivity type situated respectively in the first and second base regions along said surface; a drain region of said first conductivity type in the semiconductor body; the first body region and first source region defining a first channel region, the second body region and second source region defining a second channel region; first and second insulating material portions on said respective first and second channel regions; first and second gate portions on said respective first and second insulating portions; and a threshold adjust dopant provided in said first and second channel regions but not extending continuously in said semiconductor body portion from said first base region to said second base region. 2. The device of Claim 1 wherein substantially the entire semiconductor body portion between the first and second base regions is free of threshold adjust dopant. 3. The device of Claim 1 and further comprising an insulating region on said semiconductor body between said first and second base regions, said insulating region being thicker than said insulating material portions. 4. The device of Claim 1 wherein the threshold adjust dopant is of the same conductivity type as the source regions. 5. A method of fabricating a semiconductor device comprising: 5 providing a semiconductor body of a first conductivity type; providing an insulating region on said semiconductor body, said insulating region having a semiconductor body portion thereunder; providing first and second insulating material portions on said semiconductor body adjacent opposite sides of said insulating region; o providing first and second gate portions over said respective first and second insulating portions; providing first and second spaced apart base regions of a second conductivity type opposite said first conductivity type in said semiconductor body on opposite sides of the insulating region; 5 providing first and second source regions of said first conductivity type in said first and second base regions respectively, so that the first base region and first source region define a first channel region covered by the first insulating material portion and first gate portion, and the second base region and second source region define a second channel region covered by 0 the second insulating material portion and second gate portion; and providing a threshold adjust dopant in said first and second channel regions so that such dopant does not extend continuously in the semiconductor body portion from the first base region to the second base region. 5 6. The method of Claim 5 wherein the step of providing the threshold adjust dopant comprises implanting dopant into the semiconductor body, the insulating region blocking dopant from passing therethrough into the semiconductor body portion thereunder. 0 7. The method of Claim 6 and further comprising the step of providing that the threshold adjust dopant is of the same conductivity type as the source regions. 8. A method of fabricating a semiconductor device comprising: providing a semiconductor body of a first conductivity type; providing a layer of insulating material having first and second portions on said semiconductor body; providing first and second spaced apart base regions of a second conductivity type opposite said first conductivity type in said semiconductor body along a surface thereof and defining a semiconductor body portion therebetween; providing first and second source regions of said first conductivity type in the first and second base regions respectively along said surface so that the first base region and first source region define a first channel region covered by the first insulating material portion and first gate portion, and the second base region and second source region define a second channel region covered by the second insulating material portion and second gate portion; providing a drain region of said first conductivity type in said semiconductor body; providing a mask element over the gate; and implanting a threshold adjust dopant into the first and second channel regions, the mask element being positioned to block the threshold adjust dopant from reaching at least a portion of the semiconductor body region between the first and second spaced apart base regions. 9. The method of Claim 8 and further comprising the step of providing the threshold adjust dopant to be of the same conductivity type as the source regions.

Inventors: WILLIAMS RICHARD K, WILLIAMS, RICHARD, K.
Applicants: SILICONIX INC, SILICONIX INCORPORATED
Application year: 1997
Main classification: H01L29
IPC codes: H01L21, H01L29