JITTER REDUCTION MODULE

Abstract: Automatic test equipment having an apparatus for reducing jitter in a test system clock, including at least one transmission line for providing a delivery path for the test system clock, two tuning stubs for tuning the delivery path, and an RF transformer for providing a jitter output and electrically isolating the jitter output from the delivery path. The apparatus reduces jitter in the test system clock without substantially altering clock characteristics such as voltage levels, duty cycle, and overall shape of the test system clock.

Description: JITTER REDUCTION MODULE This invention relates generally to automatic test equipment, and more particularly to reducing jitter in a test system clock. Automatic test equipment, generally known as testers, are commonly used in the electronics industry for determining whether electronic components, semiconductor devices, or printed circuit board assemblies contain manufacturing defects. Further, testers generally consist of computerized control circuitry, driver and receiver channels, and tester pins, which connect nodes of a device under test (DUT) to the driver and receiver channels. During a typical test session, the driver channels apply test signals to the DUT, and the receiver channels detect output signals produced by the DUT in response to the test signals. The output signals are then generally evaluated by comparing them with expected response signals, which would be produced by a properly functioning device. An important feature of testers is the ability to apply the test signals and to detect the output signals at precisely specified times. Accordingly, testers typically include timing generators, which generate timing signals known as "edges." For example, a first specified edge may cause a driver channel to start applying a test signal, while a second specified edge may cause the driver channel to stop applying the test signal. Similarly, a third specified edge may cause a receiver channel to start detecting output signals, while a fourth specified edge may cause the receiver channel to stop detecting the output signals. Another important feature of testers is the ability to test the DUT at fast data rates. This is because, in many cases, faults or errors in the DUT can only be detected when the DUT is exercised at data rates that either meet or exceed the operating speed of the DUT. However, we have recognized that as the data rates of testers increase, it becomes more difficult to specify precisely the times when the edges occur. One reason for this is that jitter, which generally causes the phase of signals to vary over time, usually becomes more prominent with increasing data rates. Such jitter is inherent in test system clocks used by most timing generators. One way of reducing jitter in the test system clocks is through filtering. In particular, a band-pass filter, centered at the fundamental frequency of a clock, has been used to attenuate jitter components of the clock. However, the band-pass filter also generally attenuates higher-order harmonics of the clock. This means that although the jitter components might be sufficiently reduced, the overall characteristics of the clock may be changed. For example, the attenuation of higher-order harmonics typically reduces the slope of a clock signal at transition regions between high and low voltage levels. Another way of reducing jitter is to regenerate the clock using a phase-locked loop, which typically includes a voltage-controlled oscillator, a low-pass filter, and a feedback circuit. However, jitter in the regenerated clock is normally dependent upon the quality of the voltage- controlled oscillator. This tends to complicate the design of the phase-locked loop, thereby increasing the cost of testers . It would therefore be desirable to have a method of reducing jitter in a test system clock that does not alter characteristics of the clock such as voltage level, duty cycle, and overall shape of the clock. It would also be desirable to have a method of reducing jitter that is inexpensive and easy to implement. SUMMARY OF THE INVENTION With the foregoing background in mind, it is an object of the invention to reduce jitter components of a test system clock in a tester. Another object of the invention is to provide an apparatus for reducing test system clock jitter in a tester that is inexpensive and easy to implement. The foregoing and other objects are achieved in a jitter reduction module including a clock input, and a first port for providing a clock output with reduced jitter. A first open-circuited tuning stub is connected between the clock input and the first output, and is tuned for providing maximum gain at all integer multiples of the fundamental frequency of a test system clock. In a preferred embodiment, the first open-circuited tuning stub has an electrical length that is equal to one- half of the wavelength of the test system clock. In another embodiment, the jitter reduction module includes a second port for providing a jitter output, and a radio frequency (RF) transformer connected between the clock input and the second output. The RF transformer is preferably a balun having a transforming ratio of 1:1, and a ferrite rod core. In still another embodiment, a short-circuited tuning stub is connected between the RF transformer and the second outp t. The short circuited tuning stub preferably has an electrical length that is equal to one-half of the wavelength of the test system clock. In yet another embodiment, a second open-circuited tuning stub is connected between the RF transformer and the second output. The second open-circuited tuning stub preferably has an electrical length that is equal to one- quarter of the wavelength of the test system clock. Still further objects and advantages will become apparent from a consideration of the ensuing description and drawings . BRIEF DESCRIPTION OF THE DRAWINGS The invention will be better understood by reference to the following more detailed description and accompanying drawings in which FIG. 1 is a partial block diagram of a tester incorporating a jitter reduction module in accordance with the present invention, FIG. 2 is a block diagram of the jitter reduction module used with FIG. 1, and FIG. 3 is a block diagram of another embodiment of the jitter reduction module. DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 depicts a partial block diagram of tester 100, which incorporates jitter reduction module 104 in accordance with the present invention. In a typical test configuration, a test engineer develops test programs on computer work station 103. The test programs generally include a series of test vectors. The test engineer also typically enters commands on computer work station 103, including commands for starting a test or specifying operating parameters. In particular, the test engineer might specify a frequency of a test system clock, which is subsequently produced by frequency generator 102, thereby specifying a test cycle. The frequency of the test system clock is typically in the RF band; i.e., from 20 MHz to 800 MHz. Further, frequency generator 102 is coupled to both frequency reference 101, which provides a reference for the test system clock, and jitter reduction module 104, which is coupled to vector sequencer 105. Jitter reduction module 104 will be discussed in greater detail below. The test engineer then typically enters a command on computer work station 103 for loading the test programs into memory 110 included in vector sequencer 105. For example, during a specified test cycle, processor 109, which is also included in vector sequencer 105, sequentially reads the test vectors from memory 110, and then sends data values, timing information, and format information to channel 106. As shown, channel 106 is but one of a plurality of channels included in tester 100. Further, tester pin 107, which is also one of a plurality of tester pins, connects channel 106 to one of the nodes of device under test (DUT) 108. The number of tester pins is generally equal to the number of channels in tester 100. The data values are typically logical values of binary digits 0 and 1, and the format information generally indicates whether the data values are applied to or captured at certain nodes of DUT 108. Also, the timing information generally indicates when the data values are applied or captured, relative to the beginning of the specified test cycle. Accordingly, channel 106 includes circuitry (not shown) for either applying test data to DUT 108 or capturing output data produced by DUT 108 in response to the test data. Tester 100 then compares the captured output data with expected data, which is also typically stored in memory 110. The comparing is usually implemented in software using processor 109, which generally responds to a series of programmed steps. If the captured output data matches the expected data, then tester 100 would normally indicate that DUT 108 is functioning properly. Frequency reference 101, frequency generator 102, computer work station 103, vector sequencer 105, channel 106, and tester pin 107 represent components that are included in a conventional tester. The construction of each of these components are therefore known to those skilled in this art. It follows that specific implementations of these components are not critical to the present invention. FIG. 2 shows a block diagram of one embodiment of jitter reduction module 104. Frequency generator 102 provides jitter reduction module 104 with the test system clock on line 113, which is the electrical equivalent of a transmission line. In the preferred embodiment, line 113 is a coaxial cable having a center signal conductor for carrying the test system clock, and a grounded outer conductor. Open-circuited tuning stub 114 is also preferably a coaxial cable having a grounded outer conductor and a center signal conductor, which is coupled to the center signal conductor of line 113. Open-circuited tuning stub 114 preferably has an electrical length that is equal to one-half of the wavelength, λc, of the test system clock. For the preferred embodiment shown, both line 113 and open-circuited tuning stub 114 have a characteristic impedance, ZO . This simplifies the impedance and gain calculations shown below. However, it should be noted that, in practice, the respective characteristic impedances of line 113 and tuning stub 114 need not be the same. An important advantage of jitter reduction module 104 is that it reduces jitter in the test system clock without substantially altering characteristics of the clock such as voltage level and overall shape. This is because the gain of jitter reduction module 104 is approximately unity for the fundamental frequency and higher-harmonics of the test system clock. In particular, it is known that the impedance of open- circuited tuning stub 114 as a function of frequency may be expressed as Zll4(f) = -j (ZO)cot [ (2πf/fcλc) 1114] , where fc is the fundamental frequency of the test system clock, and I114 is the electrical length of open-circuited tuning stub 114, which is equal to λc/2 for the preferred embodiment. Accordingly, Zii4(f) = -j (ZO)cot [ (f/fc)π] . Further, the gain from the input to the output of jitter reduction module 104 may be expressed as A = Zii4(f)/[2Zii4(f)+Z0] . This quantity will be referred to as the gain at the test system clock output of jitter reduction module 104. It follows that Zii4(f), and therefore A, approach successive maxima as the frequency, f, approaches respective frequencies fc, 2fc, 3fc, and so on. Also, Zιi4(f), and therefore A, approach zero (0) when the frequency, f, approaches respective frequencies (1/2) fc, (3/2)fc, (5/2) fc, and so on. This means that maximum gain is achieved for the fundamental frequency and higher- harmonics of the test system clock. Also, because noise with frequencies approaching (1/2) fc, (3/2) fc, (5/2) fc, and so on, normally constitute jitter, jitter components in the test system clock are reduced. FIG. 3 shows a block diagram of another embodiment of jitter reduction module 104. Frequency generator 102 once again provides jitter reduction module 104 with the test system clock on line 115. In the preferred embodiment, line 115 is a coaxial cable having a center signal conductor for carrying the test system clock, and a grounded outer conductor . The test system clock on line 115 is introduced at one end of a primary coil of RF transformer 119, which is also commonly known as a transmission line transformer. In the preferred embodiment, RF transformer 119 is a balun having a transforming ratio of 1:1, and a ferrite rod core, thereby making the balun linear. The transforming ratio of 1:1 is chosen for maximizing the bandwidth of RF transformer 119. Lines 116 and 117, which are also coaxial cables having grounded outer conductors in the preferred embodiment, are coupled to RF transformer 119 at the other end of the primary coil. Line 116 is preferably an open- circuited tuning stub having an electrical length that is equal to one-half of the wavelength, λc, of the test system clock. Further, line 117 provides a test system clock with reduced jitter to vector sequencer 105. The test system clock is induced in a secondary coil of RF transformer 119. One end of the secondary coil is grounded, while the other end of the secondary coil provides jitter output 120 and is coupled to line 118, which is also preferably a coaxial cable with a grounded outer conductor. RF transformer 119 electrically isolates jitter output 120 from line 116, and lines 115 and 117, which are part of the signal path for the test system clock. Further, lines 115, 116, 117, and 118 each have a characteristic impedance, Z0, for the preferred embodiment shown. This simplifies the impedance and gain calculations that follow. However, the invention described herein is meant to include those embodiments in which lines corresponding to lines 115, 116, 117, and 118 have any appropriate characteristic impedance. Jitter reduction module 104 uses both lines 116 and 118 as tuning stubs for transmission lines 115 and 117. In particular, it was described above that the impedance of an open-circuited tuning stub, more specifically line 116, as a function of frequency, may be expressed as Zll6,OPEN(f) = -j (ZO)COt [ (2πf/fcλc) 1116] , where fc is the fundamental frequency of the test system clock, and lιi6 is the electrical length of line 116, which is preferably equal to one-half of the wavelength, λc, of the test system clock. It follows that Zll6,OPEN(f) = -j (zo)cot [ (f/fc)π] . In the preferred embodiment, line 118 is a short- circuited tuning s.tub. It is known that the impedance of a short-circuited stub, more specifically line 118, may be expressed as ZU8, SHORT (f) = j (Z0) tan [2πf/fcλc) liis] . Further, line 118 preferably has an electrical length, Ins, that is equal to λc/2. Accordingly, Ziiδ, SHORT (f) = j (ZO) tan[ (f/fc)π] . The gain at the test system clock output of jitter reduction module 104 may be expressed as Ac = ( Z0Z116 + Z116Z118 ) / ( Z0Zll6 + Z0Zll8 + 2 Zll6Zll8 ) . Also, the gain at jitter output 120 may be expressed as AJ = ( ZOZ1I8 + ZII6ZII8 ) / ( Z0Zll6+Z0Zll8+2Zll6Zll8 ) . Consequently, Zii6,OPE (f) approaches successive maxima, and Z118 , SHORT ( f ) approaches null, as the frequency, f, approaches respective frequencies fc, 2fc, 3fc, and so on. Further, Zii6,0PEN(f) approaches null, and Z118, SHORT (f) approaches successive maxima, as f approaches respective frequencies (1/2) fc, (3/2) fc, (5/2) fc, and so on. This means that the gain at the test system clock output, Ac, is approximately unity at respective frequencies fc, 2fc, 3fc, and so on, which are the fundamental frequency and higher-harmonics of the test system clock. Also, Ac is approximately null at respective frequencies (1/2) fc, (3/2) fc, (5/2) fc, and so on, which normally constitute jitter. Accordingly, line 117 passes a test system clock with reduced jitter to sequencer 105 (FIG. 1) . This also means that the gain at jitter output 120, AJ, is approximately unity at respective frequencies (1/2) fc, (3/2) fc, (5/2) fc, and so on. Additionally, AJ is approximately null at respective frequencies fc, 2fc, 3fc, and so on. Accordingly, jitter output 120 provides substantially all of the jitter derived from the test system clock. In still another embodiment, line 118 is an open- circuited tuning stub having an electrical length that is equal to λc/4. Accordingly, Zii8,0PEN(f) = -j (Z0)cot[ (f/2fc)π] . Consequently, Zιi8,0PEN(f) is non-zero as f approaches respective frequencies (1/2) fc, (3/2) fc, (5/2) fc, and so on. Further, Zii8,0PEN(f) approaches null as the frequency, f, approaches fc, 3fc, 5fc, 7fc, and so on, which are the fundamental frequency and odd harmonics of the test system clock. As a result, line 117 passes a test system clock with more jitter than the preferred embodiment described above, which included line 118 having an electrical length, λc/2, and an impedance, Zιi8, SHORT (f) . However, this embodiment may have advantages of less weight and smaller signal loss for some lower frequency applications. Another advantage of jitter reduction module 104 is that the jitter provided by jitter output 120 can be measured and analyzed by the test engineer. This is sometimes useful in evaluating the quality of the test system clock provided by line 117. Having described one embodiment, alternative embodiments or variations might be made. For example, lines 114, 116, and 118 may be configured with different electrical lengths for achieving optimal weight, signal loss, and jitter reduction for various applications. Also, alternative embodiments of RF transformer 119 may be used for achieving optimal isolation between line 117, which is the test system clock output, and jitter output 120. Also, the embodiment of jitter reduction module 104 shown in either FIG. 2 or FIG. 3 may be combined with the prior art apparatus for reducing jitter, which regenerated the test system clock using a phase-locked loop. In particular, jitter reduction module 104 may be coupled to the output of the phase-locked loop for further reducing any jitter that might remain in the regenerated clock. Therefore, the invention should be limited only by the spirit and scope of the appended claims.

Claims: What is claimed is 1. Automatic test equipment including a jitter reduction module, the jitter reduction module comprising: (a) a transmission line for carrying a test system clock; and (b) a tuning stub coupled to the transmission line. 2. The automatic test equipment as recited in claim 1, wherein the tuning stub is a coaxial cable with an open-circuited termination. 3. The automatic test equipment as recited in claim 2, wherein the tuning stub has an electrical length equal to one-half of the wavelength of the test system clock. 4. Automatic test equipment including a jitter reduction module, the jitter reduction module comprising: (a) a first transmission line for inputting a test system clock; (b) an RF transformer having a primary coil and a secondary coil, the first transmission line being coupled to one end of the primary coil; (c) a second transmission line for outputting a test system clock with reduced jitter, coupled to an opposite end of the primary coil; (d) a first tuning stub coupled to the opposite end of the primary coil; and (e) a second tuning stub coupled to the secondary coil. 5. The automatic test equipment as recited in claim 4, wherein the RF transformer is a 1:1 balun. 6. The automatic test equipment as recited in claim 4, wherein the first tuning stub is a coaxial cable with an open-circuited termination. 7. The automatic test equipment as recited in claim 6, wherein the first tuning stub has an electrical length equal to one-half of the wavelength of the test system clock. 8. The automatic test equipment as recited in claim 4, wherein the second tuning stub is a coaxial cable with a short-circuited termination. 9. The automatic test equipment as recited in claim 8, wherein the second tuning stub has an electrical length equal to one-half of the wavelength of the test system clock. 10. The automatic test equipment as recited in claim 4, wherein the second tuning stub is a coaxial cable with an open-circuited termination. 11. The automatic test equipment as recited in claim 10, wherein the second tuning stub has an electrical length equal to one-quarter of the wavelength of the test system clock. 12. A clock jitter reduction module, comprising: (a) a first cable for providing a clock signal delivery path; and (b) a second cable, coupled to the first cable, for tuning the clock signal delivery path using microwave techniques . 13. The clock jitter reduction module as recited in claim 12, wherein the second cable is a coaxial cable with an open-circuited termination. 14. The clock jitter reduction module as recited in claim 13, wherein the second cable has an electrical length equal to one-half of the wavelength of the clock signal. 15. A clock jitter reduction module, comprising: (a) a first cable for inputting a clock signal; (b) an RF transformer having a primary and a secondary coil, one end of the primary coil being coupled to the first cable; (c) a second cable coupled to an opposite end of the primary coil, for outputting a clock signal with reduced jitter; (d) a third cable having an open-circuited termination coupled to the opposite end of the primary coil; and (e) a fourth cable having a short-circuited termination coupled to the secondary coil . 16. The clock jitter reduction module as recited in claim 15, wherein the RF transformer is a 1:1 balun. 17. The clock jitter reduction module as recited in claim 15, wherein the third cable has an electrical length equal to one-half of the wavelength of the clock signal. 18. The clock jitter reduction module as recited in claim 15, wherein the fourth cable has an electrical length equal to one-half of the wavelength of the clock signal. 19. The clock jitter reduction module as recited in claim 15, wherein the fourth cable has an open-circuited termination. 20. The clock jitter reduction module as recited in claim 19, wherein the fourth cable has an electrical length equal to one-quarter of the wavelength of the clock signal.

Inventors: XU FANG, XU, FANG
Applicants: TERADYNE INC, XU FANG, TERADYNE, INC., XU, FANG
Application year: 1997
Main classification: G06F11
IPC codes: G01R31, G06F1, G06F11, H01P1