DISTORTION COMPENSATION FOR A CAPACITIVELY LOADED FOLLOWER

Abstract: The odd harmonic distortion components in the output signal (vo) of a capacitively loaded follower transistor (2) is reduced by means of an additional transistor (14) inserted between the emitter of the follower transistor (2) and the bias current source (12) of the follower transistor (2) and a second follower transistor (18) which receives the same input signal as the follower transistor (2) and which has its emitter coupled to the emitter of the additional transistor (14) via a compensation capacitor (20). The current iC through the compensation capacitor (20) is added to the output current (io) and compensates for the odd harmonic distortion.

Description: Distortion compensation for a capacitively loaded follower The invention relates to a transistor circuit comprising an input terminal for receiving an input signal, an output terminal for providing a buffered output signal in response to the input signal, a first transistor having a control electrode coupled to d e input terminal, a first main electrode coupled to the output terminal and a second main electrode, and a first bias current means coupled to the first main electrode for supplying a first bias current to e first transistor. Such a transistor circuit is the well known follower and is widely used as a buffer for driving capacitive loads. For example in sampling circuits, e.g. Track and Hold Circuits or Sample and Hold Circuits, where the signal is stored in a capacitor, some drive capacity is required in order to store the input signal with sufficient accuracy at the desired signal speed. A very basic circuit for this purpose is the follower. A bipolar implementation of the follower including the capacitive load is shown in Fig. 1. Due to the non-linear voltage-to-current transfer characteristics of a transistor the output signal across the capacitive load can be expressed as a level shifted version of the input signal plus a series of even harmonic distortion terms and a series of odd harmonic distortion terms. Using a differential circuit topology the even harmonic distortion terms can be suppressed and theoretically be eliminated supposing ideal matching between the duplicated circuit parts. However, the odd harmonic distortion terms cannot be suppressed in this way. Therefore, it is an object of the present invention to provide a follower with compensation for odd harmonic distortion. For this purpose the transistor circuit as specified in the opening paragraph is characterized in that the transistor circuit further comprises a second transistor and a third transistor, a second bias current means and a compensation capacitor, a control electrode of the second transistor being coupled to the input terminal, the second bias current means being coupled to a first main electrode of the second transistor for supplying a second bias current to the second transistor, the third transistor having a first main electrode coupled to the first bias current means, a second main electrode coupled to the first main electrode of the first transistor and a control electrode coupled to receive a bias voltage. Since the control electrode of the second transistor receives the same input signal as me first transistor, a current with similar distortion components flows in the com¬ pensation capacitor, which current is added to the output current via die main current path of me third transistor. This compensation scheme is applicable to bipolar and unipolar transis¬ tors. In order to reduce no only me odd harmonic distortion but also the even harmonic distortion an embodiment of the transistor circuit according to the invention is characterized in diat the transistor circuit further comprises a further input terminal, a further output terminal and a fourth transistor, the fourth transistor having a control electrode coupled to the further input terminal and first main electrode coupled to the further ouφut terminal and to a second main electrode of the second transistor. This embodiment is fully balanced and has a differential topology with minimal power consumption because the current through the second transistor also flows through the fourth transistor. Depending on the transistor technology, particularly for bipolar transistors, this embodiment may be furdier characterized in iat me control electrode of the second transistor is coupled to me input terminal via a first level shifting circuit and me control electrode of die third transistor is coupled to the further input terminal via a second level shifting circuit. The level shifting circuits provide proper bias and/or extra signal excursion range for the transistors. A useful and simple implementation of me level shifting circuits is provided in a further embodiment of me transistor circuit according to the invention which is characterized in that the first level shifting circuit comprises a fifth transistor and a third bias current means, the fifth transistor having a control electrode coupled to die input terminal and a first main electrode coupled to the control electrode of the second transistor, the third bias current means being coupled to me first main electrode of the fifth transistor for supplying a third bias current to d e fifth transistor, and the second level shifting circuit comprises a sixth transistor and a fourth bias current means, the sixth transistor having a control electrode coupled to the further input terminal and a first main electrode coupled to the control electrode of me third transistor, e fourth bias current means being coupled to the first main electrode of the sixth transistor for supplying a fourth bias current to the sixth transistor. The above and other features and advantages of me invention will be apparent from the following description of exemplary embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 shows a conventional bipolar follower circuit; Figure 2 shows a bipolar implementation of a follower circuit according to the invention; Figure 3 shows a unipolar implementation of a follower circuit according to the invention; Figure 4 shows a differential bipolar implementation of a follower circuit according to me invention; and Figure 5 shows a differential bipolar implementation of a follower circuit according to the invention. Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items. Fig. 1 shows a bipolar implementation of a capacitively loaded conventional follower circuit. The circuit comprises an NPN transistor 2 in emitter-follower configuration. The control electrode or base of the transistor 2 is coupled to an input terminal 4 and receives an input signal V j supplied to the input terminal 4. The first main electrode or emitter of transistor 2 is coupled to an ouφut terminal 6 which is loaded with a load capacitor 8. The second main electrode or collector of transistor 2 is coupled to a source of positive supply voltage 10. A bias current source 12 is coupled between the emitter of transistor 2 and ground and supplies a bias current I 0 to transistor 2. The ouφut signal v 0 across the load capacitor 8 can be expressed as a function of the input signal V j and a modulation index m* of the emitter follower bias current I 0 : (1) v o = v ,- " V be = v i - V BE0 " V l +m In this expression m, is defined as i o /I 0 , i 0 being the signal current flowing into the load capacitor 8; V be is the base-emitter voltage of transistor 2; V BE0 is the steady state portion of V be and V τ is the well known thermal voltage kT/q. The non-linear term V j lnO +m ] ) pre¬ sent in equation (1) can be written as: (2) V τ ln(l *m l ) ' V τ in, - The ouφut signal v 0 can accordingly be written as a DC shifted version of the input signal V j plus a series of even harmonics and a series of odd harmonics. The even harmonics can be suppressed by using a differential or balanced topology, but the odd harmonics still remain present in d e ouφut signal. Fig. 2 shows a follower according to the invention in which a capacitive compensation technique is used to suppress me odd harmonics in the ouφut signal of the follower of Fig. 1. For this purpose an NPN transistor 14 is inserted between the emitter of transistor 2 and bias current source 12. The emitter, collector and base of transistor 14 are coupled to, respectively, me bias current source 12, the emitter of transistor 2 and a terminal 16 for connecting a bias voltage source. The circuit furdier comprises an NPN transistor 18, just like transistor 2 operating in emitter-follower configuration. The base of transistor 18 is coupled to die input terminal 4 and receives me input signal V; supplied to the input terminal 4 in a fashion similar to transistor 2. The emitter of transistor 18 is coupled to the emitter of transistor 14 via a compensation capacitor 20. The collector of transistor 18 is coupled to die source of positive supply voltage 10. A bias current source 22, similar to bias current source 12, is coupled between the emitter of transistor 18 and ground and supplies a bias current I 0 to transistor 18. The purpose of me transistors 14 and 18 and the compensation capacitor 20 is to supply the emitter follower transistor 2 with a bias current which compensates for me current causing the odd harmonic components in die ouφut signal v 0 . The voltage v c across the compensation capacitor 20 can be expressed as a function of d e input signal V j and the modulation index m 2 of the transistors 14 and 18: In mis expression m 2 is defined as I Q /I Q , \ Q being me signal current flowing through the compensation capacitor 20; v c is me signal voltage across die compensation capacitor 20; and ΔV be is die difference between the base-emitter voltages of the transistors 18 and 14. The non-linear term in me signal v c can be written as: The voltage v c across the compensation capacitor 20 mus equals a shifted version of the input voltage V j plus a series of odd harmonic terms. At equal modulation indices (m. = m 2 ) the magnitude of d e odd harmonic terms in signal current i c equals twice the magnitude of die odd harmonics in signal current i 0 generated by the emitter follower transistor 2 if the capacitance C c of die compensation capacitor 20 and the capacitance C L of the load capacitor 8 are equal. As a result the odd harmonics will cancel when me current Ϊ Q flowing dirough the compensation capacitor 20 equals half the current i 0 through the load capacitor 8. Cancellation of the odd harmonics is obtained at a capacitor ratio C C /C L = 0.5. It is to be noted d at die same effect can be obtained widi other capacitor ratios by scaling the emitter areas of me transistors 14 and/or 18 in respect of the emitter area of transistor 2, and/or by selecting different bias currents for the bias current sources 12 and 22. It is further noted that a reduction of odd harmonics is also effected if the cancellation is not perfect, for instance due to small mismatches between the transistors, parasitic capaci¬ tances, etc. Instead of bipolar transistors transistors of other technologies may be used as shown in Fig. 3. In case of unipolar (MOSFET) transistors d e control electrode, first main electrode and second main electrode of a transistor correspond to, respectively, the gate, source and drain of a unipolar transistor. The general theory of the compensation scheme is applicable as well, but the equations (1) to (4) should be adapted to the specific charac- teristics of the transistors. If so desired the bias current sources can be replaced with resistors or any o ier biassing means, although this might be accompanied with a reduced cancellation of odd harmonics. Fig. 4 shows a differential or balanced version of the bipolar implementation of the follower according to die invention. This version has differential input and differential ouφut terminals and provides a differential ouφut signal with reduced even and odd harmonic distortion. The collector of transistor 18 is coupled to the emitter of an NPN transistor 24, me collector of which is coupled to the source of positive supply voltage 10. The emitter of transistor 24 is coupled to a further ouφut terminal 24 which is loaded with a further load capacitor 28. The base of transistor 24 is coupled to a further input terminal 30 and receives a complementary input signal -V j . The base of transistor 18 is coupled to the input terminal 4 via a first level shifting circuit 32 and the base of transistor 14 is coupled to the further input terminal 30 via a second level shifting circuit 34. This arrangement implies that die further input terminal 30 replaces me terminal 16 shown in Fig. 2 and provides both a bias voltage and a complementary input voltage to the base of transistor 16. The level shifting circuits 32 and 34 provide proper bias for die transistors, but may be omitted if the transistor technology allows this. Fig. 5 shows a bipolar differential version in which the level shifting circuits are presented in more detail. The first level shifting circuit 32 comprises an emitter follower transistor 38, which has the base coupled to me input terminal 4, the collector coupled to the source of positive supply voltage 10 and me emitter coupled to the base of transistor 18 via an optional diode 40. A bias current source 42 is coupled to die emitter of transistor 38 via the optional diode 40. Similarly, die second level shifting circuit 34 comprises an emitter follower transistor 44, which has the base coupled to me furdier input terminal 30, the collector coupled to die source of positive supply voltage 10 and the emitter coupled to the base of transistor 14 via an optional diode 46 and a bias current source 48 is coupled to the emitter of transistor 4 via me optional diode 46. The diodes 40 and 46 provide more collector signal range to the transistors 14 and 18, but may be omitted if such range is not needed. The level shifting transistors 38 and 44 hardly introduce extra distortion because diese transistors are not capacitively loaded. The circuits shown in Figs. 2 to 5 are suitable for use as a single ended or differential buffer for driving capacitive loads, for example in sampling circuits, e.g. Track and Hold Circuits or Sample and Hold Circuits, line drivers, etc. As already demonstrated in Fig. 3, the circuits may be implemented in any transistor technology, for instance in bipolar or MOS technology. The transistors shown may also be compound transistors, such as Darlington transistors or NPN/PNP combinations or compound transistors of mixed technology. In this respect the transistors 18 and 38 and the transistors 44 and 14 in me circuit of Fig. 5 can be considered as compound transistors as well and be replaced by compound transistors, if desired. Also transistors of reversed conductivity may be used. In d at case the polarity of the supply voltage should be reversed as well.

Claims: Claims 1. A transistor circuit comprising an input terminal (4) for receiving an input signal, an ouφut terminal (6) for providing a buffered ouφut signal in response to the input signal, a first transistor (2) having a control electrode coupled to the input terminal (4), a first main electrode coupled to die ouφut terminal (6) and a second main electrode, and a first bias current means (12) coupled to me first main electrode for supplying a first bias current to me first transistor (2), characterized in that d e transistor circuit further comprises a second transistor (18) and a third transistor (14), a second bias current means (22) and a compensation capacitor (20), a control electrode of me second transistor (18) being coupled to the input terminal (4), the second bias current means (22) being coupled to a first main electrode of me second transistor (18) for supplying a second bias current to the second tran¬ sistor (18), me third transistor (14) having a first main electrode coupled to me first bias cur¬ rent means (12), a second main electrode coupled to the first main electrode of the first transistor (2) and a control electrode coupled to receive a bias voltage. 2. A transistor circuit as claimed in Claim 1 , characterized in that the transistor circuit further comprises a further input terminal (30), a furdier ouφut terminal (26) and a fourth transistor (24), the fourth transistor (24) having a control electrode coupled to the further input terminal (30) and first main electrode coupled to the furdier ouφut terminal (26) and to a second main electrode of the second transistor (18). 3. A transistor circuit as claimed in Claim 2, characterized in that the control electrode of die second transistor (18) is coupled to the input terminal (4) via a first level shifting circuit (32) and die control electrode of die diird transistor (14) is coupled to the further input terminal (30) via a second level shifting circuit (34). 4. A transistor circuit as claimed in Claim 3, characterized in that the first level shifting circuit (32) comprises a fifth transistor (38) and a third bias current means (42), the fifth transistor (38) having a control electrode coupled to die input terminal (4) and a first main electrode coupled to the control electrode of d e second transistor (18), the third bias current means (42) being coupled to the first main electrode of the fifth transistor (38) for supplying a third bias current to the fifth transistor (38), and the second level shifting circuit (34) comprises a sixth transistor (44) and a fourth bias current means (48), the sixth transistor (44) having a control electrode coupled to the furdier input terminal (30) and a first main electrode coupled to d e control electrode of die third transistor (14), the fourth bias current means (48) being coupled to the first main electrode of the six transistor (44) for supplying a fourth bias current to the sixth transistor (44).

Inventors: VORENKAMP PIETER, VORENKAMP, PIETER
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1997
Main classification: H03K19
IPC codes: H03F1, H03F3