An integrated device for switching systems with filtered reference quantities

Abstract: An integrated device (105) for a switching system (100) comprises control means (110) for generating at least one switching control signal (Sh), reference means (120) for generating at least one reference quantity (Qref), means (110) for using the reference quantity (Qref), means (130) for storing the reference quantity (Qref), switch means (122) which, in a first operative condition, connect the reference means (120) to the using means (110) and to the storage means (130) in order to apply the reference quantity (Qref) thereto and, in a second operative condition, disconnect the reference means (120) from the using means (110) and connect the storage means (130) to the using means (110) in order to apply the stored reference quantity thereto, and filtering means (135) for keeping the switch means (122) in the second operative condition for a filtering period (Tf) in accordance with the switching of the control signal (Sh).

Description: The present invention relates to an integrated device for a switching system and, in particular, to an integrated device according to the preamble of the first claim. Switching systems comprising one or more electronic switches which are cut off and made conductive alternately are commonly used in various applications such as, for example, in supply units, in oscillators, in inverters, and the like. The switching of the electronic switches is controlled by means of a suitable device generally produced in integrated form in a single chip of semiconductor material. During each switching of the electronic switches, interference is generated and is propagated to the control device, for example, by means of a common supply, a substrate of the chip of semiconductor material, or because of capacitive coupling. This switching interference may alter the values of reference quantities (voltages or currents) used within the control device and may cause a malfunction of its internal circuits such as, for example, the activation of parasitic components which cause undesired switching; this problem is experienced in particular in systems with steeply sloping switching edges, for example, in high-voltage (power) switching systems or in low-voltage switching systems operating at a high frequency. Known control devices use solutions with extremely complex and expensive internal circuitry to prevent this problem. Filtering capacitors with high capacitances (of the order of some nF) are also generally provided, connected externally to the chip of semiconductor material in which the control device is formed; however, these external components increase the cost and size of the switching system. Moreover, document EP-A-0284357 discloses an integrated circuit having a data output buffer, wherein separate power source pads and separate reference pads are provided for the data output buffer and the circuit components. The object of the present invention is to overcome the aforementioned drawbacks. To achieve this object, an integrated device as described in the first claim is proposed. The integrated device according to the present invention is extremely simple; in particular, this solution enables the circuits which generate the reference quantities to be more compact so that the dimensions of the integrated device as a whole are kept smaller. Moreover, the structure of the present invention does not require a filtering capacitor outside the integrated device. Finally, this integrated device is extremely versatile and flexible and can easily be adapted to the most varied requirements of use. Further characteristics and advantages of the integrated device according to the present invention will become clear from the following description of various preferred embodiments thereof, given by way of non-limiting example, with reference to the appended drawings, in which: Figure 1a is a basic block diagram of a switching system comprising the integrated device of the present invention, Figure 1b shows, in a qualitative time graph, the variation of some electrical quantities of the system of Figure 1a, Figure 2a is a basic block diagram of a switching system comprising a different embodiment of the integrated device of the present invention, Figure 2b shows, in a qualitative time graph, the variation of some electrical quantities of the system of Figure 2a, Figures 3a and 3b show examples of partial circuit layouts of the integrated device of the present invention. With reference in particular to Figure 1a, this shows a switching system 100 which uses, as an electronic switch, an (N-channel), high-voltage, metal-oxide-silicon field-effect transistor (a MOSFET, or simply MOS) Mh. The transistor Mh has a source terminal connected to a reference terminal (earth) and a drain terminal connected to the first terminal of a load L the second terminal of which is connected to the positive terminal of a supply Vcc (the negative terminal of which is connected to the earth terminal); the drain terminal of the transistor Mh is also connected to an output terminal from which a signal Vout is obtained. The integrated device of the present invention can however also be used in different switching systems which include, for example, a low-voltage transistor, a different element as an electronic switch, or two or more switches. The transistor Mh is controlled by means of a device 105 produced in integrated form in a chip of semiconductor material; the transistor Mh is constituted by a discrete external component or is integrated in the same chip of semiconductor material. The control device 105, which is suitably connected to the supply terminal Vcc and to the earth terminal, includes a block 110 which is connected to a gate terminal of the transistor Mh and generates a switching control signal Sh for the transistor Mh. One or more reference quantities (currents or voltages) Qref, produced by a suitable block 120 are used by the control block 110 or by other circuit elements; the value of the reference quantity Qref is fixed or is programmable, for example, by means of suitable external components (typically resistors). The reference block 120 is connected by means of a switch 122 to the control block 110 and to a block 130 which can store or hold the reference quantity Qref; the storage block 130 preferably comprises a capacitor of limited capacitance (of the order of a few pF) or other charge-storage means. Alternatively, equivalent components are used and, in a closed condition, connect the reference block 120 to the control block 110 and to the storage block 130 and, in an open condition, disconnect the reference block 120 from the control block 110 and connect the storage block 130 to the control block 110. The switch 122 is controlled by means of a suitable filtering signal Sf generated by a block 135 which receives the control signal Sh as an input. The filtering signal Sf is preferably also supplied to a block 140 which performs service functions for the operation of the control device 105. In order to explain the operation of the system of Figure 1a, reference is made to the qualitative time graph of Figure 1b which shows the variation, with time (t), of the control signal Sh, of the output signal Vout, of the reference quantity Qref, and of the filtering signal Sf. When the control signal Sh has a low value (for example 0V relative to earth), the transistor Mh is cut off so that the output signal Vout adopts a value equal to the supply voltage Vcc; when the control signal Sh has a high value (for example, 5V), the transistor Mh is conductive so that the output signal Vout adopts a zero value. Upon each switching of the transistor Mh, the output signal Vout is subject to a transitory phenomenon of duration Tc which generates interference of equal duration in the reference quantity Qref. At the end of this transitory switching period, the reference signal Qref returns to its original value after a further transitory resetting period Tr. The inventors have recognized that the interference in the reference quantity Qref is present only during periods of time which start at a moment which is always known since it coincides with the switching of the control signal Sh; these interference periods have a duration Tn (equal to Tc+Tr in the example in question) which is dependent on the structure of the switching system. With reference again to Figure la, in the control device 105 according to the present invention, the switch 122 is normally kept closed so that the reference quantity Qref is applied to the control block 110; the same reference quantity Qref is simultaneously stored in the block 130. When the control signal Sh switches (and therefore during each of the interference periods Tn described above), the switch 122 is opened so that the control block 110 is supplied with the reference quantity stored in the block 130, which is not subject to the switching interference since the storage block 130 is disconnected from the block 120 by means of the switch 122 when this interference is present; the control block 110 thus in any case receives as an input a filtered reference quantity Qref' of substantially constant value. The filtering signal Sf preferably keeps the switch 122 open for a filtering period Tf (Figure 1b) the start of which coincides with the switching of the control signal Sh. The filtering period Tf has a duration depending on the duration of the interference period Tn, on the degree of precision required, and on the duration of the period in which the reference quantity Qref is used. In general, the filtering period Tf has a duration equal to or greater than the interference period Tn, of the order, for example, of a few µ s. Alternatively, the filtering period Tf has a shorter duration, for example, if very great precision is not required, or if the reference quantity Qref is used only for a short period of time. The duration of the filtering period Tf advantageously has a single value for all of the reference quantities Qref used in the control device 105 so as to simplify the structure of the control device 105, consequently reducing its size. Alternatively, filtering periods Tf of different durations are provided for each reference quantity Qref so as to ensure greater precision of the control device 105. In a preferred embodiment of the present invention, the filtering signal Sf is supplied to the service block 140 and is also used for carrying out different operations. For example, the block 140 may contain extinguishing circuitry which switches off the control device 105 when the supply voltage Vcc falls below a predetermined threshold value (under voltage lock-out) or when the temperature of the device exceeds a further threshold value. The operation of the extinguishing circuitry is disabled during the filtering periods Tf so that the switching interference cannot cause undesired switching-off of the control device 105; it should be noted that this solution involves no risk of damage to the control device 105 since it is not necessary for the speed of operation of the extinguishing circuitry to be very high. A different embodiment is constituted by an analog-digital conversion system; in this case, the sampling of the analog signal to be converted is disabled during the filtering periods Tf so as to perform the conversion only when switching interference is not present. A different embodiment of the present invention is illustrated in Figure 2a (the elements already shown in Figure la are identified by the same reference numerals or symbols) which shows a switching system 200 which uses, as electronic switches, two (N-channel), high-voltage MOS transistors Mh1 and Mh2 connected as a half-bridge. In particular, a drain terminal of the transistor Mhl is connected to the supply terminal Vcc and a source terminal of the transistor Mh2 is connected to the earth terminal; a source terminal of the transistor Mh1 and a drain terminal of the transistor Mh2 are connected to the first terminal of a load L1 (from which an output signal Vout1 is obtained), the second terminal of the load L1 being connected to the earth terminal. The transistors Mh1 and Mh2 are controlled by means of a device 205 (produced in integrated form in a chip of semiconductor material) , comprising a block 210 which is connected to a gate terminal of the transistors Mh1 and Mh2, and which generates two switching control signals Sh1 and Sh2 for the transistors Mh1 and Mh2, respectively. A block 250, which receives as inputs one or more filtered reference quantities Qref' and the control signal Sh2, generates a dead time signal Sd; this signal is used by the control block 210 to keep both of the transistors Mh1 and Mh2 cut off for a predetermined period Td (dead time) so as to prevent current peaks in these transistors during the switching stages. The dead time block 250 also generates a filtering signal Sf1 which is used, as in the previous embodiment, by the switch 122 and by the service block 140. This embodiment of the present invention is particularly advantageous since it enables the filtering signal Sf1 to be produced by a simple modification of a pre-existing circuit block inside of the integrated device so that the modified pre-existing circuit block performs also the function of the filtering block 135 of Fig. 1, without the need for a separate filtering block. In order to explain the operation of the system of Figure 2a, reference will be made to the qualitative time graph of Figure 2b which shows the variation, with time (t), of the control signals Sh1, Sh2, of the dead time signal Sd, of the output signal Vout1, of the reference quantity Qref, and of the filtering signal Sf1. Each switching of the control signal Sh2 from the high value (transistor Mh2 conducting) to the low value (transistor Mh2 cut off) is separated from the corresponding switching of the control signal Sh1 from the low value (transistor Mh1 cut off) to the high value (transistor Mh1 conducting) and vice versa, by the dead time Td. For each switching of the transistors Mhl and Mh2, the output signal Vout1 is subject to a transitory phenomenon of a duration equal to the sum of the dead time Td and a transitory switching period Tc1 after the dead time. This phenomenon generates, in the reference quantity Qref, interference of equal duration which disappears after a further transitory resetting period Tr1. In this embodiment, it is preferable to use a filtering period Tf1 the start of which coincides with the start of the dead time Td and the duration of which is, for example, equal to or greater than that of an interference period Tn1=Td+Tc1+Tr1. It should be noted that the reference quantity used to generate the dead time signal Sd provides a typical example of a case in which the reference quantity is used only for a short period of time; the filtering of the reference quantity is required only during the dead time Td so that the respective filtering period Tf1 will have a duration slightly greater than that of the dead time Td. With reference now to Figure 3a (the elements already shown in Figure 1a are identified by the same reference numerals or symbols) this shows an embodiment of a circuit layout for generating a reference voltage. The control device 105 includes a current mirror 305 (connected to the supply terminal Vcc) having a first branch connected to suitable known and conventional circuitry (not shown in the drawing) which generates a reference current Irefl, and a second branch connected to an external pin 310 of the chip in which the control device 105 is formed. The pin 310 is connected to the first terminal of an external resistor Rext1 the second terminal of which is connected to the earth terminal; between the pin 310 and the earth terminal there is also a parasitic capacitor Cp. The pin 310 is connected by means of the switch 122 (which is controlled by the filtering signal Sf) to the first terminal of an internal capacitor C1 the second terminal of which is connected to the earth terminal. The reference current Irefl is sent to the pin 310 by means of the current mirror 305 so that, at the terminals of the external resistor Rext1, there is a reference voltage Vref1=Iref1·Rext1, the value of which can be programmed by variation of the resistance of the external resistor Rextl. When the switch 122 is closed, the capacitor C1 is charged to the reference voltage Vref1 and, when the switch 122 is open, the capacitor C1 maintains this voltage value, regardless of switching interference in the reference voltage Vref1. There is therefore a filtered reference voltage Vref1' of substantially constant value at the terminals of the capacitor C1. It should be noted that, in this case, the transitory period for resetting the reference voltage Vref1 (Tr in Figure 1b) has a duration proportional to the product of the resistance of the external resistor Rext1 and the capacitance of the parasitic capacitor Cp. A different embodiment for generating a reference current is illustrated in Figure 3b (the elements already shown in Figure la are identified by the same reference numerals or symbols). The control device 105 includes an operational amplifier 330 which has a non-inverting input terminal (+) connected to suitable circuitry (not shown in the drawing) which generates a reference voltage Vref2, and an inverting input terminal (-) connected to an external pin 335. The pin 335 is connected to the first terminal of an external resistor Rext2 the second terminal of which is connected to the earth terminal. An (N-channel), low-voltage MOS transistor Mld has a source terminal connected to the pin 335, a gate terminal connected to an output terminal of the operational amplifier 330 and a drain terminal connected to a drain terminal of a (P-channel) low-voltage MOS transistor Ml1. The transistor Ml1 has a gate terminal connected to its own drain terminal and a source terminal connected to the supply terminal Vcc. The device 105 includes a further (P-channel) low-voltage MOS transistor Ml2 having a drain terminal, a gate terminal connected by means of the switch 122 to the gate terminal of the transistor Ml1, and a source terminal connected to the source terminal of the transistor Ml1. An internal capacitor C2 is also connected between the gate terminal and the source terminal of the transistor Ml2. The reference voltage Vref2 is applied to the pin 335 by means of the operational amplifier 330 which operates as an impedance separator (a buffer); a reference current (of programmable value) Iref2=Vref2/Rext2 thus flows in the resistor Rext2. When the switch 122 is closed, the reference current Iref2 passes through the transistor Mld (connected like a diode) and is sent by means of the current mirror formed by the transistors Ml1 and Ml2, to internal circuitry (not shown in the drawing). In this condition, the capacitor C2 is charged to a voltage Vgs equal to the voltage present between the gate terminal and the source terminal of the transistor Ml2. When the switch 122 is open the capacitor C2 keeps the gate-source voltage of the transistor Ml2 at the same value Vgs so that the current through the transistor Ml2 remains unchanged, regardless of the interference in the reference current Iref2. There is therefore a filtered reference current Iref2' of substantially constant value at the drain terminal of the transistor Ml2. Naturally, in order to satisfy contingent and specific requirements, an expert in the art may apply to the above-described integrated device many modifications and variations all of which, however, are included in the scope of protection of the invention as defined by the following claims.

Claims: An integrated device (105) comprising control means (110) for generating at least one switching control signal (Sh) to be applied to at least one electronic switch (Mh; Mh1, Mh2), reference means (120) for generating at least one reference quantity (Qref), and means (110; 210, 250) for using the reference quantity (Qref), characterized in that it includes means (130) for storing the reference quantity (Qref), switch means (122) which, in a first operative condition, connect the reference means (120) to the using means (110; 210, 250) and to the storage means (130) in order to apply the reference quantity (Qref) thereto and which, in a second operative condition, disconnect the reference means (120) from the using means (110; 210, 250) and connect the storage means (130) to the using means (110; 210, 250) in order to apply the stored reference quantity thereto, and filtering means (135) for keeping the switch means (122) in the second operative condition for a filtering period (Tf) in accordance with the switching of the control signal (Sh), the filtering period (Tf) having a duration at least equal to the duration of a period (Tn) in which there is switching interference in the reference quantity (Qref), or at least equal to the duration of a period of use (Td) of the reference quantity (Qref). An integrated device (105) according to Claim 1, in which the storage means (130) include at least one capacitor (C1; C2). An integrated device (105) according to Claim 1 or Claim 2, in which the control means (110) generate a single control signal (Sh), the filtering period (Tf) starting upon each switching of the control signal (Sh). An integrated device (205) according to Claim 1 or Claim 2, in which the control means (210) generate a first control signal (Sh1) and a second control signal (Sh2), and in which the integrated device (205) further includes means (250) for keeping the first control signal (Sh1) and the second control signal (Sh2) simultaneously at an opening value (0V) , upon each switching, for a dead time (Td) of predetermined duration, the filtering period (Tf1) starting at the beginning of the dead time (Td). An integrated device (105) according to any one of Claims 1 to 4, in which the reference means (120) generate a plurality of reference quantities (Qref), the filtering periods (Tf) corresponding to each reference quantity (Qref) being of equal duration. An integrated device (105) according to any one of Claims 1 to 5, further comprising means (140) for performing service operations, the service means (140) being connected to the filtering means (135) and being switched off during the filtering periods (Tf). An integrated device (105) according to any one of Claims 1 to 6, comprising means (305) for applying a reference current (Irefl) to an external pin (310) of the integrated device (105), the pin (310) being suitable for connection to a reference terminal by means of an external resistor (Rext1) in order to generate a reference voltage (Vref1), and an internal capacitor (C1) having a first terminal for connection to the reference terminal and a second terminal connected to the pin (310) by the switch means (122) so that the internal capacitor (C1) maintains, between the first and second terminals, a reference voltage (Vref1'), filtered of switching interference. An integrated device (105) according to any one of Claims 1 to 6, comprising means (330) for applying a reference voltage (Vref2) to an external pin (335) of the integrated device (105), the pin (335) being suitable for connection to a first supply terminal (0V) by means of an external resistor (Rext2) in order to generate a reference current (Iref2), means (Mld) for applying the reference current (Iref2) to a first terminal of a first transistor (Ml1) having a second terminal for connection to a second supply terminal (Vcc), and a control terminal connected to the first terminal of the first transistor (Ml1), a second transistor (Ml2) having a first terminal, a control terminal connected by the switch means (122) to the control terminal of the first transistor (Ml1), and a second terminal connected to the second terminal of the first transistor (Ml1), and an internal capacitor (C2) connected between the control terminal and the second terminal of the second transistor (Ml2) so that the second transistor (Ml2) maintains, at the first terminal, a reference current (Iref2'), filtered of switching interference. A switching system (100; 200) comprising the integrated device (105; 205) according to any one of Claims 1 to 8 and at least one electronic switch (Mh; Mh1, Mh2), each electronic switch (Mh; Mh1, Mh2) having a control terminal connected to the control means (110; 210) in order to receive a corresponding switching control signal (Sh; Sh1, Sh2).

Inventors: CANTONE GIUSEPPE, GARIBOLDI ROBERTO, GENOVA ANGELO, CANTONE, GIUSEPPE, GARIBOLDI, ROBERTO, GENOVA, ANGELO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1997
Main classification: G05F1
IPC codes: H03K17, H03K5, G05F3