NMOS negative charge pump

Abstract: A negative charge pump circuit comprises a plurality of charge pump stages (S1'-S4') connected in series to each other. Each stage has a stage input terminal (SI) and a stage output terminal (SO). A first stage (S1') has the stage input terminal (SI) connected to a reference voltage, a final stage (S4') has the stage output terminal (SO) operatively connected to an output terminal (O) of the charge pump at which a negative voltage is developed; intermediate stages (S2' ,S3') have the respective stage input terminal (SI) connected to the stage output terminal (SO) of a preceding stage and the respective stage output terminal connected to the stage input terminal of a following stage. Each stage (S1'-S4') comprises a first N-channel MOSFET (M1') with a first electrode connected to the stage input terminal (SI) and a second electrode connected to the stage output terminal (SO), a second N-channel MOSFET (M2') with a first electrode connected to the stage output terminal (SO) and a second electrode connected to a gate electrode of the first N-channel MOSFET (M1'), a boost capacitor (CP) with one terminal connected to the gate electrode of the first N-channel MOSFET and a second terminal driven by a respective first digital signal (A',C') switching between the reference voltage and a positive voltage supply (VDD), and a second capacitor (CL) with one terminal connected to the charge pump stage output terminal (SO) and a second terminal connected to a respective second digital signal (B',D') switching between the reference voltage and the voltage supply (VDD). A gate electrode of the second N-channel MOSFET (M2') is connected, in the first stage (S1'), to a third digital signal (D') switching between the reference voltage and the voltage supply, while in the remaining stage the gate electrode of the second N-channel MOSFET is connected to the stage input terminal (SI).

Description: The present invention relates to an NMOS negative charge pump, particularly for the integration in CMOS non-volatile memory devices. In the field of integrated circuits, particularly in non-volatile memory devices, it is often necessary to generate on-chip negative voltages starting from the positive voltage supply (VDD) which supplies the integrated circuit. This is for example the case of EEPROMs and Flash EEPROMs, wherein a negative voltage is necessary for the erase operation of the memory cells. Conventionally, negative voltages are generated on-chip by means of negative charge pumps using P-channel MOSFETs, of the type shown in Figure 1. With reference to this figure, it is possible to see that the negative charge pump is composed of several stages S1-S4 (four in this example), connected in series between ground and an output terminal 0 of the charge pump at which a negative voltage is provided. Each stage S1-S4 comprises a P-channel pass transistor M1, a P-channel pre-charge transistor M2, a charge storage capacitor CL driven by a respective first digital signal B or D periodically switching between ground and the voltage supply VDD, and a boost capacitor CP driven by a respective second digital signal A or C substantially in phase opposition with respect to signal B or D; the simplified timing of signals A, B, C and D is depicted in Figure 2. In operation, a positive charge flow takes place from the storage capacitor CL of a given stage to the storage capacitor CL of the adjacent, lefthand stage in Figure 1, through the pass transistors M1, so that the output terminal 0 acquires a negative potential. The pre-charge transistor M2 pre-charges the boost capacitor CP, which in turn boosts the gate voltage of M1 so as to allow a most efficient charge transfer to take place. When the negative charge pump is integrated in a CMOS integrated circuit, the P-channel MOSFETs are conventionally formed inside respective N-type wells which are in turn formed inside a common P-type semiconductor substrate. The main drawbacks of the circuit described above will be now discussed. First, due to the body effect affecting MOS transistors, a progressive increase in the threshold voltage of the P-channel MOSFETs takes place moving from the stages near to the terminal of the charge pump connected to ground to the stages proximate to the output terminal 0. In fact, the N-type wells wherein the P-channel MOSFETs are formed cannot be biased at negative voltages (otherwise the N-type well/P-type substrate junction becomes forward biased), while the source and drain electrodes of the P-channel MOSFETs are biased at more and more negative potentials. This reduces efficiency of the charge pump, because the voltage gain of each stage decreases; this reflects on a higher number of stages being necessary for generating a given negative voltage. Furthermore, the body effect limits the negative voltage value that can be generated, because when the body effect is so high that the threshold voltage of the P-channel MOSFETs reaches the value of the voltage supply VDD, even if more stages are added to the charge pump the negative output voltage cannot increase further (in absolute value). Second, P-channel MOSFETs are intrinsically slower than N-channel MOSFETs, so that the maximum operating frequency of the charge pump is limited; this has a negative impact on the output current capability of the charge pump. Third, the charge pump structure shown in Figure 1 has a poor reliability; in fact, when the pass transistors M1 are off, the voltage applied to their gate oxide is equal to the difference between their gate voltage and the bias voltage of the N-type weLLs inside which the transistors are formed; the gate voltage can go strongly negative (especially in the final stages of the charge pump), but the bias voltage of the N-type wells cannot be lower than 0 V (to prevent forward biasing of the N-type wells/P-type substrate junctions). Fourth, conventional CMOS manufacturing process could easily provide N-channel MOSFETs which are more resistant to junction breakdown than their P-channel counterparts; in this case, the reliability of the charge pump would be further reduced. 8107 IEEE Journal of Solid-State Circuits, New York, US, vol. 27, No. 11, November 1992, "A 5V-only operation 0.6µm Flash EEPROM with Row Decode Scheme in Triple-Well structure", pages 1540-1545, Umezawa et al. discloses a negative charge pump according to preamble of claim 1. In view of the state of the art described, it is an object of the present invention to provide a negative charge pump which is not affected by the abovementioned problems. According to the present invention, such object is attained by means of negative charge pump as defined in claim 1. The features and advantages of the present invention will be made apparent by the following detailed description of two particular embodiments thereof, illustrated as non-limiting examples in the annexed drawings, wherein: Figure 1 is a circuit diagram of a negative charge pump according to the prior art; Figure 2 is a simplified time diagram of drive signals for the charge pump of Figure 1; Figure 3 shows in cross-sectional view the structure of an N-channel MOSFET for use in a negative charge pump according to the present invention; Figure 4 is a circuit diagram of a first embodiment of a negative charge pump according to the present invention, which makes use of N-channel MOSFETs with the structure shown in Figure 3; Figure 5 is a time diagram of drive signals for the charge pump of Figure 4; Figure 6 is a circuit diagram of a negative charge pump according to a second embodiment of the present invention; Figure 7 shows in cross-sectional view the structure of a junction diode for use in the charge pump of Figure 6; and Figure 8 shows in cross-sectional view the structure of a capacitor for use in the charge pump of Figure 6. Figure 1 shows the circuit structure of a negative charge pump according to the prior art, using P-channel MOSFETs; Figure 2 shows the simplified time evolution of the drive signals of the charge pump of Figure 1. This conventional kind of negative charge pump has already been discussed in the foregoing, and the drawbacks thereof have been appointed. Figure 3 is a cross-sectional view of an N-channel MOSFET which is used in the negative charge pump according to the present invention. Inside a P type substrate P 1 (which forms the common substrate of the integrated circuit wherein the negative charge pump is integrated), an N type well 2 is formed; inside the N type well 2, an N+ contact region 4 for biasing the N type well 2 and a P type well 3 are formed; inside the P type well 3, a P+ contact region 5 for biasing the P type well 3 and N+ source/drain regions 6 of the N-channel MOSFET are formed; over the P type well 3, between the source/drain regions 6, an insulated gate 7 is formed. The device has five terminals: two source/drain terminals S/D, a gate terminal GA, a bulk terminal BU and an N well bias terminal NW. The device is functionally equivalent to an N-channel MOSFET with a diode DI inserted between terminals BU and NW. Thanks to this structure, which can be realized using a triple-well CMOS manufacturing process, it is possible to bias the P type well 3 wherein the N-channel MOSFET is formed at a potential different from that of the P type substrate 1, which is normally kept grounded. In Figure 4 a circuit diagram of a first embodiment of the present invention is shown. The negative charge pump comprises a plurality of stages S1'-S4' (four in the shown example) connected in series between ground and a decoupling stage SOUT, the output thereof being an output terminal 0 of the charge pump at which a negative voltage is provided. Each stage has a stage input terminal SI (SOI) and a stage output terminal SO (SOO); the stage input terminal of the first stage S1' is connected to ground; the stage output terminal of the last stage S4' is connected to the input terminal SOI of the decoupling stage SOUT; the stage output terminal SOO of the Latter is connected to the output terminal 0; in the intermediate stages, the stage input terminal SI is connected to the stage output terminal of the preceding stage. Each stage S1'-S4' comprises an N-channel pass transistor M1' and an N-channel pre-charge transistor M2', both having the structure shown in Figure 3, a storage capacitor CL and a boost capacitor CP. The pre-charge transistor M2' has source/drain terminals connected to the control gate of the pass transistor M1' and to a stage output terminal SO; in the first stage S1', the control gate of the pre-charge transistor M2' is driven by a digital signal D' (to be described hereinafter), while in all the other stages the control gate of M2' is connected to the stage input terminal SI. In each stage the boost capacitor CP has one plate driven by a respective digital signal A' or C', and the storage capacitor CL has one plate driven by another respective digital signal B' or D'. The timing of signals A', B', C' and D' is shown in Figure 5; all these four signals are digital signals periodically switching between ground and a positive voltage supply VDD, which is the supply voltage of the integrated circuit wherein the charge pump is integrated. The charge pump also comprises a bias voltage generator 8 which generates three bias voltages E, F and G; bias voltage E is used for biasing the bulk terminal BU of transistors M1' and M2' in the first stage S1'; bias voltage F is used for biasing the bulk terminal BU of transistors M1' and M2' in the second stage S2'; and bias voltage G is used for biasing the bulk terminal BU of transistors M1' and M2' in the third stage S3'. The bulk terminal BU of transistors M1' and M2' in the last stage S4' is instead connected directly to the output terminal O of the charge pump. The decoupling stage SOUT is similar to the other stages S1'-S4', comprising N-channel MOSFETs M7 and M8 and a boost capacitor C3 driven by signal A'. The bulk terminal BU of MOSFETs M7 and M8 is connected to the output terminal O of the charge pump. The bias voltage generator 8 comprises a voltage divider formed by four diode-connected N-channel MOSFETs M3-M6, having the structure shown in Figure 3, connected in series between the output terminal 0 of the charge pump and ground. Bias voltages E, F and G are derived from respective intermediate nodes between MOSFETs M3 and M4, M4 and M5 and M5 and M6; thus, voltages E, F and G are progressively more negative. The bulk terminals BU of MOSFETs M3-M6 are short-circuited to the respective source terminals of the transistors. The N-well terminals NW of MOSFETs M1' and M2' of the stages of the charge pump, as well as the N-well terminals of the MOSFETs M3-M6 of the bias voltage generator 8, could be directly connected to the positive voltage supply VDD. In this way, it would be assured that the junctions between the N type wells 2 and the P type substrate 1 are reverse biased and that the P type wells 3 wherein the MOSFETs are formed are electrically isolated from the substrate. However, it is preferable that the N-type well terminals NW of the MOSFETs whose P-type well is biased at negative voltages which are rather high in absolute value are biased at ground, to reduce electrical stresses. To this purpose, the N-type well terminals NW of MOSFETs M1', M2'; M7 and M8 in stages S2' to S4' and SOUT, and the N-type well terminals NW of MOSFETs M4 and M3 in the bias voltage generator 8 are connected to a voltage VB which is switchable between the voltage supply VDD and ground. In operation, voltage VB will be kept at VDD as long as the output voltage 0 is low in absolute value, and is then switched to ground when the negative voltage 0 becomes high (in absolute value). The operation of the circuit is the following. When signal D' switches from "0" to "1" (i.e., from gound to VDD), the potential of the output terminal SO of stage S4' raises. Since signal B' is still at VDD, the potential of the output node SO of stage S3' is high, so that M2' in stage S4' is on; CP can thus charge (signal C' is still at ground). When signal B' switches from VDD to ground, M2' in stage S4' turns off; when signal C' switches to VDD, the gate voltage of M1' in stage S4' is boosted to a high value, and the potentials of the stage output terminal SO of stage S4' and of the stage output terminal SO of stage S3' are equalized by means of charge transfer from capacitor CL in stage S4' to capacitor CL in stage S3'. Then, M1' in stage S4' is turned off by switching of signal C' from VDD to ground. In this way, a positive charge has been transferred from capacitor CL in stage S4' to capacitor CL in stage S3'. In a similar way, a transfer of positive charge takes place from capacitor CL in one stage to capacitor CL in the lefthand adjacent stage, and finally to ground, so that the stage output terminal SO of the stage S4' acquires a negative potential. Stage SOUT decouples the output terminal 0 from the stage output terminal SO of stage S4'; the potential of node 0 will be approximately constant not affected by ripples present at the output SO of stage S4'. It is to be observed that signals A', B', C' and D' are properly disoverlapped. In fact, signal C' cannot switch from ground to VDD before signal B' has switched from VDD to ground and signal D' has switched from ground to VDD; this is necessary to prevent a positive charge flow taking place from the lefthand to the righthand stages of the charge pump; for similar reasons, signal C' must switch to ground before signal B' has switched to VDD and signal D' has switched to ground. The arrangement shown in Figure 4 allows to minimize the influence of body effect on the threshold voltages of the N-channel MOSFETs; thanks to the particular biasing scheme of the P-type wells 3 of the N-channel MOSFETs, it is assured that the P-type well of a given MOSFET is biased at the minimum among the source and drain voltages of the MOSFET; this is the best biasing condition, because the body effect is thus minimized. The number of elements of the voltage divider of the bias voltage generator 8 must be equal to the number of stages of the charge pump. Figure 6 is a circuit diagram of a second embodiment of the present invention. The differences from the structure shown in Figure 4 are the following. In each of the first three stages S1', S2' and S3' of the charge pump, a respective junction diode D1 is provided having anode connected to the output terminal SO of the respective stage and cathode connected to ground. In the last stage S4' and in the decoupling stage SOUT, a respective diode D2 is provided having anode connected to the output terminal SO, SOO of the stage and cathode connected to the input terminal SI, SOI of the stage. The provision of diodes D1 and D2 has the advantage that the internal nodes of the charge pump start from an initial potential equal to the threshold voltage of a PN junction, instead of from a higher voltage. In this way, the charge pump can reach the steady-state quicklier. Preferably, diodes D1 and D2 have the structure shown in Figure 7, comprising an N-type well 10 formed inside the P-type substrate 1, wherein an N+ contact region 11 and a P-type well 12 are formed. Inside the P-type well 12, a P+ region 13 and an N+ region 14 are formed. Region 11 provides a bias terminal for the N-type well 10; regions 13 and 14 respectively form the anode AN and cathode KA electrodes of the diode. Junction diodes are preferred over P-channel MOSFETs because they are more reliable because junction diodes are not subject to oxide damages, and have a higher breakdown voltage. For these reasons, junction diodes can be directly connected between the internal nodes of the charge pump and ground (at least in the first stages of the pump), instead of between one stage and the following (as for example D2 in S4' and SOUT); thanks to this, the stages of the charge pump start from a voltage VT (threshold voltage of a PN junction) instead of higher voltages, and the charge pump reaches steady-state conditions faster. Figure 8 shows the structure of a PMOS-type capacitor used for the practical realization of capacitors CP and CL of the stages of the charge pump. In the P-type substrate 1, an N-type well 15 is formed; inside the N-type well 15, an N+ contact region 16 is formed for providing a bulk biasing terminal BUC, and two P+ regions 17 are also formed; over the surface of the N-type well 15 an insulated gate 18 is formed. The insulated gate forms one terminal of the capacitor, while the other terminal is formed by regions 17 and 16. By connecting the terminals BUC and 17 of the capacitors to the respective digital signal A', B', C' or D' which drives one of the terminals of the capacitors, the capacitor can work also in the accumulation region. This kind of connection of the capacitors has two advantages: first, non diodes or start-up circuits are necessary for turning the capacitors on; second, and related to the first, the pump start-up is faster, because it is not necessary to wait for turning of the capacitors on.

Claims: Negative charge pump circuit comprising a plurality of charge pump stages (S1'-S4') connected in series to each other, each stage having a stage input terminal (SI) and a stage output terminal (SO), said plurality of stages comprising a first stage (S1') having the respective stage input terminal (SI) connected to a reference voltage, a final stage (S4') having the respective stage output terminal (SO) operatively connected to an output terminal (O) of the charge pump at which a negative voltage is developed, and a plurality of intermediate stages (S2' ,S3') each having the respective stage input terminal (SI) connected to the stage output terminal (SO) of a preceding stage and the respective stage output terminal (SO) connected to the stage input terminal (SI) of a following stage, each charge pump stage (S1'-S4') comprising a first MOSFET (M1') with a first electrode connected to the stage input terminal (SI) and a second electrode connected to the stage output terminal (SO), a second MOSFET (M2') with a first electrode connected to the stage output terminal (SO) and a second electrode connected to a gate electrode of the first MOSFET (M1'), a boost capacitor (CP) with one terminal connected to the gate electrode of the first MOSFET and a second terminal driven by a respective first digital signal (A',C') switching between the reference voltage and a positive voltage supply (VDD), and a second capacitor (CL) with one terminal connected to the charge pump stage output terminal (SO) and a second terminal connected to a respective second digital signal (B',D') switching between the reference voltage and the voltage supply (VDD) the charge pump comprising means for providing the second digital signal substantially in phase opposition to the first digital signal (A', C'), characterized in that the first (M1') and the second (M2') MOSFETs are N-channel MOSFETs, a gate electrode of the second N-channel MOSFET (M2') being connected, in the first stage (S'), to a third digital signal (D') switching between the reference voltage and the voltage supply, a gate electrode of the second N-channel MOSFET, in all the stages other than said first stage (S 1'), being connected to the stage input terminal (SI), the N-channel MOSFETs having bulk electrodes (BU), the negative charge pump comprising a decoupling stage (SOUT) formed by N-channel MOSFETs and which have an input terminal (SOI) connected to the stage output terminal (SO) of said final stage, and an output terminal (SOO) connected to the output terminal of the charge pump, the charge pump comprising also a bias voltage generator (8), which generates bias voltages (E, F, G) to the bulk electrodes (BU) of the first (S1'), second (S2') and third (S3') stage of the negative charge pump, the bulk electrodes of the fourth stage (S4') and of the decoupling stage (SOUT) being biased by the output voltage. Negative charge pump according to claim 1, characterized in that said third digital signal (D') coincides with the second digital signal of a second stage (S2') having the stage input terminal (SI) connected to the stage output terminals (SO) of said first stage (S1'). Negative charge pump according to claim 2, characterized in that said decoupling stage (SOUT) comprises a third N-channel MOSFET (M7) with a first and a second electrodes respectively connected to the input (SOI) and output (SOO) terminals of the decoupling stage, a fourth N-channel MOSFET (M8) with a first and a second electrodes respectively connected to a gate electrode of the third N-channel MOSFET and to the output terminal (SOO) of the decoupling stage, and a third capacitor (C3) with one terminal connected to the gate electrode of the third N-channel MOSFET (M7) and a second terminal driven by a respective digital signal (A') switching periodically between the reference voltage and the voltage supply (VDD). Negative charge pump according to claim 3, characterized in that said bias voltages (E,F,G) for the stages become progressively more negative in going from the first stage (S1') towards the third stage (S3'). Negative charge pump according to claim 4, characterized iin that said bias voltage generator (8) generates said bias voltages (E,F,G) starting from the voltage of the output terminal (0) of the charge pump. Negative charge pump according to claim 5, characterized in that said bias voltage generator (8) comprises a voltage divider connected between the output terminal (O) of the charge pump and the rererence voltage, the voltage divider having a number of intermediate nodes directly proportional to the number of stages of the charge pump. Negative voltage pump according to claim 6, characterized in that said voltage divider comprises a series connection of diode-connected N-channel MOSFETs (M3-M6), said intermediate nodes being common nodes of adjacent diode-connected MOSFETs. Negative charge pump according to claim 7, characterized in that each of said first, second, third and fourth N-channel MOSFETs (M1',M2',M7,M8) comprises an N-type well (2) formed in a P-type substrate (1), a P-type well (3) formed inside the N-type well (2), and N-type source/drain regions (6) formed inside the P-type weLL (3). Negative charge pump according to claim 8, characterized in that the first stage (S1'), the second stage (S2') and the third stage (S3') comprise a respective junction diode (D1) having anode connected to the stage output terminal (SO) and cathode connected to the reference voltage. Negative charge pump according to claim 9, characterized in that in each of said N-type wells (2) an N-type well contact region (4) is formed. Negative charge pump according to claim 10, characterized in that the well contact regions (4) of the first and second MOSFETs (M1',M2') of the first stage are electrically connected to the voltage supply, while the well contact regions (4) of the first and second MOSFETs (M1',M2') of the remaining stages (S2'-S4') and of the third and fourth MOSFETs (M7,M8) of the decoupling stage (SOUT) are connected to a switchable potential which is switchable between the voltage supply (VDD) and the reference voltage. Negative charge pump according to claim 11, characterized in that each stage of a second sub-plurality of stages (S4') proximate to the output terminal (0) and the decoupling stage (SOUT) comprise a respective junction diode (D2) with anode connected to the stage output terminal (SO, SOO) and cathode connected to the stage input terminal (SI, SOI). Negative charge pump according to claim 12, characterized by comprising means for providing the first and second digital signals supplying a given stage substantially in phase opposition respectively to the first and second digital signals supplying the adjacent stages. Negative charge pump according to claim 13, characterized by comprising means for providing disoverlapped first and second digital signals supplying each stage, so that the second terminal of the second capacitor (CL) is driven to the reference voltage after that the second terminal of the boost capacitor (CP) has been driven to the reference voltage, and the second terminal of the second capacitor (CL) is driven back to the supply voltage before the second terminal of the boost capacitor (CP) is driven back to the supply voltage. Negative charge pump according to claim 14, characterized by comprising means for providing disoverlapped first digital signals supplying two adjacent stages, so that the second terminal of the boost capacitor (CP) in each stage is driven to the supply voltage after that the second terminal of the boost capacitors (CP) in the adjacent stages has been driven to the reference voltage, and after that the second terminal of the second capacitor in the adjacent stages has been driven to the reference voltage, and the second terminal of the boost capacitor (CP) in each stage is driven back to the reference voltage before the second terminal of the boost capacitors (CP) in the adjacent stages is driven back to the supply voltage and before the second terminal of the second capacitor (CL) in the adjacent stages is driven back to the supply voltage. Negative charge pump according to claim 15, characterized by comprising means for providing that in each stage the second digital signal switches from the supply voltage to the reference voltage after the second digital signal in the adjacent stages has switched from the reference voltage to the supply voltage and before the first digital signal in the adjacent stages switches from the reference voltage to the supply voltage and said second digital signal in each stage switches from the reference voltage to the supply voltage after the first digital signal in the adjacent stages has switched from the supply voltage to the reference voltage and before the second digital signal in the adjacent stages switches from the supply voltage to the reference voltage. Negative charge pump according to claim 16, characterized in that each one of said boost capacitor (CP), second capacitor (CL) and third capacitor (C3) is formed by an N-type well (15) formed in said P-type substrate (1) and by at least one P-type region (17) formed in said N-type well (15), a first terminal of the capacitor being formed by said P-type region (17) short-circuited to said N-type well (15), a second terminal of the capacitor being formed by a conductive gate (18) insulatively disposed over said N-type well (15).

Inventors: BRANCHETTI MAURIZIO, GHILARDELLI ANDREA, MULATTI JACOPO, BRANCHETTI, MAURIZIO, GHILARDELLI, ANDREA, MULATTI, JACOPO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1997
Main classification: H02M3
IPC codes: H02M3