A sort processor and a sort processing device

Abstract: [Object] Present invention provides a sort processor which gives a high performance of the sorting process and a high density of the sort processor in the semiconductor integrated circuit. [Means for solving problems] The invention comprises a data storage device for storing input data strings; a comparator having K + 1 input ports for inputting comparison object data of continuous K sets (K: integral number larger than or equal 2) of the data strings for comparing data from K ports; and a controller for selecting the input port which is inputted to the comparator.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a sort processor and a sort processing device for rearranging a large quantity of data, i.e. sort processing in a data base processing and a business data processing. In this specification, a sort processor and a sort processing device are differentiated. A sort processor is defined as a processor for partly performing a sort processing, on the other hand, a sort processing device is defined as a device for performing a complete sort processing using multiple sort processors connected in series. Description of the Prior Art FIG. 6 shows a construction of a computer system equipped with a conventional sort processing device, which is disclosed in "Information Processing", Vol. 33, No. 12, 1992, p.p. 1416 - 1423. In the figure, the computer system comprises a sort processing device 1, a system bus 2 of a host computer, a main storage device 3 of the host computer, a CPU 4 of the host computer, a disk drive 5 for storing a data in the host computer, and a host computer 6. An operation of the conventional sort processing device is explained by referring to FIG. 6. Firstly, the outline of the operation is explained. When a demand for data processing is generated in the host computer 6, the CPU 4 in the host computer continuously takes out data from the disk drive 5, where the object data are stored, and then continuously transmits the taken out data to the sort processing device 1 via the system bus 2. At this time, the main storage device 3 of the host computer 6 is used as an input-output buffer area as needed. The sort processing device 1 performs a sort processing when the data is inputted, and returns the result to the host computer 6 via the system bus 2. The host computer 6 stores the returned result data in the disk drive 5 in the same manner as that of data inputting. The data input to the sort processing device 1 and the output of the result data from the sort processing device 1 are performed in parallel. Secondly, the detailed operation of the sort processing device is explained below. The sort processing device 1 is continuously inputted with a sequence of data transmitted by the host computer 6, rearranges the inputted data in an assigned order, and returns the result to the host computer 6. This operation is explained using FIG. 5 disclosed in the above-mentioned "Information Processing". FIG. 7 shows the construction of the sort processing device 1 of FIG. 6, and the sort processing device 1 is constructed by serially connecting sort processors 11, 12, 13 and 14. The respective processors 11-14 are connected to the data storage devices 15, 16, 17 and 18. A host computer interface 21 is used for exchanging data and instructions with the host computer 6, and a controller 19 is used for controlling the entire sort processing device 1. The sort processors 11-14 are called from the top a sort processor in a first stage, a sort processor in a second stage, and a sort processor in a third stage, respectively. A sort processor in an "i" stage has a storage capacity corresponding to a 2 i-1 data share. An operation is explained below using an example case where data are inputted to the sort processing device 1 in the order of "8, 2, 1, 3, 5, 7, 6, 4". Firstly, the sort processor 11 of the first stage takes out the inputted data for every two data, rearranges the data in an assigned order, and transmits the rearranged data to the sort processor of the next stage. The sorted data for every two data are inputted to the next stage in the order of (8,2), (3,1), (7, 5), (6,4), ... . As these numbers show, in the sort processor 11 of the first stage, the order "1,3" of the inputted data is rearranged, and the sorted paired data in the order of (3,1) is outputted. The sorted combination of data like this is thereafter called as a data string or a string. The sort processor 12 of the second stage is inputted with these sorted data strings, takes these data strings for every pair, merges this pair of the strings, and transmits the data sorted for every four data to the next sort processor 13. The resulting strings become (8, 3, 2, 1), (7, 6, 5,4), ... . As explained above, as a result of sort processing by the sort processor 12 of the second stage, the inputted data strings (8, 2) and (3, 1) are merged to output the data string (8, 3, 2, 1). The sort processor 13 of the third stage is inputted with those data strings sorted for every four data, takes the strings for every pair, and transmits the data string sorted for every eight data to the sort processor 14 of the next stage. The result of the sort is (8, 7, 6, 5, 4, 3, 2, 1), ... . The sort processor 14 and succeeding sort processors perform the similar processing. It is possible for the sort processors of the respective stages to start sorting process before the sort processor of the preceding stage completes its sorting process. Therefore, when data is continuously inputed to the sort processor of the respective stages, the sort result is outputted in parallel with the data input after some delay. In this manner, the "n" sort processors carry out the rearrangement, that is, the sorting process of the 2 n data. The respective sort processors utilize the connected respective data storage devices 15, 16, 17 and 18 as a storage areas in their comparison and merge processes. Secondly, an operation of the sort processors is explained in reference to FIG. 9 which shows the construction of the conventional sort processor disclosed in "Information Process" Vol. 31, No. 4, 1990, p.p. 457-465. FIG. 9 shows only the inside of the sort processor 12 for the simplicity of the explanation, however, the inside of the other sort processors are the same as that of the sort processor 12. The sort processor of FIG. 9 comprises a comparator 120 for comparing data strings, respective latch registers 121 and 122 for temporarily storing a part of a compared data, data input ports 123 and 124 for inputting the data to the comparator 120, and a controller 125 for controlling operations of the sort processors. The latch registers 121 and 122 have a data size equal to the comparison data size of the comparator 120 and the data width equal to that of the input ports 123 and 124. In the following explanation, this data is assumed to be 4 bytes. An input bus 127 inputs the data from the preceding sort processor 11, and a data and address bus 128 exchanges data with the data storage device 16 connected to the sort processor 12. The sort processing by the sort processor 12 is explained in detail below. The explanation is done using an example of a case when the sort processor 12 is inputted with data strings (8, 2), (3, 1), .... in sequence from the sort processor 11 of the preceding stage, the sort processor 12 merges the data strings to a data string (8, 3, 2, 1), .... and outputs the merged data string to the sort processor 13 of the next stage. First of all, the data string (8, 2) which is firstly inputted is stored as it is in the data storage device 16 connected to the sort processor 12. Secondly, the data "3" of the data string (3,1) is inputted into the sort processor 12, and stored in the data storage device 16 in the same manner. Then thirdly, the top data "8" in the first data string (8, 2) and the top data "3" of the data string (3, 1) are loaded from the data storage device 16 to the latch registers 121 and 122 for every 4 bytes, and comparison takes place in the comparator 120. These data are compared for every 4 bytes in sequence in this comparison. In the sort processing, if the ascending order is given as an order assignment for the sort key, the smaller comparison result is outputted first. If the descending order is given as an order assignment, the larger comparison result is outputted first. The controller 125 controls the ascending/ descending order for the sort key which begins from a top byte of a data. When the comparison result is determined, the data is outputted to the next sort processor 13. In parallel with this comparison process, the top data "1" of the second data string (1, 3) is stored in the data storage device 16. In this case, as a result of the comparison, the data "8" is outputted to the sort processor 13 of the next stage. Therefore, in the following comparison, the data "3" and the data "2", which follows the "8" of the data string (8, 2), are compared. The comparison is carried out by inputting the data "3" and the data "2" to the respective latch registers 121 and 122 from the data storage device 16 for every 4 bytes, and by comparing the data for every 4 bytes. Because a conventional sort processing device is constructed in the way explained above, there have been problems such as follows: (1) In order to improve the performance of the sort processing, it has been difficult to increase the numbers which the sort processors can compare at one time, for example, 4 or 8. For instance, "Electric Communication Society Article Magazine", Vol. 1, J 66 D, No. 3, 1983/3, p.p. 332 - 339, discloses that it is possible to marge K input strings into one in theory. However, in the conventional sort processor, the comparison result is controlled by a information telling which of the input data is larger, and the above reference does not disclose the way to increase the numbers which the sort processors can compare at one time to 4 or 8, which is larger than 2. Therefore it have been impossible to perform the sorting process efficiently by simply changing the number that the sort processor can compare at one time to 4 or 8, rather than 2. (2) For example, in the construction of a conventional art, if the number of the latch registers 121 and 122 increases to 4 or 8, it have been necessary in the comparison process to read out the K data, which becomes the object of the comparison, for every 4 bytes from the data storage device 16. That is to say, at the comparison of 4 bytes, it have been necessary to access the data storage device 16 by 4 x K times. Thus, the more K increases, the more access to the data storage device 16 is needed, and this results in deterioration of the performance. As illustrated in FIG. 10 (a) showing the conventional art, on the data flowing on the bus 128 to the data storage device 16, the data access is carried out every time a comparison takes place. In other words, a data is read out (r1) to the latch register 121, then another data is read out (r2) to the latch register 122. These data are compared at last, and the comparison result is outputted to the sort processor 13 of the next stage. At the same time, the data inputted from the sort processor 11 of the preceding stage is inputted (w) to the data storage device 16. The other sort processors are synchronously performing the similar operation to the respective data storage device in parallel. Therefore, in this case, one comparison takes place for three cycles for a physical comparative unit 4B (Byte).In contrast, if the number is extended to, for example, K = 4, a comparison takes place for four data in the cycles of r1, r2, r3, r4 and w. In this case, the top processor (P 1 + P 2 ) functions in the same manner as the combination of the sort processors 11 (P 1 ) and 12 (P 2 ). That is, the top processor performs the process to merge the four data. Therefore, 5 cycles are necessary for the comparison of the four bytes. As explained above, in general, when the comparison of the K data is performed at one time, it takes the time of (K + 1) cycle per 4B, and this result in deterioration of the performance. (3) In order to avoid this deterioration of the performance, it have been thought out to store the key values to a buffer and avoid accessing to the data storage device. However, in practice, this measure also have some problems. If K buffers are used in a comparison of the K data, it is necessary to read out the succeeding data again for the buffer of the key value corresponding to the outputted data, and then to start the comparison. Therefore, the time is wasted for reading out the key value between the comparison processes, and this also deteriorates the performance. (4) Generally, in a sort processing, it is also necessary to merge multiple fields inside the record, to independently assign the ascending/ descending order to the respective fields, and to rearrange the data according to the assigned order. Therefore, the controller in the sort processor is required to judge the ascending order or descending order for the respective multiple key fields, and to perform an operation according to the order. Therefore, it have been a problem that the hardware logic becomes complicated. (5) In addition, in a case of realizing a sort processor using an LSI, there is a limitation by the number of pins within an LSI package. That is, it is possible to realize a comparator and a control device in a sort processor by a relatively simple hardware logic to form an LSI. However, on the other hand, although the LSI technology advances and makes it possible to integrate a great amount of a hardware logic in one LSI, the sort processor of the above-mentioned conventional art cannot be easily integrated in one LSI, because of the limitation by the number of the pins provided in one LSI. For example, it is currently possible to integrate two or more sort processors according to the conventional art in an LSI. On the other hand, the number of the pins is limited. More concretely, in the above case, the size of the three buses used for connecting with the external devices becomes as follows: A data input bus 126 from the preceding stage : 32 bits, A data output bus 127 to the succeeding stage : 32 bits, An address and a data bus of the data storage device : the address bus: 32 bits, the data bus:32 bits. In addition to the numbers above, when presumed from the design of an ordinary LSI, the power supply, the number of the power source, the grand and other control signals are required approximately by 30 pins, and a total of 160 LSI external pins are necessary. For example, in case that two sort processors are integrated in a single LSI (in the above situation, the sort processors 11 and 12 are integrated in one LSI), the 32 pins in the data . bus connecting each other are unnecessary because they are realized internally. But, about 220 pins including other pins are necessary. In general, in order to integrate N sort processors into one LSI, approximately 32 + 32 + 32 × 2 × N + 30 pins are required. If N is 4, the number of total pins required is approximately 350. That is, if it is possible to integrate multiple sort processors in a single LSI according to rises of the degree of the integration, it is not possible to integrate multiple sort processors in a single LSI, because the number of the pins in an LSI package is limited. (6) As a result, when realizing a sort processing device, only extremely few, 1 or 2, sort processors are integrated in a single LSI although there is extra integrating capacity. Therefore, the sort processing device is constructed from relatively many LSIs of sort processors, and this result in the enlargement of the hardware scale. (7) Furthermore, there is another problem that the hardware scale of data storage device connected to the sort processors also becomes large. For instance, in the respective sort processors, if the number of the data compared at one time is two, the capacity of the data storage device connected to the respective sort processors doubles as the stage proceeds. However, if the capacity of the sort processor of the first stage is approximately 64 bytes, the capacity increases such as 128 bytes in the second stage, 256 bytes in the third stage, 32K bytes in the tenth stage, and 32M bytes in the twentieth stage. In contrast, a current DRAM has the capacity of 16M bits or 64M bits and the access width of 8 bits for one chip. In order to realize the above data storage device with small capacity, if the data storage device with the width of 32 bits is used for example, it is necessary to use at least 4 DRAMs (with access width of 8 bits). 4 DRAMs of 16M bits are required for the respective stages from the first through the eighteenth stages, and a total of 72 DRAMs is required. The total capacity of those DRAM chips is 144MB, but only 16MB is used in reality. Because many DRAM chips are used in low efficiency, the hardware scale becomes large. Liu et al " Parallel merge module for combining sorted lists , IEE proceedings, vol. 136E, No.3, 5/89, describes the preamble of claim 1, see paragraphs 2-4. It is an object of the present invention to solve the above problems, and to improve the processing performance by comparing K (K is more than 2) data or data strings simultaneously without increasing the access demand to the data storage device. It is another object of the present invention to make the sort processing device small sized by releasing the limitation in the number of the pins in the LSI package by reducing the number of pins needed in the LSI package, by constructing a comparator to compare K data or data strings simultaneously, by reducing the number of LSI sort processors constructing a sort processing device, and by reducing the number of the memory chips of the data storage device. It is a further object of the present invention to make the assignment of an ascending/descending order possible for every sort key in the sort processing, and to make it possible to assign the internal process within a sort processor only in an ascending order or only in the descending order, and to simplify the internal construction of a sort processor. SUMMARY OF THE INVENTION According to one aspect of the invention, a sort processor for rearranging data strings to an assigned order is as in claim 1. Other aspects of the invention are as in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows one embodiment of a sort processor according to the present invention. FIG. 2 shows a construction of a sort processing device constructed using sort processors according to the present invention. FIG. 3 shows a sorting process by the sort processing device. FIG. 4 shows a flow of the data in the sort processing by the sort processors. FIG. 5 shows a relationship between the data storage device when the data compared at one time are changed and the necessary number of DRAMs. FIG. 6 shows a connection between a conventional sort processing device and a host computer. FIG. 7 shows a construction of a conventional sort processing device. FIG. 8 shows a sorting process by a conventional sort processing device. FIG. 9 shows a sort processor used in a conventional sort processing device. FIG. 10 explains the performance deterioration which occurs in a conventional sort processor when the number of data compared at one time is increased from 2 to more than 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In this embodiment, it is assumed that the data number that is compared at one time is K = 4 and the data width is 4 bytes. FIG. 1 shows a relationship of the connection between sort processors according to the present invention. The construction of FIG. 1 comprises sort processors 11, 12 and 13, and the respective sort processors comprise data storage devices 15, 16 and 17 for storing data strings to be sort processed. The respective sort processors 11, 12 and 13 comprise of four key value storing areas 131 - 134 for storing sort keys (referred to as key value below), a latch register 135, a comparator 130 and a controller 125 for controlling the entire sort processor. The comparator 130 can be realized by multiple comparators with 2 inputs without using a special circuit construction. The latch register 135 may be constructed from a general register. Moreover, an input bus 126 is inputted with data from the sort processor 11 of the preceding stage, an output bus 127 outputs data to the sort processor 13 of the succeeding stage, and an address and data bus 128 exchanges data with data storage device 16 connected to the sort processor 12. The comparator 130 includes input ports 136 - 140. The latch register 135 is a register having a bit width which the comparator 130 compares at one time. The key value storage device 131 - 134 are constructed by such as register files and memory elements having a capacity to store all the key value of data. The key value storage device 131, 132, 133 and 134 are called as a first, a second, a third and a forth key value storage device respectively for the convenience of explanation. First of all, an operation of the sorting process of the sort processor, constructed in the above-mentioned manner, is explained below. (1) The controller 125 of the sort processor stores the key value of compared individual data to the corresponding key value storage devices (131 - 134). (2) In case that one data is outputted as a result of the comparison, the controller 125 inputs the key value of the date inputted from the data storage device 16 to the latch register 135, for example for every four-byte unit, and performs a comparison. Then, the same data are inputted to empty key storages in sequence. (3) At the start of a first comparing process performed repeatedly in the respective sort processors, the key values of the three data within the four data which are to be compared are respectively stored in the three key value storage devices (131 - 133) out of the four key value storage devices (131 - 134). Then the controller 125 in the sort processor selects the input ports (136 - 138) which correspond to the these three key value storage devices (131 - 133) and the input port 140 connected to the latch register 135, and starts the comparing process at the same time when the top portion of the key value of the fourth data is stored in the latch register 135. In parallel, the key value of the fourth data is stored in the fourth key value storage device 134. (4) In case of other comparing processes than the first comparing process performed repeatedly in the respective sort processors, the comparator 130 judges the smallest data (in case of the ascending order sort) from the results of the comparison between the key data of four data, and the smallest data is outputted. The key vale of a next data which replaces the outputted data is inputted to the latch register 135, and a comparing process begins. In parallel, the key value of the data is stored in the key storage device in which the key value of the outputted data has been stored, and then the sort is performed in the ascending order. (5) In the case of a descending order, the largest data is judged from the results of the comparison, and the sort in the descending order is achieved by outputting the largest data. (6) In case that the data which is inputted to the latch register 135 and is compared, and the data which is stored at the same in the key value storage device time is selected as a result of a comparison of an ascending or descending order and is ouputted, the top portion of the key value of the next data replaced by the data is inputted to the latch register 135 in the same manner to start a comparison. The key value of the next data is inputted to the key value storage device where the outputted data has been stored. In case that this inputted data is not selected nor outputted as a result of the comparison, the key value of a following data which replaces the outputted data is stored in the latch register 135 to start a comparison. In parallel, the key value of this stored data is also stored in the key value storage device where the key value of the outputted data has been stored. (7) In case that there is no more data for replacing the outputted data, the controller 125 does not select the input port of the comparator 130 corresponding to the key value storage device where the key value of the outputted data has been stored, so that the key value of this data does not become an object of comparison any longer. FIG. 2 shows a sort processing device constructed with the sort processors according to the present invention. A sort processing device 1 comprises sort processors 11 - 14, data storage devices 15 - 18 for the respective sort processors, an interface portion 21 for exchanging data and processing demand with the host computer, a key converter 20 for converting the key value of data, and a sort processing device controller 19 for controlling the sort processing device 1 as a whole. The key converter 20 is constructed to connect to the sort processor 11 of the first stage. The present embodiment is explained using figures below. The process in which data is inputted to the sort processing device 1 from the host computer, and the sort processing device 1 which sorts and returns the data to the host computer are the same as those explained above, therefore the explanation is omitted here. First of all, the construction and the operation of the key converter 20 are explained below using FIG. 2. The construction of FIG. 2 is similar to that of FIG. 7 in which the conventional example is explained. However, the capacity of the data storage devices 15, 16, 17 and 18 added to the respective sort processors, and the internal structure of the respective sort processors in FIG. 2 are different from those of the conventional art in FIG. 6. The sort processing device 1 is continuously inputted with a series of data transmitted from the host computer, rearranges, and returns the result to the host computer. In the sort processing device 1, the sort processor group 11, 12, 13 and 14 is linearly connected to the data storage device group 15, 16, 17 and 18 which is added to the respective sort storage group, and the key converter 20 is connected prior to the sort processor 11 in the first stage. In the sort processing, the rearrangement of data is performed based on the key values of the data. For example, assuming that the format of an object data is as shown below and only the sorting process in a descending order is possible, it is explained below how data are rearranged. Data format : key 1 + key 2 + key 3 + non-key data; Where, the key 1 and key 3 are assumed to be assigned as an ascending order, and the key 2 is assumed to be assigned as a descending order. The controller 19 receives the assignment of either ascending or descending orders regarding the keys 1 - 3 from the host computer. Then the controller 19 interprets the order and controls the key converter 20 to output the data to the first sort processor 11 by inverting their bits, regarding the key 1 and key 3 out of the inputted respective data. This process makes it possible to sort multiple keys having both ascending and descending orders, as shown in the example below, even if the sort processors only have the function for sorting in a descending order. A concrete example is explained below. For instance, if two data are "2" and "4", those two data are expressed in binary numbers as "0010" and "0100". Then if those numbers are sorted in an ascending order, it becomes necessary to output these data in the order of "2", 4. While, if those two data are bit-inverted, the expressions in the binary number become "1101", "1011", and these binary numbers in decimal expressions are "13" and 11. Therefore, if the "13" and 11 are sorted in a descending order, the resulting order becomes the same. Similarly, in case when sort processors only have the function for the ascending order, the controller 19 sends an order to the key converter 20 to perform the bit-inversion on, in this example, the key 2. An operation of the sort processor is explained below using a concrete example. The sort processors are respectively defined from the top as a sort processor of a first stage (P 1 ), a sort processor of a second stage (P 2 ), a sort processor of a third stage (P 3 ) and so on. A sort processor of a "i" stage has a data storage device having a capacity for the (K-1) K i-1 data. The following explanation is proceeded by assuming K = 4. As an example of the operation, data are inputted to the sort processing device 1 in the order of: 8, 2, 1, 3, 5, 7, 6, 4, 9, 0, 8, 5, 1, 10, 3, 4, ...... The sort processor 11 of the first stage from the top takes out the inputted data for every four data, and rearranges and transmits those four data to the sort processor 12 of the succeeding stage. Where, the data "8", "2", "1" ..... do not mean that they are expressed in the decimal numbers, but they are the data constructed by the key value portions and the data body portions, however, there are cases that data are constructed only from the key value portion, and the numbers simply shows the size of the data. The data sorted for every four data are inputted to the sort processor 12 of the succeeding stage in the order of: (8, 3, 2, 1), (7, 6, 5, 4), (9, 8, 5, 0), (10, 4, 3, 1), ... . The sort processor 12 of the second stage is inputted with those data grouped by four data, takes those grouped data for every four data, transmits the data sequences sorted by every 16 to the sort processor 13 of the succeeding stage. The result is: (10, 9, 8, , 7, 6, 5, 5, 4, 4, 3, 3, 2, 1, 1, 0), ... . The sort processor 13 of the third stage performs the same process. This process is shown in FIG. 3. As shown in FIG. 3, it is possible for the processors of the respective stages to start its process before the processor of the preceding stage completes its process. Therefore, when data are inputted continuously, the sort result is outputted with a little delay time in parallel to the input of the data. In this manner, n sort processors rearranges K n data, that is, performs sorting processes on K n data. In other words, the sort of N data is achieved by log K N sort processors. For example, to sort 2 20 = 4 10 = a million of data, according to the conventional method of comparing two data at a time, twenty sort processors have been necessary. On the other hand, according to the present method where K = 4, only 10 sort processors are necessary. The respective sort processors of the present invention uses the data storage devices 15, 16, 17 and 18 which are connected to the respective sort processors as a storage region. An internal operation of respective sort processors is explained below using FIG. 1. In this example, it is assumed that the sort processor 12 is inputted with the data strings (8, 3, 2, 1), (7, 6, 5, 4), (9, 8, 5, 0), (10, 4, 3, 1), ..... from the sort processor 11 of the preceding stage. The sort processor 12 then merges these data strings to form a data string (10, 9, 8, 8, 7, 6, 5, 5, 4, 4, 3, 3, 2, 1, 1, 0)...., and outputs the data string to the sort processor 13 of the succeeding stage. First of all, the data strings (8, 3, 2, 1), (7, 6, 5, 4), (9, 8, 5, 0) are inputted to the sort processor 12 from the input bus 126 and stored in the data storage device 16 connected to the sort processor 12, maintaining their order. At the same time when the data is stored to the data storage device 16, the key values of the top data "8" of the data string (8, 3, 2, 1), the top data "7" of the data string (7, 6, 5, 4) and the top data "9" of the data string (9, 8, 5, 0) are stored in the key value storage device 131, 132 and 133, respectively. At this point, the fourth key value storage device 134 out of the four key storages is left empty. In this key value storage device 134, the key value of the fourth data string (10, 4, 3, 1) is stored. In other words, corresponding key value storage device is assigned to the key value of the respective data strings and fixed as follows. The first key value storage device 131 : the key value of the first data string The second key value storage device 132 : the key value of the second data string The third key value storage device 133 : the key value of the third data string The fourth key value storage device 134 : the key value of the fourth data string The operation above is controlled by the controller 125. Secondly, the controller 125 controls the comparator 130 to compare the data inputted from the first, second and third key storages 131, 132, 133 corresponding to the first K- 1 key values where key values are stored, with the data (key values) of the latch register 135. Then, the fourth remaining data string (10, 4, 3, 1) is inputted in sequence to the input bus 126 from the sort processor 11 of the preceding stage. The sort processor 12 stores the key value of its top data "10" for every 4 bytes in the latch register 135 in sequence, and compares it with the data stored in the key value storage devices 131, 132, 133 in every 4 byes. Simultaneously, the key value portion of the inputted data is stored in the key value storage device 134 which has been left empty. To explain in more details, when the first four bytes of the key value of the data "10" is stored in the latch register 135, the comparison begins in the comparator 130 simultaneously. In this example, since the data "10" is the largest, the key value of the data "10" is stored in the latch register 135 for every four bytes. The data "10" may also be stored in the data storage device 16 in the same manner as other data strings. In the comparator 130, the data "8", "7", "9" and "10" are compared. As a result, the largest data "10" is outputted. In case that the data inputted in the latch register 135 is outputted as it is to the next stage as a result of comparison, as seen in example, the key portion of this data is outputted from the comparator 130 to the sort processor 13 of the succeeding stage via the data output bus 127. Generally, a data comprises a key portion and a non-key portion, for example, each data 8, 9, 2, 1 in a set of data (8, 9, 2, 1) indicates only the key portion. The key portion is succeeded with the non-key portion such as ([8, abc], [9, def], [2, abc], [1, xyz]), wherein "abc", "def", "abc","xyz" indicate the non-key portions. When the data includes the non-key portion, the non-key portion of the data inputted from the data input bus 126 is outputted as it is to the sort processor 13 of the succeeding stage via the data output bus 127. These processes are controlled by the controller 125. Next, the data "4" following the data "10" in the fourth data string is inputted from the input bus 126. This data "4" is inputted to the latch register 135 for every four bytes, in the same manner as that of the data "10", and is compared for every four bytes with the data "8", "7" and "9" stored in the key value storage devices 131, 132 and 133. At the same time when the data "4" is inputted to the latch register 135, the key value of this data "4" is stored in the key value storage device 134 which had been left empty. In this comparison, the data "9" stored in the key value storage device 133 is outputted as a result of the comparison instead of the data inputted to the latch register 135. Therefore, in this case, the key portion of the data "9" is outputted to the sort processor 13 of the succeeding stage from the comparator 130 via the data output bus 127. If there is a non-key data portion of the data "9", the non-key portion of the data "9" is read our from the data storage device 16 and outputted to the sort processor 13 of the succeeding stage via the data output bus 127. After the comparison of the key value has been completed, if there is a data portion in the data "4" which do not follow to the key value, this data portion is transmitted from the sort processor 11 of the preceding stage via the data input bus 126, and is sent to the data storage device 16 and stored therein. At this time, the key value of the data "4" is stored in the key value storage device 134 which had been left empty (with remaining of unnecessary data after the output of necessary data to the sort processor of the succeeding stage), and the key value storage device 133 in which the key value of the data "9" has been stored earlier is left empty. Therefore, the controller 125 controls the comparator 130 to compare the data from the data input ports 136, 137, 139 and 140. After the control of the comparator 130 has been completed, the key value of the data "8", which follows the data "9" in the data string (9, 8, 5, 0) is read out for every four bytes and stored in the latch register 135, which is connected to the comparator 130. The comparator 130 compares the stored data with the data "8", "7" and "4" stored in the other key value storage devices 131, 132 and 134 for every four bytes. This comparing operation starts simultaneously when the first four bytes of the key value of the data "8" are stored to the latch register 135. The key value of the data "8" is stored in the latch register 135, while at the same time it is stored in the key value storage device 133. Simultaneously, the data "3 " which follows the data "4" in the data string (10, 4, 3, 1) transmitted from the sort processor 11 of the preceding stage via the data input bus 126 is stored in the data storage device 16. FIG. 4 shows a data flow in the above-explained sort processing. In FIG. 4, the key value of the data "10" is shown as 10 K , and the first and the second four bytes of the key value of the data "10" are shown as 10 K -1 and 10 K -2. In the example of the FIG. 4, the key value is assumed to be 8 bytes (4 byte × 2). In FIG. 4, the time is assumed to go to right direction through the horizontal axis. The FIG. 4 also shows an operational state of the sort processor in the second stage. The data is inputted from the preceding stage to the input bus 126 in the order of 8, 3, 2, 1, 7, 6, 5, 4, ... . This input dada from the preceding stage is shown in the top line of FIG. 4. These data are grouped for every sorted data as shown in the following. 8, 3, 2, 1 7, 6, 5, 4 9, 8, 5, 0 10, 4, 3, 1 These data are sequentially stored in the storage device 16 as shown in the second line in FIG. 4. The top data of respective sets of data are written in the corresponding key storage devices, for example, the top data "8" of the data set (8, 3, 2, 1) is written in the key storage device 131, the top data "7" of the data set (7, 6, 5, 4) is written in the key storage device 132, the top data "9" of the data set (9, 8, 5, 0) is written in the key storage device 133, the top data "10" of the data set (10, 4, 3, 1) is written in the key storage device 134 as shown in the third line to sixth line of FIG. 4 corresponding to the time of 1, 5, 9, 13 of the horizontal axis. Regarding the last key "10", since the comparison is started without waiting to store this value in the key storage device 134, the key "10" is stored in the latch register 135 for every four bytes at the same time when the key "10" is stored into the key storage device 134. When the first four bytes of the key "10" are stored in the latch register 135, each top data "8", "7"," 9" in the key storage device 131 ~ 133 and the data "10" in the latch register 135 are compared. In this case, the contents in the key storage device 131 ~ 133 and the content in the latch register is effective, and the content in the key storage device 135 where the last data is stored is non-effective. As a result of the comparison process, the data "10" having the maximum value is selected and outputted to the output bus 127. Next, since the succeeding data in the data set (10, 4, 3, 1) is "4", the key portion of "4" is stored in the key storage device 134 where the data "10" have been stored. The key "4" is stored in the latch register 135 for every four bytes at the same time when the key "4" is stored into the key storage device 134. When the first four bytes of the key "4" are stored in the latch register 135, each top data "8", "7"," 9" in the key storage device 131 ∼ 133 and the data "4" in the latch register 135 are compared at the time 14 in the horizontal axis. In this case, the contents in the key storage device 131 ~ 133 and the content in the latch register is effective, and the content in the key storage device 133 where the last data is stored is also non-effective. As a result of the comparison process, the data "9" having the maximum value between the compared data is selected and outputted to the output bus 127. Next, since the succeeding data in the data set (9, 8, 5, 0) to the top data "9" is "8", the key portion of "8" is stored in the key storage device 133 where the data "9" have been stored. The key "5" is stored in the latch register 135 for every four bytes at the same time when the key "5" is stored into the key storage device 133. When the first four bytes of the key "5" are stored in the latch register 135, each top data "8", "7" in the key storage devices 131, 132 and the data "5" in the latch register 135 are compared at the time 15 in the horizontal axis. In this case, the contents in the key storage devices 131, 132, 134 and the content in the latch register 135 is effective, and the content in the key storage device 133 where the last data is stored is also non-effective. As a result of the comparison process, the data "8" having the maximum value between the compared data is selected and outputted to the output bus 127. The similar process goes along for the succeeding data, and the contents in the key storage device where the data is stored according to the preceding comparison process are made non-effective and the content in the latch register is made effective at the current comparison. Accordingly, the comparison is carried out without delay. In the above explanation, it is mentioned that, after the data "9" is outputted, the key value portion of the data "8" is read out from the data storage device 16, and stored in the key value storage device 133 and in the latch register 135 for every four bytes in sequence. In the construction of the sort processor shown in FIG. 1 described above, the controller 125 uses the bus connected to the key value storage devices by means of time sharing. The data storage device 16, the key value storage device 131-134 and the latch register 135 may be connected by separate buses. By repeating the above operation, the sort processing is completed. As the sort processing gets closer to the completion, the data on the four strings disappear. For example, in this case, the data strings (8, 3, 2, 1), (7, 6, 5, 4), (9, 8, 5, 0), (10, 4, 3, 1) .... are inputted, and the sort processor 12 merges these four strings to output the data string (10, 9, 8, 8, 7, 6, 5, 5, 4, 3, 3, 2, 1, 1, 0), ... . In outputting this merged data string, when the two "4" are outputted, the data on the second data string (7, 6, 5, 4) disappears from this sort processor 12. The controller 125 controls the comparator 130 so that the corresponding key value storage device does not become the object of comparison for this data string. The constructions of the data storage devices 15 - 18 are explained below. The data storage devices 15 - 18 are constructed by the normal DRAM. For example, in performing a sort processing on a million data of 64MB memory, the prior art and the present invention are different in a manner shown in FIG. 5. In FIG. 5, the relation between the data storage device and the number of DRAMs necessary is shown in case that the comparation data at a time is changed. Compared to the conventional art, the present invention is able to reduce the amount of hardware. FIG. 5 shows that the number of DRAMs necessary for sorting the same amount of data and the number of the sort processors become minimum when K is 4. If K is selected as K = 2 2 = 4, K = 2 4 = 8, K = 2 n (where n is an integer) as shown in FIG. 5, the number of DRAMs can be decreased and the mounting area of the DRAMs can be also decreased. As explained above, it is possible to solve the problem in mounting the sort processors into the LSI, caused by the limitation of the pin numbers in one LSI. Moreover, by solving the mounting problem in the LSI, it is possible to reduce the number of the sort processors in the sort processing device. Therefore, the hardware scale of the sort processing device can be reduced, at the same time it is also possible to minimize the sort processing device for sorting a constant amount of data. Furthermore, it is also possible to reduce the number of the DRAMs in the data storage devices used in the sort processors, and to minimize the sort processing device. In addition, if a sort processor is constructed according to the present invention, the performance does not deteriorate even if the number of the access to the data storage device is increased. In case that a key portion comprises a plurality of small key portions and each small key portion is assigned with an ascending sort order or with a descending sort order, respectively, the sort processor simply performs a sort in a descending or an ascending order by inverting sign bits of any small keys in the preceding process. For example, if the key is as "00010100" in which the value "0001" of the first small key is assigned in the ascending order and the value "0100" of the second small key is assigned in the descending order, the value of the second key is inverted such as "1011" and the key including both the first small key and the second small key such as "00011010" is sent to the sort processor. In this case, the sort processor simply performs the sort in the ascending order by using the single ascending key comprised of two bites value "00011010". Therefore, the hardware of the sort processor can be simplified.

Claims: A sort processor (11) for sorting data strings to an assigned sorting order, comprising: a first data storage device (16) for storing K sorted input data strings, K being an integer larger than or equal to 2; a comparator (130), characterized in that said comparator (130) has K+1 input ports for inputting comparison object data of continuous K sets of the data strings, arranged to selectively compare data from K of the kit ports; in that the sort processor (11) further comprises a controller (125) arranged to select the K input ports which are input to the comparator (130); and in that K input ports out of K+1 ports of said comparator (130) are equipped with respective further data storage devices (131 - 134) each arranged to store a plurality of data which are object for comparison, the remaining input port is equipped with a single data register (135), where the K data that are compared are k-1 data input from respective K-1 input ports out of said K input ports, and data input from the register. The sort processor (11) according to claim 1, so constructed that said data storage devices (131 - 134) store only key values of data compared. The sort processor (11) according to claim 2, wherein said K data strings correspond to said K further storage devices for storing the key values of the data, respectively. The sort processor (11) according to claim 2, so constructed that, in a pre-processing for the comparison process, said controller (125) stores the key values of first K-1 data strings, out of the K data strings which are the object of comparison, in respective first K-1 key value storage devices out of K key value storage devices, and at the same time the top one of the key values of the K-th data are stored in the register (135), the sort processor further being so constructed that said controller (125) selects the input ports corresponding to said first K-1 key value storage devices and the input port connected to the register (135) to start comparison processing, and stores the key values of the K-th data string in the K-th key value storage device. The sort processor (11) according to claim 4, so constructed that, at the beginning of the first comparison processing, said controller (125) stores the top data of the respective data strings in the data storage device while storing the K-1 data strings out of K sort strings which are object of the comparison in the data storage device, and stores in parallel the key values corresponding to the respective data to the key value storage devices. The sort processor (11) according to claim 2, so constructed that, in the comparing processes subsequent to the first comparison process of the comparison processes performed repeatedly by the respective sort processors (11-14), said comparator (130) selects from the results of the comparison of the key data of K data, which data are to be outputs to the sort processor (11) in the next stage, and then said comparator (130) stores the key value of the following data in the data string of the output data, in the register (135) to start the next comparing process, and also stores this key value in the location of the key value storage device, in which the key value of the output data was stored. The sort processor (11) according to claim 6, wherein said comparator (130) is constructed to select the smallest data or the largest data. The sort processor (11) according to claim 6, so constructed that, in case that the data stored in said register (135) is output according to the result of comparison by said comparator (130), said controller (125) stores the key value of the data following the output data belongs to, in the data string to which the output data belongs to, in the register (135) to start the comparing process of the comparator (130), at the same time this key value is stored in the location of the key value storage device where the key value of said outputted data was stored. The sort processor (11) according to claim 2, so constructed that when there is no more data in the data string of the output data as a result of comparison in the comparator (130), said controller (125) does not thereafter select the input port of the comparator (130) corresponding to the key value storage device in which the key value of the output data was been stored. The sort processor (11) according to claim 1, wherein the value of said K is defined as K=2 n , n is an integer larger than or equal to 2. A sort processor device (11), wherein a plurality of sort processors (11-14) according to claim 1 are integrated in one semiconductor chip. A sort processor device (1), wherein a plurality of sort processors (11-14) according to of claim 1 are connected in series. The sort processing device (1) according to claim 12, further comprising: a key converter (20) for inverting the bits of key values ordered in an order opposed to that of the comparison function of the comparator (130), before transmitting the inverted key value to the sort processor (11) of a first stage. A sort processing device (1) comprising: a plurality of sort processors according to one of the claims 2-9 (11-14) so constructed that said plurality of sort processors (11-14) operate in parallel and repeatedly performs comparison processes using respective comparators (130) in order to perform a sorting process on a plurality of data; and a key converter (20) for inverting the bits of key values ordered in an order opposed to that of the comparison function of the comparator (130) before transmitting the inverted key value to a sort processor (11) of a first stage.

Inventors: FUSHIMI SHINYA, FUSHIMI, SHINYA
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1997
Main classification: G06F7
IPC codes: G06F7