ADAPTIVE FILTERS AND EQUALISERS

Abstract: An adaptive Decision Feedback Equaliser (DFE) is trained using the Delayed Least Mean Square (DLMS) algorithm. A delay, equal to the feedforward filter length, is introduced in the filter coefficient update, which allows the DFE to be realised as the cascade of a series of modular sections. Additionaly a signed power-of-two number representation is used for the equaliser input data. Using this number representation, all multipliers can be replaced with barrel shifters and adders. Reduced complexity of circuit implementation and improved signal throughput are obtained.

Description: AHaprivP Filter* and F_τnali ws Technical Field This invention relates to adaptive filters, and particularly, though not exclusively, to adaptive equalisers incorporating adaptive filters. ftarlrgmiinH Art Communication systems generally suffer from a variety of sources of distortion, including dispersion, i.e. variations of signal delay and attenuation as a function of frequency. Mobile communications systems suffer from a particular source of distortion known as multi-path propagation, the effects of which typically manifest themselves as a form of dispersion, leading to intersymbol interference (ISI). It is known that the effects of dispersion can be mitigated by including an equalising filter or equaliser in the communications path, for example in the receiver, to amplify the wanted signal and attenuate the interfering signals. In cases where the dispersion effects are liable to vary with time, as in the case of mobile communications, an adaptive equaliser is used which can modify its operating characteristics to compensate for the variations. The adaptive equaliser determines the current dispersion effects of the communications path by monitoring so-called training signals of predetermined form which are transmitted periodically for this purpose. Thus, for example, in the proposed High Performance Radio Local Area Network (HIPERLAN , there is a 450-bit header packet which can be used to train an equaliser in preparation for receiving following data blocks. Various kinds of adaptive equaliser architectures are known, including the decision feedback equaliser (DFE) which can be implemented using transversal filters, lattice filters or systolic arrays (see, for example, R. Perry, D. Bull, A. Nix, "Algorithms for Rexible Equalisation in Wireless Communications", IEEE Proc. ISCAS April 1995, vol 3., pp. 1940-1943). Likewise, various kinds of algorithm can be used to implement training of an equaliser to compensate for the current dispersion characteristics of a communications channel; these algorithms include the least mean square (LMS) algorithm (F. Lu, H. Samueli, "A 60-MBd, 480-Mb/s, 256-QAM Decision-Feedback Equalizer in 1.2- un CMOS", IEEE Journal of Solid-State Grcuits, March 1993, Vol. 28, No. 3, pp. 330-338) and the delayed least mean square (DLMS) algorithm, an approximation of the LMS algorithm (M. D. Meyer, D. P. Agrawal, "A High Sampling Rate Delayed LMS Filter Architecture", IEEE Trans on Grcuits and Systems II: Analog and Digital Signal Processing, vol SP-40, Nov 1993, pp 727-729). Although the behaviour of the equaliser architectures and training algorithms is known in principle, it has been found that there is wide scope for variation in the specific manner of their implementation. Different practical implementations may have widely differing performance, in terms of speed and precision of operation, and size and complexity of the circuitry (e.g. in integrated circuit form) that is required. It is an object of this invention to provide an adaptive filter, for use for example in an adaptive equaliser, which has improved operational characteristics and can be economically implemented. T_.<ffinq.τι» nf TnvwiHnn According to one aspect of this invention there is provided an adaptive filter having a transposed direct-form transversal filter section comprising a plurality L of filter stages, said adaptive filter being arranged to supply an output signal sample in each of a succession of sample periods, comprising: means for multiplying a sample from a respective one of said transversal filter sections by a respective coefficient to derive a respective product signal, means for deriving each filter output sample by summing said product signals for a plurality of transversal filter sections, means for updating said coefficients for derivation of each sample, and means for delaying use of each updated coefficient value for a Jfcth stage by i - 1 - it sample periods. This delay enables a strict implementation of the DLMS algorithm to be obtained using a cascade of modular sections, which is economical in terms of number of integrated- circuit gate-equivalents which are required. In one embodiment of the invention input data are represented in accordance with a signed-power-of-two approximation; this enables the complexity of the circuit to be reduced by eliminating multipliers, and provides a reduction in the period required to complete an iteration of the training algorithm. According to another aspect of this invention there is provided a method of adaptive filtering using a transposed direct-form transversal filter section comprising a plurality L of filter stages to supply an output signal sample in each of a succession of sample periods, wherein each filter ouφut sample is derived as a sum of products, each product is derived by multiplying a sample from a respective one of said transversal filter sections by a respective coefficient, said coefficients are updated for derivation of each sample, and use of each updated coefficient value for a Jfcth stage is delayed by L - 1 - k sample periods. Brief Description nf Drawings An adaptive filter in accordance with this invention, for use for example in an adaptive equaliser, will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block schematic diagram of a conventional decision feedback equaliser, Figure 2 is a diagram in data flow form showing the overall structure of a (3,3) decision feedback equaliser incorporating the invention; and Figure 3 is a block schematic diagram of a processing module, three of which are used to implement the equaliser of Figure 2. T t MΠHK fnr Tarrying (lint thw Tnvfnr nn A Tn_...stτia1 AppHeahiliry Figure 1 shows a conventional DFE 10, comprising a feedforward filter section 12, in this case having three stages, and a feedback filter section 14 also having three stages. The ouφuts of these two filter sections are combined by a summing device 16, the ouφut of which is coupled to a decision module 18. The decision module 18 operates to provide a fixed + 1 ouφut signal if its input is greater than zero, and a fixed -1 signal if its input is less than zero. The equaliser receives successive input signal samples in respective sampling intervals at the input to the feedforward filter, and ouφuts a filtered signal sample in each interval at the ouφut of the decision module 18. The ouφut samples are fed back via a single-interval delay circuit 20 to the feedback filter section 14. An ouφut signal sample corresponding to a given input sample becomes available after a delay of a number of sampling intervals related to the length of the filter structure. Each stage of the filter sections 12 and 14 comprises a multiplier for multiplying a respective input sample value by a respective weighting coefficient. Input samples are coupled between each pair of successive stages through a respective single-interval delay circuit The ouφuts of the multipliers are combined by adders to derive the overall filter ouφut. Thus, for example, the first stage of the feedforward filter section 12 comprises a multiplier 22° which receives the current input sample to that filter section and a respective coefficient w f ° (n - 1) where 0 is an index identifying the stage, and /indicates feedforward. The next stage receives input samples after a single-interval delay provided by a delay circuit 24, and comprises a multiplier 22 1 for multiplying the delayed samples by a coefficient w f l (π - 1) Likewise the first stage of the feedback filter section 14 comprises a multiplier 32° for multiplying the sample delayed in the delay circuit 20 by the coefficient w b (n - 1) where b indicates feedback. The next stage receives input samples after a single-interval delay provided by a delay circuit 34, and comprises a multiplier 32 l for multiplying the delayed samples by a coefficient As indicated by the notation (n - 1), each filter stage coefficient can be varied or updated for each sampling interval, in dependence on the processing of previous signal samples. The filter sections 12 and 14 can be implemented, for example, using transversal filters. Figure 2 shows the data flow in a modular, high throughput DFE structure in accordance with this invention, incorporating the DLMS algorithm and for use as an adaptive equaliser. As will be described below, this structure in effect comprises a pair of transversal filters, one implementing a feedforward filter section and the other implementing a feedback filter section, arranged in an advantageous manner which simplifies practical construction and improves the operational characteristics of the equaliser. The manner in which this structure is derived will now be described. The DLMS algorithm can be specified in terms of equations 1 and 2 below: (n) = W(n - 1) + βe * (n - _D)X(n - D) (1) ) = </(π) - - l)X(π) (2) where W is a vector of filter coefficients for the feedforward and feedback filter sections, and X is a vector of filter input samples for the feedforward and feedback filter sections; n is a index representing successive iterations of the algorithm; β is the iteration step size; e * indicates the complex conjugate of e, which is the error in the estimate of the desired response relative to the actual desired response; D represents a delay, in units of sampling intervals; d is the desired equaliser response (during training); and H indicates the transposed complex conjugate of a vector. By partitioning the vectors W and X to correspond to the feedforward (f) and feedback (b) sections respectively of the equaliser, equation (1) can be rewritten as: [ n), W t (n)] = [W/K - 1), W»(π - 1)] +βe'(π - D)[X /ι - D), X t (n - D)] (3) where X n) - [*//!) xf t - 1) ... XJ- - L + 2) x n - L -r 1)] X»(n) = [*.(«) *»(« - 1) ... x*(n - L + 2) x,(n - L + 1)] J: represents successive elements of each vector; and L represents the number of stages in the feedforward and feedback sections of the equaliser. X>(π) is the vector of previously detected symbols i.e. , X»(O - [ d(n - 1) d(n - 2) ... d(n - L + 1) d(n - L)] An ouφut vector Y(π) is defined as Y(O = [Λ(O Λ(Λ - 1) .- y«(π - L + 2) y w (τι -L + 1)] where y,(n - 0 - ∑, * f ( ι - i - * Λ(τ. - i - 1) + j 4 (.7 - i) (4) *=0 ' w represents the filter coefficients; k is an index identifying individual filter coefficients with the respective filter stages; and y 4 (n - i is the contribution to the current equaliser ouφut from the feedback filter. Rewriting (4) gives i-l yf p - 0 = Σ * (" - ' - *> * (» - ' - 1) k-0 f + x f (p - 2- ' (n - i - 1) ♦ y h (n - i) ,{~ - *)=y,-.(- ~ 0 + * " " 2/ ' (π - < - 1) + y t (n - (5) Initially y b (n - i) is defined as ^ 4 (n - 0 - ∑ *»(« - / - * . (» ~ 1 - *) (fo) *=0 β This can be interpreted as the transposed form of a transversal filter. The delay in the weight terms in (6a) for the higher indexed coefficients is due to the delay in the ouφut signal propagating along the filter structure. It should be noted that this is not a strict realisation of the DLMS algorithm. However, by inserting delays in the filter coefficient terms in (6a), a transposed filter structure implementing the DLMS algorithm is obtained i.e. the Jtth coefficient used in (6a) should be delayed by L - 1 - k iterations. In this case y b (n - i) is given by y b (» ~ 0 k - 1 - (L - 1 - k))x h ( - i - Jfc) that is 1-1 . . -.(» - 0 e ∑ *T {» ~ Lyx b n - i - k) ( Λ k~0 ° It is the data flow diagram for this transformed arrangement using the DLMS algorithm which is shown in Figure 2, in the case of a (3,3) decision feedback equaliser (i.e. a DFE with feedforward and feedback filter sections both 3 stages in length). Referring to Figure 2, the equaliser 110 shown consists of three identical processing modules 112α, 1122? and 112c. Each module implements both a part of a feedforward filter section (the filter coefficients w fi derived as described below, in the upper part of each module) and a pan of a feedback filter section (the filter coefficients vv b in the lower part of each module). The sampled input signal x .n) is supplied to the first processing module 112-z, intermediate samples are transferred between modules (e.g. the sample x n - 2) is transferred from the module 112a to the module 1122b), and the filtered ouφut samples d i - L + 1) appear at the ouφut of the third module 112c. These ouφut samples are fed back via a decision module 114 and a switch 16 to a single-interval delay circuit 118 and thus to the feedback filter sections in each module 112a - 112c; the signal from the switch 116, and the ouφut samples from the module 112c, are also supplied to an adder 120, the ouφut of which is coupled to a single-interval delay circuit 122 to provide an error signal e(n - L) to an error input of the first module 112 . The decision module 114 operates to provide a fixed +1 ouφut signal if its input is greater than zero, and a fixed -1 signal if its input is less than zero. During training of the equaliserllO the switch 116 is operated to select a signal d(n -L + 1) arranged to represent the known training sequence. Once training is completed the switch is operated to supply the ouφut of the decision module 114 instead. Each module \\2a - 112c also receives a respective earlier intermediate sample, delayed by L intervals, as shown for example by the sample x i • L) received by the module 112a, and all modules receive an earlier ouφut sample, delayed by IL intervals. The latency in the ouφut is 22 1 sample periods. This is the time required for all the feedforward filter stages to fill and for the estimate of the desired response to propagate along the filter structure. It should be noted that the input to the feedforward filter enters from the left whilst the previous decision is input to all the feedback filter sections simultaneously. Furthermore the index for the feedforward filter coefficients increases left to right, (as viewed in Figure 2) but for the feedback filter coefficients, it decreases left to right The new value for the ith feedforward coefficient * (« " 0 required by (4) is obtained, with a delay of one sampling interval, from (3) as w . (« - ) = » . (n - i - 1) + βe * (n - L - i\κc f (n - L - 2i) (7) For the update of w b '(n 1) there are two forms corresponding to equations (6a) and (6b). For (6a) the weight update is wfo) ~ wj(π - 1) ♦ βe - Dx„(n - L - i) (8a) For (6b) the weight update is given by w b '(n - (I - 1 - 0) = w b ' n - L + i) (8b) + βe - IL + 1 + _ A (n - IL + 1) In both (8a) and (8b) global communication is required; in (8a) the same error term is fed back to all the coefficient update sections, whereas in (8b) the same data symbol is fed back. The form (8b) is advantageous because the feedback data is only a complex number of the form ± 1 ±j . In addition, because of the reversed order of the feedback filter coefficients, the error term in (7) is the same as that required in (8b) and therefore this reduces the communication costs considerably. An individual processing module for the DLMS DFE structure using the update (8b) is shown in Figure 3. Referring to Figure 3, the input sample for the module (i.e. the sampled equaliser input signal in the case of the module 112a or an intermediate sample in the case of the subsequent modules) is represented by xfji • 2i), where . is an index corresponding to the position of the module in the equaliser structure, i ranges in value from zero for the module 112a to two for the module 112c. This input sample is applied to a multiplier M3 and to a two-interval delay circuit 150, which supplies the corresponding sample x n - 2i - 2) at the ouφut of the module. The other input of the multiplier M3 receives the ouφut from an adder Al, delayed by a single-interval delay circuit 152; the inputs to this adder comprise its own delayed ouφut and the ouφut from a multiplier M2. The multiplier M2 provides the product of the factor β and the ouφut of a multiplier Ml, which in turn receives the earlier intermediate sample delayed by L intervals, xfii • L - 2i), and the error signal e n - L - i). The ouφut of the adder A 1 is the coefficient update for the z ' th feedforward coefficient. The delayed intermediate sample is also fed into a two-interval delay circuit 154 to provide the corresponding previous delayed sample, xfti - L - li - 2). The error signal is likewise fed to a single-interval delay circuit 156 to provide a previous error signal, and to- one input of a multiplier M6, which also receives a sample x„{n - 2L + 1) to provide adjustment to the fth feedback filter coefficient. The ouφut of the multiplier M6 is multiplied by the factor β in a multiplier M5, the ouφut of which is supplied to an adder A3. The other input of this adder is its own ouφut, delayed by a single-interval delay circuit 158 in a manner similar to that of the adder Al and the delay circuit 152. The delayed ouφut of the adder A3 is also supplied to a multiplier M4, where is it multiplied with the feedback signal d(n • L) selected by the switch 116 (Figure 2). The ouφut of the adder A3 constitutes the coefficient update for the .th feedback coefficient. The ouφut of the multiplier M4 is summed by an adder A2 with the ouφut of the multiplier M3 and a signal y (π - i), which is the delayed (i - l)th-order estimate of the desired response, to provide a signal y,{n - i - 1); the ouφut )j of the final module is the estimate of the desired response. The compact structure shown in Figures 2 and 3, with the transposed feedback sections enabling use of the same error terms in corresponding feedforward and feedback sections, is made possible by the application of the delay of L - 1 - k iterations to the filter coefficients as described above. This structure in turn confers benefits in terms of reduced number of logic gates, integrated circuit area and cost required for practical implementation of the equaliser. In addition, this structure provides a saving in the duration of the iteration interval of at least the computation time of a multiply and add, and an adder tree, as compared to the conventional LMS algorithm. The throughput rate is determined by the time required to carry out a single multiplication, shift and addition (Ml, M2 and Al in Figure 3). The clock rate is limited only by this delay in a single processing module. A further benefit can be obtained by adopting a non-uniform quantisation of the equaliser input data, using a signed-power-of-two (SPT) approximation. A representation of a discrete-time fl-bit two's complement number x(m), in the signed power-of-two space is given by N *_» = ∑ ^)2* r) , ^) = -1,0,1 ( ) r=\ where g(r) is the power of the r* power-of-two (POT) term and N is the number of POT terms used in the approximation. If x(m) is an integer, then for N - f 52 1 all integers in the range -2*" 1 ... 2* 1 - 1 can be exactly represented. However, for N < B/2 ) not all integer values that x(m) may take can be represented by x,j(m). Hereafter the term N-SPT will be used to denote an approximation of a two ' s complement integer using N POT terms, each talcing either positive or negative sign. The area and/or latency of a multiplier (such as the multipliers Ml to M6 in Figure 3) can be significantly reduced by using restricted-number representations for either the multiplier or multiplicand, i.e. using coefficients with a limitation on the number of non- zero digits. The multiplier can then be replaced with shift and addition elements. Using a 2-SPT representation of the input data allows the multipliers in both the transversal filter and the coefficient update modules to be replaced with a pair of barrel shifters and a single adder. For a transversal filter DFE, as shown in Figure 2, the inputs to the feedback filter are the previously detected symbols. The representation of these data samples is arbitrary and it is obviously advantageous (to minimise complexity) to represent them as POT terms. By adjusting die magnitude of the training data samples, the magnitude of filter coefficients can generally be kept bounded by one. The non-uniform quantisation is applied to the input data, as opposed to the filter coefficients, because the performance of the equaliser is largely unaffected by this non- uniformity. In addition, the non-uniform quantisation of the input data is required only once per input sample. In contrast, if SPT filter coefficients were used, it would be necessary non-uniformly to quantise the coefficients following each update. This would introduce additional latency and complexity within the coefficient update loop. Moreover, as already noted, the complexity of the equaliser (if implemented using a transversal filter with a specific delay as described above) can be significantly reduced by exploiting the SPT representation of the input data. Referring to Figure 3, the contributions to the estimate of the desired response, from the feedback and feedforward filters, are combined in each module 112a to 112c using adder A2. Instead the feedforward and feedback contributions could be propagated separately and summed in the last filter stage. SUBSTITUTE SHEET (RULE 261 Postponing the summation is of particular advantage if N/M-SPT input data samples for the feedforward/feedback filter stages are used, i.e. the summation of N+M two's complement numbers with the data estimate from the lower order stage can be carried out once at the final module 112c. The data streams in the final module can be combined using an adder tree to determine the estimate of the desired response. This structure is advantageous since the different representations for the feedback and feedforward input data do not destroy the regularity of the structure. For the conventional LMS algorithm, different feedforward and feedback filter structures would be required for the different number representations of the input data. It is estimated that the use of a 2-SPT approximation of the input data would allow a reduction in the gate count of an integrated circuit implementation of up to 50% for filter coefficients of 16 bits and a filter length of 8. Furthermore, if the step size β is restricted to take one of a small number of POT values, the multipliers M2 and M5 (Figure 3) could be replaced with hardwired shifts which are multiplexed according to the current step size setting.

Claims: CLAIMS 1. An adaptive filter having a transposed direct-form transversal filter section comprising a plurality L of filter stages, said adaptive filter being arranged to supply an ouφut signal sample in each of a succession of sample periods, comprising: means for multiplying a sample from a respective one of said transversal filter sections by a respective coefficient to derive a respective product signal, means for deriving each filter ouφut sample by summing said product signals for a plurality of transversal filter sections, means for updating said coefficients for derivation of each sample, and means for delaying use of each updated coefficient value for a Jfcth stage by L - 1 - k sample periods. 2. An adaptive filter according to claim 1, wherein said updating means comprises means for deriving updated coefficients using a delayed least mean square algorithm. 3. A decision feedback equaliser having an feedback section comprising an adaptive filter according to claim 1 or claim 2, and having a feedforward section comprising a second filter. 4. A decision feedback equaliser according to claim 3, wherein said second filter is a transversal filter using coefficients derived using a delayed least mean square algorithm. 5. A decision feedback equaliser according to claim 3 or claim 4, wherein input data to the equaliser are represented in accordance with a signed-power-of-two approximation. 6. A method of adaptive filtering using a transposed direct-form transversal filter section comprising a plurality L of filter stages to supply an ouφut signal sample in each of a succession of sample periods, wherein each filter ouφut sample is derived as a sum of products, each product is dαived by multiplying a sample from a respective one of said transversal filter sections by a respective coefficient, said coefficients are updated for derivation of each sample, and use of each updated coefficient value for a Jfcth stage is delayed by L - 1 - Jfc sample periods. 7. An adaptive filter substantially as hereinbefore described with reference to Figures 2 and 3 of the accompanying drawings. 8. A decision feedback equaliser substantially as hereinbefore described with reference to Figures 2 and 3 of the accompanying drawings. 9. A method of adaptive filtering substantially as hereinbefore described with reference to Figures 2 and 3 of the accompanying drawings.

Inventors: BULL DAVID ROGER, NIX ANDREW ROBERT, PERRY RUSSELL, BULL, DAVID, ROGER, NIX, ANDREW, ROBERT, PERRY, RUSSELL
Applicants: BULL DAVID ROGER, NIX ANDREW ROBERT, PERRY RUSSELL, UNIV BRISTOL, BULL, DAVID, ROGER, NIX, ANDREW, ROBERT, PERRY, RUSSELL, UNIVERSITY OF BRISTOL
Application year: 1997
Main classification: H03H21
IPC codes: H03H21, H04L25