Digital video signal processor

Abstract: A digital video signal processor for compressing a digital video signal and recording the compressed signal in response to a key input signal provided externally by a user. A block processor (310) shuffles the digital video signal by predetermined block units. A signal compressor (340) compresses the shuffled video signal output by the block processor (310). A modulator (300) modulates the compressed video signal output by the signal compressor (340) and a black-and-white signal information. A controller (330) generates a compression control signal to output to the signal compressor (340) and outputs the black-and-white signal information to the modulator (360) in response to the detection signal. When the compression control signal is received, the signal compressor (340) transform-encodes the shuffled video signal such that a color component is encoded only with a DC coefficient. As a result, a black-and-white video signal can be recorded with a higher-resolution.

Description: The present invention relates to a digital video signal processor, and more particularly, to a digital video signal processor such as a digital video tape recorder or a digital video camera for processing a black-and-white video signal. In general, when a video data is recorded on a video tape in a digital video cassette recorder or a digital camcoder, the video data is recorded in a predetermined format. Figures 1A through 1C illustrate one of the recording format of a general digital video cassette recorder. Figure 1A shows a discrete cosine transform (DCT) block which is a set of 8×8 (64) pixels. Figure 1B shows a macro block having six DCT blocks, i.e., four luminance components Y1, Y2, Y3 and Y4, and two color difference components Cb and Cr. Figure 1C shows a video segment which consists of five macro blocks MB1, MB2, MB3, MB4 and MB5. Each of the DCT blocks for the luminance components Y1, Y2, Y3 and Y4 of the macro blocks in Figure 1B are discrete-cosine-transformed to be 14 bytes of DCT coefficients, which includes one DC coefficient and a plurality of AC coefficients. Also, each of the DCT blocks for the color difference components Cb and Cr are discrete-cosine-transformed to be 10 bytes of DCT coefficients, which includes one DC coefficient and a plurality of AC coefficients. However, in a conventional digital video signal recorder, even when a user records a black-and-white video signal, the AC coefficients of the color difference components Cb and Cr are still recorded on the tape, which results in lowering of the compression efficiency. Further, the AC coefficients of the color difference components Cb and Cr may vary without being kept at a predetermined level, which results in noise in the video signal. It is an aim of embodiments of the present invention to provide a black-and-white video signal recorder for reducing noise and recording a black-and-white video signal with high resolution when it is desired to record a black-and-white signal only among a video signal. According to the present invention there is provided an apparatus and method as set forth in the appended claims. Preferred features of the invention will be apparent from the dependent claims, and the description which follows. In an aspect of a digital video signal processor of the present invention, a block processor shuffles the digital video signal by predetermined block units. A signal compressor compresses the shuffled video signal output by the block processor. A modulator modulates the compressed video signal output by the signal compressor and a black-and-white signal information. A controller generates a compression control signal to output to the signal compressor and outputs the black-and-white signal information to the modulator in response to a key input signal provided externally by a user. When the compression control signal is received, the signal compressor transform-encodes the shuffled video signal such that a color component is encoded only with a DC coefficient. Said data compressor preferably converts the value of the DC coefficient of the encoded signal into a predetermined value when the compression control signal is received. The predetermined value is preferably an average of numbers represented by 8 bits. For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figures 1A-1C illustrate recording formats of a general digital video cassette recorder; Figure 2 is a block diagram of an embodiment of a digital video signal processor according to the present invention. The digital video signal processor of Figure 2 includes a block processor 310 for shuffling of an input digital video signal, a memory 320 for storing the data processed by the block processor 310 temporarily, a data compressor 340 for compressing the video data output by the block processor 310, a parity adder 350 for adding parity to the compressed video data output by the data compressor 340, a modulator 360 for modulating video data output by the parity adder 350 and black-and-white signal information data, a recording head 370 for recording the modulated data in a recording medium, and a controller 330 for applying a compression control signal to the data compressor 340 to set color components to a predetermined value and generating a black-and-white signal information in response to a key input signal 332. When a user wants to record a video signal in a black-and-white mode, the user may apply a key input to the apparatus, which may be a digital camcoder or a digital VCR. Upon receiving the key input signal 332, the controller 330 generates a compression control signal to output to the data compressor 340 so that the data compressor 340 transform-encodes the shuffled video signal only with a DC coefficient. Also, the controller 330 outputs the black-and-white signal information to said modulator 360 in response to the key input signal 332. The block processor 310 carries out shuffling of the input video data and to make up video segments so that the compression efficiency is increased. When data is shuffled, macro block units are taken from five different areas of one frame and combined to be a segment unit. The memory 320 temporarily stores data processed by the block processor 310. Meanwhile, the shuffled data is unshuffled to restore to be the original data during the playback. The data compressor 340 compresses the digital video signal from the block processor 310 by carrying out a discrete cosine transform (DCT) and a variable-length coding (VLC). Upon receiving the compression control signal, the data compressor 340 converts a DC coefficient among the DCT coefficients of the color difference components Cb and Cr into the predetermined DC value and sets AC coefficients to zero. Since the AC coefficients become zero, that is, there is no changing signal except for a DC signal, noise in an input video data signal or quantization noise is reduced. Furthermore, if the data amount of the encoded luminance components is large, the luminance components may be recorded in the area which was allocated for the AC coefficients of the color components. In the present embodiment, the DC level is 128, which is a median value of numbers represented by 8 bits. As a result, when the color component is converted into a predetermined DC value in the data compressor 340, the resolution is increased since more AC coefficients of the transformed luminance component may be recorded in the area for the color components Cr and Cb of the macro block shown in Figure 1B compared with case in which a color signal exists. The parity adder 350 adds a parity to the video data output by the data compressor 340 so that the video data is reproduced from the medium with negligible error during a playback. The modulator 360 modulates the video data output by the parity adder 350 and the black-and-white signal information generated by the controller 330, so that the recording head 370 records on the recording medium. The black-and-white signal information which is recorded as a side information is used to reproduce the recorded data in a black-and-white video signal during playback. As described above, embodiments of the present invention reduce noise by setting a color component to a predetermined level when a video signal is recorded in a black-and-white mode. Further, a luminance component may be recorded in the area in which the color component would be recorded otherwise, thereby increasing the resolution of the signal. The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

Claims: A digital video signal processor for compressing a digital video signal and recording the compressed signal, comprising: a block processor (310) for shuffling the digital video signal by predetermined block units; a signal compressor (340) for compressing the shuffled video signal output by said block processor (310); a modulator (360) for modulating the compressed video signal output by said signal compressor and a black-and-white signal information; and a controller (330) for generating a compression control signal to output to said signal compressor (340) and outputting the black-and-white signal information to said modulator (360) in response to a key input signal provided externally by a user, wherein said signal compressor (340) transform-encodes the shuffled video signal such that a color component is encoded only with a DC coefficient when the compression control signal is received. A digital video signal processor as claimed in claim 1, wherein said data compressor (340) converts the value of the DC coefficient of the encoded signal into a predetermined value when the compression control signal is received. A digital video signal processor as claimed in claim 2, wherein the predetermined value is an average of numbers represented by 8 bits.

Inventors: KIM YONG-JE, KIM, YONG-JE
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1997
Main classification: G11B20
IPC codes: H04N9