A SIGNAL PROCESSING MEANS

Abstract: A digital audio processing system comprising: a time-multiplexed bus (70; 50) for distributing data values in time slots (S1-SM); a first input for receiving a sequence of first data values representing a first audio signal sequence with a first sampling rate; a second input for receiving a sequence of second data values representing a second audio signal sequence with a second sampling rate; a first signal processor operable to process signal sequences having the first sampling rate; and a second signal processor operable to process signal sequences having the second sampling rate; a control unit (210) operating to indicate first time slots on the bus for data values associated with the first sample rate (fsg1) and to indicate second time slots on the bus for data values associated with a second sample rate, such that the first signal processor communicates with the first input via the first time slots, and the second signal processor communicates with the second input via the second time slots.

Description: A SIGNAL PROCESSING MEANS Technical Field of the Invention The present invention relates to a system for digital audio processsing. Description of Related Art Mixing is the action of adding two or more audio signals such that a resulting output signal is formed. Commonly, in a mixer, other functions may also be performed such as for instance filtering. This has traditionally been done with analogue technology using amplifiers, variable resistors etc. In the last couple of years, however, digital equipment has been introduced for performing these functions. Digital signal processing has the advantage of allowing better con¬ trol over noise and distorsion. A signal source may provide an analogue signal S A to an Ana- log-to-Digital Converter (A/D-converter) . The signal source may be a microphone or any other original analogue signal source. An A/D-converter works at one fixed sampling rate f s such that it provides a sample of the analogue signal once in a time period T Ξ = l/f s . The samples are provided on a digital output in such a manner that a digitized signal s d with sample frequency f s is provided. If, for example the sampling frequency f s is 48 kHz, a digitized value will be provided 48 000 times per second. For compact disc (CD) production the practised standard sampling frequency is 44.1 kHz, whereas for television purposes a frequency of 32 kHz is commonly used. At each sampling instant the amplitude of the analogue signal is established, and the result is coded as a binary number, or word, having a certain number of bits. In order to provide an accurate signal, modern audio equipment works with a large number of bits in each binary word. Each word may for example comprise 24 bits. Hence, with a word length of 24 bits and a sampling frequency of 48 kHz, the analogue signal could be represented by a bit stream of 1 152K bit/s. A prior art signal processing system which allows mixing of signals is inherently synchronous, i e the system is timed by a clock running at one stable frequency in agreement with the sampling frequency of the signals to be processed. Since the system is synchronous all audio sources that are to be part of a mixing process have to be synchronous, i.e. all inputs must provide exactly the same number of samples per time period. If that condition is not fulfilled one of the audio signal sequences will, at some instance, include one sample too few or one sample too many. A known method for handling this problem is to provide a sample rate converter for converting audio data with a first sample rate to audio data with a second sample rate. US 4 716 472 relates to the problem of enabling replay of audio stored on a digital audio tape without varying the sampling rate of the replayed audiosignal in direct propor¬ tion to the tape speed. For this purpose US 4 716 472 dis- closes a device for variable speed replay of digital audio with constant output sampling rate. The device includes a varispeed processor which receives audio data with variable sample rate from one bus and delivers audio data to another bus with a fixed sample rate. Summary A problem to be solved by the present invention is to provide a signal processing means being operable to process a number of signals at one sampling frequency, the signal processing means alternatively being settable to simultaneously process at least two separate groups of signals, the groups having mutually different sampling frequencies. This problem is solved by a digital audio processing system, comprising a time-multiplexed bus for distributing data values in time slots, a first input for receiving a sequence of first data values representing a first audio signal sequ- ence with a first sampling rate, and a second input for receiving a sequence of second data values representing a second audio signal sequence with a second sampling rate. The system also includes a first signal processor operable to process signal sequences having the first sampling rate and a second signal processor operable to process signal sequen¬ ces having the second sampling rate and a control unit operating to indicate first time slots on the bus for data values associated with the first sample rate and to indicate second time slots on the bus for data values associated with a second sample rate such that the first signal processor communicates with the first input via the first time slots, and the second signal processor communicates with the second input via the second time slots. According to a preferred embodiment the control unit further operates to define successive data frames on the time-multi¬ plexed bus such that each data frame comprises a predetermi¬ ned number of slots. The control unit operates to generate a process control signal relating to each selected unique sample rate, each process control signal including informa- tion for identifying data frames including data values asso¬ ciated with the unique sample rate. Another problem to be solved by the audio processsing system according to the invention is allowing use of any sampled signal source in one signal group irrespective of whether the input sample frequency is synchronous with those of the other signal sources in the group. One group of signals may be pro¬ cessed at one sample rate: the group sample rate. The pro- vision of a sensor generating a help signal for each input signal enables the system to compensate for individual devia¬ tions from the group sample rate while reducing or elimina¬ ting any unfavourable side effects of such compensation. This problem is solved by modifying the above described system such that at least the first signal processor is ope¬ rable to process signal sequences having a first group samp¬ ling rate, said first group sampling rate deviating from the first sampling rate and by setting up the control unit such that it operates to indicate first time slots on the bus for data values associated with the first group sample rate such that the first signal processor communicates with the first input via the first time slots. Similarly the second pro¬ cessor may be set up to process signal sequences having a second group sampling rate, said second group sampling rate deviating from the second sampling rate. Brief Description of the Drawings For simple understanding of the present invention, it will be described by means of examples and with reference to the accompanying drawings, of which Figure 1 shows a schematic block diagram of two signal pro¬ cessing units according to an embodiment of the invention. Fig 2 shows a schematic block diagram of a signal processing system including a plurality of signal processing units which are physically interconnected by a time-multiplexed data bus. Figure 3 illustrates the content of one data frame for distribution on the databus shown in fig 1 or 2. Fig 4 illustrates an example of a stream of nine consecutive data frames. Figure 5 is a schematic general view of a plurality of signal sources coupled to a signal processing system according to figure 2. Detailed Description of Embodiments Fig 1 is a schematic block diagram of a signal processing unit 10 having a number of inputs I λ - I 6 for receiving sig- nals to be processed. The unit 10 also has a number of out¬ puts 0 X - 0 6 for providing processed signals. According to a preferred embodiment of the invention, the momentary status of each digitized signal comprises 24 bits, since 24 bits is a common format in the audio processing field. Those 24 bits are used for defining the amplitude of the sampled signal. It is, however, within the scope of the invention to handle signals with another number of bits. Inputs I 1 and I 2 are coupled via control ports CP X and CP 2 , respectively, to a first digital signal processing device OSP ± . When control port CP X receives a 24 bit word from input I x it may add some help information and provide a 32 bit word to digital signal processing device DSP-, . This help informa- tion, referred to as FRAC, may comprise another six bits and is described in detail later in this text . A signal processing device, hereinafter referred to as DSP, is a digital processor designed such that it is capable of performing manipulations on digital signals provided to it. According to one embodiment of the invention a signal pro¬ cessing device comprises the processor ADSP 21062 from Analog Devices. Since digital signal processors as such are well- known in the art of audio signal mixing, detailed description of the internal function of a DSP is left out of this text. A digital signal processing device DSP may, however, be capable of processing signals by using the z-transform. By mixing, in this context is meant a summation or subtraction of at least two sampled values. Mixing could also include multiplication of one or several of the values with an amplitude factor. The signal processing device DSP} has inputs 20 x and 30 x for receiving signals from the inputs I 1 and I 2 , respectively. The device DSP- L is capable of processing for example two digital signals received on inputs 20 x and 30 x and may provide two resulting signals on the outputs 0 2 and 0 2 . The signal processing device DSP- L also has an input/output port 40 coupled to a digital parallel signal bus 50. Present- ly available standard circuits provide for processing signals with longer word lengths than 24 bits. According to one embodiment a DSP can perform calculations on words with 40 bit word length, and instructions may include 48 bits. The bus 50 is also coupled to digital signal processing devices DSP 2 and DSP 3 , such that exchange of signals is pos¬ sible between the devices DSP- ! , DSP 2 and DSP 3 via the bus 50. The device DSP 2 is associated with inputs I 3 and I 4 and with outputs 0 3 and 0 4 in the same manner as the device DSP a is associated with inputs I l t I 2 and outputs O λ , 0 2 , respective¬ ly. Similarly, the third signal processing device DSP 3 is associated with the inputs I 5 , I 6 and with the outputs 0 5 , 0 6 , respectively. The bus 50 is coupled to each one of the signal processing devices DSP j^ - DSP 3 and to a real time input/output (I/O) unit 60. The I/O unit 60 is coupled to a signal distribution bus 70. The bus 70 is a signal distribution bus for connecting the signal processing unit 10 with a control unit 210. The bus 70 may also be connectable to at least one more signal proces¬ sing unit 10 2 . The unit 10 2 may be identical to the first unit 10, or it may comprise another type of hardware components for signal processing, signal editing or signal routing. Fig 2 shows a schematic block diagram of a signal processing system 200 including a number (n) of signal processing units 10-,, 10 2 to 10 n which are interconnected by the signal distri¬ bution bus 70. Additionally, the system 200 includes a con¬ trol unit 210 for providing control data to the signal pro¬ cessing units - 10 n . According to one embodiment of the invention a signal processing unit 10 is physically provided on one circuit card. A plurality of such cards interconnected by the bus 70 and cooperating with a control unit 210 consti¬ tutes a signal processing rack. The control unit 210 may include a user interface, such as a keyboard for entering data and a display for presenting sys¬ tem status to a user. Alternatively, as illustrated in Fig 2, the control unit 210 cooperates with one or several user interface units 220. Referring now to Fig 1, the bus 50 is used for distributing digitized signals between the DSP:s DSP-^ - DSP 3 . Each slot on the bus 50 can handle words with up to 48 bit word length according to the preferred embodiment. Similarly each slot on the bus 70 can handle words with up to 48 bit word length. The audio processing system according to an embodiment of the invention operates to handle stereo audio signals. Hence, one signal source provides a pair of synchronous signals such as a right signal S R and a left signal S_ . In this case the help information FRAC may comprise twelve bits The first six bits FRAC R may be provided together with the right signal S R and the remaining bits FRAC L may be provided together with the left signal S L . Hence each word in this case comprises 30 bits (24 audio amplitude bits plus 6 bits for the FRAC sig¬ nal) . The help information FRAC is further described later in this text Hence one time slot, as described above may comprise a data word with 30 or 32 bits This is however only a nonli¬ miting example of word lengths. According to another embodi¬ ment of the invention a time slot may handle words with up to 48 bits. Accordingly the audio data may comprise another number of bits per sample and so could the FRAC signal . The bus 70 operates in a Time Division Multiplex Mode (TDM) . Information is, according to a preferred embodiment of the invention, routed between the units 10 by data frames, each of which comprises 512 time slots. Each time slot comprises 48 data bits, as described above. Figure 3 illustrates the content of one data frame DF. As stated above, each data frame comprises a number of data slots S x - S M , where M may be 512. The time slots S x - S M are provided consecutively within the duration T f of the frame. The number of slots necessary m each data frame is deter- mined by the number of signals to be processed, by the sampling frequency or sampling frequencies used, and by the number of DSP:s in the system. If a sound signal is entered to one unit 10 1 , processed within that unit and transferred to an output within that unit, there is no neces¬ sity for providing any of the related audio data to the bus 70. It is sufficient that the local unit bus 50 L handles any signal routing within the unit 10^ If one audio channel requires a lot of processing it may be necessary to route the corresponding audio signals between several processing units via the bus 70. Thus a corresponding number of time slots on the bus 70 must be assigned. If, for example, 60 audio chan¬ nels are to be (1) amplifyed, (2) filtered and (3) mixed into one output signal there is a need for 2 * 60 + 1 = 121 signal processes. In a worst case 121 slots of each data frame on bus 70 will be used. By assigning DSP:s and inputs within the same units to perform the processes the number of slots needed for routing may be reduced. If the system is designed and set up to be capable of routing a maximum of N audio signals via bus 70, the data frames on the bus 70 will comprise at least N audio slots. Accordingly, the number of slots s in one data frame DF is at least M = N. In the illulustrated example of Fig 4 there are 437 audio slots . In order to provide a cost efficient system, however, a data frame DF may also include a number of data slots dedicated to control data. According to the preferred embodiment, each data frame DF comprises 437 slots for audio data and 75 slots for control data. The bus 70 operates to distribute the data frames DF at a distribution frequency f D = l/T f . According to the preferred embodiment the distribution frequency is f D = 56 kHz. When the sampling rate f Ξ associated with one of the signals is lower than the distribution frequency f D a corresponding proportion f s /f D of the frames will comprise slots provided with audio signal samples. When a channels sampling rate equals the distribution frequency f D that channels time slot will be used in all frames. In accordance with the invention it is in fact possible to handle routing of signals having a sampling rate exceeding the distribution frequency f D . This is achieved by assigning more than one slot per frame to that signal. Assigning two slots per data frame, for example, allows a signal sample rate f s twice as high as the distribu¬ tion frequency f D . f β = 2*f n . An Example of Siσnal Mixing According to one specific example, the signal input I λ is supplied with a first signal AS X having a sampling frequency of 48 kHz and a bit length of 24 bits (Fig 1) . A second signal AS 2 having the same sampling frequency is provided to input I 6 . Since input I λ is associated with DSPi and input I 6 is associated with DSP 3 , the signals will have to be distri¬ buted via the bus 50 in order to enable a mixing of the two signals. A user of the system will provide set up instruc¬ tions via the control unit 210 (see Fig 2) such that the mixed signal will be provided at a suitable signal output. The user may elect output 0 3 for delivering a mixed signal, and additionally he may enter data relating to the manner of mixing the two signals, and he may enter information to the effect that DSP 2 is to perform mixing of the two signals. The mixing could for example be a mere addition of the two input signals. According to this example, the distribution rate f D is 56 kHz, i.e. 56 thousand data frames are distributed by the bus 50 each second. Since the sample frequency of the two signals is 48 kHz, there will be 48 thousand samples provided to the inputs I x and I 6 , respectively, each second. Hence, in an average consecutive series of 56 data frames, only 48 of them will contain information relating to the signals to be mixed. Since all signals to be mixed by the DSP 2 must arrive to DSP 2 with the same data frame, it is important that DSP X and DSP 3 cooperate to put the signals AS Ύ and AS 2 in the same data frames. For this purpose, a set of control signals PCS is provided. The control unit 210 generates the control signals, PCS, which provides information about which signals should be provided in each particular data frame. The signal processing system 200 allows for several different users to be allotted a selected number of inputs and outputs, such that one user can, for example, perform mixing of three input signals providing a resulting signal to one output, while another user is allotted four other inputs for obtain¬ ing two processed output signals. The system has the advan¬ tageous quality of allowing simultaneous processing of sig¬ nals with different sample frequencies. So, for example, one user may use the system for processing signals having a sampling frequency of 44,1 kHz while another user uses the system for processing signals having a sample frequency of 32 kHz, and still another user may work with signals having a sample frequency of 48 kHz. In order to allow this versatility, the system is program- mable to be shared between a plurality of process groups, each process group being associated with a group sample rate f gg . In the above example with three users processing signals having mutually different sample rates, the control unit 210 will define three separate tasks T 1 , T 2 and T 3 , each task being allotted certain hardware inputs, hardware outputs and certain time slots. Each task involves the reception of input signals on the allotted or chosen hardware inputs, signal processing in one or several digital signal processor (s) DSP and delivery of output signal (s) on one or several hardware output (s) . A task, however, need not necessarily involve the use of a hardware input or hardware output, but could in fact use the result from another defined task within the system and provide a futher processed signal as iput to a third task. For the purpose of enabling parallel processing of different signals having mutually different sample rates the concept of control signals PCS is provided. According to an embodiment of the invention there is one control signal PCS for each group of signals associated with a unique sample rate. Ac¬ cording to the preferred embodiment there are provided eight PCS signals. The sample rate to which a PCS signal is associ¬ ated is referred to as a group sample rate f sg . The process control signals are provided in every data frame, and each PCS includes information about whether that particu¬ lar data frame includes audio data associated with the group sample rate f sg . According to the preferred embodiment the system is set up to handle a maximum of eight group sample rates simultaneously. Hence, each data frame includes eight process control signals PCS g0 -PCS g7 , each PCS being provided in a predefined time slot. As illustrated in Fig 3, the process control signal PCS g0 , which is associated with a first group sample rate f sg0 , is always provided in slot S 4 , while f sgl is provided in slot S 5 , etc. The PCS signals are generated by the control unit 210 for the purpose of informing each of the DSP:s about which data frames are associated with which group sample rates f sg . When for example task T x relates to signals all of which have a sample rate of 32 kHz and, in accordance with the preferred embodiment, the distribution frequency f D is 56 kHz, only 32 out of 56 data frames need to include audio data relating to task T 2 . The group sample rate f sg in this case is 32 kHz. Hence, a proportion, in the above described case 32 out of 56 or in other words four out of seven, of consecutive time frames, include a PCS having a boolean value TRUE indicating presence of signals whose sample rate correspond to the group samle rate . Fig 4 illustrates a stream of nine consecutive data frames, where task T x operates at a group sample rate f sgl = 32kHz. Accordingly this task uses slots in four out of seven frames when the distribution frequency is f D = 56 kHz. The first four frames OF λ - DF 4 are shaded to indicate that they include audio data relating to group sample rate f sgl . The next three data frames are illustrated as blank for indicating that they do not include audio data relating to group sample rate f sgl . Every data frame includes a PCS associated with group sample rate f sg/ and a PCS gl -value TRUE is indicated by "T" in Fig 3, while PCS gl -value FALSE is indicated by "F" . According to a preferred embodiment the use of slots will be sequenced in a finer way. For example, when the ratio between the group sample rate f sg and the distribution frequency f D is 4/7 a consecutive series of fourteen PCS signals will be assigned the following values: TFTFTFTTFTFTFT With reference to Fig. 3, each frame on bus 70 includes 512 slots S x - S 512 . The first slot S, is a header including a frame number. According to the preferred embodiment the frame numbe- ring runs from 0 (zero) to 63. This, however is only a nonlimi¬ ting example. According to one embodiment of the invention the PCS-signals comprise, not only a bolean, but also a count value indicating the frame number, where the DSP should put the result after having processed the input signals in this frame. So, for example, when the ratio between the group sample rate f sg and the distribution frequency f D is 1/2, and the present frame header number is 14 the corresponding group control signal PCS g , will include the count value 16. The count value 16 indicates that the resulting audio signal value should be handled such, by the DSP, that it becomes available in frame number 16. If the ratio f sg /F D = 1/3 the result should be provided to every third frame, which means that if the present frame has frame no. 14 the resulting processed value should be provided in frame 17. With reference to Fig. 2, the control unit is coupled to a means for establishing the ratios f sgx /f D . The system 200 includes a clock C D providing the signal with the distribution frequency f D . The clock C D is coupled to a counter means 230 which operates to calculate the ratio between the frequency f D and each of the group rates f ggD - f sg7 . When, according to the preferred embodiment, eight different sample rate groups are handled simultaneously the counter means 230 will provide eight different ratios to the control unit 210. The control unit will, in response to the ratios and the present frame header number calculate a value for each group, such that each PCS having value TRUE also includes a count value indicating the next frame which is relevant for this group sample rate. With reference to Fig. 3 a frame may also contain information from the control unit 210 to each of the units 10 x , 10 2 - 10 n . That information includes instructions as to how a particular DSP in unit 10 ^ should process a particular signal . This in¬ formation also includes set up information corresponding to the instructions provided by a user to the control nit 210 via the user mtefaces 220. This type of instructions need not be repeated as often as at the frequency f D . Accordingly slot C outo includes an address such as the address to unit 10- L , and the following 31 slots may provide instructions to the adressed u- nit . The instructions in slots C ouτo - C 0UT3:ι are read and interpreted by a local controller 240, in the addressed unit 10i . The local controller 240 x is coupled (not shown) to DSP 1; DSP 2 and to DSP 3 such that it can provide individual instructions to each DSP in accordance with orders from the control unit 210 (Fig. 1) . The unit 60 may include a two port RAM capable of receiving all the 512 slots in a frame DF from bus 70 and temprarily storing these slots. The local controller 240, is preprogrammable (by means of the control signals C ouτo - C ouτ31 ) to select those out of the 512 slots which are relevant to the DSP:s in unit 10-,. The selected slots constitute a slimmed local frame LF X . This has the advantageous effect of relieving the DSP:s from the task of receiving a lot of irrelevant information. The local frames LF, on the local buses 50 are provided with the same header numbers as the data frames OF 1 so as to enable easy identification of the temporal relation between frames. The distribution frequency on the local bus 50 is synchronized with the distribution frequency f D of the bus 70. The local controllers 240 are also coupled such that they can provide status information to the central control unit 210. According to one embodiment of the invention this is achieved via bus 70 by means of data in slots S 43 - S 74 (Fig. 3) . According to another embodiment of the invention the communica¬ tion between the control unit 210 and the local controllers 240 is executed via a separate control data bus (not shown) . An Example of Sample Rate Conversion A signal process, say process 4, may include the conversion of an input signal with an input sample rate f Ξ1 to an output signal with a different sample rate f so . If, in the system, there is a defined group sample rate f sg which is synchronous with the input sample rate f Ξ1 the sample rate conversion is achieved by assigning a hardware input, such as e.g. I 7 , to receive an input signal having, say, a 28 kHz sample rate and assigning an audio slot, e.g. slot AD 7 , in every second data frame to that input signal . The distribution frequency being f D = 56 kHz means that 28 out of 56 frames are needed and thus every second frame need include audio data relating to the 28 kHz input signal. Since f sl is synchronous with the group sample rate f sg the corresponding PCS signal PCS 4 can be used for indicating the active frames for this process. One signal processor, such as for example DSP 4 (Fig 1) may be assigned for converting the sample rate by reading the audio data in slot AD 7 when the corresponding process control signal PCS 4 indicates that the data frame includes information relating to process 4. The processor DSP 4 may operate according to a conversion algorithm (several of which are known as such) and as a result DSP 4 will generate a corresponding signal having a different sample rate f so . Since the converted signal has a different sample rate, say f so = 32 kHz, output values will have to be provided to four out of seven data frames. While the input signal with sample rate f si = 28 kHz is assig¬ ned to slot AD 7 in every second frame, the converted signal with sample frequency f so = 32 kHz may be assigned to slot AD e in four out of seven data frames . Deviation from the Group Frequency As mentioned above, the system includes eight PCS signals PCS g0 - PCS g7 , each being associated with a different group sample rate f sg0 - f gg7 . Each input which has been assigned to receive an input signal is also informed about which group sample rate the input signal is to be associated with. This information is provided to the local controllers 240 from the control unit 210 either via bus 70 as described above, or via the separate control data bus (not shown) . When, for example, input I λ is to receive a signal to be as¬ sociated with group 1 having group sample rate f sgl = 48 kHz, the control part CP 1 is informed accordingly by the local controller 240 (Fig. 1) . The PCS signal associated with the relevant group sample rate indicates the frames (LF and DF) in which the received audio signal sample values are to be provided. In the embodiment shown in Fig. 1, DPS ! performs the task of supplying the sample values to the bus 50 such that the sample values are provided to the slots indicated by control instructions from control unit 210 in the frames indicated by the relevant PCS signal. During reception of the input signal on input I λ the control port CP X will calculate a ratio between the actual received sample rate f sιl and the group sample rate f sgl . According to one embodiment of the invention, twelve bits are used for the FRAC signal at each instance. In other words, a new FRAC value consisting of 12 bits will be generated by a sensor included in control port CP-, once every time period l/f sgl . In order to enable indication of ratios larger as well as smaller than one, it is necessary to define the value such that a point is deemed to be provided at a predefined position in the FRAC word. Using twelve bits the word FRAC = 000100000000 may be deemed to be interpreted as ratio l/l . Hence, there is deemed to be a point immediately to the right of the digit 1. The FRAC value FRAC = 000010000000 is to be interpreted as 1/2, indicating that the received group sample rate f sιl is half of the group sample rate f sql . Some ratios are not easily expressed with a limited number of bits. The sensor in the control port is set up to express the FRAC value as precise as possible using 12 bits. According to the preferred embodiment the sensor included in the control port CP (fig 1) includes a counter using the group sample rate as time base. The counter runs at a frequency set to 256 times the group sample rate such that if the input sample rate is equal to the group sample rate the value provid¬ ed by the counter will be 256. Such a count value is generated for each received signal sample value. As described above, the control port CP provides the count value together with the received signal sample value to the corresponding DSP for processing or delivery to the bus 50 and or to the bus 70. When, according to another embodiment, the ratio is not ex¬ pressible using 12 bits, the sensor will round the value to the closest expressible higher value and provide the "exaggerated" value to a number of time consecutive signal slots, and then the sensor will round the value to the closest expressible lower value and provide that "understated" value to a number of time consecutive signal slots such that a moving average of a number of time consecutive FRAC signals will provide an arbit- rary precision. When the FRAC signal turns out to indicate the ratio 1/1 the received signal is synchronous with the group sample rate, and the audio signal can be processed using the received sample values without any sample rate conversion. When, on the other hand, the sensor indicates other ratios, the FRAC value will be set to differ from l/l. The local controller will be notified, and the local controller operates to inform the central control unit 210 such that the corresponding information is relayed to the user via the user interface 220. According to one embodiment of the invention, the program in the local controller 240 operates to check if one of the local DSP:s is available for sample rate conversion. If a local DSP is available, the received deviating signal will be provid¬ ed to the available DSP, which, using a conversion algorithm, operates to read the FRAC value, generate a moving average of the received FRAC values and, in response to the audio data, the moving average and the group sample rate generate a corre¬ sponding signal sequence having the group sample rate.

Claims: Claims 1. A digital audio processing system, comprising: a time-multiplexed bus (70; 50) for distributing data values in time slots (S-,- S M ) ; a first input for receiving a sequence of first data values representing a first audio signal sequence with a first sampling rate; a second input for receiving a sequence of second data values representing a second audio signal sequence with a second sampling rate; a first signal processor operable to process signal sequences having the first sampling rate; and a second signal processor operable to process signal sequences having the second sampling rate; a control unit (210) operating to indicate first time slots on the bus for data values associated with the first sample rate (f 3gl ) and to indicate second time slots on the bus for data values associated with a second sample rate, such that the first signal processor communicates with the first input via the first time slots, and the second signal processor communicates with the second input via the second time slots . 2. A system according to claim 1, modified in that at least the first signal processor is operable to pro¬ cess signal sequences having a first group sampling rate(f sgl ) , said first group sampling rate deviating from the first samp¬ ling rate; and the control unit (210) operating to indicate first time slots on the bus for data values associated with the first group sample rate (f ggl ) such that the first signal processor communicates with the first input via the first time slots. 3. A system according to Claim 1 or 2, wherein the control unit operates to define successive data frames (DF) , on the time-multiplexed bus; each data frame comprising a predetermined number (M) of slots (S ! -S M ) . 4. A system according to Claim 3, wherein the control unit (210) operates to generate a process control signal (PCS K ) relating to each selected unique sample rate (f sgk ) ; each process control signal including information for identi¬ fying data frames including data values associated with the unique sample rate (f sgk ) . 5. A system according to Claim 1, 2 or 3 , wherein the control unit (210) operates to generate a process control signal (PCS K ) relating to each unique sample rate each process control signal (PCS K ) including information which functions to identify the slots associated with the correspon¬ ding sample rate. 6. A system according to Claim 2, 3 or 4 , wherein each frame provides a predefined number (N) of slots (AD 0 -AD N-1 ) dedicated to data values comprising audio signal amplitude values; each such slot being identificable and alottable to a selec¬ table task (T) . 7. A system according to Claim 2, 3, 4, 5 or 6 , wherein each frame includes a predefined set of slots (S 4 -S 10 ) dedicated to process control signals. 8. A system according to any of the preceeding claims, wherein the control unit operates to define data frames at a prede¬ termined frequency (f D ) . 9. A system according to Claim 8 when dependent on Claim 3, wherein an updated process control signal value (TRUE, FALSE) for each group sample rate is generated at the predetermined frequency (f D ) • 10. A system according to any of the preceding claims, wherein an input for receiving a sequence of data values includes a sample rate sensor, the sample rate sensor operating to generate a value representative of the sample rate of the received signal sequence. 11. A system according to any of claims 2 - 9 wherein an input for receiving a sequence of data values includes a sensor for determing a ratio (FRAC) between the actual received sample rate (f ail ) and the group sample rate (f sg ) to which the input is associated, the sensor (CP) generating at least one digital value indica¬ ting said ratio. 12. A system according to claim 11, wherein the input { I l t CP 1 , DSP j J operates to generate a compound word comprising said ratio value and said data value, the input cooperating with the time-multiplexed bus such that said compound word is communicated to a selected signal pro¬ cessor via a slot which is indicated by the control unit (210) . 13. A system according to any of claims 4 to 12, wherein a process control signal at one point of time includes informa¬ tion for identifying a data frame at a later point of time. 14. A digital audio signal switching apparatus for an audio processing system, comprising: a time-multiplexed bus (70; 50) for routing data values in time slots (S x - S M ) ; a first input for receiving a sequence of first data values representing a first audio signal sequence with a first sampling rate; the first input being coupled to the bus (70; 50) ; a second input for receiving a sequence of second data values representing a second audio signal sequence with a second sampling rate; the second input being coupled to the bus (70; 50) ; a first signal output operable to supply signal sequen¬ ces having the first sampling rate; the first output being coupled to the bus (70; 50) ;and a second signal output operable to supply signal sequences having the second sampling rate; the second output being coupled to the bus (70; 50) ; a control unit (210) operating to indicate first time slots on the bus for data values associated with the first sample rate (f sgl ) and to indicate second time slots on the bus for data values associated with a second sample rate, such that the first signal output communicates with the first input via the first time slots, and the second signal output communicates with the second input via the second time slots, wherein the control unit further operates to define successive data frames (DF) on the time-multiplexed bus; each data frame comprising a predetermined number (M) of slots (S 1 -S M ) , and wherein the control unit (210) operates to generate a process control signal (PCS K ) relating to each selected unique sample rate (f sgk ) ; each process control signal including information for identifying data frames including data values associated with the unique sample rate (f sgk )

Inventors: AHRNE TOMAS, AHRNE, TOMAS
Applicants: AHRNE TOMAS, AHRNE, TOMAS
Application year: 1997
Main classification: G11B20
IPC codes: G11B20