Low power consumption linear voltage regulator having a fast response with respect to the load transients

Abstract: A linear type of voltage regulator, having at least one input terminal (VBAT) adapted to receive a supply voltage and one output terminal (VOUT) adapted to deliver a regulated output voltage, comprises a power transistor (M1) and a driver circuit for the transistor; the driver circuit comprises essentially an operational amplifier (OP1) having an input differential stage biased by a bias current which varies proportionally with the variations of the regulated output voltage at the output terminal (VOUT) of the regulator.

Description: This invention relates to a linear type of voltage regulator. Field of the Invention In particular, the invention relates to a linear type of voltage regulator controlled for optimum power consumption and useful with battery-powered portable devices. Such regulators must exhibit very fast response to load transients, low voltage drop, high rejection to the supply line, and above all, low current consumption so that the battery charge can be made to last longer. Background Art Current regulators are implemented using an n-channel MOS power transistor. The reason for preferring an n-channel transistor is that, for a given performance level, it allows the occupation of silicon area to be optimized and the value of the output capacitor to be reduced by at least one order of magnitude. An examplary application of a conventional type of voltage regulator is illustrated in Figure 1. A regulator of the low-drop type having an n-channel topology, such as that shown in Figure 1, requires a driver circuit OP1 being supplied a higher voltage, VCP, than the supply voltage, VBAT, a feature which has been achieved in state-of-art regulators by using a charge pump circuit 2. The operation of the device in the circuit of Figure 1 and its application will now be described in detail. The current consumption of the regulator can be calculated from the current Ires being flowed through the divider R1-R2 plus the current draw I op of the driver circuit OP1 for the power transistor M1. Since the charge pump circuit 2 used for powering the driver circuit OP1 is a multiplier-by-n of the input voltage VBAT, its current draw from the battery is n times the current I op that it delivers to the driver circuit OP1. Considering, moreover, the efficiency E ff of the charge pump circuit, the overall battery current consumption of the regulator is: I REG = n/E ff * Iop + I res . The compensation usually employed for a regulator with this topology is of the pole-zero type, where the internal zero is to cancel out the pole introduced by the load capacitor. The outcome of such compensation is that a dominant pole is obtained, which considerably slows the response to load transients and produces a large output voltage variation. A prior solution to this problem consists of increasing the bias current I op of the differential stage of the driver circuit OP1, with the consequence of increasing the overall consumption of the regulator. This solution clashes, however, with the main characteristic of battery-powered devices, whose current consumption is to be kept as low as possible. The underlying technical problem of this invention is to provide a voltage regulator of the linear type controlled for optimum current consumption, which can exhibit fast response to the load transients and minimize the average consumption of the regulator. The technical problem is solved by a circuit as indicated and defined in the characterizing parts of Claims 1 to 7. Summary of the Invention The solvent idea on which the present invention is based is one of using a driver circuit OP1 for the power transistor M1 which has an input differential stage biased by a bias current that varies proportionally with the variations in the output voltage V OUT . The features and advantages of the circuit according to this invention will be more clearly apparent from the following detailed description of embodiments thereof, shown by way of non-limitative example in the accompanying drawings. Brief Description of the Drawings Figure 1 shows a linear type of voltage regulating circuit according to the prior art; Figure 2 shows a linear type of voltage regulating circuit according to this invention; Figure 3 shows a first embodiment of a portion of the voltage regulating circuit in Figure 2; Figure 4 shows a second embodiment of a portion of the voltage regulating circuit in Figure 2; and Figure 5 shows plots versus time of some voltage and current signals, as obtained by electrical simulation of the circuit in Figure 2. Detailed Description Shown in Figure 2 is a voltage regulating circuit 1 of the linear type which embodies this invention. The regulating circuit 1 is connected between a battery (BATTERY), itself connected to a terminal VBAT of the circuit, and a load which is connected to a terminal VOUT and illustrated schematically by a generator of an equivalent current I load in parallel with a load capacitor C load having an equivalent series resistor ESR. The following circuit components make up the regulating circuit 1: a power transistor M1 of the n-channel MOS type having a main drain-source conduction path connected between the terminals VBAT and VOUT of the circuit 1; an operational amplifier OP1 which is used as a driver circuit for the power transistor M1, has an input differential stage biased by a certain bias current I op , a non-inverting input terminal connected to a voltage reference VBG, an inverting input terminal coupled to the output terminal VOUT of the circuit 1 through a resistive divider R1-R2, and an output terminal connected to the control terminal G of the power transistor M1; a charge pump circuit 2 used for powering the operational amplifier OP1; a transconductance operational amplifier OP2, I tr having an inverting (-) input terminal coupled to the output terminal VOUT of the regulator through a resistor R3, and a non-inverting (+) input terminal coupled to the output terminal VOUT of the regulator through a low-pass filter C1, R4. The low-pass filter comprises a resistor R4 connected between the regulator output terminal VOUT and the non-inverting (+) input of the transconductance operational amplifier OP2, and a capacitor C1 connected between the non-inverting (+) input of the amplifier OP2 and a fixed voltage reference GND. The operation of the circuit shown in Figure 2 will now be described. As the load current I load goes from a minimum value to a maximum value, for example, the output voltage VOUT begins to drop due to the slow driving of the transistor M1 by the operational amplifier OP1. This variation in the output voltage VOUT reflects immediately on the inverting (-) input of the transconductance operational amplifier OP2, whereas the voltage at the non-inverting input is filtered by the low-pass filter network R4-C1. Under this condition, the output of the transconductance operational amplifier OP2, consisting of a driven current generator, designated I tr in the Figure, affects the bias current of the input differential stage of the operational amplifier OP1, increasing its value. In fact, the current I tr adds to the bias current I op of the operational amplifier OP1 in the rest condition. Thus, the overall bias current of the input differential stage of the operational amplifier OP1, driving the power transistor M1, will the higher the larger is the variation in the voltage applied to the output terminal VOUT of the regulator, thereby enhancing the speed of response of the circuit. Accordingly, the current consumption of the regulator will only increase during those load transients which induce variations in the value of the output voltage VOUT. On termination of the transient, the inputs of the operational amplifier OP2 return to the same potential, restoring the current generator I tr to its very low or zero initial value. The proposed solution has been implemented using BCD (Bipolar-CMOS-DMOS) technology. Figure 3 shows diagramatically a circuit, generally referenced 3, of a first embodiment of the transconductance operational amplifier OP2, I tr using bipolar transistors. The circuit 3 comprises an input differential stage consisting of transistors Q1, Q2, Q3, Q4, a generator of a reference current I ref , and an output current mirror Q5, Q6. Assuming that all the (npn and pnp) transistors are of unity area, in a condition of constant load, the current I tr will be equal to I ref . If the output voltage VOUT tends to drop, due to a load transient, the voltage at the base of Q2 immediately follows the voltage VOUT, while the base voltage of Q1 decreases at a time constant equal to R4*C1. Under this condition, the collector currents of Q1 and Q4 increase, resulting in an increased output current I tr . Calling ΔV the voltage variation at the output VOUT, the current I tr is given by: I tr = I ref * e ΔV/(1+η)*V T where η is the emission coefficient of the transistors Q3 and Q4. When the voltage transient at the output VOUT terminates, and the voltages at the bases of the transistors Q1 and Q2 revert to the same potential, the collector currents of Q1 and Q2 are returned to a balanced condition and, accordingly, the current Itr decreases to its initial value I ref . Thus, when using the circuit of Figure 3, the bias current will only increase as the output voltage VOUT tends to drop. The steady state consumption is of 3 microAmperes for the circuit of Figure 3, and is obtained from a reference current I ref of 1 microAmpere. The consumption of the operational amplifier OP1 amounts to about 4 microAmperes; considering that this amplifier is supplied a boosted voltage VCP from the charge pump circuit 2, and that the circuit 2 is a voltage tripler, the current drawn from the battery will be 4*3=12 microAmperes. The current Ires flowing through the divider R1-R2 is 4 microAmperes. Therefore, the regulator overall consumption will amount approximately to 16 microAmperes. On the other hand, when using a conventional type of circuit, such as that shown in Figure 1, the overall consumption in the steady state condition would be about 45 microAmperes, for a like performance in terms of response to load transients. The subject circuit solution can be extended to include applications where a fast response to both connections and disconnections of the load is demanded, that is even where the load current on the voltage regulator may decrease sharply or, upon disconnection of the load, drop to zero. Figure 4 shows a second embodiment, generally referenced 4, of the transconductance operational amplifier OP2, I tr , which is also implemented by bipolar transistors. The circuit 4 comprises a double input differential stage consisting of transistors Q1, Q2, Q3, Q4, Q5, Q6, two generators of reference currents I ref1 and I ref2 , and an output current mirror Q7, Q8. The differential stage is arranged such that the transistor pair Q3 and Q4 amplify the current I ref1 on the occurrence of a negative transient of the voltage VOUT, similar to the circuit of Figure 3, while the transistor pair Q5 and Q6 amplify the current I ref2 on the occurrence of a positive transient of the voltage VOUT. Assuming unity area for all (npn and pnp) transistors, in a condition of constant load, the current I tr will be I ref =I ref1 +I ref2 . If the output voltage VOUT tends to drop, due to a sharp increase in the load current, the base voltage of the transistor Q2 also drops immediately, following the voltage VOUT, while the base voltage of Q1 decreases at a time constant equal to R4*C1. Under this condition, the collector currents of Q1 and Q4 will increase and result in the output current I tr being also increased. On the other hand, if the output voltage VOUT increases, due to a sharp decrease in the load current, then the base voltage of the transistor Q2 increases immediately, following the voltage VOUT, while the base voltage of Q1 increases at a time constant equal to R4*C1. In this case, the collector currents of Q2 and Q6 will increase and result in the output current I tr being also increased. In this way, the current I tr is increased whenever positive or negative variations occur in the output voltage VOUT of the regulator. Figure 5 shows plots of the output voltage VOUT, graph (a), and the current I tr , graph (b), as obtained by electrical simulation of the circuit. The signal VOUT pattern obtained when using this circuit, curve 41, overlaps the pattern of the same signal, curve 40, when this circuit is not used; the different voltage drop across the signal is quite apparent. It will be appreciated that this operating priciple can also be used with regulators having different topologies. The advantages of this solution can be summarized as follows: improved speed of response to transients of the differential stage of a linear regulator; low average current consumption.

Claims: A linear type of voltage regulator having at least one input terminal (VBAT) adapted to receive a supply voltage and one output terminal (VOUT) adapted to deliver a regulated output voltage, comprising: a power transistor (M1) of the n-channel type having a control terminal (G) and a main conduction path (D-S) connected between the input terminal (VBAT) and the output terminal (VOUT) of the regulator; an operational amplifier (OP1) having an input differential stage biased by a bias current, and having a first input terminal connected to a voltage reference (VBG), a second input terminal coupled to the output terminal (VOUT) of the regulator, and an output terminal connected to the control terminal of the power transistor (M1); characterized in that the bias current of the differential stage varies proportionally with the variations of the regulated output voltage at the output terminal (VOUT) and is the sum of a first current (Iop) from a constant current generator plus a second current (Itr) from a tranconductance operational amplifier (OP2) having at least one input terminal coupled to the output terminal (VOUT) of the regulator. A voltage regulator according to Claim 1, characterized in that the transconductance operational amplifier (OP2) has an inverting (-) input terminal coupled to the output terminal (VOUT) of the regulator through a resistor (R3), arid a non-inverting (+) input terminal coupled to the output terminal (VOUT) of the regulator through a low-pass filter. A voltage regulator according to Claim 2, characterized in that the low-pass filter comprises a resistor (R4) connected between the output terminal (VOUT) of the regulator and the non-inverting (+) input of the transconductance operational amplifier (OP2), and a capacitor (C1) connected between the non-inverting (+) input of said amplifier (CP2) and a fixed voltage reference (GND). A voltage regulator according to Claim 3, characterized in that the power transistor (M1) is an n-channel MOS transistor. A voltage regulator according to Claim 4, characterized in that the operational amplifier (OP1) is supplied a boosted voltage (VCP) above the supply voltage (VBAT). A voltage regulator according to Claim 5, characterized in that the first input terminal of the operational amplifier (OP1) is a non-inverting (+) input terminal, and the second input terminal is an inverting (-) input terminal coupled to the output terminal (VOUT) of the regulator through a voltage divider (R1-R2).

Inventors: MILAZZO PATRIZIA, PULVIRENTI FRANCESCO, MILAZZO, PATRIZIA, PULVIRENTI, FRANCESCO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1997
Main classification: G05F1
IPC codes: G05F1