POWER DETECTION CIRCUIT

Abstract: A power detection circuit for detecting RF power present on an RF line, preferably for a handheld mobile telephone unit, said power detection circuit comprising a coupling stage for coupling the power detection circuit to said RF line to sense RF voltage present on said RF line; a rectifier stage for rectifying said sensed RF voltage; and a temperature compensation stage for compensating temperature variations of said rectifier stage.

Description: POWER DETECTION CIRCUIT DESCRIPTION The present invention is related to a power detection circuit for detecting RF power present on an RF line. More specifically, the present invention is related to a power detection circuit for detecting RF power present on an RF line in a handheld mobile telephone unit. In order to operate a handheld mobile telephone unit in a power efficient manner, it is desirable to detect and measure the RF power present on the RF line in the handheld mobile telephone unit feeding the antenna. In the prior art, circuits are known that use linear power detection. However, in view of the large range of the signal at the output of the detection circuit, a range switching for the signal feeding into an Analog/Digital converter is required. Moreover, the power supply of such prior art circuits needs to be stabilized to provide accurate detection and measuring results. Moreover, directional RF couplers are used in these prior art solutions. Such directional RF couplers are difficult to produce and to adjust. Therefore, significant errors in the detection and measuring result may occur. In view of the above-mentioned problems, the present invention suggests a power detection circuit that provides for cost-effective and accurate detection and measurement of the RF power present on an RF line in handheld mobile telephone unit. To solve this problem, the present invention suggests a power detection circuit comprising a coupling stage for coupling the power detection circuit to said RF line to sense RF voltage present on said RF line; a rectifier stage for rectifying said sensed RF voltage; and a temperature compensation stage for compensating temperature variations of said rectifier stage. In an presently preferred embodiment of the power detection circuit according to the present invention, said rectifier stage and said temperature compensation stage are connected in series, and the DC current flowing through said rectifier stage and said temperature compensation stage is substantially equal. To operate said rectifier stage and said temperature compensation stage, they are connected to a power supply circuit. Preferably, said power supply circuit is a charge pump. In handheld mobile telephone units using GaS FET technology, such a charge pump is also neccessary for other circuits. Preferably, an evaluation stage is connected to said rectifier stage and/or said temperature compensation stage to obtain an output signal representing the RF power in a format suited for further processing. In the presently preferred embodiment said evaluation stage comprises an Analog/Digital converter circuit and and/or an amplifier circuit having a high impedance input, and wherein said rectifier stage and/or said temperature compensation stage are connected to said Analog/Digital converter circuit via said amplifier circuit. In one embodiment, said amplifier circuit is configured as a voltage follower. In a presently preferred embodiment of the power detection circuit according to the invention, said rectifier stage and said temperature compensation stage each comprises at least one diode, wherein all of said diodes have substantially identical electrical and thermal properties, and wherein preferably all of said diodes are being mounted in the same package. As the rectifier stage and the temperature compensation stage are connected in series, the diode (s) in the temperature compensation stage shares the same DC current as the diode(s) in the rectifier stage. Consequently, the temperature drift of the power detection circuit is minimised due to the same ΔV be /Δ characteristics of the diodes. In the preferred embodiment of the invention, the rectifier stage comprises one diode forming a halfwave rectifier. It is however also possible to use a fullwave rectifier circuit having two or more diodes. Preferably, said power supply circuit provides a positive output voltage (V+) and a negative output voltage (V-) ; and said rectifier stage and said temperature compensation stage each being dimensioned and calibrated such that the input of said evaluation stage is at a predetermined dc voltage level if no RF power is present on said RF line. This allows for a very simple biasing of the input of the evaluation stage. If the voltage drop over the rectifier stage and the voltage drop over said temperature compensation stage are equal, said dc voltage level being substantially zero Volt (i.e. ground level) due to the ratiometric behaviour of the power detection circuit. In the detection mode of the rectifier stage, the rectifier diode (s) act(s) as a current source and develops a voltage at the input of the evaluation stage. According to a preferred embodiment, an inductance dimensioned to parallel resonate the dynamic capacitance of said rectifier stage and said temperature compensation stage is provided in said coupling stage. Moreover, a coupling capacitance is provided in said coupling stage to feed RF voltage present on said RF line into said rectifier stage. Said temperature compensation stage is provided with at least one coupling capacitance for diverting parasitic RF components present in said temperature compensation stage. One of said coupling capacitances is provided between the cathode of the diode in the temperature compensation stage and ground. A second coupling capacitance is provided between the anode of the diode and ground. Said temperature compensation stage is provided with at least one resistance connected in series to said diode to limit the current through said temperature compensation stage. One of said resistances is provided between the cathode of the diode and the charge pu pe. A second resistance is provided between the anode of the diode and the output of the rectifier stage. This resistance form the input of said temperature compensation stage. Said rectifier stage is provided with at least one resistance connected in series to said diode to limit the current through said rectifier stage. One of said resistances is provided between the anode of the diode and the charge pumpe. A second resistance is provided between the cathode of the diode and the output of the rectifier stage. Said rectifier stage is further provided with a peak hold circuit to store the rectified voltage for subsequent processing in the evaluation stage. In a preferred embodiment, said peak hold circuit is formed by a capacitance provided between the anode of the diode and ground. The diodes of said rectifier stage and said temperature compensation stage are operated in their non-linear range of operation. Thus, the voltage signal at the output of the rectifier stage a compressed dynamic input range (e.g. 14 dB of the Analog/Digital converter) in comparison to a larger power level range of e.g. 20 dB (8 dBm - 28dBm) of the RF power signal present on the RF line. Further characteristics, advantages, features and possible modifications will become apparent to those skilled in the art in consideration of the following detailed description of the invention with reference to the enclosed drawing. The drawing shows a power detection circuit for detecting RF power present on an RF line RFL . This RF line RFL is terminated by a ferrite RF isolator FI and is feeding an antenna (not shown) of a handheld mobile telephone unit. The present power detection circuit uses the inherently present isolation of the ferrite RF isolator FI to provide directivity. The power detection circuit has a coupling stage comprising a resistance Rl, an inductance L and a coupling capacitance Cl to feed RF voltage present on the RF line RFL into the rectifier stage. One connection of the resistance Rl is connected to the RF line RFL and the other connection of the resistance Rl is connected to first connectors of the inductance L and the capacitance Cl, respectively. The second connector of the inductance L is connected to ground. The second connector of the capacitance Cl feeds into a rectifier stage. The rectifier stage comprises a resistance R2 , a diode Dl, a capacitance C2 and a resistance R3. A first connector of the resistance R2 is connected to the positive voltage outlet V+ of a charge pump CP. The second connector of the resistance R2 is connected to the second connector of the capacitance Cl of the rectifier stage and to the anode of the diode Dl. The cathode of the diode Dl is connected to a first connector of the capacitance C2 and to a first connector of the resistance R3. The second connector of the capacitance C2 is connected to ground. The second capacitance C2 serves as a peak hold capacitance. The second connector of the resistance R3 forms the ouput of the rectifier stage and feeds into a temperature compensation stage and an evaluation stage. The temperature compensation stage comprises a resistance R4, a second diode D2 , two capacitances C3 , C4 and a further resistance R5. A first connector of the resistance R4 forms the input of the rectifier stage and is connected to the second connector of the resistance R3. The second connector of the resistance R4 is connected to the anode of the second diode D2 and a first connector of the capacitance C3. The second connector of the capacitance C3 is connected to ground. The cathode of the second diode D2 is connected to a first connector of the capacitance C4 and to a first connector of the resistance R5. The second connector of the capacitance C5 is connected to ground. The second connector of the resistance R5 is connected to the negative voltage outlet V- of the charge pump CP. A change in the positive supply voltage V+ maps directly into a change corresponding change of the negative supply voltage V-. Thus, as the positive supply voltage V+ goes more positive, the negative supply voltage V- goes more negative, and vice versa. The net result of the dc voltage level at the centre tap CT, i.e. the output of the rectifier stage and the input of the temperature compensation and evaluation stages is nil. The resistances R2 , R3 , R4 , and R5 connected in series to the diodes Dl, D2 define and limit the current flowing through temperature compensation stage and the half wave rectifier stage. The ratio of the resistances R2 + R3 over the resistances R4 + R5 defines the level of the dc voltage at the centre tap CT. If R2 + R3 equals R4 + R4 , the dc voltage at the centre tap CT is nominally at ground level. By changing this ratio, the bias voltage for the input of the evaluation stage can be defined. This can be useful for Analog/digital converters requiring a certain voltage level at the input to operate properly. The DC output voltage of the rectifier stage is proportional to the RF voltage present on the RF line RFL. The evaluation stage comprises an operational amplifier OPA configured as a voltage follower and an Analog/Digital converter ADC to convert the DC output voltage of the rectifier stage into a digital representation thereof. The non-inverting input of the operational amplifier OPA is connected to the second connector of the resistance R3 , i.e. the output of the rectifier stage and the input of the temperature compensation stage. The output of the inverting input of the operational amplifier OPA is looped back to the inverting input of the operational amplifier OPA and feeded into input of the Analog/Digital converter ADC. The output of the Analog/Digital converter ADC having a n bit wide data path form the output of the power detection circuit. As the rectifier stage and the temperature compensation stage, and more specifically, the first and second diodes Dl, D2 are connected in series, the DC current flowing therethrough is substantially equal. The first and second diodes Dl, D2 have substantially identical electrical and thermal properties and are mounted in the same package P. Thus, any V e change due to temperature variations is nullified due to the ratiometric behaviour of the power detection circuit. Hence, no regulated power supply is required. This is specifically important in mobile handheld telephones where the battery voltage changes. The diodes Dl, D2 are operated in their non-linear range of operation. Thus, their dynamic impedance is varying during the operation in dependance of the RF power level present on the RF line RFL. The inductance L is dimensioned to parallel resonate the dynamic capacitance of the rectifier stage and the temperature compensation stage. This results in a high detector impedance and hence in large- ouptut voltages at the centre tap CT for very little loading of the RF line RFL. The input impedance of the detector decreases with increasing power levels on the RF line Rfl. This leads to compression of the detection range. More specifically, the present power detection circuit compresses the 20 dB of detection range into 14 dB input dynamic range of the Analog/Digital converter. Thus, no range switching stage is required intermediate the output of the rectifier stage and the input of the Analog/Digital converter. The capacitances C3 , C4 at the anode and the cathode of the second diode D2 are provided to divert any spurious RF signals present in the temperature compensation stage to ground.

Claims: CLAIMS 1. A power detection circuit for detecting RF power present on an RF line, preferably for a handheld mobile telephone unit, said power detection circuit comprising: - a coupling stage (Rl, L, C2) for coupling the power detection circuit to said RF line (RFL) to sense RF voltage present on said RF line; - a rectifier stage (Dl, C2 , R3) for rectifying said sensed RF voltage; and - a temperature compensation stage (R , D2) for compensating temperature variations of said rectifier stage (Rl, L, C2) . 2. The power detection circuit according to claim 1, wherein - said rectifier stage (Dl, C2 , R3) and said temperature compensation stage (R4, D2) are connected in series, and the DC current flowing through said rectifier stage and said temperature compensation stage is substantially equal. 3. The power detection circuit according to claims 1 or 2 , wherein - said rectifier stage and said temperature compensation stage are connected to a power supply circuit (CP) , said power supply circuit preferably being a charge pump (CP) . 4. The power detection circuit according to any of claims 1 to 3 , wherein - an evaluation stage (OPA, ADC) is connected to said rectifier stage and/or said temperature compensation stage. 5. The power detection circuit according to claim 4, wherein - said evaluation stage comprises an Analog/Digital converter circuit (ADC) and and/or an amplifier circuit (OPA) having a high impedance input, and wherein said rectifier stage and/or said temperature compensation stage are connected to said Analog/Digital converter circuit via said amplifier circuit. 6. The power detection circuit according to claim 1, wherein - said rectifier stage and said temperature compensation stage each comprises a diode (Dl, D2) , wherein both diodes (Dl, D2) have substantially identical electrical and thermal properties, and wherein preferably both diodes are being mounted in the same package (P) . 7. The power detection circuit according to any of claims 3 or , wherein - said power supply circuit (CP) provides a positive output voltage (V+) and a negative output voltage (V-) ; and - said rectifier stage and said temperature compensation stage each being dimensioned and calibrated such that the input of said evaluation stage is at a predetermined dc voltage level if no RF power is present on said RF line (RFL) , preferably said dc voltage level being substantially zero Volt (i.e. ground level). 8. The power detection circuit according to claim 1, wherein said coupling stage is provided with - an inductance (L) dimensioned to parallel resonate the dynamic capacitance of said rectifier stage and said temperature compensation stage, and - a coupling capacitance to feed RF voltage present on said RF line into said rectifier stage. 9. The power detection circuit according to claim 1, wherein - said temperature compensation stage is provided with at least one coupling capacitance for diverting parasitic RF components present in said temperature compensation stage. 10. The power detection circuit according to claim 6, wherein - said temperature compensation stage is provided with at least one resistance (R5) connected in series to said diode (D2) to limit the current through said temperature compensation stage. 11. The power detection circuit according to claim 6, wherein - said rectifier stage is provided with at least one resistance (R2) connected in series to said diode (Dl) to limit the current through said rectifier stage. 12. The power detection circuit according to claim 1, wherein - said rectifier stage is provided with a peak hold circuit (C2). 13. The power detection circuit according to claim 1, wherein diodes of said rectifier stage and said temperature compensation stage are operated in their non-linear range of operation.

Inventors: DESAI RAJ, DESAI, RAJ
Applicants: DESAI RAJ, MAXON SYSTEMS INC LONDON LTD, DESAI, RAJ, MAXON SYSTEMS, INC. (LONDON) LTD.
Application year: 1997
Main classification: H04B17
IPC codes: G01R21, H04B17