Multiplication and addition circuit

Abstract: The present invention has an object to provide an accumulation and addition circuit able to accumulate and add digital multipliers for a plurality of analog voltage, and lower data transmission errors. The present invention performs addition of each bit corresponding to the multiplier of a plurality of data first, and adds weights corresponding to the weight of each bit. Addition is performed through multiplier circulation without data transmission.

Description: The present invention relates to a multiplication and addition circuit for multiplying digital multipliers and adding for a plurality of analog voltages. The applicant of the present invention proposes in Japanese Patent Publication No. 6-168349 a usable multiplication circuit for the above field, which realizes multiplication of an analog voltage and a digital multiplier without analog-to-digital (A/D) conversion. FIG. 9 shows a conventional circuit. Input voltage X is input to capacitive coupling CP including capacitances CC0 to CC7 through switches SW1 to SW8. The output of CP is input to inverting amplifying circuit INV2, whose output is connected to its input through feedback capacitance C3. CP outputs the result of multiplication and addition operation for X wherein multiplication is done by multiplying weight which is proportional to each capacitance, and INV2 transmits the outputs to the next stage with good linearity due to the large gain and the feedback system of C3. As each capacitance of CP corresponds to each binary bit, multiplications with binary numbers can be performed by controlling the opening and closing of each switch. Through intermediate capacitance C4, the output of INV2 is connected to inverting amplifying circuit INV3, whose input and output are connected through feedback capacitance C5. The output of CP is transmitted to the two successive stages so as to a non-inverted output is obtained. In CP, capacitance CC8 is also connected in parallel to other capacitances. CC8 is connected to X through switch SW9, inverting amplifying circuit INV1 and capacitance C1, sequentially. The input and output of INV1 are connected through feedback capacitance C2. When switch SW9 is closed, inverted X (-X) is output with good linearity. US-5,396,446 teaches a multiplication and addition circuit for performing multiplication and addition by applying two digital factors on a plurality of analog voltages. This circuit comprises a plurality of multiplexers for performing one bit multiplication of every bit corresponding to each digital multiplier. In FIG. 9, many unit capacitances are needed because CC0 to CC7 must have a capacity ratio corresponding to their binary bit weight. The number of capacitances for multiplication especially increases as they perform multiplication and addition on larger number of data, resulting in large-size circuits. It is the object of the invention to reduce the total capacitance of all capacitors used in a multiplication and addition circuit. This object is solved by the subject matter of claim 1. Preferred embodiments of the invention are the subject matter of the dependent claims. An advantage of the invention is that a sole multiplication circuit is used for a plurality of analog values which may be stored in sample and hold circuits. The total number of unit capacitances used in a multiplication circuit can be advantageously further reduced by providing two additional inverters. In the following an embodiment of the multiplication and addition circuit according to the invention is described according to the attached drawings. FIG. 1 shows an embodiment of an addition and multiplication circuit of the present invention. FIG. 2 shows a block diagram of the sampling and holding portion and addition portion in the embodiment. FIG. 3 shows an addition circuit with an included addition portion. FIG. 4 shows a multiplication portion in the embodiment. FIG. 5 shows another multiplication portion. FIG. 6 shows an inverted amplifying circuit. FIG. 7 shows the reference voltage generating circuit. FIG. 8 shows a block diagram of the sampling and holding portion and addition portion of another embodiment. FIG. 9 shows a conventional multiplication circuit. FIG. 10 shows timings of the relationship between multipliers and analog voltage. FIG. 1 shows a multiplication and addition circuit. In FIG. 1, addition portion ADD is connected to sampling and holding circuit SH to which analog input voltage Vin is input, a plurality of analog voltages stored in SH is added (described in detail later), and the addition result is multiplied by multiplication portion MUL (described in detail later). Control signal CTRL1 is input to SH from multiplier control circuit CTRL, and control signal CTRL2 is input to ADD from CTRL. SH and ADD are structured as in FIG. 2. In SH, a plurality (n number) of sampling and holding circuits SH1 to SHn are connected in serial, and in ADD, a plurality (2k number) of addition circuits are connected in parallel. Here, n is the number of data which are input parallelly, and k is the bit number of a digital multiplier. Each sampling and holding circuit is a known structure, which stores the input analog voltage, and transmits it to a sampling and holding circuit in the next step. The stored analog voltages are parallelly output to digital multipliers wherein each digital multiplier multiplies one analog voltage with one bit. The 2k number of outputs are parallelly input to addition circuits ADD1p to ADDkp, and ADD1m to ADDkm. These addition circuits are similarly structured: ADD1p to ADDkp correspond to the positive multipliers, and ADD1m to ADDkm correspond to the negative multipliers. The sampling and holding timings of each sampling and holding circuit are set by CTRL1, and the value of multiplier of each addition circuit is set by CTRL2. FIG. 3 shows an addition circuit ADDIp having a number of n multiplexers MUX1 to MUXn. These correspond to a number of n inputs VS1 to VSn from SH1 to SHn, with VS1 to VSn and reference voltage Vref being input to its respective multiplexer. MUX1 to MUXn selectively output VS1 to VSn or Vref, and the outputs are input to capacitive coupling CP3 containing capacitances C31 to C3n. The output of CP3 is input to inverting amplifying circuit INV3, whose output is connected to its input through by feedback capacitance C3F. Assuming that the control signals of MUX1 to MUXn are bp11 to bp1n, and those for outputting VS1 to VSn and Vref are 1 and 0, respectively, output A1p of ADD1p is calculated by formula (1), with the voltage measurement reference assumed to be Vref in all operations hereinafter: When the i-th multiplier is positive and its LSB (Lowest Significant Bit) is 1, bp1i=1, and when the multiplier is positive and LSB is 0 or the multiplier is negative, bp1i=0. Generalizing, the output of j-th addition circuit Ajp is as in formula (2): Assuming the control signal is bmji, the outputs of addition circuits A1m to Anm corresponding to negative multipliers are expressed in formula (3): The ratio of capacitances in the circuit in FIG. 3 is shown in formula (4): C 31 = C 32 = ... = C 3 n = C 3 F n Outputs A1p through Akp and A1m through Akm of ADD1p through ADDkp and ADD1m through ADDkm are input to multiplication portion MUL in FIG. 4. In MUL, A1p through Akp are integrated in capacitive coupling CP41, and A1m through Akm are integrated in capacitive coupling CP42. CP41 includes capacitances C411 through C41k which correspond to A1p through Akp, and CP42 includes C421 through C42k which correspond to A1m through Akm. The output of CP42 is input to inverting amplifying circuit INV41, whose output is connected to its input through feedback capacitance C4F1, and it is also connected to inverting amplifying circuit INV42 through intermediate capacitance CC4. The output of INV42 is connected to its input through feedback capacitance C4F2, similar to INV41. The output of CP41 is connected to INV42 in parallel to CC4, and MUL generates output R, as shown by formula (5): Here, the capacitance ratios in FIG. 4 and in formula (4) are shown in Table 1. Capacitance Ratio C3j (j=1 to n) 1 C3F n C42i (i=1 to k) 2 i-1 C41i (i=1 to k) 2 i-1 C4F1 2 k C4F2 2 k CC4 2 k From the ratios in Table 1 and formulas (2), (3) and (5), formula (6) is derived: Multiplication is possible with multipliers of k-digit binary numbers including any symbol. The unit capacitance number N for structuring the capacitances used in the above circuit is estimated as in Table 2. Symbol showing capacitances Capacity (Number of Unit Capacitances) Number per Circuit Number of Circuits Total Number of Unit Capacitances C3j (j=1 to n) 1 n 2k 2kn C3F n 1 n n C41i & C42i (i=1 to k) 2° to 2 k-1 2k 1 2 k+1 -2 C4F1, C4F2, CC4 2 k 3 1 3 X 2 k Total 5 X 2 k + 2kn+n-2 In a conventional circuit, since multiplications are performed prior to other operations, at least a number N' of unit capacitances is necessary for multiplication and addition using k-bit multipliers for n bits of data as calculated by formula (7): N' = n •2 k +2 + 2 n Assuming that the value of n is nc when N=N', the comparison between N and N' is shown in Table 3. k nc when N>nc 4 1.36 N'>N 8 1.27 N'>N 16 1.25 N'>N 32 1.25 N'>N When the parallel data number is two to four (it is actually far larger, 100 or more), this circuit needs fewer unit capacitances than conventional circuits. This means that, in actual use, the present invention invariably requires fewer unit capacitances and inverting amplifying circuits than conventional ones. FIG. 5 shows another embodiment of multiplication portion MUL. In this MUL, capacitive couplings CP51 for the positive multiplier and CP52 for the negative multiplier are connected to three stages of serial inverting amplifying circuits INV51, INV52 and INV53, and one stage inverting amplifying circuit INV54, respectively, at their outputs. Outputs of INV51 to INV54 are connected to their own inputs through feedback capacitances C5F1, C5F2, C5F3 and C5F4, respectively. Intermediate capacitances CC51 and CC52 are connected between C5F1 and C5F2, and between C5F2 and C5F3, respectively. The output of INV54 is connected to intermediate capacitance CC53, whose output is input to INV53 parallel to the output of CC52. In the present embodiment, although the number of inverting amplifying circuits increases, the number of unit capacitances is further decreased compared to the above embodiment, shown in Table 4. Symbol showing capacitances Capacity (Number of Unit Capacitances) Number Number of Circuits Total Number of Unit Capacitances C51j & C52j 2 o to 2 k-1 2k 1 2 k+1 -2 C5F1 & C5F4 2 k 2 1 2 X 2 k C5F2, CC51 to CC53 1 4 1 4 C5F3 1 1 1 1 Total 2 k+2 +3 On the other hand, the unit capacitance total number in the circuit in FIG. 4 is 6 X 2 k -2 When 2·2 k >5, that is, when k>1.58 (usually k is around 8), the circuit in FIG. 5 has fewer unit capacitances than that in FIG. 4, which means that in practical terms this is always so. As the capacity ratio of the last-stage feedback capacitance C5F3 (2) is far less than that of C4F2 (2 k ), the circuit response is remarkably improved. Another unit capacitance number N for C4F2 having a size of 2 k+1 unit capacitances is estimated in Table 5. Symbol showing capacitances Capacity (Number of Unit Capacitances) Number Number of Circuits Total Number of Unit Capacitances C3j (j=1 to n) 1 n 2k 2kn C3F n 1 2k 2kn C41i (i=1 to k) & C42i (i=1 to k) 2 i=1 2 1 2 k+1 -2 C4F1 & CC4 2 k 2 1 2 k+1 C4F2 2 k+1 1 1 2 k+1 Total 3 X 2 k+1 +4kn-2 Note: A capacitance for multiplication includes the minimum bit dummy. In a conventional circuit, since multiplications are performed prior to other operations, at least N' number of unit capacitances is necessary for multiplication and addition using k-bit multipliers for h data, as calculated by formula (7) above. Assuming that the value of n is nc when N=N', the comparison between N and N' is shown in Table 6. k nc when N>nc 4 1.88 N'<N 8 1.54 N'<N 16 1.50 N'<N 32 1.50 N'<N When the parallel data number is two to five (it is actually far larger, 100 or more), this circuit needs fewer unit capacitances than conventional circuits. This means that, in actual use, the present invention invariably requires fewer unit capacitances and inverting amplifying circuits than conventional ones. In FIG. 5, the output of INV54 is connected to intermediate capacitance CC53, whose output is input to INV53 parallel to the output of CC52. In the present embodiment, although the inverting amplifying circuit number increases, the unit capacitance number further decreases, as shown in Table 7. Symbol showing capacitances Capacity (Number of Unit Capacitances) Number Number of Circuits Total Number of Unit Capacitances C51i (i=1 to k) & C52i (i=1 to k) 2 i-1 2k 1 2 k+1 -2 C5F1 & C5F4 2 k 2 1 2 k+1 C5F2, CC51 to CC53 1 4 1 4 C5F3 2 1 1 2 Total 2 k+2 +4 On the other hand, the unit capacitance total number in the circuit in FIG. 4 is 3 × 2 k+1 -2. When 2 k >3, that is, when k>1.58 (usually k is around 8), the circuit in FIG. 5 has fewer unit capacitances than that in FIG. 4, which means that in practical terms this is always so. As the capacity ratio of the last-stage feedback capacitance C5F3 (2) is far less than that of C4F2 (2 k+1 ), the response of the circuit is remarkably improved. Inverting amplifying circuit INV3 in FIG. 3 is structured as in FIG. 6, and other inverting amplifying circuits as are similarly structured. In INV3, CMOS inverters INV61, INV62 and INV63 are serially connected in three stages, and the output of the last-stage CMOS inverter is connected to the input of the first-stage CMOS inverter through feedback capacitance C3F. From input VI6, the inverting amplifying circuits generate inverted output V06 with good linearity due to its large gain and effects of feedback loop. The output of INV63 is connected to low supply-voltage Vss (a ground, for example) through grounded capacitance CL, and oscillation of inverting amplifying circuit including the feedback loop is prevented because of its low-pass filter effect. The output of INV62 is connected to supply voltage Vdd through resistance RE1 and capacitance CE1, and connected to low supply-voltage Vss through resistance RE2 and capacitance CE2. These resistances are the load of the inverting amplifying circuits, functioning to control the gain and prevent oscillation. CE1 and CE2 interrupt low-frequency penetrating current to minimize electric power consumption in the resistances. Oscillation caused by the increase of load of the inverting amplifying circuits can be prevented by a serial RC-circuit connecting the input and output of INV62 or INV63 instead of RE1 and RE2. This configuration results in a smaller size of circuit than that in FIG. 6. FIG. 7 shows circuit VR for forming the reference voltage Vref. This is configured by reducing input VI6 and feedback capacitance C3F of the circuit in FIG. 6. It includes CMOS inverters INV71, INV72, INV73, grounded capacitance CL, resistances RE1 and RE2, and capacitances CE1 and CE2. VR outputs the stable value at which the input is in balanced status as the reference voltage Vref. This stable point can be freely changed by setting the threshold voltage of the CMOS inverters. To realize the dynamic range in both positive and negative directions maximum, Vref is set Vdd/2. FIG. 8 shows another embodiment of a sampling and holding portion and an adding portion. Analog input voltage is parallelly connected to each sampling and holding circuit. Sampling and holding portions are controlled by control signal CTRL1 so as to replace the oldest analog input voltage by the newest. With no data transmission necessary between the sampling and holding circuits, transmission errors are not generated. Here, as in FIG. 2, circuit timing is described given eight sampling and holding circuits. Assuming that the analog voltage stored in sampling and holding circuits SH1 to SH8 is V(SH1) to V(SH8), multipliers adopted by addition circuits ADD1 to ADD8 are M(ADD1) to M(ADD8), and sampling interval is Δt, the stored voltage and multipliers change from t0 to t0+3 Δ t, as in FIG. 10. In FIG. 10, at time t0, assuming that analog voltage is sequentially stored in SH8, SH7, ... SH1, and multipliers m1 to m8 are adopted by ADD1, ADD2, ... ADD8, respectively, the oldest analog voltage Vin (t0-7 Δt) is stored in SH8. At time t0+Δt, the oldest analog voltage Vin (t0-7 Δt) is renewed by the newest voltage Vin(t+Δt). The multipliers that is multiplied to each analog voltage are circulated by one step, so that eventually, ADD1 to ADD7 adopt m2 to m8, respectively, and ADD8 adopts ml. After this, the oldest analog voltage is renewed by the newest, and the multipliers similarly circulate, producing the effect that the multipliers are fixed and analog voltage is sequentially transmitted. As mentioned above, when data is not transmitted, the multipliers should be sequentially changed; therefore, multipliers are circularly changed by control signal CTRL2 in each addition circuit. The multiplication and addition circuit according to the present invention performs addition by every bit corresponding to the multiplier of a plurality of data beforehand, then processes weighing to the addition results according to the weight of each bit. Therefore, multiplication and addition can be performed by digital multipliers with smaller number of capacitances for a plurality of analog voltage.

Claims: A multiplication and addition circuit for performing multiplication and addition by applying digital factors on a plurality of analog voltages, comprising: i) a plurality of multiplexers (MUX1...MUXn) for performing one-bit multiplication of every bit corresponding to each digital multiplier; characterized by: ii) a plurality of addition circuits (ADD1p...ADDkp, ADD1m...ADDkm) for adding multiplexer outputs of each corresponding bit by a capacitive coupling (C31...C3n); and iii) a multiplication circuit (MUL) for adding weighted outputs (A1m...Akm, A1p...Akp) of said addition circuits by other capacitive coupling according to each corresponding bit weight. A multiplication and addition circuit as claimed in claim 1, wherein said addition circuits further comprise: i) a plurality of first addition circuits (ADD1p...ADDkp) for adding multiplexer outputs of every corresponding bit of a positive multiplier; and ii) a plurality of second addition circuits (ADD1 m...ADDkm) for adding multiplexer outputs of every corresponding bit of a negative multiplier; wherein said multiplication circuits (MUL) comprise: i) a first multiplication circuit (CP41; CP51) for adding outputs of said first addition circuits (A1p...Akp) with weights by capacitive coupling according to each corresponding bit weight; ii) a second multiplication circuit (CP42; CP52) for adding outputs of said second addition circuits with weights by other capacitive coupling according to each corresponding bit weight; and iii) a subtraction circuit (INV41, INV42; INV52; INV53) for subtracting said second multiplication circuit output from said first multiplication circuit output. A multiplication and addition circuit as claimed in claims 1 or 2, wherein said analog voltage is initially stored by a sampling and holding circuit (SH1...SHn). A multiplication and addition circuit as claimed in one of claims 1 to 3, wherein analog voltages and a reference voltage (Vref) are input to said plurality of multiplexers, for alternatively outputting said analog or reference voltage. A multiplication and addition circuit as claimed in one of claims 1 to 4, wherein said multiplication circuit (MUL) comprises: i) a capacitive coupling for adding said addition circuit outputs with weights according to each corresponding bit weight; ii) an inverting amplifying circuit (INV41, INV42), to which said capacitive coupling outputs are connected, comprising CMOS inverters serially connected in an odd number of stages; and iii) a feedback capacitance for connecting said inverting amplifying circuit output to its input. A multiplication and addition circuit as claimed in claim 4, wherein said first addition circuit comprises: i) a capacitive coupling (CP3) for adding multiplexer outputs of each bit corresponding to a positive multiplier; ii) an inverting amplifying circuit (INV3) consisting of an odd number of stages (INV61, INV62, INV63) of serial CMOS inverters connected to said capacitive coupling outputs; and iii) a feedback capacitance (C3F) for connecting an output of said inverting amplifying circuit to its input. A multiplication and addition circuit as claimed in claim 2 or 6, wherein said subtraction circuit comprises an intermediate capacitance (CC4) being connected to an output of said first multiplication circuit (CP41), and also being connected to said inverting amplifying circuit (INV41) of said second multiplication circuit (CP42) parallel to said capacitive coupling of said multiplication circuit (CP41). A multiplication and addition circuit as claimed in claim 2 or 6, wherein said subtraction circuit comprises: i) a first intermediate capacitance (CC51), a first inverting amplifying circuit (INV52) consisting of an odd number of stages of serial CMOS inverters, a second intermediate capacitance (CC52), and a second inverting amplifying circuit (INV53) consisting of an odd number of stages of serial CMOS inverters connected serially and sequentially to the output of said first multiplication circuit (CP51); ii) a third intermediate capacitance (CC53) coupled to said output of said second multiplication circuit (CP52); and iii) the output of said third intermediate capacitance (CC53) connected to said second inverting amplifying circuit (INV53) parallel to said second intermediate capacitance (CC52). A multiplication and addition circuit as claimed in claim 3, wherein said plurality of multiplexers multiply said analog voltage which is output from said sampling and holding circuit (SH1...SHn) by a bit of one digital factor, said multiplication and addition circuit comprising a multiplier controlling means for synchronously circulating the settling time of each bit multiplexer, and further for replacing the oldest analog voltage by the newest in said sampling and holding circuit.

Inventors: MOTOHASHI KAZUNORI, SHOU GUOLIANG, MOTOHASHI, KAZUNORI, SHOU, GUOLIANG
Applicants: YOZAN INC, YOZAN INC.
Application year: 1997
Main classification: G06J1
IPC codes: G06J1