Gain-variable amplifier having small DC output deviation and small distortion

Abstract: In a gain-variable amplifier, a first differential amplifier (1) is formed by first and second transistors (Q 1 , Q 2 ) having a common emitter connected to a first constant current source, a second differential amplifier (2) is formed by third and fourth transistors (Q 3 , Q 4 ) having a common emitter connected to a collector of the second transistor, and a third differential amplifier (3) is formed by fifth and sixth transistors (Q 5 , Q 6 ) having a common emitter. Collectors of the fifth and sixth transistors are connected to collectors of the third and fourth transistors, respectively. A seventh transistor is connected between the common emitter of the fifth and sixth transistors and a second constant current source.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a gain-variable amplifier used as an automatic gain control (AGC) circuit or the like. Description of the Related Art A first prior art gain-variable amplifier includes a first differential amplifier formed by first and second transistors having a common emitter connected to a constant current source, a second differential amplifier formed by third and fourth transistors connected to the collector of the second transistor, and a third differential amplifier formed by fifth and sixth transistors having a common emitter connected to the collector of the first transistor. The first differential amplifier receives an input voltage. Also, the collectors of the third and fourth transistors are connected to the fifth and sixth transistors, respectively. The second and third differential amplifiers are controlled by a gain control voltage. This will be explained later in detail. In the first prior art gain-variable amplifier, however, since the gain characteristics have an inflection point, it is difficult to control the gain by the gain control voltage. Also, the phase of the output voltage is inverted at the inflection point. Since only half of the exploitable range of the gain control voltage is utilized, the range of the gain control voltage is substantially reduced. A second prior art gain-variable amplifier includes a first differential amplifier formed by first and second. transistors having a common emitter connected to a first constant current source, a second differential amplifier formed by third and fourth transistors connected to the collector of the second transistor, and a third differential amplifier formed by fifth and sixth transistors having a common emitter connected to a second constant current source. Also, in this case, the first differential amplifier receives an input voltage. Also, the collectors of the third and fourth transistors are connected to the fifth and sixth transistors, respectively. The second and third differential amplifiers are controlled by a gain control voltage. This will be explained later in detail (see JP-A-3-32209). In the second prior art gain-variable amplifier, since the gain characteristics have no inflection point, it is easy to control the gain by the gain control voltage. Also, the phase of the output voltage is never inverted. Since a full range of the exploitable range of the gain control voltage is utilized, the range of the gain control voltage is substantially increased. In the second prior art gain-variable amplifier, however the deviation of the DC component of the output voltage depending upon the gain control voltage is large. This large deviation can become enormous in the manufacture of an integrated circuit due to deviations in the current amplification factor. Further, a signal may be subjected to distortion and degradation due to the difference in collector-emitter voltage between the first and second transistors. For example, in radio transmitter/receiver sets, the distortion appears as harmonic distortion of a transmitting/receiving frequency which degrades the operating characteristics. SUMMARY OF THE INVENTION It is an object of the present invention to reduce the deviation of the DC component of an output voltage and the signal distortion in a gain-variable amplifier. According to the present invention, in a gain-variable amplifier, a first differential amplifier is formed by first and second transistors having a common emitter connected to a first constant current source, a second differential amplifier is formed by third and fourth transistors having a common emitter connected to a collector of the second transistor, and a third differential amplifier is formed by fifth and sixth transistors having a common emitter. Collectors of the fifth and sixth transistors are connected to collectors of the third and fourth transistors, respectively. A seventh transistor is connected between the common emitter of the fifth and sixth transistors and a second constant current source. Also, an eighth transistor may be connected to the collector of the first transistor. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more clearly understood from the description as set forth below, with reference to the accompanying drawings, wherein: Fig. 1 is a circuit diagram illustrating a first prior art gain-variable amplifier; Fig. 2 is a graph showing the gain characteristics of the gain-variable ampligfier of Fig. 1; Fig. 3 is a circuit diagram illustrating a second prior art gain-variable amplifier; Fig. 4 is a graph showing the gain characteristics of the gain-variable ampligfier of Fig. 3; Fig. 5 is a circuit diagram illustrating a first embodiment of the gain-variable amplifier according to the present invention; Fig. 6 is a circuit diagram illustrating a second embodiment of the gain-variable amplifier according to the present invention; Fig. 7 is a circuit diagram illustrating a third embodiment of the gain-variable amplifier according to the present invention; and Figs. 8, 9, 10 are circuit diagrams of modifications of the gain-variable amplifiers of Figs. 5, 6 and 7, respectively; and Figs. 11, 12 and 13 are circuit diagrams of other modifications of the gain-variable amplifiers of Figs. 5, 6 and 7, respectively. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before the description of the preferred embodiments, prior art gain-variable amplifiers will be explained with reference to Figs. 1, 2, 3 and 4. In Fig. 1, which illustrates a first prior art gain-variable amplifier, a differential amplifier 1 is formed by two NPN type transistors Q 1 and Q 2 having a common emitter connected via a constant current source IS 1 whose current is I 1 , to a ground terminal GND. An AC input voltage V in is applied between bases of the transistors Q 1 and Q 2 . The differential amplifier 1 amplifies the input voltage V in . Also, a differential amplifier 2 is formed by two NPN type transistors Q 3 and Q 4 having a common emitter connected to the collector of the transistor Q 2 of the differential amplifier 1. Similarly, a differential amplifier 3 is formed by two NPN type transistors Q 5 and Q 6 having a common emitter connected to the collector of the transistor Q 1 of the differential amplifier 1. The collectors of the transistors Q 3 and Q 5 are connected by way of a load resistor R 1 to a power supply terminal V cc , while the collectors of the transistors Q 4 and Q 6 are connected by way of a load resistor R 2 to the power supply terminal V cc . Note that the AC input voltage V in is biased by a DC voltage V O . Also, a DC bias voltage V cO is applied to the bases of the transistors Q 3 and Q 6 , and a gain control voltage V c is applied to the bases of the transistors Q 4 and Q 5 . The load resistor R 2 provides an output voltage V out at an output terminal OUT. In this case, a current I O flowing through the resistor R 2 is formed by a positive phase current I, flowing through the transistor Q 4 of the differential amplifier 2 and the transistor Q 2 of the differential amplifier 1 and a negative phase current I flowing through the transistor Q 6 of the differential amplifier 3 and the transistor Q 1 of the differential amplifier 1. In Fig. 1, when the gain control votlage V c is positive, the positive phase current I. is greater than the negative phase current I - . In this case, the higher the gain control voltage V c , the larger the positive phase current I,. As a result, as shown in Fig. 2, the gain is increased as the gain control voltage V c is increased. On the other hand, when the gain control voltage V c is negative, the negative phase current I - is greater than the positive phase current I + . In this case, the lower the gain control voltage V c , the larger the negative phase current I - . As a result, as shown in Fig. 2, the gain is increased as the gain control voltage V c is decreased. In addition, if V c = 0V, the voltage at the bases of the transistors Q 3 and Q 6 is equal to the voltage at the bases of the transistors Q 4 and Q 5 . Therefore, the positive phase current I + is equal to the negative phase current I - . In this case, the positive phase current I + offsets the negative phase current I - , so that the output voltage V out includes only a DC component. As a result, as indicated by A in Fig. 2, the gain of the gain-variable amplifier of Fig. 1 is minimum. In the gain-varible amplifier of Fig. 1, however, since the gain characteristics have an inflection point as indicated by A in Fig. 2, it is difficult to control the gain by the gain control voltage V c . Also, the phase of the output voltage V out is inverted at the inflection point A. Since only half of the exploitable range of the gain control voltage V c is utilized, the range of the gain control voltage V c is substantially reduced. The DC voltage of the output voltage V out is explained next. Here, all the transistors Q 1 to Q 6 have the same characteristics. First, assume that V in = 0V and V c = Maximum value. For example, V c = V cc - V cO . Here, collector currents of the transistors Q 2 , Q 4 and Q 6 are denoted by I c2 , I c4 and I c4 , respectively, and the base currents of the transistorss Q 2 , Q 4 and Q 6 are denoted by I B2 , I B4 and I B6 , respectiverly. In this case, the transistors Q 4 and Q 6 are turned ON and OFF, respectively, so that I c6 ≒ 0 I O ≒ I c4 Therefore, V out = V cc - I O · R 2 = V cc - (I c4 + I c6 ) · R 2 ≒ V cc - I c4 · R 2 Also, in the transistor Q 2 , I 1 /2 = I c2 + I B2 Further, in the transistor Q 4 , I c2 = I c4 + I B4 From the formulae (2), (3) and (4), V out = V cc - (I 1 /2 - I B2 - I B4 ) · R 2 Next, assume that V in = 0V and V c = Minimum value such as 0V (see Fig. 2). Here, collector currents of the transistors Q 2 , Q 4 and Q 6 are denoted by I c2 ', I c4 'and I c4 ', respectively, and the base currents of the transistors Q 2 , Q 4 and Q 6 are denoted by I B2 ', I B4 ' and I B6 ', respectiverly. In this case, V out ' = V cc - (I c4 ' + I c6 ') · R 2 = V cc - {(I 1 /2 - I B2 ')/2 - I B4 ' + (I 1 /2 - I B1 ')/2 - I B6 '} · R 2 = V cc - (I 1 /2 - I B2 '- 2I B4 ') · R 2 Thus, since I B2 = I B2 ', the difference ΔV between V out and V out ' of the formulae (5) and (6) is calculated by ΔV = (2I B4 ' - I B4 ) · R 2 Note that, since I B4 = I B4 '/2 can be satisfied, ΔV = 0 Thus, in the gain-variable amplifier of Fig. 1, the deviation of the DC component of the output voltage V out depending upon the gain control voltage V c is small. In Fig. 3, which illustrates a second prior art gain-variable amplifier (see JP-A-3-32209), the resistor R 1 of Fig. 1 is not present. Also, the collectors of the transistors Q 1 , Q 3 and Q 5 of Fig. 1 are connected directly to the power supply terminal V cc . The common emitter of the transistors Q 5 and Q 6 of Fig. 1 are connected via a constant current source CS 2 whose current is I 2 , to the ground terminal GND. Note that the current ratio of I 1 to I 2 is 2. The load resistor R 2 also provides the output voltage V out at the output terminal OUT. In this case, the current I o flowing through the resistor R 2 is formed by a positive phase current I + flowing through the transistor Q 4 of the differential amplifier 2 and the transistor Q 2 of the differential amplifier 1 and a DC current I DC flowing through the transistor Q 6 of the differential amplifier 3 and the transistor Q 1 of the differential amplifier 1. In Fig. 3, when the gain control votlage V c is positive, the positive phase current I + is greater than the DC current I DC . In this case, the higher the gain control voltage V c , the larger the positive phase current I + . As a result, as shown in Fig. 4, the gain is increased as the gain control voltage V c is increased. Also, if V c = 0V, the voltage at the bases of the transistors Q 3 and Q 6 is equal to the voltage at the bases of the transistors Q 4 and Q 5 . Therefore, since the current ratio of I 1 to I 2 is 2, the positive phase current I + is twice the DC current I DC . As a result, as indicated by B in Fig. 4, the gain of the gain-variable amplifier of Fig. 3 is about half of the maximum gain. On the other hand, when the gain control voltage V c is negative, the DC current I DC is greater than the positive phase current I - . That is, the output voltage V out includes only a DC component. As a result, as shown in Fig. 4, the gain of the gain-variable amplifier of Fig. 3 is minimum. In the gain-varible amplifier of Fig. 3, since the gain characteristics have no inflection point as shown in Fig. 4, it is easy to control the gain by the gain control voltage V c from a negative value to a positive value. Also, the phase of the output voltage V o ut is never inverted. Since a full range of the exploitable range of the gain control voltage V c is utilized, the range of the gain control voltage V c is substantially increased. The DC voltage of the output voltage V out is explained next. Here, all the transistors Q 1 to Q 6 have the same characteristics. First, assume that V in = 0V and V c = Maximum value. For example, V c = v cc - v cO . Here, collector currents of the transistors Q 2 , Q 4 and Q 6 are denoted by I c2 , I c4 and I c4 , respectively, and the base currents of the transistors Q 2 , Q 4 and Q 6 are denoted by I B2 , I B4 and I B6 , respectively. In this case, V out = V cc - (I c4 + I c6 ) · R 2 = V cc - (I 1 /2 - I B4 ) · R 2 Next, assume that V in = 0V and V c = Minimum value such as - (V cc - V cO ) (see Fig. 4). Here, collector currents of the transistors Q 2 , Q 4 and Q 6 are denoted by I c2 ', I c4 ' and I c4 ', respectively, and the base currents of the transistorss Q 2 , Q 4 and Q 6 are denoted by I B2 ', I B4 ' and I B6 ', respectively. In this case, V out ' = V cc - (I c4 ' + I c6 ') - R 2 = V cc - (I 1 /2 - I B6 ') · R 2 Thus, since I B2 = I B2 ', the difference ΔV between V out and V out ' of the formulae (8) and (9) is calculated by ΔV = (I B6 '- I B2 ' - I B4 ) · R 2 Note that, since I B4 ' = I B6 ' can be satisfied, ΔV = - I B2 · R 2 Thus, in the gain-variable amplifier of Fig. 3, the deviation of the DC component of the output voltage V out depending upon the gain control voltage V c is large. This large deviation can become enormous in the manufacture of integrated circuits due to deviations in the current amplification factor. Particularly, in radio transmitter/receiver sets, the large deviation of the output DC voltage can be amplified by the downstream amplifiers which degrades various operating characteristics of the sets. Further, in Fig. 3, the signal is subjected to distortion and degradation due to the difference in collector-emitter voltage V CE (V CE1 > V CE2 ) between the transistors Q 1 and Q 2 . For example, in radio transmitter/receiver sets, the distortion appears as harmonic distortion of a transmitting/receiving frequency which degrades the operating characteristics. In Fig. 5, which illustrates a first embodiment of the present invention, an NPN type transistor Q 7 is interposed between the common emitter of the transistors Q 5 and Q 6 and the constant current source CS 2 of Fig. 3. Since the base of the transistor Q 7 is connected to the base of the transistor Q 1 , the transistor Q 7 corresponds to the transistor Q 1 . Also, a load resistor R 1 is interposed between the power supply terminal V cc and the collector of the transistor Q 3 of Fig. 3. The load resistor R 1 provides a negative phase output voltage V out1 at an output terminal OUT1, while the load resistor R 2 provides a positive phase output voltage V out2 at an output terminal OUT2. Further, a load resistor R 3 and an NPN type transistor Q 8 are connected in series between the power supply terminal V cc and the collector of the transistor Q 1 . Since the base of the transistor Q 8 is connected to the bases of the transistors Q 3 and Q 6 , the load resistor R 3 and the transistor Q 8 correspond to the load resistor R 1 and the transistor Q 3 (or Q 6 ), respectively. The gain characteristics of the gain-variable amplifier of Fig. 5 are the same as those of the gain-variable amplifier of Fig. 3 as shown in Fig. 4. Here, collector currents of the transistors Q 2 , Q 4 , Q 6 and Q 7 are denoted by I c2 , I c4 , I c6 and I c7 , respectively, and the base currents of the transistors Q 2 , Q 4 , Q 6 and Q 7 are denoted by I B2 , I B4 , I B6 and I B7 , respectively. Also, in this case, V out2 = V cc - (I c4 + I c6 ) · R 2 = V cc - (I 1 /2 - I s2 - I s4 ) · R 2 Next, assume that V in = 0V and V c = Minimum value such as - (V cc - V O ) (see Fig. 4). Here, collector currents of the transistors Q 2 , Q 4 , Q 6 and Q 7 are denoted by I c2 ', I c4 ', I c6 ' and I c7 ', respectively, and the base currents of the transistors Q 2 , Q 4 , Q 6 and Q 7 are denoted by I B2 ', I B4 ', I B6 ' and I B7 ', respectively. In this case, V out2' = V cc - (I c4 ' + I c6 ') · R 2 Since I c4 ' = I 1 /2 - I B4 ' and I c6 ' = I 1 /2 - I B7 ' - I B6 ' (I B4 ' = I B6 '), V out2' = V cc - (I 1 /2 -I B6 ' - I B7 ') - R 2 Therefore, the difference ΔV between V out2 and V out2 ' of the formulae (11) and (13) is calculated by ΔV = (I B6 ' + I B7 ' - I B2 - I B4 ) · R 2 In this case, since all the transistors have the same characteristics, I B6 ' = I B4 I B7 ' = I B2 Thus, from the formulae (14), (15) and (16), ΔV = 0 In the gain-variable amplifier of Fig. 5, the deviation of the DC component of the output voltage V out2 depending upon the gain control voltage V c is zero. Also, in Fig. 5, the difference in the collector-emitter voltage V CE between the transistors Q 1 and Q 2 can be reduced by the resistor R 3 and the transistor Q 8 to minimize the distortion for the smallest gain. In Fig. 6, which illustrates a second embodiment of the present invention, an NPN type transistor Q 7 is interposed between the common emitter of the transistors Q 5 and Q 6 and the constant current source CS 2 of Fig. 3. Since the base of the transistor Q 7 is connected to the base of the transistor Q 1 , the transistor Q 7 corresponds to the transistor Q 1 . Also, a load resistor R 1 is interposed between the power supply terminal V cc and the collector of the transistor Q 3 of Fig. 3. The load resistor R 1 provides a negative phase output voltage V out1 at an output terminal OUT1, while the load resistor R 2 provides a positive phase output voltage V out2 at an output terminal OUT2. Further, a load resistor R 4 and an NPN type transistor Q 9 are connected in series between the power supply terminal V cc and the collector of the transistor Q 1 . Since the base of the transistor Q 9 is connected to the base of the transistor Q 4 and Q 5 , the load resistor R 4 and the transistor Q 9 correspond to the load resistor R 2 and the transistor Q 4 (or Q 5 ), respectively. The gain characteristics of the gain-variable amplifier of Fig. 6 are also the same as those of the gain-variable amplifier of Fig. 3 as shown in Fig. 4. Also, the DC output characteristics of the gain-variable amplifier of Fig. 6 are the same as those of the gain-variable amplifier of Fig. 5. That is, in the gain-variable amplifier of Fig. 6, the deviation of the DC component of the output voltage V out2 depending upon the gain control voltage V c is zero. Also, in Fig. 6, the difference in the collector-emitter voltage V CE between the transistors Q 1 and Q 2 can be reduced by the resistor R 4 and the transistor Q 9 to minimize the distortion for the largest gain. gain. In Fig. 7, which illustrates a third embodiment of the present invention, the first embodiment as illustrated in Fig. 5 is combined with the second embodiment as illustrated in Fig. 6. In this case, the transistors Q 8 and Q 9 form a differential amplifier 4. The gain characteristics of the gain-variable amplifier of Fig. 7 are also the same as those of the gain-variable amplifier of Fig. 3 as shown in Fig. 4. Also, the DC output characteristics of the gain-variable amplifier of Fig. 7 are the same as those of the gain-variable amplifier of Figs. 5 and 6. That is, in the gain-variable amplifier of Fig. 7, the deviation of the DC component of the output voltage V out2 depending upon the gain control voltage V c is zero. Also, in Fig. 7, the difference in the collector-emitter voltage V CE between the transistors Q 1 and Q 2 can be reduced by the resistors R 3 and R 4 and the transistors Q 8 and Q 9 to minimize the distortion regardless of the gain. In the above-described embodiments, the negative phase output voltage V out1 and the positive phase output voltage V out2 are both utilized. However, if only the negative phase voltage V out2 is utilized, the gain-variable amplifiers of Figs. 5, 6 and 7 can be modified into circuits as illustrated in Figs. 8, 9 and 10. In Fig. 8, the load resistors R 1 and R 3 of Fig. 5 are deleted; in Fig. 9, the load resistor R 1 of Fig. 6 is deleted; and in Fig. 10, the load resistors R 1 and R 3 are deleted. On the other hand, if only the positive phase voltage V out2 is utilized, the gain-variable amplifiers of Figs. 5, 6 and 7 can be modified into circuits as illustrated in Figs. 11, 12 and 13. In Fig. 11, the load resistor R 2 of Fig. 5 is deleted; in Fig. 12, the load resistors R 2 and R 4 of Fig. 6 are deleted; and in Fig. 13, the load resistors R 2 and R 4 are deleted. As explained hereinabove, according to the present invention, the deviation of the DC output characteristics can be reduced, and also, the distortion by the difference in the collector-emitter voltage between the input transistors can be reduced.

Claims: A gain-variable amplifier comprising: first and second power supply terminals (GND, V cc ); first and second constant current sources (IS 1 , IS 2 ) connected to said first power supply terminal; a first differential amplifier (1) formed by first and second transistors (Q 1 , Q 2 ) having a common emitter connected to said first constant current source, said first differential amplifier amplifying an input voltage (V in ); a second differential amplifier (2) formed by third and fourth transistors (Q 3 , Q 4 ) having a common emitter connected to a collector of said second transistor respectively; a third differential amplifier (3) formed by fifth and sixth transistors (Q 5 , Q 6 ) having a common emitter, collectors of said fifth and sixth transistors being connected to collectors of said third and fourth transistors, respectively; and a first load resistor (R 1 or R 2 ) connected between a collector of one of said third and fourth transistors and said second power supply terminal, a collector of said first transistor being coupled to said second power supply terminal, a collector of said fourth transistor being connected coupled to said second power supply terminal, bases of said third and sixth transistors being connected for receiving a first control voltage (V co ), bases of said fourth and fifth transistors being connected for receiving a second control voltage (V c + V co ), characterized in that a seventh transistor (Q 7 ) is connected between the common emitter of said fifth and sixth transistors and said second constant current source, and a base of said seventh transistor is connected to a base of said first transistor. The gain-variable amplifier as set forth in claim 1, further comprising a second load resistor (R 2 or R 1 ) connected between a collector of the other of said third and fourth transistors and said second power supply terminal. The gain-variable amplifier as set forth in claim 1, further comprising: a third load resistor (R 3 ) connected to said second power supply terminal; an eighth transistor (Q 8 ) connected between said third load resistor and the collector of said first transistor, a base of said eighth transistor receiving said first control voltage. The gain-variable amplifier as set forth in claim 1, further comprising a ninth transistor (Q 9 ) connected between the collector of said first transistor and said second power supply terminal. The gain-variable amplifier as set forth in claim 1, further comprising: a fourth load resistor (R 4 ) connected to said second power supply terminal; and a ninth transistor (Q 9 ) connected between the collector of said first transistor and said fourth load resistor.

Inventors: ANDO YOSHIAKI, ANDO, YOSHIAKI
Applicants: NEC ELECTRONICS CORP, NEC ELECTRONICS CORPORATION
Application year: 1997
Main classification: H03G1
IPC codes: H03G1, H03G3