DICTATION AND TRANSCRIPTION APPARATUS

Abstract: A dictation apparatus is disclosed (1) for storing a speech signal in memory means (15, 20), the device comprising data compression means (30) for data compressing the speech signal into a data compressed speech signal and storing means for storing the data compressed speech signal in the memory means. The data compression means (30) are adapted to carry out a data compression step on the speech signal in one of at least two different data compression modes, the at least two different data compression modes resulting in different data compression ratios when applied to the same speech signal, the said at least two different data compression modes being selectable by a user. The data compression means (30) are further adapted to create data files (Bi) comprising portions of the data compressed speech signal, the data files comprising a header portion (HDR), the data compression means being also adapted to generate an identifier signal identifying the data compression mode selected and being adapted to store said identifier signal in said header portion. For realizing an insert, control means are present, which is selectively operable by a user for providing an insert signal and an end of insert signal. In response to the occurrence of each insert signal a block of at least two and at most three pointing vectors is generated. The block of pointing vectors comprises a first address signal corresponding to the address generated by address generator means upon the occurrence of the insert signal and a second address signal corresponding to a beginning address of an available portion of said addressable memory for storing a dictation insert.

Description: Dictation and transcription apparatus. The invention relates to a dictation apparatus for storing a speech signal in addressable memory means and to a transcription apparatus for transcribing speech messages. A dictation apparatus as defined in d e opening paragraph is well known in the art. Reference is made in this respect to EP-A 65,148, document (4) in the list of related documents. Data compression may be realized in prior art dictation apparatuses by discarding the silence periods normally present in the speech signal. Further, one may store an indication signal indicating the length of the silence period and its location in the speech signal. Upon transcription, a replica of the speech signal can be regenerated by inserting silence periods of the same length at the indicated positions in the compressed speech signal. Sometimes an insert need to be added to a speech signal stored earlier in the memory means. EP-A 65,148 describes a way how to enable an insert to be stored in the memory means. The invention aims at providing an improved dictation apparatus. The dictation apparatus in accordance with the invention is characterized in that the device comprising - input means for receiving the speech signal, - data compression means for data compressing the speech signal into a data compressed speech signal, the data compression means being adapted to carry out a data compression step on the speech signal in one of at least two different data compression modes, the at least two different data compression modes resulting in different data compression ratios when applied to the same speech signal, the said at least two different data compression modes being selectable by a user, the data compression means being further adapted to create data files comprising a data compressed speech signal, the data files comprising a header portion, the data compression means being also adapted to generate an identifier signal identifying the data compression mode selected and being adapted to store said identifier signal in said header portion, - storing means for storing the data files in the memory means, the storing means comprising address generator means for generating addresses for said addressable memory means, for storing blocks of information comprised in a data file in the memory means, - control means selectively operable by a user for providing an insert signal and an end of insert signal, - pointing vector generator means for generating a block of at least two and at most three pointing vectors in response to the occurrence of each insert signal, said block of pointing vectors comprising a first address signal corresponding to the address generated by the address generator means upon the occurrence of the insert signal and a second address signal corresponding to a beginning address of an available portion of said addressable memory for storing a dictation insert. The invention is based on the following recognition. The memory capacity of memories included in dictation apparatuses is limited. Preferably, an increased number of dictations should be stored in a memory. This has been realized in the prior art by leaving out the silence periods present in a speech signal. A larger compression ratio can be obtained by applying more powerful compression techniques. More specifically, lossy compression techniques result in large data compression ratios. Larger data reduction ratios, however, may lead to a decrease in quality of the retrieved signal upon data expansion. In accordance with the invention, a dictation system has been proposed in which the user has the possibility to choose one data compression mode from two or more data compression modes in which the dictation apparatus can compress the speech signal. The user can make a trade off between the number of speech messages that he wants to dictate and store in one memory unit and the quality of the speech signal upon reproduction. If the user wants to have more dictations stored in the memory, he will select the data compression mode giving a higher data compression ratio. If the user prefers a higher quality of reproduction, he will choose the data compression mode giving a lower data compression ratio. Further, storing an insert in the memory means is realized by storing two, ' n another embodiment, three pointing vectors at the maximum for each insert to be stored the memory means. This has an advantage over the prior art dictation apparatus, which requires the storage of a jump signal at the location in the originally stored speech signal where the insert should be made, thereby overwriting a portion of the original speech signal stored, a jump signal at the end of the stored insert and four pointing vectors linking the two addresses from which a jump should take place to the two addresses where the jumps should end. Contrary to this, in one embodiment of the invention, only two pointing vectors are required, linking the address in the originally stored speech signal where the insert should be made and the address corresponding to a beginning address of an available portion of said addressable memory for storing a dictation insert. At the end of the insert, an end-of- file signal could be stored, which can be used as jump instruction upon reproduction so as to jump back to the position of the insert in the original speech message. In another embodiment, exactly three pointing vectors are stored in a block of pointing vectors, the third address signal corresponding to the address generated by die address generator means upon the occurrence of the end of insert signal. Upon reproduction in the transcription apparatus, the addresses generated by the address generator means are compared to die first address signal so as to activate the first jump from the location of d e insert in the originally stored speech signal, which corresponds to this first address signal, towards the location where the beginning of the insert is stored, which corresponds to the second address signal, upon equality of the generated addresses with the first address signal. The addresses generated by the address generator means are further compared to the third address signal so as to activate a second jump from the location where the end of die insert is stored, which corresponds to the third address signal, towards the location of d e insert in the originally stored speech signal, which corresponds to the address subsequent to the first address, upon equality of the generated addresses with the third address signal. The various subclaims define preferred embodiments of the dictation apparatus and the transcription apparatus in accordance with the invention. These and other aspects of the invention will be apparent from and elucidated further with reference to the embodiments described in the following figure description, in which figure 1 shows an embodiment of the dictation apparatus, which is in hand held form, figure 2 shows an embodiment of the memory card for use in an embodiment of a dictation apparatus, provided with such a removable memory card, figure 3 shows the circuit diagram in the dictation apparatus, figure 4 shows an embodiment of a transcription apparatus, either in table top, or in PC form, figure 5 shows the memory unit in which the files comprising the speech signals are stored, and figure 6 shows d e storage of an insert in the memory unit. Figure 1 shows a front view of a dictation apparatus in accordance with the invention, which is in this example in hand held form. The apparatus 1 provided with an on/off switch 2 located on the side of d e housing of die apparatus. At the bottom of the housing a battery compartment 3 (not shown) is provided mat can be reached at die back of die housing. A sliding switch 4 is provided on the front face of die housing for switching the apparatus in the various dictation modes. The apparatus is provided with a number of buttons: button 5 is the record button, button 6 is the LETTER button, button 7 is d e MODE button, button 8 is the INSERT button and button 9 is the DELETE button. The switch 10 is the recording mode switch. The switch 11 is me sensitivity switch. The apparatus 1 is further provided with a LCD display for displaying various information regarding a dictation, such as the recording time of the dictation, d e recording time left, the recording mode, the number of dictations, etc. A microphone 13 and a loudspeaker 18 are provided in the housing and a volume control knob 14 is provided on d e side of d e housing. Further, a slot 16 is provided in die top face of me device for receiving a memory card 15. The memory card 15 is also shown in figure 2. The memory card 15 is provided with a solid state memory 20 and with electrical terminals 22 connected to die solid state memory 20. The solid state memory 20 can eg. be an EEPROM or a flash erasable memory. The electrical terminals 22 can be such that iey enable an electrical cooperation widi die internationally standardized PCMCIA interface of a PC. Figure 3 shows the electrical construction of d e apparatus 1 and its cooperation with die memory card 15. The apparatus 1 comprises a digital signal processor 30, having a digital input/output 32 coupled to terminals 34 that are electrically coupled to d e terminals 22 of die memory card 15, when positioned in the slot 16. The microphone 13 is coupled to an analog input 36 of die processor 30, if required via an amplifier 38. The processor 30 further comprises an analog output 40 which is coupled to the loudspeaker 18 via an amplifier 42. The various knobs and buttons, denoted in figure 3 by die reference numeral 44 are coupled to control inputs 46 of the processor 30. Further, a control output 48 of the pro¬ cessor 30 is coupled to a display control unit 50 for controlling the display of information on the display 12. The user places die memory card 15 into d e slot 16 of die apparatus 1 until die terminals 22 of the memory card 15 come into contact wid electrical terminals 34 provided in d e slot of die device 1. The memory card is now in electrical and mechanical contact with d e apparatus 1. The processor 30 is capable of receiving d e analog speech signals via d e input 36 and to A/D convert d e speech signal into a digital speech signal. Further, upon selection by me user, d e processor 30 is capable of carrying out one of at least two different data compression steps on the digital speech signal. Suppose, die processor 30 is capable of carrying out two data compression steps on the speech signal. Each compression step carried out on the same speech signal results in different compression ratios. The data compression steps can be in the form of lossless compression steps. This means mat no data is actually lost and d e original speech signal can be fully recovered upon data expansion. One example of a lossless data compression method is linear predictive coding followed by a Huffman encoding carried out on the output signal of die linear predictive coder. Data compression can also be lossy. One such lossy data compression step is subband coding, well known in the art and applied in DCC digital magnetic recording systems. In lossy compression methods, part of d e information diat is unaudible is actually tiirown away. Upon data expan¬ sion, a replica of d e original speech signal is recovered. As die information tiiat is left out upon data compression was unaudible, d e replica of the speech signal will be heard by d e user as being the same as the original speech signal. The processor 30 may be capable of carrying out a lossless data compression step on the speech signal and a lossy data compression step, as the two different data compression steps at can be realized by the processor 30. As an alternative, d e processor 30 can carry out two different lossless data compression steps resulting in different data compression ratios. As again another alternative, the processor 30 may be capable of carrying out two different lossless data compression steps on d e speech signal, resulting in two different data compression ratios. As an example of the last possibility: die processor 30 could be provided with a simple subband encoder as applied in DCC. The subband encoder can be simple as less subbands are required for encoding the speech signal. Less subbands are required, eg. 5 instead of die 32 in die DCC subband encoder, as the bandwidth of die speech signal is much smaller man a wideband audio signal. Different compression ratios can be obtained with the simplified subband encoder by changing the bitpool for the bitallocation step in the simplified subband encoder. Reference is made in this respect to d e documents (1), (2), (3a) and (3b) in the list of documents that can be found at the end of this descrip- tion. When d e user wants to record a speech message into d e device, he depresses die LETTER button 6, which indicates that die user wants to store a speech message. Further, d e user can actuate d e MODE button 7 in order to select various modes, such as whether die speech message should have a (high) priority, or whetiier d e speech message should be protected from overwriting. Subsequentiy d e user selects a recording mode by actuating die button 10. Selecting the recording mode means mat d e user selects a data compression mode. If die user wants a relatively good quality recording, he/she chooses d e data compression mode resulting in die lowest data compression ratio. As a result, a larger amount of information will be stored in the memory 20 for d e said dictation, so d at less dictations can be stored in said memory. If the user wants as many dictations as possible being stored in the memory 20, he she will choose die data compression mode resulting in the higher data compression ratio. A lower quality storage of die dictations may be d e result. The compressed information is included in blocks of information (or 'files') F, , F 2 , .... This is shown in figure 5. Each file of information F has a header portion, denoted HDR, and an information portion, denoted IP. An identifier signal is stored in d e header portion. The identifier signal in a header portion HDR of a signal block identifies d e com¬ pression mode applied on me speech signal in order to generate d e data compressed information stored in the information portion IP of mat same signal block. The sequence of signal blocks is supplied to the digital output 32 of die processor 30 and subsequentiy stored in the memory 20 on the memory card 15. The data portion of a file could be terminated by using an end-of-file codeword EOF. It should be noted here, diat in the present example, d e processor 30 generate signal blocks as long as required to store the information of exactly one speech message in. Storing of e data compressed speech signal into d e memory 20 is realized by supplying the data compressed speech signal to an input 28 of the memory. Further an address generator 26 is present in the processor 30 to generate addresses for the memory 20. Those addresses are supplied to die memory 20 via an input 24, see the figure 5. Bytes of information of d e data compressed speech signal are stored at subsequent storage locations in the memory 20 by supplying subsequent addresses to d e memory 20 via d e input 24. As said before, die file can be closed by storing an end-of-file word in the memory 20. Now, it will be described how an insert can be stored in the memory. Reference is made to figure 6, for further explanation. Suppose the user of the dictation apparatus has stored a speech message in his/her dictation apparatus as a speech file F j . Upon checking die dictation when rehearing die message, he/she considers an insert to be necessary at a certain location in d e speech message. He/she presses die INSERT button 8 at the location in the stored speech message where die insert should be done. In figure 6, it can be seen diat die insert should be added after d e address n in die originally stored speech message. Upon depressing me INSERT button 8, a block 29 of pointing vectors is generated. As a first pointing vector in me block 29, die address n, where die insert should be added, is stored in die block 29. Next, die signal processor looks for an empty portion in die memory 20 where die insert can be stored. In the example of figure 6, this empty portion is directly behind d e file F j and starts at d e address p. As a second pointing vector in d e block 29, the address p, where die beginning of d e insert will be stored, is added to die block 29. Next, die signal processor 30 stores the insert in d e memory 20. Upon d e termination of d e storage of die insert in die memory 20, die insert is stored in the memory locations starting with die address p, until the address q. As a ti ird pointing vector in die block 29, the address q, where die end of d e insert is be stored, is added to d e block 29. Next, die signal processor 30 stores die block of three pointing vectors in the header portion HDR of die file F j , see figure 6. Especially in a situation where me memory 20 is removable from die dictation apparatus, die block of pointing vectors should be stored in die memory 20 itself. It may however be possible to store d e block of pointing vectors in anotiier location in die memory 20 man in die file header of the file itself. One could imagine a table of contents for all the files in the memory being stored in the memory 20, and that d e block of pointing vectors is stored in this table of contents. In another embodiment, the block of pointing vectors could have been stored in a memory location in the dictation apparatus which is separate from the memory 20 in which the files are stored. Further, in another embodiment, me storage of the insert in die memory 20 could have been terminated by storing an end-of-file word at die end of the stored insert. In this situation, there is no real need for storing the third address in die block of pointing vectors, as will be made clear later. If the user wants to hear die speech message stored in die memory 20, the processor 30 is capable of retrieving e data compressed information from die memory 20 and carry out a data expansion step on the data compressed information stored in the memory. It will be clear that die data expansion step will be the inverse of d e data compres¬ sion step carried out during dictation. The data expansion step to be carried out in the processor 30 will be further explained hereafter, with respect to an embodiment of a transcription apparatus, as shown in figure 4. After having obtained a replica of d e speech signal, tiiis speech signal is D/A converted in d e processor and supplied to die output 40, for reproduction by die loudspeaker 18. For transcription of die speech messages stored in d e memory 20 on the memory card 15, die memory card 15 is withdrawn from d e device 1 and inserted in a table top transcription apparatus 52, see figure 4. The transcription apparatus 52 comprises a digital signal processor 53, having a digital input 54 coupled to terminals 56 diat are electrically coupled to d e terminals 22 of the memory card 15, when positioned in a slot (not shown) provided in d e apparatus 52. A loudspeaker 58 is coupled to an analog output 60 of die processor 53, via an amplifier 62. The processor 53 further comprises a control output 64 which is coupled to a display control unit 66 for controlling the display of information on a display 68. A keyboard 70 is coupled to control inputs 72 of die processor 53. The user places the memory card 15 into the slot (not shown) of d e transcrip- tion apparatus 52 until die terminals 22 of die memory card 15 come into contact with electrical terminals 56 provided in die slot of die transcription apparatus 52. The memory card is now in electrical and mechanical contact with the apparatus 52. Upon actuating a 'RETRIEVE' button on d e keyboard 70, die information stored in d e memory 20 on the memory card 15 is read out and stored in an internal memory of me digital signal processor 53. The processor 53 is capable of carrying out one of at least two different data expansion steps on the digital information retrieved from die memory card. It will be clear mat die expansion mode carried out in the processor 53 is the inverse of die compression mode carried out during the dictation step in d e processor 30. The processor 53 retrieves d e identifier signal from die header portions HDR of d e signal blocks and carries out a data expansion step in response to die identifier signal. As a result, a replica of die digital speech signal is obtained. The processor 53 is further capable of D/A converting the replica of die digital speech signal into an analog speech signal and to supply d e analog speech signal via die output 60 to the loudspeaker 58, so that a typist or other person can hear die speech signal diat need to be transcribed. The typist can type in die speech message reproduced via the loudspeaker using the keyboard 70, so as to obtain a typed version of die speech message. In another embodiment of the transcription apparatus 52, when realized in the form of a personal computer, having a sufficiently large memory capacity, the apparatus may be provided witii a speech recognition algoritiim which enables die apparatus to generate a character file from d e speech signal as a result of such speech recognition step. The character file could be made visible on d e display 68, so diat d e typist can check for errors by reading die text on die display screen 68 and hearing die speech message via d e loudspeaker 58, and correct tiiose errors using die keyboard 70. Previously an example of a lossless data compression method has been described, namely: linear predictive coding followed by a Huffman encoding. It will speak for itself diat d e processor 53 must be capable of carrying out a corresponding Huffman decoding followed by a corresponding linear predictive decoding in order to regenerate d e original speech signal. An example of a lossy data compression step has also been described, namely: subband coding. It will speak for itself diat the processor 53 must be capable of carrying out a corresponding subband decoding in order to regenerate a replica of die original speech signal. Now, d e retrieval of the speech file and die insert shown in figure 6, will be explained. The processor unit 53 has an address generator 26 which generates subsequent address signals for addressing subsequent storage locations in d e memory 20. For retrieving die file F j , die address generator 26 generates addresses starting witii die address a and subsequent addresses until the address n. Upon retrieving d e header portion HDR, d e processor unit 53 is capable of retrieving the block of pointing vectors 29 from d e header. The processor unit 53 further comprises a comparator 74, schematically shown in figure 4, for comparing the addresses generated by the address generator 26 witii addresses stored in d e block of pointing vectors. First a comparison is made with d e first address n stored in die block of pointing vectors. Upon detection of equality, the comparator generates a control signal which is supplied to die address generator 26, together with d e second address p in die block of pointing vectors. Upon receiving die control signal, the address generator 26 is set to the address p, and subsequently generates subsequent addresses starting from die address p. The insert can now be retrieved from die memory 20. The comparator 74 now compares die addresses generated by die generator 26 with die third address q stored in die block of pointing vectors. Upon detection of equality, die comparator generates anotiier control signal which is supplied to die address generator 26. Upon receiving die control signal, die address generator 26 is set to the address n+ 1 , and subsequentiy generates subsequent addresses starting from the address n + 1. The remaining portion of die speech message can now be retrieved from die memory 20. In another embodiment, die end of the insert is detectable because of an end-of- file word which is stored as die last word at die location of the address q. Now, a block of pointing vectors can comprise two addresses only. Upon detection of die end-of-file word at die location q in die memory, the address generator 26 is set to die address n+ 1, and subsequently generates subsequent addresses starting from die address n+ 1. The remaining portion of die speech message can now be retrieved from die memory 20. Whilst die present invention has been described with respect to preferred embodiments tiiereof, it is to be understood diat these are not limitative examples. Thus, various modifications may become apparent to those skilled in die art, witiiout departing from die scope of die invention, as defined by die claims. Further, die invention lies in each and every novel feature or combination of features as herein disclosed. Related documents (1) EP-A 402,973 (PHN 13.241). (2) EP-A 400.755 (PHQ 89.018A). (3a) EP-A 457,390 (PHN 13.328). (3b) EP-A 457,391 (PHN 13.329). (4) EP-A 65,148

Claims: CLAIMS: 1. A dictation apparatus for storing a speech signal in addressable memory means, die device comprising - input means for receiving die speech signal, - data compression means for data compressing die speech signal into a data compressed speech signal, die data compression means being adapted to carry out a data compression step on die speech signal in one of at least two different data compression modes, die at least two different data compression modes resulting in different data compression ratios when applied to die same speech signal, die said at least two different data compression modes being selectable by a user, die data compression means being further adapted to create data files comprising a data compressed speech signal, the data files comprising a header portion, the data compression means being also adapted to generate an identifier signal identifying die data compression mode selected and being adapted to store said identifier signal in said header portion, - storing means for storing the data files in die memory means, die storing means comprising address generator means for generating addresses for said addressable memory means, for storing blocks of information comprised in a data file in die memory means, - control means selectively operable by a user for providing an insert signal and an end of insert signal, - pointing vector generator means for generating a block of at least two and at most three pointing vectors in response to die occurrence of each insert signal, said block of pointing vectors comprising a first address signal corresponding to the address generated by die address generator means upon the occurrence of the insert signal and a second address signal corresponding to a beginning address of an available portion of said addressable memory for storing a dictation insert. 2. Dictation apparatus as claimed in claim 1, wherein said pointing vector generator means for generating a block of pointing vectors is adapted to generate a block of exactly three pointing vectors in response to the occurrence of said insert signal, and diat said block of pointing vectors further comprises a third address signal corresponding to die address generated by the address generator means upon the occurrence of the end of insert signal. 3. Dictation apparatus as claimed in claim 1 or 2, wherein the storing means are adapted to store die block of pointing vectors in die header portion of a data file. 4. Dictation apparatus as claimed in claim 1, 2 or 3, wherein die apparatus is devoid of means for generating a jump signal and is devoid of means for storing said jump signal at an address corresponding to said first address signal in said memory means. 5. Dictation apparatus as claimed in claim 1, characterized in diat, die memory means comprise a removable solid state memory unit for storing die data files, die solid state memory unit being provided witii coupling means for mechanically and electrically coupling die memory unit to die hand held dictation device. 6. Dictation apparatus as claimed in claim 5, characterized in diat die coupling means are further adapted to mechanically and electrically couple the memory unit to a PC. 7. Dictation apparatus as claimed in claim 6, characterized in diat die coupling means are adapted to mechanically and electrically couple die memory unit to an inter¬ nationally standardized interface of die PC. 8. Dictation apparatus as claimed in claim 7, characterized in diat said interface is a PCMCIA interface. 9. Dictation apparatus as claimed in anyone of die claims 5 to 8, characterized in diat the solid state memory unit comprise an EEPROM. 10. Dictation apparatus as claimed in anyone of die claims 5 to 8, characterized in mat die solid state memory unit comprise a Flash erasable memory unit. 11. Dictation apparatus as claimed in anyone of the claims 5 to 8, characterized in diat die solid state memory unit comprise a back-up battery. 12. Dictation apparatus as claimed in anyone of die preceding claims, characterized in diat die data compression means are adapted to carry out a data compression step on die speech signal in one of at least two different data compression modes, at least one of the said at least two different data compression modes being a lossy data compression mode. 13. Transcription apparatus for transcribing speech messages, characterized in diat it comprises data expansion means adapted to carry out a data expansion step on a data compressed speech signal stored in addressable memory means, die said data compressed speech signal being data compressed in one of at least two different data compression modes, the at least two different data compression modes resulting in different data compression ratios when applied to die same speech signal, the data compressed speech signal being stored in the memory means in data files comprising the data compressed speech signal, the data files comprising a header portion in which an identifier signal is stored and a block of at least two and at most tiiree pointing vectors may be stored, die identifier signal identifying die data compression mode selected during data compressing die speech signal, the data expansion means being adapted to retrieve die identifier signal from header portions and being adapted to carry out one of at least two different expansion modes on die data compressed information stored in die files in response to die identifier signal so as to obtain a replica of die speech signal, - control means selectively operable by a user for providing a playback signal, - retrieval means for retrieving die data files from die memory means, die retrieval means comprising address generator means for generating address signals for said addressable memory means, for retrieving blocks of information comprised in a data file stored in die memory means, and for retrieving a first and a second address signal from a block of pointing vectors, die address generator means being adapted to generate a sequence of address signals in response to die occurrence of a playback signal, - comparator means for comparing the sequence of address signals generated by die address generator means witii die first address signal and for generating a jump control signal upon detection of equality between an address signal supplied by die address signal generator means and die first address signal, die address signal generator means being adapted to generate a sequence of address signals in response to die occurrence of said jump control signal, starting with said second address. 14. Transcription apparatus as claimed in claim 13, wherein said block of pointing vectors comprises exactiy three pointing vectors, and diat said block of pointing vectors further comprises a third address signal, that die address generator means is adapted to issue a second jump control signal upon detection of equality between an address signal supplied by die address signal generator means and the tiiird address signal, die address signal generator means being adapted to generate a sequence of address signals in response to die occurrence of said second jump control signal, starting witii die address subsequent to said first address. 15. Transcription apparatus as claimed in claim 14, characterized in diat die memory means is in the form of a removable solid state memory unit and diat die transcrip¬ tion device is provided with coupling means for mechanically and electrically cooperating witii coupling means of the solid state memory unit. 16. Transcription apparatus as claimed in claim 15, characterized in that die coupling means are in accordance with an internationally standardized interface. 17. Transcription apparatus as claimed in claim 15, characterized in diat said interface is a PCMCIA interface.

Inventors: BOELDL HERBERT, BOELDL, HERBERT
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1997
Main classification: G06F3
IPC codes: G06F3, G10L19, G11C7