Voltage monitoring circuit in an integrated circuit device

Abstract: A voltage watching circuit including a charging section for being charged by an external supply voltage to produce a charged voltage, a watched voltage detecting section for inverting its output if the charged voltage provided from the charging section reaches a predetermined level, a latch section for latching an output of the watched voltage detecting section, and a reset section for resetting the latch section until the charged voltage of the charging section reaches the predetermined level. According to the circuit, the voltage watching with a proper voltage level is possible regardless of the variation of the temperature and process parameters, and a low power-consumption is achieved.

Description: The present invention relates generally to a voltage monitoring circuit, and in particular, to a voltage monitoring circuit in a. semiconductor device. Generally, in an integrated semiconductor device circuit, a supply voltage to the individual parts of the circuit reaches a proper voltage level only after a transient period. During such a transient period, a low supply voltage at a value less than the proper voltage level is typically blocked from being supplied to the internal circuit to prevent any malfunction of the internal circuit. A conventional voltage monitoring circuit, as shown in FIG. 1, generally includes a charging section 10 which is charged by an external supply voltage to produce a charged voltage, a voltage detecting section 20 for inverting its output if the charged voltage of the charging section 10 reaches a predetermined level, and an inverter 30 for inverting an output signal of the watched voltage detecting section 20 . According to the conventional circuit of FIG. 1, when the external supply voltage is switched on, a P-type metal oxide semiconductor (PMOS) transistor 12 in the charging section 10 is turned on, and thus a capacitor 14 , connected to a first node N1 , begins to be charged. As the capacitor 14 is charged, a voltage is dropped across the first node N1 . When this voltage reaches a trip point, a PMOS transistor 22 and an N-type metal oxide semiconductor (NMOS) transistor 24 in the voltage detecting section 20 are tripped, and the voltage level of a second node N2 shifts from an initial high to a low level, then causes the output ϕVCCH to shift from an initial low to a high level in response to a low input from N2 . The timing of the output inversion is determined by the resistance value of the PMOS transistor 12 acting as a diode, the capacitance value of the capacitor 14 , and the adjustment of the trip points of the voltage detection section 20 and the inverter 30. However, the conventional voltage monitoring circuit as described above may malfunction due to the output ϕVCCH of the inverter 30 being shifted at a lower voltage level than desired wherein the lower voltage level is caused by a transient delay between supply voltage and the voltage actually realized at the first node N1 . Also, since the shift point of the output of the inverter 30 , which is the detected voltage level, is restricted to a threshold voltage level Vt of the NMOS transistor 14 of the inverter 20 , it is impossible to cause the shift of the output to happen at a higher voltage level than the threshold voltage. FIG. 2 is a schematic circuit diagram of another conventional voltage monitoring circuit which is constructed to heighten the detected level of the monitored voltage in comparison to the voltage monitoring circuit of FIG. 1. Referring to FIG. 2, the circuit further comprises a watched voltage adjusting section 50 coupled between the source of an NMOS transistor 44 of the watched voltage detecting section 44 and ground. The watched voltage adjusting section 50 comprises an NMOS transistor 52 whose gate and drain are connected to each other so as to act as a diode. The watched voltage adjusting section 50 operates to raise the trip point of the inverter as high as the threshold voltage Vt of the NMOS transistor. FIG. 3 is a schematic circuit diagram of still another conventional voltage monitoring circuit which comprises a voltage detecting section 60 including n stages of inverters, and a voltage adjusting section 70 which is coupled between the respective inverter stages and ground. In the voltage adjusting section 70, as the number of the inverter stages increases, the number of diodes connected to the respective inverters decreases. One disadvantage of the voltage monitoring circuit of Fig.3 is that as the power is repeatedly switched on and off, the second and third nodes N2 and N3 in the inverter stages 63, 64, 66 and 68 tend to discharge to the threshold voltage level Vt of "1"V rather than to a "0"V. This effect causes the other inverters to weakly switch on, creating a DC current path between the supply voltage to ground. Thus, the circuit suffers unnecessary power consumption. Further, in order to raise the shifting point of the second node N2 as much as n times the threshold voltage Vt, n-1 stages of inverters are additionally required, which results circuit complexity and the increase of the layout area. Also, the shifting point of the inverter's output is easily affected by a temperature due to the sensitive nature of the diodes. US 5, 440, 263 discloses a voltage threshold detection circuit for use in inhibiting the operation of an integrated circuit until its supply voltage is above a threshold. The voltage threshold detection circuit disclosed in this document has a detection transistor, for detecting the presence of a predetermined voltage at the gate of the transistor. The voltage applied to the gate of the detection transistor is derived from the voltage input to the voltage threshold detection circuit. The drain of the detection transistor is connected to an inverter and the output of the inverter is latched by means of a further latching transistor. In operation, the drain of the detection transistor is precharged to Vcc resulting in the output of the inverter being latched at a low level until the voltage input to the voltage threshold detection circuit exceeds the threshold, whereupon the detection transistor is switched on and the output of the inverter becomes high and is latched there by the latching transistor. The preferred voltage monitoring circuit according to the present invention provides means for adjusting the actual voltage level to a proper level and maintains stable circuit characteristics against the varying environment, such as temperature change and process parameters. Further, the preferred voltage monitoring circuit of the present invention requires significantly lower power consumption parameters. According to the present invention there is provided a voltage watching circuit comprising: charging means for storing voltage from an external supply voltage to produce a charged voltage; voltage detecting means for inverting its output if said charged voltage from said charging means reaches a predetermined level; latch means for latching an output of said voltage detecting means; characterised in that the voltage watching circuit also comprises reset means for resetting said latch means until said charged voltage of said charging means reaches said predetermined level. The charging means may include a first PMOS transistor forwardly coupled between the external supply voltage and a first node, and a capacitor coupled between the first node and ground. The charging means may also include a second PMOS transistor reversely coupled between the first node and the external supply voltage, and an NMOS transistor reversely coupled between ground and the first node. The watched voltage detecting means may include an NMOS transistor, coupled between a second node and a third node, for being switched in response to the charged voltage of the charging means. The watched voltage detecting means further includes a plurality of NMOS transistors connected in series between the third node and ground. The latch means includes a first PMOS transistor, coupled between the external supply voltage and the output of the watched voltage detecting means, for switching in response to the output of the latch means. The latch means further includes a second PMOS transistor, coupled between the external supply voltage and the output of the latch means, for switching in response to the output of the watched voltage detecting means. The reset means includes an inverter for inverting its output if the charged voltage level of the charging means reaches a trip point. The reset means further includes an NMOS transistor, coupled between an output of the latch means and ground, for switching in response to the output of the inverter. The voltage monitoring circuit according to the present invention may further comprise output buffer means including a first inverter for inverting an output of the latch means, a second inverter for inverting an output of the first inverter, a PMOS transistor reversely coupled between an output node and the external supply voltage, and an NMOS transistor reversely coupled between ground and the output node. BRIEF DESCRIPTION OF THE DRAWINGS The above objects, other features, and advantages of the present invention will become more apparent by describing the preferred embodiments thereof with reference to the accompanying drawings, in which: FIG. 1 is a schematic circuit diagram of a conventional voltage monitoring circuit; FIG. 2 is a schematic circuit diagram of another conventional voltage monitoring circuit; FIG. 3 is a schematic circuit diagram of still another conventional voltage monitoring circuit; FIG. 4 is a schematic circuit diagram illustrating a preferred structure of the voltage monitoring circuit according to the present invention; FIG. 5 is a schematic circuit diagram of the voltage monitoring circuit according to a preferred embodiment of the present invention; FIGs. 6A to 6C are waveform diagrams depicting the input-output characteristics of the voltage monitoring circuit according to the present invention; FIGs. 7A and 7B are worst case waveform diagrams of the conventional and present voltage monitoring circuits, respectively, depicting the variation characteristics of the monitored voltage with respect to changes in temperature and process parameters; and FIGs. 8A and 8B are optimum case waveform diagrams of the conventional and present voltage monitoring circuits, respectively, depicting the variation characteristics of the monitored voltage with respect to changes in temperature and process parameters. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 4 illustrates a preferred voltage monitoring circuit according to the present invention. Briefly, the voltage monitoring circuit of FIG. 4 includes a charging section 110 , a voltage detecting section 120 , a latch section 130 , and a reset section 140 . The charging section 110 includes a PMOS transistor PM1 forwardly connected between an external supply voltage VCC and a first node N1 , and a capacitor C connected between the first node N1 and the ground VSS . The PMOS transistor PM1 is turned off when the difference between the external supply voltage and a charged voltage of the capacitor is below a threshold voltage. The voltage detecting section 120 includes an NMOS transistor NM1 , connected between a second node N2 and a third node N3 , for switching in response to the charged voltage of the charging section 110 . The voltage detecting section 120 further includes a plurality of NMOS transistors NM2 and NM3 connected in series between the third node N3 and the ground VSS. In operation, if the charged voltage reaches Vgs(NM1) + 2Vt, the NMOS transistor NM1 is turned on, causing the voltage level of the second node N2 to fall from VCC to 2Vt. Accordingly, the actual voltage is determined to be Vgs(NM1) + 2Vt. As a result, the actual voltage can be adjusted by the number of the NMOS transistors connected in series. The latch section 130 includes a PMOS transistor PM2 , connected between the external supply voltage VCC and the output of the voltage detecting section 120 , for switching in response to output ϕVCCH of the latch section, and a PMOS transistor PM3 , connected between the external supply voltage VCC and the output of the latch section, for switching in response to the output of the voltage detecting section 120 . Initially, when ϕVCCH is low, the PMOS transistor PM2 is turned on, causing the voltage level of the second node N2 to become VCC . At the same time, the PMOS transistor PM3 is kept off since the level of the second node N2 is high at VCC . In this state, if the voltage level of the second node N2 falls to Vgs(NM1) + 2Vt as determined by the voltage detecting section 120 , the PMOS transistor PM3 is switched on since ϕVCCH is high, while the PMOS transistor PM2 is switched off, preventing the current to flow through the second node N2 to be cut off and thus avoiding unnecessary power consumption in the voltage detection section 120 . The reset section 140 includes an inverter G1 for inverting the charged voltage level of the charging section 110 when it reaches a trip point. The reset section 140 further includes an NMOS transistor NM4 , connected between the output of the latch section 130 and the ground VSS , for switching in response to the output of the inverter G1 . If the charged voltage at N1 does not reach the trip point of the inverter G1 (such as 1V) after the supply power is switched on, the voltage level of the fourth node N4 is kept to VCC to maintain the NMOS transistor NM4 to conduct. Accordingly, ϕVCCH becomes low, causing the latch section 130 to reset. If the charged voltage at N1 exceeds the trip point of the inverter G1 , the fourth node N4 is kept low, and the NMOS transistor NM4 is switched off. Accordingly, when the voltage observed at N1 becomes Vgs(NM1) + 2Vt, the output of the watched voltage detecting section 120 is latched in the latch section 130 . FIG. 5 is a schematic circuit diagram of the preferred voltage monitoring circuit according to the present invention. According to this embodiment, the charging section 110 further includes a PMOS transistor PM4 which is coupled between the PMOS transistor PM1 and the first node N1 , and whose gate is connected to the first node N1 . The charging section 110 further includes a PMOS transistor PM5 reversely coupled between the first node N1 and the external supply voltage VCC , and an NMOS transistor NM5 reversely coupled between the ground VSS and the first node N1 . The PMOS transistor PM5 operates to keep the voltage of the first node N1 at VCC if the voltage level of the first node rises beyond a threshold voltage over VCC . The NMOS transistor NM5 operates to keep the voltage of the first node N1 at VSS if the voltage level of the first node N1 falls below a threshold voltage below VSS. Thus, the device can be protected from the input of an abnormal voltage. In this embodiment, the inverter G1 includes a PMOS transistor PM6, coupled between the external supply voltage VCC and the fourth node N4, for switching in response to the charged voltage. The inverter G1 further includes a plurality of NMOS transistors, such as NM6 and NM7 , coupled in series between the fourth node N4 and the ground, for simultaneously switching in response to the charged voltage. The inverter G1 as constructed above enables the trip point to be higher than that of a single NMOS transistor. The voltage watching circuit of FIG. 5 further comprises an output buffer section 150 for buffering the output of the latch section. The output buffer section 150 includes a first inverter G2 for inverting the output of the latch section 130 , a second inverter G3 for inverting the output of the first inverter G2 , a PMOS transistor PM9 reversely coupled between the output ϕVCCH and the external supply voltage VCC , and an NMOS transistor NM11 reversely coupled between the ground VSS and the output ϕVCCH . Here, PM9 and NM11 act as a device protector in the same manner as PM5 and NM5 . The first inverter G2 includes a PMOS transistor PM7 , coupled between the external supply voltage VCC and a fifth node N5 , for switching in response to the output of the latch section, and a plurality of NMOS transistors such as NM8 and NM9 , coupled in series between the fifth node N5 and the ground VSS , for simultaneously switching in response to the output of the latch section. The second inverter G3 includes a PMOS transistor PM8 and an NMOS transistor NM10 . Now, the operation of the voltage monitoring circuit according to the present invention as constructed above will be explained. FIGs. 6A to 6C graphically illustrate the observed voltages in which the rising slope of the supply voltage is about 60µs/V. Specifically, the observed voltage becomes 1.8V if no diode is connected to the third node N3 of the voltage detecting section 120 of the voltage monitoring circuit of the present invention. The observed voltages are between 3V and 4.4V if one of two diodes are connected to the third node N3 , respectively. FIGs. 7A and 7B and FIGs. 8A and 8B graphically illustrate the observed voltage variation with respect to process and the temperature in accordance with the conventional and the present voltage watching circuits, respectively. Specifically, the variation range of the watched voltage according to the present invention is greatly narrow in comparison to that according to the conventional circuit having a wide variation range of the watched voltage both in the most inferior condition (FIGs. 7A and 7B) and in the optimum condition (FIGs. 8A and 8B). From the foregoing, it will be apparent that the voltage monitoring circuit according to the present invention provides the advantages in that it enables a proper adjustment of the watched voltage of nVt with its simple construction without the necessity of employing n stages of inverters. Also, the number of diodes to be employed in the respective inverters can be greatly reduced, and this causes the observed voltage variation due to the variation of the temperature and the process to be restrained, resulting in stable operation characteristics. Further, according to the present invention, a low power consumption can be achieved since the power is consumed only during the switching operation, and thus the DC current path is cut off in all states except for the switching operation.

Claims: A voltage watching circuit comprising: charging means (110) for storing voltage from an external supply voltage (VCC) to produce a charged voltage (N1); voltage detecting means (120) for inverting its output if said charged voltage (N1) from said charging means (110) reaches a predetermined level; latch means (130) for latching an output of said voltage detecting means (120); characterised in that the voltage watching circuit also comprises reset means (140) for resetting said latch means (130) until said charged voltage (N1) of said charging means (110) reaches said predetermined level. A voltage watching circuit as claimed in claim 1, wherein said charging means (110) comprises: a PMOS transistor (PM1) forwardly coupled between said external supply voltage (VCC) and ground (VSS); and a capacitor (C) coupled between a first node and ground. A voltage watching circuit as claimed in claim 1, wherein said charging means (110) further comprises a PMOS transistor (PM5) reversely coupled between said first node and said external supply voltage; and an NMOS transistor (NM5) reversely coupled between ground and said first node. A voltage watching circuit as claimed in claim 1, wherein said watched voltage detecting means (120) comprises: an NMOS transistor (NM1), coupled between a second node and a third node, for being switched in response to said charged voltage (N1) of said charging means (110); and a plurality of NMOS transistors (NM2, NM3) connected in series between said third node and ground. A voltage watching circuit as claimed in claim 1, wherein said latch means (130) comprises: a first PMOS transistor (PM2), coupled between said external supply voltage (VCC) and said output of said watched voltage detecting means (120), for being switched in response to an output (N6) of said latch means (130); and a second PMOS transistor (PM3), coupled between said external supply voltage and said output of said latch means (130), for being switched in response to said output of said watched voltage detecting means (120). A voltage watching circuit as claimed in claim 1, wherein said reset means (140) comprises: an inverter (G1) for inverting its output if said charged voltage level of said charging means (110) reaches a trip point; and an NMOS transistor (NM4), coupled between an output of said latch means (130) and ground (VSS), for being switched in response to said output of said inverter (G1). A voltage watching circuit as claimed in claim 6, wherein said inverter (G1) comprises: a PMOS transistor (PM6), coupled between said external supply voltage and a fourth node, for being switched in response to said charged voltage; and a plurality of NMOS transistors (NM6, NM7), coupled in series between said fourth node and ground, for being simultaneously switched in response to said charged voltage. A voltage watching circuit as claimed in claim 1, further comprising output buffer means (150) for buffering an output of said latch means (130). A voltage watching circuit as claimed in claim 8, wherein said output buffer means comprises: a first inverter (G2) for inverting an output of said latch means (130); a second inverter (G3) for inverting an output of said first inverter (G2); a PMOS transistor (PM9) reversely coupled between an output node and said external supply voltage; and an NMOS transistor reversely coupled between ground and said output node. A voltage watching circuit as claimed in claim 9, wherein said first inverter (G2) comprises: a PMOS transistor (PM7), coupled between said external supply voltage and a fifth node, for being switched in response to said output of said latch means (130); and a plurality of NMOS transistors (NM8, NM9), coupled in series between said fifth node and ground, for being simultaneously switched in response to said output of said latch means (130).

Inventors: KIM JONG-SUN, KIM, JONG-SUN
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1997
Main classification: G01R19
IPC codes: G01R19, G05F1, G06F1, G11C5