Two's complement multiplier

Abstract: A partial product adder for summing up four partial products P0, P1, P2, and P3 which are binary numbers in twos-complement representation having different weights is composed of a carry save adder consisting of an array of 4:2 compressors each having four inputs. Of the four inputs of each 4:2 compressor, the input W presents the shortest propagation delay, while the inputs Y and Z compose critical paths. To implement sign extension of the first partial product P0 having the smallest weight, a logic circuit provides, in a plurality of digit positions higher than the sign digit P0s of the first partial product, values resulting from a logic operation between the value of the sign digit P0s of the first partial product and the value of the sign digit P1s of the second partial product having the second smallest weight. The first partial product P0 after sign extension is allocated to the input W of the carry save adder, while the plurality of upper digits of the input Z related to the second partial product P1 have their values fixed to 0. This reduces a time penalty accompanying the sign extension.

Description: The present invention relates to a multiplier for calculating a product of a multiplier factor and a multiplicand, each of which is a binary number in twos-complement representation. A parallel multiplier calculates a product by summing up a plurality of partial products generated in parallel from a multiplier factor and a multiplicand. The number of the partial products can be reduced based on the Booth's algorithm. As discussed in "SPIM: A Pipelined 64x64-bit Iterative Multiplier" (M. R. Santoro et al., IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, pp.487-493, April 1989), 4:2 compressors capable of constructing a binary tree are suitable for the summation of the partial products. A Wallace free adder composed of an array of numerous 4:2 compressors is used to sum up the partial products, in which each 4:2 compressor consists of two 3-input 2-output full adders. The individual partial products have different weights. If the partial products are binary numbers in twos-complement representation, therefore, it is necessary to implement sign extension of the partial products prior to performing an addition with respect to the partial products. By way of example, consideration will be given to the case where four partial products P0, P1, P2, and P3 generated in accordance with the second-degree Booth's algorithm are summed. It is assumed here that the four partial products P0, P1, P2, and P3, each composed of nine digits, have respective weights of 2 0 , 2 2 , 2 4 , and 2 6 . The most significant digit of each of the partial products is a sign digit. In this case, it is necessary to implement sign extension of each of the three partial products P0, P1, and P2 except the partial product having the largest weight (most significant partial product) P3. Specifically, six additional digits each having the value of the sign digit of the partial product having the smallest weight (first partial product) P0 are provided in digit positions higher than the sign digit of the first partial product P0, thereby achieving sign extension of the first partial product P0. Four additional digits each having the value of the sign digit of the partial product with the second smallest weight (second partial product) P1 are provided in digit positions higher than the sign digit of the second partial product P1, thereby achieving sign extension of the second partial product P1. Two additional digits each having the value of the sign digit of the partial product with the third smallest weight (third partial product) P2 are provided in digit positions higher than the sign digit of the third partial product P2, thereby achieving sign extension of the third partial product P2. An addition is performed with respect to the individual corresponding digits of the four partial products P0, P1, P2, and P3 after sign extension. As indicated by its name, the 4:2 compressor has four inputs and two outputs. One of the four inputs reaches the two outputs of the 4:2 compressor by passing through only one of the two full adders, while the other three inputs reach the two outputs of the 4:2 compressor by sequentially passing through the two full adders. As a result, any of the other three inputs forms a critical path presenting the longest propagation delay in the adder. However, in the case of implementing sign extension of all the partial products except the most significant partial product as described above, the input composing the critical path is dependent on the value of the sign digit of any partial product, which causes a time penalty. UA-4879677 discloses a parallel adder circuit including a partial product adding circuit for adding 1-bit partial products. together in order to a total plurality of partial products, and a sign bit decoder circuit for decoding sign bits of a given bit number to provide a total sum of sign bits and supply this total sum to the partial product adding circuit at given bits. In a multiplier utilizing Booth's algorithm, a decoder circuit is used for decoding sign bits of the partial product to provide the total sum of all the sign bits, and a decoded output is supplied to the partial product adding circuit. Therefore, the number of higher bit inputs can be reduced and the number of full adders in the partial product adding circuit can be decreased. IBM TECHNICAL DISCLOSURE BULLETIN., vol. 9, no. 2, July 1996, NEW YORK US, pages 171-173, XP002038144 L. LIU ET AL.: 'MULTIPLICATION USING 2's COMPLEMENT NUMBERS' discloses that Exclusive-Or's and Or's may be used and combined for replacing carry-save adder stages. It is stated that it may be possible to drop all carry generations because of the data pattern and the Exclusive-Or and Or circuits generate a correct sum, whereby a significant saving of carry-save adder stages for handling the addition of the sign extensions may be realized. SUMMARY OF THE INVENTION It is therefore an object of the present invention to reduce the time penalty accompanying the sign extension during the summation of the partial products. This object is achieved by the features of claim 1. The present invention allocates a specified partial product after sign extension implemented based on a plurality of sign digits to a specified input not composing the critical path in the Wallace tree adder, thereby fixing the input composing the critical path in the Wallace tree adder to a constant value. Specifically, a multiplier according to the present invention comprises a partial product adder for summing up a plurality of partial products which are binary numbers in twos-complement representation having different weights, wherein the partial product adder comprises a Wallace free adder having a plurality of inputs and at least one output for performing an addition with respect to the plurality of partial products and a logic circuit for providing, in a plurality of digit positions higher than the sign digit of the partial product having the smallest weight (first partial product) of the plurality of partial products, values resulting from a plurality of logic operations between the value of the sign digit of the first partial product and the value of the sign digit of another partial product. In the Wallace free adder, the specified input presents propagation delay between the output and itself, which is shorter than propagation delay presented by at least one other input. The first partial product after sign extension implemented by the logic circuit is allocated to the specific input. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a specific embodiment of a multiplier according to the present invention; FIG. 2 is a block diagram showing a part of the internal structure of a partial product adder in FIG. 1; FIG. 3 is a block diagram showing another part of the internal structure of the partial product adder in FIG. 1; FIG. 4 is a block diagram showing the internal structure of a 4:2 compressor in FIGS. 2 and 3; FIG. 5 is a circuit diagram showing the internal structure of a full adder in FIG. 4; FIG. 6 illustrates the operation of a partial product adder having the structure shown in FIGS. 2 and 3; FIG. 7 is a block diagram showing a variation of the partial product adder shown in FIG. 2; and FIG. 8 illustrates the operation of a partial product adder having the structure shown in FIG. 7. DETAILED DESCRIPTION OF THE INVENTION Referring now to the drawings, a specific embodiment of a multiplier as a type of arithmetic processing apparatus according to the present invention will be described. FIG. 1 shows a specific example of the structure of the multiplier according to the present invention, which comprises: a multiplier factor encoder 10; four partial product generators 11, 12, 13, and 14; a partial product adder 15; and a carry look ahead adder 16 to calculate the product M of a multiplicand U and a multiplier factor V, each of which is an 8-digit binary number in twos-complement representation. The multiplier factor encoder 10 generates four encoded values E0, E1, E2, and E3 from the multiplier factor V in accordance with the second-degree Booth's algorithm. The four partial product generators 11, 12, 13, and 14 generate in parallel four partial products P0, P1, P2, and P3, which are binary numbers in twos-complement representation having different weights, from the multiplicand U and the four encoded values E0, E1, E2, and E3. The four partial products P0, P1, P2, and P3, each composed of nine digits, have respective weights of 2 0 , 2 2 , 2 4 , and 2 6 . The most significant digit of each of the partial products is a sign digit. The partial product adder 15 performs an addition with respective to the individual corresponding digits of the four partial products P0, P1, P2, and P3 and supplies the result of addition (composed of two binary numbers) Q to the carry look ahead adder 16. The carry look ahead adder 16 calculates the product M from the result of addition Q supplied from the partial product adder 15. FIGS. 2 and 3 show the internal structure of the partial product adder 15 in FIG. 1. In the drawings are shown: a Wallace free adder 20 consisting of fifteen 4:2 compressors 200 to 214; and a logic circuit 30 composed of an EXCLUSIVE-OR gate 31 and an OR gate 32. Each of the fifteen 4:2 compressors 200 to 214 actually has five inputs X, Y, Z, W, and CI and three outputs C, S, and CO, of which CI is a carry input from the lower digit, CO is a carry output to the upper digit, C is a carry output to the carry look ahead adder 16, and S is a sum output to the carry look ahead adder 16. The four partial products P0, P1, P2, and P3 are allocated to the inputs W, Z, Y, and X of the carry save adder 20, respectively. In FIG. 2, P0s, P1s, P2s, and P3s represent the respective sign digits of the partial product having the smallest weight (first partial product) P0, the partial product having the second smallest weight (second partial product) P1, the partial product having the third smallest weight (third partial product) P2, and the partial product having the largest weight (most significant partial product) P3. As shown in FIG. 2, sign extension of the first partial product P0 is implemented in the following process. A digit having the value of the sign digit P0s of the first partial product is provided in the digit position (with the weight of 2 9 ) one digit higher than the sign digit P0s of the first partial product. In the digit position (with the weight of 2 10 ) of the first partial product P0 corresponding to the sign digit P1s of the second partial product, there is provided the exclusive OR value A between the respective sign digits P0s and P1s of the first and second partial products obtained by the EXCLUSIVE-OR gate 31. In the digit positions of the first partial product P0 extending from the one (with the weight of 2 11 ) corresponding to the digit position one digit higher than the sign digit P1s of the second partial product to the one (with the weight of 2 14 ) corresponding to the sign digit P3s of the most significant partial product, there are provided the OR values B between the values of the respective sign digits P0s and P1s of the first and second partial products obtained by the OR gate 32. Hence, A = P0s ^ P1s B = P0s + P1s are satisfied, where ^ represents the exclusive OR value and + represents the OR value. The sign digit (with the weight of 2 10 ) of the second partial product P1 and the four digits (with the weights of 2 11 to 2 14 ) higher than the sign digit of the second partial product P1 have their values fixed to 0. Each of the two digits (with the weights of 2 13 to 2 14 ) higher than the sign digit P2s of the third partial product P2 has the value of the sign digit P2s of the third partial product. If the first and second partial products P0 and P1 are subjected to sign extension according to the conventional embodiment, the summation of the respective five digits with the weights of 2 10 to 2 14 of the first and second partial products P0 and P1 can be expressed as 00000 + 00000 = 00000 (when P0s = 0 and P1s = 0) 11111 + 00000 = 11111 (when P0s = 1 and P1s = 0) 00000 + 11111 = 11111 (when P0s = 0 and P1s = 1) 11111 + 11111 = 11110 (when P0s = 1 and P1s = 1). Briefly, with the values of the five digits (with the weights of 2 10 to 2 14 ) of the first partial product P0 thus determined by the logic circuit 30, the values of the five digits (with the weights of 2 10 to 2 14 ) of the second partial product P1 can be fixed to 0. FIG. 4 shows the internal structure of a 4:2 compressor 214 consisting of first and second full adders 101 and 102. Each of the first and second full adders 101 and 102 has three inputs IN1, IN2, and IN3 and two outputs CY (carry) and SUM (sum). The inputs X, Y, and Z of the 4:2 compressor 214 are allocated to the inputs IN1, IN2, and IN3 of the first full adder 101, respectively. The input W of the 4:2 compressor 214 is allocated to the input IN2 of the second full adder 102. The output SUM from the first full adder 101 is given to the input IN1 of the second full adder 102, while the carry input CI from the lower digit is given to the input IN3 of the second full adder 102. The carry output CO is supplied from the first full adder 101 to the higher digit, while the outputs C and S are supplied from the second full adder 102 to the carry look ahead adder 16. The internal structure of each of the other fourteen 4:2 compressors 200 to 213 shown in FIGS. 2 and 3 is the same as shown in FIG. 4. FIG. 5 shows the internal structure of the first full adder 101 consisting of two EXCLUSIVE-OR gates 111 and 112, three 2-input NAND gates 113, 114, and 115, and one 3-input NAND gate 116. The internal structure of the second full adder 102 shown in FIG. 4 is the same as shown in FIG. 5. As shown in FIGS. 4 and 5, the input W to the 4:2 compressor 214 passes through only the second full adder 102, i.e., through at most two gates to reach the outputs C and S of the 4:2 compressor 214, while the input X to the 4:2 compressor 214 passes through at most three gates in the first and second full adders 101 and 102 to reach the output C of the 4:2 compressor 214. On the other hand, each of the inputs Y and Z to the 4:2 compressor 214 passes through at most four gates in the first and second full adders 101 and 102 to reach the output C of the 4:2 compressor 214. In other words, the input W presents the shortest propagation delay, while the inputs Y and Z compose critical paths in the Wallace free adder 20, respectively. Therefore, as described above, the first, second, third, and fourth partial products P0, P1, P2, and P3 are allocated to the inputs W, Z, Y, and X, respectively. FIG. 6 conceptually illustrates the sign extension and allocation of the four partial products P0, P1, P2, and P3. Since each of the five most significant digits of the input Z composing the critical path is fixed to the constant value of 0, the time penalty accompanying the sign extension is reduced, which contributes to the execution of high-speed multiplication. Moreover, since each of the exclusive OR value A and OR value B is generated by one gate in the logic circuit 30 with the first partial product P0 allocated to the input W, propagation delay in the logic circuit 30 will not increase propagation delay in the partial product adder 15. The four partial products P0, P1, P2, and P3 may also be allocated to the inputs X, Y, Z, and W of the Wallace free adder 20, respectively. In this case, the five most significant digits of the input Y composing the critical path are fixed to the constant value of 0, so that the time penalty accompanying sign extension is similarly reduced. Moreover, since the first partial product P0 having input delay comparable to that in one gate is allocated to the input X, propagation delay in the logic circuit 30 will not increase propagation delay in the partial product adder 15. FIG. 7 shows a variation of the partial product adder shown in FIG. 2. In the variation, not only the five most significant digits of the input Z to the Wallace free adder 20 but also the three most significant digits of the input Y thereto are also fixed to the constant value of 0. A logic circuit 40 shown in the drawing consists of two EXCLUSIVE-OR gates 41 and 43 and two OR gates 42 and 44. Similarly to FIG. 2, the four partial products P0, P1, P2, and P3 are allocated to the inputs W, Z, Y, and X of the Wallace free adder 20, respectively. As shown in FIG. 7, sign extension of the first partial product P0 is implemented in the following process. A digit having the value of the sign digit P0s of the first partial product is provided in the digit position (with the weight of 2 9 ) one digit higher than the sign digit P0s of the first partial product. In the digit position (with the weight of 2 10 ) of the first partial product P0 corresponding to the sign digit P1s of the second partial product, there is provided the exclusive OR value A between the respective sign digits P0s and P1s of the first and second partial products obtained by the EXCLUSIVE-OR gate 41. In the digit position (with the weight of 2 11 ) of the first partial product P0 corresponding to the digit position one digit higher than the sign digit P1s of the second partial product, there is provided the OR value B between the values of the respective sign digits P0s and P1s of the first and second partial products obtained by the OR gate 42. In the digit position (with the weight of 2 12 ) of the first partial product P0 corresponding to the sign digit P2s of the third partial product, there is provided the exclusive OR value G between the OR value B and the value of the sign digit P2s of the third partial product obtained by the EXCLUSIVE-OR gate 43. In the digit positions of the first partial product P0 extending from the one (with the weight of 2 13 ) corresponding to the digit position one digit higher than the sign digit P2s of the third partial product to the one (with the weight of 2 14 ) corresponding to the sign digit P3s of the most significant partial product, there are provided the OR values H between the OR value B and the value of the sign digit P2s of the third partial product obtained by the OR gate 44. Hence, A = P0s ^ P1s B = P0s + P1s G = B ^ P2s H = B + P2s are satisfied, where ^ represents the exclusive OR value and + represents the OR value. The sign digit (with the weight of 2 10 ) of the second partial product P1 and the four digits (with the weights of 2 11 to 2 14 ) higher than the sign digit of the second partial product P1 have their values fixed to 0. The sign digit (with the weight of 2 12 ) of the third partial product P2 and the two digits (with the weights of 2 13 and 2 14 ) higher than the sign digit of the third partial product P2 also have their values fixed to 0. FIG. 8 conceptually illustrates the sign extension and allocation of the four partial products P0, P1, P2, and P3. Since the respective upper digits of the inputs Y and Z composing the critical paths are fixed to the constant value of 0 independent of the value of the sign digit of any partial product, the time penalty accompanying the sign extension is further reduced, which contributes to the execution of high-speed multiplication. Moreover, since each of the exclusive OR values A and G and OR values B and H is generated by at most two gates in the logic circuit 40 with the first partial product P0 allocated to the input W, propagation delay in the logic circuit 40 will not increase propagation delay in the partial product adder 15. Although each of the foregoing specific embodiments has used the multiplier comprising the Wallace free adder consisting of the plurality of 4:2 compressors, the present invention is generally applicable to a multiplier comprising a Wallace free adder in which a specific one of a plurality of inputs presents propagation delay shorter than propagation delay in at least one other input. In a multiplier composed of 16 x 16 digits, e.g., the present invention is applicable to the summation of partial products in a Wallace free adder consisting of an array of 7:3 compressors. The algorithm used in the multiplier factor encoder is not limited to the second-degree Booth's algorithm but a higher-degree Booth's algorithm may also be used instead.

Claims: A multiplier for calculating a product of a multiplier factor and a multiplicand each of which is a binary number in twos-complement representation, said multiplier comprising: a multiplier factor encoder (10) for generating a plurality of encoded values from said multiplier factor; a plurality of partial product generators (11-14) for generating, from said multiplicand and said plurality of encoded values, a plurality of partial products which are binary numbers in twos-complement representation having a difference of two or more digits in weight; and a partial product adder (15) for summing up said plurality of partial products to calculate said product, wherein said partial product adder comprises: a Wallace tree adder (20) having a plurality of inputs and at least one output for performing addition with respect to said plurality of partial products; and a logic circuit for providing values, in a plurality of digit positions higher than a sign digit of the first partial product (P0) having the smallest weight of said plurality of partial products, to implement sign extension of said first partial product, characterized in that said logic circuit specifically has the functions of: providing the value of the sign digit (P0s) of said first partial product (P0) in each of the digit positions of said first partial product extending from the one digit higher than the sign digit (P0s) of said first partial product (P0) to the on corresponding to the digit position one digit lower than a sign digit (P1s) of the second partial product (P1) having the second smallest weight of said plurality of partial products; providing a first exclusive OR (41) value between the value of the sign digit (P0s) of said first partial prnduct (P0) and the value of the sign digit (P1s) of said second partial product (P1) in the digit position of said first partial product corresponding to the sign digit (P1s) of said second partial product (P1); providing a first OR (42) value between the value of the sign digit (P0s) of said first partial product (P0) and the value of the sign digit (P1s) of said second partial product (P1) in each of the digit positions of said first partial product extending from the one corresponding to the digit position one digit higher than the sign digit (P1s) of said second partial product (P1) to the one corresponding to the digit position one digit lower than a sign digit (P2s) of the third partial product (P2) having the third smallest weight of said plurality of partial products; providing a second exclusive OR (43) value between said first OR (42) value and the value of the sign digit (P2s) of said third partial product (P2) in the digit position of said first partial product corresponding to the sign digit (P2s) of said third partial product (P2); and providing a second OR (44) value between said first OR (42) value and the value of the sign digit (P2s) of said third partial product (P2) in each of the digit positions of said first partial product extending from the one corresponding to the digit position one digit higher than the sign digit (P2s) of said third partial product (P2) to the one corresponding to the sign digit (P3s) of the most significant partial product (P3) having the largest weight of said plurality of partial products, and wherein a specified one of said plurality of inputs of said Wallace tree adder (15) presents shorter propagation delay to said outpout than at least one other input, and said first partial product (P0) after sign extension implemented by said logic circuit is allocated to said specified input.

Inventors: MIYOSHI AKIRA, MIYOSHI, AKIRA
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1997
Main classification: G06F7
IPC codes: G06F7