BALLAST CIRCUIT

Abstract: A ballast circuit is disclosed which includes an inverter for generating an alternating voltage comprising at least one switching element, a load circuit coupled to the inverter and comprising terminals for lamp connection, a driving circuit coupled to the switching element for generating a driving signal for rendering the switching element alternately conducting and non-conducting, a measuring circuit coupled to the load circuit and the driving circuit for generating a first signal that is a measure for a current flowing in the load circuit. In accordance with the invention the driving circuit further comprises phase-shifting circuitry for generating a second signal that is phase shifted with respect to the first signal and in that the driving circuit comprises control means for controlling that the driving signal is substantially in phase with the second signal. Because of the phase shift between the first signal and the driving signal, capacitive operation is effectively avoided.

Description: Ballast Circuit The invention relates to a ballast circuit for operating a lamp comprising - an inverter for generating an alternating voltage comprising at least one switching element, - a load circuit coupled to the inverter and comprising terminals for lamp connection, - a driving circuit coupled to the switching element for generating a driving signal for rendering the switching element alternately conducting and non-conducting, - a measuring circuit coupled to the load circuit and the driving circuit for generating a first signal that is a measure for a current flowing in the load circuit. Such a ballast circuit is known from U.S. Patent No. 4,952,849. Ballast circuits or electronic lamp ballasts as they are also called include inverters to provide a high frequency substantially square wave voltage output to a load. The load typically includes a load circuit that during operation comprises a lamp. A typical inverter circuit includes power switching circuitry (i.e. transistors) to convert a DC input to a desired high frequency AC output. A control circuit, such as disclosed in U.S. Patent No. 4,952,849 to Fellows et al. for driving the switching circuitry of a voltage-fed inverter, senses current flowing through the load to control the switching circuitry. The switches are turned on so as to minimize damage thereto during transition. This is commonly referred to as zero-voltage switching (ZVS). The switching technique minimizes voltage across the switch as the switch is being turned on. The switching frequency of the inverter is typically above the resonant frequency of the resonant circuit, that is to maintain the resonant circuit in an inductive mode. It is critical to maintain the circuit in an inductive mode when transitioning between the power switches in a ZVS scheme. Otherwise, large power losses and damage to the components within the circuit can result. One commonly used method to achieve zero-voltage switching is to maintain the switching frequency higher than the resonant frequency, as described in Steigerwald, "A Comparison of Half-Bridge Resonant Converter Topologies," IEEE Transactions on Power Electronics. April 1988, pp. 174-181. This frequency-based scheme can be easily implemented using voltage controlled oscillators (VCO). However, a critical requirement of such control method is that prior knowledge of the resonant frequency is needed to determine the frequency sweeping region. In simple applications, for example, in LC resonant inverter-based power supplies and electronic ballasts with a single lamp, the maximum gain frequency does not change significantly during the load and line changes as long as the inverters are operated in the high-Q condition. In these cases, the frequency- based control method operates successfully. However, in some cases, the characteristics of the resonant circuit can change with lamp loads, bus voltage, ambient conditions or aging of the components. Such changes can affect the operating mode of the resonant circuit. Simple frequency based control methods may be unable to adapt to the new frequency-sweep region and therefore be unable to maintain zero voltage switching. The circuit of Nalbant, described in "A New and Improved Control Technique," Proceedings of IEEE Applied Power Electronics Conference. March 1995, pp. 657-664, achieves zero voltage switching by increasing the operating frequency above the resonant frequency. Switching occurs by setting thresholds on the current flowing in a loading matching network. When one of these thresholds is crossed, switching occurs in the inverter. This approach has the disadvantage that threshold values must be chosen and set, and complex logic must be implemented. If the current values experience large fluctuations, the threshold may not be crossed and a correct switching cycle may be missed, or the wrong operating frequency may result. Accordingly, it is the object of the invention to provide a zero-voltage switching scheme for a power supply or ballast comprising an inverter which overcomes the above mentioned disadvantages of the prior art. A ballast circuit as described in the opening paragraph is therefore in accordance with the invention characterized in that the driving circuit further comprises phase-shifting circuitry for generating a second signal that is phase shifted with respect to the first signal and in that the driving circuit comprises control means for controlling that the driving signal is substantially in phase with the second signal. The phase-shifting circuitry realizes a phase angle shift between the first signal and the driving signal an therefore also between the current in the load circuit and the alternating voltage generated by the inverter. Because of this phase angle shift, capacitive operation of the inverter is prevented and ZVS is effectively realized. Preferably the second signal is shifted by a predetermined positive phase angle shift with respect to the first signal such that the alternating voltage generated by the inverter is leading the first signal with the predetermined positive phase angle. It has been found that the phase-shifting circuit can be relatively simple in this case. Good results have been obtained for ballast circuits according to the invention, wherein the driving signal renders the switching element conductive when the second signal crosses zero. It has been found that a relatively easy and dependable way of realizing the phase shifting circuitry is by making use of an all-pass filter. It can be desirable to include a filter in the ballast circuit for suppressing a low frequency component of the first signal. Good results have also been obtained for ballast circuits according to the invention, wherein the inverter comprises a halfbridge inverter. These and other objects, features and advantages of the invention will become apparent with reference to the accompanying drawings and the following detailed description and claims. In the drawings FIG. 1 is a block diagram of the power supply in accordance with an exemplary embodiment of the subject invention; FIG. 2 is a schematic diagram of the inverter and the power supply; FIG. 3 is a block diagram of the power supply, illustrating the particular functions of the driving circuit; FIG. 4 is a schematic diagram of a portion of the driving circuit, illustrating the high-pass filter, gain control, phase-shift circuitry, and wave-shaping functions; FIG. 5 is a partial schematic, partial logic diagram of a portion of the driving circuit, illustrating the wave-shaping and PWM functions; FIG. 5 A is partial block diagram, partial schematic diagram of the timing circuit of Fig. 5; FIG. 6 is a schematic diagram illustrating the start-up circuitry; FIG. 7 is a schematic diagram illustrating the frequency sweep function associated with start-up; FIG. 8 is a schematic diagram illustrating the bridge driver circuitry; FIG. 8A is a schematic diagram illustrating the functions of the driver IC; and FIG. 9 is a time plot of the current flowing through the resonant circuit, the phase-shifted signal, and the switching sequence of the switches. The power supply circuit shown in FIG. 1 includes a voltage source V, inverter circuit A, resonant circuit and load B, and driving circuit C which controls inverter circuit A. Voltage source V is a direct current voltage source supplying inverter circuit A via lines RL1 and RL2. Alternatively, an AC voltage source may be substituted in conjunction with a rectifier circuit, which may further include power correction. Inverter circuit A is of the voltage-fed half-bridge topology, and is under control of the driving circuit C. Resonant circuit B receives the substantially square wave output of inverter circuit A on lines 100 and 102 into a substantially sinusoidal lamp current. In the exemplary embodiment, the load is a multiple parallel-loaded lamp system. The driving circuit C receives a voltage signal proportional to the current flowing through the resonant circuit B via line 104. Phase shifting circuitry is present in driving circuit C to shift the sensed current signal by a predetermined phase angle. The phase angle φ nf is an input to the system. This phase angle could also be used as a dimming interface in dimmable lamp systems. The driving signals 106 and 108 to the inverter are based upon this phase-shifted current signal to provide zero-voltage switching and to control inverter circuit A. Turning now to FIG. 2, inverter circuit A includes a pair of switches Ql and Q2 which are arranged in a half-bridge configuration and convert the DC voltage from voltage source V to a high-frequency substantially square wave AC output signal across the inverter outputs, under the control of driver circuit C. Although the present embodiment is described with respect to a half-bridge inverter having a pair of switches, the switching scheme described herein is applicable to a full bridge topology having four switches. In such a configuration, the switches would be controlled in pairs rather than individually. The switches Ql and Q2 are preferably MOSFETs, although it is contemplated that BJTs could also be used as the power switches. Switch Ql is connected in parallel with parasitic diode Dl. A snubber capacitor may also be connected in parallel with switch Ql, which may include the junction capacitor contingent to switch Ql. Similarly, switch Q2 is connected in parallel with parasitic diode D2. Likewise, a snubber capacitor may also be connected in parallel with switch Q2, which may include the junction capacitor contingent to switch Q2. The drain of switch Ql is connected via the rail RL1 to the output from the voltage source V. The source of the switch Ql is connected to the drain of switch Q2. The control gate of switch Ql is connected via control line 108 to a respective gate controller terminal of driving circuit C via a parallel arrangement of a resistor RIO and a diode D10. The anode of diode D10 is connected to the control gate of the switch Ql. The diode D10 provides rapid evacuation of charges from the control gate to enhance switching speed. The control gate of switch Q2 is similarly connected to a gate controller terminal of driving circuit C through control line 106. A similar parallel arrangement exists for switch Q2 with resistor R12 and diode D12. This particular arrangement has been implemented in conjunction with MOSFET switches Ql and Q2. A different gate drive would be implemented for bipolar transistor switches, which is within the scope of the present invention. Line 100 connects the midpoint I between the source of the switch Q2 and the drain of the switch Ql to one end of the blocking capacitor Cbk. Capacitor Cbk blocks DC components of the inverter output voltage generated at node I. Line 112 connects the midpoint I via resistor R14 to driving circuit C, as will be described below. Line 102 is connected to the drain of switch Q2. Line 100 and line 102 serve as the output of inverter circuit A. The output of inverter A is a substantially square wave signal. With continued reference to Fig. 2, The resonant circuit B shapes the voltage and current waveforms to the load, such as a parallel loading of instant start fluorescent lamps LI, L2, L3, and L4, each in series with ballasting capacitors CL1, CL2, CL3, and CL4, respectively. The resonant circuit B includes resonant inductor Lr connected in series with the blocking capacitor Cbk via line 100. Resonant capacitor Cr is connected in parallel with a primary winding of isolation transformer Tl. Due to the filtering action of the resonant circuit B on the square wave voltage output of the inverter circuit A, the current flows with a substantially sinusoidal waveform. This current is sensed by the voltage drop on line 102 across R20, having a small resistance. The sensed current signal on line 104 serves as a input to driving circuit C as will be described below. Fig. 3 illustrates, in block diagram form, the components of driving circuit C. Current sensing circuit 200 senses the voltage drop across RSI. High-pass filter 204 is used to filter one of the frequency components of the sensed current. The frequency component corresponding to the operating frequency is permitted to pass, but lower frequency signal components are suppressed from the current signal. Automatic gain control 206 is utilized to control the amplitude of the signal so as to avoid saturating circuit components. Phase shifting circuitry 208 provides a phase shift of φ nf to the signal. Wave shaping circuitry 210 is triggered by the zero-crossing points of the phase-shifted current signal. Pulse width modulation 212 produces the switch pulses, and gate driver 216 controls the timing of the switches and corresponding duty cycles. Start-up logic 214 transitions operation of the lamp from start-up to the steady state operating condition. Turning now to FIG. 4, current sensing circuit 200, a differential ampli- fier, senses the voltage drop across R20. R22, R24, R26, R28 and R30 are connected to op- amp 202, such as LT1122, to provide output voltage signal on line 106 which is proportional to the current in the resonant circuit B. The signal is substantially sinusoidal at the operating frequency, and normally has lower frequency components. High pass filter 204 receives the signal of the sensed current. Capacitor CIO and resistor R32 are selected to suppress this low frequency component of the current signal. The present invention is applicable to resonant circuits of higher order as well. Therefore, there may be a plurality of low frequency components to the oscillating current signal which are suppressed by filter 204. Automatic gain control 206 is provided on the output from high pass filter 204, which prevents the sensed current signal from saturating the components of the circuitry. A pair of inverting op amps 220 and 222 are used to scale the signal magnitude and provide positive gain factor. The ratio of external resistors R34/R36 for op amp 220 and R38/R40 for op amp 222 are selected to scale the signal. Because the amplitude of the signal flowing through the circuit may fluctuate, an automatic gain controller 224 is used to maintain the signal within a given range. Automatic gain controller 224 includes op-amp 226. The gain is controlled by voltage controlled resistor, such as JFET Tl, in parallel with impedance R42. The gate of JFET Tl is connected to the feedback path consisting of impedance R44, diode D20, zener diode D22 and RC circuit consisting of resistance R46 and capacitance C12. An additional inverting amplifier 226 further scales the signal by selection of resistors R52 and R54. Phase shifting of the signal is performed by the phase-shifting circuitry 208, which includes the pair of all-pass filters 228 and 230 in series. The all-pass filters incorporate op-amps such as LT1122. As is known in the art, such filters provide a loop gain of 1 but provide a predetermined phase angle shift to the signal passing therethrough. The circuitry of the present invention allows the phase angle to be a driving variable. As described above, the application of a positive phase angle to the sensed current signal ensures zero-voltage switching when the zero-crossing points of the phase shifted signal is used as a control signal for turning on the switches in the inverter circuit A. Ideally, the selection of any positive phase angle will assure zero- voltage switching. In practice, however, due to the junction capacitance of the MOSFETs used for switches Ql and Q2, there is a minimum phase angle requirement. The phase angle may be implemented by an open loop or a closed loop based scheme. In the open loop scheme, the amount of phase shift may be preselected by selecting the amount of resistance R56 and R58 in parallel with the capacitors C14 and C16, repsectively, to the non-inverting input in all-pass filters 228 and 230, respectively. Alternatively, voltage controlled resistors, such as JFETs may be used. The present circuit is shown with two all-pass filters, although a greater or fewer number of filters are contemplated. The optimum phase shift may be determined empirically from the circuit characteristics, such as the capacitance of the snubbing capacitors in parallel with switches Ql and Q2 if used in the circuit, or the current. Alternatively, a closed loop scheme may be implemented. With such a scheme, output voltage regulation may be performed by sensing the output voltage across the load. Since the output voltage is a function of the operating frequency or the phase angle, output voltage regulation may be achieved by adjusting the phase angle in order to produce the desired output voltage. This scheme may find application in light dimming ballasts. Following the phase shifting of the signal, the wave shaping circuitry 210 provides timing for the initiation of the switching as will be described below. Filter including capacitor C18 shapes the signal, and buffer 230 is a voltage follower interposed to provide a low output impedance and isolation from the input. The output of buffer 230 is on line 119. Noninverting amplifier 232 (Fig. 5) includes op-amp 234, and external resistors R60 and R62 are selected to scale the voltage. Filter 236 includes resistor R64 and C20. With continued reference to Fig. 5, the switching signal is generated by a timing circuit, such as 555 timing IC 300, produced by Motorola, the specifications of which are incorporated by reference herein and illustrated in Fig. 5A. Timer 300 is configured in the monostable mode wherein the driving signal is triggered to the "on" state by the zero- crossing of the phase-shifted current signal. Comparator 310 converts the substantially sinusoidal analog voltage signal from filter 236 to a square wave sequence which corresponds to the zero-crossing point of the shifted current signal. The comparator converts this zero- crossing point to set the leading edge of the switching pulse. Applied voltage VI, in combination with resistors R66 and R68 and diode D30, provide a proper scaling to the signal to the inverter II. High pass filter 238, including capacitor C22 and resistor R70 and diode D32 in parallel, and inverter 12 further shape the signal on line 120, which is connected to the trigger input (pin 2) of the timer 300. The threshold terminal (pin 7) and the discharge terminal (pin 6) are connected together in this mode. The control voltage at pin 5 is preset to a constant value by a voltage divider with resistors R72 and R74. The output signal is present on line 122 from output terminal (pin 3). Output signal on line 122 from timing circuit 300 and output on line 123 from start-up circuit 320 pass through OR gate 214 which acts as an electronic switch. As illustrated in Figs. 6-7, start-up circuit 320 provides the function of initial frequency sweeping for lamp ignition. Start-up circuit 210 includes voltage controlled oscillator (VCO) 312, single pulse flip-flop 314 in Fig. 6 and a DC voltage sensing and scaling circuit 316 (Fig. 7). VCO 312 is preferably voltage-to-frequency converter AD654 produced by Analog Devices of Norwood, Massachusetts, the specifications of which are incorporated by reference herein, although any suitable VCO is contemplated for use in this circuit. Comparator 318 and single pulse flip flop 320 in Fig. 7. The start-up process is described as follows. In Fig. 6, before the DC bus voltage V is fully built up, the voltage in line 130 is low and the output pin Q of the flip flop 314 is high. VCO 312 starts to operate at high frequency region f ιuut which leads to a high frequency square wave signal in line 123. The output voltage of the resonant circuit B is low due to the high frequency operation and lower DC bus voltage V. When the DC bus voltage is increased to a preset threshold, the output voltage of comparator 318 in Fig. 7 is set to low. This in turn triggers the flip flop 320 and sets the voltage to high at line 130. Effectively, in Fig. 6, the voltage input at control voltage terminal (pin 4) of VCO 312 is reduced gradually. Correspondingly, the output frequency produced by VCO 312 is reduced. This process completes the frequency sweeping from high frequency f 8tΔrt to lower operating frequency f^. Correspondingly, the resonant circuit output voltage to the lamps LI, L2, L3 and L4 is gradually increased until the lamps are ignited. After the lamps are operating, the processed current signal in line 122 triggers the flip-flop 314 and the output signal on line 123 is blocked by using the OR gate 322. Subsequently, the power supply in Fig. 3 operates at a self-oscillating frequency with predetermined phase angle φ nf . Turning now to Fig. 8, the signal 124 is inverted at logical inverter 16. The signal subsequently passes to the "in" terminal at gate driver 330, such as half-bridge driver integrated circuit IR2111 produced by International Rectifier, El Segundo, California, the specifications of which are incorporated by reference herein and illustrated at Fig. 8A. With continued reference to Fig. 8, gate driver 330 includes logic to convert a single square wave input signal, such as that on line 124, into two separate driving signals on lines 108 and 106 which control switches Ql and Q2, respectively. Gate driver 330 may be configured to produce signals 108 and 106 such that a blanking time exists in which neither Ql nor Q2 conduct. The waveforms produced by the above-described circuit are represented in the time plot illustrated in Fig. 9. The current flowing through the resonant circuit B is represented on the plot by signal 500. Within driving circuit C, this signal corresponds to the voltage signal on line 114, which is proportional to the current and has been filtered of lower frequency components by high-pass filter 204 (See, Figs. 3-4). As described above, the signal on line 114 passes through automatic gain control 206 and phase-shifting circuitry 208. The phase shifted signal 502 corresponds to the output of phase-shifting circuitry 208 on line 118 (See, Fig. 4). The phase-shifted signal 502 is phase-shifted by an amount 504 corresponding to φ nf as described above. The zero-crossing point of signal 502 is used as the reference to control switching. Thus, at the zero-crossing point 508, switch Ql is turned off, as indicated by line 510 (solid line) and switch Q2 is turned on, as indicated by line 512 (dot-dash line). The figure illustrates that Q2 is turned on at the same time that Ql is turned off. A blanking time 514 is ordinarily provided by driver 304 such that Ql and Q2 are both off for a brief period of time. While there has been shown to be what are presently considered to be the preferred embodiments of the invention, it will apparent to those of ordinary skill in the art that various modifications can be made without departing from the scope of the invention as defined by the appended claims. Accordingly, the disclosure is illustrative only and not limiting.

Claims: CLAIMS: 1. A ballast circuit for operating a lamp comprising - an inverter for generating an alternating voltage comprising at least one switching element, - a load circuit coupled to the inverter and comprising terminals for lamp connection, - a driving circuit coupled to the switching element for generating a driving signal for rendering the switching element alternately conducting and non-conducting, - a measuring circuit coupled to the load circuit and the driving circuit for generating a first signal that is a measure for a current flowing in the load circuit, characterized in that the driving circuit further comprises phase-shifting circuitry for generating a second signal that is phase shifted with respect to the first signal and in that the driving circuit comprises control means for controlling that the driving signal is substantially in phase with the second signal. 2. A ballast circuit as claimed in claim 1, wherein the second signal is shifted by a predetermined positive phase angle shift with respect to the first signal such that the alternating voltage generated by the inverter is leading the first signal with the predetermined positive phase angle. 3. A ballast circuit as claimed in claim 1 or 2, wherein the driving signal renders the switching element conductive when the second signal crosses zero. 4. A ballast circuit as claimed in claim 1, 2 or 3, wherein the phase shifting circuitry includes an all-pass filter. 5. A ballast circuit as claimed in one or more of the previous claims, wherein the driving circuit includes a filter for suppressing a low frequency component of the first signal. 6. A ballast circuit as claimed in one or more of the previous claims, wherein the inverter comprises a halfbridge inverter.

Inventors: CHANG JOSEPH, CHIN CHANG, CHANG, JOSEPH, CHIN, CHANG
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1997
Main classification: H05B41
IPC codes: H02M7, H05B41