DIFFERENTIAL AMPLIFIER

Abstract: The invention provides for a receiver, such as a differential receiver (300), that includes a first input (302), a second input (304), and an output (306). The receiver (300) has a first signal path from the first input (302) to the output, the first signal path including a first differential amplifier (308) and a first active load (312) wherein the first differential amplifier (308) has an end connected to a first power supply voltage (VDD) and a second end connected to a second power supply voltage and the first active load (312). The first differential amplifier (308) also has a connection to the first input (302) and the second input (304), and the first active load (312) has a connection to the output (306). The receiver (300) also has a second signal path from the second input (304) to the output (306), the second signal path including a second differential amplifier (310) and second active load (314), wherein the second differential amplifier (310) has an end connected to a first power supply voltage and a second end connected to a second power supply voltage (VDD) and the second active load (314). The second differential amplifier (310) also has a connection to the first input (300) and the second input (304), and the second active load (314) has a connection to the output (306). The first signal path and the second signal path both have the same number of devices.

Description: DIFFERENTIAL AMPLIFIER 1. Technical Field The present invention relates to a receiver circuit and m particular, but not exclusively, to differential receivers and to differential receivers for receiving high speed low voltage signals. Still more particularly, the present invention relates to differential receivers for receiving high speed low voltage signals with minimized delay skew. 2. Description of the Related Art Differential receivers for high speed, low voltage differential signalling (LVDS) applications require symmetric, low delay skew responses for a wide range of common mode and differential input signals. With these two conditions, the skew will vary due to faster propagation of one signal edge. Skew is the difference between a low-to- high transition delay (t LH ) and high-to-low transition delay (t HL ) , i.e. skew* = t LH - t HL or skew = t HL - t LH . In Figure 1, a typical implementation of a differential receiver with an active load is illustrated. Receiver 100 includes negative input 102 and positive input 104 along with an output 106. The input differential pair of transistor 108 and transistor 110 drives a current mirror containing transistor 112 and transistor 114. This current mirror m turn drives the gate of transistor 116, which is an output device connected to output 106. Transistors 108 and 110 are n-channel metal-oxide-semiconductor (MOS) transistors while transistors 112-116 are p-channel MOS transistors. Additionally, receiver 100 includes transistors 118 and 120, which are n-channel MOS transistors. Current sources 122 and 124 also are found in receiver 100. Receiver 100 is powered by connections to a first power supply voltage and a second power supply voltage m which the first power supply voltage is an upper power supply voltage VDD and the second power supply voltage is a lower power supply voltage, such as for example, ground. A low-to-high (LH) rising signal edge propagates faster than the falling edge of a high-to-low (HL) of the output signal. The LH rising edge of the input signal quickly pulls down the gate of transistor 116 and drives the output at output 106 high with very little delay. In contrast, the falling edge of the output signal at output 106 encounters more delay because as the input signal undergoes the HL transition, transistor 110 is being turned off. Through the action of the current mirror including transistors 112 and 114, transistor 116 is turned off by the rising voltage on its gate. This delay is caused by the mirroring effect from transistor 112 to transistor 114 and will always cause a larger delay for an HL transition The difference in LH and HL propagation delays results in a delay skew m receiver 100 for the high output state. A further problem exists with using a constant current source at transistor 116 for the output pull-down is a constant power dissipation during the output at output 106 being in a high logic state. For a fast output pull-down, the current of transistor 120 has to be large and causes a large static power dissipation m receiver 100. Turning next to Figure 2 , a more symmetrical implementation of a receiver known in the art is depicted. In this case, receiver 200 includes a negative input 202 and a positive input 204 along with an output 206 Receiver 200 contains a differential pair of transistors 208 and 210, which drives symmetric diode-connected transistors 214 and 216 These two transistors serve as an active load for the differential pair of transistors 202 and 204. In this depicted circuit, the delay path, formed by transistors 216 and 218, for a LH transition is shorter than the delay path around the loop consisting of transistors 214, 220, 222, and 224 for HL transitions. Receiver 200 exhibits a skew problem for a small differential input signal centred around a common mode equal to about one-half of a VDD power supply voltage. The LVDS specifications require that the receiver guarantees very small skew for a specified range of differential input voltage (e.g. from about 70 mV to about 400 mV) and for large common-mode voltage ranges (e.g., from about 0.7 V to about 1.8 V) for a power supply voltage VDD equalling about 3.3 volts plus or minus five percent. The input overdrive will speed up the LH transition more than the HL transition and thus increase the skew. The common mode voltage will have similar and more severe effects upon the skew problems due to the changing operating conditions of the input and active load devices. Thus, it would be advantageous to have an improved receiver in which skew is reduced. The invention seeks to provide for a receiver device exhibiting advantages over known devices. According to one aspect of the present invention there is provided a receiver comprising a first input configured to receive a first signal, a second input configured to receive a second signal, an output, a first signal path having a first end connected to the first input and the second input and a second end connected to the output , wherein the first signal path includes a first number of devices and generates a first transition in an output signal generated at the output in response to a first type of potential difference between the first signal received at the first input and the second signal received at the second input, a second signal path having a first end connected to the first input and the second input and a second end connected to the output, wherein the second signal path includes a second number of devices equal in number to the first number of devices and generates a second transition in an output signal generated at the output in response to a second type of potential difference between the first signal received at the first input and the second signal received at the second input, and wherein the devices within the first signal path and the second signal path are configured to minimize skew between the first type of transition and the second type of transition of the output signal at the output . According to another aspect of the present invention there is provided a differential receiver comprising a first input, a second input, an output, a first p-channel transistor, a second p-channel transistor, and a first current source, the first p-channel transistor and second p- channel transistor each having a gate, a drain, and a source, the first current source having a first end connected to the source of the first p-channel transistor and the source of the second p-channel transistor and a second end connected to a first power supply voltage, the gate of the first p-channel transistor being connected to the first input and the gate of the second p-channel transistor being connected to the second input, wherein the first p-channel transistor, the second p-channel transistor, and the first current source form a first differential amplifier, a first n-channel transistor, a second n-channel transistor, and a second current source, the first n-channel transistor and second n-channel transistor each having a gate, a drain, and a source, the second current source having a first end connected to the source of the first n- channel transistor and source of the second n-channel transistor and a second end connected to a second power supply voltage, the gate of the first n-channel transistor being connected to the first input and the gate of the second n-channel transistor being connected to the second input, wherein the first n-channel transistor, the second n- channel transistor, and the second current source form a second differential amplifier, a third n-channel transistor and a fourth n-channel transistor, the third n-channel transistor and the fourth n-channel transistor each having a gate, a drain, and a source, the third n-channel transistor being a diode-connected transistor, the source of the third n-channel transistor and the source of the fourth n-channel transistor being connected to the second power supply voltage, the gate of the third n-channel transistor being connected to the gate of the fourth n-channel transistor, the drain of the third n-channel transistor being connected to the gate of the third n-channel transistor and to the drain of the second p-channel transistor, the drain of the fourth n-channel transistor being connected the output, the third n-channel transistor and the fourth n-channel transistor forming a first active load, a third p-channel transistor and a fourth p-channel transistor, the third p-channel transistor and the fourth p- channel transistor each having a gate, a drain, and a source, the third p-channel transistor being a diode connected transistor, the source of the third p-channel transistor and the source of the fourth p-channel transistor being connected to the first power supply voltage, the gate of the third p-channel transistor being connected to the gate of the fourth p-channel transistor, the drain of the third p-channel transistor being connected to the gate of the third p-channel transistor and to the drain of the second n-channel transistor, the drain of the fourth p- channel transistor being connected to the output, the third p-channel transistor and the fourth p-channel transistor forming a second active load. According to a further aspect of the present invention there is provided a differential receiver comprising a first input, a second input, an output, a first signal path from the first input to the output, the first signal path including, a first differential amplifier, and a first active load, wherein the first differential amplifier has an end connected to a first power supply voltage and a second end connected to a second power supply voltage and the first active load and wherein the first differential amplifier has a connection to the first input and the second input and the first active load has a connection to the output, a second signal path from the second input to the output, the second signal path including, a second differential amplifier; and a second active load, wherein the second differential amplifier has an end connected to a first power supply voltage and a second end connected to a second power supply voltage and the second active load and wherein the second differential amplifier has a connection to the first input and the second input and the second active load has a connection to the output, wherein the first signal path and the second signal path both have an equal number of devices and the output devices in the first active load and the second active load are driven by the first differential amplifier and the second differential amplifier. According to yet another aspect of the present invention there is provided a receiver comprising a first input, a second input, an output, wherein high and low output voltages are generated by the output in response to input signals applied to the first input and the second input, a first differential amplifier and a second differential amplifier, each differential amplifier having a connection to the first input and a connection to the second input and the first differential amplifier having a number of devices identical to a number of devices within the second differential amplifier, and a first active load and a second active load, each active load having a connection to the output and the first active load having a number of devices identical to a number of devices within the second active load, wherein the first differential amplifier and the first active load are used to generate a high-to- low voltage transition at the output in response to a positive potential difference between signals applied to the first input and the second input and the second differential amplifier and the second active load are used to generate a low-to-high voltage transition in response to a negative potential difference between signals applied to the first input and the second input and wherein the devices within the first differential amplifier, the second differential amplifier, the first active load, and the second active load are configured to minimize skew m the high-to-low voltage transition and the low-to-high voltage transition . SUMMARY OF THE INVENTION The present invention provides a differential receiver that includes a first input, a second input, and an output. The receiver has a first signal path from the first input to the output, the first signal path including a first differential amplifier and a first active load. The first differential amplifier has an end connected to a first power supply voltage and a second end connected to a second power supply voltage and the first active load. The first differential amplifier also has a connection the first input and the second input, and the first active load has a connection to the output. The receiver also has a second signal path from the second input to the output, the second signal path including a second differential amplifier and second active load. The second differential amplifier has an end connected to a first power supply voltage and a second end connected to a second power supply voltage and the second active load. The second differential amplifier has a connection the first input and the second input, and the second active load has a connection the output. The first signal path and the second signal path both have the same number of devices . BRIEF DESCRIPTION OF THE DRAWINGS The invention is described further hereinafter, by way of example only, with reference to the accompanying drawings m which: Fig. 1 is a typical implementation of a differential receiver with an active load; Fig. 2 is a more symmetrical implementation of a receiver known in the art; Fig. 3 is a schematic diagram of a receiver according to an embodiment of the present invention; Fig. 4 is a more detailed schematic diagram of receiver 300 of Fig. 3; and Fig. 5 is a diagram of input and output signals from the receiver of Fig. 4. DETAILED DESCRIPTION With reference now to the figures, and in particular with reference to Fig. 3, a schematic diagram of a receiver is depicted according to an embodiment of the present invention. Fig. 3 is a complementary metal oxide semiconductor (CMOS) implementation of the present invention. Receiver 300 in Fig. 3 includes a positive input 304, a negative input 302, and an output 306. Inputs 302 and 304 receive input signals while output 306 provides a signal that is delivered to another device or circuit . Receiver 300 also includes a differential amplifier 308, a differential amplifier 310, an active load 312, and an active load 314. The differential amplifiers produce currents, and the active loads are used to convert the currents into an output voltage at output 306. Receiver 300 is powered by a first power supply voltage and a second power supply voltage. The first power supply voltage is an upper power supply voltage (e.g., VDD), and the second power supply voltage is a lower power supply voltage (e.g., VSS or ground) . Differential amplifier 308 includes transistor 316, transistor 318, and a current source 320. In the depicted example, transistor 316 and transistor 318 are p-channel metal-oxide-semiconductor (MOS) transistors. Differential amplifier 310 includes transistor 322, transistor 324, and a current source 326. In the depicted example, transistor 322 and transistor 324 are n-channel metal-oxide- semiconductor (MOS) transistors. Active load 312 contains transistors 328 and 330 while active load 314 contains transistors 332 and 334. Transistors 328 and 330 are n- channel MOS transistors, while transistors 332 and 334 are p-channel MOS transistors. The gates of transistors 328 and 332 are tied to their drains such that transistors 328 and 330 and transistors 332 and 334 operate as current mirrors. Additionally, transistor 332 is a diode-connected transistor. The devices in differential amplifier 308 and active load 312 form a first signal path from inputs 302 and 304 to output 306, while the devices in differential amplifier 310 and active load 314 form a second signal path from inputs 302 and 304 to output 306. The devices in differential amplifier 310 and active load 314 are used in LH voltage transitions at output 306, and the devices in differential amplifier 308 and active load 312 are used in HL voltage transitions at output 306. LH voltage transitions occur at output 306 in response to signals applied at inputs 302 and 304 having a positive potential difference. HL voltage transitions occur at output 306 in response to signals applied at inputs 302 and 304 having a negative potential difference. As can be seen, two differential input pairs (transistors 316 and 318 and transistors 322 and 324) are employed. Transistors 316 and 318 drive transistor 330 directly through transistor 328, which is a diode-connected transistor. Similarly, transistors 322 and 324 drive transistor 334 directly through transistor 332. According to the present invention, both signal paths for generating LH and HL voltage transitions have a smaller number of devices than in present receiver configurations. Additionally, according to the present invention, an identical number of devices are present in both in signal paths, and both differential amplifiers drive the output devices directly. Additionally, the present invention provides another advantage in that no static power dissipation occurs in the output stage formed by transistors 330 and 334. Thus, the present invention provides a high speed receiver that operates over a specified range of common mode voltages and differential input signals as required in low voltage differential signaling technology while minimizing skew between rising and falling edges of the output signal. With reference now to Fig. 4, a more detailed schematic diagram of receiver 300 in Fig. 3 is depicted according to the present invention. Reference numbers repeated from Fig. 3 in Fig. 4 refer to the same transistors in these two figures. Current source 320 in Fig. 3 correspond to a current mirror consisting of diode-connected p-channel transistor NPl and p-channel transistor MP5. Similarly, current source 326 is implemented by a current mirror consisting of diode-connected n-channel transistor MN3 and n-channel transistor MN4. Transistor MP3A is connected to transistor 322 to add a matching active load device to transistor 332. Similarly, transistor MN5A has been connected to transistor 316 to provide a matching active load device to transistor 328. Terminal VDDA provides an upper power supply voltage to receiver 400 while terminal VSSA provides a lower power supply voltage. Terminals BIASP and BIASN are employed in level shifting of receiver 400. Transistors MP8 and MP9 along with their respective sources, transistors MP2 and MP4 serve as level shifters for transistors 322 and 324 to accommodate a common mode input range from about 0.7 V to about 1.8 V. Transistors NPDN1-NPDN5, which are n-channel transistors, and transistors NPD1-NPD4, which are p-channel transistors, are employed during power-down of receiver 400 using terminal PD . Transistors MN3 and MN4 are n-channel transistors while transistors MPl, MP2 , MP4 , and MP5 are p- channel transistors. These transistors are also used during power-down of receiver 400. Transistors MP7 and MN7 form an output buffer employed to drive a load connected to terminal RECOUT . Transistors NPDN0 and MPPU are used for bringing input INM to a low state and input INP to a high state to minimize noise and to prevent oscillators in case of floating inputs. The receivers depicted in Figs. 3 and 4 may be employed in circuits having differential inputs and a single ended output. In particular, the receiver of the present invention may be implemented in devices such as, for example, operational amplifiers and comparators. With reference now to Fig. 5, a diagram of input and output signals from a receiver according to an embodiment of the present invention is depicted. Diagram 500 is a diagram of an Hspice simulation of the receiver depicted in Fig. 4. The skew s the difference between the low-to-high (t PL ..) and the high-to- low (t PHL ) output delay. In the depicted example, the delay for the LH transition is t PLH = 2.18ns, and the delay for the HL transition t PHL = 2.99ns, resulting in a skew less than 1 nanosecond; skew is equal to 0.81ns. The depicted example employs three input/output cases for three common-mode levels of the input (0.7 V, 1.25 V, and 1.8 V) . As can be seen, the low amount of skew is achieved by making the two signal paths from the input to the output for HL and LH voltage transitions equal and as short as possible. In the depicted example, the differential receiver maintains this low skew for a differential input signal range from approximately 70 V to greater than 400 mV. The common mode range achieved by the depicted example is from about 0.7 V to about 1.8 V as required by IEEE Standard SPI-2 for SCSI Low Voltage Differential interface. Thus, the present invention provides an improved high speed receiver capable of operating over a specified range of common mode voltages and differential input signals with minimized skew between rising and falling edges of the output signal. These advantages are provided by employing signal paths from the inputs to the output for HL and LH transitions that are equal in length and as short as possible . While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled m the art that the invention is not restricted to the details of the foregoing embodiment .

Claims: CLAIMS 1. A receiver (300) comprising: a first input (302) configured to receive a first signal; a second input (304) configured to receive a second signal ; an output (306) ; a first signal path (308, 312) having a first end connected to the first input (302) and the second input (304) and a second end connected to the output (306), wherein the first signal path includes a first number of devices and generates a first transition in an output signal generated at the output in response to a first type of potential difference between the first signal received at the first input and the second signal received at the second input ; a second signal path (310, 314) having a first end connected to the first input (302) and the second input (306) and a second end connected to the output (306) , wherein the second signal path (310, 314) includes a second number of devices equal in number to the first number of devices and generates a second transition in an output signal generated at the output in response to a second type of potential difference between the first signal received at the first input and the second signal received at the second input ; and wherein the devices within the first signal path (308, 312) and the second signal path (310, 314) are configured to minimize skew between the first type of transition and the second type of transition of the output signal at the output . 2. A receiver as claimed in Claim 1, wherein the first signal path and the second signal path each include a differential amplifier (308, 310). 3. A receiver as claimed in claim 1 or 2 , wherein the first signal path and the second signal path each include an active load (312, 314) . 4. A receiver as claimed in Claim 1, 2 or 3 , wherein the said first type is positive potential difference and the said first transition is a high-to-low transition. 5. A receiver as claimed in Claim 4, wherein the said second type is a negative potential difference and the said second transition is a low-to-high transition. 6. A receiver as claimed in Claim 1, wherein the first signal path includes: a first differential amplifier (308) ; a first active load (312), wherein the first differential amplifier (308) is connected to the first power supply voltage and the second power supply voltage and the first active load (312) and wherein the first differential amplifier (308) has a connection to the first input (302) and the second input (304) and the first active load (312) has a connection to the output (306) ; the second signal path includes : a second differential amplifier (310) ; a second active load (314), wherein the second differential amplifier (310) is connected to the first power supply voltage and a second end connected to the second power supply voltage and the second active load (314) and wherein the second differential amplifier (310) has a connection to the first input (302) and to the second input (304) and the second active load (314) has a connection to the output (306) ; and wherein the first signal path and the second signal path both have an equal number of devices and the output devices in the first active load (312) and the second active load (314) are driven by the first differential amplifier (308) and the second differential amplifier (310) . 7. A receiver as claimed in Claim 6, wherein the first differential amplifier (308) comprises a first transistor (316), a second transistor (318), and a first current source (320) , the first transistor and second transistor each having a gate, a drain, and a source, the first current source having a first end connected to the source of the first transistor and the source of the second transistor and a second end connected to a first power supply voltage, the gate of the first transistor being connected to the first input and the gate of the second transistor being connected to the second input; and wherein the second differential amplifier (310) comprises a third transistor (322) , a fourth transistor (324) , and a second current source (326) , the third transistor and fourth transistor each having gate, a drain, and a source, the second current source having a first end connected to the source of the third transistor and source of the fourth transistor and a second end connected to a second power supply voltage, the gate of the third transistor being connected to the first input and the gate of the fourth transistor being connected to the second input . 8. A receiver as claimed in Claim 7, wherein the first transistor (316) and the second transistor (318) are p- channel metal-oxide-semiconductor transistors. 9. A receiver as claimed in Claim 7 or 8, wherein the third transistor (322) and the fourth transistor (324) are n-channel metal -oxide-semiconductor transistors. 10. A receiver as claimed in Claim 7, 8 or 9 , wherein the first active load (312) comprises a fifth transistor (328) and a sixth transistor (330) , the fifth transistor and the sixth transistor each having a gate, a dram, and a source, the fifth transistor (328) being a diode -connected transistor, the source of the fifth transistor and the source of the sixth transistor being connected to the first power supply voltage, the gate of the fifth transistor being connected to tne gate of the sixth transistor, the dram of the fifth transistor being connected to the gate of the fifth transistor and to the dra of the second transistor, the dram of the sixth transistor being connected to the output ; and wherein the second active load (314) comprises a seventh transistor (332) and an eighth transistor (334), the seventh transistor (332) and the eighth transistor (334) each having a gate, a drain, and a source, the seventh transistor (332) being a diode-connected transistor, the source of the seventh transistor and the source of the eighth transistor being connected to the second power supply voltage, the gate seventh transistor being connected to the gate of the eighth transistor, the dram of the seventh transistor being connected to the gate of the seventh transistor and to the drain of the fourth transistor, the drain of the sixth transistor being connected the output. 11. A receiver as claimed in Claim 10, wherein the fifth transistor (328) the sixth transistor (330) are n-channel metal -oxide -semiconductor transistors . 12. A receiver as claimed m Claim 10 or 11, wherein the seventh transistor (332) and the eighth transistor (334) are 5 p-channel metal-oxide-semiconductor transistors. 13. A receiver as claimed in any one of Claims 6 to 12 , wherein the first input (302) is a negative input and the second input (304) is a positive input. 0 14. A receiver as claimed in any one of Claims 6 to 13, wherein the first signal path causes a transition from high- to-low voltage transition in a signal generated at the output . J 15. A receiver as claimed in any one of Claims 6 to 14, wherein the second signal path causes a low-to-high voltage transition in a signal generated at the output. 0 16. A receiver as claimed in Claim 6, wherein the first differential amplifier (308) comprises a first p-channel transistor, a second p-channel transistor, and a first current source, the first p-channel transistor and second p- channel transistor each having a gate, a drain, and a source, the first current source having a first end connected to the source of the first p-channel transistor and the source of the second p-channel transistor and a second end connected to a first power supply voltage, the gate of the first p-channel transistor being connected to the first input and the gate of the second p-channel transistor being connected to the second input, wherein the first p-channel transistor, the second p-channel transistor, and the first current source form a first differential amplifier; the second differential amplifier (310) comprises a first n-channel transistor, a second n-channel transistor, and a second current source, the first n-channel transistor and second n-channel transistor each having a gate, a drain, and a source, the second current source having a first end connected to the source of the first n-channel transistor and source of the second n-channel transistor and a second end connected to a second power supply voltage, the gate of the first n-channel transistor being connected to the first input and the gate of the second n-channel transistor being connected to the second input, wherein the first n-channel transistor, the second n-channel transistor, and the second current source form a second differential amplifier; the first active load (312) comprises a third n-channel transistor and a fourth n-channel transistor, the third n- channel transistor and the fourth n-channel transistor each having a gate, a drain, and a source, the third n-channel transistor being a diode-connected transistor, the source of the third n-channel transistor and the source of the fourth n-channel transistor being connected to the second power supply voltage, the gate of the third n-channel transistor being connected to the gate of the fourth n-channel transistor, the drain of the third n-channel transistor being connected to the gate of the third n-channel transistor and to the dram of the second p-channel transistor, the drain of the fourth n-channel transistor being connected the output, the third n-channel transistor and the fourth n-channel transistor forming a first active load; and the second active load (314) comprises a third p- channel transistor and a fourth p-channel transistor, the third p-channel transistor and the fourth p-channel transistor each having a gate, a dram, and a source, the third p-channel transistor being a diode connected transistor, the source of the third p-channel transistor and the source of the fourth p-channel transistor being connected to the first power supply voltage, the gate of the third p-channel transistor being connected to the gate of the fourth p-channel transistor, the drain of the third p- channel transistor being connected to the gate of the third p-channel transistor and to the dram of the second n- channel transistor, the drain of the fourth p-channel transistor being connected to the output, the third p- channel transistor and the fourth p-channel transistor forming a second active load. 17. A receiver as claimed in Claim 16, wherein the first power supply voltage is an upper power supply voltage and the second power supply voltage is a lower power supply voltage . 18. A receiver as claimed in Claim 17, wherein the upper power supply voltage is VDD. 19. A receiver as claimed in Claim 17 or 18, wherein the lower power supply voltage is a ground voltage. 20. A receiver as claimed in Claim 16, wherein the first p- channel transistor and the second p-channel transistor drive the fourth n-channel transistor directly and the first n- channel transistor and the second n-channel transistor drive the fourth p-channel transistor directly to generate a signal at the output. 21. A receiver as claimed in Claim 16, wherein the first input is a negative input. 22. A receiver as claimed in Claim 21, wherein the second input is a positive input. 23. A receiver as claimed in Claim 1, wherein the first path comprises a first differential amplifier (308) and a first active load (312), and the second path comprises a second differential amplifier (310) and a second active load (314), wherein each said differential amplifier (308, 310) includes a connection to the first input and a connection to the second input and the first differential amplifier having a number of devices identical to a number of devices within the second differential amplifier; each said active load (312, 314) having a connection to the output and the first active load having a number of devices identical to a number of devices within the second active load; and wherein the first differential amplifier (308) and the first active load (312) are used to generate a high-to-low voltage transition at the output in response to a positive potential difference between signals applied to the first input and the second input and the second differential amplifier (310) and the second active load (314) are used to generate a low-to-high voltage transition m response to a negative potential difference between signals applied to the first input and the second input and wherein the devices within the first differential amplifier, the seconα differential amplifier, the first active load, and the second active load are configured to minimize skew m the high-to-low voltage transition and the low-to-high voltage transition. 24 A receiver as claimed in Claim 23, wherein the devices within the first differential amplifier (308) mcluαe a differential pair of p-channel transistors (316, 318) . 25. A receiver as claimed in Claim 24, wherein the first active load (312) includes a pair of n-channel transistors (328, 330) configured as a current mirror. 26. A receiver as claimed in Claim 23, 24 or 25, wherein the second differential amplifier (310) includes a differential pair of n-channel transistors (322, 324) . 27 A receiver as claimed in Claim 26, wherein the second active load includes a pair of p-channel transistors (332, 334) configured as a current mirror. 28. A receiver as claimed in any one of Claims 23 to 27, wherein the receiver has a common mode input range of about 0.7 V to about 1.8 V. 29. A receiver as claimed in any one of Claims 23 to 28, wherein a potential difference between signals applied to the first input and the second input range from about 70 V to about 400mV. 30. A method of generating an output signal in a receiver (300) comprising the steps of: connecting a first input (302) to a first end a signal path comprising a first differential amplifier (308) including a first transistor (316), a second transistor (318) , and a first current source (320) , and a first active load (312) including a device connected to an output (306) ; and connecting a second input (304) to first end of a second signal path comprising a second differential (310) amplifier including a first transistor (322) , a second transistor (324), and a second current source, and a second active load (314) including a device connected to the output , wherein the second differential amplifier (310) and the second load (314) have a number of devices identical to a number of devices in the first differential amplifier and the first active load and each device within the first differential amplifier, the second differential amplifier, the first active load, and the second active load are sized to minimize skew within the receiver.

Inventors: GASPARIK FRANK, GASPARIK, FRANK
Applicants: GILL DAVID ALAN, SYMBIOS LOGIC INC, GILL, DAVID, ALAN, SYMBIOS LOGIC INC.
Application year: 1997
Main classification: H03F3
IPC codes: H03F3