Testing of a semi-conductor integrated circuit device

Abstract: In a semi-conductor integrated circuit device, a memory space provided with the integrated circuit device is not occupied by space for testing the integrated circuit device as the testing memory space. In the test mode of the semi-conductor integrated circuit device, test of internal circuit is capable of being implemented due to the fact that it permits a part of region belonging to the integrated circuit device to allocate to outer memory space. While in a normal operation mode, degree of freedom of design of the integrated circuit device is increased by releasing the testing memory space.

Description: BACKGROUND OF THE INVENTION The present invention relates to a semi-conductor integrated circuit device. More to particularly, this invention relates to a test circuit of a semi-conductor integrated circuit device. Description of the Prior Art Formerly, in the test circuit of the semi-conductor integrated circuit device, in order to implement a performance test of an internal circuit, a part of space of an internal memory region is set to a test memory region. Test instruction code, test data, and so forth are written in terms of this test memory region beforehand. The region within which test instruction code and test data are written is accessed in the test mode, thus implementing the test of the internal circuit. However, under this test method, it is necessary to ascertain a test instruction code and a test data of the internal circuit. Furthermore, there is the problem that when error occurs, analytical property is very low. In order to cope with such the problem, one test method is disclosed in the Japanese Patent Application Laid-Open No. HEI 1-239485. In this test method, memory region for a test is constituted by a RAM. The test instruction code and the test data are down loaded from the outer section, before performing the test. However, in general, an area of a RAM is larger than that of a ROM. Furthermore, since it is necessary to provide a redundant circuit such as a writing circuit thereto from the outer section, enlargement of chip area is enforced. As another method, terminal for memory-access is provided for outer terminal, thus taking a test instruction code and test data therein from an outer-chip. EP-A-0 556 826 describes a semiconductor integrated circuit device comprising a decoder for decoding the inputted macro instructions and an external test mode setting circuit. However in these prior art, when it permits memory region for the test to allocate to internal memory, there is the defect that enlargement of hardware scale is enforced. A part of the memory space is occupied as the test region, there is the defect that effective practical use of whole memory region is disturbed accordingly. Particularly, in recent year, various core of the processor is required. Design of ACIC system using macro block becomes realistic. Under this state, degree of freedom of design of system is disturbed remarkably, because a part of memory space for a test is incapable of being utilized beforehand. SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide a semi-conductor integrated circuit device provided with improved test method. It is another object of the present invention to provide a semi-conductor integrated circuit device which is capable of performing test of the internal circuit with increasing of hardware suppressed to minimum. According to one aspect of the present invention, for achieving the above-mentioned object, there is provided a semi-conductor integrated circuit device using single-chip semi-conductor which comprises address decode means for decoding that space is test memory space, when a test mode instruction signal denotes to be test mode, it causes a decode signal outputted from said address decode means to be effective, while when a test mode instruction signal denotes to be non-test mode, it causes a decode signal outputted from said address decode means to be ineffective, when said decode signal is active, allocating memory region accessed by said semi-conductor integrated circuit device to outer part memory region of said semi-conductor integrated circuit device. When output of test region address decoder denotes to be test region, there are means for bringing access to normal memory region into ineffective and access to outer memory region into effective. The above and further objects and novel features of the invention will be more fully understood from the following detailed description when the same is read in connection with the accompanying drawings. It should be expressly understood, however, that the drawings are for purpose of illustration only and are not intended as a definition of the limits of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a first embodiment according to the present invention; Fig. 2 is a block diagram showing an address decoder of Fig. 1; and Fig. 3 is a block diagram showing an address decoder of a second embodiment according-to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the invention will now be described in detail referring to the accompanying drawings. Fig. 1 is a block diagram showing an internal circuit of an integrated circuit of a first embodiment according to the present invention. In the first embodiment, an internal-data-bus-width is taken as 16 bits, and an address-width is taken as 16 bits. In the test mode, 8k words after 0xe000h are used as a test region. It is suitable to set capacity of outer memory region, and layout on memory space for the test mode voluntarily in answer to necessity. It is not necessary to be stuck with the embodiment. The integrated circuit device of the first embodiment comprises an arithmetic circuit 1, an internal memory 2, an address bus 4, a data bus 5, and data lines 6, 7, 8, 9, 10, 11, 12, 13, 14 and 15. The arithmetic circuit 1 is a block within single-chip microprocessor which block implements data arithmetic, thus outputting memory access address with 16 bits address from the data line 6 to the address bus 4. The arithmetic circuit 1 performs input-output of data in terms of 16-bits data bus 5 from the data line 9. The internal memory 2 is a memory with 16 bits of one-word-width included in the single-chip microprocessor. Operation of the internal memory 2 is activated by value indicated by the data line 13. The internal memory 2 obeys address data on the address bus 4 inputted from the data line 7, thus implementing input-output of data in terms of the data bus 5 from the data line 10. An address data inputted from the data line 8 on the address bus 4 is decoded by the address decoder 3 depending on a value which indicates test mode inputted from the data line 15, the address decoder 3 outputting selection signal of internal data memory region to the data line 13, and outputting outer memory selection signal to the data line 14. A data on the address bus 4 is outputted to the other address terminal for accessing the outer memory from the data line 11. A data on the data bus 5 is connected to the outer terminal of data bus by the data line 12. Fig. 2 is a gate circuit view showing one example of the address decoder 3. The address decoder 3 comprises 4-input NAND gate 21, and an inverter 22. The data line 15 which is the input line of signal denoting test mode is connected to input of 4-input NAND gate 21. High-order 3 bits within the data line 8 to which address data is inputted are connected to the input of the 4-input NAND gate 21. Output of the 4-input NAND gate 21 is outputted as an outer memory selection signal from the data line 14. Output of the 4-input NAND gate 21 is connected to input of the inverter 22. Output of the inverter 16 is outputted as an internal memory selection signal from the data line 13. Next, operation of the integrated circuit device will be described. Firstly, a case of normal operation will be described. In case of the normal operation test mode signal is set to "0". On account of this setting, "0" is inputted to the 4-input NAND gate 21 from the data line 15, so that the data line 14 connected to the output-end becomes "1". Since the input-end of the inverter 22 becomes "1", the data line 13 connected to the output-end becomes "0". Chip selection signal of the normal memory is active in low level. Consequently, in this embodiment, when memory selection signal is "0", there is considered that memory comes into active, it is not necessary to be restrained especially to "0" / "1" of signal. For example, when active memory with "1" is used, it is proper to perform inversion-output of respective memory selection signals. In the embodiment, the outer memory becomes non-selection state in accordance with the value of the data line 14 so that the internal memory is selected. Under this state, when it permits the single-chip microprocessor to operate, input-output of data between the internal memory 2 and the single-chip microprocessor is capable of being implemented. At this time, the outer memory region does not function because the outer memory selection signal becomes non-selection state. Consequently, in the normal operation mode, the arithmetic circuit 1 is capable of accessing the internal memory 2 in all address space. Namely, it is not necessary to ensure specific region on memory space for a test beforehand, thus becoming possible to use all memory space effectively. Next, operation at the time of test mode will be described. At the time of test mode, test mode signal is set to "1". On account of this setting, "1" is inputted to the 4-input NAND gate 21 from the data line 15. When all bit of high-order 3 bits of the data line 8 with 16-bit-width, and bit 15 to bit 13 are "1", namely, when 0xc000h to 0xffffh addresses are inputted, output of the 4-input NAND gate 21 becomes "0". Consequently, at this time, the outer memory selection signal comes into active, while the internal memory selection signal comes into inactive to the contrary. Under this condition, in the arithmetic circuit 1 of the single-chip microprocessor, addresses of 0x0000h to 0xdfffh access the internal memory region, while addresses of 0xc000h to 0xffffh access the outer memory. When the test of processor is implemented, the test of the internal circuit is capable of being performed by inputting the instruction code, test data and so forth to the processor from the outer memory region. It is not necessary to write the test instruction code and the test data to the inside of internal circuit, thus testability improving. When only restricted region is used as the test memory region, the outer memory region is capable of being reduced. Namely, when 1k word within the address space with 16-bit width is used as test region, it is sufficiently that there are only ten pieces of address terminals for outputting to the outer memory so that necessary numbers of terminal for the test are capable of reducing. Furthermore, in this test mode, test of peripheral circuit which is mapped into the area is capable of being performed because the access thereto can be implemented in the same way as the normal operation in terms of regions with the exception of the address region which is switched to the outer memory region. In the above embodiment, example with respect to only one memory space is shown. Due to the fact that respective memory space has the same circuit, it is capable of being applied to test circuit of microprocessor with a plurality of memory spaces. For example, in the microprocessor with Harvard architecture, an instruction memory region and a data memory region are separated into two memory spaces. Recently, single-chip micro processor with a lot of memory spaces such as digital signal processor (DSP) and so forth, is known. In these processors, it becomes possible to control an access to the outer memory space in every memory space independently. At this time, the number of outer terminal is capable of reducing by the method of pin-multiplexing and so forth. Next, a second embodiment of the invention will be described in detail. Although a fundamental constitution of the second embodiment is the constitution which is similar to the first embodiment as shown in Fig. 1, an address decoder 3 is constituted as shown in Fig. 3. The address decoder 3 comprises a test address decoder 31, a ROM address decoder 32, a RAM address decoder 33, 2-input NAND gates 34, 35, and 36, and data lines 8, 13, 14, 37, 38, and 39. The data line 8 is connected to input-ends of respective address decoders 31, 32, and 33. The data line 37 is connected to an output-end of the test address decoder 31. The data line 38 is connected to an output-end of the ROM address decoder 32. The data line 39 is connected to an output-end of the RAM address decoder 33. The data line 15 and the data line 37 are connected to an input-end of the 2-input NAND gate 34. The data line 14 is connected to an output-end of the 2-input NAND gate 34. The data line 14 and the data line 38 are connected to input-ends of the 2-input NAND gate 35. Bit [1] of the data line 13 is connected to an output-end of the 2-input NAND gate 35. The data line 14 and the data line 39 are connected to input-ends of the 2-input NAND gate 36. Bit [0] of the data line 13 is connected to an output-end of the 2-input NAND gate 36. The internal memory 2 of the second embodiment is constituted by two blocks of the ROM and the RAM. The data line 13 becomes 2-bit data line because the data line 13 has a selection signal of the ROM and the RAM respectively. Bit [1] is ROM selection signal, and bit [0] is RAM selection signal. The test address decoder 31 decodes an address data inputted from the data line 8, thus outputting "1" when the test address decoder 31 denotes a test memory region, while when the test address decoder 31 does not denote the test memory region, "0" is outputted. The ROM address decoder 32 decodes an address data inputted from the data line 8, thus outputting "1" when the ROM address decoder 32 denotes a ROM memory region, while when the ROM address decoder 32 does not denote the ROM memory region, "0" is outputted. The RAM address decoder 33 decodes an address data inputted from the data line 8, thus outputting "1" when the RAM address decoder 33 denotes a RAM memory region, while when the RAM address decoder 33 does not denote the RAM memory region, "0" is outputted. At the time of normal operation mode, "0" as the test mode signal is inputted from the data line 15. On account of the input, output of the 2-input NAND gate 34 becomes "1", while outer part memory selection signal comes into inactive. Since input of one side of respective 2-input NAND gates 35, 36 becomes "1", the 2-input NAND gate 35 inversion-outputs value of the data line 37, and the 2-input NAND gate 36 inversion-outputs a value of the data line 39. Consequently, when output of the ROM address decoder 32 comes into active, the ROM selection signal within the internal memory selection signal comes into active, and when output of the RAM address decoder 33 comes into active, the RAM selection signal within the internal memory selection signal comes into active. In answer to this state, when the address denotes the ROM region, input-output of data in relation to the internal ROM becomes possible, while when the address denotes the RAM region, input-output of data in relation to the internal RAM becomes possible. Consequently, in the time of normal operation mode, the single-chip microprocessor is capable of accessing the ROM or the RAM of the internal memory mapped to the voluntary address on the memory space in accordance with the address data outputted from the internal arithmetic circuit 1. In the test mode, "1" as the test mode signal is inputted from the data line 15. At this point, when the value which is indicated by the address data inputted from the data line 8 denotes the region mapped into outer memory region for the test, output of the test address decoder 31 becomes "1", and output of the 2-input NAND gate 34 becomes "0". At this time, input of one side of respective 2-input NAND gate becomes "0", therefore, output of the 2-input NAND gates 35, 36 always become "1". On the assumption that memory region of the ROM is established such that it includes the test memory region, with regard to the test memory region within the address of ROM in the test mode, access to the internal ROM is negated, while access to the outer memory region is implemented. Namely, it is not necessary to allocate the specific region within the memory space included into the arithmetic circuit as a test memory space beforehand. In the second embodiment, it is shown that the internal memory region is divided into two regions of the ROM and the RAM. Also in the cases where the internal memory region is divided into a lot of regions, an enlargement thereof is capable of implementing with the same method. Namely, when it permits selection signal in terms of respective memory regions to generate, the enlargement can be realized by masking region selection signal (one or the plural) which uses memory region corresponding to the test memory region by virtue of test memory region selection signal coming into active only at the time of test mode. It can be considered that one or the plural regions within the divided regions is also allocated to the outer part memory. At this case, it is capable of coping with this case using logical add of both of the test memory selection signal and the outer part memory selection signal in the normal mode as the practical outer memory. At this time, outer part address terminal for accessing outer part memory, outer part data bus terminal, outer part memory selection signal output terminal are capable of being shared. When selection of the memory to be accessed is implemented, there is the method using read / write strobe signal in terms of respective memory regions. It is capable of coping with the method having read / write strobe signal by using respective memory region selection signals in the embodiment as the masking signal of these strobe signals. Furthermore, when it permits hardware resources exception for memory to map to memory space, the test is capable of being performed by accessing these hardware resources from the arithmetic circuit by virtue of mapping exception for the test memory region also in the test mode. As stated-above, according to the present invention, specific region on the memory space is switched to the outer memory space at the time of only test mode. It is not necessary to write the test instruction code or test data therein beforehand. There is the effect that modification of a test program or test data is implemented easily. It is not required to ensure region for including the test instruction code or the test data on the inside thereof. The hardware scale is capable of being reduced because it is not necessary to provide an exclusive hardware resources for storing data and so forth. The test region does not occupy a part of the memory region, thus being capable of increasing degree of freedom on the memory space. Since a part of space within the memory space is used as the test region, it becomes not necessary to output all bit of address data, thus being capable of reducing number of outer terminals. While preferred embodiment of the invention have been described using specific terms, such description is for illustrative purpose only, and it is to be understood that changes and variations may be made without departing from the scope of the following claims.

Claims: A single-chip integrated semiconductor circuit device comprising: an internal memory (2), an address decoder (3) receiving address data (ADDRESS) representing a test memory space and a test mode instruction signal (TEST MODE), and outputting a decoding signal (14), said decoding signal (14) being active when said test mode instruction signal indicates a test mode and being inactive when said test mode instruction signal indicates a non-test mode, and means (21) for allocating the test memory space to an external memory region when said decoding signal is active, characterized by means (21,22) for enabling access of the integrated circuit device to the whole memory space of the internal memory (2) when said decoding signal is inactive. The circuit device according to claim 1, wherein said test memory space corresponds to a part of the memory space of said internal memory, and address data having an address width denoting the inside of said test memory space are outputted at outer terminals. The circuit device according to claim 1, wherein internal resources are mapped to a memory region corresponding to said test memory space. Integrated circuit device according to claim 1, further comprising outer terminals serving in common as accessing terminals and as test terminals, respectively. The integrated circuit device according to claim 1 further comprising a plurality of memory spaces, wherein said address decoder comprises means for decoding that respective spaces are test memory spaces corresponding to respective spaces of said plurality of memory spaces. A test method of a semiconductor integrated circuit device using single-chip semiconductor comprising the steps of: decoding that a memory space to be accessed is a test memory space, decoding a test mode instruction signal and activating a decoding signal when said test mode instruction signal denotes a test mode, and deactivating said decoding signal when said test mode instruction signal denotes a non-test mode, and allocating said test memory space accessed by said semiconductor integrated circuit device to an external memory region of said semiconductor integrated circuit device when said decoding signal is active, characterized by enabling access to the whole memory space of an internal memory when said decoding signal is deactivated. The test method of claim 6 of a semiconductor integrated circuit device having a plurality of memory spaces comprising the step of: decoding that said respective spaces are test memory spaces corresponding to respective spaces of said plurality of memory spaces.

Inventors: ISHIDA RYUJI, ISHIDA, RYUJI
Applicants: NEC ELECTRONICS CORP, NEC ELECTRONICS CORPORATION
Application year: 1997
Main classification: G11C29
IPC codes: G06F12, G01R31, G11C29