Digital video signal processor

Abstract: In a digital video signal processor for compressing a digital video signal and recording the compressed signal, a black-and-white signal detector (210) determines whether the digital video signal is a black-and-white signal and outputs a detection signal when it is determined that the digital video signal is a black-and-white signal. A block processor (220) shuffles the digital video signal from the black-and-white signal detector by predetermined block units. A signal compressor (250) compresses the shuffled video signal output by the block processor (220). A modulator (270) modulates the compressed video signal output by the signal compressor (250) and a black-and-white signal information. A controller (230) generates a compression control signal to output to the signal compressor (250) and outputs the black-and-white signal information to the modulator (270) in response to the detection signal. When the compression control signal is received, the signal compressor (250) transform-encodes the shuffled video signal such that a color component is encoded only with a DC coefficient. As a result, a black-and-white video signal can be recorded with a higher-resolution.

Description: The present invention relates to a digital video signal processor, and more particularly, to a digital video signal processor such as a digital video tape recorder or a digital video camera for processing a black-and-white video signal. In general, when a video data is recorded on a video tape in a digital video cassette recorder or a digital camcoder, the video data is recorded in a predetermined format. Figures 1A through 1C illustrate one of the recording format of a general digital video cassette recorder. Figure 1A shows a discrete cosine transform (DCT) block which is a set of 8x8 (64) pixels. Figure 1B shows a macro block having six DCT blocks, i.e., four luminance components Y1, Y2, Y3 and Y4, and two color difference components Cb and Cr. Figure 1C shows a video segment which consists of five macro blocks MB1, MB2, MB3, MB4 and MB5. Each of the DCT blocks for the luminance components Y1, Y2, Y3 and Y4 of the macro blocks in Figure 1B are discrete-cosine-transformed to be 14 bytes of DCT coefficients, which includes one DC coefficient and a plurality of AC coefficients. Also, each of the DCT blocks for the color difference components Cb and Cr are discrete-cosine-transformed to be 10 bytes of DCT coefficients, which includes one DC coefficient and a plurality of AC coefficients. However, in a conventional digital video signal recorder, even when a user records a black-and-white video signal, the AC coefficients of the color difference components Cb and Cr are still recorded on the tape, which results in lowering of the compression efficiency. Further, the AC coefficients of the color difference components Cb and Cr may vary without being kept at a predetermined level, which results in noise in the video signal. JP-A-63-175593 (Toshiba Corporation) discloses an analogue colour decoder that detects the presence of a colour burst signal in a video signal, and provides a relay changeover circuit to replace an RGB output by a luminance signal when the video signal is a black and white signal. It is an aim of embodiments of the present invention is to provide a black-and-white video signal recorder for reducing noise and recording a black-and-white: video signal with high resolution when it is desired to record a black-and-white signal only among a video signal. According to one aspect of the present invention, there is provided a digital video signal processor for compressing a digital video signal and recording the compressed signal. In the digital video signal processor, a black-and-white signal detector determines whether the digital video signal is a black-and-white signal and outputs a detection signal when it is determined that the digital video signal is a black-and-white signal. A block processor shuffles the digital video signal from the black-and-white signal detector by predetermined block units. A signal compressor compresses the shuffled video signal output by the block processor. A modulator modulates the compressed video signal output by the signal compressor and a black-and-white signal information. A controller generates a compression control signal to output to the signal compressor and outputs the black-and-white signal information to the modulator in response to the detection signal. When the compression control signal is received, the signal compressor transform-encodes the shuffled video signal such that a color component is encoded only with a DC coefficient. As a result, a black-and-white video signal can be recorded with a higher-resolution. Preferably, said signal detector determines that the digital video signal is a black-and-white signal when a color burst signal is absent in the digital video signal. Preferably, said data compressor converts the value of the DC coefficient of the encoded signal into a predetermined value when the compression control signal is received. The predetermined value is preferably an average of numbers represented by 8 bits. For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figures 1A-1C illustrate recording formats of a general digital video cassette recorder; and Figure 2 is a block diagram of an embodiment of a digital video signal processor according to the present invention. Referring to Figure 2, a digital video signal processor includes a black-and-white signal detector 210 for determining whether an input video signal is a black-and-white signal, a block processor 220 for shuffling the video data output by the black-and-white signal detector 210 to build up a video segment, a memory 240 for storing the data processed by the block processor 220 temporarily, a data compressor 250 for compressing the data output by the block processor 220, a parity adder 260 for adding parity to the compressed video data output by the data compressor 250, a modulator 270 for modulating video data received from the parity adder 260 and a black-and-white signal information data, a recording head 280 for recording the modulated data in a recording medium, and a controller 230 for applying a compression control signal to the data compressor 250 to set color components to a predetermined value and generating a black-and-white signal information according to the detection signal from the black-and-white signal detector 210. In Figure 2, an input video signal is a digital video signal converted from an analog video signal so that it can be recorded in a recording medium of a digital video cassette recorder or a digital video camera. The black-and-white signal detector 210 determines whether the digital video signal is a black-and-white signal or a color signal. There are many methods for such a determination. For example, when a digital video signal does not include a color burst signal, the digital video signal is determined as a black-and-white signal, otherwise, it is determined as a color signal. The block processor 220 carries out shuffling of the data output by the black-and-white signal detector 210 to increase the compression efficiency. When data is shuffled, macro block units are taken from five different areas of one frame and combined to be a segment unit. The memory 240 temporarily stores data processed by the block processor 220. During playback, the shuffled data is unshuffled to restore to be the original data in a reproducer not shown. The data compressor 250 compresses the digital video signal from the block processor 220 by carrying out a discrete cosine transform (DCT) and a variable-length coding (VLC). When the black-and-white signal detector 210 receives a black-and-white video signal, it applies a black-and-white detection signal which is an active high pulse to the controller 230. Upon receiving the detection signal, the controller 230 generates the compression control signal to output to the data compressor 250 so that the data compressor 250 transform-encodes the shuffled video signal only with a DC coefficient. Also, the controller 230 outputs the black-and-white signal information to said modulator 270 in response to the detection signal. In response to the compression control signal output by the controller 230, the data compressor 250 converts a DC coefficient among the DCT coefficients of the color difference components Cb and Cr into the predetermined DC value and sets AC coefficients to zero. Since the AC coefficients become zero, that is, there is no changing signal except for a DC signal, noise in an input video data signal or quantization noise is reduced. Furthermore, if the data amount of the encoded luminance components is large, the luminance components may be recorded in the area which was allocated for the AC coefficients of the color components. In the present embodiment, the DC level is 128, which is a median value of numbers represented by 8 bits. As a result, when the color component is converted into a predetermined DC value in the data compressor 250, the resolution is increased since more AC coefficients of the transformed luminance component may be recorded in the area for the color components Cr and Cb of the macro block shown in Figure 1B compared with case in which a color signal exists. Meanwhile, the parity adder 260 adds a parity to the video data output by the data compressor 250 so that the video data is reproduced from the medium with negligible error during a playback. The modulator 270 modulates the video data output by the parity adder 260 and the black-and-white signal information generated by the controller 230, so that a recording head 280 records the modulated data on the recording medium. The black-and-white signal information which is recorded as a side information is used to reproduce the recorded data in a black-and-white video signal during playback. As described above, embodiments of the present invention reduce noise by setting a color component to a predetermined level when a video signal is recorded in a black-and-white mode. Further, a luminance component may be recorded in the area in which the color component would be recorded otherwise, thereby increasing the resolution of the signal.

Claims: A digital video signal processor for compressing a digital video signal and recording the compressed signal, comprising: a black-and-white signal detector (210) for determining whether the digital video signal is a black-and-white signal and outputting a detection signal when it is determined that the digital video signal is a black-and-white signal; a block processor (220) for shuffling the digital video signal from said black-and-white signal detector (210) by predetermined block units; a signal compressor (250) for compressing the shuffled video signal output by said block processor (220) ; a modulator (270) for modulating the compressed video signal output by said signal compressor (250) and a black-and-white signal information; and a controller (230) for generating a compression control signal to output to said signal compressor (250) and outputting the black-and-white signal information to said modulator (270) in response to the detection signal, wherein said signal compressor (250) transform-encodes the shuffled video signal such that a color component is encoded only with a DC coefficient when the compression control signal is received. A digital video signal processor as claimed in claim 1, wherein said signal detector (210) determines that the digital video signal is a black-and-white signal when a color burst signal is absent in the digital video signal. A digital video signal processor as claimed in claim 1 or 2, wherein said data compressor (250) converts the value of the DC coefficient of the encoded signal into a predetermined value when the compression control signal is received. A digital video signal processor as claimed in claim 3, wherein the predetermined value is an average of numbers represented by 8 bits.

Inventors: KIM YONG-JE, KIM, YONG-JE
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1997
Main classification: G11B20
IPC codes: H04N9, H04N5, H03M7, H04N11, G11B20