Semiconductor memory device with redundancy

Abstract: A semiconductor memory device comprising a memory cell array (10) and a redundant memory cell array (12) in which a defective cell in the memory cell array is substituted by a cell in the redundant memory cell array; further comprising: a PROM circuit (46) in which a redundant address corresponding to the defective cell is recorded; a redundant address data holding circuit (48) that holds the data of the redundant address recorded in the PROM circuit (46) on initialisation; a circuit (50) for deciding on redundancy that compares the data held by the redundant address data holding circuit (48) with an address supplied from outside and makes a decision; and a driver circuit (14) for the memory cell array that is actuated in accordance with the result of this decision by the circuit for deciding on redundancy and a driver circuit (16) for the redundant memory cell array. Since a semiconductor memory device as above does not have a PROM circuit that delays the operation in the circuit for deciding on redundancy, high-speed operation of the circuit for deciding on redundancy can be achieved. As a result, overall access time can be reduced.

Description: The present invention relates to a semiconductor memory device such as a dynamic random access memory (DRAM) and more particularly relates to a semiconductor memory device wherein, when redundant memory is provided, access time can be shortened. The capacity of semiconductor memory devices such as DRAMs is continually being increased. It has recently been reported that capacity has reached 1 Gigabit. In such large-capacity memories, redundant memory is provided in order to raise yield by rescuing defective bits, defective word lines, and defective bit lines. In particular, rescue of fixed defects produced by short-circuiting or disconnection of word lines or bit lines due to process factors is adopted in practically all memories. And in recent years techniques have even been proposed to substitute with cells of redundant memory defective bits whose refresh period has become short. A memory including such a redundant memory has a circuit for deciding on redundancy wherein addresses to be substituted are stored in a PROM or the like, to decide whether these coincide with an input address or not. Typically such a circuit for deciding on redundancy is a circuit in which PROM elements such as fuses are incorporated at various different places in the circuit. Fig. 5 is a layout diagram of a prior art memory provided with redundant memory. In this example, a redundant memory cell array 12 is provided in addition to memory cell array 10. In this case, as an example, only the redundant structure on the row side is shown. A word line WL in memory cell array 10 is selected and driven by a row decoder driver 14 that is supplied with a row address 30. The memory data of a memory cell provided at the point of intersection of word line WL and bit lines BL1, BL2 is then read onto bit lines BL1, BL2, sensed and amplified by sense amplifier 20 and applied to input/output circuit 22 through data buses Bus1, Bus2 and output from input/output terminal DQ. The output of sense amplifier 20 is selected by means of column decoder driver 18, which is supplied with a column address 32. A defective word line is substituted with a redundant word line RWL in the redundant memory cell array. A row address corresponding to a defective word line is recorded in PROM in a circuit for deciding on redundancy 24. The circuit for deciding on redundancy 24 determines whether or not a supplied row address coincides with a recorded address. Fig. 6 is a view showing an example of this circuit for deciding on redundancy. This circuit basically has an NOR circuit structure and comprises fuses f0, /f0, f1, /f1 constitutin PROM cells that store a substitute address and N type transistors Q 12 , Q 13 , Q 14 and Q 15 to the gates of which an address is applied from outside, connected in series. P type transistor P 10 and N type transistor Q 11 are the circuits that activate the circuit for deciding on redundancy 24 by H level of redundancy decision timing signal 34. Let us now provisionally assume that fuses f0 and f1 are melted if the substitution address is (A0, A1). Thereupon the operation of this circuit is as follows: redundancy decision timing signal 34 is normally L level and transistor Q 11 is non-conductive, its output 36 being H level. When an address signal is then applied from outside, causing redundancy decision timing signal 34 to become H level, H level of output 36 is maintained only if the external address is (A0, A1) = (1, 1); if an address other than this is applied, a current path as shown by the broken line in the drawing is generated, causing output 36 to become L level. Signal 26 that selects memory cell array 10 is therefore L level in selection, and the signal 28 that selects redundant memory cell array 12 also goes into L level in selection. As described above, in the circuit for deciding on redundancy 24, PROM elements such as fuses which have large resistance or capacitance are present on the critical path of address determination, so the time required to determine the level of output 36 is long. Since, as shown in Fig. 5, a word decoder driver is selected by a decision signal 26, 28 after decision whether the address 30 from outside is the same as a substitution address or not, the speed of circuit for deciding on redundancy 24 is low, making the memory access time long. It is therefore desirable to provide a semiconductor memory device wherein the time required for redundancy decision can be shortened. US-A-5 357 458 discloses an EPROM equipped with redundant cells, an unerasable PROM (UPROM) for storing a redundant address corresponding to defective cells in the EPROM, a latch for holding a redundant address from the UPROM, and a comparator for comparing the latched address with a supplied address. A latch signal is provided to make the latch store a certain address stored in the UPROM. Japanese patent publication No. 03-083298 discloses a semiconductor memory device according to the preamble of accompanying claim 1. In this device, the latch signal applied to the data holding circuit (latch) is generated during the power ON together with the reset signal, leading to a problem that the latch signal may not rise to a sufficient level when the power voltage rises slowly. In addition, there is a problem that the reset operation may not be completed, owing to current flowing through a reset transistor which lowers the voltage of the reset signal when the power voltage rises slowly. According to the present invention, there is provided a semiconductor integrated circuit having a PROM element for storing data indicating a redundant address and a data holding circuit for holding predetermined data wherein the data holding circuit resets the holding data by being supplied with a reset signal which is generated in response to a power ON and the data holding circuit holds the holding data of the PROM element by being supplied with the holding data of the PROM element according to a latch signal, whereby further the data holding circuit includes a first and second gate circuit, each cross-coupled between a first input terminal of one gate circuit and an output terminal of the other, for holding the predetermined data, said reset signal being supplied to a second input terminal of the first gate circuit, and said holding data being supplied to a second input terminal of the second gate circuit, according to said latch signal which is generated in response to an initialization signal supplied from outside at an initialization after the power ON. Since a semiconductor memory device as above does not have a PROM circuit that delays the operation in the circuit for deciding on redundancy, high-speed operation of the circuit for deciding on redundancy can be achieved. As a result, overall access time can be reduced. Furthermore, in a semiconductor memory device as above, a latch signal may be generated in response to a mode register set command supplied from outside on the initialisation and the data of the redundant address recorded in the PROM circuit may be held in the redundant address data holding circuit in response to the latch signal. Reference is made, by way of example, to the accompanying drawings in which: Fig. 1 is a diagrammatic circuit view of a semiconductor memory device according to an embodiment of the present invention; Fig. 2 is a timing chart showing the operation when the power source voltage is turned on; Fig. 3 is a circuit diagram showing an example of a PROM and a latch circuit; Fig. 4 is a circuit diagram showing an example of a PROM, a latch circuit and a circuit for deciding on redundancy; Fig. 5 is a view showing a diagrammatic layout of a conventional memory having redundant memory; and Fig. 6 is a view showing an example of a circuit for deciding on redundancy. An embodiment of the present invention is described below with reference to the drawings. However, the technical range of the present invention is not restricted to this embodiment. Fig. 1 is an outline circuit diagram of a semiconductor memory device according to an embodiment of the present invention. Portions corresponding to the circuit diagram of Fig. 9 illustrating the prior art example are given the same reference symbols. In this example, the data of memory 46 such as a PROM that stores addresses substituted by redundant cells is recorded in a latch circuit 48 in response to a latch signal 52 generated on memory initialisation. This latch circuit 48 does not contain memory elements such as fuses whose stray capacitance or stray resistance is high and which would cause operation to be slowed down. The latch data in latch circuit 48, which is capable of high-speed operation, and the row address 30, which is supplied from outside, are therefore compared by circuit for deciding on redundancy 50, which makes a decision as to whether these are the same or not. Selection signals 26, 28 are generated in accordance with the result of this decision. The invention may be applied to a synchronous DRAM (SDRAM). The SDRAM is known as a high speed operation memory that inputs an operation command, address signals and an input data and outputs an output data in synchronism with a clock signal given by a system. In general when an SDRAM is powered up, synchronously with the rise of the clock CLK supplied from the system, a command 54 corresponding to the operating mode is supplied from the system. The command 54 is then decoded by an incorporated command decoder 40 and the data of the corresponding operating mode is saved in a command register 42. In the operating modes there are for example a mode in which only data corresponding to a given address is output and a mode in which 8-bit data subsequent to a given address is output. A memory operating mode can therefore be specified by a combination of commands from the system and prescribed output operation etc. can be conducted in response to data or an address supplied by the system under this operating mode. The command to set up the aforesaid operating mode is called the mode register set (MRS) command. Thereupon, in the present embodiment, when the power source is turned ON, latch signal generating unit 44 generates latch signal 52, in response to the mode register set command supplied by the system, and address data corresponding to the substituted cell or substituted word line is read into latch circuit 48 from PROM 46. Fig. 2 is a timing chart showing the operation on rise of the power source voltage as mentioned above. In response to rise of the power source voltage, the mode register set command MRS synchronised with the clock CLK from the system is applied as command 54 and a prescribed operating mode is thereby set in command register 42, whereupon the latch signal 52-is generated by latch signal generating circuit 44. Application of this embodiment is not restricted to SDRAM and it can be applied to memories in general. It is important that it should be possible to generate a latch signal 52 by some method or other in the initial stage when the power source voltage is rising and that redundant address data should be capable of being written to latch circuit 48 from PROM 46 in response to this latch signal 52. Fig. 3 is a circuit diagram showing an example of PROM 46 and latch circuit 48. In this example, PROM circuit 46 is provided with an N type transistor Q 47 and fuse elements 56 and a P type transistor P 46 connected between ground and power source V DD . Latch signal 52 is applied to the gates of both transistors. The redundancy address is stored in fuse elements 56. Also, latch circuit 48 is formed by cross-connecting the output and input terminals of NAND gates 58 and 60. The output of PROM circuit 46 is connected to one input terminal of NAND gate 58. The input terminal of the other NAND gate 60 is supplied with a reset signal 62 that is generated on rise of the power source voltage. Regarding the operation of this circuit, in the ordinary condition, latch signal 52 is L level and the output terminal n48 of the PROM circuit is at H level due to P type transistor P 46 being in conductive condition. Transistor Q 47 thereupon conducts in response to an H level latch signal 52 generated on rise of the power source voltage, with the result that the level of output n48 becomes either H level or L level depending on whether fuse element 56 is in open condition or short-circuited condition. The logic level of this output n48 is latched in latch circuit 48. This latch data is held so long as the power source voltage does not drop. This latch circuit can be constituted in simple manner using two ordinary NAND gates constituted for example by CMOS circuits. Incorporation of latch circuit 48 does not therefore itself create much of a problem regarding density of circuit integration. Fig. 4 is a view showing an example of PROM circuit 46, latch circuit 48 and circuit for deciding on redundancy 50. In this Figure, circuit for deciding on redundancy 50 is constituted by decision circuits 500, 501 provided for each address bit and an OR gate 510 that inputs the respective outputs out of these decision circuits. Inverter 520 is provided for forming inverted logic. Each respective address bit unit 100, 101, 102, 103 has PROM circuits 460, 461 and latch circuits 480, 481. The construction of these circuits is the same as described in Fig. 3, so the same reference symbols are used. Within decision circuits 500, 501, there are provided CMOS switches 68, 70 which are ON/OFF controlled in complimentary manner by complimentary output signals 620, 640 or 621, 641 from the latch circuits. These CMOS switches 68, 70 are supplied with positive-phase and negative-phase signals of row address 30 from outside. 66 is an inverter circuit. Then, depending on the data that is written to fuse element 56, one of CMOS switches 68, 70 conducts and the address or its inverted signal 30 corresponding to the conducted CMOS switch 68, 70 is generated at the output labelled "out" in Figure 4. Let us now provisionally assume that the corresponding redundant address in address bit unit 100 is H level and that fuse element 56 was melted. In this case, even if latch signal 52 becomes H level, output n48 stays at H level. Consequently, in latch circuit 480, output 620 becomes L level and output 640 becomes H level. As a result, CMOS switch 68 is in the conductive condition, switch 70 is in non-conductive condition. If thereupon we assume that the address 30 supplied from outside is H level, the L level inverted by inverter 66, passing through switch 68 which is in . conductive condition, makes the output out of address bit unit 100 L level. As described above, if the supplied address and the stored address coincide at all the address bit units, all their outputs out become L level. Consequently the output of OR gate 510 becomes L level and the H level non-selection signal 26 inverted by inverter 520 is applied to decoder driver 14 of defective word line WL and the L-level selection signal 28 is applied to word decoder driver 16 on the redundant side. As a result, redundant word line RWL is driven and drive of defective word line WL is not performed. As is clear from the circuit shown in Fig. 4, the comparison and decision process which the redundant address data latched in the latch circuit and the row address 30 obtained from outside or internally are subjected to is performed by decision circuits 500, 501 which do not contain elements such as fuses which would slow down the operating speed. The operation of address determination can therefore be conducted at high speed. The data in the PROM circuits in which the redundant address is stored are loaded into latch circuits 480, 481 in response to latch signal 52 at the stage of the initial rise in voltage of the power source. Since this loading action is a circuit operation which is conducted by means of fuse elements 56, it cannot be performed at high speed. However, once the substitution address has been latched in the latch circuit 480, 481, the address determination operation for each subsequent access does not have to go through a fuse element and can therefore be performed at very high speed. In particular, if the memory is made of large capacity, the number of addresses to be determined is increased. This therefore means that the high speed of performance of the decision operation at each address enables the decision operation for the totality of addresses to be performed at high speed. As described above, with the present invention, no PROM elements such as fuse elements are arranged on the critical path on which the redundancy decision is made, so the overall access time can be shortened since the operational delay of the circuit for deciding on redundancy caused by high-resistance PROM elements is eliminated.

Claims: A semiconductor integrated circuit having a PROM element (46) for storing data indicating a redundant address and a data holding circuit (48) for holding predetermined data, wherein the data holding circuit (48) resets the holding data by being supplied with a reset signal (62) which is generated in response to a power ON and the data holding circuit (48) holds the holding data of the PROM element (46) by being supplied with the holding data of the PROM element according to a latch signal (52), whereby further said data holding circuit (48) includes a first and second gate circuit (60,58), each cross-coupled between a first input terminal of one gate circuit and an output terminal of the other, for holding the predetermined data, said reset signal (62) being supplied to a second input terminal of the first gate circuit (60), and said holding data being supplied to a second input terminal (n48) of the second gate circuit (58), according to said latch signal (52) which is generated in response to an initialization signal supplied from outside at an initialization after the power ON. The semiconductor integrated circuit according to claim 1, further comprising a memory cell array (10) and a redundant memory cell array (12); the redundant address corresponding to a defective cell in the memory cell array; a redundancy decision circuit (50) for comparing the holding data of the data holding circuit (48) with a supplied address; and a driver circuit (14) for the memory cell array and a driver circuit (16) for the redundant memory cell array that are actuated in accordance with the result of the decision by the redundancy decision circuit (50) . The semiconductor integrated circuit according to claim 2, wherein the initialization signal supplied from outside at the initialization is a mode register set command.

Inventors: KOJIMA KAZUMI, UCHIDA TOSHIYA, KOJIMA, KAZUMI, UCHIDA, TOSHIYA, Kojima, Kazumi, c/o Fujitsu VLSI Ltd.
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1997
Main classification: G06F11
IPC codes: G11C29, G11C11