Flip-Chip layout input apparatus and method

Abstract: A layout input apparatus of the present invention includes: an input section for inputting first coordinate information representing a position of a first circuit portion included in a first semiconductor integrated circuit and second coordinate information representing a position of a second circuit portion included in a second semiconductor integrated circuit. The layout input apparatus further includes a control section for performing a predetermined coordinate transformation with respect to the second coordinate information; and a storage section for storing the first coordinate information as at least a part of first layout data representing a layout of the first semiconductor integrated circuit and storing the transformed second coordinate information as at least a part of second layout data representing a layout of the second semiconductor integrated circuit.

Description: BACKGROUND OF THE INVENTION 1. FIELD OF THE INVENTION: The present invention relates to a layout input apparatus and a layout input method. 2. DESCRIPTION OF THE RELATED ART: In recent years, the degree of integration of semiconductor integrated circuits is increasing, and their operation speed is becoming higher. Under this circumstance, various large-scale systems are being realized by a semiconductor integrated circuit formed on a single chip, which greatly contributes to the miniaturization and decrease in cost of such systems. However, in order to produce a semiconductor integrated circuit whose minimum size is reduced to a quarter micron or less, significant capital investment is required. Furthermore, it is becoming difficult to enhance production yield with the increase in chip area and high integration of a semiconductor integrated circuit. Therefore, it may cost lower to realize a large-scale system by combining a plurality of relatively large semiconductor integrated circuits produced by a conventional process than to realize a large-scale system on a single chip. A mounting technique as shown in Figures 34A through 34D has been proposed for the purpose of reducing the production cost and mounting area of a semiconductor integrated circuit. According to this mounting technique, a semiconductor chip with a first LSI formed thereon (first LSI chip) and a semiconductor chip with a second LSI formed thereon (second LSI chip), as shown in Figure 34A, are mounted in a single package in such a manner that they are superposed on top of the other. For example, a semiconductor integrated circuit chip with a central processing unit (CPU) formed thereon is used as the first LSI chip, and a semiconductor integrated circuit chip with a static RAM (SRAM) is used as the second LSI chip. Conventional semiconductor integrated circuits are composed of a number of semiconductor devices formed on one principal surface of a semiconductor substrata (semiconductor chip) and wirings connecting the devices to each other. According to the Flip & Stack mounting technique, two semiconductor chips are placed in such a manner that their surfaces on which semiconductor integrated circuits are formed face each other, as shown in Figures 34B through 34D. Terminal pins (not shown) of a package are electrically connected through bonding wires to a bonding pad provided on the periphery of the first LSI chip. Input/output (I/O) terminals of the second LSI chip are connected to I/O terminals for Flip & Stack mounting provided on the first LSI chip. Such a connection requires the first LSI chip and the second LSI chip to be provided with electrical connecting portions which have a "mirror inversion" relationship, as shown in Figures 34A. As described above, according to the conventional Flip & Stack mounting technique, two semiconductor integrated circuits which are different in function and use, such as a CPU and an SRAM, are used as the first and second LSIs. The layouts of these two semiconductor integrated circuits are independently designed by a conventional layout input method, after the coordinates of the connecting portions which have a mirror inversion relationship are defined. However, the conventional layout input method does not allow the layouts of two LSIs to be designed simultaneously. This makes it difficult to determine optimum layouts, resulting in an increase in the time required for designing layouts. In addition, the layout verification is required to be conducted independently with respect to two LSIs. Therefore, the number of steps of forming net lists for an individual LSI increases. Furthermore, the connection between two LSIs is manually checked, which increases verification time and decreases reliability. Simultaneous design of flip mounted integrated circuits is known from EP 0 417 345 A1. A plurality of integrated circuits are mounted on chips, the chips being mounted on a carrier side by side. The complete electrical circuitry is looked at and considered synoptically. Dividing, partitioning and placing of the circuitry is done in a top-down methotology in which each chip of the plurality of chips and the package, that means the chips arranged on the carrier, are optimized as a whole. The chips are arranged on the carrier in such a way that between the chips on the carrier the shortest connection lines are possible and also in such a way that the overal length needed for all connection lines is as short as possible. The single chips are designed from the outside to the inner part of the chip. After the input/output assignment in the input/output port areas of the chips starting from there to the inner of the chip the design is performed. The electric circuits within a chip are arranged in considering the input/output pads and necessities that are provided in the circumferential areas of said specific chip. It is the object of the invention to provide a method for optimized design of two or more large scale integrated circuits which are flip and stack mounted. A layout input method for the simultaneous design of flip and stack integrated circuits according to the invention is set out in claim 8. A layout input apparatus for the simultaneous design of flip and stack integrated circuits according to the invention is claimed in claim 1. Preferred embodiments of the invention are described by the dependent claims. In a preferred embodiment, the position of the connecting portion, the first position, and the second position are represented by an identical coordinate. Because of the above-mentioned structure, the layouts of two LSIs can be designed while the layouts are being displayed so as to be superposed on top of the other on an identical screen. Therefore, information as to alterations in the layout of either LSI can be immediately reflected on the other, which makes it easy to optimize the layouts and shortens design time. Furthermore, according to the above-mentioned method, the layouts of two LSIs are simultaneously read and their connection is previously recognized. Therefore, the layouts can be logically verified only based on a net list of the combination of two LSIs. This can reduce the number of steps of forming net lists and prevent mistakes caused by a manual check of connecting portions. Thus, the invention described herein makes possible the advantages of providing a layout input apparatus and a layout input method capable of simultaneously laying out a plurality of LSIs. These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1A shows layout images at a time of input of layouts; and Figure 1B shows layout images at a time of completion of LSIs. Figure 2A shows a structure of a single semiconductor integrated circuit including a plurality of logical blocks; and Figure 2B shows a structure of two semiconductor integrated circuit portions in the case where a plurality of logical blocks are classified into two groups. Figure 3 is a flow chart of an entire process for designing a semiconductor integrated circuit including the step of dividing the circuit. Figure 4 is a flow chart showing an example of a method for dividing a semiconductor integrated circuit. Figure 5 is a block diagram showing a structure of a layout input apparatus of Embodiment 1 according to the present invention. Figure 6 is a perspective view showing the relationship between the layout data and the mask elements. Figure 7 is a flow chart showing a procedure for forming layout data 503 through 505 . Figure 8A is a perspective view of a screen of a display device 3; and Figure 8B is a top plan view of the screen the display device 3 . Figure 9 shows a structure of coordinate information 603 through 605 stored in a ROM 5 . Figure 10 is a flow chart showing detailed steps of inputting a layout. Figure 11 shows layouts at each level. Figure 12 shows a structure of the layout data 503 through 505 stored in a data storing section 7 . Figure 13 shows the changes in layout graphic by coordinate transformations. Figure 14 shows a display screen (superposed display screen) of the layout input apparatus of Embodiment 1 according to the present invention. Figure 15 is a block diagram showing a structure of a layout input apparatus of Embodiment 2 according to the present invention. Figure 16 is a flow chart showing a procedure for forming layout data 802 through 804 . Figure 17 shows an example of the relationship between the coordinate plane of the second layout data and the coordinate plane of the first layout data. Figure 18 shows another example of the relationship between the coordinate plane of the second layout data and the coordinate plane of the first layout data. Figure 19 shows still another example of the relationship between the coordinate plane of the second layout data and the coordinate plane of the first layout data. Figure 33 is a flow chart showing an operation procedure of the layout verification apparatus in the case of conducting a DRC. Figure 34A is a plan view showing connecting portions of two LSI chips for Flip & Stack mounting; Figure 34B is a cross-sectional view showing the state two LSI chips are mounted; Figure 34C is a plan view showing the state in which two LSI chips are mounted; and Figure 34D is a perspective view showing the state in which two LSI chips are mounted. DESCRIPTION OF THE PREFERRED EMBODIMENTS The layout input apparatus and the layout input method according to the present invention provides for simultaneously laying out a plurality of LSIs. Such a layout input apparatus and a layout input method are particularly suitable for designing the layout of a semiconductor chip used for Flip & Stack mounting. Figure 1A schematically shows two LSI chips mounted by Flip & Stack mounting. Figure lB schematically shows the layouts of two LSI chips before Flip & Stack mounting. As shown in Figure 1A, in order to electrically connect the two LSI chips, the connecting portions of these chips are positioned so as to face each other during mounting, whereas the connecting portions in the layout graphics of semiconductor integrated circuits formed on the respective chips are shifted from each other, as shown in Figure 1B . The layout input apparatus of the present invention displays, through the second LSI chip, two semiconductor integrated circuit portions respectively formed on two LSI chips mounted by Flip & Stack mounting, which are superposed on top of the other, as shown in Figure 1A . Because of this, the position of the connecting portions of the two LSI chips is clearly displayed in the two superposed layout graphics. This results in substantial reduction of time required for the layout design. In addition, the information of alterations in one layout can be reflected on the other layout, so that the layouts of the two superposed LSIs can be easily optimized and design time shortens. A plurality of semiconductor integrated circuits used for Flip & Stack mounting can be obtained, for example, by dividing a single semiconductor integrated circuit including a plurality of logical blocks into a plurality of semiconductor integrated circuit portions in the course of designing layouts. For example, in the case where a single semiconductor integrated circuit includes a plurality of logical blocks, the division of the semiconductor integrated circuit can be realized by extracting parameters representing the characteristics of each of a plurality of logical blocks and classifying a plurality of logical blocks into a plurality of groups in accordance with the parameters. The logical blocks belonging to the identical group are assigned to the identical semiconductor integrated circuit portion. Figure 2A schematically shows one semiconductor integrated circuit LSI 0 including a plurality of logical blocks ( BLC A , BLC B , BLC C and BLC D ). Here, the operation speed of the logical blocks ( BLC A and BLC B ) is 25 MHz, and that of the logical blocks ( BLC C and BLC D ) is 50 MHz. A plurality of logical blocks ( BLC A , BLC B , BLC C and BLC D ), respectively, have differing characteristics as well as common characteristics. For example, the logical blocks ( BLC B and BLC D ) may be composed of digital circuits, and the other logical blocks ( BLC A and BLC C ) may be composed of analog circuits. In this case, the logical blocks can be classified into a first group (logical blocks BLC A and BLC C ) and a second group (logical blocks BLC B and BLC D ), based on the parameter representing whether the logical block is composed of a digital circuit or an analog circuit. Accordingly, the classification of the groups varies depending upon the parameter representing the characteristic of interest. Figure 2B schematically shows the case where 4 logical blocks ( BLC A , BLC B , BLC C and BLC D ) are classified into two groups based on the operation speed, and two groups are assigned to two semiconductor chips. More specifically, the logical blocks ( BLC A and BLC B ) are assigned to a first semiconductor integrated circuit portion LSI 1 , and the logical blocks ( BLC C and BLC D ) are assigned to a second semiconductor integrated circuit portion LSI 2 . These two semiconductor integrated circuit portions are formed respectively on different semiconductor chips by a known semiconductor production process. Thereafter, a plurality of semiconductor chips are mounted in one package by a multi-chip mounting technique and electrically connected to each other. Thus, a plurality of semiconductor chips are integrated as one semiconductor device. As described above, a plurality of semiconductor integrated circuit chips suitable for multi-chip mounting can be produced efficiently by dividing a single semiconductor integrated circuit into a plurality of semiconductor integrated circuit portions in the course of designing layouts. Each of a plurality of semiconductor integrated circuit portions thus obtained has logical blocks classified based on the characteristic parameter as constituent elements. Therefore, a layout which excludes a useless space as a whole and is suitable for the improvement of operation speed can be obtained. For example, in the case where a semiconductor integrated circuit portion designed by a 0.5 µm rule is formed on one of a pair of semiconductor chips for the multi-chip mounting and a semiconductor integrated circuit portion designed by a 1.0 µm rule is formed on the other chip, a semiconductor chip with a semiconductor integrated circuit portion designed by a mild design rule can be produced at low cost with relatively high yield. Therefore, a package price for the semiconductor integrated circuit as a whole can be reduced. Furthermore, in the case where semiconductor integrated circuit portions which operate at different clock frequencies are formed on a plurality of semiconductor chips for the multi-chip mounting, each semiconductor integrated circuit portion operates at a required clock frequency without wasting electric power so that power consumption can be reduced as a whole. Next, referring to Figure 3, a design flow of a semiconductor integrated circuit including a division step of the circuit will be schematically described. First, as shown in Figure 3, each group is defined based on the parameter of blocks included in the group. The hierarchy in accordance with each group is generated on a net list, whereby one semiconductor integrated circuit is divided into at least two semiconductor integrated circuit portions. Then, the layouts of the divided semiconductor integrated circuit portions are input, and the layout rule verification is conducted with respect to each semiconductor integrated circuit portion. Thereafter, the layout logic verification is conducted between the laid out semiconductor integrated circuit and the net list. After the layout design is thus completed, mask data is formed by a known method. A plurality of masks (photomasks) are produced based on the mask data. The semiconductor production process is conducted using a plurality of masks thus produced, whereby the divided semiconductor integrated circuit portions can be respectively produced on separate semiconductor chips. As described above, one semiconductor integrated circuit is not divided into a plurality of functional blocks to be arranged on one semiconductor chip. Instead of this, one semiconductor integrated circuit is divided into a plurality of semiconductor integrated circuit portions to be assigned to at least two semiconductor chips. Next, referring to Figure 4, an exemplary method for dividing a semiconductor integrated circuit will be described in more detail. In STEP 1, the net list and the parameters of the respective blocks included in a semiconductor integrated circuit are read, and the parameters of the respective blocks are checked. At this time, the hierarchy of the net list has a structure in which blocks A, B, C and D are arranged in parallel with each other under the semiconductor integrated circuit LSI 0 (see the lower central portion of Figure 4). The parameters of the respective blocks are classified into those representing logic characteristics, operation frequency characteristics, process characteristics, etc. The logic characteristics include the type of a logic element, a ROM, a RAM, an arithmetic unit, an analog element, etc. The operation frequency characteristics include the level of frequencies such as 25 MHz and 50 MHz. The process characteristics include the type of process for a CMOS, a DRAM, a bipolar element, a bi-CMOS, etc. Other characteristics include whether or not it is a memory core or a peripheral circuit, a design rule, a threshold of a transistor, etc. In STEP 2, logical blocks are classified into groups based on the characteristics specified from the above-mentioned parameters. In this example, it is assumed that the logical blocks are classified into groups based on the operation frequency characteristics. The operation frequency of the logical blocks ( BLC A and BLC B ) is 25 MHz, and the operation frequency of the logical blocks ( BLC C and BLC D ) is 50 MHz. In this case, the logical blocks are classified into Group 1 (LSI 1: operation frequency 25 MHz) = logical blocks BLC A and BLC B and Group 2 (LSI 2: operation frequency 50 MHz) = logical blocks BLC C and BLC D . The hierarchy in accordance with these groups is added to the net list. In the case of this example, the hierarchy of the net list has a structure in which semiconductor integrated circuit portions LSI 1 and LSI 2 are arranged under the semiconductor integrated circuit LSI 0 , as shown in the lower right portion of Figure 4. As described above, one semiconductor integrated circuit LSI 0 can be divided into two semiconductor integrated circuit portions LSI 1 and LSI 2 . Thereafter, a layout of each semiconductor integrated circuit portion is input for designing the layout. Such a layout input requires the connecting portions which connect two semiconductor integrated circuit portions to each other to be appropriately positioned. Thus, in the case of the present invention, a layout which is different from that in the case of arranging a plurality of functional blocks classified into groups on the identical semiconductor chip is required to be designed with respect to the respective semiconductor integrated circuit portions thus divided. Hereinafter, the semiconductor integrated circuit portions LSI 1 and LSI 2 will be referred to as a "first LSI" and a "second LSI", respectively. It should be noted that the "first LSI" and the "second LSI" are not limited to those obtained by dividing a single semiconductor integrated circuit into a plurality of semiconductor integrated circuit portions. The layout input apparatus and the layout input method according to the present invention can be applied to any of a plurality of semiconductor integrated circuit portions having layout data related to each other. Hereinafter, the present invention will be described by way of illustrative embodiments. Embodiment 1 Referring to Figures 5 through 14, a layout input apparatus and a layout input method of Embodiment 1 according to the present invention will be described. As shown in Figure 5 , a layout input apparatus includes an input device 4 through which a layout designer or the like inputs a layout and a display device 3 which is capable of displaying a two-dimensional input layer or the like of layout data for the layout designer. The input device 4 includes a keyboard, a mouse, and the like, and the display device 3 includes a CRT, a flat panel display, and the like. The display device 3 and the input device 4 are connected to a CPU 1 through an I/O interface 2 . The CPU 1 is connected to a RAM 5 and a ROM 6 storing a graphic input program 501 , a coordinate transformation program 502 , etc. A data storing section 7 stores layout data 503 of the first LSI, layout data 504 of the second LSI, and layout data (connection information) 505 representing connecting portions between the first LSI and the second LSI. Each of the layout data 503 of the first LSI and the layout data 504 of the second LSI is composed of a plurality of two-dimensional input layers. The two-dimensional input layers include data corresponding to the pattern of each mask used in a process for producing a semiconductor integrated circuit. The layout data will be described with reference to Figure 6. The layout data of the semiconductor integrated circuit is composed of a plurality of mask elements (a mask used for the production process, i.e., during a lithography step is based on the mask elements). The shape and arrangement of transistors, wirings, wiring contacts, etc. included in the semiconductor integrated circuit are defined by superposing one mask element on another. Next, a procedure for forming the layout data 503 through 505 will be described with reference to Figure 7 . First, in STEP 1, the CPU 1 reserves a space area required for storing the layout data 503 through 505 in the data storing section 7 so as to form a database. The reservation of such a space area is executed in response to the "layout start" command input by, for example, a layout designer through the input device 4 . Next, in STEP 2, the layout designer inputs layouts of the first LSI and the second LSI. The coordinate system used in the case of inputting the layout of the first LSI is identical with that used in the case of inputting the layout of the second LSI. The coordinate input through the input device 4 is displayed on the display device 3 without being transformed. This enables the layouts of the first and second LSIs to be designed while the layouts of the first and second LSIs are being displayed so as to be superposed on each other on the identical screen. In STEP 2, the layout of the connecting portions connecting the first LSI to the second LSI is input. The remaining STEP 3 through STEP 7 are discussed in greater detail below. Figures 8A and 8B are exemplary screens of the display device 3 in which each coordinate showing the positions of circuit portions 6031-1 , 6031-2 , 6032-1 , 6033-1 through 6033-3 included in the first LSI, each coordinate showing the positions of circuit portions 6041-1 , 6041-2 , 6042-1 , 6043-1 through 6043-3 included in the second LSI, and the coordinate showing the position of a connecting portion 6051-1 are input. In the case where a circuit portion is a square, for example, the coordinate on the upper left end of the square and the lower right end of the square are input. In Figures 8A and 8B , solid lines represent the circuit portions related to the first LSI, broken lines represent the circuit portions related to the second LSI, and boldface lines represent the connecting portion. Usually, coordinate axes (X-axis and Y-axis) are not displayed on the screen of the display device 3 ; however, in Figures 8A and 8B , an X-axis and a Y-axis are displayed in order to emphasize the use of an input coordinate system common to the first and second LSIs. The information of the coordinate input through the input device 4 is stored in the RAM 5 without being transformed. Such an input of the information of the coordinate can be achieved, for example, by using the graphic input program 501 stored in the ROM 6 . Figure 9 shows an example of coordinate information 603 through 605 stored in the RAM 5 as a result of the input of the layouts of the first and second LSIs. In this example, the coordinate information 603 of the first LSI and the coordinate information 604 of the second LSI, respectively, have a three-layered structure, and are correlated with each other through a connecting layer 6051 of the coordinate information 605 . The coordinate information 603 includes coordinate information of the circuit portions 6031-1 and 6031-2 laid out on a layer 6031 , coordinate information of the circuit portions 6032-1 laid out on a layer 6032 , and coordinate information of the circuit portions 6033-1 through 6033-3 laid out on a layer 6033 . The coordinate information 604 includes coordinate information of the circuit portions 6041-1 and 6041-2 laid out on a layer 6041 , coordinate information of the circuit portions 6042-1 laid out on a layer 6042, and coordinate information of the circuit portions 6043-1 through 6043-3 laid out on a layer 6043 . In order to lay out a specified circuit portion on a specified layer included in the first and second LSIs, the information identifying the first LSI and the second LSI and the information representing the specified layer should be input in addition to the coordinate information specifying the position of the specified circuit portion. Such an input can be usually executed by selecting a menu displayed on the display device 3. In Embodiment 1, the coordinate system of the coordinate information 603 and the coordinate system of the coordinate information 604 stored in the RAM 5 are identical. These coordinate systems are also identical with the above-mentioned input coordinate system. This means that the coordinate information input through the input device 4 is stored in the RAM 5 without being transformed. Next, STEP 2 will be described in detail with reference to Figure 10. First, in SUB_STEP1, the layout designer lays out a component called a cell realizing a simple logic such as an inverter, NAND, and NOR. In SUB_STEP2, the layout designer conducts arrangement and wiring of the cell in accordance with a logic of a block level net list. In SUB_STEP3, the layout designer conducts arrangement and wiring of a block layout in accordance with a top level net list. In each of the above steps, the layout designer optimizes the layout while performing temporary arrangement, wiring estimation, etc. In the present embodiment, the layout designer performs rough arrangement of the connecting portions of the first and second LSIs, and then, proceeds to SUB_STEP3. If there is any inconvenience in SUB_STEP3, SUB_STEP2 is performed again. The relationship between the layouts formed in each step in Figure 10 is shown in Figure 11. Returning now to Figure 7, after finishing STEP 2, the layout designer proceeds to STEP 3. In STEP 3, the layout designer confirms the inconvenience or the like caused by the connection, and returns to STEP 2, if correction is required, so as to optimize the layout. If there is no problem, the layout designer proceeds to STEP 4. In STEP 4, the CPU 1 judges whether or not the coordinate transformation is conducted with respect to the coordinate information stored in the RAM 5. Such a judgement is executed in response to the "layout end/layout data save" command input through the input device 4 , for example, by the layout designer. In the case where the coordinate transformation is judged to be required in STEP 4, the layout designer proceeds to STEP 5 . Otherwise, the layout designer proceeds to STEP 7 . In STEP 5 , Y-axis symmetrical transformation is performed with respect to the coordinate information. Thereafter, in STEP 6 , the origin movement transformation is further performed with respect to the result obtained by performing the Y-axis symmetrical transformation of the coordinate information. In STEP 7, the CPU 1 outputs the layout data 503 through 505 formed in accordance with the above procedure to the data storing section 7 . For example, in the case of forming the layout data 503 through 505 of the first and second LSIs used for Flip & Stack mounting, the CPU 1 stores the coordinate information 603 of the first LSI in the data storing section 7 as at least a part of the layout data 503 without performing the coordinate transformation with respect to the coordinate information 603 , performs the coordinate transformation with respect to the coordinate information 604 of the second LSI, and stores the result obtained by performing the coordinate transformation with respect to the coordinate information 604 in the data storing section 7 as at least a part of the layout data 504 . In this manner, the coordinate transformation with respect to the coordinate information 604 is executed after the coordinate information 604 is read from the RAM 5 and before the coordinate information 604 is stored in the data storing section 7 . In the case of multi-chip mounting other than Flip & Stack mounting, the above-mentioned coordinate transformation is not required. Figure 12 shows an example of the layout data 503 through 505 stored in the data storing section 7 . The layout data 503 and 505 shown in Figure 12 are identical with the coordinate information 603 and 605 shown in Figure 9 . The layout data 504 in Figure 12 is equal to the result obtained by performing the Y-axis symmetrical transformation and the origin movement transformation with respect to the coordinate information 604 in Figure 9 . Next, the Y-axis symmetrical transformation and the origin movement transformation will be described in detail. The pattern of the mask elements defining transistors, wirings, wiring contacts, and the like is usually represented by the combination of squares provided on a coordinate plane as shown in Figure 6 . The square on the coordinate plane is represented by coordinates of two vertices of a diagonal line of the square. In the case where these vertices are, for example, (10, 10) and (20, 20), the coordinate after the Y-axis symmetrical transformation is given by (-10, 10) and (-20, 20). In the case where an X component of an external shape of the second LSI is 1000, the origin movement transformation is performed by adding (1000, 0) to the coordinate of two vertices of the square. As a result of these coordinate transformations, two vertices of the square are represented by (990, 10) and (980, 20). The layout data 504 is obtained by performing the above-mentioned coordinate transformations with respect to each circuit potion of each layer included in the coordinate information 604 . Figure 13 schematically shows how the layout graphic (original graphic) of the second LSI is changed by the coordinate transformations. The original graphic shown in Figure 13 corresponds to the layout graphic obtained by seeing the semiconductor integrated circuit portion formed under the second LSI chip through the second LSI chip in the state shown in Figure 1A . In contrast, the graphic after the coordinate transformations corresponds to the layout graphic obtained by directly seeing the semiconductor integrated circuit portion formed on the second LSI chip in the arrangement shown in Figure 1B from above. Mask data is produced by using the graphic after the coordinate transformations. Figure 14 shows each layout of the first and second LSIs and a layout obtained by superposing these layouts on top of the other (perspective view). More specifically, the left side of Figure 14 shows top views of semiconductor integrated circuit portions formed on the principal planes of two semiconductor chips; the right side of Figure 14 shows a top view of a state in which the second semiconductor chip (LSI 2) is superposed on the first semiconductor chip (LSI 1) in such a manner that the respective principal planes face each other. This corresponds to Flip & Stack mounting, and the layout of the second semiconductor chip seen through a substrate is shown so as to be superposed on the layout of the first semiconductor chip. In the apparatus shown in Figure 5 , after a graphic input layer is specified, the coordinate information representing the shape and position of the graphic to be input is input through the input device 4 . Most of the graphics to be input are squares. In the case where the graphic to be input is a square, the coordinate information thereof can be the coordinate of two vertices of a diagonal line of the square. The input coordinate information is stored in the RAM 5 in accordance with the graphic input program 501 . The CPU 1 displays the coordinate information stored in the RAM 5 on the display device 3 without transforming it. Thus, the layouts of the first and second LSIs are displayed as shown on the right side of Figure 14. After the coordinate information is input, the CPU 1 selectively transforms the coordinate information stored in the RAM 5 by using the coordinate transformation program 502 . The result of the transformation is stored in the data storing section 7 as layout data. According to the present embodiment, a layout can be input while the layout graphic as shown on the right side of Figure 14 is being displayed by the display device 3 . As a result, the layouts of two LSIs for Flip & Stack mounting can be simultaneously designed, so that the mutual influence on the layouts due to the changes in arrangement of the connecting portions of two LSIs can be grasped at a glance and steps can be taken immediately. This enables the design period to be shortened and layouts to be optimized (i.e., highly integrated). Embodiment 2 Referring to Figures 15 through 19 , a layout input apparatus and a layout input method of Embodiment 2 according to the present invention will be described. As shown in Figure 15 , a layout input apparatus includes an input device 4 through which a layout designer or the like inputs a layout and a display device 3 which is capable of displaying a two-dimensional input layer or the like of layout data for the layout designer. The input device 4 includes a keyboard, a mouse, and the like, and the display device 3 includes a CRT, a flat panel display, and the like. The display device 3 and the input device 4 are connected to a CPU 1 through an I/O interface 2 . The CPU 1 is connected to a RAM 5 and a ROM 6 storing a graphic input program 801 , etc. A data storing section 7 stores layout data 802 of the first LSI, layout data 803 of the second LSI, and layout data 804 representing connecting portions between the first LSI and the second LSI. Each of the layout data 802 of the first LSI and the layout data 803 of the second LSI is composed of a plurality of two-dimensional input layers. The two-dimensional input layers include data corresponding to the pattern of each mask used in a process for producing a semiconductor integrated circuit. Next, a procedure for forming the layout data 802 through 804 will be described with reference to Figure 16 . First, in STEP 1, the CPU 1 reserves a space area required for storing the layout data 802 through 804 in the data storing section 7 so as to form a database. The reservation of such a space area is executed in response to the "layout start" command input by, for example, a layout designer through the input device 4 . Next, in STEP 2 , the layout designer inputs layouts of the first LSI and the second LSI. In the same way as in Embodiment 1, the coordinate system used in the case of inputting the layout of the first LSI is identical with that used in the case of inputting the layout of the second LSI. The coordinate input through the input device 4 is displayed on the display device 3 without being transformed. This enables the layouts of the first and second LSIs to be designed while the layouts of the first and second LSIs are being displayed so as to be superposed on each other on the identical screen. In STEP 2 , the layout of the connecting portions connecting the first LSI to the second LSI is input. The coordinate information input through the input device 4 is stored in the RAM 5 in accordance with the graphic input program 801 stored in the ROM 6 . In the case where the coordinate information input through the input device 4 is that of the second LSI, the graphic input program 801 performs the coordinate transformation with respect to the coordinate information of the second LSI in response to the input of the coordinate information of the second LSI, and stores the result obtained by performing the coordinate transformation with respect to the coordinate information of the second LSI in the RAM 5 . In the case where the coordinate information input through the input device 4 is that of the first LSI, the graphic input program 801 stores the coordinate information of the first LSI in the RAM 5 without performing the coordinate transformation with respect to it. The coordinate information of the first and second LSIs thus stored in the RAM 5 has the same structure as that of the layout data 503 through 505 shown in Figure 12 . Therefore, unlike Embodiment 1, it is not required to perform the coordinate transformation with respect to the coordinate information of the second LSI at a time when the coordinate information of the second LSI stored in the RAM 5 is output to the data storing section 7 . The CPU 1 performs the coordinate transformation with respect to the coordinate information of the second LSI stored in the RAM 5 , and then, displays the layout graphic on the display device 3 based on the transformed coordinate information. Because of this, the layout of the second LSI is displayed on the display device 3 in such a manner than it is seen through the reverse surface of a chip as shown on the right side of Figure 14 . The processings in STEP 3 and STEP 4 shown in Figure 16 are identical with those of STEP 3 and STEP 7 shown in Figure 7 . Therefore, the description thereof will be omitted here. In Embodiment 2, the layout data 802 through 804 stored in the data storing section 7 have the same structures as those of the layout data 503 through 505 shown in Figure 12 . More specifically, as shown in Figure 17 , the sign (plus or minus) of an X-axis on the coordinate plane of the layout data 803 for the second LSI is opposite to that of an X-axis on the coordinate plane of the layout data 802 for the first LSI. Furthermore, the origin on the coordinate plane of the layout data 803 for the second LSI is shifted from the origin on the coordinate plane of the layout data 802 for the first LSI by a predetermined offset ( X off ) along the X-axis direction of the layout data 802 for the first LSI. Therefore, the connecting portions between the first LSI and the second LSI should be input in the course of the layout design, in such a manner that the connecting portions in the layout graphics displayed on the display device 3 are superposed on each other, As shown in Figure 18, the origin on the coordinate plane of the layout data 803 for the second LSI may be shifted from the origin on the coordinate plane of the layout data 802 for the first LSI by a predetermined offset ( X off ) along the X-axis direction and by a predetermined offset ( Y off ) along the Y-axis direction of the layout data 802 for the first LSI. Furthermore, as shown in Figure 19, the origin on the coordinate plane of the layout data 803 for the second LSI may be matched with the origin of the layout data 802 for the first LSI. The layout input apparatus and the layout input method according to the present invention allows the layouts of a plurality of LSIs to be simultaneously input in the course of the layout design. Therefore, the mutual influence on the layouts due to the changes in arrangement of the connecting portions of two LSIs can be grasped at a glance and steps can be taken immediately. This enables the design period to be shortened and layouts to be optimized (i.e., highly integrated).

Claims: A layout input apparatus for the simultaneous design of flip and stack integrated circuits, comprising: a) an input section (4) for inputting first coordinate information (603) representing a position of a first circuit portion included in a first semiconductor integrated circuit (LSI 1) and second coordinate information (604) representing a position of a second circuit portion included in a second semiconductor integrated circuit (LSI 2), wherein b) the first semiconductor integrated circuit (LSI 1) having a connecting portion is formed on a first surface of a first semiconductor chip, c) the second semiconductor integrated circuit (LSI 2) having a connecting portion is formed on a second surface of a second semiconductor chip, and wherein d) the first semiconductor chip and the second semiconductor chip are mounted so as to overlap in such a manner that the connecting portion on the first surface and the connecting portion on the second surface face each other, characterized in that the apparatus further comprises: e) a display device (3) for displaying the first circuit portion according to the first coordinate information (603) and the second circuit portion according to the second coordinate information (604); f) a control section (1, 5, 6) for performing a predetermined coordinate transformation on the second coordinate information (604), said transformation including a symmetrical transformation with respect to a predetermined axis and a parallel movement along a predetermined direction; and g) a storage section (7) for storing the first coordinate information (603) as at least a part of first layout data (503; 802) representing a layout of the first semiconductor integrated circuit (LSI 1) and storing the transformed second coordinate information (604) as at least a part of second layout data (504; 803) representing a layout of the second semiconductor integrated circuit (LSI 2), wherein h) the second semiconductor integrated circuit (LSI 2) is formed on the second semiconductor chip according to the transformed second coordinate information (604). A layout input apparatus for the simultaneous design of flip and stack integrated circuits according to claim 1, wherein the control section (1, 5, 6) performs the predetermined coordinate transformation when the second coordinate information is stored in the storage section. A layout input apparatus for the simultaneous design of flip and stack integrated circuits according to claim 1, wherein the control section (1, 5, 6) performs the predetermined coordinate transformation in response to the input of the second coordinate information. A layout input apparatus for the simultaneous design of flip and stack integrated circuits according to claim 1, wherein a first coordinate system for the first layout data is different from a second coordinate system for the second layout data. A layout input apparatus for the simultaneous design of flip and stack integrated circuits according to claim 4, wherein each of the first coordinate system and the second coordinate system has an X-axis and a Y-axis, and an origin in the first coordinate system is shifted from an origin in the second coordinate system by a predetermined X-offset in a direction of the X-axis and by a predetermined Y-offset in a direction of the Y-axis. A layout input apparatus for the simultaneous design of flip and stack integrated circuits according to claim 5, wherein the predetermined Y-offset is 0. A layout input apparatus for the simultaneous design of flip and stack integrated circuits according to claim 5, wherein the predetermined X-offset is 0 and the predetermined Y-offset is 0. A layout input method for the simultaneous design of flip and stack integrated circuits, comprising the steps of: a) inputting first coordinate information (603) representing a position of a first circuit portion included in a first semiconductor integrated circuit (LSI 1) and second coordinate information (604) representing a position of a second circuit portion included in a second semiconductor integrated circuit (LSI 2), wherein b) the first semiconductor integrated circuit (LSI 1) having a connecting portion is formed on a first surface of a first semiconductor chip, c) the second semiconductor integrated circuit (LSI 2) having a connecting portion is formed on a second surface of a second semiconductor chip, and wherein d) the first semiconductor chip and the second semiconductor chip are mounted so as to overlap in such a manner that the connecting portion on the first surface and the connecting portion on the second surface face each other, characterized by the further steps of: e) displaying the first circuit portion according to the first coordinate information (603) and the second circuit portion according to the second coordinate information (604); f) performing a predetermined coordinate transformation on the second coordinate information (604), said transformation including a symmetrical transformation with respect to a predetermined axis and a parallel movement along a predetermined direction; g) storing the first coordinate information (603) as at least a part of first layout data (503; 802) representing a layout of the first semiconductor integrated circuit (LSI 1) and storing the transformed second coordinate information (604) as at least a part of second layout data (504; 803) representing a layout of the second semiconductor integrated circuit (LSI 2); and h) forming the second semiconductor integrated circuit (LSI 2) on the second semiconductor chip according to the transformed second coordinate information (604).

Inventors: SEGAWA REIJI, SEGAWA, REIJI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1997
Main classification: G06F17
IPC codes: H01L25, G06F17