Circuit architecture for processing multichannel frames of synchronous digital signals with a broadband, particularly for a SONET/SDH standard

Abstract: The invention relates to a circuit architecture for processing multi-channel frames of broadband synchronous digital signals, in particular signals of the SONET/SDH standard, being of a type which comprises an input portion (3) and an output portion (4). It is characterized by being constructed of at least one modular component (2) adapted to process frames comprising a single channel and connectable modularly to N further identical components corresponding to the number of frame channels.

Description: Field of the Invention This invention relates to a circuit architecture for processing multi-channel frames of broadband synchronous digital signals, in particular signals of the SONET/SDH standard, being of a type which comprises a receiving input portion and a transmitting output portion. Background Art It is a universally recognized fact that the foreseeable future of planetary communications rests on broadband video signals. Accordingly, an expanded application of such facilities as video telephone, video conference, video surveillance, color facsimile transmission, and cable television (CATV), calls for integrated circuit architectures which can handle broadband electric signals. Moreover, the ever more widespread availability of communication and interconnection lines based on fiber optics is demanding integrated electronic circuits of suitable design and construction to handle broadband signals in an effective and efficient manner. In this particular field, it has been possible to establish certain transmission standards, such as the standards known by the acronyms SONET (Synchronous Optical Network) or SDH (Synchronous Digital Hierarchy). These standards are set and controlled by CCITT, a US committee regulating synchronous transmissions based on optical communication. These standards are useful to settle and organize the transmission protocols that enable information to be transmitted on communications networks, meaning by this term the complex systems which interconnect communication components. In particular, the standards considered in this specification expressly relate to the synchronous digital transmission and reception of digital signal frames. An exhaustive review of these problems is found in a text, Broadband Telecommunication Technology, Artech House, 1993, Chapter 3: "Synchronous Digital Transmission". To better appreciate the aspects of the present invention, notice should be taken of that state-of-art frame processing involves: A) On reception (RX): 1) signal pre-processing; 2) optional demultiplexing, i.e. a frame decomposition for extracting certain subchannels; 3) parallel processing of the individual channels forming the frame, but in such a way as to have each channel processed separately from the others; B) On transmission (TX): 1) preparing in parallel the individual channels forming the frame; 2) multiplexing the various channels, if more than one are provided; 3) final processing of the whole frame. Illustrated in block diagram form by the accompanying Figure 1A is the structure of a conventional circuit architecture for processing a frame comprising a single channel. In this particular case, the multiplexing or demultiplexing steps obviously would not be required. On the other hand, Figure 1B shows, again in block diagram form, the structure of a conventional circuit architecture for processing a frame comprising N channels, with N=3 or N=4. A further prior solution to the problem of processing multi-channel frames was made available to the general public in 1993 by TransSwitch Corporation, Shelton CT, U.S.A., and described in a bulletin No. TXC-02201-MC, January 1993. Figure 2 shows schematically a circuit architecture which operates in accordance with TransSwitch's solution. Similar solution have been proposed by the Spanish Telephonic Compay and by the company PMC Serra, as well in the article to Hamlin et al.: "A SONET/SDH Overhead Terminator for STS-3, STS-3C and STM-1", IEEE Journal of Solid-State Circuits, March 1993. All these examples of applications currently available on the telecommunications market use N+1 components, that is one component more than the number of channels in the frame. All of the known solutions provide for the use of a single component to perform the pre-processing and demultiplexing functions on reception, as well as the multiplexing and final processing functions on transmission. In addition, they provide N components, identical with one another, to perform the function of processing in parallel the individual channels on reception, and preparing the individual independent channels on transmission. Usually, the single component is a definitely smaller size than each of the N components. Its dimensions are smaller by a factor of one to five. The underlying technical problem of this invention is to provide a circuit architecture for processing broadband digital signal frames, particularly intended for the SONET/SDH standards, and for optionally decomposing them into subchannels, which architecture has such structural and functional characteristics as to ensure a substantial reduction in the number and dimensions of the circuit components employed, while also reducing costs and facilitating manufacture. Summary of the Invention The solution idea behind this invention is to provide a single component adapted to process single-channel frames, yet usable in a modular manner for a number N of times to process frames comprising N channels. Based on this solution idea, the technical problem is solved by an architecture as previously indicated and defined in the characterizing part of Claim 1. The features and advantages of the architecture according to this invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings. Brief Description of the Drawings In the drawings: Figures 1A and 1B are respective diagramatic representations of circuit architectures according to the prior art; Figure 2 is a further diagramatic representation of a prior art circuit solution; Figure 3 is a diagramatic representation of a circuit architecture embodying this invention; and Figure 4 shows diagramatically a few sequences of digital signals appearing at the inputs and outputs of the various components of the inventive architecture, in an exemplary application involving a three-channel frame. Detailed Description Referring to the drawings, and in particular to Figure 3 thereof, generally and schematically shown at 1 is a circuit architecture according to the invention for processing broadband synchronous signal frames, specifically to the SONET/SDH standard. This architecture is also effective to decompose such frames into submultiple containers of a lower order. In essence, the system proposed herein is able to process both SONET/SDH frames comprising a single channel and frames comprising plural subchannels multiplexed together. Advantageously, the architecture 1 can be implemented in the form of a single electronic circuit integrated in a semiconductor. The architecture 1 comprises a plurality N of identical components 2, each for processing a frame comprising a single channel. The digital signal frames commonly employed by current standards may be of the following types: (A) 9 rows by 90 columns; (B) 9 rows by 270 columns; (C) three 9x90 frames multiplexed together to form a multi-frame of 9 rows by 270 columns; and (D) four 9x270 frames multiplexed together to form a multi-frame of 9 rows by 1080 columns. The components 2 can be connected in parallel together, as explained hereinafter. Each component 2 comprises an input portion 3, an output portion 4, and an internal block 5 serving both receive and transmit functions. The block 5 will also be referred to by the acronym MUX-DEMUX hereinafter, to indicate the multiplexing and demultiplexing capabilities of this block 5, although the functions it is to perform are somewhat more complex than one of mere mux/demux. The MUX-DEMUX block 5 represents a coordinator for the receive and transmit portions, generating clock and synchronization signals for such portions. Specifically, the internal block 5 is to send appropriate data to each portion. The architecture of this invention can process frames of different sizes, wherein the larger size frames may comprise exact multiples of the smaller size frames. In order to make the gist of the invention easier to understand, reference will be made hereinafter to a pratical instance of a frame which comprises but three channels, without restricting by this choice the protection scope of this Application. Each component 2 comprises an input block 1rx carrying out a frame synchronization operation. In praticular, the block 1rx will recognize synchronization patterns, and regardless of the frame size and formation, carry out a descrambling operation and a byte-to-byte parity calculation. The outgoing data from the block 1rx will, therefore, be different from the incoming ones, in that they have been scrambled by a polynomial defined by the transmit standard. These data are output together with the synchronization signal identified. The block 1rx has its output connected to a second block provided in the component 2 of the architecture 1, being referenced 2rx-2tx. This block corresponds essentially to the internal block 5. When a multi-frame is being received, the block 2rx-2tx is operative to extract one byte every three, with frames of the (C) type, or one byte every four, with frames of the (D) type. This extraction takes place after acquiring the synchronization and descrambling the frame in the block 1rx. A third block 3rx is connected downstream of the block 2rx-2tx and comprises counters which allow, based on the synchronization signal obtained from the first block 1rx, to keep track of position within the frame, that is of the row and column, and allow thorough processing of the frame by coordinating all the operations for extracting and processing the bytes to be handled. It should be noted that, with frames of the (C) or (D) type, the block 2rx-2tx passes to the block 3rx a clock signal which is by one third or one fourth slower than the original frame synchronization signal. When transmitting, the second block 2rx-2tx replaces the byte which has been extracted and passed to the third block 3rx with that generated by the first block 1tx. The blocks 1rx and 3rx substantially correspond to the input portion. The component 2 comprises further blocks on which the transmit step depends. Each component comprises a fourth block 1tx whose output is connected to the second block 2rx-2tx. The fourth block composes the frame by calculating the bytes to be inserted, and placing them into appropriate rows and columns. Subblocks are provided within the block 1tx for calculating the various bytes to be inserted in the various positions within the frame. The block 1tx also comprises counters which keep track of position, that is of the row and column, within a given frame and coordinate the frame composition by controlling the acquisition of the byte generated by an appropriate subblock according to the current position. A further block 3tx completes the frame composition by calculating and inserting the parity calculated for all the bytes of the previous frame and already composed at the output. The block 3tx inserts the frame synchronization bytes and effects a scrambling to avoid lengthy repetitions of zero and one values. The blocks 1tx and 3tx substantially correspond to the output portion. It matters to observe that, with non-decomposable single frames of the (A) or (B) type, the operations to be effected by the blocks 1rx and 3rx are executed sequentially with direct connection of such blocks and direct passage of the signals, among which the basic one of synchronization. In this case, the operations to be effected by the blocks 1tx and 3tx are also executed sequentially, and the synchronization signal operates at the same frequency for all four of these blocks 1rx, 3rx, 1tx, 3tx. In other words, frames of the (A) or (B) type do not require operation of the second central block 2rx-2tx. Provided within the component 2 is a further microprocessor interface block which contains program dedicated registers for defining the operation of the entire component 2. In essence, by suitably programming these registers, the component 2 can be set for operation with frames of the (A) or (B) type and, accordingly, to program the second block 2rx-2tx for utilization of the same clock being input to all the blocks. Alternatively, the component 2 could be programmed for operation with frames of the (C) or (D) type. Where the frames are composed of a single channel, MUX-DEMUX must be able to pass the data stream, and corresponding control signals, in a transparent way from the block 1rx to the block 3rx, and in an independent manner from the block 1tx to the block 3tx. Where the frames are instead to be decomposed into subchannels, there are two decompositions possible: a) mapping three frames of 51 Mbit/s into one frame of 155 Mbit/s; b) mapping four frames of 155 Mbit/s into one frame of 622 Mbit/s. The component 2 employed in such cases would be the same, but programmed in different ways, namely: MI (Master Input), SL (Slave), and MO (Master Output). Particularly in case b), there would be two slaves SL1 and SL2 processing two different subchannels in the same way. References MI, SL, MO are attached in Figure 3 to each of the components 2 shown to indicate their functions in this specific example. Furthermore, the disabled blocks are crossed out. Each of the components 2 processes one channel, except that the channel referenced MI will also effect an initial pre-processing 3(1rx) of the complex frame entering reception, while the channel referenced MO will effect the final processing 4(3tx) of the exiting complex frame. The block MUX-DEMUX will operate differently, depending on how it is programmed. The first case a) will be considered first to explain how a frame can be decomposed into three subchannels. The frame includes three smaller frames, alternating a byte from each of the three subframes. Thus, the block MUX-DEMUX of the first component MI is to first enable the block 1rx to act on the most complex incoming frame, as shown in Figure 4. Then, from the block 1rx output, one byte every three is extracted, starting from the third, and passed to the third block 3rx with latched related synchronization signals and, of course, a clock signal at the rate of one third the starting rate. This clock is generated and synchronized by the same MUX-DEMUX. So much for the extraction of a channel to be receive processed; as for the remaining channels to be extracted and processed sequentially from the next components, the same MUX-DEMUX is to output the two channels received from the block 1rx and not forwarded to the remaining local receive block, as well as the channel composed of the local block 1tx which constitutes one of the three channels which are to compose the definitive complex frame. The manner of passing this information on to the following components consists of replacing the channel extracted for local reception with that built by the local transmission. This operation is effected by forwarding the synchronization obtained from the block 1rx and keeping the blocks 3rx and 1tx synchronized by the same clock signal. This is done at a rate being one third the clock used by all MUX-DEMUXs of the various components, and by the 1rx of MI and 3tx of MO only. The same synchronization is also passed to the following components. In addition, the MUX-DEMUX of MI is to disable the local block 3tx, since the final processing of the complete frame can only be effected after the latter has been built, alternating one byte every three, out of the frames from the three blocks 1tx of the various components. The block MUX_DEMUX of the component referenced SL will disable both the local block 1rx and the local block 3tx, since it is to only extract and process the second channel (one byte every three from the second) and replace it with the channel generated by the block 1tx. The block MUX_DEMUX of the component 2 referenced MO will disable its own block 1rx and extract one byte every three from the first, replace it with that from 1tx, and forward the frame thus built to the block 3tx for final processing. The result supplied from this block 3tx represents the final output from the architecture 1. Figure 4 may aid to appreciate the operation of the architecture of this invention. This Figure shows diagramatically the sequences of input and output signals to/from the various components 2 of the architecture 1, as programmed for processing three channels. Likewise, in the second case b) relating to the mapping of four channels in a frame of 622 Mbit/s, the MUX-DEMUX of the master component referenced MI will behave similarly to that previously described, except that the extracted channel will be of one every four from the fourth. The second component, acting as a slave SL1, will extract one byte every four from the third, while the third component SL2 will extract one byte every four from the second, and the last Master Output (MO) component extract one byte every four from the first. The invention does solve the technical problem and offers several advantages, foremost among which is that, in connection with electronic boards for 622 Mbit/s applications, there are four components provided, instead of five as in the prior art, plus a microprocessor and a component serving PMD (Physical Media Dependent) functions. In particular, the spared component in this approach would have had to handle a large number of high-speed interconnections. By contrast, for (either 51 or 155 or 622 Mbit/s) single channel applications, there would be one component involved instead of two. For a practical implementation of this architecture, it is obviously more convenient to develop one, albeit slightly more complex, component than two separate components.

Claims: A circuit architecture for processing multi-channel frames of broadband synchronous digital signals of the SONET/SDH standard, being of a type which comprises a receiving input portion (3) and a transmitting output portion (4) and characterized in that it comprises a plurality of exactly N identical modular components, where N is the number of channels and each of said N identical modular components is adapted to process a frame comprising a single channel and comprises at least a microprocessor interface block which contains program dedicated registers for defining the operation of the modular component itself, each modular component extracting a byte from said frame, keeping track of its position within the frame by a synchronization signal and replacing said byte after a processing operation for allowing complete frame processing by coordinating all the extracting and processing operations for the bytes to be handled. An architecture according to Claim 1, characterized in that each component (2) of said plurality of modular components comprises an input block (1rx) forming a part of said input portion (3) and being intended to perform a frame synchronization operation. An architecture according to Claim 2, characterized in that each component (2) comprises a second internal block (2rx-2tx) connected to at least said input block (1rx), and to the receive and transmit portions of said component (2), acting as a coordinator. An architecture according to Claim 3, characterized in that each component (2) comprises a third block (3rx) connected downstream of said second block (2rx-2tx) and provided with counters which, based on the synchronization signal obtained from the first block (1rx), is adapted to keep track of position within the frame. An architecture according to Claim 4, characterized in that , with multi-channel frames, the second block (2rx-2tx) is adapted to supply, to the third block (3rx), a synchronization signal which is by one third or one quarter slower than the original frame synchronization signal. An architecture according to Claim 4, characterized in that each component (2) further comprises a fourth block (1tx) having its output connected to the second block (2rx-2tx), and which is intended to compose the frame by calculating the bytes to be inserted and placing them on rows and columns. An architecture according to Claim 6, characterized in that , on transmission, the second block (2rx-2tx) replaces the extracted byte passed to the third block (3rx) with that generated by the fourth block (1tx). An architecture according to Claim 7, characterized in that each component (2) comprises a further block (3tx) which is adapted to complete the frame composition by calculating and inserting the calculated parity for all the bytes of the whole previous frame already composed at the output. An architecture according to Claim 1, characterized in that , for multi-channel frames, a first component (MI) acts as a master input, at least a second component (SL) acts as a slave, and at least one final component (MO) acts as a master output. An architecture according to Claim 9, characterized in that said first component (MI) is adapted to carry out an initial pre-processing of the complex frame entering reception, while said final component (MO) is adapted to carry out a processing of the outgoing complex frame.

Inventors: DELL ORO ANNALISA, VEGGETTI ANDREA, DELL'ORO, ANNALISA, VEGGETTI, ANDREA
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1997
Main classification: H04J3
IPC codes: H04Q11, H04J3