SYSTEM FOR CONTROLLING ACCESS TO A REGISTER MAPPED TO AN I/O ADDRESS SPACE OF A COMPUTER SYSTEM

Abstract: A method of providing access to an input/output (I/O) mapped register (60) of a computer system (18) is described. The computer system (18) includes a processor (20) operable in a system management mode (SMM), in which the processor (20) accesses a dedicated system management memory space, a real mode, a protected mode and a virtual 8086 mode. The method includes the steps of firstly receiving an access request at the I/O mapped register (60). Logic circuitry (64) associated with the I/O mapped register (60) then determines whether the processor (20) is operating in SMM by examining the status of a system management interrupt acknowledge (SMIACT#) output of the processor (20). If the logic circuitry (64) determines that the processor (20) is operating in SMM, a first, unrestricted type of access by the processor (20) to the I/O mapped register (60) is provided. Alternatively, if the logic circuitry (64) determines that the processor (20) is not operating in SMM, a second, restricted type of access by the processor (20) to the I/O mapped register (60) is provided. If the first, unrestricted type of access is provided to the processor (20), it performs an operation, under the direction of code stored in the dedicated system management memory address space, on the contents of the I/O mapped register (60).

Description: SYSTEM FOR CONTROLLING ACCESS TO A REGISTER MAPPED TO AN I/O ADDRESS SPACE OF A COMPUTER SYSTEM FIELD OF THE INVENTION The present invention pertains to the field of computer systems. More particularly, the present invention relates to a method and apparatus for controlling access to a register mapped to the input/output (I/O) address space of a computer system so as, inter aha, to protect the register. BACKGROUND OF THE INVENTION Registei s mapped to the I/O address space (termed I/O-mapped registers) are commonly located within interfaces for interfacing between a computer system and a peripheral device. I/O-mapped legisters may also be located in a number of other functional units within a computer system, such as a bus bridge, and may be utilized for a number of functions, including data buffering, status indication and control and configuration functions I/O-mapped legisters ate vulnerable to having then contents coπ upted 01 undesirably altered in a number of ways For example, a "bei sei k" or malfunctioning program, a virus piogram or even the opei atmg system itself may attempt to alter the contents of an I/O-mapped register in an illegal manner The corruption of the contents of an I/O-mapped register may have very serious consequences for the functioning of the computer system, and also tor the physical integrity of the components and peripheral devices of the computer system This vulnerability is particularly serious when the contents ot an I/O-mapped register, performing a contiol oi conf igur ation function, aie modified At the veiy least, corruption of the register contents may lesult in a sof twaie tailuie. In a worst case scenario, such as wheie the I/O-mapped legistei stoies a value relating to powei management, corruption of the contents of the iegistei may cause the piocessor to over-heat and burn This worst case scenario poses a consideiable threat to the integrity of compute! system hardware and software, and even to the safety of a computei system usei The vulneiability of I/O-mapped legistei s also piovides ? . authors of virus programs with the oppoitunity to write virus programs which cause untold mischief and disruption within a computer system Prior art methods of providing access protection for an I/O-mapped register include providing a "locking" mechanism whereby a lock/unlock value is wπtten to a dedicated "lock" register associated with an I/O-mapped register Pπor to access of the I/O-mapped register, a protection algorithm is executed which determines, by inspection of the "lock" registei, whether the I/O-mapped register can be accessed While this method provides relatively effective protection against an attempt by a malf unctioning program to access the I/O-mapped iegister, it does not provide adequate protection against an intelligent foe, such as virus program The virus program may, for example, gain access to, and ovei write, the "lock" register, or may attack and bypass the protection algorithm A micropiocessor architectuie (termed Intel Aichitectuie) developed by Intel Corpoiation of Santa Clara, California, also provides piotection mechanisms for I/O-mapped registers Details of these piotection mechanisms are piovided in "Pentium® Processoi User's Manual, Volume 3 Architectuie and Programming Manual", published 1994, pages 12 1 to 12-8, and pages 1 *5-5 to 15-9 Specifically, the Intel architectuie makes provision foi two I/O access protection mechanisms Undci both piotection mechanisms, an I/O access is checked in parallel with addiess translation to determine whethei it satisfies various protection requπements The fust I/O protection mechanism recognizes loin privilege levels, labeled 0 to 3, under the so-called "protection ring model" A program being executed by the piocessoi has a pnvilege level, termed the Cuπent Privilege Level (CPL), which is stored in the lower two bits of the CS segment iegister Access to I/O instructions, such as IN and OUT, by an application piogiam is contiolled by an Input/Output Piotection Level (IOPL), which is compared to the CPL to determine whethei the application piogiam can vahdly access an I/O instiuction This protection mechanism generally allows the operating system, which has a privilege level of 0, and certain device dπveis, which have pnvilege levels of 1, to access I/O instiuctions, while blocking access to I/O instiuctions by applications, and less pπvileged device dnveis, which have a pnvilege level of ^ However, this protection mechanism is not effective against a virus program that manages to obtain a privilege level of 0, or against a poorly written device driver having a level 1 privilege. The second I/O protection mechanism provides an I/O permission bit map which controls access to individual registers mapped to the I/O address space. This protection mechanism is an implementation of the "locking" mechanism described above. Briefly, each bit of the bit map corresponds to an I/O register byte, and the relevant bit is tested by the processor before accessing an I/O- mapped register. If the tested bit is set, a general-protection error is generated. On the other hand, if the test bit is not set, the I/O operation can proceed. However, this protection mechanism suffers from the inadequacies detailed above with reference to "locking" mechanisms. The above protection mechanisms also suffer from the drawback of providing either complete access or denying any access to the I/O address space. This "all or nothing" approach is inflexible, and does not pemiit varying degrees or levels of protection to be afforded to an I/O-mapped register. Finally, aside from the protection issue, it is desirable to facilitate more flexible use of I/O-mapped registers. Such registers are typically limited to perfbnning a single function and may, depending on the operating condition of the computer system, comprise an under-utilized resource in certain scenarios, while there may exist a shortage of the resource provided by an I/O-mapped register in another scenario. SUMMARY OF THE INVENTION According to a first aspect of the invention there is provided a method of providing access to an input/output (I/O)-mapped register of a computer system, the computer system including a processor operable in at least first and second operational modes. The method includes the steps of firstly receiving an access request to the I/O-mapped register. Logic circuitry associated with the I/O-mapped register then determines whether the processor is operating in the first mode, which may be a system management mode (SMM). If the logic circuitry detennines that the processor is operating in the first mode, a first, unrestricted type of access by the processor to the I/O-mapped register is provided. Alternatively, if the logic circuitry detennines that the processor is operating in the second mode, a second, restricted type of access by the processor to the I/O- mapped register is provided. If the first, unrestricted type of access is provided to the processor, it performs an operation, on the contents of the I/O-mapped register, under the direction of code stored in a dedicated system management memory address space. The step of providing a first type of access may comprise providing at least read access to the I/O-mapped register, and the step of providing a second type of access may comprise preventing access to the I/O-mapped register. Alternatively, the step of providing a first type of access may comprise providing both read and write access to the I/O-mapped register, and the step of providing a second type of access may comprise providing only read access to the I/O-mapped register. According to a second aspect of the invention there is provided a method of controlling access to a register mapped to an input/output (I/O) address space within a computer system. The computer system defines a memory address space, the I/O address space, and a system management mode (SMM) memory address space. The computer system further includes a processor operable in a system management mode (SMM) in which the processor accesses the SMM memory address space. The method requires receiving a system management request at the processor, and then placing the processor in the system management mode in response receiving the system management request. Thereafter, the processor is provided with a first type of access to the register, and performs an operation on the contents of the register. The processor is then placed out of the system management mode, and provided with a second type of access to the register. According to a third aspect of the invention there is provided an interface arrangement for use in a computer system. The computer system is operable in first and second modes of operation. The interface arrangement includes a register mapped to an input/output (I/O) address space, a decoder having an input to receive address data identifying the register, and an output to provide a select signal to the register, and logic circuitry configured to detect when the computer system is operating in the first mode, and configured to provide a first type of access to the register when the computer system is operating in the first mode, and to provide a second type of access to the register when the computer system is not operating in the first mode. The invention extends to a computer system including an interface arrangement as described above. Oilier features of the present invention will be apparent from the accompanying drawings and from the detailed description which follows. BRIEF DESCRIPTION OF THE DRAWINGS The present invention is illustrated by way of example in the figures of the accompanying drawings, in which like references indicate similar elements and in which: Figure 1 is a state diagram indicating the various modes of operation of a processor. Figure 2 is a block diagram showing a computer system in which the present invention may be realized. Figure 3A is a block diagram showing processor addiess space when a processor is not operating in a system management mode. Figure 3B is a block diagram showing piocessor address space when a processor is operating in a system management mode Figure 4 is a block diagram showing a computer system incorporating apparatus tor controlling access to an I/O-mapped register according to the invention. Figure 5 is a block diagram showing a first embodiment of a circuit arrangement for controlling access to an I/O-mapped register according to the invention Figure 6 is a block diagram showing a second embodiment of a circuit arrangement for controlling access to an I/O-mapped register according to the invention Figure 7 is a block diagram showing a third embodiment of a circuit arrangement for controlling access to an I/O-mapped register according to the invention Figure S is a flow-chart illustrating one embodiment of a method of controlling access to an I/O-mapped legistei according to the invention Figure 9 is a flow-chart illustrating one embodiment of a method by which a processoi obtains unrestricted access to an I/O-mapped register Figure 10 is a diagrammatic representation of a system management random access memoiy (SMRAM) according to the invention Figures 1 1 A is a diagrammatic representation of the address spaces accessed by a piocessor in a pnor ait computei system Figures 1 1 B is a diagrammatic lepiesentation of the address spaces accessed by a piocessor in a computer system incorpoiating the present invention DETAILED DESCRIPTION A method and apparatus for controlling access to a register mapped to an input/output (I/O) address space of a computer system are described. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. I/O Address Space Computer systems employing certain processor architectures provide two distinct address spaces, namely a memory address space, and an I/O address space. Registers within I/O interfaces and other functional units are mapped to the I/O address space, and are referred to as 1/O-mapped registers. Generally, an I/O port has a dedicated I/O-mapped register associated therewith. However, two or more I/O- mapped registers may share a common port, if appropriate circuitry is provided for directing data between the registers and ports. I/O-mapped registers may perform a number of functions within a computer system, such as data buffering, status and configuration indication, and control functions. In one embodiment, a computer system allows I/O-ports to be addressed in two ways, namely through a memory-mapped I/O operation, where I/O ports appear in the memory address space, and through a separate I/O address space accessed using I/O instructions. These instructions include IN and OUT instructions. System Management Mode Processors within a computer system may be designed to operate in a number of different modes, in which various features and functions are enabled or disabled. The enabling and disabling of these features may be motivated by a wide range of considerations including performance optimization, backwards compatibility imd function transparency. For example, the Pentium® processor manufactured by Intel Corporation of Santa Clara, California, is capable of operating in any one of the four modes illustrated in Figure 1, namely 1 a Real- Address Mode 10; 2 a Protected Mode 12; 3 a Virtual 8086 Mode 14; and 4 a System Management Mode (SMM) 16 Such modes are well-known in the art The SMM 16 piovides high level systems functions, such as power management and security, in a manner transparent to both application software and the opeiating system For example, code to power-down a penpheral device attei it has been idle foi a pre-determined amount of time is stoied in a dedicated SMM addiess space, termed the system management landom access memory (SMRAM) This code can be accessed when a processor enteis the SMM 16, and executed completely tiansparently to the operating system, device dnvers and application software This negates the necessity for application and operating system software developei s to customize softwaie to incorpoiate such powei management features Refeπ ing to Figure 2, a computer system 18 capable of operating in SMM 16, and within which the present invention can be employed, is shown The computei system 18 has as its pπmaiy components a processor 20, a host bus 22, a host budge 24, main memory 26, an intennediate bus 28, an expansion bridge 30 and an expansion bus 32 The piocessoi 20 piocesses signals, pertoims computations and controls operations The host bridge 24 provides an interface between the host bus 22 and the mtei mediate bus 28 In one embodiment, the intermediate bus 28 is a Peπpheial Components Interconnect (PCI) bus, and is operated accoidtng to the Peripheral Components Inteiconnect (PCI) Local Bus Specification, Revision 2 1 , published June 1 , 1995 The expansion budge 30 piovides an interface between the intermediate bus 28 and the expansion bus 32, and is viewed by an intennediate bus arbitei (not shown) as a PCI device In one embodiment, the expansion bus 32 is eithet an Industiy Standaid Architectuie (ISA) bus or an Extended Industiy Standaid Architectuie (EISA) bus The host bridge 24 incorporates a memory controller 34 for controlling access to the main memory 26. A PCI device 36.1 , which may be an input/output (I/O) device or a further expansion bridge, is coupled to the intermediate bus 28 via an interface 39. Examples of I/O devices are well-known and may include Small Computer System Interface (SCSI) controllers, Personal Computer Memory Card International Association (PCMCIA) interfaces and keyboard controllers. A graphics controller 36.2 is also coupled to the intermediate bus 28 via an interface 39, and controls access to a graphics frame buffer 38. An expansion bus master 40. 1 and an expansion bus slave 40.2 are coupled to the expansion bus 32 via interfaces 4 1 . The expansion bus master 40.1 may, for example, be a Direct Memory Access (DMA) controller. The expansion bus slave 40.2 may be a floppy disk drive. The interfaces 39 and 41 include a number of registers (not shown), including data-buffering, control and status registers, and appropriate decoding logic (not shown), which will be described in further detail below. The expansion bridge 30 provides an interface between the intermediate bus 28 and the expansion bus 32. The expansion bridge 30 may also include registers of the types described above and decoding logic. Accordingly, for the purposes of this specification, the term "interface arrangement" shall be taken to refer to either interfaces which provide an interface between a computer system and a peripheral device (such as interfaces 39 and 41 ) or to bus bridges (such as the expansion bridge 30). Furthermore, an interface arrangement could be incorporated into the computer- system or the peripheral device, or could be a discrete functional unit. As shown in Figure 2, the expansion bridge 30, the graphics controller 36.2, the PCI device 36.1 , the expansion bus master 40.1 and the expansion bus slave 40.2 are coupled to a provide a system management interrupt (SMI#) signal 42 to the processor 20. The SMI# signal 42 is a non-maskable interrupt having a higher priority than all other interrupts, including other non-maskable interrupts. The processor 20 is coupled to provide a system management interrupt acknowledge (SMIACT#) signal 44 to the memory controller 34, the SMIACT# signal 44 being asserted in response to the assertion of the SMI# signal 42. The # designation following each signal indicates that the signal is active low, and is accordingly asserted by a low transition. It will be appreciated that any peripheral device, bus bridge, power management circuit or security circuit may be coupled to provide the SMI# signal 42 to the processor 20. When the SMI# signal 42 is asserted, the processor 20, in acknowledgment, asserts the SMIACT# signal 44 to notify the memory controller 34 that the next processor access will be to system management random access memory (SMRAM) 50. Figure 3A shows the processor address space 46 prior to entry into the SMM, while Figure 3B shows the processor address space 48 after assertion of the SMIACT# signal 44. As is shown in Figure 3B, the SMRAM 50 is mapped to an address range within processor address space 48. After assertion of the SMI# signal 42 by a device, the processor 20 waits for all outstanding data write operations to complete, and then saves register state information into the SMRAM 50. The processor then enters SMM 16 by setting internal registers to initial SMM state conditions, and begins execution of a SMI handler (not shown) which is stored at a predetermined entry point within the SMRAM 50. While in SMM 16, the processor 20 is able to access the entire I/O address space, and the entire memory address space. When the SMI handler is invoked it will firstly examine a status vector to deteπnine the nature and source of the SMI# signal 42. Having identified the nature and source of the request, the SMI handler then executes a SMM routine which addresses and services the request. The SMI# signal 42 may be asserted by a number of devices for a number of reasons, the most common requests being to: (a) power-down an idle device; (b) power-up a device to which access is required; (c) modify the format of data in a register so as to allow compatibility between the computer system 18 and a peripheral device; (d) service mobile computing functions which are not serviceable by the operating system (e.g. docking functions); (e) throttle clocks and oscillators; (f) save state information for the computer system: and (g) power-down the computer system. Other functions dependent on the system design may also cause the assertion of the SM1# signal 42. Once the SMI handler has executed the appropriate SMM routine, a leturn from system management (RSM) instruction is issued, and the processor state that was stored upon entry into SMM is restored Accordingly, SMM 16 provides a transparent and convenient mannei of servicing system management functions within the computei system 18 Apparatus Description Tin ning now to Figure 4, theie is shown the computei system 18 incorporating one embodiment of the present invention The expansion bridge 30 is shown to include a plurality of legistei s 60 1 to 60 3, these registeis 60 being mapped to the I/O address space The registei s 60 I to 60 3 are configured to perform a numbei of f unctions, including data-buftenng, status indication and vanous contiol f unctions The expansion bndge 30 also includes a decoder 62 which is coupled to icceive addiess and control lntonnation tiom the intermediate bus 28, and to select one of the legistei s 60 1 to 60 3 for access by the processor 20 oi anothei device within the computer system 18 Logic circuitiy 64 is also shown to be included within the expansion bndge 30, and to be coupled to leceive the SMIACT# signal 44 from the piocessoi 20 Accoidingly, by monitonng the SMIACT# signal 44, the logic cπcuiti y 64 is able to detect when the piocessoi 20 entei s SM M 16 ' I he logic cucuitry 64 is f unctional to provide a fu st type of access to the registei s 60 1 to 60 3 when it detects that the piocessoi 20 is in SMM 16, and to provide a second type of access to the legisteis 60 1 to 60 3 when it detects that the piocessoi 20 m not in SMM 16 (i e in leal-addiess, piotected oi virtual 8086 mode) Moie specif ically, the logic cncuitiy 64 allows f ull ieud/wnte access to the registei s 60 1 to 60 3 when the pi ocessoi 20 is detected to be in SMM 16, while pi eventing, oi bloc king, access to the iegistei s 60 1 to 60 3 when the processor is not in SM M 16 Figure 4 shows the logic cncuiti y 64 as being coupled to the decoder 62, and piovidmg an input into the decoder 62 to achieve the functionality descnbed above It will howevei be appreciated that the logic cncuiti y 64 could be incoi poiated into the decodei 62, oi could alternatively be located down-sti eam of the decodei 62 to gate a select signal liom the decodei 62 when the processoi 20 is not in SMM 16 Furthermore, the first type of access allowed by the logic circuitry 64 need not be full read/wπte access, and the second type of access need not be a complete access block. For example, the first type of access could be read access only, paired with a second type of access providing a complete access block to a specific register. Alternatively, the first type of access could be full read/write access, paired with a second type of access allowing only read access to a register The first and second access types described above aie effective to provide varying degrees of protection to a registei , by either totally preventing, or merely limiting, access to a register when the processor 20 is not in SMM 16 Accoidingly, the above described arrangement provides a simple, yet effective, protection against malfunctioning programs, virus programs or even an operating system kernel which may otherwise have been able to access, and illegally modify, the contents ol the registers 60 The secuie protection af forded to the registers 60 as described above is particularly valuable when any one of the registers 60. 1 to 60.3 is used toi powei management and system configuration purposes, as corruption of data stoied in such a legistei could have serious implications for the integrity of data, software and even physical devices within the computer system 1 8. The fu st and second types of access need not relate to degiees of access to the registei s 60, but can relate to the manner in which the legistei s 60 themselves operate Foi example, the first type of access allowed by the logic circuitry 64 may be to facilitate access to the register 60 1 as a serial port, and the second type of access may be to allow access to the register 60 1 as a parallel port, or vice versa Figures 5 to 7 illustrate in more detail circuit an angements for facilitating the first and second types of access to an 1/O-mapped registei . Referring firstly to Figure 5, thei e is shown a circuit arrangement 66, including a chip 68 having a control/status registei 70 and a data register 72, the registers 70 and 72 being mapped to the I/O addiess space The ciicuit aπangement 66 further includes an address decoder 74, which is coupled to receive address data from an address bus 76, and a memory/input-output (M/IO) signal fiom a control bus 78 The circuit arrangement 66 also includes logic circuitry in the form of an AND gate 80, which is coupled to receive a SELECT signal 82 from the address decoder 74, and a SMIACT# signal 84 from the control bus 78. The AND gate 80 is also coupled to provide a CHIP SELECT signal 86 to the chip 68. Accordingly, by allowing the AND gate 80 to gate the SELECT signal 82 from the address decoder 74, the AND gate 80 is able to prevent any access to the registers 70 and 72 when a processor from which the SMIACT# signal 84 originates is not operating in SMM 16. In this way, the register 70 and 72 are protected from corruption or unauthorized modification when the processor is not in SMM 16 Figure 6 shows a further embodiment of the present invention, in which a circuit arrangement 88 includes an I/O-mapped register 90, and an address decoder 92 The address decoder 92 is coupled to receive address data from an address bus 76, and a memory/input-output (M/IO) signal fiom a control bus 78 The circuit arrangement 88 also includes logic circuitry comprising AND gates 94 and 96, and an OR gate 98. The AND gate 94 is coupled to leceive a read/write (R/W) signal 100 from the control bus 78 and a SELECT signal 102 from the addiess decoder 92, and to output a SELECT 1 signal 104 to the OR gate 98 The AND gate 96 is coupled to receive the SELECT signal 102 from the address decoder 92 and a SM IACT# signal 106 from the control bus, and to output a SELECT2 signal 108 to the OR gate 98 The OR gate 98 outputs a REGISTER SELECT signal 1 10 to the register 90 Accordingly, it will be appreciated that when the SM IACT# signal 106 is de-asserted, the decoder 92 and logic circuitry configuration shown in Figure 4 will only permit read access to the register 90. Howevei , when the SMIACT# signal 106 is asserted both read and wnte access to the register 90 is facilitated. Figure 7 shows yet another embodiment of the present invention, in which a circuit arrangement 1 10 includes a pair of registers 1 12 and 1 14 which are both mapped to the same I/O address The circuit arrangement 1 10 also includes an address decoder 1 16 The addiess decodei 1 16 is coupled to receive address data from an addiess bus 76, and a memory/input-output (M/IO) signal from a control bus 78. The circuit arrangement 1 10 also includes AND gates 1 18 and 120 and a multiplexer (MUX) 122. The AND gates 1 18 and 120 aie each coupled to receive a SELECT signal 124 from the address decoder 1 16 The AND gate 1 18 is further coupled to t eceive an SM IACT# signal 126 from the control bus, while AND gate 120 is coupled to receive an inverted SM1ACT# signal 128 from an inverter 130 The AND gate 1 18 provides a SELECT1 signal 132 to the register 1 12 when a processoi from which the SMIACT# signal originates is not in SMM 16. Similarly, the AND gate 120 provides a SELECT2 signal 134 to the register 1 14 when the processor from which the SMIACT# signal originates is in SMM 16. The MUX 122 is a bi-directional multiplexer, and couples one of the registers 1 12 or 1 14 to a data bus 79, depending on whether the SMI ACT# signal 126 is high or low More specifically, when the SMIACTW signal is asserted (i.e low), indicating that the processor is in SMM 16, the MUX 122 will couple the register 1 14 to the data bus 79 for either a read or write operation. Alternatively, should the SMIACT# signal 126 not be asserted (i.e high), indicating that the processor is not in SMM 16, the MUX 122 will couple the register 122 to the data bus 79 Accordingly, the contents of the registei 1 14 are inaccessible when the processoi is not m SMM 16, and piotected from access, and possible corruption, by a virus oi a malf unctioning program when the piocessor is not in SMM 16 It will further be appreciated that the registers described above can be of varying sizes, and accordingly the resolution with which the present invention can be applied to piovide protection can also be varied. For example, each of the registei s described above could have a size of between 1 and 124 bits Method Description Turning now to Figure 8, a method 132 of controlling access to an I/O- mapped registei is illustrated The method compπses firstly leceiving a request to access an I/O-mapped registei at decodei and logic cucuitry associated with the 1/O-mapped registei at step 134 At step 136, the logic circuitry detects the processor mode Moie specifically, it is detected whether a processor from which the access request issued is functioning in SMM by examining an SMIACT# signal originating from the processoi If it is determined at step 138 that the processor is functioning in SMM, then the method proceeds to step 140, and the piocessoi is gianted uniestπcted access to the I/O-mapped register Alternatively, if it is determined at step 138 that the processor is not f unctioning in SMM, then the method proceeds to step 142, and the processor is either granted restricted or no access to the I/O-mapped register. A method 150 by which a processor obtains unrestricted access to an I/O- mapped register is illustrated in Figure 9. At step 152, a device, such as a bus bridge incorporating a control register which is mapped to the I/O address space and which is perfoπning a power management function, issues a system management interrupt request to a processor by asserting a SMI# signal. At step 154, the processor acknowledges the request by asserting a S MIACT# signal. The processor then proceeds 10 map the SMRAM to a memory range in the memory address space, as shown in Figure 3B, and writes processor state information lo the SM RAM at step 156. Figure 10 provides a diagrammatic representation of SMRAM 180, and shows the location of the processor state information 1 82 written to the SMRAM 1 80 at step 156. At step 158, the processor enters SMM, and at step 160 the processor jumps to an entry point 184 in the SMRAM 1 80 to access an SMI handler routine 1 86. The SMI handler routine 186 then checks status registers (also termed a status vector) to deteπnine the nature and source of the SMI request at step 162. In the present example, the status register reveals that the SMI request originated from the bus bridge described above and that the contents of the control register thereof require modification. For example, the control register may contain a "throttle" value indicative of a percentage of the full operating frequency at which the processor is to operate. Accordingly, the status register will reveal that the SMI request was issued in response to a need to "throttle down" the operating frequency of the processor, and accordingly to reduce the "throttle" value. At step 164, the SMI handler routine 186 is given unrestricted access to the relevant I/O-mapped register, as described above, by reason of the assertion of the SM1ACT# signal. At step 166, the SMI handler routine 1 86 performs the required operation on the contents of the register (i.e. on the "throttle" value). More specifically, the S MI handler routine 1 86 executes the I/O-mapped register access and modification code 188, which comprises part of the SMI handler routine 186, as shown in Figure 10. Having completed execution on the code 188, the SMI handler routine 186 issues a return from S MM (RSM ) instruction at step 168. The processor then retrieves the processor state information 182 at step 170, and restores the processor state that existed prior to issuance of the SM I# signal at step 152. Figures I 1A and 11 B show two address space schemes, the address space scheme of Figure 11 A being implemented in the prior art, and the address space scheme of Figure 1 I B being achievable by the present invention. In the scheme illustrated in Figure 1 1 A, a processor 190 is shown to have access to the address space indicated in circle 192 when the processor 190 is in the real, protected or virtual 8086 modes of operation, and to the address space indicated in circle 194 when in SMM. As is apparent, the processor 190 has access to the full I/O mapped space in all modes of operation. In the scheme illustrated in Figure 1 I B, the processor 190 has access to the address space indicated in circle 196 when the processor is in the real, protected or virtual 8086 modes of operation, and to the address space indicated in circle 198 when in SMM. As indicated in circle 198, the present invention allows for the creation of a dedicated SMM I/O- mapped address space, which is only accessible when the processor is in the SMM mode. The present invention provides an effective manner of controlling access by a piocessor or other computer device to an 1/O-mapped register. The inclusion of circuitry to implement the present invention can be achieved without incurring a high die space penalty, in view of the simplicity of the circuitry. The present invention allows for the creation of a protected I/O address space, which can only be accessed when a processor is operating in SM M. As the protection afforded to the protected I/O address space is only lifted when the processor is operating in SMM, the invention provides effective protection to the contents of I/O-mapped register against malfunctioning and virus programs, as well as illegal accesses by the operating system. The present invention is also advantageous in that it allows for the creation of various depths or levels of protection. For example, the protection can be absolute, or the protection can merely extend to blocking write transactions to a protected I/O-mapped register. The invention may allow for the configuration oϊ I/O-mapped registers for expanded functionality. For example, in a further embodiment, the present invention may allow an I/O-mapped register to be configured as either a serial or parallel data-buffer register, depending on the mode in which the processor is operating Thus, a method and apparatus for controlling access to a register mapped to an I/O addiess space of a computer system have been described Although the present invention has been described with ieference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing fiom the broader spirit and scope of the invention Accoidingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense

Claims: CLA I MS What is claimed is: 1 . A method of providing access to an input/output (I/O)-mapped register of a computer system, the computer system including a processor operable in first and second modes of operation, the method including the steps of: receiving a request for access to the I/O-mapped register, deteπrπnmg whether the processor is operating m the first mode of operation, pioviding a fu st type of access to the I/O-mapped registei if the processor is operating in the first mode of operation; and providing a second type of access to the I/O-mapped i egister if the processoi is not operating in the first mode of operation 2 The method of claim 1 wherein the first mode of operation is a system management mode m which the processor accesses a dedicated system management memory address space, and the step of determining comprises determining whether the processoi is operating in the system management mode 3 The method of claim 2 further comprising the step of perfoπning an operation, under the direction of code stored in the dedicated system management memory address space, on the contents ol the I/O-mapped register if the first type of access to the I/O-mapped register is provided. 4 The method of claim 1 wherein the second type ol access is restricted relative to the f u st type of access, so as to provide protection foi the I/O-mapped register fi om piedetei mined access types when the processor is not operating in the first mode 5 The method ot claim 4 wherein the step of providing a first type of access comprises pioviding at least read access to the I/O-mapped registei , and wherein the step of providing a second type of access comprises preventing access to the I/O-mapped register. 6. The method of claim 5 wherein the step of providing a first type of access comprises providing both read and write access to the I/O-mapped register. 7. The method of claim 4 wherein the step of providing a first type of access comprises providing both read and write access to the I/O-mapped register, and wherein the step of providing a second type of access comprises providing only read access to the I/O-mapped register. 8. The method of claim 2 wherein the step of detennining whether the processor is operating in the system management mode comprises the steps of: receiving a system management mode slat us signal from the processor; and monitoring the system management mode status signal to determine whether the processor is operating in the system management mode. 9. A method of providing access to a register mapped to an input/output (I/O) address space of a computer system, the method including the steps of: receiving a system management request at the processor; placing the processor in a system management mode in response to receipt of the system management request; providing the processor with a first type of access to the register mapped to the input/output (I/O) address space of the computer system; performing an operation on the contents of the register; placing the processor out of the system management mode: and providing the processor with a second type of access to the register. 10. The method of claim 9 wherein the computer system accesses a dedicated SMM memory address space when in the system management mode, and wherein the operation on the contents of the register is perfoπned by the processor under the direction of code stored in the SMM memory address space 1 1 An interface arrangement for use in a computer system, the computei system being operable in first and second modes of operation, the interface arrangement comprising a register mapped to an input/output (I/O) address space, a decoder having an input coupled to leceive address data identifying the registei , and an output coupled to output a select signal indicating that addiess data identifies the registei , and logic cncuitry configured to detect when the computer system is operating in the fu st mode, and configuied to piovide a f u st type of access to the tegistei when the computer system is operating in the first mode, and to provide a second type of access to the iegister when the computer system is not opei ating in the first mode 12 The interface arrangement of claim 1 1 wherein the f u st mode of operation is a system management mode in which a piocessor of the computer system accesses a dedicated system management memory address space, and the logic circuitry is configured to provide the first type of access to the iegister when the piocessor is operating in the system management mode 1 3 The interface ai rangement of claim 1 1 wheiein the logic circuitry includes an input coupled to receive a signal from a piocessoi of the computer system which indicates that the computer system is opeiating in the l u st mode 1 4 The interface airangement ot claim 1 1 wheiein the second type ot access is restricted lelative to the fu st type ot access, so as to provide piotection for the T) . register from predetermined access types when the processor is not operating in the first mode. 15 The interface arrangement of claim 14 wherein the logic circuitry is configured to provide at least read access to the register when the computer system is operating in the first mode, and to prevent access to the register when the computer system is not operating in the first mode. 16 The interface arrangement of claim 14 wherein the logic circuitry is configured to provide both read and write access to the register when the computer system is opeiating in the fu st mode, and to provide only iead access to the register when the computer system is not opei ating in the fu st mode 17. The interface arrangement of claim 1 1 wheiein the logic cncuitiy is configured to provide access to the register as a first type of port when the computer system is operating in the first mode, and to provide access to the register as a second type of port when the computei system is not operating in the first mode. 1 8 Λ computer system being operable in a system management mode (SMM), the computer system including . a processoi having access to a dedicated SMM memoiy addiess space when the computer system is operating in the system management mode, an interface arrangement, coupled to the processoi , and including. a tegistei mapped to an input/output (I/O) addiess space, a decoder having an input coupled to receive address data identifying the register, and an output coupled to provide a select signal to the registei; and logic cncuitiy conf igured to detect when the computer system is operating in the system management mode, and conf iguied to provide a first type of access by the processor to the register when the computer system is operating in the system management mode, and to provide a second type of access by the processor to the register when the computer system is not operating in the system management mode.

Inventors: POISNER DAVID I, POISNER, DAVID, I.
Applicants: INTEL CORP, INTEL CORPORATION
Application year: 1997
Main classification: G06F15
IPC codes: G06F9, G06F13, G06F15