POWER SUPPLY FOR FEEDING AND IGNITING A DISCHARGE LAMP

Abstract: A power supply according to the invention for feeding and igniting a discharge lamp (85) comprises an integrated circuit (109) having contact pins to cooperate with an external circuit (60, 70) with output clamps (88, 170) for the discharge lamp. The integrated circuit (109) comprises at least one pin (VL) coupled to a switch (82) in the external circuit, for placing the switch in a first switching state when at a first logic level and in a second switching state when at a second logic level. Said at least one contact pin (VL), when at its second logic level also serves for receiving at least one sensed signal (Sig) representing an operating condition of the external circuit.

Description: Power supply for feeding and igniting a discharge lamp. The invention relates to a power supply for feeding and igniting a discharge lamp, comprising an integrated circuit having contact pins to cooperate with an external circuit comprising output clamps for the discharge lamp, the integrated circuit comprising at least one contact pin coupled to a switch in the external circuit, for placing the switch in a first switching state when at a first logic level and in a second switching state when at a second logic level. Such a power supply is known from U.S. Patent No. 4,952,849. The power supply includes both an input stage and an output stage. The input stage provides a D.C. source of power for the ouφut stage through conversion of an A.C. signal, obtained from a power line, to a D.C. signal. The output stage, which can be of the half bridge . inverter type, drives the lamp. Control circuitry, is used therein a.o. to control the heating of the lamp filaments for conditioning the latter prior to ignition (preheating). Control circuitry may also control cut back in the power consumed by the filaments once the lamp ignites. A miniaturisation of the power supply is achieved by implementing control circuitry thereof as an integrated circuit. The size of an integrated circuit is determined for a large part by the number of contact pins, hereinafter also denoted by pins. It is an object of the invention to provide a power supply of the above- mentioned kind in which the integrated circuit requires less contact pins. According to the invention this object is achieved in that said at least one contact pin when at its second logic level also serves for receiving at least one sensed signal representing an operating condition of the external circuit. By using one or more contact pins both as an output and as an input, less contact pins are necessary and a smaller surface area of the integrated circuit suffices. A practical embodiment is described by Claim 2. To force the said at least one contact pin to the first logic level, the semiconductor switch connected to the voltage corresponding to the first logic level is rendered conducting by the common control signal. At the same time the other semiconductor switch, while being of the opposite type, is rendered non-conducting. When changing the logic level of the control signal the semiconductor switch connected to the voltage corresponding to the first logic level is rendered non-conducting, so that the contact pin is no longer forced to its first logic level. The control signal then renders the other semiconductor switch conducting, so that it can pass the sensed signal to the circuit destinated for processing it. A favourable embodiment of the power supply according to the invention is characterised by Claim 3. A practical implementation of said embodiment is defined by Claim 4. Claim 5 describes an attractive embodiment of the power supply according to the invention. Preferably the second resonant frequency thereof is higher than the first resonant frequency. During preheat, when the pin is at the first logic level, the additional component in the output circuit is coupled to the combination of the inductor and the capacitor, so that the output circuit is characterised by the first, relatively low resonant frequency. Since the switching frequency during preheat is much higher than this lowered resonant frequency, it is unlikely that a high voltage will be applied to the lamp during preheat. After preheat, the pin assumes the second logic level, resulting in that the additional component in the output circuit is decoupled from the combination of the inductor and the capacitor. Now the output circuit is characterised by the second, relatively high resonant frequency. During ignition, the switching frequency of the inverter sweeps downwardly from its high frequency during preheat toward the increased unloaded resonant frequency. By increasing the unloaded resonant frequency following preheat it is much easier to develop a sufficiently high voltage across the lamp for ignition of the latter. The said at least one contact pin when at the low logic level also receives a signal representing the voltage condition across the lamp which is processed for purposes of power regulation. The signal may also be used for the purpose of overvoltage detection. These and other aspects of the power supply according to the invention will be explained in more detail with reference to the drawing, in which: FIG. 1 is a block diagram illustrating a power supply in accordance with the invention; FIG. 2 is a schematic of an inverter and associated drive control circuit in accordance with the invention. As shown in FIG. 1, a power supply 10 is supplied from an A.C. power line represented by an A.C. source 20. The power supply comprises an integrated circuit 109 having contact pins to cooperate with an external circuit, i.e. an inverter 60 and a load 70, via drive control circuit 65. The power supply 10 further comprises an EMI filter 30, a full wave diode bridge 40 and a preconditioner 50. The load 70 includes an inductor 75, a capacitor 80 and output clamps 88, 170 for a discharge lamp, i.e. a fluorescent lamp 85. EMI filter 30 removes harmonics generated by preconditioner 50 and inverter 60. Diode bridge 40 rectifies the filtered sinusoidal voltage resulting in a D.C. voltage with ripple. Preconditioner 50 serves several functions. The rectified peak A.C. voltage outputted from diode bridge 40 is both boosted and made into a substantially constant D.C. voltage supplied to inverter 60. Preconditioner 50 also improves the overall power factor of power supply 10. For example, 120, 220 and 277 RMS voltages applied to EMI filter 30 by A.C. source 20 result in D.C. voltages of approximately 250, 410 and 490 V being supplied to inverter 60, respectively. Inverter 60, which is driven by drive control circuit 65 during full arc discharge of lamp 85 at a switching frequency of about 45 kilohertz (kHz), converts the D.C. voltage into a square wave voltage waveform applied to load 70. The lamp illumination level can be increased and decreased by decreasing and increasing the frequency of this square wave voltage waveform, respectively. Inverter 60, load 70 and drive control circuit 65 are shown in greater detail in FIG. 2. A substantially constant voltage VDC provided by preconditioner 50 is supplied to inverter 60 across a pair of input terminals 61 and 62 of the latter. Inverter 60 is configured as a half-bridge and includes a B+ (rail) bus 101, a grounded return bus 102 and a pair of switches (e.g. power MOSFETs) 100 and 112 which are serially connected between bus 101 and bus 102. Switches 100 and 112 are joined together at a junction 110 and commonly identified as forming a totem pole arrangement. The MOSFETs serving as switches 100 and 112 have a pair of gates GI and G2, respectively. Buses 101 and 102 are connected to input terminals 61 and 62, respectively. A resistor 103 and a capacitor 106 are joined together at a junction 104 and serially connected between bus 101 and bus 102. A pair of capacitors 115 and 118 are joined together at a junction 116 and serially connected between junction 110 and bus 102. A zener diode 121 and a diode 123 are joined together at junction 116 and serially connected between junction 104 and bus 102. Inductor 75, capacitor 80, a capacitor 81, lamp 85 and a resistor 174 are joined together at output clamp 170. A pair of windings 76 and 77 are coupled to winding 75 for application of voltages across the filaments (not shown) of lamp 85 in conditioning the latter during the preheat operation. A D.C. blocking capacitor 126 and inductor 75 are serially connected between junction 110 and output clamp 170. Capacitor 80 and a pair of resistors 153 and 177 are connected together at a junction 179. Lamp 85 and resistor 153 are joined together at output clamp 88 and serially connected between output clamp 170 and junction 179. Resistors 174 and 177 are joined together at a junction 175 and serially connected between output clamp 170 and junction 179. Capacitor 81 and a switch (e.g. MOSFET) 82 are serially connected between output clamp 170 and junction 179. A resistor 162 is connected between bus 102 and junction 179. A diode 180 and a capacitor 183 are joined together at a junction 181 and are serially connected between junction 175 and ground. The contact pins of the integrated circuit (IC) 109 to cooperate with the external circuit include a pin VDD, which is connected to junction 104, which supplies the voltage for driving IC 109. Contact pin RIND receives a signal which is a measure for the current through the inductor 75. The signal is therewith also a measure for the currents through the filaments of the lamp, connected to windings 76 and 77, which are coupled to the inductor 75. The signal received at contact pin RIND is applied to a feedback circuit (not shown) in IC 109 serving to maintain the current through the filaments of the lamp during the preheat cycle at a predetermined value. The integrated circuit comprises at least one contact pin NL coupled to a switch 82 in the external circuit, for placing the switch in a first switching state when at a first logic level and in a second switching state when at a second logic level. The voltage at the VL pin, which is applied to a gate G3 of switch 82, controls when capacitor 81 is placed in parallel with capacitor 80. Pin VL is connected through a resistor 189 to junction 181. Pin VL, when at its second logic level also serves for receiving at least one sensed signal Sig representing an operating condition of the external circuit. The signal sensed reflects the peak voltage of lamp 85. A further pin LI2 is connected through a resistor 168 to output clamp 88. A pin LI1 is connected through a resistor 171 to junction 179. The difference between the currents inputted to pins LI1 and LI2 reflects the sensed current flowing through lamp 85. The integrated circuit 109 comprises a first semiconductor switch SI having a main electrode connected to a voltage VDD corresponding to the first logic level. IC 109 further comprises a second semi-conductor switch S2 having a main electrode connected to a circuit (not shown) for processing the sensed signal Sig. Said main electrode is further connected to a conductor carrying a voltage GΝD corresponding to the second logic level via resistive means R. The semiconductor switches SI, S2 each have a further main electrode connected to the contact pin VL. The semiconductor switches SI, S2 each have a control electrode connected to a common control signal Ctrl. One of the semiconductor switches, i.e. S2 is of an N-channel type, the other, here SI is of a P-channel type. The current flowing out of a CRECT pin into ground through a parallel combination of a resistor 195 and a capacitor 192 reflects the average power of lamp 85 (i.e. the product of lamp current and lamp voltage). A GND pin is connected directly to ground. A pair of pins GI and G2 are connected directly to gates GI and G2 of switches 100 and 112, respectively. The voltage applied to the DIM pin reflects the desired level of illumination. Operation of inverter 60 and drive control circuit 65 is as follows. Initially (i.e. during startup), as capacitor 106 is charged based on the RC time constant of resistor 103 and capacitor 106, switches 100 and 112 are in a nonconducting and a conducting state, respectively. The input current flowing into pin VDD of IC 109 is maintained at a low level (Less than 500 μA) during this startup phase. When the voltage across capacitor 106 exceeds a voltage turn-on threshold (e.g. 12 V), IC 109 enters its operating (oscillating/switching) state with switches 100 and 112 each switching back and forth between their conducting and nonconducting states at a frequency well above the resonant frequency determined by inductor 75 and capacitor 80. IC 109 initially enters a preheat cycle (i.e. preheat state) once inverter 60 begins oscillating. Junction 110 varies between about 0 V and VDC depending on the switching states of switches 100 and 112. Capacitors 115 and 118 serve to slow down the rate of rise and fall of voltage at junction 110 thereby reducing switching losses and the level of EMI generated by inverter 60. Zener diode 121 establishes a pulsating voltage at junction 116 which is applied to capacitor 106 by diode 123. A relatively large operating current of, for example, 10-15 mA supplied to pin VDD of IC 109 results. Capacitor 126 serves to block the D.C. voltage component from being applied to lamp 85. During the preheat cycle the signal Ctrl renders the first semiconductor switch SI conducting and the second semiconductor switch S2 non-conducting. Consequently pin VL assumes the voltage VDD corresponding to the first logic level. As a result switch 82 is set in a first switching state, in casu is turned on. Capacitor 81 is now placed in parallel with capacitor 80. Inductor 75 and the parallel combination of capacitors 80 and 81 form a resonant circuit. During the preheat-cycle lamp 85 is in a non-ignited state, that is, no arc has been established within lamp 85. The operating frequency with which IC 109 drives the inverter 60 is initiated at an initial frequency of for example 100 kHz. The initial frequency may be determined by settings internal or external to IC 109. IC 109 immediately reduces the operating frequency at a rate set internal to the IC. The reduction in frequency continues until the signal received at the RIND pin has attained a value set by the feedback circuit to which this signal is applied. The switching frequency of switches 100 and 112 is regulated so as to maintain the signal at said predetermined value, which results in a relative constant frequency of about 80-85 kHz (defined as the preheat frequency) at junction 110. A relatively constant RMS current flows through inductor 75 which through coupling to windings 76 and 77 permits the filaments (i.e. cathodes) of lamp 85 to be sufficiently preconditioned for subsequent ignition of lamp 85 and to maintain long lamp life. The duration of the preheat cycle is set by capacitor 165, connected to contact pin CP. When the value of capacitor 165 is zero (i.e. open), there is effectively no preheating of the filaments resulting in an instant start operation of lamp 85. At the end of the preheat operation the signal Ctrl renders the first semiconductor switch SI non-conducting and the second semiconductor switch S2 conducting. Consequently pin VL is now connected to the GND contact pin via resistive means R. Pin VL consequently assumes a its second logic level, setting switch 82 in a second switching state, in casu turning it off. Capacitor 81 is no longer connected in parallel to capacitor 80. IC 109 now starts sweeping down from its switching frequency at preheat at a rate set here internal to IC 109 toward an unloaded resonant frequency (i.e. resonant frequency of inductor 75 and capacitor 80 prior to ignition of lamp 85, e.g. 60 kHz). As the switching frequency approaches the resonant frequency, the voltage across lamp 85 rises rapidly (e.g. 600-800 V peak) and is generally sufficient to ignite lamp 85. Once lamp 85 is lit, the current flowing therethrough rises from a few mA to several hundred mA. The current flowing through resistor 153, which is equal to the lamp current, is sensed at pins LI1 and LI2 based on the current differential therebetween as proportioned by resistors 168 and 171, respectively. The voltage of lamp 85, which is scaled by the voltage divider combination of resistors 174 and 177, is detected by diode 180 and capacitor 183 resulting in a D.C. voltage, proportional to the peak lamp voltage, at junction 181. The voltage at junction 181 is converted into a current Sig by resistor 189 flowing into pin VL and conducted via semiconductor switch S2 to a circuit (not shown) for processing the signal represented by this current. Hence contact pin VL, when at its second logic level also serves for receiving at least one sensed signal Sig representing an operating condition of the external circuit. The processing comprises a multiplication inside IC 109 with the differential currents between pins LI1 and LI2 resulting in a rectified A.C. current fed out of pin CRECT into the parallel combination of capacitor 192 and resistor 195. Capacitor 192 and resistor 195 convert the A.C. rectified current into a D.C. voltage which is proportional to the power of lamp 85. The voltage at the CRECT pin is forced equal to the voltage at the DIM pin by a feedback circuit/loop contained within IC 109. Regulation of power consumed by lamp 85 results. The signal provided at the DIM pin, representing the desired level of illumination, can be generated through different methods including, for example, phase angle dimming in which a portion of the phase of the A.C. input line voltage is cut off. These methods convert the cutoff phase angle of the input line voltage into a D.C. signal applied to the DIM pin. The device producing the signal for the DIM pin may provide for a galvanic isolation, for example by a transformer. The voltage at the CRECT pin is zero when lamp 85 ignites. As lamp current builds up, the current generated at the CRECT pin, which is proportional to the product of lamp voltage and lamp current, charges capacitor 192. The switching frequency of inverter 60 decreases or increases until the voltage at the CRECT pin is equal to the voltage at the DIM pin.

Claims: CLAIMS: 1. Power supply for feeding and igniting a discharge lamp (85), comprising an integrated circuit (109) having contact pins to cooperate with an external circuit (60, 70) comprising output clamps (88, 170) for the discharge lamp, the integrated circuit comprising at least one contact pin (VL) coupled to a switch (82) in the external circuit, for placing the switch in a first switching state when at a first logic level and in a second switching state when at a second logic level, characterised in that, said at least one contact pin (VL), when at its second logic level also serves for receiving at least one sensed signal (Sig) representing an operating condition of the external circuit. 2. Power supply according to Claim 1, characterised in that the integrated circuit (109) comprises a first semiconductor switch (SI) having a main electrode connected to a conductor carrying a voltage (VDD) corresponding to the first logic level, a second semi¬ conductor switch (S2) having a main electrode connected to a circuit for processing the sensed signal (Sig) and further connected to a conductor carrying a voltage (GND) corresponding to the second logic level via resistive means (R), the semiconductor switches each having a further main electrode connected to the at least one contact pin (VL), the semiconductor switches each having a control electrode connected to a common control signal (Ctrl), one of the semiconductor switches being of an N-channel type, the other being of a P-channel type. 3. Power supply according to Claim 1 or 2, characterised in that the sensed signal (Sig) represents a condition of the lamp (85). 4. Power supply according to Claim 3, characterised in that said condition is the voltage of the lamp (85). 5. Power supply according to one of the preceding Claims, characterised in that the extemal circuit includes an inverter (60) providing power to an output circuit (70) comprising a combination of an inductor (75) and a capacitor (80), further including an additional component (81) coupled to the combination when the switch (82) is in its first switching state, the combination and additional component being characterized by a first resonant frequency, the additional component being decoupled to the combination when the switch is in its second switching state, the combination being characterized by a second resonant frequency. 6. Power supply according to claim 5, characterised in that the second resonant frequency is higher than the first resonant frequency.

Inventors: GIANNOPOULOS DEMETRI J, VELDMAN PAUL R, GIANNOPOULOS, DEMETRI, J., VELDMAN, PAUL, R.
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1997
Main classification: H05B41
IPC codes: H02M3, H02M7, H05B41