Automatic gain control circuit using pin diode and bidirectional CATV receiver including such circuit

Abstract: An input high frequency signal passes through a PIN diode (D1) having a variable high frequency resistance and is output from an AGC circuit. The PIN diode (D1) is connected so as to be biased forward between an AGC signal level and a fixed voltage level (such as ground potential). A bias resistor (R3) and a coil (L1) are connected in series between a node on the output side of the PIN diode and a node (N4) supplied with the ground potential. More specifically, the resistor and the coil are inserted in parallel between the transmission path for high frequency signals and the ground potential.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to automatic gain control (hereinafter "AGC") circuits for use in a high frequency circuit device such as, television receiver, particularly CATV receiver and videotape recorder, and more particularly, to an AGC circuit using a PIN diode (P type-Intrinsic N type semiconductor diode) and a CATV receiver including such a circuit. Description of the Related Art Other prior art circuits are disclosed in JP0A 371 010 A and US 4 369 414 A. The configuration and operation of a conventional AGC circuit will be described in conjunction with Figs. 6 to 8. Fig. 6 is a block diagram showing the configuration of a tuner portion 2000 in a conventional bidirectional CATV receiver. A terminal 10 is provided with high frequency signal inputs from a broadcasting station or a key station. The band of such high frequency signals is for example in the range from 52MHz to 750MHz. A band pass filter 13 selectively passes only signals in the band of 52MHz to 750MHz among the input high frequency signals. An AGC circuit 44 receives a signal output from band pass filter 13 and controls the gain for the input high frequency signal based on the level of an AGC signal input to the terminal 15 of AGC circuit 44. A high frequency amplifier 16 receives and amplifies the high frequency signal from AGC circuit 44, and outputs the result to a mixer 17. A local oscillator 18 oscillates a signal of a frequency shifted from the broadcasting frequency of a station to chose by the amount of intermediate frequency for output to mixer 17. The intermediate frequency is for example 953MHz. Mixer 17 mixes the signal output from local oscillator 18 with the input high frequency signal. The resulting mixed signal includes various frequency components. A band pass filter 19 limitatively passes signals in the band of for example 953MHz among the signals output from mixer 17, and outputs a first intermediate frequency signal. Then, an intermediate frequency amplifier 20 amplifies the first intermediate frequency signal, and a band pass filter 21 limits the band of the signal to pass. A mixer 22 mixes the first intermediate frequency signal passed through band pass filter 21 and the signal transmitted by a local oscillator 23. The signal produced by mixing in a mixer 22 is received by a band pass filter 24, which in turn limits the band of the signal to pass, and outputs a second intermediate frequency signal of for example 43.5MHz. An intermediate frequency amplifier 25 amplifies the second intermediate frequency signal from band pass filter 24 for output to a terminal 26. Terminal 11 receives a signal output to a broadcasting station or key station from the receiving side (hereinafter "up signal"). The up signal used has a frequency band lower than a signal received from the broadcasting station (hereinafter "down signal") and not higher than 42MHz. Band pass filter 12 limits the band of the up signal to be applied to terminal 11 and outputs the band-limited signal to terminal 10. Note that in the tuner in the bidirectional CATV receiver shown in Fig. 6, the gain of a received signal is controlled by AGC circuit 44. If high frequency amplifier 16 receives a signal in a level higher than specified, a signal output therefrom is distorted, which causes disturbance such as intermodulation and cross modulation. Therefore, AGC circuit 44 is usually provided preceding to high frequency amplifier 16. The AGC signal applied to AGC circuit 44 is output from an AGC control circuit (not shown) which changes the level of the AGC signal to output depending upon the intensity of a signal received from intermediate frequency amplifier 25. Fig. 7 is a circuit diagram showing the configuration of the conventional AGC circuit 44. Herein, diodes D1 to D3 are PIN diodes. Fig. 8 is a graph showing the change of high frequency resistance (rd) as the forward current of PIN diode (If) changes. Now, referring to Figs. 7 to 8, the operation of the conventional AGC circuit 44 will be detailed. Referring to Fig. 7, terminal 1 is provided with a high frequency signal output from band pass filter 13 (see Fig. 6). The gain relative to the input high frequency signal is controlled depending on the gain of the AGC signal as will be described, and a high frequency signal is output from terminal 2. The high frequency signal output from terminal 2 is transmitted to high frequency amplifier 16 shown in Fig. 6. The voltage level of the AGC signal varies for example in the range from 0 to 8V. The AGC signal is generated based on the intensity level of the intermediate frequency output, and the gain of the tuner is feedback-controlled in response to the AGC signal, so that the intensity of intermediate frequency output from the tuner is controlled to be constant. The bias voltage supplied to the connection point of diode D2 and a capacitor C2 is voltage produced by dividing power supply voltage VB by resistors R1 and R2. The potential on the connection point of diode D2 and capacitor C2 is set lower than the potential on the connection point of diode D1 and a bias resistor R3 when the AGC voltage is maximized. When the AGC signal level is at a maximum value, current is passed through a coil L2, diode D1 and bias resistor R3 by the voltage supplied by the AGC signal. The larger the current value, the smaller becomes the high frequency resistance of diode D1 as shown in Fig. 8, and the signal gain of the AGC circuit decreases as a result. Note that the values of resistors R1 and R2 are set so that diodes D2 and D3 are both reversely biased when the AGC signal level is at its maximum value. Then, as the AGC signal level decreases from its maximum value, current passed through diode D1 decreases as well, and the potential at the connection point of diode D1 and resistor R3 is lowered as a result. Current passed through diodes D2 and D3 increases accordingly. The high frequency resistance of diode D1 increases, and the high frequency resistance of diodes D2 and D3 decreases. As a result, the high frequency resistance of PIN diode D1 disposed along the direction of the transmission of high frequency signals increases, while the high frequency resistance of PIN diodes D2 and D3 disposed crossing the direction of transmission decreases, resulting in an increase in the attenuation amount of the AGC circuit. In order to output a signal input from terminal 1 with a maximum gain, in other words with a minimum attenuation, to terminal 2, the resistance value of bias resistor R3 is lowered and the value of current passed through diode D1 is increased for the purpose of reducing the attenuation of the signal and improving the noise figure. Thus, the high frequency resistance of diode D1 decreases. However, if the resistance value of bias resistor R3 is extremely reduced, the impedance of the AGC circuit is lowered as a result, which conversely increases the noise figure. The resistance value of bias resistor R3 should be set taking into account the balance between improvement of the noise figure due to current increase and the increase of the noise figure due to lowered impedance. Therefore, in the AGC circuit as shown in Fig. 7, for example, the resistance value of bias resister R3 is about several kΩ, in other words it should be set to a relatively large value. More specifically, in the conventional AGC circuit as shown in Fig. 7, even for the maximum level of the AGC signal, the high frequency resistance of diode D1 is not sufficiently lowered, and therefore the noise figure increases. In order to restrict the noise figure from increasing as much as possible, the resistance value of bias resistor R3 should be reduced so that more current may be passed through diode D1. However, if the resistance value of bias resistor R3 is too small, the impedance of the circuit conversely decreases, which increases the noise figure. SUMMARY OF THE INVENTION It is desirable to provide an AGC circuit using a PIN diode capable of restricting the noise figure from increasing without lowering the impedance of the circuit itself if the PIN diode disposed along the direction of the transmission of the high frequency signal is biased so that its high frequency resistance is sufficiently lowered. It is also desirable to provide a bidirectional CATV receiver capable of improving the frequency characteristic of the lower side of the receiving frequency band and the noise figure, and restricting data interference and disturbance when a signal is transmitted to a broadcasting station from the receiver side. According to the present invention there is provided and AGC circuit as claimed in claim 1. Therefore the resistance value of the bias resistor for the PIN diode may be advantageously reduced without reducing the impedance of the AGC circuit. Thus, a large amount of current may be passed through the PIN diode, and the noise figure may be improved while increasing the maximum gain of the AGC circuit. Furthermore, a trap is provided on the frequency side lower than the frequency band of a high frequency signal to receive, and the frequency characteristic on the lower side of the receiving frequency band may be improved. Therefore, not only the noise figure may be improved, but also signals in a lower frequency region than the receiving frequency band may be prevented from coming in, thereby restricting data interference and disturbance. In order that the present invention is more readily understood, specific embodiments thereof will now be described with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram schematically showing the configuration of a tuner in a didirectional CATV receiver according to an example of the invention; Fig. 2 is a circuit diagram showing the configuration of an AGC circuit 14 shown in Fig. 1; Fig. 3 is a circuit diagram showing the configuration of an AGC circuit 34 according to an embodiment of the invention; Fig. 4 is a graph showing the relation between the noise figure of AGC circuit 14 according to the example and the noise figure of a conventional AGC circuit 44; Fig. 5 is a graph showing the frequency dependence of the gains of the conventional AGC circuit 44 and AGC circuit 34 according to the embodiment; Fig. 6 is a block diagram schematically showing the configuration of a tuner in a conventional bidirectional CATV receiver; Fig. 7 is a circuit diagram showing the configuration of a conventional AGC circuit; and Fig. 8 is a graph showing the dependence of high frequency resistance on the forward current of a PIN diode. Fig. 1 is a block diagram schematically showing the configuration of a tuner 1000 in a bidirectional CATV receiver according to an example of the invention; The configuration of tuner 1000 is substantially identical to that of conventional tuner 2000 shown in Fig. 6 except for the configuration of AGC circuit 14, like portions are denoted with like reference numerals and the detailed description will not be repeated. Now, as specifically shown in Fig. 1, in tuner 1000 there is provided an AGC control circuit 26 which receives an intermediate frequency signal output from intermediate frequency amplifier 25 and outputs an AGC signal to AGC circuit 14 according to the output intensity level of the intermediate frequency signal. AGC circuit 14 includes a coupling capacitor C1 which receives a high frequency signal from band pass filter 13 at its one end, an inductor L2 for isolation which receives an AGC signal from AGC control circuit 26 at its one end, a gain control portion 142 which receives a high frequency signal from the other end of coupling capacitor C1 and controls a gain relative to the high frequency signal based on the AGC signal received from the other end of inductor L2 for isolation, a bias portion 144 which supplies a prescribed bias voltage to gain control portion 142, and a coupling capacitor C5 having one end to receive a high frequency signal output from gain control portion 142 and the other end connected to high frequency amplifier 16. Fig. 2 is a diagram showing in more detail the configuration of AGC circuit 14 shown in Fig. 1. Coupling capacitor C1 is connected between a node N1 receiving a high frequency signal from band pass filter 13 and a node N3 in gain control portion 142. Node N3 is connected to the one end of inductor L2 for isolation which receives the AGC signal at that other end. Gain control portion 142 includes a PIN diode D1 connected between nodes N3 and N4 so that the direction from node N3 to node N4 corresponds to the forward direction, and a capacitor C2, a PIN diode D2, and a capacitor C3 connected in series between node N3 and a node GND supplied with ground potential. Capacitor C2 has its one end connected to node N3. The connection point of the other end of capacitor C2 and diode D2 is a node N5, and the connection point of one end of capacitor C3 having its other end connected to ground node GND and PIN diode D2 is a node N6. PIN diode D2 is connected so that the direction from node N5 to node N6 corresponds to the forward direction. Gain control portion 142 further includes a PIN diode D3 and a capacitor C4 connected in series between node N4 and ground potential node GND. The connection node of the one end of capacitor C4 having its other end connected with ground node GND and PIN diode D3 is a node N7. PIN diode D3 is connected so that the direction from node N7 to node N4 corresponds to the forward direction. Node N6 and node N7 are connected with each other. Gain control portion 142 further includes an inductor L1 and a bias resistor R3 connected in series between node N4 and ground node GND. There is a coupling capacitor C5 connected between node N4 and node N2 from which an output signal from AGC circuit 14 is output. Bias portion 144 supplies a prescribed potential level to node N5. Bias portion 144 includes resistors R1 and R2 connected in series between power supply potential VB and ground potential GND. The potential level produced by dividing the prescribed potential level based on the ratio of resistance values of resistors R1 and R2 is supplied to node N5. If, for example, the AGC signal is at 6V, the potential level supplied to node N5 is set at about 2V. As the potential level of node N5 is thus set, the voltage drop of PIN diode D2 for example causes the potential level of node N6 (i.e., node N7) to be about 4V. Therefore, for the AGC signal level at about 6V, PIN diodes D2 and D3 are both reversely biased. Unlike the conventional AGC circuit shown in Fig. 7, AGC circuit 14 has inductor L1 and bias resistor R3 connected in series between node N4 and ground potential node GND. In AGC circuit 14, since coil L1 is connected in series with bias resistor R3, the impedance of AGC circuit 14 is kept at a high level. Reducing the resistance value of bias resistor R3 does not reduce the impedance to a high frequency signal. Reducing the resistance value of bias resistor R3 allows current flowing through PIN diode D1 to be increased. As shown in Fig. 8, PIN diode D1 has its high frequency resistance (rD) reduced as the forward current (If) increases. Therefore, in AGC circuit 14, the high frequency resistance along the direction of the transmission of the high frequency signal is reduced, which improves the noise figure of the AGC circuit. In the conventional AGC circuit shown in Fig. 7, reducing the resistance value of bias resistor R3 reduces the impedance of the AGC circuit, which increases the noise figure. Meanwhile, AGC circuit 14 can keep the impedance value at a high level, and therefore the noise figure is not increased. Fig. 4 is a graph showing the frequency dependence of the noise figures of the conventional AGC circuit 44 and AGC circuit 14. Referring to Fig. 4, broken line 51 represents the dependence of the noise figure of the conventional AGC circuit 44 on the frequency, and solid line 52 that of AGC circuit 14. In the entire frequency band from 52MHz to 750MHz of received high frequency signals, AGC circuit 14 has improved noise figure over conventional AGC circuit 44. Note that AGC circuit 14 according to the first embodiment may be employed not only for the tuner in bidirectional CATV receiver 1000 as shown in Fig. 1, but also for a high frequency circuit device such as a general television receiver and a video tape recorder. In those other applications, the noise figure of each device relative to high frequency signals may be advantageously improved. As shown in Fig. 2, in AGC circuit 14, PIN diodes D2 and D3 are arranged in series in the forward direction in the path from node N5 to node N4 via nodes N6 and N7. This is because application of bias voltage on node N5 enables application of D.C. bias on both PIN diodes D2 and D3. The above configuration is an example only, entirely the same effect may be expected as long as, in the path from node N1 to node N2 via nodes N3 and N4, i.e., the transmission path of a high frequency signal, D.C. bias voltage for the PIN diodes connected in parallel to the ground potential changes based on the potential level of the AGC signal. Fig. 3 is a diagram showing the configuration of an AGC circuit 34 in a tuner in a bidirectional CATV receiver according to an embodiment of the invention. The tuner in the bidirectional CATV receiver according to this embodiment is basically identical to the example shown in Fig. 1 except for the configuration of AGC circuit 34. AGC circuit 34 is different from AGC circuit 14 in that a capacitor C6 is connected in parallel to bias resistor R3. The other portions are substantially identical to those of AGC circuit 14 shown in Fig. 2, therefore like portions are denoted with like reference numerals and the detailed description will not be provided. In the AGC circuit 34, since capacitor C6 is connected in parallel to resistor R3, a series trap forms by coil L1 and capacitor C6. The out-of-band rejection characteristic at a frequency f represented as follows may be improved. f=1/{2π(L1·C6) 1/2 } wherein the inductance of coil L1 is L1, and the capacitance of capacitor C6 is C6. Fig. 5 is a graph showing the dependence of the gain of AGC circuit 34 on frequency when such a series trap is additionally provided in comparison with the dependence of the gain of conventional AGC circuit 44 on frequency. Referring to Fig. 5, broken line 55 represents the frequency characteristic of conventional AGC circuit 44. Solid line 56 is the frequency characteristic of the gain of AGC circuit 34. As indicated by arrow RA in Fig. 5, in the receiving frequency band in the range from 52MHz to 750MHz, the insertion loss from tuner input end 10 to the output end of AGC circuit is virtually 0dB (in other words the gain is 1.) In the AGC circuit according to the present embodiment, as in AGC circuit 14 according to the above example, the resistance value of the bias resistor may be reduced without lowering the impedance of the circuit. Therefore, a large amount of current may be passed through PIN diode D1, the high frequency resistance of diode D1 decreases, and therefore the maximum gain of the AGC circuit increases, thereby improving the noise figure. Furthermore, in the AGC circuit 34, capacitor C6 is additionally provided and a trap 57 appears in the frequency characteristic. In tuner 1000 in the bidirectional CATV receiver as shown in Fig. 1, an up signal input from terminal 11 is prevented from coming into high frequency amplifier 16 by the function of trap 57. As a result, data interference or disturbance may be prevented. In addition, according to the change of impedance characteristic caused by capacitor C6 and coil L1, as can be clearly seen in the region denoted by 58 in Fig. 5, the gain in the frequency region on the lower side of receiving frequency band may be restricted from lowering. Thus, the gain is compensated for in the lower side of receiving frequency band, the noise figure may be further improved by using AGC circuit 34. Therefore, in a high frequency circuit device such as CATV receiver, other television receivers, and video tape recorder, use of AGC circuit 34 may provide good demodulated images with reduced noises. In addition, by the use of AGC circuit 34 in a tuner in a bidirectional CATV receiver, signals in a frequency region lower than the receiving frequency band may be prevented from coming into the side of high frequency amplifier in the receiver, and therefore data interference or disturbance can be prevented. More specifically, up signals are blocked before being amplified, and interference by the up signals with signals to receive may be restricted.

Claims: An AGC circuit, comprising: a signal input node (N1) for receiving an externally applied high frequency signal; a signal output node (N2) for outputting a high frequency signal from said AGC circuit; a reference potential node (GND) operable to be supplied with a prescribed potential; a first PIN diode (D1) having one end to receive a high frequency signal from said signal input node (N1) and the other end to output a high frequency signal to be applied to said signal output node (N2); impedance means connected between said other end of said first PIN diode (D1) and said reference potential node (GND); wherein said first PIN diode (D1) is biased in the forward direction based on an externally applied AGC signal, and its high frequency resistance is changed as a current value in the forward direction changes; wherein said impedance means includes a bias resistor (R3), an inductor (L1) and a trap capacitor (C6), wherein said bias resistor (R3) and said inductor (L1) are connected in series, and the trap capacitor (C6) is connected in parallel to the bias resistor (R3), a coupling capacitor (C2) having one end coupled to the one end of said first PIN diode; and a second PIN diode (D2) provided between the other end of the coupling capacitor and the reference potential node so that the forward direction of the second PIN diode corresponds to the direction from the other end of said coupling capacitor to said reference potential node. The AGC circuit as recited in claim 1, wherein: the second PIN diode (D2) is also disposed between the one end of the first PIN diode and said reference potential node so that the D. C. component of a signal is not transmitted and the high frequency component of the signal can be transmitted; the AGC circuit further comprising: a third PIN diode (D3) provided between the other end of said first PIN diode and said reference potential node so that the D.C. component of a signal is not transmitted and the high frequency is component of the signal can be transmitted, said second and third PIN diodes having their high frequency resistance values reduced as they are biased forward; and bias means (144) for supplying such a prescribed bias potential that said second and third PIN diodes are both reversely biased for a maximum value of said AGC signal and that said second and third PIN diodes are both biased forward as the level of said AGC signal decreases. The AGC circuit as recited in claim 1, further comprising: a first capacitor, a second PIN diode and a second capacitor connected in series between the one end of said first PIN diode and said reference potential node; and a third PIN diode and a third capacitor connected in series between said the other end of said first PIN diode and said reference potential node, said second and third capacitors receiving said prescribed potential at their one ends, the anode of said second PIN diode being connected to the other end of said second capacitor, the cathode of said third PIN diode being connected to the other end of said third capacitor, the connection node of said second PIN diode and said second capacitor being connected to the connection node of said third PIN diode and said third capacitor; and bias means for supplying such a prescribed bias potential to the connection node of said first capacitor and said second PIN diode that said second and third PIN diodes are both reversely biased for a maximum value of said AGC signal. A tuner for use in a bi-directional CATV receiver comprising: a signal input/output terminal (10) receiving an externally applied high frequency signal and externally outputting a high frequency signal; a first band pass filter (13) for passing an input signal in a prescribed band applied to said signal input/output terminal; high frequency amplification means (16) for amplifying an output received from said automatic gain control means; sense amplification means (17-25) receiving the output of said high frequency amplification means and extracting an intermediate frequency transmission signal; gain control means (26) outputting said AGC signal based on the output signal level of said sense amplification means; and a second band pass filter (12) for passing an output signal in a prescribed band applied to said signal input/output terminal; and an automatic gain control circuit (34) according to any preceding claim. The tuner as recited in claim 4, wherein said automatic gain control means includes: a second PIN diode proved between said one end of said first PIN diode and said reference potential node so that the D.C. component of the signal can be transmitted; a third PIN diode provided between said the other end of said first PIN diode and said reference potential node so that the D.C. component of a signal is not transmitted and the high frequency component of the signal can be transmitted, said second and third PIN diodes having their high frequency resistance values reduced as they are biased forward; and bias means for supplying such a prescribed bias potential that said second and third PIN diodes are both reversely biased for a maximum value of said AGC signal and that said second and third PIN diodes are both biased forward as the level of said AGC signal decreases.

Inventors: FUKAI SEIICHIROU, MASUDA SHIGETO, FUKAI, SEIICHIROU, MASUDA, SHIGETO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1997
Main classification: H03G1
IPC codes: H03G1, H04N7, H03G3