Memory device with multifunctional terminals

Abstract: The present invention relates to a semiconductor integrated, storage circuit device (MEM) having at least a first enable terminal (CE) for enabling the device (MEM), and a first number of address terminals (A0-A19) for inputting an external address (EA) formed of a corresponding first number of bits (A0-A19). It comprises a plurality (MTX) of data storage elements which are addressable by an internal address (IA) formed of a second number of bits (A0-A20) larger than said first number, and further comprises address storage elements (BF1) which are coupleable with their inputs to said first enable terminal (CE) for storing additional address bits (A20); thus, the internal address (IA) is comprised of the external address (EA) and the additional address bits (A20).

Description: This invention relates to a storage circuit device integrated on a semiconductor and having multi-purpose terminals, according to the preamble of Claim 1. Integrated storage circuit devices, commonly referred to as integrated memory circuits, have long been in use for a wide number of applications in electronics; specifically their information storage capacity is in constant increase. This is one reason why the manufacturers of integrated circuits have recently reported on the occasion of technical meetings, and less frequently actually produced, devices which are designed for storing more than one element of binary information in each of their storage elements; see, for example, the article "A Multilevel-Cell 32Mb Flash Memory", ISSCC95, Session 7, February 1995, Paper TA 7.7. Such devices are commonly referred to as multi-level memories. Increased storage capacity brings about, inter alia, an increase in the number of terminals (pins) on the assembled component, particularly in the number of address-dedicated pins. Even a moderately expanded storage capacity, say a doubled capacity, which would merely involve the addition of one address pin, may instead result in a far larger package having to be used; for example, a standard thirty two pins package may turn out to eventually include forty pins. The article "1.5V K-CMOS-RAM with Only 8 Pins" published by IEEE JOURNAL PF SOLID-STATE CIRCUITS, vol. SD-16, June 1981, No. 3 pages 190-194, New York, USA, MEUSBURGER describes a RAM memory comprising four input terminals DQ1-DQ4 controlled by a control logic controlled by a clocks on a pin ST. The memory input/output is done exclusively by DQ1-DQ4. During the operation, a series of pulse on pin ST controls read and write cycles in which first and a second group of addresses are sequentially read from D1-D4.In other fields of microelectronics, solutions have been adopted which provide multiplexed terminals, that is, if there are eight data-dedicated terminals in a processor, and the internal word length is of thirty two bits, a word may be supplied to the processor in four time-successive steps through these eight terminals. In addition, there are integrated memory circuits of the serial type, i.e. wherein all the binary information relating to a terminal function -- usually data and/or addresses -- goes through the terminal itself in timed succession. This is the case, for instance, with an integrated circuit ST24E16 from SGS-THOMSON MICROELECTRONICS. Such solutions allow the number of terminals to be considerably reduced, but are too elaborate for the aforementioned problem, are fairly complicated and, therefore, occupy a larger semconductor die area. The object of the present invention is to solve such problems. This object is achieved by a memory circuit device having the features defined in Claim 1. Further advantageous aspects of the invention are set forth in the subclaims. The idea on which the present invention is based is one of using an enable terminal of the device to also input those address bits which cannot be accommodated by the address terminals. The invention will be more clearly understood by having reference to the following description and the accompanying dawings, in which: Figure 1 is a block diagram of a memory circuit device according to the invention; Figure 2 is a circuit diagram of control circuitry which can be used in the device of Figure 1; and Figures 3A and 3B show timing diagrams for the signals at the enable terminals, under different conditions of operations of the circuitry in Figure 2. Referring to Figure 1, a semiconductor integrated, storage circuit device MEM according to this invention has at least a first device-enable terminal and a first number of address terminals for inputting an external address EA. In the example of Figure 1, which concerns a memory of the EPROM type, there are a low active chip-enable terminal CE, a low active output-enable terminal OE, twenty address terminals A0-A19 respectively for twenty bits of the external address EA, and of course, a power supply terminal VCC, a ground terminal GND, and a number of, eight in this example, data terminals D0-D7 for outputting and possibly inputting read data or data to be written. A device having such characteristics is, for example, an integrated circuit M27C80 from SGS-THOMSON MICROELECTRONICS. The device of this invention further comprises a plurality of data storage elements addressable by an internal address IA formed of a larger number of bits than the number of bits in the external address EA. In the example, the internal address IA is formed of twenty one bits, denoted A0-A20. It also includes address storage elements BF1 coupleable to the first enable terminal, the terminal CE in the example, for inputting additional address bits to be stored up, the bit A20 in the example. The internal address IA comprises the external address EA and the additional address bits. The address inputs of the matrix MTX are, therefore, connected to the address terminals A0-A19 of the device MEM and to the data output A20 of the (latched) storage buffer BF1. In order for the first enable terminal to be effectively used for two functions, the device includes control circuitry operative to couple this first enable terminal to the address storage elements as a result of a first predetermined recognizable electrical event, such as a voltage or current edge or pulse, at one of the enable terminals. The number of additional bits may be more than one; in this case, a new bit would be stored for each new electrical event, so that the control circuitry is to also record the number of stored bits, which increases its complexity. In order to have the operation of the memory device fully controlled, the control circuitry may be adapted for coupling the first enable terminal to the address storage elements upon the device being turned on or reset back on. Alternatively, the control circuitry may be adapted, upon the device power-on or reset-on, to store predetermined binary information into the address storage elements. To bring the device back to normal operation, and terminate the gathering of the additional address bit, the control circuitry may be adapted for de-coupling the first enable terminal from the address storage elements on the occurrence of a second predetermined recognizable electrical event, either a voltage or current edge or pulse, at one of the enable terminals. It matters to observe that, if the additional address bit is arranged to be gathered by the chip-enable terminal, for example, then the first electrical event may be provided either at the output-enable terminal or the chip-enable terminal, whereas the second electrical event is best provided at the output-enable terminal only, to avoid mistaking it for a change in the data relating to the additional bit. In the embodiment of the control circuitry illustrated in Figure 2, the chip-enable terminal CE and output-enable terminal OE are shown. The terminal OE is connected to the two inputs of a NAND gate G10, respectively directly and through a chain of three inverters G1, G2, G3 which function as an inverting delay element. The output of the gate G10 is connected to a first input of a NOR gate G13; the second input of the gate 13 is connected to the terminal CE. The terminal OE is also connected to the two inputs of a NOR gate G12, respectively directly and through a chain of three inverters G7, G8, G9 acting as an inverting delay element. The terminal CE is connected to the two inputs of a NAND gate G11, respectively direcly and through a chain of three inverters G4, G5, G6 acting as an inverting delay element. The output of the gate G11 is connected to a first input of a NOR gate G14; the second input of the gate G14 is connected to the terminal OE. An OR gate G15 has three inputs respectively connected to the outputs of the gates G13 and G14, and to a power-on-reset signal POR. A great many storage devices is provided with internal circuitry operative to generate a power-on-reset signal each time that the device is turned on or reset back on. Each time that the supply voltage drops below a given threshold for some time, the circuitry generates a positive voltage pulse having a predetermined duration. A flip-flop FF of the SR type has a state output Q, a negated output QN, a set input S connected to the output of the gate G15, and a reset input R connected to the output of the gate G12. The terminal CE is further connected to a first (latched) buffer BF1 with storage feature and to a second buffer BF2 without storage feature. The buffer BF1 has a control input provided to enable, when at a high logic level, connection between the input and output, which control input is connected to the output Q of the flip-flop FF. The buffer BF2 has a control input to enable, when at a high logic level, connection between the input and output, which control input is connected to the output QN of the flip-flop FF. The output of the buffer BF1 corresponds to the the bit A20 of the internal address IA. The output of the buffer BF2 corresponds to an internal enable signal IE, and should be connected to all those locations where the terminal CE would be connected conventionally. Illustrated in Figure 2 is, moreover, a very simple way of implementing the buffer BF2 acting on a negative logic input signal. The data input of the buffer is connected to a first input of an AND gate, the control input of the buffer is connected to a second input of the AND gate, the data output of the buffer is connected to the output of the AND gate. The storage buffer BF1 corresponds, for example, to the cascade connection of a non-storage buffer and a storage element. The circuitry of Figure 2 allows just one additional address bit A20 to be stored into the buffer BF1; this arrangement, while seemingly limited, is in practice highly useful and easy to implement. The data relating to the additional address bit should be delivered on the chip-enable terminal CE at times to be explained. The operation of the circuitry of Figure 2 is readily analyzed. The gates G1, G2, G3, G10, G13 are effective to sense a leading edge of the signal presented at the terminal OE when the signal at the terminal CE is at a low logic level, and to indicate it at the output of the gate G13 by means of a positive pulse whose duration is substantially same as the delay introduced by the gates G1, G2, G3. The gates G4, G5, G6, G11, G14 are effective to sense a leading edge of the signal presented at the terminal CE when the signal at the terminal OE is at a low logic level, and to indicate it at the output of the gate G13 by means of a positive pulse whose duration is substantially same as the delay introduced by the gates G4, G5, G6. The gate G15 is operative to transfer the pulses appearing at its inputs to the set terminal S of the flip-flop. Thus, if a rising edge occurs at the terminals CE or OE, or there has been a power-on, the state of the flip-flop FF is set, so that the output Q will go to a high logic level and the output QN to a logic low. The signal at the terminal CE will then be delivered through the buffer BF1 to the matrix MTX and the additional address bit simultaneously stored into the buffer itself. On the other hand, the buffer BF2 will present at its output a signal at a low logic level, and accordingly, the portions of the storage device as are connected to its output will be enabled. In the alternative, the device could conceivably be kept disabled during the gathering of the additional address bit. The gates G7, G8, G9, G12 are operative to sense a trailing edge of the signal presented at the terminal OE and to indicate it to the output of the gate G12 by means of a positive pulse having a duration equal to the delay introduced by the gates G7, G8, G9. With the output of the gate G12 connected to the reset terminal R of the flip-flop FF, such a pulse will cause the state of this flip-flop to be reset, whereby the output Q goes to a low logic level and the output QN goes to a high logic level. The signal at the terminal CE, therefore, will be delivered through the buffer BF2 to the storage device interior as an internal enable signal IE; at the output of the buffer BF1, the logic state stored in the buffer during the previous step will instead be presented as an additional address bit. Figure 3A shows the case where a leading edge of the signal at the terminal CE precedes a possible leading edge of the signal at the terminal OE. After a given delay R1, the buffer BF1 begins to gather the additional address bit from the terminal CE. This gathering step will end upon the occurrence of a trailing edge of the signal at the terminal OE, after a delay R2. Illustrated in Figure 3B is the instance of a leading edge of the signal at the terminal OE preceding a possible leading edge of the signal at the terminal CE. With a given delay R3, the buffer BF1 begins to gather in the additional address bit. This gatheirng step ends on the occurrence of a trailing edge of the signal at the terminal OE, after a delay R4. The embodiment shown in Figures 2, 3A and 3B has the advantage of being compatible with the existing mode of operation of storage devices which are not arranged for dual utilization of the enable terminals. The same holds for an embodiment similar to the above, but having the functions of the chip-enable and output-enable terminals reversed. With slight obvious modifications from the illustrated construction, two similar embodiments can be arrived at for the instance of "normal" rather than "negated" logic enable signals. Throughout the above examples, the gathering of the additional address bit(s) is performed in an asynchronous manner: there are a gather start event and a gather end event. The gathering could be arranged to occur sinchronously, however, although at the expense of slightly increased complexity due to well-known problems as associate with synchronous transmissions. In this case, the device of this invention would comprise a control circuitry adapted to trigger a clocked transfer of a number of binary information elements corresponding to the number of additional bits from a selected enable terminal to the address storage elements in consequence of a predetermined recognizable electrical event, such as either a voltage or a current edge or pulse, at one of the enable terminals. As previsouly discussed, the present invention can be useful where the storage capacity is to be increased two- or four-folds, for example, but the same package is to be used, or pin-to-pin compatibility is to be retained. This may be the case in moving from a conventional two-level storage device to a multi-level storage device. Another application for which the present invention is specially useful concerns storage devices which have two modes of operation, e.g. a two-level mode and a four-level mode, according to the acceptable error rate for the application, or to the type of data to be stored. In this case, it is preferable for the number of additional bits to be equal to the logarithm to the base two of the largest number of binary information elements that each storage element in the plurality MTX can store.

Claims: A semiconductor integrated storage circuit device (MEM) having a first enable terminal (CE) for enabling said device (MEM), a second enable terminal (OE) for enabling said device (MEM), and having a first number of address terminals (A0-A19) for inputting an external address (EA) formed of a corresponding first number of bits (A0-A19), comprising a plurality (MTX) of data storage elements characterised in that said plurality (MTX) of data storage elements are addressable by means of an internal address (IA) formed of a second number of bits (A0-A20), larger than said first number, and further comprising at least one address storage element (BF1) having an input terminal coupleable to said first enable terminal (CE) for storing at least one additional address bit (A20) on the occurrence of a first predetermined electrical event at one of the enable terminals (CE,OE), and said first enable terminal (CE) being de-coupled from said at least one address storage element (BF1) upon the occurrence of a second predetermined electrical event at the second enable terminal (OE), and wherein said internal address (IA) comprises said external address (EA) and said additional address bit (A20). A device according to Claim 1, wherein said control circuitry is effective to couple said first enable terminal (CE) to said address storage elements (BF1) as the device (MEM) is turned on or reset on. A device according to Claim 1, wherein said control circuitry is effective to store predetermined binary information into said address storage elements (BF1) as the device (MEM) is turned on or reset on. A device according to Claim 1, wherein the number of said additional bits (A20) is one. A device according to Claim 1, wherein said first enable terminal (CE) is the chip-enable terminal. A device according to any previous claims, wherein said control circuitry is effective to sense said first event on either an chip-enable terminal (CE) or an output-enable terminal (OE). A device according to any previous claims, wherein said control circuitry is effective to sense said second event on the output-enable terminal. A device according to Claim 1, comprising control circuit for triggering a clocked transfer of a number of binary information elements corresponding to the number of said additional bits (A20) to said address storage elements (BF1) on the occurrence of a predetermined electrical event at one of the enable terminals (CE,OE). A device according to Claim 1, being of a suitable type to store a third number, greater than one, of binary information elements into each of said plurality (MTX) of data storage elements. A device according to Claim 9, wherein the number of additional bits is the logarithm to the base two of said third number.

Inventors: ROLANDI PAOLO, ROLANDI, PAOLO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1997
Main classification: G11C11
IPC codes: G11C5