Photoelectric conversion device using charge skimming

Abstract: This invention provides an element having a skimming charge transfer function in an X-Y address type photoelectric conversion device using, e.g., a CMOS sensor, and a photoelectric conversion device, which accumulates photoelectric signal charges produced by a photoelectric conversion element (1) in a control electrode (gate) of a MOS transistor (2) so as to obtain a signal with a high S/N ratio by removing signal components produced by background radiation without using any CCD as an accumulation means of skimming charges, has a skimming electrode (12) for transferring skimming charges of those produced by the photoelectric conversion element (1), an n + -type region (31) for accumulating the transferred skimming charges, a MOS transistor (2) for reading out potential changes caused by the skimming charges, and a circuit (51, 52) for automatically controlling the amount of skimming charges to be transferred.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a photoelectric conversion device, for example, to one-dimensional or two-dimensional photoelectric conversion devices for reading images in a video camera, X-ray imaging apparatus, infrared ray imaging apparatus, and the like and, more particularly, to a photoelectric conversion device using a skimming charge transfer scheme. Related Background Art Conventionally, CCDs are popularly used as imaging devices of video cameras, digital cameras, and the like, and such image reading device uses a "charge skimming transfer scheme" disclosed in, e.g., IEEE trans. Electron. vol. ED-29, p. 3, 1982 and Japanese Patent Publication No. 7-48826. Fig. 13 shows an infrared ray imaging apparatus using the conventional charge skimming transfer scheme described in Japanese Patent Publication No. 7-48826. Figs. 12A and 12B show changes in charge amount before and after charge skimming transfer, and Figs. 11A to 11C show the input circuit of a charge skimming transfer type infrared ray imaging element. Figs. 11A to 11C and Fig. 13 illustrate a photodiode 101, a silicon CCD 102, infrared rays 104, an output circuit 105, an input gate electrode 110, an accumulation electrode 111, a skimming electrode 112, a CCD electrode 113, an overflow drain 114, an overflow electrode 115, and a skimming voltage input terminal 119. In Figs. 12A and 12B, charges 116 are produced due to background radiation, charges 117 are ascribed to radiation from a signal source, and charges are skimmed at a skimming level 118. The operation of the charge skimming transfer type infrared ray imaging element with the above arrangement will be described below with reference to the drawings. (1) As shown in Fig. 11A, infrared rays 104 are converted into photocurrents by the photodiode 101, and the photocurrents are input to and accumulated in a portion beneath the accumulation electrode 111 via the input gate electrode 110. (2) Upon completion of accumulation, as shown in Fig. 11B, a pulse signal is applied to the skimming electrode 112 to change the height of the potential well to transfer some accumulated charges to a portion underneath the CCD electrode 113. The amount of charges to be transferred is controlled by the pulse signal (to be referred to as a skimming voltage hereinafter) to be applied to the skimming electrode 112. (3) Thereafter, as shown in Fig. 11C, charges remaining in the portion beneath the accumulation electrode 111 are ejected to the overflow drain 114 via the overflow electrode 115. When charge skimming transfer is performed, as described above, since DC components 116 produced by the background radiation can be removed, as shown in Figs. 12A and 12B, contrast can be emphasized, and the amount of charges to be transferred to the portion beneath the CCD electrode 113 can be reduced. Charges transferred to the portion below the CCD electrode 113 are sequentially transferred by the CCD 102 in the same manner as in a case wherein the charge skimming transfer scheme is not adopted, and are output to an external circuit via the output circuit 105. As described above, in the conventional photoelectric conversion device, when the number of photons of background radiation is extremely larger than the number of photons radiated by the signal source, the obtained signal has low contrast, and such problem cannot be solved by merely extending the accumulation time of the silicon CCD. In the above-mentioned prior art, this problem is solved by performing skimming charge transfer. However, since the skimming voltage is calculated and generated by an external circuit on the basis of the signal voltages of the respective pixels, other problems such as a long processing time, high cost of the entire system, and the like are posed. Other examples of photoelectric conversion devices are known from US-A-5146302 and EP-A-0371685. Each device as disclosed therein is comprised as set out in the preamble of claim 1 of the claims appended hereto. Notably in each of these, charge is transferred to and received by a CCD. The photoelectric conversion device of the present invention is intended to obtain a signal with a high S/N ratio by removing signal components produced by background radiation without using any CCD as a skimming charge accumulation means. As set out in claim 1 of the claims appended hereto, the photoelectric conversion device of the present invention is characterised in that: each respective receiving means comprises a respective amplifier transistor, having a non-destructively-amplifying function, arranged to receive the charge, transferred by said electrode, at a control electrode area, the voltage potential of which is dependant on the respective amount of charge transferred thereto, and the control means controls each electrode according to a signal output from a respective amplifier transistor. In the following embodiments of the present invention, when a MOS transistor is used as a charge receiving means in place of a CCD which is used in the conventional device, a photoelectric conversion device which can remove background signal components as in the conventional device, and can still provide a signal having a high S/N ratio and, hence, high contrast can be realised. Since the skimming voltage can be automatically controlled in real time, an optimal skimming charge amount can be easily obtained. Other features of the present invention will become apparent from the following description of the embodiments taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A to 1C are circuit diagrams showing a circuit for one pixel and a skimming charge transfer scheme according to the first embodiment of the present invention; Fig. 2 is a circuit diagram of the first embodiment of the present invention; Fig. 3 is a timing chart of the first embodiment of the present invention; Fig. 4 is a flow chart showing the operation according to the first embodiment of the present invention; Fig. 5 is a circuit diagram of an automatic skimming voltage control circuit according to the first embodiment of the present invention; Figs. 6A and 6B are respectively a circuit diagram and a timing chart of a maximum value detection circuit for a pixel signal according to the first embodiment of the present invention; Fig. 7 is a circuit diagram of the second embodiment of the present invention; Fig. 8 is a circuit diagram of the third embodiment of the present invention; Fig. 9 is a circuit diagram of a circuit for one pixel according to the fourth embodiment of the present invention; Fig. 10 is a circuit diagram of a circuit for one pixel according to the fifth embodiment of the present invention; Figs. 11A to 11C are circuit diagrams for explaining the conventional charge skimming scheme; Figs. 12A and 12B are graphs showing the relationship between the skimming operation and the charge amount; and Fig. 13 is a circuit diagram for explaining the conventional charge skimming scheme. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described in more detail hereinafter with reference to the accompanying drawings. Figs. 1A to 1C show the sectional structure and peripheral circuits of a photoelectric conversion element according to the first embodiment of the present invention, and also illustrate the charge skimming transfer processes. Referring to Figs. 1A to 1C, a photoelectric conversion device comprises a photodiode 1, which is illustrated as a circuit element on the circuit diagram for the sake of simplicity (however, an actual photodiode 1 is constituted by the p-n junction between a p-type semiconductor substrate and an n + -type diffusion layer 30; the same applies to the photodiode shown in the other figures). The device also comprises a driver MOSFET 2 for outputting a signal. The drain terminal of the MOSFET 2 is connected to an output line via a selection switch 13, and a resistive load or constant current load (not shown) is inserted in the output line. The load element and the driver MOSFET 2 constitute an amplifier. The device further comprises an input gate electrode 10, an accumulation electrode 11, a skimming electrode 12, and a MOS switch 16 for resetting the floating gate of the MOSFET 2. Such photoelectric conversion device accumulates photoelectric signal charges produced by a photoelectric conversion means 1 in the control electrode (gate) of a MOS transistor 2, and comprises: a skimming electrode 12 serving as means for transferring skimming charges of those produced by the photoelectric conversion means 1; an n + -type region 31 serving as means for accumulating the transferred skimming charges; a MOS transistor 2 serving as means for reading out potential changes caused by the skimming charges; and means (to be described later with reference to Fig. 2) for automatically controlling the amount of skimming charges to be transferred. The charge skimming transfer operation of this embodiment will be described below with reference to the drawings. (1) As shown in Fig. 1A, light 4 is converted into photocurrents by the photodiode 1 as the photoelectric conversion means, and the photocurrents are input to and accumulated in a portion beneath the accumulation electrode 11 via the input gate electrode 10. (2) Upon completion of accumulation, as shown in Fig. 1B, a pulse signal is applied to the skimming electrode 12 to change the height of the potential well, and some accumulated charges (skimming charges) are transferred to the n + -type diffusion layer 31 connected to the floating gate of the MOS transistor 2. The amount of charges to be transferred is controlled by the pulse signal (skimming voltage) to be applied to the skimming electrode 12. (3) Thereafter, as shown in Fig. 1C, residual charges underneath the accumulation electrode 11 are ejected to the overflow drain 14 via the overflow electrode 15. When charge skimming transfer is performed, as described above, since DC components 116 produced by the background radiation can be removed, as shown in Figs. 12A and 12B, contrast can be emphasized, and a signal with a high S/N ratio can be obtained. By appropriately repeating the operations (1) to (3), the background signal components can be removed, and a signal with a higher S/N ratio can be obtained. In this embodiment, since signal charges can be non-destructively read out, the skimming amount can be automatically optimized by reading signals during the accumulation period, and setting the skimming voltage based on, e.g., a voltage corresponding to the maximum signal of skimming charges of all the pixels. In pixels having the photoelectric conversion means, signals may be read out in units of pixel blocks, and the skimming amount can be controlled by a skimming voltage corresponding to the minimum voltage of the readout signals in units of pixel blocks. Such control in units of clocks can be realized by controlling scanning circuits for scanning the respective pixels to locally scan the pixels. Fig. 2 is a schematic circuit diagram showing a MOS linear sensor as an example of the photoelectric conversion device of the first embodiment described above with reference to Figs. 1A to 1C. Fig. 2 shows circuits for four pixels, and a dotted line portion G1 as a peripheral circuit for one pixel will be explained below. Note that the selection switch 13 in Figs. 1A to 1C is not shown in Fig. 2. In Fig. 2, the circuit comprises a photodiode 1 serving as a photoelectric conversion means, which is illustrated as a circuit element on the circuit diagram for the sake of simplicity (however, an actual photodiode 1 is constituted by the p-n junction between a p-type semiconductor substrate and an n + -type diffusion layer 30; the same applies to the photodiode shown in the other figures). The circuit also comprises a driver MOSFET 2 for outputting a signal. The drain terminal of the MOSFET 2 is connected to an output line, and a MOSFET 17 serving as a load resistor is inserted in the output line. The load element 17 and the driver MOSFET 2 constitute a source-follower amplifier for each pixel. The circuit further comprises an input gate electrode 10, an accumulation electrode 11, a skimming electrode 12, and a MOS switch 16 for resetting the floating gate of the MOSFET 2. The circuit further comprises an overflow drain 14 and a MOSFET 15 serving as an overflow control switch. Moreover, the sensor comprises an automatic skimming voltage control circuit 51, and a circuit 52 for detecting the maximum value of skimming charges of each pixel. The circuits 51 and 52 as means for automatically controlling the skimming charge amount detect the maximum signal of skimming charges, and compare it with a proper signal level. When the maximum signal of the skimming charges is smaller than the proper signal level, the means controls the skimming voltage to increase the amount of skimming charges; otherwise, the means controls the skimming voltage to decrease the amount of skimming charges. In Fig. 2, the skimming electrode 12 serves as means for transferring skimming charges of those produced by the photoelectric conversion means, the automatic skimming voltage control circuit 51 and the maximum value detection circuit 52 for detecting the maximum value of skimming charges of each pixel serve as means for controlling the amount of skimming charges to be transferred, an n + -type region 31 serves as means for accumulating the transferred skimming charges, and the MOS switch 15 serves as means for resetting charges which remain after the skimming charges of those produced by the photoelectric conversion means are transferred. Fig. 3 is a timing chart of the circuit in Fig. 2, and Fig. 4 is a flow chart showing the control scheme and operation of the circuit in Fig. 2. The operation of this embodiment will be briefly described below with reference to Figs. 3 and 4. At time t 0 , pulses  R ,  T ,  S and  SKM are applied to reset the residual charges in the pixels. Upon completion of resetting (t 1 ), accumulation of photoelectric charges is started. At time t 2 , when pulses  T and  S are applied, and a pulse  SKM of an initial voltage is applied to the skimming electrodes, skimming charges corresponding to the applied voltage are read out to the floating gates of the transistors 2 of the respective pixels. At this time, when pulses  L and  TR are also applied, the source-follower amplifiers of the respective pixels operate to read out pixel signals to capacitors C T1 to C T4 . Thereafter, a scanning circuit 21 is operated from times t 3 to t 4 to serially read out the signals from the capacitors C T1 to C T4 to an output terminal 53, and the circuit block 52 obtains, e.g., the maximum value of these signals. The circuit block 51 generates an optimal skimming voltage  SKM in accordance with the obtained maximum signal amount, and applies it to the respective pixel at time t 5 to perform skimming transfer and signal read again. By repeating the series of operations described above, an optimal skimming signal can be obtained. In the above description, after skimming transfer, the pixels continue charge accumulation without resetting the accumulation electrodes. Alternatively, the accumulation electrode and pixel portions may be reset in each scan and thereafter, accumulation may be resumed. Fig. 5 shows an example of an automatic setting circuit of a skimming voltage during the accumulation period, which is denoted by 51 in Fig. 2. In this circuit, an input signal (the signal output from a unit 52 in Fig. 2) is inverted and amplified by an inverting amplifier 61, and its output voltage is reflected in the amplitude of the pulse  SKM . More specifically, as the input signal is smaller, the amplitude of the pulse  SKM becomes larger to automatically increase the amount of skimming charges to be transferred. Figs. 6A and 6B show an example of a circuit for detecting the maximum value of skimming charge signals of the respective pixels, which circuit is denoted by 52 in Fig. 2. Fig. 6A is a circuit diagram, and Fig. 6B is a timing chart thereof. In the circuit operation, a pulse  INIT changes to Hi-level to turn on a MOS switch 71, thereby resetting a capacitor 72. Thereafter, every time a signal is input, the input signal is compared with a voltage in the capacitor 72. If the input signal is lower than the voltage in the capacitor 72, a pulse OUT changes to V cc level shown in Fig. 6B; otherwise, the pulse OUT changes to GND level. As a consequence, a PMOS 73 is turned on, and the input signal is written in the capacitor 72. Upon completion of a series of operations, a pulse  READ changes to high-level to turn on a MOS switch 74 so as to form a feedback loop, thereby outputting the voltage in the capacitor 72. Fig. 7 is a circuit diagram showing the second embodiment, which is substantially the same as the first embodiment, except for means for detecting a maximum value of pixels. In Fig. 7, an NPN transistor 23 is inserted in the output line of each pixel, and its emitter is commonly connected. With this arrangement, when signals are read out from the respective pixels to capacitors C T1 to C T4 , the maximum value of the signals can be immediately obtained. In this case, a circuit 52' may be a simple buffer amplifier. Fig. 8 shows the third embodiment, which is substantially the same as the first embodiment, except that the means for detecting the maximum signal of pixels is replaced by means for detecting background light. In Fig. 8, for example, a pixel G4 enclosed in the dotted line serves as a dummy pixel, which is arranged at a position where no signal light is incident, and the voltage of background light is obtained based on the output from this pixel, thereby controlling the skimming voltage. Fig. 9 is a circuit diagram of a photoelectric conversion element according to the fourth embodiment of the present invention. This embodiment is substantially the same as the first embodiment, except that the output amplifier in the device described in the first embodiment is replaced by an NMOS inversion circuit. With this arrangement, the gain can be set to be 1 or more. Note that the same reference numerals in Fig. 9 denote the same parts as those in Figs. 1A to 1C, and a detailed description thereof will be omitted. Fig. 10 is a circuit diagram of a photoelectric conversion element according to the fifth embodiment of the present invention. In this embodiment, instead of arranging all of a skimming electrode, input gate electrode and accumulation electrode, only a skimming electrode 12 is provided and it is arranged to also play the roles of the input gate electrode and the accumulation electrode of the above-mentioned embodiment. After skimming charges of those produced by a photodiode are transferred to an n + -type region 31, the residual charges are ejected by a MOS switch 15 arranged in an n + -type region 30. The amount of skimming charges is controlled by the skimming electrode 12 in the same manner as in the above embodiment. In the above embodiments, the photoelectric conversion device which reads out a photoelectric signal by transferring it to the gate electrode of the MOS transistor has been described. The present invention can also be applied to other photoelectric conversion devices such as a FGA (floating gate array device), an AMI (amplified MOS intelligent imager), a BASIS (base-stored image sensor), and the like. In the above embodiments, a one-dimensional photoelectric conversion device has been exemplified. However, the same effect can be obtained even when the present invention is applied to a two-dimensional photoelectric conversion device. In the above embodiments, n-type layers are used as the diffusion layers 30 and 31. Alternatively, an n-type semiconductor substrate and p-type diffusion layers may be used. As described above, since, for example, an MOS transistor or the like is used as the accumulation means of skimming charges in place of a CCD which is used in the conventional device, a charge skimming transfer type photoelectric conversion device which can remove background signal components as in the conventional device, and can yet provide a signal with a high S/N ratio and, hence, high contrast, can be realized. Also, since the skimming voltage can be automatically controlled in real time, an optimal skimming charge amount can be obtained. Many widely different embodiments of the present invention may be constructed without departing from the scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.

Claims: A photoelectric conversion device comprising: a plurality of pixels (1,2,12), each of said pixels including respective photoelectric conversion means (1), an electrode (12) adapted to transfer skimming charge produced by said photoelectric conversion means, and respective receiving means (31,2) for accumulating the charge transferred by said electrode; and control means (51-54) for controlling each said electrode (12) to change the respective amount of skimming charge transferred from each said photoelectric conversion means (1) to each said respective receiving means (2); characterised in that : each respective receiving means comprises a respective amplifier transistor (2), having a non-destructively-amplifying function, arranged to receive the skimmin charge, transferred by said electrode (12), at a control electrode area (31), the voltage potential of which is dependant on the respective amount of charge transferred thereto, and said control means (51-54) controls each electrode (12) according to a signal output from the respective amplifier transistor (2). A device according to claim 1, wherein said control means (51-54) includes a maximum value detection circuit (52) adapted to detect a maximum signal of the charges output from the amplifying transistors (2) of said plurality of pixels, a comparison circuit (61) adapted to compare the maximum signal with an appropriate signal level, and a voltage output circuit (61-65) adapted to output different voltage levels to said electrode (12) so as to increase and decrease according to output of said comparison circuit the amount of the charges transferred from said photoelectric conversion means (1) to said amplifying transistor (2). A device according to claim 1, wherein said control means (51-54) controls the amount of the charges transferred from said photoelectric conversion means (1) to said amplifying transistor (2), on a unit basis of a block which includes a plurality of pixels. A device according to claim 1, wherein said amplifying transistor (2) is a MOS transistor part of an inverting amplifier circuit. A device according to claim 1, wherein said control means controls said electrode (12) by changing pulse amplitude.

Inventors: UENO ISAMU, UENO, ISAMU
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1997
Main classification: H04N3
IPC codes: H01L27, H04N3, H04N5