Interpolating digital to analog converter architecture for improved spurious signal suppression

Abstract: A digital-to-analog conversion method and interpolating digital-to-analog converter (20) for a data modulation system which reduces the spurious energy content of the output signal by an order of magnitude to thereby permit use of a less complex reconstruction filter to smooth the analog output. The process is a two step charge redistribution with feedback to interpolate between samples. DC offset is minimized by using double sampling techniques which permit a fully held signal between interpolation samples. A first conversion stage (22) converts the first n bits of an N bit data signal received at an input rate to a first output value, and a second conversion stage (26) converts the remainder of the N bits and combines signals from the two conversion stages to provide a combined output (28) to an interpolation stage (30) which provides an interpolated output (32) at an interpolation output rate. A feedback circuit (34) provides the interpolated output to an input of the second conversion stage (26).

Description: The present invention relates to digital to analog conversion method and an interpolating digital to analog converter with improved spurious energy rejection. Systems for modulating digital data desirably suppress spurious energy in order to facilitate modulation to a higher frequency within a finite transmission bandwidth. Typically an input data stream is conditioned (or shaped) with a pre-modulation baseband processor 10 in Figure 1. Conventional digital interpolation techniques ( e . g ., finite impulse response (FIR) filter 12) generate a sequence of digital words at an interpolation rate which represent the amplitude versus time relationship of the pulse shape. A digital to analog converter (DAC) 14 running at the interpolation rate approximates the pulse shape in discrete time form. Conditioning of the pulse shape is completed in a continuous time reconstruction filter 16 where the discrete time nature of the pulse is smoothed to suppress spurious energy which occurs at the update rate of the DAC 14. The reconstruction filter 16 should be of a high order (typically an order greater than four) for high performance systems. It is also desirable that such filters can be manufactured in a monolithic integrated circuit. However, high order reconstruction filters are very difficult to manufacture in a monolithic integrated circuit (if it can be done at all), and an alternative approach is desired. The approach proposed herein is to reduce the need for a high order reconstruction filter by improving the spurious energy rejection in the DAC which precedes it. For example, if the spurious energy occurring at the DAC output rate is reduced by one order of magnitude compared to the prior art converter, the order of the reconstruction filter may be reduced from at least four to one. The specification of U.S. Patent 5,327,092 suggests providing two switched-capacitor filter stages, thereby reducing the order of a post-filter so that it may be more easily manufactured in a monolithic integrated circuit. However, the circuit therein is still cumbersome, does not take into account a dc offset which may build up during operation, and may be further improved. The present invention DAC is based on charge redistribution, and use a cascaded design to reduce the need for precisely matched capacitors and resistors (see, for example, "High-resolution switched-capacitor D/A converter" by R. Gregorian, Microelectronic Journal , Vol. 12, No. 2, 1981.) However, the cascaded design does not afford the desired reduction of spurious energy and further improvements are needed. The present invention includes a switched-capacitor interpolation filter as an integral component of the DAC. The filter output is fed back to a conversion stage of the DAC to smooth the analog output and thereby reduce the spurious energy in the output. While switched-capacitor interpolation filters are known, there has been no suggestion to integrate them into a DAC. The present invention includes a digital to analog conversion circuit as defined in claim 1 and a method of reducing spurious energy in an analog signal which is output from a digital to analog converter (DAC) as defined in claim 6. The invention will now be described, by way of example, with references to the accompanying drawings in which: Figure 1 is block diagram of a pre-modulation baseband processor of the prior art in which the present invention finds application, Figure 2 is a block diagram of an embodiment of the present invention, Figure 3 is a partial circuit and partial block diagram of a embodiment of the present invention, Figure 4 is a circuit diagram of an embodiment of the capacitor array of Figure 3, Figure 5 is a partial circuit diagram illustrating activation of switches d1, d2, ..., dn in the capacitor array of Figure 4, and Figure 6 is a graph illustrating examples of DAC output with (curve B) and without (curve A) the integrated interpolating filter of the present invention. The present invention recognizes that digital-to-analog conversion is a discrete time process, and increases the output rate over the input rate by interpolating the amplitude values. The interpolation herein allows the invention to reduce the spurious energy content of the output signal by an order of magnitude to thereby permit use of a less complex reconstruction filter. The process may be described as a two step charge redistribution with feedback to interpolate between samples. DC offset is minimized by using double sampling techniques which permit a fully held signal between interpolation samples. Figure 2 shows an embodiment of the interpolating digital-to-analog converter 20 of the present invention may include a first conversion stage 22 for converting the first n bits ( e . g ., the n least significant bits) of an N bit data signal received at an input rate to a first output value in line 24, a second conversion stage 26 for combining the remainder of the N bits ( e . g ., the most significant bits) in the data signal with the first output value to provide an amplitude value output in line 28, an interpolation stage 30 integral with second conversion stage 26 for providing an interpolated amplitude output at node 32 at an interpolation output rate which is a multiple of the input rate, and a feedback circuit 34 for feeding back the interpolated amplitude output from interpolation stage 30 to second conversion stage 26. Figures 3 - 5 illustrate first conversion stage 22 that may include an offset compensated amplifier connected to a stable reference. First stage 22 includes a first capacitor array 40 (for which see Figure 4) with n parallel paths 42 with capacitors C therein which are switched into and out of operation by switches d1, d2,...dn which are respectively responsive to the first n data bits b1, b2, ..., bn gated with clock 1. Figure 5 illustrates the use of AND gates to provide signals a1, a2, ..., an for operation of switches d1, d2,...dn. In Figure 4, the prefix to C indicates a multiple of the unit capacitance C in a preferred embodiment, although other values may be used. Switches 44 discharge capacitors C during one of the time periods 1 and 2 which alternate at the sampling frequency (the time period shown next to a switch indicates a preferred time period, although the indicated time periods may be swapped in another embodiment.) The sampling frequency is greater than the digital data update frequency, and the interpolation factor is the ratio of the sampling frequency to the data update frequency. For example, an update frequency of 1.024 MHz and a sampling frequency of 5.12 MHz yields an interpolation factor of 5. The output of capacitor array 40 is provided as an input to a non-inverting terminal (-) of a first operational amplifier 46. A switched-capacitor circuit 48 may be provided for amplifier 46. The output of amplifier 46 may be provided as the first output value in line 24. Second conversion stage 26 includes a second capacitor array 50 with (N-n) parallel paths, each with a capacitor therein, which are switched responsive to the remainder of the N data bits. Second capacitor array 50 may be identical tc first array 40 shown in Figure 4, except for the data bits to which the switches d1,...dn respond ( i . e ., bn + 1, bn + 2,...bN gated by clock 2) and the time period in which switches 44 are closed (during 1 instead of 2.) The output of capacitor array 50 is connected to node 51 which is a summing node for the first stage least significant bit conversion network ( i . e ., for bits 1 to n) through capacitor E in line 24, and capacitor array 50, which is the conversion network for the most significant bits ( i . e ., n + 1 to N). A switched-capacitor circuit 54 may be provided to hold the charge transferred from the summing operation. The resulting output of amplifier 52 may be provided in output line 28 prior to interpolation stage 30. Interpolation stage 30 includes a third operational amplifier 56 with a switched-capacitor circuit 58. Second stage 26 and interpolation stage 30 are desirably integrated into a single component in a monolithic integrated circuit DAC. The combination of the two stages reduces the number of components and reduces the necessary silicon area. Integral stages 26 and 30 also includes a feedback circuit 34 with a feedback capacitor F which introduces a complex pole so that DAC stage 26 and interpolation stage 30 together act as a second order filter 60. Hence, design of the desired interpolation response is reduced to the design of a simple second order filter. The resulting interpolated output is available at node 32. Connections between the stages may include switched-capacitors to ensure continuity therebetween, such as switched-capacitor E in line 24 between first stage 22 and second stage 26, and switched-capacitor D in line 28 between second stage 26 and interpolation stage 30. The embodiment of Figure 3 builds on the circuitry of the prior art DAC. However, the second stage of the prior art DAC is replaced in the present invention by filter network 60 (stages 26 and 30 and feedback circuit 34) which improves rejection of spurious signals. In the prior art, the first conversion stage is typically followed by an identical second conversion stage which generates the most significant bits portion of the analog signal. For a conventional 8 bit DAC, the first stage would sum into a second stage with an attenuation of 16 to realize the least significant bits portion of the signal. The embodiment of Figure 3 replaces the conventional second stage with a filter designed to eliminate offset effects while realizing a second order transfer function. This filter network, 60, is incorporated directly into the DAC and is clocked at a higher speed (five times the rate at which the digital word is being updated in one embodiment) thus smoothing the DAC output. Further, the offset correction of the second conversion stage 26 effectively removes dc offset at the output from operational amplifier 56. The filter circuitry herein generates an output offset voltage V OFFOUT 56 at operational amplifier 56 which is dependent on the input offset voltage V OFFSET 52 of operational amplifier 52: V OFFOUT 56 = -(F/G + E/G) V OFFSET 52 The voltage offset of operational amplifier 52 may be set to zero by the correlated double sampling technique illustrated in Figure 3. The offset of operational amplifier 52 is sampled during one phase ( e . g ., 2) and removed during the other phase (1). The resulting output has a second order transfer function with the offset removed. An example of the five times interpolation is illustrated in Figure 6 in which curve A is an output from a DAC without the integrated interpolating filter of the present invention and curve B is an output from a DAC incorporating an embodiment of the present invention. In this example, the DAC update rate was 1.024MHz and the interpolation rate was 5.12MHz. The interpolating DAC of this example provides no more than 0.2dB loss at 100KHz while giving 20dB extra attenuation at the spurs of 1.024MHz. This gives nearly 37dB of spurious rejection, 20dB over that achievable in the prior art. The present invention may provide any reasonable interpolation factor by varying capacitor values in consideration of the clock frequencies. Selection of appropriate capacitances of capacitors A, B, D and F set the second order filter transfer function and hence the interpolation factor so as to reduce the spurious energy in the output by an order of magnitude compared to the spurious energy in outputs from simple prior art converters, thereby permitting a single order reconstruction filter following the DAC. As is apparent, a somewhat similar result may be achieved by adding a filter to the cascaded DAC of the Gregorian article. In contrast, the present invention integrates the filter into the DAC and adds capacitors A, B, D, and F and operational amplifier 56. The mere addition of a filter to the Gregorian circuit would require these additions and substantially more. Thus, the present invention improves produceability and spurious energy rejection while using less silicon area than would be required without the present invention. A digital-to-analog conversion method and interpolating digital-to-analog converter for a data modulation system which reduces the spurious energy content of the output signal by an order of magnitude to thereby permit use of a less complex reconstruction filter to smooth the analog output. The process is a two step charge redistribution with feedback to interpolate between samples. DC offset is minimized by using double sampling techniques which permit a fully held signal between interpolation samples. A first conversion stage converts the first n bits of an N bit data signal received at an input rate to a first output value, and a second conversion stage converts the remainder of the N bits and combines signals from the two conversion stages to provide a combined output to an interpolation stage which provides an interpolated output at an interpolation output rate. A feedback circuit provides the interpolated output to an input of the second conversion stage. A multistage charge redistribution digital to analog converter (DAC) comprising a filter network which has a network data conversion stage integral with an interpolation stage for improving suppression of spurious signals in an input signal to the DAC, said interpolation stage being clocked at a rate which is a multiple of the input rate of the DAC input signal, and for feeding back an output therefrom to said network data conversion stage to smooth an analog signal output from the DAC. A digital-to-analog conversion method and interpolating digital-to-analog converter for a data modulation system which reduces the spurious energy content of the output signal by an order of magnitude to thereby permit use of a less complex reconstruction filter to smooth the analog output. The process is a two step charge redistribution with feedback to interpolate between samples. DC offset is minimized by using double sampling techniques which permit a fully held signal between interpolation samples. A first conversion stage converts the first n bits of an N bit data signal received at an input rate to a first output value, and a second conversion stage converts the remainder of the N bits and combines signals from the two conversion stages to provide a combined output to an interpolation stage which provides an interpolated output at an interpolation output rate. A feedback circuit provides the interpolated output to an input of the second conversion stage. The features disclosed in the foregoing description, in the following claims and/or in the accompanying drawings may, both separately and in any combination thereof, be material for realising the invention in diverse forms thereof.

Claims: A digital to analog conversion circuit comprising a D/A converter running at an interpolation rate for converting an N bit data signal received at an input rate to an analog signal in which spurious energy in the received data signal is reduced in the analog signal, the D/A converter being a charge redistribution type, characterized in that the DAC comprises a filter network which has a network data conversion stage (26) integral with an interpolation stage, said filter network (60) improving suppression of spurious signals in an input signal to the DAC, said interpolation stage (30) being clocked at a rate which is a multiple of the input rate of the DAC input signal, and said filter network (60) feeding back an output therefrom to said network data conversion stage (26) to smooth an analog signal output from the DAC. A DAC as claimed in claim 1 further comprising a prior data conversion stage for receiving the input signal to the DAC and for converting n bits of an N bit input signal to the DAC to a first output value which is provided to said network data conversion stage (26), said network data conversion stage (26) is for converting the remaining bits of the N bit input signal to a second output value and for combining the first and second output values to provide a combined output value, and said interpolation stage (30) comprises a switched-capacitor filter (40) for receiving the combined output value and providing an interpolated output at an interpolation rate which is said multiple times the input rate. A digital to analog converter (DAC) as claimed in claim 1, characterized in that the converter comprises: a first conversion stage (22) for converting n bits of an N bit data signal received at said input rate to a first output value; the filter network (60) further comprising, a second conversion stage (26) for converting the remainder of the N bits in the data signal to a second output value, and for combining the first and second output values into a combined output value, the interpolation stage (30) for receiving the combined output value from said second conversion stage (26) and for providing an interpolated output an interpolation output rate which is a multiple of the input rate, and a feedback circuit (34) for feeding back the interpolated output from said interpolation stage (30) to said second conversion stage (26), whereby the interpolated output is the analog signal with reduced spurious energy. A DAC as claimed in claim 3 wherein said feedback circuit (34) comprises a capacitor (F) which, in conjunction with said second conversion stage (26), forms a complex pole for providing an interpolated output. A DAC as claimed in any one of claims 1 or 3 wherein said interpolation stage (30) comprises a first operational amplifier (56) and first and second switched-capacitors (A, B) in parallel paths connecting an input and output of said first operational amplifier (56), and said interpolation stage (30) is connected to said second conversion stage (26) through a third switched-capacitor (F). A method of reducing spurious energy in an analog signal which is output from a digital to analog converter (DAC) which converts an N bit data signal received at an input rate to an analog signal, the method comprising the steps of: a) converting in a first conversion stage (22) n bits of an N bit data signal received at an input rate to a first output value; b) combining in a second conversion stage (26) the remainder of the N bits in the data signal with the first output value to provide an amplitude value output; c) providing an interpolated amplitude output from an interpolation stage (30) which interpolates the amplitude value output at an interpolation output rate which is a multiple of the input rate; and d) feeding back the interpolated amplitude output to an input to the second conversion stage (26); whereby spurious energy in the interpolated amplitude output is reduced form that obtained by a direct conversion of the data signal. A method as claimed in claim 6 wherein the feedback step comprises the step of forming a complex pole.

Inventors: MYERS BRENT A, MYERS, BRENT A.
Applicants: HARRIS CORP, HARRIS CORPORATION
Application year: 1997
Main classification: H03M1
IPC codes: H03M1