Pixel conversion apparatus

Abstract: A pixel conversion apparatus of the present invention includes sync separation means for separating a sync signal from an input signal, pixel conversion information analysis means for analyzing how to convert the number of pixels to display the input signal as an image from the input signal and a picture display area, timing signal generation means for generating a timing signal for displaying an image according to the outputs of the sync separation means and the pixel conversion information analysis means, pixel conversion means for processing a pixel conversion of the input signal according to the output of the timing signal generation means, interpolation means for processing a pixel interpolation when pixel to be interpolated generates by pixel conversion at the pixel conversion means, and sync signal generation means for generating a sync signal for displaying the input signal as an image. Because the relation between the input signal and the image display area is previously analyzed and processed, there is no lack or display by mistake of image information included in the input signal and a high quality image can be effectively displayed on the picture display area of the display device.

Description: BACKGROUND OF THE INVENTION The present invention relates to a pixel conversion apparatus in an electronic equipment field taking a liquid crystal display as a representative. It relates to a pixel conversion apparatus, especially used when the number of pixels of the display area is different from the number of pixels of the input signal. For displaying a picture on a display device such as a liquid crystal panel having different number of pixels from the pixels of an input signal, a pixel conversion apparatus is used. A pixel conversion apparatus in accordance with the prior art is explained below, referring to the drawing, to explain a function of scanning line conversion. FIG. 1 is a block diagram of a pixel conversion apparatus in accordance with the prior art in the case of a reduction conversion. FIG. 2 is a chart explaining a function of interpolating reduction conversion. In FIG. 1, the block 20 is a reference counter. The block 21 is a comparator. The block 22 is a register. The block 23 is an adder. The block 24 is an interpolation circuit. The block 25 is a memory. The block 26 is an address generator. FIG. 2 shows a functional principle at reduction factor is 0.6. In FIG. 2, short vertical lines of input signal express sample values of the original signal and the black dots express the values necessary to be newly made by interpolation. First, a reciprocal of the reduction factor SH = (standard picture size) / (size to be reduced) is inputted from, for example a microcomputer. In this example, SH = 1/0.6 = 1.67, and it means that a new sample value is made at every 1.67 times of the original sampling period. The signal SH is applied to a ΣSH circuit 27 composed of register 22 and adder 23. ΣSH circuit 27 integrates the input signal at the output of comparator 21 at every time an incidence pulse appears. The integer part of the output signal of ΣSH circuit 27 which is an integral output is compared with the output of reference counter 20 and comparator 21 outputs an incidence pulse when the values are equal. The incidence pulse indicates a position of a sample point to be interpolated, while the decimal part of the output signal of ΣSH circuit 27 is used as an interpolation coefficient at the moment. Thus, the sample value obtained as a result of interpolation is written in a designated position on the main memory according to a writing address made from the coincidence pulse at the counter. Thus, because a reduced image can be formed on the memory by interpolating new pixel data at a generation of coincidence pulse and writing in a main memory, if it is read at a standard speed and is D/A converted, a reduced analog image signal is obtained. An example of a horizontal reduction is described but it is similar in a vertical reduction and in this case, a pulse synchronized with a horizontal sync signal takes a part of the clock signal. To convert the number of sampling like this, it is necessary to calculate sampling points and interpolation coefficients for interpolation based on the reference clock (or horizontal sync pulse) and to form a data array by a memory. Further, for example, considering a case to convert a VGA (video graphics array) standard into an XGA (extended video graphics array) standard and display it on a liquid crystal panel for XGA standard, the number of horizontal dots is 800 and the number of horizontal effective dots is 640 in the case of VGA standard. Because the number of horizontal effective dots is 1024 in the case of XGA, a signal of VGA standard can be displayed on a liquid crystal panel for XGA standard by multiplying the number of horizontal sampling by 1.6 (= 1024/640). A signal of 832 horizontal dots and 640 horizontal effective dots is included in a standard decided at VESA (Video Electronics Standards Association). When this signal is displayed for example, on a liquid crystal panel for XGA standard, if the number of horizontal effective dots is converted simply like multiplying by 1,6 (= 1024/640), the number of horizontal dots becomes 1331.2 (= 832x1.6), the number is an odd number with a decimal part and a normal display can not be obtained on this panel. Further, because the number of horizontal dots is larger than 1280 (standard of XGA), a part of image does not fill the specifications of a liquid crystal panel and it is sometimes impossible to display. Therefore, only the effective picture area of the converted signal is once written in a memory and only the effective picture area is read from the memory with a clock signal filling the specifications of the liquid crystal panel. In this case, it is general to adopt a method that reading clock signal is generated non-synchronized with the input signal, while the writing clock signal is synchronized with the input signal. For a television signal such as NTSC (National Television Standard Committee), a composition to display on a panel having VGA of 640x480 pixels by doubling the number of scanning lines is generally used. In this case, to double the number of scanning lines, a composition to convert the number of scanning lines into double by writing the input signal into a FIFO (first in and first out) and reading a line twice at a double speed of the writing is generally used. The composition is simple and there is no need of a field memory and only an FIFO (line memory) is necessary but the vertical resolution deteriorates because it is not interlaced. To secure a good vertical resolution, a field memory such as movement adaptive type scanning line interpolation is necessary. A plurality of clock signal generation circuits for writing and reading into and from a memory used for a pixel conversion of the prior art is explained below and a plurality of PLL (phase locked loop) circuits having the same composition are merely used for generating each clock signal. FIG. 3 is a block diagram of a video display apparatus in accordance with the prior art. The block 1 is a sync separator. The block 2 is a first phase detector. The block 3 is a first LPF (low pass filter). The block 4 is a first VCO (voltage controlled oscillator). The block 5 is a first counter. The block 6 is a first PLL composed of first phase detector 2, first LPF 3, first VCO 4 and first counter 5. The block 7 is a pixel converter. The block 8 is a second phase detector. The block 9 is a second LPF. The block 10 is a second VCO. The block 11 is a second counter. The block 12 is a second PLL composed of second phase detector 8, second LPF 9, second VCO 10 and second counter 11. The block 13 is a timing signal generator. A composite video signal inputted from an outside is supplied to pixel converter 7, an expansion or a reduction is processed by a clock signal from first PLL 6 and a clock signal from second PLL 12. (Clock signals having different frequencies are used between the input and the output.) The composite video signal inputted from the outside is also supplied to sync separator 1 at the same time. At sync separator 1, only a sync signal is extracted from the composite video signal. A horizontal sync signal separated at sync separator 1 is supplied to first phase comparator 2. The PWM (pulse width modulation) output of first phase comparator 2 is supplied to first LPF 3. The response characteristic of first PLL 6 is almost decided at first LPF 3. Receiving an output of first LPF 3, first VCO 4 outputs a stable first clock signal. This first clock signal is used for driving a front stage of pixel converter 7. Further, the-first clock signal is frequency divided at an arbitrary rate at first counter 5 and is returned to first phase detector 2. A phase difference between two input signals is detected at first phase comparator 2. The output of first counter 5 is also supplied to second phase comparator 8. The response characteristic of second PLL 12 is decided at second LPF 9. In the case in which pixel interpolation is necessary at a pixel conversion apparatus in accordance with the prior art, what interpolation is made is explained below. A horizontal pixel conversion circuit of the prior art is explained below referring to the drawings. FIG. 4 is a block diagram of a horizontal pixel conversion circuit of the prior art. PLL circuit 42 is a circuit for faithfully reproducing a clock signal forming the input signal from the input signal and it is necessary to know previously and correctly the number of clocks per one horizontal period and the phase difference between the input signal and the clock a reproduced at PLL circuit 42 has to be adjusted. In recent years, signals outputted from computers have a lot of variety, for example the clock frequency has a wide range from about 20 MHz to over 100 MHZ. At any two computers, the numbers of clocks per one horizontal period including a blanking period are not always the same, even if the number of effective display pixels of the two computers are the same. With what clock frequency or with what number of clocks per one horizontal period, the operator of the computer or the software of the computer outputs a signal is quite arbitrary. Therefore, the oscillation frequency range of PLL circuit 42 must be wide and a lot of values must be previously stored for the number of clocks per one horizontal period. The function of a gradation integral display circuit 43 is expressed by the following equation. Qi = D(i) x a + D(i+1) x b + D(i+2) x c + D(i+3) x d Where, Qi is the i-th data after pixel conversion. D(i+1), D(i+2) and D(I+3) are the D(I+1)-th, the D(I+2)-th and the D(I+3)-th data before conversion, respectively. For example, the values a, b, c and d of the input signal are decided by a ratio of number of pixels between before and after conversion and is obtained by calculating a contribution factor of the data before conversion against the data after conversion. An example of the gradation integral display at a conversion from five pixels to four pixels is shown in Fig 5. As shown in Fig 5, the five pixels before conversion are divided into four equal parts and new brightness values for the four pixels are obtained by integrating each brightness value at each divided area. Information which originally one pixel had is reflected to one or two pixels after pixel conversion. SUMMARY OF THE INVENTION The object of the present invention is to present a pixel conversion apparatus which can effectively display an input video signal after pixel conversion on an image display area to be displayed with a high quality and without any lack or any display by mistake of the image information included in the input signal. The present invention provides a pixel conversion apparatus as defined in claim 1. A pixel conversion apparatus having the features of the preamble of claim 1 is disclosed in EP-A-0479 508. Because the relation between the input signal and the image display area is previously analysed and processed, there is no lack or display by mistake of image information included in the input signal and a high quality image can be effectively displayed on the picture display area of the display device. Advantageously, the timing generation means discriminates the number of pixels and the effective display area of the input signal. Further, the blanking period of the picture displaying the input signal is calculated from the discrimination result and the picture display area with the horizontal sync signal in the blanking period being made different from the effective picture area. It means that because the input signal picture information can not be displayed on the picture display area of the display device, the picture is not displayed with any cut or intermittently. Expressing as scanning line conversion, scanning line conversion which can display on a display device such as a liquid crystal panel without frame frequency conversion can be realised. Especially, the pixel conversion information analysis means discriminates which the input video signal is interlaced or non-interlaced, discriminates which the interlaced signal is in an odd field or in an even field and the interpolation means processes a different interpolation between for an odd field and for an even field according to the discrimination result of odd/even field. Thus, because the picture information is correctly reproduced for a pixel conversion even when the input video signal is interlaced, a display can be obtained without deterioration in vertical resolution. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a pixel conversion apparatus in accordance with the prior art in the case of a reduction conversion. FIG. 2 is a chart explaining a function of interpolating reduction conversion of a pixel conversion apparatus in accordance with the prior art in the case of a reduction conversion. FIG. 3 is a block diagram of a picture display apparatus in accordance with the prior art. FIG. 4 is a block diagram of a horizontal pixel conversion circuit in accordance with the prior art. FIG. 5 is a chart explaining a function of horizontal pixel conversion a pixel conversion apparatus in accordance with the prior art in the case of a reduction conversion. FIG. 6 is a block diagram of a pixel conversion apparatus in accordance with an exemplary embodiment of the present invention. FIG. 7 is a block diagram of a timing signal generator 65 used in a pixel conversion apparatus in accordance with the exemplary embodiment of the present invention. FIG. 8 shows relations between the number of samples and the number of scanning lines for three kinds of video signals in a pixel conversion apparatus in accordance with the exemplary embodiment of the present invention. (a) image area of an original signal (b) image area of a signal 1 after conversion (c) image area of a signal 2 after conversion FIG. 9 is a block diagram of a pixel conversion apparatus in accordance with a comparative example. FIG. 10 is a block diagram of a timing signal generator 66 used in a pixel conversion apparatus in accordance with the comparative example. FIG. 11 is a chart explaining a function of frame frequency conversion. (a) a relation between writing and reading at a non-synchronous conversion (b) a relation between writing and reading at a synchronous conversion FIG. 12 is a chart explaining a function of frame frequency conversion . (a) a memory writing period before conversion (b) a memory writing period after, conversion. DESCRIPTION OF THE PREFERRED EMBODIMENTS An exemplary embodiment of the present invention is explained below referring to FIGs. 6-8. (Exemplary embodiment) FIG. 6 is a pixel conversion apparatus in accordance with an exemplary embodiment of the present invention. In FIG. 6, the block 61 is a sync separator. The block 62 is a first PLL circuit for generating a first clock signal synchronizing with a horizontal sync signal of the input signal. The block 63 is a second PLL circuit for generating a second clock signal synchronizing with a horizontal sync signal of the input signal. The block 64 is a scanning line converter for converting the number of scanning lines of the input signal. The block 65 is a timing signal generator for generating an interpolation coefficient and an interpolation timing signal to interpolate the sample at scanning line converter 64 and generating a sync signal to drive a display device such as a liquid crystal panel. FIG. 7 is an example of a block diagram of a timing signal generator. The block 76 is a first counter for generating a signal HD1 by dividing a first clock signal CK1 at an arbitrary rate. The block 77 is a horizontal interpolation circuit for generating an interpolation coefficient and a timing signal used at horizontal interpolation by using first clock signal CK1. The block 78 is a second counter for generating a signal HD2 by dividing second clock signal CK2 at an arbitrary rate. The block 79 is a vertical interpolation circuit for generating an interpolation coefficient and a timing signal used at vertical interpolation by using second clock signal CK2. The block 710 is a first H counter for generating a first horizontal sync signal a by counting second clock signal CK2. The block 711 is a second H counter for generating a second horizontal sync signal b by counting second clock signal CK2. The block 712 is a selector for selecting the output signal a of first H counter 710 or the output signal b of second H counter 711. The block 713 is a V counter for controlling selector 712 by counting a horizontal sync signal c which is an output of selector 712. FIG. 8 shows relations between the number of samples (horizontal) and the number of scanning lines (vertical) for three kinds of video signals. The function of the pixel conversion apparatus in accordance with an exemplary embodiment of the present invention is explained below. In FIG. 6, an input signal is applied to sync separator 61, where a horizontal sync signal Hsync and a vertical sync signal Vsync are separated and outputted. First PLL circuit 62 reproduces a first clock signal CK1 from Hsync. The frequency of first clock signal CK1 is decided at first PLL circuit 62 by setting a dividing ratio at first counter 76 in timing generator 65. For example, in the case of VGA standard, a dot clock signal at the signal sending side can be reproduced by setting the dividing ratio 800. A clock signal CK2 set at second counter 78 is similarly generated at second PLL circuit 63. For example, in the case of converting a VGA standard signal which is an input signal, the dividing ratio of second counter 78 is set to 1280 similarly to XGA standard. Horizontal interpolation circuit 77 and vertical interpolation circuit 79 generate an interpolation coefficient and a timing signal converting from a VGA standard to an XGA standard and scanning line converter 64 converts the number of scanning lines. The input signal is converted from the relation between the number of samples and the number of scanning lines of CK1 shown in FIG. 8(a) to the relation between the number of samples and the number of scanning lines of CK2 shown in FIG. 8(b). That is, because the number of horizontal dots is converted from 800 dots to 1280 dots (1.6 times), the number of scanning lines in a vertical direction is also converted from 525 lines to 840 lines, that is 1.6 times. However, because the number of scanning lines of a standard XGA signal is 806 lines, there is no room in the timing specifications for a picture display device such as a liquid crystal panel and some parts are not displayed for a signal with 840 lines. The output signal a of first H counter 710 and the output signal b of second H counter 711 are set 1280 and 2304, respectively and the number of lines is counted at V counter 713 and the output signal a or b is selected at the border of 768 lines. The sync signals are selected so that the timing of the horizontal sync of the effective lines is left as it is and the horizontal sync of the effective lines during a vertical blanking period is that shown in FIG. 8(c) and the number of horizontal dots for 40 (=808 - 768) lines during a vertical blanking period is 2304 dots. Thus, because the number of vertical lines becomes 808 lines and it is close to 806 lines of XGA standard, the image can be displayed on the liquid crystal panel. Although an example having two H counters was shown in the exemplary embodiment of the present invention, a timing of the horizontal sync signal is selected by using more than two H counters and a proper display can be obtained. According to such a composition, it is possible to display a picture even on a display device having less room of timing without frame frequency conversion by providing with a plurality of horizontal sync signals during a frame period. That is, the number of lines is not converted according to the ratio of the number of horizontal effective dots before conversion to the number of horizontal effective dots after conversion by selecting a horizontal sync signal having a plurality of horizontal frequencies in the same frame, the conversion ratio of a horizontal direction can be made different from that of a vertical direction. As a result, the number of, scanning lines can be converted without any lack of picture on the display area. (Comparative example) A comparative example is explained below referring to FIGs. 9, 10, 11 and 12. The blocks having similar functions to those in the exemplary embodiment are numbered with the same reference numbers and their explanations are omitted. In FIG. 9, the block 67 is a memory. FIG. 10 is a block diagram of a timing signal generator 66 shown in FIG. 9. The block 715 is a third H counter. The block 716 is a fourth H counter. The block 717 is a second selector. The block 718 is a second V counter. FIGs. 11 and 12 are charts expressing frame frequency conversion. In the comparative example, although it is general to convert a frame frequency using a memory in the case in which timing specifications of a display device is not satisfied, in this case, if the memory writing and the memory reading are made with non-synchronized clocks as shown in FIG. 11(a), a jumping over of a frame before conversion occurs on the picture. That is, when the reading clock frequency is a little higher than the writing clock frequency, the read address passes over the write address while writing like #1 (the first) frame as shown in FIG. 11(a). Although the first frame is read at reading, on the way it changes to call out a frame signal one frame ahead. It has no problem in a still picture but in a moving picture, the frame jumps over on the effective picture area and it appears as an interference. It is possible not to make jump over in the picture by setting a clock frequency and horizontal and vertical sync frequencies after conversion so that the ratio of the number of frame clocks before conversion to the number of frame clocks after conversion is an integer as shown in FIG. 11(b). FIG. 11(b) shows an example that three frames are converted into four frames. Defining m is the total number of clocks per one frame before conversion, for example if the number of horizontal dots is 2000 and the number of scanning lines is 830, m = 2000 * 830 = 1660000 clocks. Where, if the number of maximum horizontal dots is 1700 and the number of maximum scanning lines is 832 as timing specifications of a liquid crystal panel, the number of maximum allowable clocks per one frame of the liquid crystal panel is 1700 * 832 = 1414400 clocks, and even how many horizontal sync signals are given in one frame as shown in the exemplary embodiment, the specifications for a liquid crystal panel can not be satisfied. Accordingly, only the effective picture area of the signal before conversion is written in a memory and as for reading, only the effective picture area is read out and the frame frequency is converted. Defining the total number of clocks per one frame after conversion as n, n is selected so that the ratio of n to m is an integer. For example, the three frames before conversion and the four frames after conversion are made to be equal in time. That is, 3 * m = 4 * n Therefore, n = 3/4 * m = 1,245,000 clocks. It satisfies the number of maximum allowable clocks of the liquid crystal panel. Then, the number of horizontal dots and the number of scanning lines after conversion are decided. The number of horizontal dots and the number of scanning lines as shown in the exemplary embodiment can be easily decided by having a plurality of horizontal sync signals per one frame. For example, it is decided that the number of horizontal dots is 1558 for first 795 scanning lines of total 797 scanning lines and the number of horizontal dots is 1637 for the last two scanning lines. The specifications of the liquid crystal panel is satisfied. As for memory reading, only the effective picture area is read according to the number of dots decided like the above. The relations between the number of horizontal dots and the number of scanning lines before and after conversion and the relation of memory controls are shown in FIG. 12. In this case, a frame frequency conversion is done but neither write address nor read address does not jump over by making the writing clock the same as the reading clock. By that, interference due to a frame jumping over in the effective picture area does not occur. Because the clocks for memory writing and memory reading can be the same, the number of clock reproducing circuits can be less compared with the case of non-synchronization. The number of total clocks before conversion m is decided by H counter 710 or 711 and V counter 713 and the number of total clocks after conversion n is decided by H counter 715 or 716 and V counter 718. Thus, in the comparative example, a scanning line conversion is done without frame jumping over or discontinuous displaying.

Claims: A pixel conversion apparatus for converting an input video signal having a first format to an output video signal having a second format which is different from said first format, the input video signal and the output video signal having fields having two video signal portions each comprising a series of consecutive scanning lines which are delimited by horizontal and vertical sync signals (Hsync, Vsync), wherein the first signal portion is an effective video signal portion which contains the image information and the second signal portion is a blanking video signal portion which does not contain image information and which follows with respect to time. the effective video signal portion, said apparatus comprising: sync separation means (61) for separating the horizontal and vertical sync signals (Hsync, Vsync) from said input video signal; pixel conversion means (62,63,64,76,78) for determining how to convert pixels of said input video signal to pixels of the output video signal, for provision of clock pulses for the output video signal, each clock pulse being related to a pixel, and for carrying out said conversion such that the aspect ratio of the images of the output video signal is equal to the aspect ratio of the image of the input video signal; interpolation means (77,79) for interpolating at least a portion of said pixels from said pixel conversion means (62,63,64,76,78); and timing generation means (710,711,712,713) that is arranged to provide a first horizontal sync signal for each scanning line of the effective video signal portion according to the second format on the basis of the outputs of the pixel conversion means (62,63,64,76,78); characterised in that the timing generation means (710,711,712,713) is further arranged to provide the first horizontal sync signal according to a first number of the clock pulses for each scanning line within the effective video signal portion and provide a second horizontal sync signal according to a second number of the clock pulses for each scanning line within the blanking video signal portion; said second number of clock pulses being different from said first number of clock pulses such that is the number of the consecutive scanning lines within the effective video signal portion after the conversion is equal to the number of lines required for the effective video signal portion of said output video signal and such that ii) the total member of consecutive scanning lines within the effective video signal portion and the blanking video signal portion after the conversion is substantially equal to the total number of lines required for the effective video signal portion and the blanking video portion in said second format. A pixel conversion apparatus according to claim 1, wherein the pixel conversion means (62,63,64,76,78) comprises: a first PLL circuit (62) for generating a first clock signal (CK1) synchronizing with the separated horizontal sync signals (Hsync) outputted from said sync separation means. a second PLL circuit (63) for generating a second clock signal (CK2) synchronizing with said separated horizontal sync signals (Hsync), the second clock signal (CK2) constituting the clock pulses; a scanning line conversion circuit (64) for i) converting the number of scanning lines of said input video signal to a further number of scanning lines, and for converting the number of pixels per scanning line to a further number of pixels per scanning line and for ii) providing said output video signal; and wherein the timing generation means (710,711,712,713) furthermore includes said interpolation means (77,79) which is arranged to i) generate an interpolation timing signal and an interpolation coefficient for horizontal interpolation at said scanning line conversion circuit (64) responsive to the first clock signal (CK1), and ii) generate an interpolation timing signal and an interpolation coefficient for vertical interpolation at said scanning line conversion circuit (64) responsive to the second clock signal (CK2).

Inventors: FUNAMOTO TARO, HATANO TAKAHISA, KAMEOKA FUMIOU, SHINDO YOSHIKUNI, FUNAMOTO, TARO, HATANO, TAKAHISA, KAMEOKA, FUMIOU, SHINDO, YOSHIKUNI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1997
Main classification: G09G3
IPC codes: G09G3, H04N7, G09G5