Level conversion circuit having differential circuit employing MOSFET

Abstract: Disclosed herein is a level conversion circuit which operates at high speeds even at a low power-supply voltage. The level conversion circuit is largely constituted by an emitter follower section 101, an amplitude amplification section 102, and a level conversion section 103. The amplitude amplification section 102 is a differential amplifier constructed so that the gate of an N-channel MOS transistor M1 is connected to a node 001, the connection node 002 of the drain is connected to a high power-supply terminal VCC through a resistor R2, the source is connected to a node 004, the base of an N-channel MOS transistor M2 is connected to a reference power-supply terminal VR, the connection node 003 of the drain is connected to the high power-supply terminal VCC through a resistor R3, the source is connected to a node 004, the base of an NPN transistor Q4 is connected to a reference power-supply terminal VCSI, the collector is connected to the node 004, and the emitter is connected to the first low power-supply terminal GND1 through a resistor R4.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a level conversion circuit and, more particularly, to such a circuit that converts an ECL level or CML level signal to a MOS level signal. Description of the Related Art As a signal input circuit of a MOS-IC or MOS-LSI, a level conversion circuit is widely employed to convert an input signal having an ECL level or a CML level signal to into an internal signal having a MOS level signal. Such a circuit generally employs a differential circuit composed of bipolar transistors. Specifically, as shown in Fig. 2, a conventional level conversion circuit includes an emitter follower section 101, an amplitude amplification section 102, and a level conversion section 103. The emitter follower section 101 is an emitter follower constructed such that the base of an NPN transistor Q1 is connected to an input terminal IN, the collector is connected to a high power-supply terminal VCC, and the connection node 001 of the emitter is connected to a first low power-supply terminal GND1 through a resistor R1. The amplitude amplification section 102 is a differential amplifier constructed such that the base of an NPN transistor Q2 is connected to the node 001, the connection node 002 of the collector is connected to the high power-supply terminal VCC through a resistor R2, and the emitter is connected to a node 004. The base of an NPN transistor Q3 is connected to a reference power-supply terminal VR, the connection node 003 of the collector is connected to the high power-supply terminal VCC through a resistor R3, and the emitter is connected to a node 004. The base of an NPN transistor Q4 is connected to a reference power-supply terminal VCSI, the collector is connected to the node 004, and the emitter is connected to the first low power-supply terminal GND1 through a resistor R4. The level conversion section 103 is a level conversion section constructed such that the gate of a P-channel MOS transistor P1 is connected to the node 003, the source is connected to the high power-supply terminal VCC, and the drain is connected to a node 006. The gate of a P-channel MOS transistor P2 is connected to the node 002, the source is connected to the high power-supply terminal VCC, and the drain is connected to an output terminal OUT. The gate and drain of an N-channel MOS transistor N1 are connected to a node 006, and the source is connected to a second low power-supply terminal GND2. The gate of an N-channel MOS transistor N2 is connected to the node 006, the source is connected to the second low power-supply terminal GND2, and the drain is connected to the output terminal OUT. In operation, when the high level of the same current mode logic (CML) level as the high power-supply potential is input to the input terminal IN, the level of the signal is shifted by the amount of the ON-state base-emitter voltage of the NPN transistor by the emitter follower section 101. The shifted signal is input to the node 001 which is the input of the amplitude amplification section 102, and the NPN transistor Q2 is turned on. The NPN transistor Q3 is turned off and current flows through the resistor R2. A level lower by the amount of the voltage drop of the resistor than the high power-supply potential is output to the node 002, and the high power-supply potential is output to the node 003. These levels are input to the level conversion section 103. The P-channel MOS transistor P2 is turned on and the P-channel MOS transistor P1 is turned off. The electric charges on the node 006 are pulled out by the N-channel MOS transistor N1, and the N-channel MOS transistor N2 is turned off. The high level of the same CMOS level as the high power-supply potential is output to the output terminal OUT. When the low level of the CML level lower by the amount of a logic amplitude than the high power-supply potential is input to the input terminal IN, the low level of the same CMOS level as the second low power-supply potential is output to the output terminal OUT. In this conventional level conversion circuit, the levels on the nodes 002 and 003, which are the outputs of the amplitude amplification section 102, have to be sufficiently low in order to completely turn on one transistor of the P-channel MOS transistors P1 and P2 of the input section of the level conversion section 103 and completely turn off the other transistor. If this requirement is not met, the level conversion section will not be operated, or even if it were operated, the operating speed would become slow. The low level on the output of the amplitude amplification section 102 must be a sufficiently low level so that one transistor of the input transistors of the level conversion section 103 can be completely turned on even when the value fluctuates and becomes the highest value. However, if the low level of the output is set to a sufficiently low value in view of the case where it is the maximum value, there will be the problem that the collector potentials of the NPN transistors Q2 and Q3, which constitute the current switches of the amplitude amplification section 102, will be overreduced and that the transistors will be saturated and the operating speeds will be reduced, when the low level of the output fluctuates conversely in the lowest direction. In order to avoid the saturation of the NPN transistors Q2 and Q3 at the current switch section of the amplitude amplification section 102, there is a method where a diode is inserted between the emitter of the NPN transistor Q1 and the node 001 so that the input signal level to a transistor constituting the current switch section is further reduced by the amount of the ON-state base-emitter voltage of the transistor. When the first low power-supply terminal GND2 is sufficiently low and the potential on the reference power-supply terminal VCSI is also low, there is no problem. However, when the first power-supply potential GND1 is high and becomes equal to the potential of the second low power-supply terminal GND2 and when the power-supply voltage, which is the potential difference between the high power-supply potential and the low power-supply potential, is low, there arises the problem that the collector potential of the NPN transistor Q4 constituting a current source falls and that the NPN transistor Q4 is saturated, if an input signal level is lowered. Making the low level on the output of the amplitude amplification section 102 sufficiently large so that the MOS transistors P1 and P2 of the level conversion section 103 can be completely turned on or off and also preventing the saturation of the transistors of the current switch and current source sections become even more severe as the power-supply voltage becomes lower. A circuit similar to the one shown in figure 2 is also disclosed in US-A-5434518. US-A-5332935 discloses to use MOS-transistors for the differential amplifier of an amplitude amplification section (102). According to this document the amplitude amplification section comprises a pair of MOS-transistors forming a differential amplifier, the source thereof being coupled to a current source and the drain thereof being coupled through load elements with a potential line. According to this document P-MOS transistors are used as load elements. The source of both transistors forming the differential amplifier are connected to a current source formed by a further N-MOS transistor. EP-A-0 436 823 teaches to avoid saturation of bipolar transistors by using fet-transistors. US-A-4779016 discloses a further level conversion circuit. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a level conversion circuit which operates at high speeds even at a low power-supply voltage. This object is achieved by a level conversion circuit according to claim 1. The dependent claims are related to further advantageous aspects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described in further detail with reference to the accompanying drawings, in which: FIG. 1 is a circuit diagram showing an embodiment of a level conversion circuit of the present invention; and FIG. 2 is a circuit diagram showing an example of a conventional level conversion circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to Fig. 1, a level conversion circuit according to an embodiment of the present invention includes an emitter follower section 101, an amplitude amplification section 102, and a level conversion section 103. The emitter follower section 101 is an emitter follower constructed such that the base of an NPN transistor Q1 is connected to an input terminal IN, the collector is connected to a high power-supply terminal VCC, and the connection node 001 of the emitter is connected to a first low power-supply terminal GND1 through a resistor R1. The amplitude amplification section 102 is a differential amplifier constructed such that the gate of an N-channel MOS transistor M1 is connected to the node 001, the connection node 002 of the drain is connected to the high power-supply terminal VCC through a resistor R2, and the source is connected to a node 004. The base of an N-channel MOS transistor M2 is connected to a reference power-supply terminal VR, the connection node 003 of the drain is connected to the high power-supply terminal VCC through a resistor R3, and the source is connected to a node 004. The base of an NPN transistor Q4 is connected to a reference power-supply terminal VCSI, the collector is connected to the node 004, and the emitter is connected to the first low power-supply terminal GND1 through a resistor R4. The level conversion section 103 is a level conversion section constructed such that the gate of a P-channel MOS transistor P1 is connected to the node 003, the source is connected to the high power-supply terminal VCC, and the drain is connected to a node 006. The gate of a P-channel MOS transistor P2 is connected to the node 002, the source is connected to the high power-supply terminal VCC, and the drain is connected to an output terminal OUT, The gate and drain of an N-channel MOS transistor N1 are connected to a node 006, and the source is connected to a second low power-supply terminal GND2. The gate of an N-channel MOS transistor N2 is connected to the node 006, the source is connected to the second low power-supply terminal GND2, and the drain is connected to the output terminal OUT. In operation, when the high level of the same current mode logic (CML) level as the high power-supply potential is input to the input terminal IN, the level of the signal is shifted by the amount of the ON-state base-emitter voltage of the NPN transistor by the emitter follower section 101. The shifted signal is input to the node 001 which is the input of the amplitude amplification section 102, and the N-channel MOS transistor M1 is turned on. The N-channel MOS transistor M2 is turned off and current flows through the resistor R2. A level lower by the amount of the voltage drop of the resistor than the high power-supply potential is output to the node 002, and the high power-supply potential is output to the node 003. These levels are input to the level conversion section 103. The P-channel MOS transistor P2 is turned on and the P-channel MOS transistor P1 is turned off. The electric charges on the node 006 are pulled out by the N-channel MOS transistor N1, and the N-channel MOS transistor N2 is turned off. The high level of the same CMOS level as the high power supply potential is output to the output terminal OUT. When the low level of the CML level lower by the amount of a logic amplitude than the high power-supply potential is input to the input terminal IN, the low level of the same CMOS level as the second low power-supply potential is output to the output terminal OUT. In the level conversion circuit of the embodiment of the present invention, MOS transistors are used in the transistors which constitute the current switches of the amplitude amplification section. Therefore, in the case where an output level is set to a sufficiently low value so that the input transistors P1 and P2 of the level conversion section 103 can be completely turned on or off when the low level on the output of the amplitude amplification section 102 fluctuates and assumes the highest value, the output level can be set to a sufficiently low value without causing a reduction in an operating speed which is caused due to saturation, unlike bipolar transistors, even when the low level on the output fluctuates conversely in the lowest direction, and consequently the high-speed operation of the level conversion section 103 also becomes possible. Because a low level can be output at the logic amplitude section without reducing the level of an input signal, it is possible to operate the NPN transistor of the current source without saturating it even at a low voltage. As has been described above, the level conversion circuit according to the present invention constitutes the current switches of the differential amplifier, which is the amplitude amplification section, by MOS transistors, whereby there is no reduction in the speed which is caused by the saturation of the current switches resulting from a fluctuation in the output level in the amplitude amplification section and the output level can be set so as to be sufficiently low. Accordingly, there is the advantage that high-speed operation is made possible even when power-supply voltage is reduced. While the invention has been described with reference to a preferred embodiment thereof, the invention is not to be limited to the details given herein, but may be modified within the scope of the appended claim.

Claims: A level conversion circuit comprising: an input node (001); a first MOS transistor (M1) of a first channel type having a gate coupled to said input node (001), a source and a drain; a second MOS transistor (M2) of said first channel type having a gate supplied with a first reference voltage (VR), a source coupled to the source of said first MOS transistor and a drain; a third MOS transistor (P2) of a second channel type having a gate connected to the drain of said first MOS transistor (M1), a source coupled to a first potential line (VCC) and a drain; a fourth MOS transistor (P1) of said second channel type having a gate connected to the drain of said second MOS transistor (M2), a source coupled to said first potential line (VCC) and a drain; a fifth MOS transistor (N1) of said first channel type having a gate and a drain coupled to the drain of said fourth MOS transistor (P1) and a source coupled to a second potential line (GND2); a sixth MOS transistor (N2) of said first channel type having a gate coupled to the gate of said fifth MOS transistor (N1), a drain coupled to the drain of said third MOS transistor (P2) and a source coupled to said second potential line (GND2); and an output terminal (OUT) coupled to the drain of said third MOS transistor (P2), said level conversion circuit further comprising a first bipolar transistor (Q4) having a base supplied with a second reference voltage (VCSI), a collector connected to the source of said first MOS transistor (M1) and an emitter, a first resistor (R4) connected between the emitter of said first bipolar transistor (Q4) and a third potential line (GND1), a second resistor (R2) coupled between the drain of said first MOS transistor and said first potential line (VCC), and a third resistor (R3) coupled between the drain of said second MOS transistor (M2) and said first potential line (VCC). The circuit as claimed in claim 1, characterized by further comprising an emitter follower transistor (Q1) having a base supplied with an ECL or CML level signal and a collector-emitter path coupled between said first potential line (VCC) and said input node (001), and a fourth resistor (R1) coupled between said input node (001) and said third potential line (GND1). The circuit as claimed in claim 2, characterized in that said first channel type is an N-channel type, said second channel type is a P-channel type, and each of said first bipolar transistors (Q4) and said emitter follower transistor (Q1) is of an NPN type.

Inventors: KANNO HIROSHI, KANNO, HIROSHI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1997
Main classification: H03K19
IPC codes: H03K5, H03K19, H03F3