METHOD AND APPARATUS FOR OPTIMIZATION OF STANDARD CELL LIBRARIES

Abstract: A method and apparatus (100) for optimization (104) of standard cell libraries (114). A methodology for optimization of device sizes in CMOS standard cell libraries is described.

Description: Description METHOD AND APPARATUS FOR OPTIMIZATION OF STANDARD CELL LIBRARIES Technical Field The present invention relates to methods and apparatus for designing an integrated circuit, and more particularly, to methods and apparatus for optimizing standard cell libraries that are used for designing an integrated circuit. Background of the Invention Digital standard cells are used in a variety of integrated systems using integrated circuits (ICs) produced from standard cell libraries. These systems have wide variability in design requirements . In some systems, power consumption is critical, in others, minimal silicon area is important due to its reduced cost, and, in some systems, operating speed is the dominant consideration. Given the varying requirements of system designs and the widespread usage of digital standard cells, it is desirable to have standard cell libraries which are tuned to these specific needs. Previous optimizations of standard cell libraries have focused on specific circuits and implementations. Typically, standard cell optimization has been limited to the design of a buffer or inverter chain which has been optimized to minimize power dissipation or signal delay. An example of low power optimization is disclosed in "Energy Control and Accurate Delay Estimation in the Design of CMOS Buffers," by Sha Ma and Paul Franzon, IEEE Journal of Solid-State Circuits, vol. 29, no. 9, pp. 1150-1153, September 1994. "Variable-tape CMOS buffer," by S.R. Vemura and A.R. Thorbjornsen, IEEE Journal of Solid-State Circuits, vol. 26, no. 9, pp. 1265-1269, September, 1991, discusses an example of minimal delay buffer optimization. As a matter of practice, the delay optimization efforts have been primarily targeting the ratio of successive stages rather than the NMOS to PMOS ratio. However, no reference has disclosed the advantages of providing a single method and apparatus for optimizing to any one of a chosen set of parameters. Summary of the Invention According to one aspect, the invention is a method for designing a set of device specifications for a library of standard cell components for use in composing an integrated circuit. The method includes the steps of a) determining a process technology for building the components and b) determining an optimization criterion from a predetermined set of optimization criteria. The method further includes the step of c) specifying a set of library-specific knowledge. Further, the method includes the step of d) processing the set of library-specific knowledge as a function of the process technology and the optimization criterion and producing the set of device specifications therefrom. According to another aspect, the invention is a method for designing a set of device specifications for a library of CMOS standard cell components for use in composing an integrated circuit . Each of the CMOS standard cell components includes N- type transistors and P-type transistors. The method includes the steps of a) determining a process technology for building the CMOS standard cell components, and b) determining an optimization criterion from a predetermined set of optimization criteria. The method further includes the step of c) specifying a set of library-specific knowledge. Also the method includes the step of d) processing the set of library-specific knowledge as a function of the process technology and the optimization criterion and producing the set of device specifications therefrom. According to a still further aspect, the invention is an apparatus for designing a set of device specifications for a library of standard cell components for use in composing an integrated circuit . The apparatus includes an input circuit to specify a process technology for building the components and an input circuit to specify an optimization criterion selected from a predetermined set of optimization criteria. The apparatus also includes a memory device to specify a set of library-specific knowledge. The apparatus further includes a processing circuit to process the set of library-specific knowledge as a function of the process technology and the optimization criterion and producing the set of device specifications therefrom. Brief Description of the Drawings Figure 1 is a block diagram of the method of the present invention. Figure 2 is a flow chart of a method for designing a set of device specifications having low power consumption. Figure 3 is a more detailed flow chart of the method for designing a set of device specifications having low power consumption, shown in Figure 2. Figure 4 is a flow chart of a method for checking the noise margin of a combination of logic gates. Figure 5 is a flow chart of a method for checking the noise margin of a specific logic gate. Figure 6 is a flow chart of a method for minimizing the area of a logic gate. Figure 7 is a flow chart of a method for optimizing the NMOS and PMOS widths of a logic gate. Figure 8 is a flow chart of a method for optimizing the ratio of NMOS to PMOS widths of a predetermined logic gate. Figure 9 is a flow chart of a method for optimizing the total width of a predetermined logic gate. Figure 10 is a flow chart of a method for optimizing either the NMOS width or the PMOS width of a predetermined logic gate. Figure 11 is a flow chart of a method for optimizing the PMOS width of a predetermined logic gate. Figure 12 is a flow chart of a method for optimizing the NMOS width of a predetermined logic gate. Figure 13 is a flow chart of a method for maximizing the speed of a predetermined logic gate. Detailed Description of the Preferred Embodiment of the Invention Figure 1 is a block diagram of the method of the present invention. The method 100 includes a step 102 of determining the process technology for building the components desired. The method 100 also includes a step 104 of determining an optimization criterion from a predetermined set of optimization criteria. The standard cell compilers of the present invention all use one of three sets of transistor sizes. The three sets of transistor sizes are respectively optimized for low power, high speed, or minimal area designs, thereby producing standard cell libraries that are optimized accordingly. For example, the standard cell height is a function of the transistor sizes. This provides a means of determining an area cost when performing device size optimization. Each set of transistor sizes consists of four NMOS and four PMOS sizes. The four sizes are selected based on the number of transistors connected in series. For example, a two input NAND gate has two NMOS devices in series . Therefore such a gate would have the transistor size selected for two NMOS transistors in series. The notation used for this transistor size is N_2ε. The same two input NAND gate has one PMOS device in series . Therefore such a gate would use the transistor size selected for a single PMOS transistor in series, P_ls. The goal of transistor size optimization is to determine the four NMOS and four PMOS transistor sizes which will optimize the standard cell library to achieve minimal power dissipation, maximum operating speed, or minimal silicon area. Details of the three optimization procedures follow. Referring again to Figure 1, a sizer program 106 receives the results of the steps 102 and 104 and information from a library specific knowledge database 108. As will be described in greater detail subsequently, the sizer program 106 then processes the set of library-specific knowledge as a function of the process technology and the optimization criterion to produce a set of device specifications 110. Subsequently the set of device specifications 110 can then be made available to a parameterization library compiler 112 which compiles the desired standard cell components and produces a resulting library 114. Figure 2 is a flow chart of a method for designing a set of device specifications having low power consumption. In an integrated circuit, power dissipation is minimized by reducing capacitance as much as is practical . This is implemented with minimal device sizes, subject to a lower limit imposed by setting a minimum noise margin for the gates. The noise margin limit insures that the standard cells will be sufficiently immune to power supply noise. Noise margin is defined as the difference between the logic threshold of a gate and the power supply. The gate's logic threshold is evaluated with the output of the inverting gate shorted to all inputs. Logic thresholds are evaluated for all gates in the standard cell library across temperature, power supply, and process variations. Transistor sizes are adjusted if a gate fails to meet a noise margin requirement and the process is restarted. This is repeated until all gates pass the noise margin requirement . A preference for reducing transistor sizes is included in the process, however, transistor sizes will be increased if required to meet the noise margin requirements. In addition, the output rise and fall times for the gates are limited, by limiting the maximum capacitance that a gate can drive. The maximum capacitance limits the feed through current through the PMOS and NMOS devices from the power supply to ground. Figure 2 is a flow chart of a method for designing a set of device specifications having low power consumption. The method 200 includes an initialization step 202 in which each of the four NMOS and four PMOS transistor sizes is set to ba, the minimum size allowed by the design rules of the specific process technology. After this, in step 204, the state noise margin (NM) is checked by performing the subroutine Check NM{) , which will be described in greater detail subsequently. Figure 3 is a more detailed flow chart of the method 200 for designing a set of device specifications having low power consumption, shown in Figure 2. The method 200 starts with initialization of minimally-sized devices (step 202) . Next the static NM of NOR gates built with the minimally-sized devices is tested (step 300) . If the NM of the NOR gates is too low, the size of the PMOS devices is increased (step 302) and step 300 is performed again. Eventually the NM of the NOR gates reaches a sufficiently high level and the method 200 proceeds to the step 308. In step 308, the NM of NAND gates is tested. If it is too high, the method 200 proceeds to the step 310, where the size of NMOS devices is increased and step 308 is again performed. Again, eventually the NM of NAND gates is not too high, at which point the method 200 determines the logic threshold of complex gates (step 312) , which are various combinations of NMOS and PMOS sizes. If the NM of complex gates is outside of a range bounded by predetermined values, the method 200 determines if the NM is too low (step 314) . If it is, the size of PMOS devices is increased and the method 200 returns to the step 312. If the NM is not too low, it must be too high, in which case the method moves to the step 318, where the size of NMOS devices is increased and step 312 is reperformed. If the value of NM is within the determined range, the method 200 moves to step 304, where it is determined whether there are any changes for complex gates. If there are, the method returns to step 300 to begin the process again. If there are no changes for complex gates, the method goes to the stop step 306 and terminates. Figure 4 is a flow chart of a method for checking the noise margin of a combination of logic gates. The method 400 begins with step 402, which determines whether the PMOS and NMOS devices are changing as the method 400 is used. Initially, the PMOS and NMOS devices are changing, so the method 400 moves to the step 404, where NOR gates are checked by evaluating the effect of changing the values of the four PMOS sizes, by using the subroutine Check NM_gate () , which will be described in greater detail subsequently. Next, the method 400 moves to step 408, where NAND gates are checked by evaluating the effect of changing the values of the four NMOS sizes, again by using the subroutine Check NM_gate () . Finally, the method 400 moves to step 410, where complex gates are checked by evaluating the effect of changing the values of three of the four NMOS sizes and three of the four PMOS sizes, again by using the subroutine Check NM_gate () . The method 400 then returns to step 402, where any changes to PMOS and NMOS are determined. If there are non, the method 400 moves to the return step 406. Figure 5 is a flow chart of a method for checking the noise margin of a specific logic gate. The method 500 begins with step 502, where initial values for NMOS and PMOS sizes, minimal NMOS and PMOS step sizes, and logic thresholds LTmin and LTmax are set. After the method 500 moves to the step 504, the logic threshold is compared to the current values of the logic thresholds LTmin and LTmax. If the logic threshold is neither too high nor too low, the method 500 moves to the step 506, where the values of NMOS and PMOS sizes are established, and then to step 508, from which the subroutine returns. If the logic threshold is either too high or too low, the method 500 moves to the step 510, where a logic threshold is calculated again for high and low supply voltage, combinations of strengths of P and N, and minimum and maximum temperatures. After moving to step 512, the method 500 then compares the logic threshold to the thresholds. If the logic threshold is too high, the method proceeds to the comparison step 514 to determine whether the logic threshold is too high. If it is, the method 500 moves to the step 516, where the new size of PMOS is compared to the minimum acceptable PMOS size. If the new size of PMOS is greater than the minimum acceptable PMOS size, the size of the incremental change in PMOS size is reduced by a factor of 2 (step 520) . Otherwise (step 524) , the size of the incremental change in NMOS size is reduced by a factor of 2. If the size of the incremental change in PMOS size is reduced by a factor of 2, the method moves to the step 522, where the current PMOS size is reduced by the new value of the incremental change. On the other hand, if the size of the incremental change in NMOS size is reduced by a factor of 2, the current NMOS size is increased by the new value of the incremental change in PMOS size. In step 518 of method 500, the logic threshold is tested. If it is too low, the method 500 goes to the step 528. At this point tests are performed on the current value of NMOS size similar to the tests that are performed on the current value of PMOS size in steps 516, 520, 522, 524 and 526. Eventually the method 500 reaches the step 534, where the NM is again reevaluated ant the method returns to the step 504. Minimal area optimization is designed to achieve the fastest possible cells in the minimum area. The devices are sized to fill up the minimum standard cell height. In addition to the check for minimum noise margin, the ratio of gate output rise to output fall times are controlled. To achieve this goal, an initial set of transistor sizes is selected taking in to considerations the standard cell height requirements. This initial set of transistor sizes is further optimized using iterative SPICE simulations to minimize gate delays without increasing the standard cell height. In this process, maximum speed gates are obtained within a minimal layout area. The initial set of transistor sizes approximately equalizes the rise and fall times of the various gates, using the current ratios specified in Table 1, "Initial Current Ratios for Area Optimization" . These sets of currents were empirically found to provide a good tradeoff between area and performance. These sizes are then used to calculate a standard cell height. This initial device set is then further optimized using a sequence similar to the high speed optimization, with the exception that the initial standard cell height is not allowed to increase. Optimization is done on a set of inverter, NAND and nor gates as identified in Table 2, "Minimal Area Gate Optimization Steps. This process establishes the set of transistor sizes required to optimize the standard cell library for minimal area. The optimization determines the one, two, and three in series NMOS and PMOS transistor sizes. The four in series NMOS and PMOS transistor sizes are set such that four in series devices will provide the same pull up or pull down current as the three in series transistor sizes. However, the four in series devices sizes are limited to the maximum NMOS or PMOS device width as computed by the standard cell height routine in this step. Next the ratio of pull up to pull down current is checked for the inverter, NAND and nor gates. This ratio of pull up to pull down current is limited. The NMOS or PMOS transistor width is reduced if possible, otherwise the opposite (PMOS/NMOS) transistor size is increased, as required. A final static noise margin check, as described for the Low Power Optimization, insures that the resulting standard cell library meets the same noise margin requirements as the low power optimized cells. Figure 6 is a flow chart of a method for minimizing the area of a logic gate. In the method 600, the step 602 sets minimum NMOS and PMOS widths. Next, in step 604, the method 600 sizes other NMOS devices to match the pulldown current of N_ls and sizes other PMOS devices to match the pulldown current of P_ls. Moving to step 606, the method 600 establishes the current value of HeightLimit for the standard cell height. This height is increased by 7 percent in step 608. In step 610, the minimum NMOS width is set to ba, as is the minimum PMOS width. The series current of a single device of size min_n is determined in step 612, and then the maximum NMOS width is set to the same as the two-in-series width necessary to provide 33 percent greater current than the series current of a single device of size min_n. In step 616 of method 600, N_ls is set to min_n, N_2s is set to Max_n/2 and N_3s is determined from these two values. In step 618, the series current of a single device of size min_p is determined. Then the maximum PMOS width is set to the value of the three-in-series width necessary to provide series current of a single device of size min_p (step 620) . In step 622, values of P_ls, P_2s, and P_3s are established. In step 624, the HeightLimit value is set to the minimum of its previous value and the standard cell height for the values set in step 622. In step 626, SPICE is used iteratively to minimize the delay for a two-input NAND by adjusting device sizes, using the subroutine opt_np() , to be discussed subsequently. In step 628, SPICE is used iteratively to minimize the delay for an inverter by adjusting device sizes. In step 630, SPICE is used iteratively to minimize the delay for a two-input NOR by adjusting device sizes. In step 632, SPICE is used iteratively to minimize the delay for a three-input NAND by adjusting device sizes. Finally, in step 634, SPICE is used iteratively to minimize the delay for a three-input NOR by adjusting device sizes . Next, in step 636, the three-in-series currents of N-3s and P_3s are determined. In step 638, values of N_4s and P_4s are determined by respective comparisons of the appropriate currents with the minimum spaces available for NMOS and PMOS . In step 640, the static NM is checked, and in step 642, the rise and fall times are checked to be within a factor of three of one another. Figure 7 is a flow chart of a method for optimizing the NMOS and PMOS widths of a logic gate. In step 702 of method 700, parameters are initialized. Then the N-to-P ratio is optimized by making use of the subroutine opt_ratio() , which will be discussed subsequently. The method 700 then moves to the step 706, where the height is compared to the height limit. If the height is too high, the method 700 moves to the step 708, where the total device width is optimized using the subroutine opt_total() with the decrease parameter. The subroutine opt_total() will be discussed subsequently. The method 700 then moves to the step 710. On the other hand, if the height is not over the height limit (step 706) , the total device width is optimized using the subroutine opt_total() with the increase parameter. Again, the height is compared to the height limit (step 710) . If the height is not greater than the height limit, the method 700 moves to the step 714 where the N-to-P ratio is optimized using the subroutine opt_ratio(), with the increase parameter. On the other hand, if the height is greater than the height limit, the method 700 moves to the step 718 where the N- to-P ratio is optimized using the subroutine opt_ratio(), with the decrease parameter. Regardless, the method 700 next moves to the step 716 where the best delay that is inside the height limit from the previous iteration through this subroutine is determined. If the MatchCurrents parameter is set, other devices are resized to match the PMOS and NMOS currents. In step 722 of method 700, there is a check for a better limit in case there is no hardlimit specified as a parameter. If there is a better limit, the method 700 moves to the step 724 where the percentage delay improvement is compared to the square of the percentage increase in the height. If the percentage delay improvement is less than the square of the percentage increase in the height, the method 700 moves to the step 726, where the devices sizes are accepted. Regardless, in step 728, other devices are resized to match currents if MatchCurrents is set . Figure 8 is a flow chart of a method for optimizing the ratio of NMOS to PMOS widths of a predetermined logic gate . In the method 800, the step 802 determines whether the P/N ratio has converged. If not, the subroutine return (step 804) . Otherwise, the standard cell height is recalculated and a standard load capacitance is established (step 806) . Next, in step 808, the delay through the gate with the specified PMOS and NMOS sizes is calculated. In step 810 two evaluations are made. One evaluation is based on a comparison which determines whether the standard cell height is less than the height limit. If it is and the delay has improved, the method 800 moves to the step 824. The other evaluation is used if there is no hardlimit and the percentage delay improvement is greater than the square of the percentage increase in height. Again, if it is the method 800 moves to the step 824. Failing these two possibilities, the method 800 moves to the step 812, where the p step size is compared to the minimum allowable. If it is too small, the method 800 establishes p step sizes in step 814 and moves to step 816. Otherwise, the P/N ratio has converged (step 818) , and the method moves to the step 816. In step 816, the direction of change of the P/N ratio is determined. If it is increasing the value of PMOS is decreased and the value of NMOS is increased (step 818) . Then the method 800 moves to the step 820. Otherwise the value of PMOS is increased and the value of NMOS is decreased, so that the direction of change is increasing. The method 800 then also passes to the step 820. Step 820 resizes the other devices to match the NMOS and PMOS currents, and then returns to step 802. If the test at step 810 is passed, the method 800 moves to the step 824, where the direction of change is also evaluated. If it is increasing the PMOS value is increased and the NMOS value is decrease, and then the method 800 moves to the step 820. If the direction is change is decreasing, the method 800 moves to the step 826, where the PMOS value is decreased and the NMOS value is increased, and the method moves to the step 820. Figure 9 is a flow chart of a method for optimizing the total width of a predetermined logic gate. In step 902 of the method, it is determined whether the value of the total width has converged. If it has not, the method 900 moves to the return step 904. If it has converged, the method 900 proceeds to the step 906, where the standard cell height and standard load capacitance are set. In step 908, the delay through the gate type with the sizes PMOS/NMOS is calculated and the method 900 moves to the step 910. In step 910 two evaluations are made. One evaluation is based on a comparison which determines whether the standard cell height is less than the height limit. If it is and the delay has improved, the method 900 moves to the step 926. The other evaluation is used if there is no hardlimit and the percentage delay improvement is greater than the square of the percentage increase in height. Again, if it is, the method 900 moves to the step 926. Failing these two possibilities, the method 900 moves to the step 912, where the p step size is compared to the minimum allowable. If it is too small, the method 900 decreases p step sizes in step 914 and moves to step 916. Otherwise, the total width has converged (step 918) , and the method moves to the step 916. In step 916, the direction of change of the total width is determined. If it is increasing the value of PMOS is decreased and the value of NMOS is increased (step 920) . Then the method 900 moves to the step 922. Otherwise the value of PMOS is increased and the value of NMOS is decreased, so that the direction of change is increasing. The method 900 then also passes to the step 922. Step 922 resizes the other devices to match the NMOS and PMOS currents, and then returns to step 902. If the test at step 910 is passed, the method 900 moves to the step 926, where the direction of change of the total width is also evaluated. If it is increasing the PMOS value is increased and the NMOS value is decrease, and then the method 900 moves to the step 922. If the direction in change is decreasing, the method 900 moves to the step 928, where the PMOS value is decreased and the NMOS value is increased, and the method 900 moves to the step 922. Figure 10 is a flow chart of a method for optimizing either the NMOS width or the PMOS width of a predetermined logic gate. In step 1002, the parameters are initialized. In step 1004, a swtich is made depending on whether the MOS is an NMOS. If it isn't, the PMOS size is optimized using opt_p(), which is discussed later. If it is, the NMOS size is optimized using opt_n() , which is also discussed later. In any case, the best delay inside the height limit is determined from all previous runs, and the method moves to the step 1012. In step 1012, it is determined whether there is a better delay that is over the height limit, assuming that there is no limit on the height. If there is a better delay, the method 1000 goes to the step 1014, where the percentage delay improvement is compared to the square of the percentage increase in height. If the percentage delay improvement is greater than the square of the percentage increase in height, the method 1000 proceeds to the step 1018, which accepts the device sizes for this pass through the subroutine. The method 1000 then moves to the step 1016. If the percentage delay improvement is not greater than the square of the percentage increase in height, the method 1000 simply proceeds to the step 1016. Figure 11 is a flow chart of a method for optimizing the PMOS width of a predetermined logic gate. In step 1102 of the method 1100, it is determined whether the PMOS size has converged. If it has not converged, the method 1100 moves to the return step 1104. If it has converged, the method 1100 moves to the step 1106, where the standard cell height and standard load capacitance are set. In step 1108, the delay through the gate type with the sizes PMOS is calculated and the method 1100 moves to the step 1110. In step 1110 two evaluations are made. One evaluation is based on a comparison which determines whether the standard cell height is less than the height limit. If it is and the delay has improved, the method 1100 moves to the step 1126. The other evaluation is used if there is no hardlimit and the percentage delay improvement is greater than the square of the percentage increase in height. Again, if it is, the method 1100 moves to the step 1126. Failing these two possibilities, the method 1100 moves to the step 1112, where the p step size is compared to the minimum allowable. If it is too small, the method 1100 decreases p step sizes in step 1114 and moves to step 1116. Otherwise, the PMOS size has converged (step 1118) , and the method moves to the step 1116. In step 1116, the direction of change of the PMOS size is determined. If it is increasing the value of PMOS is decreased (step 1120) . Then the method 1100 moves to the step 1122. Otherwise the value of PMOS is increased, so that the direction of change is increasing. The method 1100 then also passes to the step 1122. Step 1122 does not resize the other devices, but returns to step 1102. If the test at step 1110 is passed, the method 1100 moves to the step 1126, where the direction of change of the total width is also evaluated. If it is increasing the PMOS value is increased, and then the method 1100 moves to the step 1122. If the direction in change is decreasing, the method 1100 moves to the step 1128, where the PMOS value is decreased, and the method 1100 moves to the step 1122. Figure 12 is a flow chart of a method for optimizing the NMOS width of a predetermined logic gate. In step 1202 of the method 1200, it is determined whether the NMOS size has converged. If it has not converged, the method 1200 moves to the return step 1204. If it has converged, the method 1200 moves to the step 1206, where the standard cell height and standard load capacitance are set. In step 1208, the delay through the gate type with the size NMOS is calculated and the method 1200 moves to the step 1210. In step 1210 two evaluations are made. One evaluation is based on a comparison which determines whether the standard cell height is less than the height limit. If it is and the delay has improved, the method 1200 moves to the step 1226. The other evaluation is used if there is no hardlimit and the percentage delay improvement is greater than the square of the percentage increase in height. Again, if it is, the method 1200 moves to the step 1226. Failing these two possibilities, the method 1200 moves to the step 1212, where the n step size is compared to the minimum allowable. If it is too small, the method 1200 decreases n step size in step 1214 and moves to step 1216. Otherwise, the NMOS size has converged (step 1218) , and the method 1200 moves to the step 1216. In step 1216, the direction of change of the NMOS size is determined. If it is increasing the value of NMOS is decreased (step 1220) . Then the method 1200 moves to the step 1222. Otherwise the value of NMOS is increased, so that the direction of change is increasing. The method 1200 then also passes to the step 1222. Step 1222 does not resize the other devices, but returns to step 1202. If the test at step 1210 is passed, the method 1200 moves to the step 1226, where the direction of change of the NMOS is also evaluated. If it is increasing the NMOS value is increased, and then the method 1200 moves to the step 1222. If the direction in change is decreasing, the method 1200 moves to the step 1228, where the NMOS value is decreased, and the method 1200 moves to the step 1222. The goal of high speed optimization is to achieve minimal gate delays without excessive area increase. The area increase is determined by the cell height, as the standard cell widths do not vary significantly with the device sizes. To accomplish this, a minimal standard cell height is computed, based on minimum sized NMOS and one and one half (1.5) times minimum PMOS. The standard cell height is allowed to grow nominally twenty five percent (25%) over this minimum. Beyond this 25%, the standard cell height is allowed to increase further only when the increase in speed exceeds the square of the height increase. The device sizes are calculated to fit into this standard cell height using iterative SPICE simulations which select the optimum NMOS and PMOS transistor sizes to minimize gate delays. The gate delay is measured as the average of the input rising and input falling delays for three gates in series. Unused inputs are connected high for NAND gates or low for nor gates. The load on each gate consists of the following gate plus a standard load. A standard load is based on the input capacitance of four clocked inverters plus a routing capacitance which is scaled by the standard cell height. This load changes as the device sizes are optimized, reflecting the effect of load capacitance as device sizes change. Optimization is done on a set of NAND and nor gates as identified in Table 3, "High Speed Gate Optimization Steps" determining the transistor sizes for that gate. SPICE based optimization establishes the one, two, and three in series NMOS and PMOS transistor sizes required to optimize the standard cell library for high speed operation. The four in series NMOS and PMOS transistor sizes are set such that four in series devices will provide the same pull up or pull down current as the three in series transistor sizes. However, the four in series devices sizes are limited to the maximum NMOS or PMOS device width as computed by the standard cell height routine in this step. A final static noise margin check insures that the high speed standard cell library meets the same noise margin requirements as the low power optimized cells. Figure 13 is a flow chart of a method for maximizing the speed of a predetermined logic gate. In step 1302 of the method 1300, the minimum width of NMOS is set to ba, while the minimum PMOS width, P_ls, is set to 50 percent greater than ba. In step 1304 other NMOS devices are sized to match the pulldown current of N_ls, and other PMOS devices are sized to match the pullup current of P_ls. Passing to step 1306 the standard cell height with the designated devices sizes is calculated. Next, in step 1308, 17 percent is added to the value of the height limit. In step 1310, the size of two-in-series NMOS is initialized to be large (i.e., 50 percent greater than N_2s) . Also the size of one-in-series PMOS is initialized to be small (= ba) . Next, the delay for a two-input NAND is minimized by iteratively running SPICE and adjusting device sizes, using the subroutine opt_np() . Following this, in step 1314, seven percent is added to the height limit. In step 1316, the delay for a two-input NOR is minimized by iteratively running SPICE and adjusting device sizes, using the subroutine opt_np() . Following this, in step 1318, the standard cell height is calculated with the new device size and used as the value of the height limit. In step 1320, the delay for a three-input NAND is minimized by iteratively running SPICE and adjusting device sizes, using the subroutine opt_n_orjp() . Following this, in step 1322, the standard cell height is calculated with the new device size and used as the value of the height limit. In step 1324, the delay for a three-input NOR is minimized by iteratively running SPICE and adjusting device sizes, using the subroutine opt_n_or_p() . Following this, in step 1326, the current for a three-in-series N-3s and the current for a three- in-series P_3s are found. Then, using these values in step 1328, the values for N_4s and P_4s are established as the minimum of the calculated values and the respective spaces available for NMOS and PMOS. Finally, in step 1330 the static NM is checked. While the foregoing is a detailed description of the preferred embodiment of the invention, there are many alternative embodiments of the invention that would occur to those skilled in the art and which are within the scope of the present invention. Accordingly, the present invention is to be determined by the following claims. -Ii

Claims: Claims 1. A method for designing a set of device specifications for a library of standard cell components for use in composing an integrated circuit, the method comprising the steps of: a) determining a process technology for building the components; b) determining an optimization criterion from a predetermined set of optimization criteria,- c) specifying a set of library-specific knowledge; and d) processing the set of library-specific knowledge as a function of the process technology and the optimization criterion and producing the set of device specifications therefrom. 2. The method of claim 1, wherein the predetermined set of optimization criteria includes speed of the components, area of the components, and power consumption of the components. 3. The method of claim 1, wherein the set of device specifications includes designations of device sizes and relative locations. 4. The method of claim 3, wherein the designations of device sizes include transistor gate widths. 5. The method of claim 3, wherein the designations of relative locations include locations of landmarks . 6. The method of claim 3, wherein the designations of relative locations include allocations of device type regions. 7. The method of claim 3, wherein the designations of relative locations include specification of connection points in the standard cell components. 8. A method for designing a set of device specifications for a library of CMOS standard cell components for use in composing an integrated circuit, each of the CMOS standard cell components including N-type transistors and P-type transistors, the method comprising the steps of: a) determining a process technology for building the CMOS standard cell components; b) determining an optimization criterion from a predetermined set of optimization criteria,- c) specifying a set of library-specific knowledge; and d) processing the set of library-specific knowledge as a function of the process technology and the optimization criterion and producing the set of device specifications therefrom. 9. The method of claim 8, wherein the predetermined set of optimization criteria includes speed of the components, area of the components, and power consumption of the components. 10. The method of claim 8, wherein the set of device specifications includes designations of device sizes and relative locations. 11. The method of claim 10, wherein the designations of device sizes include transistor gate widths. 12. The method of claim 10, wherein the designations of relative locations include locations of landmarks. 13. The method of claim 10, wherein the designations of relative locations include allocations of device type regions . 14. The method of claim 10, wherein the designations of relative locations include specification of connection points in the standard cell components. 15. The method of claim 10, wherein the designations of device sizes include relative sizes of the N-type transistors and the P-type transistors. 16. The method of claim 10, further including the step of: f) processing the set of device specifications by a parameterized library compiler. 17. The method of claim 16, further including the step of: g) producing the library from the parameterized library compiler. 18. An apparatus for designing a set of device specifications for a library of standard cell components for use in composing an integrated circuit, the apparatus comprising: an input circuit to specify a process technology for building the components,- an input circuit to specify an optimization criterion selected from a predetermined set of optimization criteria; a memory device to specify a set of library-specific knowledge; and a processing circuit to process the set of library-specific knowledge as a function of the process technology and the optimization criterion and producing the set of device specifications therefrom. 19. The apparatus of claim 18, wherein the predetermined set of optimization criteria includes speed of the components, area of the components, and power consumption of the components. 20. The apparatus of claim 18, wherein the set of device specifications includes designations of device sizes and relative locations.

Inventors: FISHER LOUIS C, JENSEN JOHN S, ROSSMAN THOMAS F, FISHER, LOUIS, C., JENSEN, JOHN, S., ROSSMAN, THOMAS, F.
Applicants: CASCADE DESIGN AUTOMATION, CASCADE DESIGN AUTOMATION CORPORATION
Application year: 1997
Main classification: G06F17
IPC codes: G06F17, H01L21