High-precision analog reading circuit for memory arrays, in particular flash analog memory arrays

Abstract: An analog reading circuit (10) comprising a current mirror circuit (19) forcing two identical currents into a cell (2) to be read and into a reference cell (27) and an operational amplifier (31) having an inverting input connected to the drain terminal (13) of the cell (2) to be read, a non-inverting input connected to the drain terminal (28) of the reference cell (27) and an output connected to the gate terminal (30) of the reference cell. The reference cell (27) therefore forms part of a negative feedback loop which maintains the overdrive voltages of the cell (2) to be read and the reference cell (27) constant, irrespective of temperature variations. The reading circuit (10) is also of high precision and has a high reading speed.

Description: The present invention relates to a memory device comprising memory cells, in particular flash memory cells, and a high-precision analog reading circuit for reading said memory cells. As is known and shown by way of example in Fig. 1, a flash memory array 1 comprises a plurality of flash cells 2 disposed in rows and columns, wherein the gate terminals of the cells 2 disposed in a same row are connected to a respective word line 3, the drain terminals of the cells 2 disposed in a same column are connected to a respective bit line 4 and the source terminals are generally connected to ground. The word lines 3 are collected to a row decoder 5 and the bit lines 4 are connected to a column decoder 6 which receive respective address and control signals from a control unit 7 which enables the selection, each time, of a single word line 3 and a single bit line 4 and thus access to the cell 2 connected to the word line and the selected bit line. A cell 2 may in particular be read by connecting the selected word line 3 to an external voltage V CPX of predetermined value (for instance 8-9 V) and by forcing a bias current I f into the selected bit line 4. Maintaining the selected cell in the linear region, the following equation is valid: I f = K* (W/L) *[(V CFX - V th ) - V DS /2]*V DS in which K is a constant connected with the manufacturing process, W/L is the width/length dimensional relationship of the cell, V th is the threshold voltage of the cell (i.e. the minimum voltage to be applied between the gate and source terminals of this cell so that it starts to conduct current) and V DS is the drain-source drop of the cell. In (1), the term K* (W/L)*V DS = GM f represents the transconductance (gain) of the cell and the term (V CPX - V th ) represents the overdrive of the cell. By appropriately biasing the cell, the drop V DS is constant and the term V DS /2 is negligible with respect to the overdrive (V CPX - V th ); in this condition the current I f flowing through the cell depends in a linear manner on the threshold voltage V th . During writing, the cell is selected by biasing the connected bit and word lines to respective predetermined programming voltage values. Writing takes place by means of the hot electron injection phenomenon, on the basis of which the high voltage supplied to the drain terminal of the cell to be written causes an increase in the velocity of the electrons and some of these achieve an energy sufficient to overcome the oxide barrier. By forcing a voltage on the gate terminal that is higher than the voltage at the drain terminal, the obtained electric field accelerates the electrons through the oxide layer that separates the channel region from the floating gate region and enables the entrapment of these electrons within the floating gate region. As a result of this entrapment of electrons, the cell modifies its threshold voltage. The phenomenon of hot electron injection is, by its nature, uncontrolled and cannot be repeated with precision; during programming, the cell is therefore read several times in order to read the achieved threshold voltage (verify phase). For this reason, an analog memory formed by flash cells has a storage precision that depends on the precision of reading. The threshold voltage is, moreover, highly dependent on the temperature and the manufacturing process used; this means that, in order to obtain a high level of precision and reliability, it is necessary to provide for solutions that ensure substantial insensitivity to variations in operating conditions. In order to enable high-precision reading of flash memory cells, a preceding European Patent Application 96830612.6 (EP-0 833 348) filed on 5 December 1996 in the name of the applicant and entitled "Method and circuit for checking multi-level programming of floating-gate nonvolatile memory cells, particularly flash-cells" discloses a closed-loop circuit in which a current of predetermined value is forced through a first terminal (for instance the drain terminal) of the cell to be read; this first terminal is connected to an input of an operational amplifier that also receives a reference voltage; the second terminal (for instance the source terminal) of the cell is connected to a predetermined potential and the output of the operational amplifier is connected to the gate terminal of the cell. In this way, a voltage directly proportional to the threshold voltage of the cell is present at the output of the operational amplifier and can be compared with the desired threshold voltage in order to decide whether or not to continue programming. This solution, although precise, raises the problem of the high capacitance associated with the drain terminal of the cell to be read, due to the sum of all the capacitances associated with the cells connected in parallel to the same bit line. This capacitance in effect introduces a pole into the transfer function which slows down the reading: In particular, the maximum speed that can be achieved, in terms of frequency, F MAX is given by the equation: F MAX =GM f /C p in which GM f is the transconductance of the cell, as defined above, and C p is the capacitance associated with the bit line in question. In (2) GM f cannot be modified as it depends on design and technology considerations; C p could be reduced by increasing the voltage applied to the drain terminal of the cell but, in order to avoid the risk of cancellation of the cell, this voltage cannot be excessively increased. The object of the invention is therefore to provide a memory, in particular a flash memory, having a reading circuit that remedies the drawbacks of known circuits. The present invention therefore relates to a memory device comprising a high-precision analog reading circuit, as defined in claim 1. A preferred embodiment of the present invention is described below, purely by way of non-limiting example, with reference to the accompanying drawings, in which: Fig. 1 shows a simplified circuit diagram of a flash memory of known type; Fig. 2 shows a simplified circuit diagram of the present reading circuit; Fig. 3 shows a more detailed circuit diagram of the present circuit. Fig. 2 shows a reading circuit 10 (also known as a "sense amplifier") for reading a cell 2 to be read belonging to the memory array 1 shown in Fig. 1. With respect to the memory array 1, Fig. 2 shows, for simplicity, only the cell 2 to be read addressed via the row decoder 5 and the column decoder 6; the row decoder 5 is not shown and only the essential components of the column decoder 6 are shown. In more detail and as shown in Fig. 2, the cell 2 to be read has a source terminal 11 connected to ground, a gate terminal 12 connected to a voltage source 15 supplying the reading voltage V CPX and a drain terminal 13 connected to a node 18 via a selection switch 16 and a first biasing transistor 17 of NMOS type belonging to the column decoder 6 of Fig. 1. The node 18 is connected to a current mirror circuit 19 formed by two PMOS transistors 21, 22; in more detail, the PMOS transistor 21 is diode-connected (i.e. has its drain and gate terminals short-circuited) and has its drain terminal connected to the node 18, its source terminal connected to the supply line 23 set at V dd and its gate terminal connected to the gate terminal of the PMOS transistor 22; the latter has its source terminal connected to the supply line 23 and its drain terminal connected to a node 24. The node 24 is connected, via a second biasing transistor 25 again of NMOS type and a dummy switch 26 that is always kept closed, to the drain terminal 28 of a reference cell 27, for instance a virgin cell, having a source terminal 29 connected to ground and a gate terminal 30 connected to the output of an operational amplifier 31; the latter has an inverting input connected to the node 18 and a non-inverting input connected to the node 24. Fig. 2 also shows some physical quantities useful for the following discussion, in particular the output voltage V o of the operational amplifier 31 which also forms the output voltage of the reading circuit 10, the voltage drop V DS,2 and V DS,27 between the drain and source terminals of the cell 2 to be read and the reference cell 27 respectively and the currents I 2 and I 27 flowing through these cells. The circuit of Fig. 2, as a result of the current mirror circuit 19, forces identical currents into the cell 2 to be read and into the reference cell 27 so that they have the same overdrive voltage. In this situation, the threshold voltage of the cell 2 to be read is proportional to the difference between its gate voltage and that of the reference cell 27 and threshold voltage variations due to temperature variations are identical in the cell 2 to be read and in the reference cell 27 and mutually compensate one another. In the circuit of Fig. 2, the function of the biasing transistors 17 and 25 is to maintain the cells 2 and 27 in the linear region and to prevent the cancellation of these cells when they are not selected, by keeping the voltage drop between the drain and source terminals of the cells 2 and 27 constant. The reference cell 27 is, moreover, inserted in a negative feedback loop (including, in addition to the reference cell 27 itself, the biasing transistor 25 and the operational amplifier 31) which ensures, via the voltage V o applied to the gate terminal 30 of the reference cell 27, the same overdrive voltage value for the cell 2 to be read and for the reference cell 27, as described in mathematical terms below. In more detail, assuming that the cell 2 to be read and the reference cell 27 have been produced in an identical manner using the same technology, on the basis of (1), the current I 2 flowing through the cell 2 to be read and the current I 27 flowing through the reference cell 27 are given by: I 2 = K* (W/L)* [(V CPX - V th,2 ) - V DS,2 /2]*V DS,2 I 27 = K* (W/L)* [(V o - V th,27 ) - V DS,27 /2]*V DS,27 in which V th,2 and V th,27 are the threshold voltages of the cell 2 to be read and the reference cell 27 respectively and the other quantities have the meaning described above. Supposing that the PMOS transistors 21 and 22 belonging to the current mirror circuit 19 and the biasing transistors 17 and 25 work at saturation, this gives: I 2 = I 27 In addition, in equilibrium, the voltages at the inputs of the operational amplifier 31 (voltages at the nodes 18 and 24) are equal and, given that the biasing transistors 17, 25 receive, at their gate terminal, the same biasing voltage V R (of 1.2-1.4 V for instance), they have the same gate-source drop; it follows, disregarding the voltage drop at the terminals of the selection switch 16 and the dummy switch 26, that: V DS,2 = V DS,27 The following can be obtained from (3) and (4), taking account of (5) and (6): V CPX - V th,2 = V o - V th,27 i.e., with the structure shown, the overdrive voltage of the cell 2 to be read is equal to the overdrive voltage of the reference cell 27. The following can, moreover, be immediately obtained from (7): V o = V CPX - (V th,2 - V th,27 ) i.e.: V th,2 = V CPX - V o + V th,27 It can be seen from (9) that the threshold voltage of the cell 2 to be read depends in a linear manner on the output voltage V o of the amplifier, as a result of which the reading of this output voltage, as the threshold voltage of the reference cell 27 and the reading voltage applied to the gate terminal of the cell 2 to be read are known, provides the required threshold value. Precise knowledge of the threshold voltage V th,27 of the reference cell 27 is not necessary either. For storing and successively reading the threshold voltage of the cell 2 to be read it is necessary only to know its relative value with respect to the threshold voltage of the reference cell 27, i.e. to know the value of the output voltage given by (8). This quantity V o also has the advantage that it is independent of temperature. Considering the threshold voltage to be due to the sum of two terms, a first at constant temperature (at 300°K) and a second dependent on temperature, the following relationships are valid for the cell 2 to be read and for the reference cell 27: V th,2 = V th,2 (300°K) + β (T) V th,27 = V th,27 (300°K) + β(T) and (8) becomes: V o = V CPX - [V th,2 (300°K) + V th,27 (300°K)] as a result of which the output voltage V o is independent of temperature variations. In the circuit of Fig. 2, at constant temperature conditions, it is not indispensable for the comparable components in the two branches comprising the cell 2 to be read and the reference cell 27 to be matched to one another (i.e. for the pairs 21-22, 17-25, 16-26 and 2-27 to be formed by components identical to one another) given that it is not necessary to know at the output the absolute threshold value but only its relative value, given by the voltage V o as explained above, and therefore small mismatches between the components of each pair do not affect the precision of reading. These mismatches do, however, have an impact in the case in which the reading conditions of the cell 2 differ from the writing conditions. Even so, as explained above, any small mismatches do not jepardize the operation of the reading circuit 10 in this case either. Let's assume in effect that there is a dimensional difference between the cell 2 to be read and the reference cell 27 that can be summarised by means of a variation ΔK of the factor K. In this situation, and disregarding the factor V DS,2 /2, (3) becomes: I 2 = (K + ΔK)* (W/L) * (V CPX - V th,2 ) * V DS,2 If (3') is combined with (4), disregarding the factor V DS,27 /2 and taking account of(10) and (11), this gives: V o = V CPX - [V th,2 (300°K) - V th,27 (300°K)] + (ΔK/K) * V CPX + - (ΔK/K) * V th,2 - (ΔK/K) * β (T). In (13), the first three terms are identical to (8), the fourth and fifth terms are constant and do not influence the precision of the reading device, as described above, and the sixth term (ΔK/K) * β (T) is the only temperature-dependent term; as shown, however, any change β of the threshold voltage due to temperature is reflected at the output reduced by the term (ΔK/K) and therefore in de-amplified mode. In the reading circuit of Fig. 2, the loop formed by the operational amplifier 31, the reference cell 27, the switch 26, the biasing transistor 25 and the PMOS transistor 22 forms a two-stage amplifier, whose first stage is formed by the operational amplifier 31 and whose second stage uses the reference cell 27 as an amplifier member. The biasing transistor 25 operates as a cascode member which supplies a high impedance to the output of the loop (node 24). This two-stage amplifier is thus compensated in the manner shown in the more detailed diagram of Fig. 3 as described below. Fig. 3 shows, in addition to the elements of Fig. 2, a compensating capacitor 40, a compensating transistor 41 and a current source 42. In more detail, the compensating capacitor 40 is connected between the node 24 and a node 43; the current source 42 is disposed between the supply line 24 and the node 43 and the compensating transistor 41 of PMOS type has its source terminal connected to the node 43, its gate terminal connected to the output of the operational amplifier 31 and its drain terminal connected to ground. Lastly, in Fig. 3, a capacitor 45, shown in dashed lines, represents the parasitic capacitance of the bit line to which the cell 2 to be read is connected; Fig. 3 also shows the transistors (of NMOS type) that form the switches 16 and 26 and a reset transistor 44 of NMOS type having its drain terminal connected to the intermediate node between the transistors 16 and 17, its source terminal connected to ground and its gate terminal receiving a control signal R. The compensating capacitor 40 gives rise to a pole at the Miller frequency, as a result of which the cut-off frequency of the amplifier formed by the members 22, 25, 26, 27 and 31 and by the capacitor 40 (disregarding, for the time being, the compensating capacitor 41) has a cut-off frequency F CO of: F CO = 1 2π GM OA C C in which GM OA is the transconductance of the operational amplifier and C C is the capacitance of the capacitor 41. ° The capacitor 40 gives rise, however, to a second pole at the frequency F II-p of F II-P = 1 2π GM f C D in which GM f is the transconductance of the reference cell 27, as defined above, and C D is the capacitance associated with the node 24. For reasons of stability, the cut-off frequency F CO must be at maximum equal to half the second pole frequency F II-P such that this second pole frequency represents the main factor influencing the reading speed. The transconductance GM f of the reference cell 27, of flash type, is very low and around 3-4 µA/V but fortunately the parasitic capacitance C D of the node 24 is low given that there is no load. This consequently makes it possible to obtain a decidedly high reading speed. The compensating capacitor 40 also gives rise to a right-plane zero at the frequency FZ of: F z = 1 2π GM f C c As is known to persons skilled in the art, this zero causes a delay of 90° as a result of which the loop, in the absence of the compensating transistor 41, would become unstable. This problem is resolved by the presence of the compensating transistor 41 which acts as a buffer in emitter-follower configuration and uncouples the output of the second stage of the amplifier (node 24) from the compensating capacitor 40. The advantages of the described reading circuit are the following. The structure described, by ensuring the same overdrive with respect to the cell 2 to be read and the reference cell 27, ensures that the threshold voltage of the cell to be read is linked to the difference between the gate voltages of the cell to be read and the reference cell; moreover, the possibility of using, as an operating quantity at the verify phase and during reading, the output voltage V o of the operational amplifier 31 rather than, directly, the threshold voltage of the cell to be read means that the quantity used is temperature-compensated. The use of the reference cell 27 within the feedback loop rather than the cell 2 to be read makes it possible substantially to increase the reading speed, given the lower capacitance associated with the reference cell 27 on its own with respect to the capacitance associated with the cell 2 to be read. Lastly, as mentioned above, the described reading circuit has good stability, with a simple and reliable structure. It is evident that many variations and modifications may be made to the reading circuit described and illustrated here, all of which come within the scope of the invention.

Claims: A memory device comprising memory cells, in particular flash cells, and a high-precision analog reading circuit (10) for reading said memory cells, the reading circuit (10) being connected to a first (2) and a second (27) cell each having a first (13, 28) and a second (11, 29) terminal and a control terminal (12, 30), said reading circuit (10) comprising first and second current source means (21, 22) connected to said first and second cells respectively and generating first and second currents respectively whcih are equal to each other, characterised in that it comprises negative feedback means (31) having a first and a second input connected to said first terminal (13) of said first cell (2) and to said first terminal (28) of said second cell (27) respectively and an output connected to said control terminal (30) of said second cell. A memory device according to claim 1, characterised in that said first cell (2) is an array cell to be read and said second cell (27) is a reference cell. A memory device according to claim 1 or 2, characterised in that said negative feedback means (31) comprise an operational amplifier having an inverting input connected to said first terminal (13) of said first cell (2) and a non-inverting input connected to said first terminal (28) of said second cell (27). A memory device according to any one of the preceding claims, characterised in that said first and second current source means (21, 22) form a current mirror circuit (19). A memory device according to any one of the preceding claims, characterised in that said first and second current source means (21, 22) are connected to said first terminal (13) of said first cell (2) and to said first terminal (28) of said second cell (27) respectively. A memory device according to claim 5, characterised in that it comprises a first (17) and a second (25) biasing transistor interposed between said first current source means (21) and said first terminal (13) of said first cell (2) and between said second current source means (22) and said first terminal (28) of said second cell (27) respectively, said first and second biasing transistors having respective control terminals connected reciprocally and receiving a common biasing signal. A memory device according to any one of the preceding claims, characterised in that said first terminal (13, 28) of said first and second cells (2, 27) is a drain terminal, said second terminal (11, 29) of said first and second cells is a source terminal and said control terminal (12, 30) of said first and second cells is a gate terminal. A memory device according to any one of the preceding claims, characterised in that it comprises a compensation circuit (40-42) interposed between said first terminal (28) of said second cell (27) and said output (30) of said negative feedback means (31). A memory device according to claim 8, characterised in that said compensation circuit (40-42) comprises a compensating capacitor (40) and a compensating transistor (41), said compensating capacitor (40) having a first terminal connected to said first terminal (28) of said second cell (2) and a second terminal connected to a first terminal (43) of said compensating transistor (41), said compensating transistor having a control terminal connected to said output (30) of said negative feedback means (31).

Inventors: CANEGALLO ROBERTO, CHIOFFI ERNESTINA, GERNA DANILO, PASOTTI MARCO, ROLANDI PIER LUIGI, CANEGALLO, ROBERTO, CHIOFFI, ERNESTINA, GERNA, DANILO, PASOTTI, MARCO, ROLANDI, PIER LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1997
Main classification: G11C27
IPC codes: G11C27, G11C16