Multiplying method with a round-off function and circuitry therefor

Abstract: A multiplying method with a negative/positive symmetrical round-off function and circuitry therefor are disclosed. When a product (24) is positive, a value having a (logical) ONE at the uppermost one of bits to be rounded and ZER0s at the lower bits is rounded up. When a product (24) is negative, a value having a (logical) ONE at the uppermost one of bits to be rounded and ZER0s at the lower bits is rounded down. This rounds off the product (24) such that a mean accumulative error when the product (24) is positive and a mean accumulative error when it is negative cancel each other. When a product (24) is positive, a correction term (21) having a ONE at the uppermost one of the bits to be rounded and ZER0s at the lower bits is applied to a subproduct adder (2) and an adder. For a negative product (24), the correction term (21) has a ZERO at the above uppermost bit and ZER0s at the lower bits.

Description: BACKGROUND OF THE INVENTION The present invention relates to a multiplication system for digital signal processing and, more particularly, to a multiplying method with a positive/negative symmetrical round-off function for reducing an error, and circuitry therefor. Multiplying circuitry with a round-off function has customarily been used to enhance the accuracy of the result of multiplication, as taught in, e.g., Japanese Patent Laid-Open Publication Nos. 6-053228 and 6-103304. However, the conventional multiplying circuitry has the following problems (1) through (3) left unsolved. (1) When a plurality of products are accumulated, desired accuracy is not achievable with the round-off function. Specifically, when a ONE is added to a bit just below the figure to be rounded off, the mean value of the figure to be rounded off is not a ZERO. The resulting errors are sequentially accumulated. (2) A method of the kind correcting an error is not feasible for a microprocessor or similar application which performs correction at each time of operation in order to store the result of operation in a register file. Specifically, assuming n-bit multiplication, a value for correcting an error appears only at a figure even lower than the lowermost bit of a 2n-bit product. Therefore, should the product be rounded of by correction at each time of calculation, the correction value would be rounded down and would thereby prevent the effect of correction from appearing in the resulting product. (3) The circuitry is not practicable without scaling up hardware. The circuitry proposed in the above Laid-Open Publication No. 6-103304, for example, additionally includes a subtracter for the correction of the mean error of round-off calculation. This scales up hardware and therefore increases the processing time. The prior art document EP-A-0 562 513 discloses a rounding operation circuit for arithmetic logic means of a signal processor provided for counting fractions over 1/2 as one and disregarding the rest for the positive and negative number, which comprises a decoder circuit having an (n+1)-long input to which a first input signal represented by two's complement and a second n-bit long input signal for specifying the rounded position of the first signal are entered, when the first input signal is positive, a signal in which the bit at the rounded position is "1" and the rest is "0" is emitted based on the second input signal and, when the first input signal is negative, a signal in which the bits less significant than the bit at the rounded position are all "1" and the rest is "0" is emitted; arithmetic logic means for adding the output signal of this decoder circuit and the first input signal; and a rounding-down circuit for counting 1 and cutting away 0 positively and negatively symmetrically to any rounding position, to allow a fast and accurate rounding operation. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a multiplying method capable of reducing an error particular to round-off and thereby enhancing accuracy in the event of multiplication and the accumulation of the results of multiplication, and circuitry therefor. It is another object of the present invention to provide a multiplying method guaranteeing accurate calculation even when applied to, e.g., a microprocessor completing multiplication and round-off by a single calculation, and circuitry therefor. It is another object of the present invention to provide multiplying circuitry needing a minimum of additional hardware and ensuring accurate calculation. There is provided a method by rounding a multiplication product as defined in claim 1. A multiplying circuitry carrying out the method is specified in claim 2. Further embodiments of the invention are also specified in the appended dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become apparent from the following detailed description taken with the accompanying drawings in which: FIG. 1 is a block diagram schematically showing conventional multiplying circuitry with a round-off function; FIG. 2 demonstrates the operation of the circuitry shown in FIG. 1; FIG. 3 is a block diagram schematically showing a conventional digital calculation system with a round-off function. FIG. 4 is a block diagram schematically showing a first embodiment of the multiplying circuitry with a round-off function in accordance with the present invention; FIG. 5 shows the principle of operation of the first embodiment; FIGS. 6A and 6B each shows a specific operation of the first embodiment; FIG. 7 is a schematic block diagram showing a second embodiment of the present invention; FIG. 8 shows the general configuration of a subproduct adder included in the second embodiment; FIG. 9 is a schematic block diagram showing a third embodiment of the present invention; and DESCRIPTION OF THE PREFERRED EMBODIMENTS To better understand the present invention, brief reference will be made to conventional multiplying circuitry with a round-off function, shown in FIG. 1. As shown, the multiplying circuitry is made up of a subproduct generator 1, a subproduct adder 2, and an adder 3. A multiplicand X and a multiplier Y are input to the subproduct generator 1. The subproduct generator 1 outputs a plurality of subproduct terms 24. Assuming eight bits, the subproduct generator 1 outputs five terms by using the Booth's method. When the five terms are added by the subproduct adder 2, two terms 25 are left. The adder 3 adds the two terms 25 and thereby outputs a product Z. When a multiplier and a multiplicand each having n bits are multiplied, a 2n-bit product is produced. The 2n-bit product is rounded off to n bits because the subsequent calculation often has only an accuracy of n bits. For example, when upper n bits are selected, the lower n bits are rounded off by rounding up, rounding down or rounding to the nearest whole number. Rounding to the nearest whole number is desirable from the accuracy standpoint. Specifically, when the bit just below the upper n bits is a ONE, it will be rounded up; when such a bit is a ZERO, it will be rounded down. When a multiplier and a multiplicand each having eight bits are multiplied, the product before round-off has sixteen bits. In this case, binary "10000000" is added to the lower eight bits of the sixteen-bit product for correction, and then the upper eight bits are produced. This can be done if the subproduct adder 2 is provided with an extra input 21 and if the correction term (round-off correction term) is applied to the input 21. The two terms 25 output from the subproduct adder 2 are added by the adder 3. As shown in FIG. 2, the product output from the conventional circuitry of FIG. 1, whether it be positive or negative, is rounded off to the nearest greater value if a portion to be rounded off is greater than binary "10000000" or rounded down if it is smaller than "01111111", as indicated by dots. Circles shown in FIG. 2 show that the above portion does not included such a value. Signal processing, for example, often involves the addition of a plurality of products. In this respect, the round-off procedure of the kind described has a problem that the mean value of rounded portions is not a ZERO and appears in the form of an error. To reduce a mean accumulative error, Japanese Patent Laid-Open Publication No. 6-103304 mentioned earlier proposes a method which subtracts, before round-off, a mean error to be rounded off. Specifically, this document teaches a digital calculation system including a plurality of error correction circuits each preceding a particular round-off circuit other than the first round-off circuit. Each error correction circuit subtracts an error correction value in order to obviate a difference between the actual result and the ideal result. More specifically, as shown in FIG. 3, a multiplier 10 multiplies a multiplicand X and a multiplier Y. An adder 11 adds an addition term. A subtracter 12 subtracts a correction term for cancelling a mean error from the output of the adder 11. Finally, a round-off unit 13 rounds of the output of the subtracter 12 and outputs a product Z. The conventional technologies described with reference to FIGS. 1-3 have some problems left unsolved, as discussed earlier. Preferred embodiments of the present invention free from the problems of the conventional technologies will be described hereinafter. 1st Embodiment Referring to FIG. 4, multiplying circuitry with a round-off function embodying the present invention is shown. As shown, the circuitry has a subproduct generator 1 to which a multiplicand X and a multiplier Y are input, a subproduct adder 2, an adder 3, and an XNOR (Exclusive NOR) gate 4 to which the sign bits of the multiplicand X and multiplier Y are input. A round-off correction term 21 is input to the subproduct adder 2. The output of the XNOR gate 4 is applied to the adder 3 as a carry input 20. The subproduct generator 1 produces a plurality of subproduct terms 24 from the multiplicand X and multiplier Y input thereto. For example, when the multiplicand X and multiplier Y have eight bits each, the subproduct generator 1 outputs five subproduct terms 24 by use of the Booth's method. The subproduct terms 24 are input to the subproduct adder 2 and added thereby. The subproduct adder 2 is implemented by, e.g., a carrier save adder. The round-off correction term 21 is input to the subproduct adder 2 together with the subproduct terms 24. In the correction term 21, the uppermost bit of the figure to be rounded off is a ZERO while the bits lower than the uppermost bit are ONEs. For example, assume that the multiplicand X and multiplier Y have eight bits each, and that the upper eight bits should be left as a result of calculation while the lower eight bits should be rounded off. Then, the correction term 21 is binary "01111111". The subproduct adder 2, implemented by a carry save adder by way of example, outputs two results 25 of subproduct addition. The adder 3 adds the two outputs 25 of the subproduct adder 2 and produces a product Z. The sign bits of the multiplicand X and multiplier Y are input to the XNOR gate 4. The XNOR gate 4 outputs a ONE if the product is positive or outputs a ZERO if it is negative. The output of the XNOR gate 4 is applied to the carry input 20 of the adder 3. The operation of the illustrative embodiment will be described hereinafter. First, reference will be made to FIG. 5 for describing how the result of multiplication is rounded off. In FIG. 5, each portion extending from a circle to a dot is the range to be rounded off; the dot is included in this range, but the circle is not included. If the result of multiplication is positive, and if the figure just below the figure to be rounded off is a ONE, then the result is rounded up, as in the conventional system. If the figure just below the figure to be rounded off is a ZERO, then the result of multiplication is rounded down, as in the conventional system. This kind of scheme corresponds to a round-off procedure which rounds up values above 0.5 inclusive and rounds down values below 0.5. Assume the above result of multiplication is negative, and that only the figure just below the figure to be rounded off is a ONE while the figures below it are ZEROs. Then, values smaller than the above value are rounded down while values greater than the same are rounded up. This corresponds to a negative round-off procedure which rounds down values below 0.5 inclusive and rounds up values above 0.5. With the above calculation, the illustrative embodiment allows a mean error output when the result is positive and a mean error output when it is negative to cancel each other. Consequently, the error is substantially zero when evenly spread products are accumulated. FIGS. 6A and 6B demonstrate the fact that the illustrative embodiment produces the result shown in FIG. 5. Although FIGS. 6A and 6B show four-bit multiplication, the embodiment is practicable with any desired bit length. As shown in FIG. 6A, assume "1000" (= -8) and "1001" (= -7) as an exemplary multiplicand X and an exemplary multiplier Y, respectively, providing a positive product and providing lower four bits of "1000". The product of these multiplicand X and multiplier Y is "00111000" (= 56) having eight bits. In this case, the correction term 21 to be input to the subproduct adder 2 is "0111". When the product is positive, the sign bit of the multiplicand X and that of the multiplier Y have the same value, causing the XNOR gate 4 to output "1". Because the product (= "00111000"), correction term (= "0111") and the output of the XNOR gate 4 (= "1") are added, the result (corrected product) is "01000000". When this result is rounded off, "0100" is produced (see CORRECTED PRODUCT shown in FIG. 6A). In this manner, when the result is positive, "1000" is rounded up. As shown in FIG. 6B, assume "1000" (= -8) and "0001" (= 1) as an exemplary multiplicand X and an exemplary multiplier Y, respectively, providing a negative product and lower four bits of "1000". The product is "11111000" (= -8). In this case, the correction term 21 is "0111". When the product is negative, the sign bit of the multiplicand X and that of the multiplier Y are different from each other, causing the XNOR gate 4 to output "0". As a result, the sum of the product, correction value and the output of the XNOR gate 4 is "11111111". This result is rounded to "1111" (see CORRECTED PRODUCT shown in FIG. 6B). When the result is negative, "1000" is rounded down. As stated above, when the product is positive, a value having a ONE at the uppermost one of the bits to be rounded (fourth bit) and ZEROs at the lower bits is used as a correction value ("0111" + "1" = "1000"). When the product is negative, a value having a ZERO at the uppermost one of the bits to be rounded and ONEs at the lower bits is used as a correction value (= "0111"). This coincides with the result shown in FIG. 5. 2nd Embodiment Referring to FIG. 7, an alternative embodiment of the present invention will be described. In FIG. 7, the same or similar structural elements as or to the elements shown in FIG. 4 are designated by like reference numerals. As shown, a multiplicand X and a multiplier Y are input to the subproduct generator 1. A plurality of subproduct terms 24 are added by the subproduct adder 2. The round-off correction value 21 is input to the subproduct adder 2 together with the subproduct terms 24. The subproduct adder 2, implemented by a carry save adder by way of example, outputs two terms 25. The adder 3 adds the two terms 25 and outputs a product Z. The XNOR gate 4 receives the sign bits of the multiplicand X and multiplier Y and outputs a ONE if the product is positive or outputs a ZERO if it is negative. In the illustrative embodiment, the output 22 of the XNOR gate 4 is also applied to the subproduct adder 2. In this embodiment, the subproduct adder 2 has a configuration shown in FIG. 8. As shown, the subproduct terms output from the subproduct generator 1 have bits sequentially shifted in correspondence to the figure positions of the multiplier Y. Specifically, assuming eight-bit multiplication and the Booth's method, five subproduct terms 24 are output. Four (24 1 -24 4 , FIG. 8) of the five subproducts terms 24 have nine bits each. One (24 1 ) of the four terms (24 1 -24 4 ) includes the lowermost bit of the product. Three (24 2 -24 4 ) of the remaining terms each is shifted by two bits to the upper position. The last term (24 5 ) has sixteen bits. As shown in FIG. 8, because addition is executed on a bit basis, the number of terms to be added is small at the bits close to the uppermost bit and lowermost bit, but it is great at the center. Numerals associated with SUBPRODUCT ADDER 2 in FIG. 8 indicate the numbers of inputs. For example, assuming eight-bit multiplication, a single term is added at the uppermost bit, three terms including the correction term 21 are added at the lowermost bit, and six terms are added at the seventh bit, as counted from the lowermost bit, at the center. A positive/negative correction term 22 is applied to the input of the subproduct adder 2 assigned to the lowermost bit and added to the lowermost bit thereby. As a result, the number of terms to be added at the lowermost bit increases to four. This, however, has no influence on the overall processing time, considering the fact that the maximum number of bits to be added is six. 3th Embodiment FIG. 9 shows a further alternative embodiment of the present invention which is applied to product sum calculation. In FIG. 9, the same or similar structural elements as or to the elements shown in FIG. 4 are designated by like reference numerals. As shown, the subproduct generator 1 produces a plurality of subproduct terms 24 from a multiplicand X and a multiplier Y. The subproduct adder 2 adds the subproduct terms 24, round-off correction term 21 and an addition term A. The subproduct adder 2 outputs two values 25. The adder 3 adds the two values 25 output from the subproduct adder 2. The signs of the multiplicand X and multiplier Y are fed to the XNOR gate 4. The XNOR gate 4 outputs a ONE if the product is positive or outputs a ZERO if it is negative. The output of the XNOR gate 4 is applied to the carry input 20 of the adder 3. Assume that the circuitry shown in FIG.9 is built in, e.g., a microprocessor. Then, the multiplier, multiplicand and addition term have the same number of bits, n , because they are produced from a register file. While the resulting product has 2n bits, n bits are produced by round-off. Because the bit positions of the addition term are matched to the n bits to be produced, the values of the bits relating to round-off are derived from multiplication. Therefore, the rounding direction may be determined on the basis of the sign of the result of multiplication. The associative law does not hold with the round-off procedure. Therefore, although the addition term may have 2n bits, the result would depend on the order of calculation if round-off were not executed with the multiplication term. It follows that when round-off is effected at each time of calculation, it is reasonable to executed round-off only with the product. The first to third embodiments shown and described may be summarized, as follows. A subproduct adder (2, FIG. 4) adds subproduct terms (24, FIG. 4) and a correction term (21, FIG. 4) in which the uppermost one of bits to be rounded is a ZERO and the lower bits are ONEs. When the product is positive, as indicated by the sign bit of a multiplicand and that of a multiplier, a ONE is output while, when the product is negative, a ZERO is output. This ONE or ZERO is applied to the carry input (20, FIG. 4) of an adder (3, FIG. 4) or to the lower bit input (22, FIG. 7) of the subproduct adder. As a result, the product is rounded to the nearest whole number without regard to its sign. Specifically, the subproduct adder and adder add, when the product is positive, a value having a ONE at the uppermost one of the bits to be rounded and ZEROs at the lower bits or add, when the product is negative, a value having a ZERO at the uppermost one of the bits to be rounded and ONEs at the lower bits. In the illustrative embodiments, because the mean value of the portions to be rounded is not a ZERO, an error ascribable to the round-off of products appears when the products are accumulated. However, round-off when the product is positive and round-off when it is negative are symmetrical to each other, allowing an error in the former case and an error in the latter case to cancel each other. As a result, the error at the time of accumulation is substantially zero, enhancing accurate calculation. Further, because only the product is rounded to the nearest whole number, the effect of correction is not deteriorated even if round-off is executed at each time of calculation. Therefore, desirable effects are achievable even when the embodiments are applied to a microprocessor of the type executing round-off with the result of every calculation. In summary, it will be seen that the present invention provides multiplying circuitry with a round-off function and having various unprecedented advantages, as enumerated below. (1) The circuitry reduces an error at the time of accumulation of products. Specifically, round-off when the product is positive and round-off when it is negative are symmetrical to each other, allowing a mean accumulative error in the former case and a mean accumulative error in the latter case to cancel each other. As a result, the error at the time of accumulation is substantially zero. (2) The circuitry is desirably applicable even to, e.g., a microprocessor executing multiplication to round-off by a single calculation. Specifically, the circuitry simply performs rounding to the nearest whole number, as distinguished from subtraction of a correction term using bits exceeding calculation accuracy. As a result, the bits left after round-off reflect both the effect of round-off and the effect of error cancellation. (3) The circuitry needs a minimum of additional hardware because only an XNOR gate for determining the sign of a product and an arrangement for adding it are added. To add the sign of a product, use may be made of the carry input of an adder, or the addition tree of the lowermost bit of a subproduct adder may be changed from a three-input configuration to a four-input configuration.

Claims: A method of rounding a multiplication product (24) applicable to a multiplier or a product sum calculator, wherein the multiplication product (24) is obtained by multiplying a multiplicand (X) and a multiplier (Y) both represented in a 2's complement form, and the multiplication is performed by adding subproducts (24 1 -24 5 ) which are shifted in accordance with the bits of the multiplier (Y), and the multiplication product (24) is rounded according to the steps: a correction term (21) in which the uppermost one of bits to be rounded is a ZERO and the lower bits are ONEs is added together with the subproducts (24 1 -24 5 ) in order to obtain a first rounded multiplication product (24), and a positive/negative correction term (22) is determined in dependence of the sign of the multiplication product (24) as indicated by the sign bits of the multiplicand (X) and the multiplier (Y) and is added to the lowermost bit of said first rounded multiplication product, wherein the positive/negative correction term (22) is determined to be ONE, if the sign is positive, and to be ZERO, if the sign is negative. A multiplying circuit comprising means adapted to carry out the steps of the method of rounding a multiplication product (24) according to claim 1, which comprises: means (2,3) for adding the subproducts (24 1 -24 5 ), the correction term (21) and the positive/negative correction term (22); means (4) for selecting the positive/negative correction term (22) in dependence of the sign of the multiplication product (24) which outputs the positive/negative correction term (22)to the adding means (2,3). A multiplying circuit according to claim 2, wherein the adding means (2,3) comprises a subproduct adder (2) and an adder (3) for adding the partial products (24 1 -24 5 ), the correction term (21) and the positive/negative correction term (22). A multiplying circuit according to claim 2 or 3, wherein the subproduct adder (2) is a carry save adder and the positive/negative correction term (22) is coupled to the carry save adder. A multiplying circuit according to any one of claims 2 to 4, wherein the selecting means (4) is a XNOR gate having two inputs coupled to the sign of the multiplicand (X) and the multiplier (Y), respectively, and one output coupled to the carry input of the adding means (2,3).

Inventors: SUZUKI KAZUMASA, SUZUKI, KAZUMASA
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1997
Main classification: G06F7
IPC codes: G06F7, G06F17