METHOD FOR FORMING ULTRA-THIN GATE OXIDES

Abstract: This invention improves the quality of gate oxide dielectric layers using a two-pronged approach, thus permitting the use of much thinner silicon dioxide gate dielectric layers required for lower-voltage, ultra-dense integrated circuits. In order to eliminate defects caused by imperfections in bulk silicon, an in-situ grown epitaxial layer is formed on active areas following a strip of the pad oxide layer used beneath the silicon nitride islands used for masking during the field oxidation process. By growing an epitaxial silicon layer prior to gate dielectric layer formation, defects in the bulk silicon substrate are covered over and, hence, isolated from the oxide growth step. In order to maintain the integrity of the selective epitaxial growth step, the wafers are maintained in a controlled, oxygen-free environment until the epitaxial growth step is accomplished. In order to eliminate defects caused by a native oxide layer, the wafers are maintained in a controlled, oxygen-free environment until being subjected to elevated temperature in a controlled, oxidizing environment. In one embodiment, the oxidizing environment comprises diatomic oxygen, while in another embodiment, the oxidizing environment comprises diatomic oxygen and ozone.

Description: METHOD FOR FORMING ULTRA-THIN GATE OXIDES Field of the Invention This invention relates to integrated circuit manufacture and, more particularly, to the formation of ultra-thin high quality gate oxides that are useable in flash and dynamic random access memories. Background of the Invention The thermal oxidation of silicon in a dry, oxygen ambient is a vital element in the manufacture of integrated circuits. Thermal oxides are used routinely as gate dielectric layers for field-effect transistors. As device dimensions are scaled down to increase circuit density, increasingly lower voltages are necessary to prevent channel punch-through and reduce the parasitic transistor effect between adjacent devices. With lower voltages, thinner gate dielectric layers are required. For example, the current of 4-megabit dynamic random access memories (DRAMs) typically uses gate oxide layers having a thickness within a range of 200 to 25θA for both memory array and peripheral transistors. For 16-megabit DRAMs, this figure is expected to fall to 150 to 20θA; for 64-megabit and 256-megabit DRAMs, the thickness is expected to fall still further. For electrically-programmable memories such as electrically- erasable programmable read-only memories (EEPROMs) and flash memories, even thinner gate oxide layers are required to facilitate Fowler-Nordheim tunneling (universally used as the erase mechanism and often as the write mechanism). For the current generation of 4-megabit flash memories, 11 OA- thick gate oxide layers are the norm. For future generations of more dense flash memories, gate oxide layers are expected to drop to the 80 to 90 range. As gate oxide layers become thinner, it becomes increasingly important that such layers be defect free in order to eliminate leakage. Defects in the gate oxide layer have several sources. One major source of defects is the imperfections in the single-crystal bulk silicon from which starting wafers are manufactured. Such imperfections in the 10 single-crystal silicon lattice generally result from impurities, which may include metal atoms. Thermal growth of an oxide layer on top of bulk silicon will result in "pin holes" in the dielectric at the defect sites. Another major source of defects is the low quality of the native silicon dioxide which forms at room temperature on exposure to the atmosphere. Prior processes for forming a gate dielectric layer typically begin with a cleaning step which normally consists of a short-time dip in a hydrofluoric acid bath. Following the cleaning step, the wafers are generally exposed to the atmosphere, at which time a 3 to 7A-thick layer of native oxide forms on the surface of exposed bare silicon. The defects in native silicon dioxide are the result of the low temperature of formation (which results in oxides of uneven stoichiometry) and the uncontrolled content of the atmosphere (which results in trace amounts of compounds other than silicon dioxide). U.S. Patent No. 4,656,054 to Inoue describes a method of manufacturing a semiconductor device involving a capacitor, the primary object being to improve the method of mass-manufacturing chips containing a larger- capacitance capacitor. It does teach selectively growing a silicon layer on the substrate surface by an epitaxial growth method and then forming a gate oxide film by thermal oxidation. However, the objective of Inoue is to create a capacitor, the capacitance being controlled by the pattern and depth of etching into the insulation layer. Inoue's focus is on the ability to repeatably produce the same pattern of depressions and does not include any mention of a controlled manufacturing environment or an attempt to maximize the quality of the gate oxide layer. Inoue teaches improving capacitor performance and Inoue does not consider the quality of the substrate surface prior to the epitaxial growth step. U.S. Patent No. 5,013,681 to Godbey teaches removal of silicon oxide present on the active area after the wafer is placed in the growth chamber. U.S. Patent No. 4,870,245 to Price teaches an apparatus for plasma enhanced thermal treating of silicon-bearing materials. Price does not described increasing the effectiveness of fabrication steps through plasma enhancement. U.S. Patent No 5,304,221 to Atherton teaches a process for modelling and controlling production integrated processing equipment (PIPE), although in the Background of the Invention section it makes passing reference to PIPEs being able to minimize human involvement and operate in a controlled environment, although "controlled environment" is not defined in Atherton. What is lacking in the art is an improved method of forming silicon dioxide for use as gate dielectric layers which are less prone to leakage than those which are conventionally grown. Summary of the Invention The present invention improves the quality of gate oxide dielectric layers by using a two-pronged approach. In order to eliminate defects caused by imperfections in the bulk silicon, an in-situ grown epitaxial layer is formed on active areas following a strip of the pad oxide layer used beneath the silicon nitride pattern used for masking during the field oxidation process. By growing an epitaxial silicon layer prior to gate dielectric layer formation, defects in the bulk silicon substrate are covered over and, hence, isolated from the oxide growth step. In order to maintain the integrity of the selective epitaxial growth step, the wafers are maintained in a controlled, oxygen-free environment until the epitaxial growth step is accomplished. In order to eliminate defects caused by a native oxide layer, the wafers are maintained in a controlled, oxygen-free environment until being subjected to elevated temperature in a controlled, oxidizing environment. In one embodiment, the oxidizing environment comprises diatomic oxygen, while in another embodiment, the oxidizing environment comprises diatomic oxygen and ozone. Brief Description of the Drawings Figure 1 is a cross-sectional view of a portion of an in-process semiconductor wafer immediately following field oxidation; Figure 2 is a cross-sectional view of the portion of an in-process semiconductor wafer depicted in Figure 1 following removal of the silicon nitride masking layer and the pad oxide layer; Figure 3 is a cross-sectional view of the portion of an in-process semiconductor wafer depicted in Figure 2 following selective epitaxial growth of a silicon layer on top of the active areas; and Figure 4 is a cross-sectional view of the portion of an in-process semiconductor wafer depicted in Figure 3 following a thermal oxidation step. Preferred Embodiment of the Invention The method for forming a high quality gate oxide layer on a bulk silicon active area will be explained in the context of a conventional integrated circuit process flow. Referring now to Figure 1 , a semiconductor wafer has been subjected to a conventional field oxidation process known as LOCOS. The process involved forming a pad oxide layer 1 1 on top of the entire wafer, depositing an oxygen-impermeable silicon nitride layer on top of the pad oxide layer, patterning and etching the silicon nitride layer to form silicon nitride islands 12 which masked the active areas 13, and subjecting the wafer to an oxidation step which has formed field oxide regions 14. Referring now to Figure 2, the silicon nitride islands 12 have been stripped, following which the pad oxide layer 11 that was beneath the islands is stripped in an oxygen-free environment to prevent a native oxide layer from forming on the exposed substrate once the pad oxide layer 11 is stripped. Referring now to Figure 3, with the in-process wafer of Figure 2 still being maintained in an oxygen-free environment, an epitaxial silicon layer 31 is selectively grown on top of the active areas 13. With selective epitaxial growth, no silicon is deposited on the field oxide regions 13. At an atomic level during the epitaxial growth step, silicon atoms possessing high surface mobility are deposited on the bare single-crystal silicon substrate in the active areas. The atoms migrate to sites on the single crystal substrate where nucleation is favored, thus forming a virtually defect-free layer of epitaxial silicon on top of the silicon substrate in the active areas 13. Referring now to Figure 4, the in-process wafer is subjected to a thermal oxidation step, which oxidizes an upper portion of the epitaxial layer 31 to form a gate oxide layer 41. The oxidation step is allowed to proceed until the appropriate thickness of gate oxide is achieved, it is essential that between the epitaxial growth step depicted in Figure 3 and the oxidation step depicted in Figure 4, the wafer be protected from the atmosphere to prevent the formation of a native oxide layer on the active areas. Thus, the wafer must either be maintained in an inert atmosphere or in a vacuum chamber in which the partial pressure of oxygen is very nearly zero. Processing of the wafer following the formation of the high-quality gate oxide layer 41 may be entirely conventional, with a polysilicon layer or a layer of other material suitable for gate electrodes being deposited on top of the gate oxide layer 41. The polysilicon layer is doped, then patterned and etched to form gate electrodes. Through the process of the present invention, the quality of gate oxide dielectric layers is thus improved by using the two-pronged approach described above. In order to eliminate defects caused by imperfections in the bulk silicon, an in-situ grown epitaxial layer is formed on active areas following a strip of the pad oxide layer used beneath the silicon nitride pattern used for masking during the field oxidation process. By growing an epitaxial silicon layer prior to gate dielectric layer formation, defects in the bulk silicon substrate are covered over and, hence, isolated from the oxide growth step. In order to maintain the integrity of the selective epitaxial growth step, the wafers are maintained in a controlled, oxygen-free environment until the epitaxial growth step is accomplished. In the alternative, the controlled environment is a low-pressure, virtually oxygen-free environment. In order to eliminate defects caused by a native oxide layer, the wafers are maintained in a controlled, oxygen-free environment until being subjected to elevated temperature in a controlled, oxidizing environment. In one embodiment, the oxidizing environment comprises diatomic oxygen, while in another embodiment, the oxidizing environment comprises diatomic oxygen and ozone. Although only a single embodiment of the invention has been disclosed herein, it will be obvious to those having ordinary skill in the art of integrated circuit manufacture that certain changes and modifications may be made thereto without departing from the scope and the spirit of the invention as hereinafter claimed.

Claims: We claim: 1. A method for forming a high quality gate oxide layer on a bulk silicon active area of a silicon wafer, said method comprising the following sequence of steps: (a) placing the wafer in a controlled environment; (b) selectively growing an epitaxial silicon layer on the surface of the active area while in the controlled environment; and (c) thermally oxidizing at least a portion of the epitaxial layer while in the controlled environment. 2. The method of Claim 1, wherein said controlled environment is an oxygen-free environment. 3. The method of Claim 1, wherein said controlled environment is a low- pressure, virtually oxygen-free environment. 4. The method of Claim 1 , wherein the active area is kept completely free of oxides of silicon prior to step (a). 5. A method of forming integrated circuitry on the bulk silicon active area of a wafer of single-crystal silicon while maintaining the wafer in a controlled environment, said method comprising the following sequence of steps: (a) forming a mask pattern on the surface of the wafer that covers future active areas with a layer of oxygen-impermeable material and exposes future field isolation regions; (b) oxidizing the exposed surfaces of the wafer to form field isolation regions; (c) stripping the mask pattern; (d) selectively growing an epitaxial silicon layer on the surface of the active areas; (e) thermally oxidizing at least an upper portion of the epitaxial layer to form a gate dielectric layer; (f) depositing a gate electrode layer on top of the gate dielectric layer; and (g) patterning the gate electrode layer to form gates for field effect transistors. 6. The method of Claim 5, wherein said controlled environment is an oxygen-free environment. 7. The method of Claim 5, wherein said controlled environment is a low- pressure, virtually oxygen-free environment. 8. The method of Claim 5, wherein the active area is kept completely free of oxides of silicon prior to step (d).

Inventors: LEE RUOJIA, THAKUR RANDHIR P S, LEE, RUOJIA, THAKUR, RANDHIR, P., S.
Applicants: MICRON TECHNOLOGY INC, MICRON TECHNOLOGY, INC.
Application year: 1997
Main classification: H01L21
IPC codes: H01L21, H01L27, H01L29