Voltage controlled oscillator

Abstract: The voltage controlled oscillator comprising a ring oscillator outputs an oscillating signal of which the duty cycle is almost 50% in spite of the high frequency. Each of the delay inverting circuits in the ring oscillator varies the output signal from the "L" level to the "H" level for the constant delay time tr when the input signal varies the "H" level to the "L" level. It also varies the output signal from the "H" level to the "L" level for the variable delay time tf in response to the delay control voltage Vc when the input signal varies the "L" level to the "H" level. The output signal from the ring oscillator comprising the delay inverting circuits is applied to another delay inverting circuit. The another delay inverting circuit responses at the constant delay time tr when the input signal varies the "H" level to the "L" level, and responses at the delay time tf/2 in accordance with the delay control voltage Vc when the input signal varies the "L" level to the "H" level. As a result, the another delay inverting circuit outputs an oscillating signal of which the duty cycle is almost 50%.

Description: The present invention relates to a voltage controlled oscillator (hereinafter, called VCO) which can control an oscillating frequency by connecting inverting logic circuits of an odd number in a ring and by controlling a delay time in each of the inverting logic circuits with a control voltage. The present invention relates also to a method of controlling a VCO. FIG. 6 is a structural view illustrating a conventional VCO of a ring circuit. The VCO is provided with three delay inverting circuits 1, 2, 3 connected in a ring. These delay inverting circuits 1-3 are logic circuits, each of which compares an input signal into an input terminal A with a reference voltage Vr applied to an input terminal B and outputs a signal of a logic level inverted in accordance with a compared result to an output terminal C. Each of the delay inverting circuits 1-3 is provided with a control terminal D, and controls a delay time of an output signal from an output terminal C with a delay control voltage Vc applied to the control terminal D. That is, each of the delay inverting circuits 1-3 is provided with an inverting circuit comparing the input signal with the reference voltage Vr and outputting an inverted signal and a delay circuit connected to an output of the inverting circuit. The delay circuit comprises a charge part which is a capacitor and a discharge part which is a transistor of which an continuity condition is controlled by the delay control voltage Vc. The output of the delay inverting circuit 3 is connected to the input of the delay inverting circuit 1 and is inputted into a logic gate 4 for wave forming. A oscillating signal OUT of which a wave form is arranged to be rectangular is outputted into the output of the logic gate 4. In this VCO, for example, when the input of the delay inverting circuit 1 is the level "L" at a time that a power is supplied, after the delay time by the operation in the delay inverting circuits 1-3, a signal of the level "H" is outputted from the output of the delay inverting circuit 3. Since this signal is fed back to the input of the delay inverting circuit 1, after the delay time by the further operation in the delay inverting circuits 1-3, the output of the delay inverting circuit 3 turns to the "L" level. In this way, the oscillating operation of which a frequency is a ring delay time by the operation in the delay inverting circuits 1-3 is carried out. Now, the following operation is carried out in each of the delay inverting circuits 1-3. That is, when the output signal from the inverting circuit varies from the "L" level to the "H" level, the charge part in the delay circuit is charged in a constant short time and the output signal from the delay circuit becomes the "H" level. On the contrary, when the output signal from the inverting circuit varies from the "H" level to the "L" level, the electric charges held in the charge part are discharged in accordance with a time constant of the discharge part in the delay circuit and the output voltage of the delay circuit lowers continuously. Then, the output signal becomes the "L" level after a time passes. The time constant is controlled by the delay control voltage Vc applied to the delay circuit in the delay inverting circuits 1-3 from the control terminal D, therefore, it is possible to control the oscillating frequency by the delay control voltage Vc. However, there is a problem in the conventional VCO as follows. That is, in the control of the oscillating frequency, the delay time, when the output signal in each of the delay inverting circuits 1-3 varies from the "H" level to the "L" level, is controlled and the ring delay time is controlled, whereby the oscillating frequency is controlled. As to the oscillating signal, a time of the "H" level is longer than that of the "L" level, therefore, it is impossible to keep a duty cycle at 50%. As a result, since the pulse width of the "L" level in the oscillating signal OUT becomes narrow, it is impossible to keep a setup time and a hold time for a flip-flop circuit or the like which is connected as a rear stage. Thus, it is caused that a malfunction occurs. Further, though it is possible to set the duty cycle close to 50% by increasing a number of the delay inverting circuits to be a ring, the ring delay time increases. Thus, for example, there is a problem that it becomes difficult to oscillate at a high frequency not less than 156 MHz used for high speed communication. The present invention aims to solve the above described problem in the conventional VCO and aims to provide a VCO which can obtain an oscillating output of almost 50% duty cycle in spite of a high frequency. According to a first aspect of the invention, there is provided a voltage controlled oscillator comprising: a plurality of signal processing stages connected as a ring oscillator, each stage comprising: inverting means comprising an emitter-coupled pair of transistors, for inverting an input signal between first and second logical levels, delay means comprising a bipolar transistor feeding capacitive means, for producing an output signal comprising a delayed version of the input signal wherein a first delay time of a transition from the first logical level to the second logical level is smaller than a second delay time of a transition from the second logical level to the first logical level, and a further said signal processing stage connected to an output of the ring oscillator wherein the delay means thereof is configured such that the second delay time of the further said stage is set to a predetermined proportion of, and is different from, the second delay time of each of said ring oscillator stages, so as to enable a desired duty cycle of the oscillator output to be set. The voltage controlled oscillator may comprise at least four signal processing stages of an even number and controlling an oscillating frequency, each of the signal processing stages comprising: an input terminal receiving a signal at a level within a predetermined range; a reference terminal receiving a reference signal at a value within the predetermined range; and a control terminal receiving a control signal; the inverting means of the signal processing stage inverting the signal between the first logical level and the second logical level based on whether a logical level of the signal exceeds the reference signal or not; and the delay means of the signal processing stage receiving the signal inverted by the inverting means and outputting a signal of which a level varies at a constant rate within the predetermined range when the signal is inverted from the first logical level to the second logical level: wherein the delay means of the further said signal processing stage outputs the signal of which a level varies at a half of a variable rate within the predetermined range in accordance with the control signal when the signal is inverted from the second logical level to the first logical level, and the signal processing stages connected as the ring oscillator respectively output the signal of which a level varies at the variable rate within the predetermined range in accordance with the control signal when the signal is inverted from the second logical level to the first logical level. Here, said delay means in each of said signal processing stages connected as the ring oscillator may comprise a first charge part which is provided with electric charge by the signal of the second logical level inverted by the inverting means and which outputs the signal varying at the constant rate, and a first discharge part which is controlled by the control signal and which discharges the electric charge from the first charge part in accordance with the control signal when the signal inverted by the inverting means is the first logical level. Said delay means in the further said signal processing stage may additionally comprise a second charge part which is filled with electric charge by the signal of the second logical level inverted by the inverting means and which outputs the signal varying at the constant rate or at a half of the variable rate, and a second discharge part which is controlled by the control signal and which discharges the electric charge from the second charge part in accordance with the control signal when the signal inverted by the inverting means is the first logical level. Additionally, a capacitance of the second charge part may be equal to that of the first charge part, and the second discharge part may discharge the electric charge from the second charge part at twice a speed of the first discharge part . Alternatively, a capacitance of the second charge part may be a half of a capacitance of the first charge part, and the second discharge part may discharge the electric charge in the second charge part at a speed equal to that in the first discharge part. With the VCO structured as above described, the VCO can operate as follows. In the first delay circuit of the delay inverting circuit in the ring oscillating circuit, a delay time from the first logical level to the second logical level is different from a delay time from the second logical level to the first logical level. Thus, the duty cycle of the output signal from the ring oscillator is out of 50%. The second inverting circuit inverts the logical level of the output signal from the ring oscillator, and the second delay circuit shortens the delay time from the second logical level to the first logical level to 1/2. Then, the signal of which the delay time is shortened is outputted. The delay time is corrected by the second inverting circuit and the second delay circuit. Therefore, the duty cycle of the oscillating signal becomes close to 50%. The first mentioned voltage controlled oscillator may comprising at least four signal processing circuits of an even number and controlling an oscillating frequency, each of the signal processing circuits comprising: an input terminal receiving a signal at a level within a predetermined range; a reference terminal receiving a reference signal at a value within the predetermined range; and a control terminal receiving a control signal; wherein the inverting means of said further signal processing stage inverts the signal between the first logical level and the second logical level within a half of the predetermined range based on whether a logical level of the signal exceeds the reference signal or not, and the delay means of said further signal processing stage receives the signal inverted by the inverting means and outputs the signal of which a level varies at a constant rate within the half of the predetermined range when the signal is inverted from the first logical level to the second logical level and outputs the signal of which a level varies at a variable rate within the half of the predetermined range in accordance with the control signal when the signal is inverted from the second logical level to the first logical level; and wherein the inverting means of the signal processing stages connected in the oscillator ring each comprise an inverting circuit inverting the signal between a third logical level and a fourth logical level within the predetermined range based on whether a logical level of the signal exceeds the reference signal or not, and the delay means of the signal processing stages connected in the oscillator ring receives the signal inverted by the inverting circuit and outputs the signal of which a level varies at the constant rate within the predetermined range when the signal is inverted from the third logical level to the fourth logical level and outputs the signal of which a level varies at the variable rate within the predetermined range in accordance with control signal when the signal is inverted from the fourth logical level to the third logical level. In this case, the VCO can operate as follows. The signal is outputted from the ring oscillator, and the output signal of which the logical level is inverted by the second inverting circuit and of which the output amplitude is restricted to 1/2 is applied to the second delay circuit. In the second delay circuit, the delay time is set in accordance with a variation of the logical level of the output signal of which the amplitude is 1/2, therefore, the delay time from the fourth level to the third level is shortened to a half (1/2) of the delay time from the second level to the first level. As a result, it is possible to put the duty cycle of the oscillating signal close to 50% similarly to the second aspect. A second aspect of the present invention provides a method of controlling a voltage controlled oscillator so as to produce a desired duty cycle, the voltage controlled oscillator comprising: three or a greater odd number of signal a plurality of signal processing stages connected as a ring oscillator, each stage comprising: inverting means comprising an emitter-coupled pair of transistors, for inverting an input signal between first and second logical levels, delay means comprising a bipolar transistor feeding capacitive means, for producing an output signal comprising a delayed version of the input signal, wherein a first delay time of a transition from the first logical level to the second logical level is smaller than a second delay time of a transition from the second logical level to the first logical level, the method further comprising the step of inverting the output signal from the ring oscillator and delaying the transition from the second logical level to the first logical level by a time which is a predetermined proportion of, and which is different from, the second delay time of each of said ring oscillator stages, so as to enable a desired duty cycle of the oscillator output to be set. This method of controlling a voltage controlled oscillator, comprising a delay inverter connected to the ring oscillator, may comprise: receiving a signal within a range; receiving a reference signal of a value in the range; receiving a control signal; inverting the signal between the first logical level and the second logical level within the range based on whether a logical level of the signal exceeds the reference signal or not in the ring oscillator; receiving the signal which is inverted and; outputting the signal of which a level varies at a constant rate within the range from the ring oscillator when the signal is inverted from the first logical level to the second logical level, and outputting the signal of which a level varies at a variable rate within the range in accordance with the control signal from the ring oscillator when the signal is inverted from the second logical level to the first logical level; receiving the signal outputted from the ring oscillator and inverting the signal between the first logical level and the second logical level based on whether a logical level of the signal exceeds the reference signal or not in the delay inverter; and outputting the signal of which a level varies at the constant rate within the range when the signal is inverted from the first logical level to the second logical level, and outputting the signal of which a level varies at a half of the variable rate within the range in accordance with control signal when the signal is inverted from the second logical level to the first logical level. Other objects and advantages of the present invention will become apparent during the following discussion conjunction with the accompanying drawings, in which: FIG. 1 is a structural view illustrating a VCO of the first embodiment according to the present invention; FIGs. 2(a) and 2(b) are circuit views illustrating delay inverting circuits 10, 40 in FIG. 1; FIG. 3 is a view illustrating an operating wave form in the VCO in FIG. 1; FIG. 4 is a circuit view illustrating a delay inverting circuit 40A in a VCO of the second embodiment according to the present invention; FIG. 5 is a circuit view illustrating a delay inverting circuit 40B in a VCO of the third embodiment according to the present invention; and FIG. 6 is a structural view illustrating a conventional VCO. Preferred aspects and embodiments of the present invention will now be described with reference to the accompanying drawings. <First Embodiment> FIG. 1 is a structural view illustrating a voltage controlled oscillator (VCO) of the first embodiment according to the present invention. The VCO is provided with three delay inverting circuits 10, 20, 30 which are connected in a ring. These delay inverting circuits 10, 20, 30 are similar to one another, and each of which is provided with an inverting circuit inverting a logic level of an input signal Vi and a delay circuit connected to the output of the inverting circuit. The inverting circuit is a logic circuit which compares the input signal Vi into an input terminal A with a reference voltage Vr applied to an input terminal B and which outputs an inverting signal of a logic level which is inverted in accordance with the compared result. That is, in case of Vi≤Vr, the inverted signal of the "H" level is outputted, and in case of Vi>Vr, the inverted signal of the "L" level is outputted. The delay circuit controls a delay time when the inverted signal outputted from the inverting circuit is applied to the output terminal C. The delay circuit, when the inverted signal from the inverting circuit varies from the "L" level to the "H" level, responses for a constant delay time tr (for example, tr=0.2ns), and when the inverted signal varies from the "H" level to the "L" level, responses for a variable delay time tf (for example, tf=1.6-4.0ns), and then outputs a delayed output signal from the output terminal C. The output terminal C of the delay inverting circuit 30 is connected to the input terminal A of the delay inverting circuit 10 and is connected to the input terminal A of the delay inverting circuit 40. The delay inverting circuit 40 is provided with a control terminal D, and the delay control voltage Vc which is used in common with the delay inverting circuits 10-30 is applied to the control terminal. The delay inverting circuit 40 functions almost similarly to the delay inverting circuits 10, 20, 30, and is provided with an inverting circuit similar to that in the delay inverting circuit 10 and a delay circuit in which a delay time is set to be slightly different from that in the delay inverting circuit 10. That is, the delay circuit in the delay inverting circuit 40, when the inverted signal from the inverting circuit varies from the "L" level to the "H" level, responses for the delay time tr similar to that in the delay inverting circuit 10. On the contrary, the delay circuit, when the inverted signal varies from the "H" level to the "L" level, responses for a half of the variable delay time tf in the delay inverting circuit 10, that is, for tf/2 in accordance with the delay control voltage Vc, and outputs the delayed output signal from the output terminal C. The output terminal C in the delay inverting circuit 40 is connected to the input of the logic gate 50 for arranging a wave form, and then the oscillating signal OUT of which a wave form is arranged in a rectangular wave is outputted from the output of the logic gate 50. FIGs. 2(a) and 2(b) are views respectively illustrating delay inverting circuits 10, 40 in FIG. 1. The delay inverting circuit 10, as shown in FIG. 2(a), is provided with an inverting circuit 10a comprising transistors 11, 12, resistances 13, 14 and a constant current source 15 and a delay circuit 10b comprising transistors 16, 17, a capacitor 18 and a resistance 19. The input terminals A, B are respectively connected to bases of the transistors 11, 12 of the same characteristics. Collectors of the transistors 11, 12 are respectively connected to a source voltage Vcc through the resistances 13, 14 of the same value, and emitters are connected together to a ground GND through the constant current source 15. The transistor 16 is connected between the output terminal C and the source voltage Vcc, and the base of the transistor 16 is connected to the collector of the transistor 11. The capacitor 18 is connected between the output terminal C and the ground GND. Then, a charge part 10c is provided with the capacitor 18 and the transistor 16. A discharge part 10d comprising the transistor 17 and the resistance 19 which are further connected in series is connected between the output terminal C and the ground GND. The base of the transistor 17 is connected to the control terminal D. Now, the delay inverting circuit 40, as shown in FIG. 2(b), is almost equal to the delay inverting circuit 10, and is provided with an inverting circuit 40a comprising transistors 41, 42, resistances 43, 44 and a constant current source 45, and a delay circuit 40b comprising transistors 46, 47a, 47b, a capacitor 48 and resistances 49a, 49b. Characteristics of the transistors 41, 42, 46, 47a are respectively equal to the transistors 11, 12, 16, 17. Values of the resistances 43, 44, 49a are respectively equal to those of the resistances 13, 14, 19. A value of the constant current source 15 is that of the constant current source 45, and a value of the capacitor 18 is that of the capacitor 48. Further, the transistor 47a, 47b and the resistances 49a, 49b connected in parallel in the discharge part 40d are respectively set at same values. That is, the difference between the delay inverting circuit 40 and the delay inverting circuit 10 is that the impedance of the discharge part 40d in the delay inverting circuit 40 is a half of the impedance of the discharge part 10d in the delay inverting circuit 10. FIG. 3 is a view illustrating operating wave forms of the respective delay inverting circuits 10-40 in the VCO shown in FIG. 1. An explanation will be given of the operation in the VCO shown in FIG. 1 with reference to FIGs. 2(a), 2(b) and 3. Here, it is assumed that a half of the source voltage Vcc is applied to the input terminal B in each of the delay inverting circuits 10-40 as the reference voltage Vr, and the delay control voltage Vc within a predetermined range is applied to the control terminal D in common. For example, at a time t0 in FIG.3, it is assumed that the output signal S30 from the delay inverting circuit 30 varies from the "H" level to the "L" level. Since the output signal S30 is applied to the input terminal A, in the delay inverting circuit 10 shown in FIG. 2(a), the base voltage of the transistor 11 becomes lower than that of the transistor 12. The emitters of the transistors 11, 12 are connected together to the ground GND through the constant current source 15, therefore, these are switched so that only one of them turns on. In this case, the transistor 11 is switched over from on to off, and the collector voltage of the transistor 11 raises to almost the source voltage Vcc. Then, the transistor 16 becomes on, and the capacitor 18 is rapidly charged through the transistor 16. After a short delay time tr, at the time t1, the output signal S10 from the output terminal C becomes the "H" level. At the time t1, when the output signal S10 from the delay inverting circuit 10 varies from the "L" level to the "H" level, the output signal S10 of the "H" level is applied to the input terminal A in the delay inverting circuit 20. The delay inverting circuit 20 is similar to the delay inverting circuit 10, therefore, the explanation is given of the operation in the delay inverting circuit 20 with reference to FIG. 2(a). When the input terminal A becomes the "H" level, the transistor 11 turns on. Then, the collector voltage of the transistor 11 becomes the "L" level almost close to the level at the ground GND, and then the transistor 16 becomes off. Thus, charges held in the capacitor 18 are discharged through the transistor 17 and the resistance 19 controlled by the delay control voltage Vc, and the output voltage reduces sequentially in accordance with a time constant T10 determined by the capacity of the capacitor 18 and a composite resistance of the transistor 17 and the resistance 19. Then, after the delay time tf which is relatively long from the time t1, the output signal S20 from the delay inverting circuit 20 becomes the "L" level. The delay time tf is determined in accordance with the continuity condition of the transistor 17, therefore, it is possible to control the delay time tf with the delay control voltage Vc. At a time t2, when the output signal S20 from the delay inverting circuit 20 varies from the "H" level to the "L" level, the output signal S20 is applied to the input terminal A of the delay inverting circuit 30. Thus, in the delay inverting circuit 30, the operation which is similar to that of the delay inverting circuit 10 at the time t0 is carried out. Then, the output signal S30 from the delay inverting circuit 30 switches over from the "L" level to the "H" level at the time t3 after the delay time tr. At a time t3, when the output signal S30 from the delay inverting circuit 30 varies from the "L" level to the "H" level, the output signal S30 is applied to the input terminal A of the delay inverting circuit 10. Thus, in the delay inverting circuit 10, the operation which is similar to that of the delay inverting circuit 20 at the time t1 is carried out. Then, the output signal S10 from the delay inverting circuit 10 switches over from the "H" level to the "L" level at the time t4 after the delay time tf. Likewise, the output signal S20 from the delay inverting circuit 20 switches over from the "L" level to the "H" level at the time t5 after the delay time tr from the time t4. Further, the output signal S30 from the delay inverting circuit 30 switches over from the "H" level to the "L" level at the time t6 after the delay time tr from the time t5. In this way, the inverting operation of the output signal S30 from the delay inverting circuit 30 is repeated in a cycle of a delay time (3tr+3tf) between the time t0 and the time t6. Thus, a frequency FR30 and a duty cycle DT30 of the output signal S30 from the delay inverting circuit 30 are expressed as the following expressions (1) and (2), FR30 = 1/3(tr+tf) DT30 = (tr+2tf)/3(tr+tf) Here, if tr=0.2ns and tf=1.6ns, FR30 = 185.2MHz DT30 = 62.9%. If tr=0.2ns and tf=4.0ns, FR30 = 79.4MHz DT30 = 65.1%. On the contrary, at the time t0, when the output signal S30 from the delay inverting circuit 30 varies from the "H" level to the "L" level, the output signal S30 is applied to the input terminal A of the delay inverting circuit 40. Thus, in the delay inverting circuit 40 shown in FIG. 2(b), the base voltage of the transistor 41 becomes lower than that of the transistor 42. Since emitters of the transistors 41, 42 are connected together to the ground GND through the constant current source 45, therefore, these are switched so that only one of them turns on. In this case, the transistor 41 is switched over from on to off, and the collector voltage of the transistor 41 raises to almost the source voltage Vcc. Then, the transistor 46 turns on, and the capacitor 48 is rapidly charged through the transistor 46. After the delay time tr which is equal to that in the delay inverting circuit 10, at the time t1, the output signal S40 from the output terminal C becomes the "H" level. At the time t3, when the output signal S30 from the delay inverting circuit 30 varies from the "L" level to the "H" level, the input terminal A in the delay inverting circuit 40 become the "H" level and the transistor 41 switches over to on. Then, the collector voltage of the transistor 41 becomes the "L" level almost close to the voltage at the ground GND, and then the transistor 46 becomes off. Thus, charge held in the capacitor 48 is discharged through a parallel circuit comprising the transistor 47a and the resistance 49a and the transistor 47b and the resistance 49b, and the voltage at the output terminal C reduces sequentially in accordance with a time constant T40 determined by the capacitance of the capacitor 48 and composite resistances of the transistors 47a, 47b and the resistances 49a, 49b. The capacitors 19, 49, the transistors 17, 47a, 47b and the resistances 18, 48a, 48b are respectively set at the same capacitance, the same characteristics and the same resistant value, therefore, the time constant T40 in the delay inverting circuit 40 becomes a half of the time constant T10 in the delay inverting circuit 10. Thus, after the delay time tf/2 from the time t3, at a time t3.5, the output signal S40 from the delay inverting circuit 40 becomes the "L" level. Thus, a frequency FR40 and a duty cycle DT40 of the output signal S40 from the delay inverting circuit 40 are expressed as the following expressions (3) and (4), FR40 = 1/3(tr+tf) DT40 = (tf+tr+tf/2)/3(tf+tr) = 0.5-tr/6(tf+tr) Here, if tr=0.2ns and tf=1.6ns, FR40 = 185.2MHz DT40 = 45.8%. If tr=0.2ns and tf=4.0ns, FR40 = 79.4MHz DT40 = 49.2%. In this way, the delay times are set to be tr«tf, whereby it is possible to keep the duty cycle DT40 at almost 50%. As above described, in the VCO of this embodiment, the delay inverting circuits 10-30 which forms a ring circuit is provided with the delay inverting circuit 40 of which the delay time is a half of that in the delay inverting circuits 10-30 so that the oscillating output is obtained. Thus, it is possible to obtain a duty cycle of almost 50% compared with a case that an oscillating output is obtained from the delay inverting circuit 30. That is, since a number of stages in a ring oscillating circuit does not vary, it is possible to obtain an oscillating signal OUT of which the duty cycle is almost 50% without reducing a oscillating frequency. <Second Embodiment> FIG. 4 is a view illustrating a delay inverting circuit 40A in a VCO of the second embodiment according to the present invention. In FIG. 4, the same numerals are used for the same elements in FIG. 2(b). The delay inverting circuit 40A is arranged instead of the delay inverting circuit 40 in FIG. 1. The differences from the delay inverting circuit 40 shown in FIG. 2(b) are that a charge part 40f comprising a series circuit of capacitors 48a, 48b of which capacitance is equal to that of the capacitor 48 is provided instead of the charge part 40c and a discharge part 40g in which the transistor 47a and the resistance 49b are removed instead of the discharge part 40d. With this arrangement, though the capacitance of the charge part 40f becomes 1/2 and the impedance of the discharge part 40g becomes twice, the time constant is equal to that in the first embodiment. Thus, the operation similar to the first embodiment is carried out, and then it is possible to obtain the same effects. <Third Embodiment> FIG. 5 is a view illustrating a delay inverting circuit 40B in a VCO of the third embodiment according to the present invention. In FIG. 5, the same numerals are used for the same elements in FIG. 2(b). The delay inverting circuit 40B is arranged instead of the delay inverting circuit 40 in FIG. 1. The differences from the delay inverting circuit 40 shown in FIG. 2(b) are that an inverting circuit 40h comprising resistances 43a, 44a of which values are 1/2 of those of the resistances 43, 44 in the inverting circuit 40a instead of them is arranged and a discharge part 40j in which the transistor 47b and the resistor 49b in the discharge part 40d is removed. With this arrangement, the voltage difference between the "L" and "H" levels outputted from the inverting circuit 40h in the delay inverting circuit 40B corresponds to a product of the value of the resistance 43a and the current value of the constant current source 45, therefore, the voltage difference is a half of voltage difference between the "L" and "H" levels outputted from the inverting circuit 10a in the delay inverting circuit 10. Since the charge part 40c is charged by the output voltage from the inverting circuit 40h, charge held by the capacitor 48 in the discharge part 40c is a half of that held by the capacitor 18 in the delay inverting circuit 10. Thus, it is possible for the discharge part 40j in the delay inverting circuit 40B to discharge the capacitor 48 for a half of the time which is taken for the discharge part 10d in the delay inverting circuit 10. That is, since the delay inverting circuit 40B in FIG. 5 operates similarly to the delay inverting circuit 40 in FIG. 2(b), there are the same effects as the first embodiment. Additionally, the present invention is not limited to the above described embodiments, and can be modified in various ways. For example, there are modifications as follows. (a) The ring oscillating circuit in FIG. 1 comprises three stages, however, a ring oscillating circuit comprising odd stages not less than three operates similarly. Thus, a number of stages may be set in accordance with a desired oscillating frequency. (b) The reference voltage Vr is applied to each of the input terminals B of the delay inverting circuits 10-40 in those embodiment, however, it is not always necessary to apply the reference voltage Vr from the outside. Thus, the reference voltage Vr may be produced in each of the delay inverting circuits 10-40. (c) Each of the delay inverting circuits 10-40 comprises bipolar transistors, however, it may be a CMOS (Complementary Metal Oxide Semiconductor) gate circuit comprising MOS (Metal Oxide Semiconductor) transistors or the like. (d) Circuit structures and constants of the charge part 40c and the discharge part 40d in the delay circuit 40b are not limited to the values explained in those embodiment, therefore, any combination of values may be used as long as a time constant during discharge is a half of that in the delay inverting circuit 10 or the like. As above explained in detail, the second aspect is provided with a second delay circuit of which a delay time from the second logical level to the first logical level is shortened to a half of that in the first delay circuit. Then, the second inverting circuit and the second delay circuit correct the duty cycle of the oscillating signal outputted from the second delay circuit, therefore, it is possible to keep the duty cycle of the oscillating signal outputted from the second delay circuit at almost 50%. Alternatively, a third aspect is provided with a second inverting circuit which inverts the logical level of the output signal from the ring oscillating circuit and of which the output amplitude is restricted to a half of that of the signal inputted to the VCO. The second delay circuit outputs a signal which is delayed in accordance with a variation of the logical level within the output amplitude which is 1/2 of that of the signal, therefore, a delay time from the fourth logical level to the third logical level is shortened to a half of that from the second logical level to the first logical level. Thus, it is possible to keep the duty cycle of the oscillating signal at almost 50% similarly to the other aspects. This invention being thus described, it will be obvious that same may be varied in various ways. The scope of protection is not to be limited by the described embodiments but by the claims.

Claims: A voltage controlled oscillator comprising: a plurality of signal processing stages connected as a ring oscillator, each stage comprising: inverting means comprising an emitter-coupled pair of transistors, for inverting an input signal between first and second logical levels, delay means comprising a bipolar transistor feeding capacitive means, for producing an output signal comprising a delayed version of the input signal wherein a first delay time of a transition from the first logical level to the second logical level is smaller than a second delay time of a transition from the second logical level to the first logical level, and a further said signal processing stage connected to an output of the ring oscillator wherein the delay means thereof is configured such that the second delay time of the further said stage is set to a predetermined proportion of, and is different from, the second delay time of each of said ring oscillator stages, so as to enable a desired duty cycle of the oscillator output to be set. A voltage controlled oscillator according to claim 1, wherein said predetermined proportion is one half, whereby the desired duty cycle is set to 50 per cent. A voltage controlled oscillator according to claim 1, comprising at least four signal processing stages of an even number and controlling an oscillating frequency, each of the signal processing stages comprising: an input terminal receiving a signal at a level within a predetermined range; a reference terminal receiving a reference signal at a value within the predetermined range; and a control terminal receiving a control signal; the inverting means of the signal processing stage inverting the signal between the first logical level and the second logical level based on whether a logical level of the signal exceeds the reference signal or not; and the delay means of the signal processing stage receiving the signal inverted by the inverting means and outputting a signal of which a level varies at a constant rate within the predetermined range when the signal is inverted from the first logical level to the second logical level: wherein the delay means of the further said signal processing stage outputs the signal of which a level varies at a half of a variable rate within the predetermined range in accordance with the control signal when the signal is inverted from the second logical level to the first logical level, and the signal processing stages connected as the ring oscillator respectively output the signal of which a level varies at the variable rate within the predetermined range in accordance with the control signal when the signal is inverted from the second logical level to the first logical level. A voltage controlled oscillator according to claim 3, wherein said delay means in each of said signal processing stages connected as the ring oscillator comprises a first charge part which is provided with electric charge by the signal of the second logical level inverted by the inverting means and which outputs the signal varying at the constant rate, and a first discharge part which is controlled by the control signal and which discharges the electric charge from the first charge part in accordance with the control signal when the signal inverted by the inverting means is the first logical level. A voltage controlled oscillator according to claim 4, wherein said delay means in the further said signal processing stage comprises a second charge part which is filled with electric charge by the signal of the second logical level inverted by the inverting means and which outputs the signal varying at the constant rate or at a half of the variable rate, and a second discharge part which is controlled by the control signal and which discharges the electric charge from the second charge part in accordance with the control signal when the signal inverted by the inverting means is the first logical level. A voltage controlled oscillator according to claim 5, wherein a capacitance of said second charge part is equal to that of said first charge part, and said second discharge part discharges the electric charge from said second charge part at twice the speed of said first discharge part. A voltage controlled oscillator according to claim 5, wherein a capacitance of said second charge part is a half of a capacitance of said first charge part, and said second discharge part discharges the electric charge in said second charge part at a speed equal to that of said first discharge part. A voltage controlled oscillator as claimed in claim 1, comprising at least four signal processing circuits of an even number and controlling an oscillating frequency, each of the signal processing circuits comprising: an input terminal receiving a signal at a level within a predetermined range; a reference terminal receiving a reference signal at a value within the predetermined range; and a control terminal receiving a control signal; wherein the inverting means of said further signal processing stage inverts the signal between the first logical level and the second logical level within a half of the predetermined range based on whether a logical level of the signal exceeds the reference signal or not, and the delay means of said further signal processing stage receives the signal inverted by the inverting means and outputs the signal of which a level varies at a constant rate within the half of the predetermined range when the signal is inverted from the first logical level to the second logical level and outputs the signal of which a level varies at a variable rate within the half of the predetermined range in accordance with the control signal when the signal is inverted from the second logical level to the first logical level; and wherein the inverting means of the signal processing stages connected in the oscillator ring each comprise an inverting circuit inverting the signal between a third logical level and a fourth logical level within the predetermined range based on whether a logical level of the signal exceeds the reference signal or not, and the delay means of the signal processing stages connected in the oscillator ring receives the signal inverted by the inverting circuit and outputs the signal of which a level varies at the constant rate within the predetermined range when the signal is inverted from the third logical level to the fourth logical level and outputs the signal of which a level varies at the variable rate within the predetermined range in accordance with control signal when the signal is inverted from the fourth logical level to the third logical level. A method of controlling a voltage controlled oscillator so as to produce a desired duty cycle, the voltage controlled oscillator comprising: three or a greater odd number of signal a plurality of signal processing stages connected as a ring oscillator, each stage comprising: inverting means comprising an emitter-coupled pair of transistors, for inverting an input signal between first and second logical levels, delay means comprising a bipolar transistor feeding capacitive means, for producing an output signal comprising a delayed version of the input signal, wherein a first delay time of a transition from the first logical level to the second logical level is smaller than a second delay time of a transition from the second logical level to the first logical level, the method further comprising the step of inverting the output signal from the ring oscillator and relaying the transition from the second logical level to the first logical level by a time which is a predetermined proportion of, and which is different from, the second delay time of each of said ring oscillator stages, so as to enable a desired duty cycle of the oscillator output to be set. A method according to claim 9, wherein said predetermined proportion is one half, whereby the desired duty cycle is set to 50 per cent. A method of controlling a voltage controlled oscillator as claimed in claim 9, comprising a delay inverter connected to the ring oscillator, said method comprising: receiving a signal within a range; receiving a reference signal of a value in the range; receiving a control signal; inverting the signal between the first logical level and the second logical level within the range based on whether a logical level of the signal exceeds the reference signal or not in the ring oscillator; receiving the signal which is inverted and; outputting the signal of which a level varies at a constant rate within the range from the ring oscillator when the signal is inverted from the first logical level to the second logical level, and outputting the signal of which a level varies at a variable rate within the range in accordance with the control signal from the ring oscillator when the signal is inverted from the second logical level to the first logical level; receiving the signal outputted from the ring oscillator and inverting the signal between the first logical level and the second logical level based on whether a logical level of the signal exceeds the reference signal or not in the delay inverter; and outputting the signal of which a level varies at the constant rate within the range when the signal is inverted from the first logical level to the second logical level, and outputting the signal of which a level varies at a half of the variable rate within the range in accordance with control signal when the signal is inverted from the second logical level to the first logical level.

Inventors: KAMEI TAKAHIRO, KAMEI, TAKAHIRO
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1997
Main classification: H03K3
IPC codes: H03B5, H03K3, H03H11