FRACTIONAL PRECISION INTEGER SQUARE ROOT PROCESSOR AND METHOD FOR USE WITH ELECTRONIC CIRCUIT BREAKER SYSTEMS

Abstract: A processor system apparatus and method for determining a square root of a particular value of a square of a parameter for use with an electronic circuit breaker system. The system comprises a signal processor or logic circuit for receiving and using at least one input signal to process and output at least one output signal, wherein the logic circuit is configured to determine a whole root of the square root of a particular value of the square of a parameter, wherein the logic circuit is configured to determine a slope of the square of a parameter bounded by at least a first point and a second point, where the first point corresponds to a first value of the square of a parameter and the second point corresponds to a second value of the square of a parameter, wherein the logic circuit is configured to determine a difference between the particular value of the square of a parameter and a value of a square of the whole root, wherein the logic circuit is configured to determine a fractional part of the square root of a particular value of the square of a parameter using the slope and the difference, wherein the logic circuit is configured to determine the square root by combining the whole root of the square root and the fractional part of the square root, and wherein the logic circuit outputs at least one output signal using the square root.

Description: FRACTIONAL PRECISION INTEGER SQUARE ROOT PROCESSOR AND METHOD FOR USE WITH ELECTRONIC CIRCUIT BREAKER SYSTEMS BACKGROUND OF THE INVENTION Field of the Invention This invention relates to embedded system applications for use with electronic circuit breaker systems in which the embedded system applications require at least square root computations. This invention further relates to microcontroller or microprocessor based systems that determine at least square roots using a fractional precision integer square root method to relatively accurately and quickly determine at least the square roots of integer values of various input parameters associated with electronic circuit breaker systems. A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. Description of Related Art To determine at least the square root of a number, known embedded system applications may use certain commercially available language compilers, such as C-language compilers that use a floating point square root method having double precision accuracy. For certain embedded systems applications, however, double precision accuracy may not be required. Accordingly, such applications may also use a relatively fast integer method. The accuracy of this method, however, may not be adequate in certain applications. One example of an embedded system application that requires greater speed than the floating point method and better accuracy than the fast integer method are electronic circuit breaker systems that are capable of measuring various input parameters representing electrical energy usage in approximately real-time, such as are used in the power industry. However, determining the RMS values for current or voltage input parameters or determining at least the square-roots associated with certain harmonics calculations may require a significant portion of the computing time of the processor(s) of the electronic circuit breaker system. Commercially available C-language compilers using floating point methods may take on the order of approximately 10 milliseconds to run on a 16-bit microcontroller or microprocessor running at 16 MHZ. Accordingly, in electronic circuit breaker system applications, the processor that determines the RMS currents and voltages in approximately real-time to measure energy usage may use on the order of about fifty (50) percent of its computing time to determine square roots using such floating point methods. In particular, electronic circuit breaker systems that measure energy usage may require on the order of about 50 square root calculations every second. If the processor takes 10 milliseconds to determine each square root, then the processor will use on the order of one-half (1/2) second of a one second interval simply to determine the square roots of various measured input parameters. Where energy measurement is done in approximately real-time, this may leave insufficient processing time for other purposes, such as updating displays, reading keypads and handling communications to a remote processor. Summary of the Invention It is an object of the present invention to overcome the speed limitations of the double precision floating point method of certain known commercial language compilers and the accuracy limitations of the fast integer method for determining at least square roots in embedded system applications, including embedded system applications for electronic circuit breaker systems that measure energy usage. More specifically, it is an object of the present invention to provide a relatively accurate and relatively fast method of determining at least the square roots of the integer values of measured input parameters for use in such embedded system applications. According to one aspect of the present invention, a processor system apparatus is provided for determining a square root of a particular value of a square of a parameter for use with an electronic circuit breaker system, comprising: a logic circuit receiving and using at least one input signal to process and output at least one output signal, wherein the logic circuit is configured to determine a whole root of the square root of a particular value of the square of a parameter, wherein the logic circuit is configured to determine a slope of the square of a parameter bounded by at least a first point and a second point, where the first point corresponds to a first value of the square of a parameter and the second point corresponds to a second value of the square of a parameter, wherein the logic circuit is configured to determine a difference between the particular value of the square of a parameter and a value of a square of the whole root, wherein the logic circuit is configured to determine a fractional part of the squire root of a particular value of the square of a parameter using the slope and the difference, wherein the logic circuit is configured to determine the square root by combining the whole root of the sguare root and the fractional part of the square root, and wherein the logic circuit outputs at least one output signal using the square root. According to another aspect of the present invention, which achieves one or more of these objectives, a method is provided for determining a square root of a particular value of a square of a parameter for use with an electronic circuit breaker system, and comprises the steps of: determining a whole root of the square root of a particular value of the square of a parameter; determining a slope of the square of a parameter bounded by at least a first point and a second point, where the first point corresponds to a first value of the square of a parameter and the second point corresponds to a second value of the square of a parameter; determining a difference between the particular value of the square of a parameter and a value of a square of the whole root; determining a fractional part of the square root of a particular value of the square of a parameter using the slope and the difference; and combining the whole root of the square root and the fractional part of the square root. According to another aspect of the present invention, a processor system apparatus is provided for determining a polynomial root of a particular value of a polynomial of a parameter for use with an electronic circuit breaker system, comprising: a logic circuit receiving and using at least one input signal to process and output at least one output signal, wherein the logic circuit is configured to determine a whole root of the polynomial root of a particular value of the polynomial of a parameter, wherein the logic circuit is configured to determine a slope of the polynomial of a parameter bounded by at least a first point and a second point, where the first point corresponds to a first value of the polynomial of a parameter and the second point corresponds to a second value of the polynomial of a parameter, wherein the logic circuit is configured to determine a difference between the particular value of the polynomial of a parameter and a value of a polynomial of the whole root, wherein the logic circuit is configured to determine a fractional part of the polynomial root of a particular value of the polynomial of a parameter using the slope and the difference, wherein the logic circuit is configured to determine the polynomial root by combining the whole root of the polynomial root and the fractional part of the polynomial root, and wherein the logic circuit outputs at least one output signal using the polynomial root. According to another aspect of the present invention, which achieves one or more of these objectives, a method is provided for determining a polynomial root of a particular value of a polynomial of a parameter for use with an electronic circuit breaker system, comprising the steps of: determining a whole root of the polynomial root of a particular value of the polynomial of a parameter; determining a slope of the polynomial of a parameter bounded by at least a first point and a second point, where the first point corresponds to a first value of the polynomial of a parameter and the second point corresponds to a second value of the polynomial of a parameter; determining a difference between the particular value of the polynomial of a parameter and a value of a polynomial of the whole root; determining a fractional part of the polynomial root of a particular value of the polynomial of a parameter using the slope and the difference; and combining the whole root of the polynomial root and the fractional part of the polynomial root. According to another aspect of the present invention, a processor system is provided for determining a square root of a particular value of a square of a parameter for use with an electronic circuit breaker system, comprising: a logic circuit means for receiving and using at least one input signal to process and output at least one output signal, wherein the logic circuit means determines a whole root of the square root of a particular value of the square of a parameter, wherein the logic circuit means determines a slope of the square of a parameter bounded by at least a first point and a second point, where the first point corresponds to a first value of the square of a parameter and the second point corresponds to a second value of the square of a parameter, wherein the logic circuit means determines a difference between the particular value of the square of a parameter and a value of a square of the whole root, wherein the logic circuit means determines a fractional part of the square root of a particular value of the square of a parameter using the slope and the difference, wherein the logic circuit means determines the square root by combining the whole root of the square root and the fractional part of the square root, and wherein the logic circuit means outputs at least one output signal using the square root. According to another aspect of the invention, a processor system is provided for determining a polynomial root of a particular value of a polynomial of a parameter for use with an electronic circuit breaker system, comprising: a logic circuit means for receiving and using at least one input signal to process and output at least one output signal, wherein the logic circuit means determines a whole root of the polynomial root of a particular value of the polynomial of a parameter, wherein the logic circuit means determines a slope of the polynomial of a parameter bounded by at least a first point and a second point, where the first point corresponds to a first value of the polynomial of a parameter and the second point corresponds to a second value of the polynomial of a parameter, wherein the logic circuit means determines a difference between the particular value of the polynomial of a parameter and a value of a polynomial of the whole root, wherein the logic circuit means determines a fractional part of the polynomial root of a particular value of the polynomial of a parameter using the slope and the difference, wherein the logic circuit means determines the polynomial root by combining the whole root of the polynomial root and the fractional part of the polynomial root, and wherein the logic circuit means outputs at least one output signal using the polynomial root. These and other objects, advantages and features of the present invention will be readily understood and appreciated with reference to the detailed description of preferred embodiments discussed below together with the accompanying drawings. Brief Description of the Drawings Figure 1 is a chart showing the relative nonlinearity of the square of X at lower values of X. Figure 2 is a chart showing the relative linearity of the square of X at higher values of X. Figure 3 is a schematic block diagram of the system having a signal processor or logic circuit for determining in part at least the square roots of integer values of various measured parameters. Figures 4 and 5 are flow charts illustrating the method of the present invention for determining at least the square roots of integer values of various measured input parameters. Detailed Description Of Preferred Embodiment 8 Figure 3 shows the schematic block diagram of the present system 10 comprising the logic and control circuit 20. The logic and control circuit 20 comprises a logic circuit 21, a clock 22, a random-access-memory (RAM) 23 or other appropriate memory, and may include an analog-to-digital (A/D) converter 25 or a digital-to-analog (D/A) converter 26. The system 10 may further comprise communications 30, a keypad 40 and a display 50 for use with the logic circuit 21. The communications 30 enables the logic circuit 21 to communicate energy information from the logic circuit 21 to a remote processor (not shown) . As this capability is known to those skilled in the art, it will not be further described herein. The logic circuit 21 may comprise one or more microprocessors, each of which comprises a central processing unit (CPU) and a read-only-memory (ROM) . The logic circuit 21 may also be implemented using a dedicated configuration of digital logic elements, gate array technology or any other appropriate hardwired logic circuit technology. The logic circuit 21 interfaces with the clock 22, manages data flow to and from the RAM 23 and converters 25 and 26 and performs all computations for determining output signals that relate to the determined square root values of the values of the measured input parameters or input signals. The analog-to-digital converter 25 may be used to convert one or more analog input signals (1, 2, . . ., N; blocks 60a to 60n) to digital signals that are input to and processed by the logic circuit 21. Preferably, a twelve- bit analog-to-digital (A/D) converter 25 is used to provide better data resolution for controlling the various features, such as the alarm circuit, of the electronic circuit breaker system. It is believed, however, that an eight-bit analog-to-digital (A/D) converter may also provide adequate data resolution depending on the specific application. With respect to the present system, the analog or digital input signals may include any analog input signal used therein, including, for example, analog samples of the current, voltage and their sinusoidal components or harmonic characteristics. Of course, digital versions of these same input signals may also be input to the logic circuit 21 as digital input signals 70 (1, 2, . . ., N; blocks 70a to 70n) . The analog output signals 80 (1, 2, . . . , N; blocks 80a to 8On) may include any analog output signal used in electronic circuit breaker systems that measure energy usage. The analog circuits/switches 85 (1, 2, . . . , N; blocks 85a to 85n) may include the circuits or switches that are used to control, for example, an alarm in the electronic circuit breaker system. Of course, digital output signals 90 (1, 2, . . . , N; blocks 90a to 90n) may also be output to digital circuits/switches 95 (1, 2, . . . , N; blocks 95a to 95n) to the extent that the control signals are digital and not analog. The system 10 is an electronic circuit breaker system that is used to measure energy usage, such as is readily known and available to those skilled in the art. In this regard, the electronic circuit breaker systems may comprise the electronic circuit breaker trip units of the type produced by Siemens Energy & Automation, Inc. for their "SB" case system breaker product line. Of course, it is understood that the present system may be used with other similarly appropriate electronic circuit breaker trip units produced by other manufacturers without departing from the spirit and scope of the present invention. More particularly, the electronic circuit breaker trip unit (not shown) may include, for example, the "Dual Process Electric Power Trip Unit" of U.S. Patent 5,311,392, which is also assigned to Siemens Energy & Automation, Inc. The electronic circuit breaker trip unit may comprise a mechanical breaker portion that is used to interrupt or provide electrical power to an electrical load and an electronic portion that may be like the one shown in U.S. Patent No. 5,311,392. The protective features of the electronic circuit breaker system allow it to trip when certain events occur or to activate an alarm signal so as to sound an alarm or open the breaker, depending on the system configuration that the user selects. The feature of measuring energy usage that may be provided with such electronic circuit breaker trip units involves collecting current and voltage samples, determining and storing functions of these samples which may indicate significant events, and logging these events as they occur. Root-mean-square values are determined from sampled values of the monitored current and voltage input parameters taken over some interval, such as one second. Some sampling techniques and the methods that may be used to determine the RMS current and voltage values are described, for example, in U.S. Patent No. 5,311,392. Additionally, other parameters such as phase currents and voltages, average phase currents and voltages, average line-line voltages, ground and neutral currents, frequency, real power, reactive power, apparent power, power factor, kilowatt hours (KWH) and KWH reverse, kilovar hours, kilovar demand, harmonic distortion and any other appropriate parameters may also be determined from the current and voltage samples by methods well known to persons skilled in the art. The method for determining a polynomial root, where the polynomial is a square, of some of the various input parameters is done in the following way. As shown in Figures 1 and 2, for increasing X, the line function X 2 becomes more linear for a given unit change in X. For example, the function X 2 between X x =2 and X 2 =3 is less linear than the line function X 2 between X 1 =200 and X 2 =20l. 11 Accordingly, since X 2 is more linear at higher numbers on the X axis and since integer values on the X axis represent the whole root of the function X 2 , the decimal fractional part of the square root may be determined by determining the slope of the line between the whole roots bounding a particular value of X 2 for which the square root must be determined. The logic circuit 21 first obtains the whole root below the X 2 value from a look-up table which contains the square of an integer X ranging from 1 to 2" , where n = 8 for eight (8) bit integer values for a 16-bit microprocessor, since sixteen (16) bits are needed to represent the squared value of the whole root integer values so that X 2 ranges from 0 to 2 2r . In particular, for n=8, X ranges from 0 to 255 and X 2 correspondingly ranges from 0 to 65,025. If the value of X 2 is a perfect square, then the result from the look-up table is the square root of the value of X 2 . Otherwise, the result is the next lower whole root WR B corresponding to a perfect square that is below that particular value of X 2 . For example, where X 2 = 15, the whole root WR B of the square root from the look-up table is 3. To determine the decimal or fractional part DR of the square root of X 2 , the slope of the line between the lower whole root WR B and the next higher whole root WR A must be determined. This may be done by multiplying the whole root WR B which has a perfect square WR B 2 that is below the particular value of X 2 by two (2) and adding one (1) . The difference between X 2 and WR 9 2 is then divided by the slope (the divisor) to determine the remaining decimal fractional part DR of the square root of the value X 2 . Alternatively, of course, WR A may be used to determine the slope by multiplying the whole root WR A (which has a perfect square WR A 2 that is above the particular value of X 2 ) by two (2) and subtracting one (1) . More specifically, the square root of X 2 , where, for example, X 2 = 40,200 (see Figure 2), is determined as follows: The logic circuit 21 first uses the look-up table to fin d the closest whole root WR B having a perfect square WR 8 2 that is below the value of X 2 , namely 40,200. Next, the logic circuit 21 determines the difference between X 2 and WR B 2 . The logic circuit 21 then divides the difference of 200 between X 2 and WR S 2 by the slope of the line. The slope of the square of the parameter X is bounded by at least a first point X 2 and a second point WR S 2 , where the first point X 2 corresponds to a first value of the particular value of a square of a parameter X and the second point WR B 2 corresponds to a second value of the square of a parameter X, X = WR B 2 . Importantly, for values of X greater than 2, the slope of the line is equal to 2(X-1)+1, where X-l is the whole root WR B having a perfect square WR B 2 that is below the value of X 2 so that the slope of the line is equal to 2WR B + 1. Since processing speed is important, the logic circuit 21 scales WR B by a scaling factor SF2 that is 100 2 (SQRT (SF2) = 100) so as to maintain two (2) places of accuracy in the solution while using only integers. Next, the logic circuit 21 determines the decimal or fractional part DR of the square root, where the integer portion of DR = ((WR B x SF2)/(2WR B +1) )/(SQRT (SF2)), which is 49. The logic circuit 21 then returns the square root of the particular value of X 2 , which is WR B appended to DR, namely 20049. In comparison, the square root obtained using a floating point method would return 200.4993766. Also, if X 2 is less than 300, then the logic circuit 21 scales X 2 by the scaling factor SF2 (100 2 ) to shift the values toward the more linear f .art of the X 2 line function. The logic circuit 21 then determines the square root of the value of X 2 as described above, after which it divides it by the square root of SF2, where SQRT(SF2) = 100. 13 For values of X 2 equal to or greater than 85, the percentage difference with respect to the floating point method is on the order of about 0.10 percent. For values of X below 85, the percentage difference with respect to the floating point method ranges from on the order of about .10 percent to 0.30 percent. Significantly, it has been determined that the present method is on the order of about twenty- five (25) times as fast as double precision floating point methods used by a commercial C-language compiler available from Introl Inc. of Milwaukee, Wisconsin. Referring to Figure 4, this figure shows the specific logic flow chart and method for determining the square root of any appropriate value of some analog input parameter, such as current, voltage or some other appropriate input parameter, which the logic circuit 21 may then process so as to output signals, such as to control an alarm on the circuit breaker system or provide to a remote processor (not shown) through communications 30. First, in step S100, the logic circuit 21 has obtained the appropriate input parameter value or values and enters the main square root routine (MT_sqrt routine) . Next, in step S105, the logic circuit 21 sets a first scaling factor SF1 to one (1) and also sets the operational mode to the "Large X 2 " mode. In step S110, the logic circuit 21 determines whether the value of X 2 is less than 300, and if not, it continues to step S120. Otherwise, if the value is less than 300, then the logic circuit 21 scales the value of X 2 by a second scaling factor SF2 of loo 2 (i.e., 10,000), sets the mode to the "Small X 2 " mode and then continues to step S120. In step S120, the logic circuit 21 determines whether the value of X 2 exceeds the square of 2", where n may be 8 for a 16-bit microprocessor. The number n may, of course, vary 14 depending on how the software is written and the particular microprocessor or microcontroller that is used. If the value of X 2 does not exceed 65,536 (i.e., (2 8 ) 2 ) in step S120, then in step S130 the logic circuit 21 calls the (MT_get_root) subroutine to get or determine the whole root WR B of the value of X 2 from the look-up table. Figure 5 shows the logic flow chart for the get WR B (Mt_get_root) subroutine beginning at step S130, and is described later. If the logic circuit 21 determines in step S120 that the value exceeds 65,536, then in step S125 the logic circuit 21 divides the value by 4 2 (i.e., 16) and further scales SF1 by 4. The logic circuit 21 repeats step S120 until it determines that the value of X 2 does not exceed 65,536, after which the logic circuit 21 continues to step S130 and determines the whole root WR B of the value of X 2 from the look-up table. After determining WR B , in step S150, the logic circuit 21 determines the slope (divisor) of the line function X 2 by scaling the whole root WR 3 of the value WR S 2 by two (2) and adding one (1) (i.e., slope (or divisor) = (2WR B + 1)). In step S155, the logic circuit 21 determines the difference between WR B 2 and X 2 . Then, in step S160, the logic circuit 21 scales this difference by the scaling factor SF2, where SF2 = 100 2 (i.e., 10,000). In step S165, the logic circuit 21 divides the difference by the slope (or divisor), which was determined in step S150, * .o determine the decimal or fractional part DR of the square root of the particular value of X 2 . In step S170, the logic circuit 21 appends the fractional portion DR to the whole root WR 9 so as to provide the square root of the value of X 2 to two places. Additionally, if the logic circuit 21 is in the "Small X 2 " mode, then the logic circuit 21 must divide the answer or square root by 100 in step S180, since the 15 value of X 2 (i.e., the square of the square root) was scaled by SF2 (100 2 or 10,000) in step S115. Finally, the logic circuit 21 provides or returns the answer, namely the square root of the value of X 2 , in step S185 for further appropriate processing, such as determining the RMS current or voltage. Using the GET WR B (MT_get_root) subroutine to determine WR B , which begins at step S130, the logic circuit 21 determines the whole root portion WR 3 of the square root of the particular value of X 2 . In particular, in step S135, the logic circuit 21 looks up or searches the "squares table" for the value of X 2 . If the particular value of X 2 is found in step S140, then the logic circuit 21 returns WR B (which is an exact square root) in step S150 to the main routine, namely the main (MT_sqrt) routine. If the value is not found in step S140, then the logic circuit 21 determines the closest perfect square WR g 2 below the value of X 2 and the corresponding WR B/ which is the whole portion WR 3 of the square root of the closest perfect square below X 2 , and returns WR B in step S150 to the main program routine. Although the logic flow chart discussed in the specification and shown in Figures 4 and 5 is programmed into a well-known signal processor, namely a microprocessor, it may also be implemented using digital hardwired logic by persons having ordinary skill in the art. Since such digital circuit construction or programming per se is not part of the invention, no further description thereof is deemed necessary. While the present invention has been described in connection with what are the most practical and preferred embodiments as currently contemplated, it shι-.-ld be understood that the present invention is not limited to the disclosed embodiments. Accordingly, the present invention is intended to cover various modifications and equivalent arrangements, methods and structures that are within the spirit and scope of the claims. APPENDIX static csaat ΓAR ϋ * -"ORD HT_a uare3_table|"2S5) Ou , lc, 4 , 9u, ISc 25c, 36c 49c 64α, aiu lOOu, 121u, 144u, lS9u, 19άc, 22Su, 25SC 239c, 324c, 3όlu, 4G0u, 441u, 4a4c, S29u, 57Sc S2Su, 676c 729c, 734u, 341u, 9C0u, 961c, 1024c, 1039c, 1156c, 1225c, 1296u, 1369c, 1444c, 1521c, 1500c 1531c 1764c, 134Su, 1936c 2025c, 2115c, 2209u, 2304u, 2401c 25C0C 2501c 2704c, 23C9u, 2916c, 302Sc, 3136c 3249u, 3364c 3431c 25COc 3721c 3344c J553u, 4096c, 422Su, 43S6u, 4439c, 4524c, 4751c, 4900c 5041c, S184 , 532Sc, 547Su, S525u, 5776c 5929c, 6084c 6241c 54C0C 6551c, 6724u, saa9c, 70SSu, 7225c 739Su, 7559c 7744c 7921c 8100c, 8231c, 3464c, 8c49u, 3536c, 9025c 9216c, 5409c 9504c 9901c, lαcoou, 10201c 10404u, 10609c, lOSl≤c, 11025c 11235c, 11449c 11064c, ilSSic, 12100u, 12221c 12544c 12763c 12996c 13225c 13456c 1 689c 13924U, 14161U, 14400 , 14c41c 14334c 15129c 15376c 15625c, lS37Sc, 1S1_Σ9U, 15384c 16641c 15300c 17161c 17424c 17685c 17955c 1322Su, 19496c, 13759c, 19044u, 19221c 19S0Cc, 19SS1C 2 Q 164U, 2C443C, 2Q736c, * Z102Sc, 21316c, 21≤09u, 21304c 22201c, 22500c, 22Sαic 23104c, 23409c, 23715c, 24025c, 2423όu, 24649c, 24964c, 2Ξ231c 25600c, 2S=21c 25244c, 2=5S9c, 25396c, 272 5.; 27556u, 27333c, 25224c, 23561c, 2350CU, 29241c, 23534c 23929u, 3C275u, 30625u, 20970c 31329u, 31534 , 32041c 3240CC, 32761c, 33124c 33435c, 33355.:, 34225c 345SSU, 3495SC, 35344c, 35721c, 35100U, 36431c 36364c 37243c 27636c, 3aC25c, 33415u, 38a09c 33204c, 33S01u, 4αoαou, 40401c 40304c 41205c, 41615c 42025c, 42435c, 4ZS49C, 43264U, 43≤aiu, 44100u, 44521c 44944c, 4S3S9u, 45796c, 4622Sc 46656c r 47039u, 47524U, 47951c, 43400c. 43341u, 49234c, 45729c, 50176c, 5062SC, S1076u, 51529c 51934c, 52-J41.Ϊ, £250Gc 53361c, 53324c 54239c, 547S> * c 5S22SC, 55ά9Sc, Sόlό9c, 56644c 57121c £7ό00u, 53081c S8Sό4u, 59049c, 53536c 60023c 60516U, 61009c 61504c 62001c £250Cc 63001c, S3504u, 64009c, 64316c 6S025u }; " ■» Kama HX_=qr-t Der-crip-ticn. i Th s _TunctI.cn calculates the sσcara rcαt cf the value assed in. Thi. value ratexned has 2 deci_ιal digits bcilt in. JQΓ α a-opl , if 4 ia passed in, 200 (2.00) is retcrced, if 19 ia passed in, 43S (4.35) ia returned. Codaβ-nlt-h (g) . Hiie McXay ** » Ir.puta : valu. to ta a βςrt of (0 - 42949572295). ** Raturr.3 : soTTt of value times 100 with 2 deci-aal digits bcilt La. * ■• * Calls HT_get_roo-c * **■ Globala ncse •*" » Notes This βςrt algorithm is acccrata to < 0.1- fox- values > SS. The p-a-rcent error is in nc case greater than 0.4 for small nuπibers; fccharaora, in no case is the sbsclute di faranca between the value retcrned a.d the actual aqrt mere t aji 0.03 for βraali r.u-ibβrs- 7sr inatar.ca thα wor.β error is with 6. Here the sqrt shαcld be 2.449489743. This function ratumβ 2.44 which gives a -0.39 percent error or -0.01 difference. static πχ,ONG HT_aqrt ( . tJ ONG value ) DXOΓΓG root; /* Whαla numhar part ci atjcare rαo- » / UCJOKC diviaαr; , /« • Divisor used to ge frr ionαJL parr ■» / TH.OKC multiplier = -1; /* 7jnal answer -suitipliez / B OLZA. * amall_nua = TX SZ; /" Value < 300 flag * /* Tα c/et better accuracy on seal! ncώβrs, e will multiply the number by 10C00, then run it through the lgori hm, removing 100 f cs: the £- nn ~l answer. Thin esechcd lβ:a t-c number carry .lore decimal information with it throug.1 the algorithm. if (value < 30Qul) { value *= 1C000; β-nall_-n m — TSXS ; > I* The squares table car. cr.ly handle values up to 65S36. Therefore, if the aaasbβr passe ia is greater, we will divide until it is lass. At the e d we can adjust the rssuit to account far the division that we are doing here. while (value > S5536ul) { / w Divide by IS and iccreast. the multiplier by four each time until the scaled value i3 leas than 65S37. */ value /= 15ul; multiplier *= 4ul; > /* <"÷et the whole nuraber pa cf the square root. * */ root = HI gat_rcct ( value ) ; /* Cet the divisor βo that the decimal part cf the sqrt can be found. The divisor s the slope ci the line " between the whole roots. *"* cr all numbers greater than 2, the next squared value la equal tα the root of the current value ti ea 2 plus 1 plus the current value. Xherecore, the slope is tns rocc of the current value times 2 plus 1. */ divisor = lul •+• (root * 2ul); /» Find rhe difference between the scaled value and the square of the root. value -= (root * root) ; /** ■ Since this is all intagsr math, multiply by 10000 tα ba able tα maintain a couple of decimal places. */ value » = lOOOO-ul; /* Divide the adjusted value by the divisor to gat the decimal portion of the βqrt. "/ value /= divisor; /* Combine the whole and fractional parts cf tiie scaled sqrt/ then multiply by the mulciDiier to get back to the unsealed sqrt. */ value - ((root * lOOul) * (valua / lOC iJ J * multiplier; /" If t he input was < 300, the esul must also be adjusted for t he lOOσσ t hat was multiplied in at the beginning. » / if (amall_cua =» F * ?-X.SΞ) < returr. ( value ) / } /" »..— • *»#*.,.*»„ *♦,**♦*.♦*.,»**»»»• *-.* « • * Name : HT_get_rcαt »" * Deβcr/iptian : Thia function gets the rcot cf the value passed ir. free ** the squares table. The methcd fcr fir.di.ig the value ia a * " • binary search. The value parsed lr. ia a. lcng; cweter, tie "♦ value feu at not ba > QxlQQCO (a word + 1) . * » - * ( β ) : 2£i"-ce KcKoy static UXOKG H ** r_get_root( ULONG value ) < BOO£- * £-A- * < got index - FM.SΞ; /' ?lag that the root has been found */ t * XONG i-dαx = 128; / * Square table index */ U3 * rτ * £ i = 123; / ** counter » / / ♦ Look through the table until- the rαct ia found or the closest --hole root. With the hiπar/ search method, we 5c asp dividing the table _nto pieces st.'.xtin in the center. while (gαt_i.ιdβx =- 7\LSc) { L »— 1; L£ (HT_squarea_taiιle[ index] i- value) /" If the table value ia less we go higher, otherwise we go l ver, if • KT_βguareβ_table'index j < value ) index += i; > else index -* i,- /* If a get to 1, we are aa close to the value aa we are goiog to get; however, if wa ara acove the value, wc need to auatract one. "/ i£ (i == 1) if (HZ βquarea table'index] > value) index — ; > gαt_iπdax = XRtrz ; /* If the value passed in is a perfect square, we uUl find it in the able. '/ } else { gσt_index = THtS > } /• Ret n the iπdβac which is the root of hs value passed La. . » / rβturr. ( i-zdex ) ;

Claims: 21 WHAT IS CLAIMED IS: 1. A method of determining a square root of a particular value of a square of a parameter for use with an electronic circuit breaker system comprising the steps of: determining a whole root of said square root of a particular value of said square of a parameter; determining a slope of said square of a parameter bounded by at least a first point and a second point, where said first point corresponds to a first value of said square of a parameter and said second point corresponds to a second value of said square of a parameter; determining a difference between said particular value of said square of a parameter and a value of a square of said whole root; determining a fractional part of said square root of a particular value of said square of a parameter using said slope and said difference; and combining said whole root of said square root and said fractional part of said square root. 2. The method of claim 1, in which said whole root is determined by using a look-up table to find a whole root of a perfect square nearest said particular value of said square of a parameter. 3. The method of claim l, in which said fractional part of said square root is determined by determining a ratio of said difference and said slope. 4. The method of claim 1, in which said slope is determined by using said whole root. 5. The method of claim 4, in which said slope is determined by scaling said whole root. /37299 22 6. A processor system for determining a square root of a particular value of a square of a parameter for use with an electronic circuit breaker system, comprising: a logic circuit receiving and using at least one input signal to process and output at least one output signal, wherein said logic circuit is configured to determine a whole root of said square root of a particular value of said square of a parameter, wherein said logic circuit is configured to determine a slope of said square of a parameter bounded by at least a first point and a second point, where said first point corresponds to a first value of said square of a parameter and said second point corresponds to a second value of said square of a parameter, wherein said logic circuit is configured to determine a difference between said particular value of said square of a parameter and a value of a square of said whole root, wherein said logic circuit is configured to determine a fractional part of said square root of a particular value of said square of a parameter using said slope and said difference, wherein said logic circuit is configured to determine said square root by combining said whole root of said square root and said fractional part of said square root, and wherein said logic circuit outputs at least one output signal using said square root. 7. The system of claim 6, in which said logic circuit determines said whole root by using a look-up table to find a whole root of a perfect square nearest said particular value of said square of a parameter. 8. The system of claim 6, in which said logic c _cuit determines said fractional part of said square root by determining a ratio of said difference and said slope. /37299 23 9. The system of claim 6, in which said logic circuit determines said slope by using said whole root. 10. The system of claim 9, in which said logic circuit determines said slope by scaling said whole root. 11. A method of determining a polynomial root of a particular value of a polynomial of a parameter for use with an electronic circuit breaker system comprising the steps of: determining a whole root of said polynomial root of a particular value of said polynomial of a parameter; determining a slope of said polynomial of a parameter bounded by at least a first point and a second point, where said first point corresponds to a first value of said polynomial of a parameter and said second point corresponds to a second value of said polynomial of a parameter; determining a difference between said particular value of said polynomial of a parameter and a value of a polynomial of said whole root; determining a fractional part of said polynomial root of a particular value of said polynomial of a parameter using said slope and said difference; and combining said whole root of said polynomial root and said fractional part of said polynomial root. 12. The method of claim 11, in which said whole root is determined by using a look-up table to find a whole root of a perfect polynomial nearest said particular value of said polynomial of a parameter. 13. The method of claim 11, in which said fractional part of said polynomial root is determined by determining a ratio of said difference and said slope. 14. The method of claim 11, in which said slope is determined by using said whole root. 24 15. The method of claim 14, in which said slope is determined by scaling said whole root. 16. A processor system for determining a polynomial root of a particular value of a polynomial of a parameter for use with an electronic circuit breaker system, comprising: a logic circuit receiving and using at least one input signal to process and output at least one output signal, wherein said logic circuit is configured to determine a whole root of said polynomial root of a particular value of said polynomial of a parameter, wherein said logic circuit is configured to determine a slope of said polynomial of a parameter bounded by at least a first point and a second point, where said first point corresponds to a first value of said polynomial of a parameter and said second point corresponds to a second value of said polynomial of a parameter, wherein said logic circuit is configured to determine a difference between said particular value of said polynomial of a parameter and a value of a polynomial of said whole root, wherein said logic circuit is configured to determine a fractional part of said polynomial root of a particular value of said polynomial of a parameter using said slope and said difference, wherein said logic circuit is configured to determine said polynomial root by combining said whole root of said polynomial root and said fractional part of said polynomial root, and wherein said logic circuit outputs at least one output signal using said polynomia root. 17. The system of claim 16, in which said logic circuit determines said whole root by using a look-up table to find a whole root of a perfect polynomial nearest said particular value of said polynomial of a parameter. 25 18. The system of claim 16, in which said logic circuit determines said fractional part of said polynomial root by determining a ratio of said difference and said slope. 19. The system of claim 16, in which said logic circuit determines said slope by using said whole root. 20. The system of claim 19, in which said logic circuit determines said slope by scaling said whole root. 21. A processor system for determining a square root of a particular value of a square of a parameter for use with an electronic circuit breaker system, comprising: a logic circuit means for receiving and using at least one input signal to process and output at least one output signal, wherein said logic circuit means determines a whole root of said square root of a particular value of said square of a parameter, wherein said logic circuit means determines a slope of said square of a parameter bounded by at least a first point and a second point, where said first point corresponds to a first value of said square of a parameter and said second point corresponds to a second value of said square of a parameter, wherein said logic circuit means determines a difference between said particular value of said square of a parameter and a value of a square of said whole root, wherein said logic circuit means determines a fractional part of said square root of a particular value of said square of a parameter using said slope and said difference, wherein said logic circuit means determines said square root by combining said whole root of said srr ire root and said fractional part of said square root, and wherein said logic circuit means outputs at least one output signal using said square root. 26 22. A processor system for determining a polynomial root of a particular value of a polynomial of a parameter for use with an electronic circuit breaker system, comprising: a logic circuit means for receiving and using at least one input signal to process and output at least one output signal, wherein said logic circuit means determines a whole root of said polynomial root of a particular value of said polynomial of a parameter, wherein said logic circuit means determines a slope of said polynomial of a parameter bounded by at least a first point and a second point, where said first point corresponds to a first value of said polynomial of a parameter and said second point corresponds to a second value of said polynomial of a parameter, wherein said logic circuit means determines a difference between said particular value of said polynomial of a parameter and a value of a polynomial of said whole root, wherein said logic circuit means determines a fractional part of said polynomial root of a particular value of said polynomial of a parameter using said slope and said difference, wherein said logic circuit means determines said polynomial root by combining said whole root of said polynomial root and said fractional part of said polynomial root, and wherein said logic circuit means outputs at least one output signal using said polynomial root.

Inventors: MCKOY MICHAEL E, MCKOY, MICHAEL, E.
Applicants: SIEMENS ENERGY & AUTOMAT, SIEMENS ENERGY & AUTOMATION, INC.
Application year: 1997
Main classification: G06F7
IPC codes: G06F7