MOS logic circuit

Abstract: A MOS logic circuit in the present invention is charged by adiabatic charging, and is composed of a clamp circuit (CLP) having a pair of PMOS transistors (MP1,MP2), and two functional circuits, each having at least one NMOS transistor (MN1,MN2), a gate electrode of each of the NMOS transistors being an input node, one terminal of each functional circuit being connected to a common constant-voltage power source, and the other terminal of each functional circuit being connected to a drain electrode of the corresponding PMOS transistor, thus forming an output node. A substrate electrode of each of the NMOS transistors making up the two functional circuits is cross-connected to the output node of the other functional circuit. In this way, even in the HOLD operation, in which both input nodes fall to low level, the NMOS transistor which is to output low level becomes depletion mode, and the outputting operations are stabilized without increasing circuit size.

Description: FIELD OF THE INVENTION The present invention as it is defined in the appended claims is generally concerned with a logic circuit provided in a MOS integrated circuit, and in particular with a MCS logic circuit which uses adiabatic charging to achieve low power consumption. BACKGROUND OF THE INVENTION An adiabatic charging circuit is one method of reducing power consumption in MOS chip logic circuits, as proposed by Seitz, C.L., Frey, A.H., Mattisson, S., Rabin, S.D., Speck, D.A., and van de Snepscheut, J.L.A. in "Hot-Clock nMOS," Proceedings of the 1985 Chapel Hill Conference on VLSI , pp. 1-17 (Computer Science Press, 1985). The following will explain this adiabatic charging. In charging the voltage of a certain node in a standard CMOS circuit, from the time the switch connected to the power source (MOSFET) is closed until the node (capacity C) is fully charged, the resistance of the switch results in the dissipation of (1/2) × CV 2 of energy, where V is the potential difference across the switch. However, when the potential of the node and the potential of the power source are equal, the current will not flow through the switch even when the power source and the node are connected through the switch, and there will accordingly be no dissipation of energy due to the resistance of the switch. Accordingly, when the voltage of the power source is increased slowly in comparison with the time constant RC of the switch resistance R and the node capacitance C, it is possible to increase the potentials of the node and the power source in such a way that the potential difference across the switch is reduced and so that the potentials of the node and the power source remain close to one another. In this way, the potential of the node can be balanced with the power source, and the capacitance of the node can be charged adiabatically. In such a case, the energy dissipated by the resistance of the switch will be: E = ∫ T 0 RI 2 dt = ∫ T 0 R C dV dt dt Here, T is the time necessary for this process, and V (t) is the voltage characteristic of the capacitance. If the curve of the voltage is a line, R and T are constant, and T RC, then equation (1) above becomes analogous to equation (2) below: E = (1/2) • CV 2 • (2RC/T) If the curve of the voltage is a sine wave, equation (2) above is multiplied by the coefficient π 2 /8. Equation (2) above shows that if T is increased infinitely, the amount of energy necessary to charge the node capacity can be reduced to zero. This method of quasi-static charging is the adiabatic charging referred to above. The amount of energy dissipated in this adiabatic charging is substantially different from that in standard CMOS charging, where, as noted above, (1/2) × CV 2 of energy is dissipated, regardless of time; i.e., regardless of constant RC. For example, in the case of the CMOS inverter shown in Figure 7, when input IN sent to input node KI changes as shown in Figure 8(a), output OUT - from output node KO will change as shown in Figure 8(b). More specifically, when the input IN falls from high level to low level at time t11, PMOS transistor QP is turned on, and NMOS transistor QN is turned off. Accordingly, the charging current (shown by reference symbol I1) from power line 1 flows through the PMOS transistor QP to charge the output node KO. The output node KO will be charged to the potential Vdd of the power source to which the power line 1 is connected. In contrast, when the input IN rises from low level to high level at time t12, the PMOS transistor QP is turned off, and the NMOS transistor QN is turned on. The charge of the output node KO is discharged (as discharge current I2) through the NMOS transistor QN to power line 2. Accordingly, in this kind of regular charging, as shown in Figure 9, the energy loss due to switching results from the potential difference V1 between the fixed potential Vdd of the power source (shown by reference symbol α1) and the potential of the output node KO (shown by reference symbol α2). In contrast, in the adiabatic charging method mentioned above, the potential of the power source changes as shown by reference symbol α3, and accordingly the potential of the output node KO also changes as shown by reference symbol α4. Thus the energy loss is reduced to a small amount corresponding to the potential difference shown by reference symbol V2. In recent years many MOS transistor circuits using this kind of adiabatic charging have been proposed, for example, Moon, Y. and Jeong, D.-K.: "Efficient Charge Recovery Logic," 1995 Symposium on VLSI Circuits: Digest of Technical Papers, pp. 129-130 (May 1995), and Kramer, A., Denker, J.S., Flower, B., and Moroney, J.: "2nd Order Adiabatic Computation with 2N-2P and 2N-2N2P Logic Circuits," Porc. Int. Symp. Low Power Design , pp. 191-196 (Dana Point, April 1995). Figure 10 shows MOS logic circuit F0, a typical example of this kind of conventional art. This MOS logic circuit F0 is the inverter/buffer gate of a dual rail logic circuit called an "ECRL (Efficient Charge Recovery Logic) Circuit" or a "2N-2P Circuit." In brief, this MOS logic circuit F0 is arranged so that a serial circuit consisting of a PMOS transistor QP1 and an NMOS transistor QN1, and a serial circuit consisting of a PMOS transistor QP2 and an NMOS transistor QN2 are connected in parallel between power lines 1 and 2. The gate electrodes of the NMOS transistors QN1 and QN2 are connected to a first input node KI1 and a second input node KI2, respectively; an input IN + is applied to the gate electrode of the NMOS transistor QN1, and an input IN - , which is logic-inverted with respect to the input IN + , is applied to the gate electrode of the NMOS transistor QN2. The connection between the drain electrode of the PMOS transistor QP2 and the drain electrode of the NMOS transistor QN2 provides a first output node KO1, from which the output OUT + is applied to the gate electrode of the PMOS transistor QP1, to which it is cross-connected. In the same way, the connection between the drain electrode of the PMOS transistor QP1 and the drain electrode of the NMOS transistor QN1 provides a second output node KO2, from which the output OUT - is applied to the gate electrode of the PMOS transistor QP2, to which it is cross-connected. The power line 1 is connected to a pulse power source , the voltage output level of which changes between ground level and a fixed high level Vdd. The power line 2, on the other hand, is connected to the output of a constant-voltage power source, the output level of which is equal to the ground level. Figure 11 is a wave-form diagram showing the operation of the MOS logic circuit F0 arranged as described above. In this MOS logic circuit F0, the operations of one cycle consist of four operations: "RESET," "WAIT," "EVALUATE," and "HOLD." The wave forms of the input IN + , the input IN - , the pulse power source , the output OUT - , and the output OUT - on Figure 10 correspond to Figure 11 (a), (b), (c), (d), and (e), respectively. First, in the RESET operation, the change in the level of the pulse power source  from high level to low level (see Figure 11 (c)) is accompanied by a drop to low level of the output nodes KO1 and KO2, thereby erasing the respective data of the output nodes KO1 and KO2 (see Figure 11 (d) and (e)). Next, in the WAIT operation, the voltage output level of the pulse power source  remains at low level, while the input to either one of the input nodes (in the example in Figure 10, the input IN - to the input node KI1; see Figure 11 (a)) rises from low level to high level. After an input state is established in this way, the EVALUATE operation is performed, in which the pulse power source  rises from low level to high level (see Figure 11 (c)). At this time, since, as stated above, the input IN + is high level, and the input IN - is low level, the NMOS transistor QN1 is turned on, but the NMOS transistor QN2 is turned off; the PMOS transistor QP2 is turned on, and the level of the output OUT + rises in response to the rise in the output voltage of the pulse power source  (see Figure 11 (d)). Further, at this time, the MOS transistors QN2 and QP1 remain off, and the output OUT - remains at low level (see Figure 11 (e)). After the potentials of the output nodes KO1 and KO2 are established, the HOLD operation is performed, in which both the input nodes KI1 and KI2 fall to low level, and the input data is erased (see Figure 11 (a) and (b)). The gate electrodes of the PMOS transistors QP1 and QP2, as stated above, are cross-connected to the output nodes KO1 and KO2, and therefore when the inputs IN + and IN - are erased, the NMOS transistors QN1 and QN2 are both turned off, but the high level of the output node KO1 is maintained (see Figure 11 (d)), and the low level of the output node KO2 is dynamically maintained because it is cut off from the constant-voltage power source. In the next cycle, after performing a RESET operation in the same way, during a WAIT operation, the input IN - rises from low level to high level, and the input IN + remains at low level. As a result, in the next HOLD operation, the output OUT - is maintained at high level (see Figure 11 (e)) and the output OUT + is at low level (see Figure 11 (d)). The inverter/buffer operations are performed as described above. By replacing the NMOS transistors QN1 and QN2, which are functional circuits, with the serial and/or parallel connections of a plurality of MOS transistors, a MOS logic circuit F0 can be a unit logic circuit capable of outputting the desired combinational logic in accordance with the above-noted connections. Further, a circuit can be structured in sequence using the unit logic circuits. For example, by using the inverter/buffer shown in Figure 10 as a unit logic circuit, and connecting several such unit logic circuits in a multi-stage cascade, a sequential circuit such as that shown in Figure 12 can be provided. Such a sequential circuit can be used, for example, as a shift register. In the example shown in Figure 12, inverter/buffers F1, F2, F3, and F4 are driven by pulse power sources 1, 2, 3, and 4, the phases of which are shifted 1/4 cycle away from one another. It is sufficient if the pulse power sources 3 and 4 have the opposite phases with respect to 1 and 2, respectively, so that 3= 1 and 4= 2 . Inputs IN - and IN - are sent to the first-stage inverter/buffer F1, and the output of each of the inverter/buffers F1, F2 and F3 is sent to the following inverter/buffer F2, F3, and F4, respectively. Outputs OUT + and OUT - are outputted from the last-stage inverter/buffer F4. A wave-form diagram of the operations of the pulse power sources 1, 2, 3, and 4 is shown in Figure 13. Next, the operations of the inverter/buffers F1 through F4 at t0, t1, t2, and so on are shown in Figure 14. In Figure 14, "#1" shows the data of the first cycle, and "#2" shows the data of the second cycle. In this way, the data #1, #2, and so on are shifted sequentially to the following stages each 1/4 cycle, in synchronization with the cycles of the pulse power sources 1 through 4. In the foregoing conventional MOS logic circuit, if the NMOS transistor QN1 or QN2 is turned on, the output node KO2 or KO1, respectively, will be maintained at low level. However, as mentioned above, during the HOLD operation, the input nodes KI1 and KI2 both fall to low level, and when the NMOS transistor QN1 or QN2 is turned off, whichever of the output nodes KO2 and KO1 is to output a low level is only maintained dynamically, and therefore is prone to be influenced by neighboring circuits, etc. For example, in cases like the shift register shown in Figure 12, each logic circuit connected in cascade becomes unstable due to the influence of logic switching in the neighboring circuit, thereby causing logic errors. This creates the problem of limitations in circuit design, such as not being able to place adjacent to one another circuits operated by pulse power sources of different phases; i.e., different pulse power sources. Further, in the MOS logic circuit F0, as shown in Figure 15, there are parasitic pn diodes shown by reference symbols D1 and D2 between the drain of the NMOS transistor QN1 and p well 5, and between the drain of the PMOS transistor QP1 and n well 6, respectively. For this reason, when the RESET operation is performed when the output node KO2 is outputting a low level, since in the initial state of the RESET operation the pulse power source  is high level and the input node KI1 low level, the pn diode D2 between the drain of the PMOS transistor QP1 and the p well 6 is reverse biased, and a charge is stored in the junction capacitance of the pn diode D2. Conversely, since the same potential is applied across the pn diode D1 between the drain of the NMOS transistor QN1 and the n well 5, no charge is stored in the junction capacitance of the pn diode D2. Accordingly, when the pulse power source  falls from high level to low level in the RESET operation, the charge stored in the junction capacitance of the pn diode D2 is distributed to the junction capacitance of the pn diode D1, and therefore the potential of the output node KO2 drops to a negative value, which is lower than the ground level which is the output level of the constant-voltage power source. Hence the problem arises that that much additional energy is required in recharging. Other conventional art intended to solve this kind of problem is the 2N-2N2P circuit proposed in the paper by Kramer, et.al. referred to above. Figure 16 is an electrical circuit diagram of a MOS logic circuit F10 of the type proposed by this other conventional art. In this MOS logic circuit F10, elements similar to and corresponding with those in the MOS logic circuit F0 shown in Figure 10 will be given the same reference symbols, and explanation thereof will be omitted. In this MOS logic circuit F10, NMOS transistors QN3 and QN4 are provided parallel to NMOS transistors QN 1 and QN2, respectively. The gate electrode of the NMOS transistor QN3 is connected to the gate electrode of a PMOS transistor QP1, i.e., to an output node KO1, and the gate electrode of the NMOS transistor QN4 is connected to the gate electrode of a PMOS transistor QP2, i.e., to an output node KO2. Accordingly, during the HOLD operation, when, for example, the output node KO1 is maintained at high level, the NMOS transistor QN3 is turned on, so even if the input IN + drops to low level, the output node KO2 can be stably maintained at a low level. In this way, the MOS logic circuit F10 is arranged so that even if both the inputs IN + and IN - fall to low level, the low-level output remains stable. Further, when the RESET operation is performed when the output OUT - from the output node KO2 is at low level, the NMOS transistor QN3 is turned on, or if when the output OUT + from the output node KO1 is at low level, the NMOS transistor QN4 is turned on, and in either case there will be no storage of a charge as shown in Figure 15. Thus power consumption can be held to a minimum. Although there is more freedom of design with the MOS logic circuit F10 because there is no influence from neighboring circuits, it has the problem that two additional NMOS transistors QN3 and QN4 per unit logic circuit are required, and that the size per unit logic circuit is increased by 6/4 times. SUMMARY OF THE INVENTION The object of the present invention is to provide a MOS logic circuit capable of stable operations with low power consumption and without causing increase in circuit size. In order to attain this object, a MOS logic circuit of the present invention is comprised of: (1) a clamp circuit having a pair of PMOS transistors, the gate electrode of each of which is cross-connected to the drain electrode of the other, and the source electrode of each of which is connected to a pulse power source; and (2) two functional circuits, each of which has at least one NMOS transistor, the gate electrode of each NMOS transistor serving as an input node, one terminal of each functional circuit being connected to a common constant-voltage power source, and the other terminal thereof being an output node and being connected to the drain electrode of the corresponding PMOS transistor; the substrate electrode of each of the NMOS transistors making up the functional circuits being cross-connected to the output node of the other functional circuit. With this arrangement, if each of the functional circuits is made up of one NMOS transistor, the MOS logic circuit will be a basic circuit referred to above as the 2N-2P circuit, which is capable of low-power-consumption operation through adiabatic charging. In this kind of MOS logic circuit, the substrate electrode of each NMOS transistor is cross-connected to the output node of the other functional circuit. Accordingly, during a HOLD operation in which both the inputs are at low level while the pulse power source remains at high level, high level is applied to the substrate of the NMOS transistor which is to output a low level, and the NMOS transistor is given a forward bias so as to have depletion-mode characteristics, and maintains its on condition. In this way, logic errors due to the influence of neighboring circuits can be prevented without causing increase in the number of NMOS transistors or increased circuit size. Further, because of the forward bias mentioned above, even if a RESET operation is performed while the output is at low level, the corresponding NMOS transistor will remain on without fail, the capacitive coupling shown in Figure 15 will not occur, and thus the consumption of additional power during recharging can be avoided. The other objects, features, and superior points of this invention will be made clear by the description below. Further, the advantages of this invention will be evident from the following explanation in reference to the Figures. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an electric circuit diagram of a MOS logic circuit in the first embodiment of the present invention. Figure 2 is a graph explaining operation characteristics of an NMOS transistor. Figure 3 is a fragmentary cross-sectional diagram of a MOS logic circuit, explaining one concrete example of a structure for the MOS logic circuit shown in Figure 1. Figure 4 is a fragmentary cross-sectional diagram of a MOS logic circuit, explaining another concrete example of a structure for the MOS logic circuit shown in Figure 1. Figure 5 is an electric circuit diagram of a MOS logic circuit in the second embodiment of the present invention. Figure 6 is an electric circuit diagram of a MOS logic circuit in the third embodiment of the present invention. Figure 7 is a circuit diagram explaining the charging and discharging operations of a CMOS inverter. Figures 8 (a) and (b) are wave-form diagrams explaining the operations of the CMOS inverter shown in Figure 7. Figure 9 is a graph explaining the difference between regular charging and adiabatic charging. Figure 10 is an electric circuit diagram of a typical conventional MOS logic circuit using this adiabatic charging. Figures 11 (a) through (e) explain both the present invention and the conventional art, and are a wave-form diagram explaining the operations of the MOS logic circuits shown in Figures 1, 10, and 12. Figure 12 is an electric circuit diagram of a shift register realized by the MOS logic circuit shown in Figure 10. Figure 13 is a wave-form diagram of a pulse power source, for explaining the operations of the shift register shown in Figure 12. Figure 14 is a diagram showing the operating states of each inverter/buffer, for explaining the shift register shown in Diagram 12. Figure 15 is an explanatory diagram showing a fragmentary cross-section of the MOS logic circuit shown in Figure 10, for explaining problems with the MOS logic circuit shown therein. Figure 16 is an electric circuit diagram of another conventional MOS logic circuit. DESCRIPTION OF THE EMBODIMENTS The following is an explanation of the first embodiment of the present invention, referring to Figures 1 through 4 and Figure 11. Figure 1 is an electric circuit diagram of MOS logic circuit LOG in accordance with the first embodiment of the present invention. The MOS logic circuit LOG is a unit logic circuit. Numbers of the MOS logic circuits LOG may be combined and assembled together in, for example, cascade connection on an integrated circuit substrate in order to obtain the desired logic between input and output. In brief, the MOS logic circuit LOG is made up of a clamp circuit CLP and two functional circuits FUN1 and FUN2. The clamp circuit CLP is made up of a pair of PMOS transistors MP1 and MP2. The MOS logic circuit LOG shown in Figure 1 shows an inverter/buffer as one example of a logic circuit, and thus takes the form of a basic circuit structure in which the respective functional circuits FUN1 and FUN2 have one NMOS transistor, i.e., NMOS transistors MN1 and MN2, respectively. The source electrode of each of the PMOS transistors MP1 and MP2 is connected to a common power line 11, and the power line 11 is connected co a pulse power source  for performing adiabatic charging. The gate electrode of each of the NMOS transistors MN1 and MN2, on the other hand, is connected to input nodes HI1 and HI2, respectively, through which inputs IN and IN are applied. Further, the source electrode of each of the NMOS transistors MN1 and MN2 is connected, through a power line 12, to a constant-voltage power source which outputs a ground level. The drain electrode of the PMOS transistor MP1 and the drain electrode of the NMOS transistor MN1 are connected to each other, providing output node HO2, which outputs the output OUT . The output node HO2 is also cross-connected to the gate electrode of the PMOS transistor MP2. In the same way, the drain electrode of the PMOS transistor MP2 and the drain electrode of the NMOS transistor MN2 are connected to each other, providing output node HO1, which outputs the output OUT. The output node HO1 is also cross-connected to the gate electrode of the PMOS transistor MP1. The gate electrode of the PMOS transistor MP1 is connected to the substrate electrode BP1 of the PMOS transistor MP1, and the gate electrode of the PMOS transistor MP2 is connected to the substrate electrode BP2 of the PMOS transistor MP2. Accordingly, when the pulse power source  rises to high level while the input IN is at high level, the NMOS transistor MN1 is turned on, and the output OU T falls to low level. As a result, the PMOS transistor MF2 is turned on, and the output OUT rises to high level. Conversely, when the pulse power source  rises to high level while the input IN is at high level, the NMOS transistor MN2 is turned on, and the output OUT falls to low level. As a result, the PMOS transistor MP1 is turned on, and the output OUT rises to high level. It should be noted that, in the present invention, the substrate electrode BN1 of the NMOS transistor MN1 is connected to the gate electrode of the PMOS transistor MP1, i.e., to the output node HO1, and that when the output OUT rises to high level, the NMOS transistor MN1 becomes forward biased. In the same way, the substrate electrode BN2 of the NMOS transistor MN2 is connected to the gate electrode of the PMOS transistor MP2, i.e., to the output node HO2, and when the output OUT rises to high level, the NMOS transistor MN2 becomes forward biased. The threshold voltages of the NMOS transistors MN1 and MN2 are adjusted so that when the substrate electrodes BN1 and BN2 are at low level (ground level), the NMOS transistors MN1 and MN2 show enhancement mode transistor characteristics as shown by reference symbol β1 on Figure 2, and when the substrate electrodes BN1 and BN2 are at high level (i.e., when the pulse power source  is at peak voltage Vdd), the NMOS transistors MN1 and MN2 show depletion mode transistor characteristics as shown by reference symbol β2 on Figure 2. The operations of the MOS logic circuit LOG structured as described above are as shown in Figure 11. The wave forms of the input IN, the input IN , the pulse power source , the output OUT, and the output OUT in Figure 1 correspond to Figure 11 (a), (b), (c), (d), and (e), respectively. First, in the RESET operation, when the pulse power source  falls from high level to low level, the high-level output (in the example in Figure 11, (d), which is the output OUT) also falls to low level, and as a result the output data is erased. In the WAIT operation, the pulse power source  remains at low level, and either the input IN or the input IN (in the example in Figure 11, (a), which is the input IN) rises from low level to high level. When high-level input has been established in this way, by means of the EVALUATE operation, the input which is high level (Figure 11 (a)) is maintained at high level, and the voltage of the pulse power source  rises from low level to high level. This is accompanied by a rise from low level to high level in the output which is to be high-level (in the example in Figure 11, (d), which is the output OUT). When the output has been established in this way, by means of the HOLD operation, even if both of the inputs IN and IN fall to low level and the input is erased, the high-level output is maintained. In operations such as those described above, in the present invention, during the HOLD operation, the substrate electrode of whichever of the NMOS transistors MN1 and MN2 is to output a low level has a high-level output applied to it, thus stably maintaining the other output at a low level. For example, if the NMOS transistor NM1 is to output a low level, the high-level output OUT is applied to the substrate electrode BN1 of the NMOS transistor NM1, and, as shown in Figure 2, the characteristics of the NMOS transistor MN1 become depletion mode, and the output OUT is stably fixed at a low level. In this state, even if the RESET operation is performed, the NMOS transistor MN1 will be turned on without fail, the capacitive coupling shown in Figure 15 will not occur, and thus the consumption of additional power during recharging can be avoided. Accordingly, even when many MOS logic circuits LOG (which are the unit logic circuits) are combined, stable operations can be performed without influence from neighboring circuits, thus increasing the freedom of circuit design. Furthermore, in fixing the low-level output at the ground level in this way, whereas in the MOS logic circuit F10 shown in Figure 16, the NMOS transistors QN3 and QN4 were necessary, in the present invention, the circuit remains the 2N-2P circuit structure discussed above, and increase of the number of transistors, and of circuit size, is avoided. In addition to the foregoing effect, since the substrate electrodes BP1 and BP2 of the PMOS transistors MP1 and MP2 are connected to the respective gate electrodes of the PMOS transistors, their threshold voltages can be reduced, and a low operating voltage can be used. In this way, further reduction in power consumption can be realized. In the present invention, the substrate potential of each of the MOS transistors MP1, MP2, MN1, and MN2 must be controlled separately, but this may be realized by means of a structure such as those shown in Figures 3 and 4. Figure 3 is a cross-sectional diagram explaining one concrete example of a structure for realizing the MOS logic circuit LOG in the present invention. This structure is a so-called an SOI (Silicon On Insulator) structure, and Figure 3 shows the vicinity of MOS transistors MN1 and MP1. In a SIMOX substrate, which is a representative SOI structure substrate, the surface of silicon substrate 21 is impregnated with oxygen, and then heat-treated to provide insulating layer 22, thus insulating and separating the silicon substrate 21 from the other elements provided above it. When the regular MOS transistor manufacturing process is carried out on a substrate of this type, each transistor will be separated from the other by insulator. Alternatively, instead of the structure shown in Figure 3, the structure shown in Figure 4 is also possible. In this case, on the surface of silicon substrate 31 in the NMOS transistor MN1 area, deep n well 32 is first provided, and in the PMOS transistor MP1 area, deep p well 33 is provided. On top of these wells 32 and 33 are then provided shallow p well 34 and shallow n well 35, respectively, and the shallow p well 34 and the shallow n well 35 become the substrates for the NMOS transistor MN1 and the PMOS transistor MP1, respectively. On the shallow p well 34 are provided a source area SN1, a drain area DN1, and a substrate electrode BN1, as well as a gate electrode GN1, etc., and on the shallow n well 35 are formed a source area SP1, a drain area DP1, and a substrate electrode BP1, as well as a gate electrode GP1, etc. Each of the MOS transistors MN1 and MP1 maintains good insulation from the other by means of so-called trench separation, in which the insulator separation is realized by trenches 36 provided around the perimeter of each transistor. Through electrodes (not shown) are applied potentials corresponding to low level and high level to the deep n well 32 and the deep p well 33, respectively, so that, even if the potentials of the shallow p well 34 and the shallow n well 35, respectively, change, respective reverse bias states will always be maintained. In the present invention, since the respective forward biases are applied to the substrate electrodes BN1 and BN2 of the NMOS transistors MN1 and MN2, the potential difference between high level and low level, i.e., Vdd referred to above, must be 0.6V or less. The following is an explanation of the second embodiment of the present invention, referring to Figure 5. Figure 5 is an electric circuit diagram of MOS logic circuit LOGa in accordance with the second embodiment of the present invention. In this MOS logic circuit LOGa, members similar to and corresponding with those of the MOS logic circuit LOG will be given the same reference symbols, and explanation thereof will be omitted. In the MOS logic circuit LOGa, substrate electrodes BP1 and BP2 of PMOS transistors MP1a and MP2a, which make up a clamp circuit CLPa, are connected to the respective source electrodes of the PMOS transistors. Accordingly, the PMOS transistors MP1a and MP2a must be given high threshold voltages, but since there is no connection between the gate and the substrate, so that direct current will no longer flow from the source electrode through the pn junction, it can be made more difficult for the direct current to flow from the pulse power source  to the ground level, and thus power consumption can be reduced. The following is an explanation of the third embodiment of the present invention, referring to Figure 6. Figure 6 is an electric circuit diagram of MOS logic circuit LOGb according to the third embodiment of the present invention. In the MOS logic circuit LOGb, members similar to and corresponding with those of MOS logic circuit LOG will be given the same reference symbols, and explanation thereof will be omitted. In the MOS logic circuit LOGb, functional circuits FUN1b and FUN2b are provided with two NMOS transistors each, MN11 and MN12, and MN21 and MN22, respectively. In concrete terms, in the functional circuit FUN1b, the NMOS transistors MN11 and MN12 are connected in series with each other, but in the functional circuit FUN2b, the NMOS transistors MN21 and MN22 are connected in parallel with each other. The gate electrodes of the NMOS transistors MN11 and MN12 serve as input nodes HI11 and HI12, respectively, to which are applied inputs A and B, respectively. Through the output node HO1, an output value OUT is applied to the substrate electrodes BN11 and BN12 of the NMOS transistors MN11 and MN12 respectively. The gate electrodes of the NMOS transistors MN21 and MN22, on the other hand, serve as input nodes HI21 and HI22, respectively, to which are applied inputs A and B , respectively. Through the output node HO2, an output value OUT is applied to the substrate electrodes BN21 and BN22 of the NMOS transistors MN21 and MN22 respectively. In the above structure, when at least one of the inputs A and B is at low level (and, accordingly, at least one of the inputs A and B is at high level), the NMOS transistor MN21 or MN22 is turned on, and therefore the output OUT (the output node HO1) falls to low level. The low level of the output OUT is sent to the gate electrode of the PMOS transistor MP1, thus turning on the PMOS transistor MP1. As a result, the output OUT (the output node HO2) rises to high level. On the other hard, when both the input A and the input B are high level, both of the NMOS transistors MN11 and MN12 are turned on, and therefore the output OUT (the output node HO2) falls to low level. The low level of the output OUT is sent to the gate electrode of the PMOS transistor MP2, thus turning on the PMOS transistor MP2. As a result, the output OUT (the output node HO1) rises to high level. In this way, in the MOS logic circuit LOGb, AND logic A•B is furnished by the output OUT, and NAND logic (A•B) by the output OUT . If the output OUT is outputted by the output node HO1 and the output OUT by the output node HO2, the output OUT furnishes NAND logic. Further, if the input logic values are changed, inputting the input A to the input node HI21, the input B to the input node HI22, the input A to the input node HI11, and the input B to the input node HI12, the output OUT furnishes NOR logic, and the output OUT furnishes OR logic. As described above, the MOS logic circuit LOGb operates as an AND/NAND circuit. In the same way, depending on the structure of the functional circuits FUN1b and FUN2b, the desired logic can be realized. The MOS logic circuit in the present invention, made up, as explained above, of a clamp circuit and two functional circuits, each functional circuit having at least one NMOS transistor, is a MOS logic circuit called an ECRL circuit or a 2N-2P circuit, capable of low-power-consumption operation through adiabatic charging by use of a pulse power source, and is arranged so that the substrate electrode of each NMOS transistor is cross-connected to the output node of the other functional circuit. Therefore, during the HOLD operation, in which the pulse power source remains at high level while both inputs are at low level, the substrate of the NMOS transistor which is to output low level (which is to be turned on) is forward biased and becomes depletion mode, and maintains its on state. By this means, logic errors due to the influence of neighboring circuits can be prevented without increasing the number of NMOS transistors, i.e., without increasing circuit size. Further, because of the forward bias mentioned above, even if the RESET operation is performed while the output is at low level, the NMOS transistor in the corresponding functional circuit will be turned on without fail, the capacitive coupling shown in Figure 15 will not occur, and thus the consumption of extra power during recharging can be avoided. It is advantageous to connect the substrate electrode of each PMOS transistor in the clamp circuit to the gate electrode of the sane PMOS transistor. In this case, the PMOS transistors may be given a low threshold voltage, thus making low voltage operation possible. It is also advantageous to connect the substrate electrode of each PMOS transistor in the clamp circuit to the pulse power source. In this case, the threshold voltage of the PMOS transistors is raised, but it becomes difficult for the direct current to flow from the pulse power source to the constant-voltage power source, thus making possible a further decrease in power consumption. It is advantageous for the substrate to be of the SOI structure. In this case, each MOS transistor may be insulated and separated from the others, and it becomes possible to apply a forward bias to the substrate electrodes of the NMOS transistors, as discussed above. It is also advantageous for each MOS transistor to be electrically separated from the others by a double dispersion area and by insulator. In this case, each MOS transistor may be insulated and separated from the others, and it becomes possible to apply a forward bias to the substrate electrodes of the NMOS transistors, as discussed above. The concrete embodiments and examples of implementation discussed in the foregoing detailed explanations of the present invention serve solely to illustrate the technical details of the present invention, which should not be narrowly interpreted within the limits of such concrete examples, but rather may be applied in many variations without departing from the scope of the patent claims set forth below.

Claims: A MOS logic circuit comprising: a clamp circuit having a pair of PMOS transistors (BP1, BP2), each having a gate electrode, a drain electrode, and a source electrode, the gate electrode of each of the PMOS transistors being cross-connected to the drain electrode of the PMOS transistor which is the other member of the pair, and the source electrode of each of the PMOS transistors being connected to a common pulse power source (11); and two functional circuits, each having at least one NMOS transistor (MN1, MN2), a gate electrode of each of the NMOS transistors serving as an input node, one terminal of each said NMOS transistor being connected to a common constant-voltage power source (12), and the other terminal of each said NMOS transistor being connected to the drain electrode of its corresponding PMOS transistor (BP1, BP2) and serving as an output node; each substrate electrode of the NMOS transistors (MN1, MN2) which constitute the respective functional circuits being cross-connected to the output node of the other functional circuit. The MOS logic circuit according to Claim 1, wherein a substrate electrode of each of the PMOS transistors (BP1, BP2) in the clamp circuit is connected to the gate electrode of each said PMOS transistor (BP1, BP2). The MOS logic circuit according to Claim 1, wherein a substrate electrode of each of the PMOS transistors (BP1, BP2) is connected to the pulse power source (11). The MOS logic circuit according to Claim 1, wherein the substrate has an SOI structure capable of insulating and separating each of the MOS transistors (BP1, BP2, MN1, MN2) from the others. The MOS logic circuit according to Claim 1, wherein, on the substrate, each of the MOS transistors (BP1, BP2, MN1, MN2) is electrically isolated from the others by a double dispersion area and by insulator. The MOS logic circuit according to Claim 2, wherein each of the functional circuits is made up of a single NMOS transistor (MN1, MN2). The MOS logic circuit according to Claim 3, wherein each of the functional circuits is made up of a single NMOS transistor (MN1, MN2). The MOS logic circuit according to Claim 2, wherein, in one of the functional circuits, two NMOS transistors are connected in series (MN11, MN12), and in the other functional circuit, two NMOS transistors (MN21, MN22) are connected in parallel. The MOS logic circuit according to Claim 6, wherein the constant-voltage power source (12) outputs ground level. The MOS logic circuit of adiabatic charging type, comprising a clamp circuit and two functional circuits, each of the functional circuits including at least one NMOS transistor (MN1, MN2), wherein: the functional circuits are arranged so that during a HOLD operation the NMOS transistor which is to be turned on is given a forward bias. The MOS logic circuit according to Claim 10, wherein the clamp circuit includes a pair of PMOS transistors (BP1,BP2), a substrate electrode of each of the PMOS transistors being connected to a gate electrode of each said PMOS transistor. The MOS logic circuit according to Claim 11, wherein the substrate electrode of each of the PMOS transistors (BP1, BP2) is connected to the source electrode of each said PMOS transistor. The MOS logic circuit according to Claim 11, wherein the substrate has an SOI structure capable of insulating and separating each of the MOS transistors (BP1, BP2, MN1, MN2) from the others. The MOS logic circuit according to Claim 11, wherein, on the substrate, each of the MOS transistors (BP1, BP2, MN1, MN2) is electrically isolated from the others by a double dispersion area and by insulator. The MOS logic circuit according to Claim 10, wherein each of the functional circuits is made up of a single NMOS transistor (MN1, MN2). The MOS logic circuit according to Claim 10, wherein, in one of the functional circuits, two NMOS (MN11, MN12) transistors are connected in series, and in the other functional circuit, two NMOS transistors (MN21, MN22) are connected in parallel. The MOS logic circuit according to Claim 2, wherein the threshold voltage of the NMOS (MN1, MN2) transistor is adjusted so that the NMOS transistor shows enhanced-mode transistor characteristics when low level is applied to the substrate electrode, and shows depletion-mode transistor characteristics when high level is applied to the substrate electrode. The MOS logic circuit according to Claim 10, wherein the threshold voltage of the NMOS (MN1, MN2) transistor is adjusted so that the NMOS transistor shows enhanced-mode transistor characteristics when low level is applied to the substrate electrode, and shows depletion-mode transistor characteristics when high level is applied to the substrate electrode.

Inventors: KIOI KAZUMASA, KIOI, KAZUMASA
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1997
Main classification: H03K19
IPC codes: H03K19, H01L27