Cache flush apparatus and computer system having the same

Abstract: Addresses of all of dirty blocks of a cache memory (20) are, by an update address registering section (33), stored in one of plural regions of an update address memory (32). When a certain cache block is brought to a dirty state and then suspended from the dirty state, the update address removing section (34) removes the address from the region. When cache flush is performed, a flush executing section (35) sequentially fetches the addresses of the dirty blocks from each region to issue, to the system bus (40), a command for writing-back data indicated by the address into the main memory (51) so that the contents of all of the a dirty block are written-back into the main memory (51). Therefore, the cache flush apparatus according to the present invention is able to shorten time required to perform the cache flush procedure and to improve the performance of a computer system having the cache flush apparatus.

Description: The present invention relates to a cache flush apparatus for a cache memory having a snoop mechanism for maintaining data coherency and a fault tolerant computer system having the cache flush apparatus. In general, a modern high-speed processor has a cache memory for temporarily holding data required by the processor in order to reduce the effective memory access latency. A cache memory holds data and the memory address at which the data is read out in a fixed size data storage unit called a cache block. In a computer (more specifically a multi-processor computer) having a plurality of processors each of which has its own cache memory, a snoop mechanism is usually used to maintain data coherency among the cache memories. A snoop mechanism monitors the system bus to detect bus commands and if a bus command which requires some action of the cache memory is detected, the snoop mechanism does the required action such as replying the bus command with data held in one of its cache blocks, discarding data in one of its cache blocks and the like. The cache memory is classified into copy-back type and write-through type. While a write-through type cache memory writes back data into the main memory immediately when it is updated within the cache memory, a copy-back type cache memory postpones the write-back of data until it becomes necessary. Therefore, for a copy-back type cache memory, a cache block may hold updated data which has not been written back into the main memory yet. Such a cache block is called a dirty block and the state of such a cache block is called dirty. A copy-back type cache memory requires a cache flush operation which writes back all the data updated solely within the cache memory into the main memory. For example, data transfer between an input/output device without memory coherency mechanism and the main memory requires a cache flush before the data transfer in order to assure that the main memory holds valid data. From now on, a "cache memory" means a copy-back type cache memory. A cache flush is also necessary for a main memory based checkpoint/rollback type fault tolerant computer. Such a fault tolerant computer periodically creates a checkpoint within its main memory. When the computer detects some faults during the normal data processing, the computer rolls back its internal state to the most recent checkpoint and then restarts the normal data processing. Since a checkpoint image created within the main memory should contain sufficient information to restart the normal data processing, it is necessary to perform a cache flush as a part of checkpoint creation. A cache flush is usually performed by using machine instructions provided by the processor. Intel Pentium processor and its successors, for example, provide a "wbinvd" (writeback & invalidate) instruction. The instruction writes back data of all the dirty blocks into the main memory and sets the state of every cache block invalid. Therefore, when a cache flush has been performed by executing the "wbinvd" instruction as a part of checkpoint creation, cache misses occur very frequently during the normal data processing which follows the checkpoint creation. MIPS R4000 processor, for example, provides a "secondary cache hit writeback" instruction. The operand of the instruction, different from the case of the "wbinvd" instruction, is a single cache block. The following is a sample program of a cache flush operation. With the foregoing program, "cache 0x1b, 0($4)" is the "secondary cache hit writeback" instruction. The instruction checks the state of the cache block of a secondary cache memory designated by the contents of the fourth register ($4). If the state is dirty, the data of the cache block is written-back into the main memory and the state of the cache block turns "clean-exclusive" or "shared". The loop should be repeated as many as the number of the cache blocks of the secondary cache memory even if the number of dirty blocks is small. It should be mentioned that the execution time of a cache instruction is usually much longer than that of an ordinary instruction such as an arithmetic instruction. SPARC V9 processor does not provide any instruction for a cache flush. If a cache flush is necessary, a load instruction should be used so that the data within a dirty block is replaced by the data newly loaded into the cache block. Therefore, the inefficiency of a cache flush is apparently more critical than the case of Intel Pentium processor. To accelerate a cache flush operation has been a concern for designers of a main memory based check-point/rollback type fault-tolerant computer. Japanese patent disclosure (KOKAI) No. 5-6308, "Cache controller, fault tolerant computer and data transfer method". Mitsubishi Denki Co. Ltd., corresponding to DE 4136792 A1 proposed a cache controller with additional memory for storing the memory address at which a piece of data is updated. In a cache flush operation, while a conventional cache controller checks the state of every cache block and, if it is dirty, writes back the data held in the cache block, the proposed cache controller can use the addresses stored in the additional memory densely. However, this method has a critical disadvantage that it requires a major modification of the present cache controller design, which is too costly. In other words, this document discloses a cache flush control system comprising cache controllers each provided in modules. However, this document does not comprise a cache flush apparatus which is independent from the cache memory and connected to the cache memory through the system bus. Therefore, it does not teach a detection of data update in the cache memory by monitoring the system bus. This document can be interpreted as a disclosure of a cache flush apparatus comprising update address storage means, namly a plurality of stacks at each CPU cache modules 1 to N, for storing the address of data held in a dirty block of the corresponding cache memory, an update address registering means to detect update data within the cache memory and storing the address of this data in the update address storing means, update address removing means for detecting a write-back of data from a dirty block and removing the update address from the update address storage means, and a flush executing means for writing-back into a main memory the data of all dirty blocks based on the addresses held in the update address storage means. EP 0 750 262 A2, published on December 27, 1996 and which forms part of the state of the art under Art. 54(3) EPC, discloses an external tag storage device which stores an address of updated data and a tag indicating that the data is updated in the caches. In view of the foregoing, the primary object of the present invention is to provide a cache flush apparatus applicable to a variety of commercial high speed microprocessors having cache memories. The cache flush apparatus, attached to the system bus, maintains the memory addresses held in dirty blocks within its own storage during the normal data processing. When a cache flush is required, the cache flush apparatus reads the memory addresses from the storage efficiently and issues bus commands each of which requires to write back data held in one of the dirty blocks. As a result, a dirty block becomes "shared" and it still holds the same data. For a non-dirty cache block, it remains unchanged. According to the present invention, there is provided a cache flush apparatus for use in a computer according to claim 1, and a computer system according to claim 4. The dependent claims are related to further advantageous aspects of the invention. A main memory based checkpoint/rollback type fault tolerant computer periodically creates a checkpoint in its main memory. The flush executing means of the cache flush apparatus accelerates a cache flush and advantageously the state of the cache blocks remains valid. Therefore a main memory based checkpoint/rollback type fault tolerant computer with the cache flush apparatus thereof increases the system performance considerably. In addition to the above computer system for periodically acquiring checkpoints, the cache flush apparatus according to the present invention can be applied to a duplex computer system in which the primary computer alternately continues normal data processing and sends its checkpoint image to the secondary computer and when a fault occurs within the primary computer, the secondary computers takes over the normal data processing. The cache flush means of the cache flush apparatus accelerates the checkpoint creation of the primary computer. The invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram showing the configuration of a computer system according to the first embodiment of the present invention; FIGS. 2A and 2B are conceptual views showing the structure of a region Ai of the update address memory of the first embodiment; FIG. 3 is an operation diagram of the update address registering section of the first embodiment; FIG. 4 is an operation diagram of the update address removing section of the first embodiment; FIG. 5 is an operation diagram of the flush executing section of the first embodiment; FIG. 6 is an operation diagram of the update address registering section of the second embodiment; FIG. 7 is an operation diagram of the update address removing section of the second embodiment; FIG. 8 shows a table representing the operation which is performed when the processor of the first embodiment continuously writes data D0, D1 and D2 at addresses 0, B × M and 2B × M; FIG. 9 is a conceptual view showing the structure of the region Ai according to a modification of the first embodiment; FIG. 10 is an operation diagram of the cache flush device which is performed when the update address registering section of the modification detects a data update command; FIG. 11 is an operation diagram of the cache flush device which is performed when the update address removing section of the modification detects a command for writing-back the dirty block into the main memory; FIG. 12 is an operation diagram of the flush executing section of the modification; FIG. 13 shows a table representing the operation which is performed when the processor of the modification continuously writes data D0, D1 and D2 to addresses 0, B × M and 2B × M; FIG. 14 is a diagram showing the structure of a computer system according to another modification of the first embodiment; FIG. 15 is an operation diagram of the other modification shown in FIG. 14; FIG. 16 is a diagram showing the structure of a computer system according to a second embodiment (not covered by the invention); FIG. 17 is a conceptual view showing the structure of the region of the update address memory of the second embodiment (not covered by the invention); FIG. 18 is an operation diagrams of the update address registering section and an entry reclaiming section when the update address registering section detects a command indicating data update in the cache memory of the second embodiment (not covered by the invention); FIG. 19 is an operation diagram of the flush execution section of the second embodiment (not covered by the invention); FIG. 20 is a table showing the operation which is performed when the processor of the second embodiment continuously writes data D0, D1 and D2 to addresses 0, B × M and 2B × M (the second embodiment is not covered by the invention); FIG. 21 is a diagram showing the structure of a computer system according to a third embodiment; FIG. 22 is an operation diagram of the update address removing section of the third embodiment for seeking the entry in which the same address as the write-back address is stored, for a predetermined time; FIG. 23 is a diagram showing the structure of a computer system according to a fourth embodiment; FIG. 24 is a conceptual view showing the structure of the region of the update address memory of the fourth embodiment; FIG. 25 is an operation diagrams of the update address registering section and the entry reclaiming section of the fourth embodiment when the update address registering section detects a command indicating data update in the cache memory; FIG. 26 is an operation diagram of the update address removing section of the fourth embodiment; FIG. 27 is an operation diagram of the flush execution section of the fourth embodiment; FIG. 28 is a diagram showing the structure of a fault tolerant computer according to a fifth embodiment of the present invention; FIG. 29 is a diagram showing shift of three steps as the time elapses in the computer of the fifth embodiment; FIG. 30 is a diagram showing the structure of a fault tolerant computer according to a sixth embodiment of the present invention; and FIG. 31 is a diagram showing states of changes of a first computer 100a and a second computer 100b of the computer of the sixth embodiment as the time elapses. A preferred embodiment of a computer system having a cache flush apparatus according to the present invention will now be described with reference to the accompanying drawings. (First Embodiment) FIG. 1 is a block diagram showing the configuration of a computer system according to the first embodiment of the present invention. Each processor 10 has its own copy-back type cache memory 20 with a cache coherency mechanism and is connected to a system bus 40. In a case where the configuration of the cache memory 20 is two level (namely comprises primary and secondary cache memories) or more, the cache memory according to this embodiment means the cache memory nearest to the system bus 40. In case where a cache memory comprises an instruction cache memory and a data cache memory, the cache memory according to this embodiment means the data cache memory. The system bus 40 according to this embodiment has 32 bit address. A cache flush device 30 and a memory controller 50 for a main memory 51, are connected to the system bus 40. The cache flush device 30 includes a system bus interface 31, an update address memory 32 (consisting of regions A 0 to A n-1 ), an update address registering section 33, an update address removing section 34 and a flush executing section 35. The update address registering section 33 and the update address removing section 34 can be implemented as a single hardware module. The system bus interface 31 serves as an interface with the system bus 40. The update address memory 32 consists of n regions A 0 to A n-1 for storing addresses of data held in the dirty blocks of the cache memories 20. In this embodiment, if and only if a dirty block holds data of a certain address, the address is stored in a certain region of the update address memory 32. From now on, we call such a memory address stored in the update address memory 32 an update address. The structure of a region of the update address memory 32 will now be described. As shown in FIG. 2A and FIG. 2B, a region Ai has one or more entries each of which can store an update address. To indicate whether or not an entry has an update address, the either of the following methods is employed. An exceptional value (for example, 0×FFFFFFFF) is used to indicate the entry does not have an update address. (see FIG. 2A). A flag is attached to each entry and when an entry holds no update address, the corresponding flag is set on. (see FIG. 2B). The method of determining how many regions the update address memory should have and the method of mapping each region to the memory address space will be described later. FIG. 3 shows the operation diagram of the update address registering section 33. When a processor 10 updates a piece of data within a cache memory 20, the cache.memory 20 issues a bus command on the system bus 40. The system bus interface 31 detects the bus command and transfers it to the update address registering section 33 (step A1). The update address registering section 33 selects a region A i from the regions A 0 to A n-1 according to the memory address MU at which the data is updated and the processor identifier (ID) which has updated the data (step A2). The update address registering section 33 finds out an empty entry of the region A i , and stores the memory address MU as an update address in the empty entry (step A3). The memory address MU is included in the bus command. The processor identifier can be acquired by either of the following two methods depending on the specification of the system bus 40; 1) by extracting the identifier from the bus command; 2) by monitoring some signal lines of the system bus 40 used for bus arbitration. FIG. 4 shows the operation diagram of the update address removing section 34. When a write back of data from a dirty block occurs, the cache memory 20 issues a bus command on the system bus 40. The system bus interface 31 detects the bus command and transfers it to the update address removing section 34 (step B1). The update address removing section 34 selects a region from the regions A 0 to A n-1 according to the memory address MW at which the data has been written back and the processor identifier from which the data has been written back (step B2). Then, the update address removing section 34 finds out the entry having the update address equal to the memory address MW and removes the update address from the entry (step B3). The update address registering section 33 and the update address removing section 34 must select a region in the same way. The reason why the update address memory 32 consists of n regions and the both sections 33 and 34 select a region in the same way is that the operation of the update address removing section 34 can be accelerated by reducing the number of entries which must be examined. The flush executing section 35, receiving a request from one of the processors 10, reads and removes every update address from the update address memory 32 and issuing a bus command which causes a write-back of data from the dirty block having the update address until all the update addresses are removed. FIG. 5 shows the operation diagram of the flush executing section 35. In Fig. 5, the flush executing section 35 initializes the variable i to zero (step C1). If the region Ai (the region indicated by i ) contains no update address (NO of step C2), the flush executing section 35 increments the variable i by one (step C4). Otherwise (YES of step C2), the flush executing section 35 reads and removes every update address from the region Ai and issues a bus command which causes a write-back of data from the dirty block having the update address (step C3). Then, the operation returns to step C2. The flush executing section 35 terminates the operation when the variable i becomes equal to n (Yes of step C5). In the above description, an update address is removed by the flush executing section 35. However, it is also possible for the update removing section 34 to remove the update address by detecting the bus command issued by the flush executing section 35. Then, how the cache flush device 30 according to the first embodiment is used in the computer system will now be described. (Initialization) The processors 10, prior to activating the cache flush device 30, initialize the update address memory 30 and the cache memories so that they are in a consistent state. More specifically, one of the processors 10 clears all the entries of the update address memory 30 and every processor 10 invalidates all the cache blocks of its own cache memory by executing its proper machine instructions. (During the Normal Operation) After the initialization, the update address registering section 33 and the update address removing section 34 begin to perform the operations described above so that the update address memory 32 stores the addresses of data held in the dirty blocks of the cache memories 20. On the contrary, for every update address stored in the update address memory 32, there exists a corresponding dirty block. The reason will now be described. Let us assume that the state of the cache memories and the state of the update address memory are consistent and the processor 10-1 is going to update the data of memory address MU. After the update of data, it will be explained that the state of the cache memories and the state of the update address memory will remain consistent after the data update. (1) In a case where the cache memory 20-1 has no data of memory address MU; The cache memory 20-1 issues a bus command which requests to send the data of memory address MU and to invalidate the cache blocks of the other cache memories 20-2, 20-3 which hold the data of memory address MU.When the data is supplied to the cache memory 20-1, the cache block selected by the cache controller (not shown) according to the memory address MU stores the data and the cache block is changed to a dirty block.The update address registering section 33 receives the foregoing bus command through the system bus interface 31 and selects one of the regions A 0 to A n-1 according to the memory address MU and the processor identifier 10-1 and finds out an empty entry and stores the memory address MU in the entry. (2) In a case where the cache memory 20-1 has the data of address MU in shared state; The cache memory 20-1 issues a bus command which requests to invalidate the cache blocks of the other cache memories 20-2, 20-3 which hold the data of memory address MU.When an acknowledgment for the foregoing bus command is replied to the cache memory 20-1, the cache block which holds the data is changed to a dirty block.The update address registering section 33 receives the foregoing bus command through the system bus interface 31 and selects one of the regions A 0 to A n-1 according to the memory address MU and the processor identifier 10-1 and finds out an empty entry and stores the memory address MU in the entry. (3) In a case where the cache memory 20 has data to be updated in dirty state; The cache memory 20-1 issues no bus command and thus the cache flush device 30 does not perform any operation. However, no problem arises because the memory address MU has been already stored in one of the regions A 0 to A n-1 . In the above description, it is assumed that a cache block may have three states "invalid", "shared", and "dirty". However, since there are some cache memories which have four states "invalid", "shared", "dirty", and "clean exclusive", it is now described how to apply the cache flush device to such a cache memory. "Clean exclusive" means that the cache block has a valid and unchanged data exclusively (not shared by any one of the other cache memories). When the processor 20-1 is going to update the data of a "clean exclusive" cache block, the cache block is changed to a dirty block without issuing any bus command. Therefore, the cache flush device of the present invention would fail in detecting the update of data. So, it is necessary to prevent a cache block from becoming "clean exclusive". For this purpose, when a processor is going to read data and a cache miss occurs, the bus interface 31 should make a shared reply. As a result, the state of the cache block becomes "shared" instead of "clean exclusive". When the data of a dirty block is written-back to memory address MW of the main memory 51, the update address removing section 34 detects the bus command and selects one of the regions A 0 to A n-1 in the same way as in the update address registering section 33 so that the region which contains the memory address MW is selected. Then the update address removing section 34 finds the entry whose update address is equal to the memory address MW. When the flush executing section 35 completes the cache flush procedure, there is no dirty cache block in the cache memories 20 and there is no update address in the update address memory 32, the same state as the initialization is completed. Though there are various possible ways of configuring the regions of the update address memory 32, it is preferable to determine the configuration according to the major aspects of the cache memory configuration, e.g. the number of processors, the number of cache blocks, and direct map or set associative. (1. Preferable configuration for a direct-map cache memory without a write buffer) The size of a cache block is denoted to be B bytes and the number of the cache blocks is denoted to be M. In this case, data at the memory address A is stored in the ((A/B) mod M) th cache block. It is preferable to establish one to one correspondence between a cache block and a region. So the number of the regions should be M×P where P is the number of the processors and each region should have one entry. The update address registering section 33 and the update address removing section 34 should select the ((A/B) mod M)×PID, where A is the memory address contained in the bus command and PID is the processor identifier. It should be noted that if the number of the processor is one, the above formula will not need to contain the processor identifier. The update address registering section 33 does not have to find out an empty entry because the selected region has only one entry which is certain to be empty. The update address removing section 34 can remove the update address without checking whether the update address within the entry of the selected region is equal to the memory address A. (2. Preferable configuration for a direct-map cache memory with a write buffer) The write buffer of a recent high performance processor requires a more complicated cache flush device of the present invention. When a processor with a write buffer is going to update data of memory address A and the corresponding cache block C happens to hold data of memory address B in dirty state, a data replacement occurs in the following sequence; (1) A write-line bus command for data of memory address B is created and temporally stored in the write buffer. (2) A read-line-and-invalidate bus command for data of memory address A is issued on the system bus 40. (3) The data of memory address A is supplied to the cache block C as a reply for the bus command. (4) The write-line bus command suspended in the write-buffer is issued on the system bus 40 and the data is written back to the main memory. Therefore, between step (2) and step (4), the cache block C appears to hold both data of memory address A and data of memory address B. Although a naive possible configuration of a cache flush device is to increase the number of the entries of each region, the following problems would arise: (1) The quantity of the hardware is enlarged. (2) The performance of the update address removing section is slower because the number of the entries to be searched increases. For a direct map cache memory with a write buffer, there are two efficient ways of configuring a cache flush device. (Configuration 2-A) The configuration of the update address memory 32 is the same as in the preferable configuration for a direct-map cache memory without a write buffer. The operation of the update address registering section 33, as is depicted in FIG. 6 is the same. However it should be noted that when memory address MU is going to be stored in the entry of the selected region (D3), it sometimes happens that the entry already has a valid updated address because of the write buffer. Even if it is the case, the update address registering section 33 simply overwrites the memory address MU into the entry. The operation of the update address removing section 34, as is depicted in Fig. 7, is slightly different at the point where it removes the update address from the entry only when the update address of the entry is equal to the memory address MW (E3, E4, E5). Referring to FIG. 8, an example of the operation of the cache flush device and the cache memory is explained. In this example, there is only one processor 10 which sequentially writes data D0 at memory address 0, data D1 at memory address B×M, and data D2 at memory address 2B×M in this order. Here symbol B denotes the size of the cache block and M denotes the number of the cache blocks. The initial state of the 0 th cache block is assumed to be invalid and therefore the entry of the region A 0 does not have a valid update address. (1) When the processor 10 is going to write D0 at memory address 0, the 0 th cache block does not hold the data of memory address 0. So a read-line-with-invalidate bus command for memory address 0 is issued on the system bus 40. (2) When data of memory address 0 is supplied as a response of the above bus command, the update address registering section 33 stores memory address 0 as an update address in the entry of the region A 0 . The processor 10 writes D0 into the 0 th cache block. (3) When the processor 10 is going to write D1 at memory address B×M, the 0 th cache block holds data D0 in dirty state. A write-line bus command for data D0 is created and suspended in the write buffer. A read-line-with-invalidate bus command for memory address B×M is issued on the system bus 40. (4) The update address registering section 33 overwrites memory address B×M as an update address in the entry of the region A 0 . When the data of memory address B×M is supplied, the processor 10 writes data D1 into the 0 th cache block. (5) Before issuing the write-line bus command for memory address 0, the processor 10 is going to write data D2 at memory address 2B×M. Another write-line bus command for data D2 is created and suspended in the write buffer. A read-line-with-invalidate bus command for memory address 2B×M is issued on the system bus 40. As a result, two write-line bus commands are suspended in the write buffer. (6) The update address registering section 33 overwrites memory address 2B×M as an update address in the entry of the region A 0 . When the data of memory address 2B×M is supplied, the processor 10 writes data D2 in the 0 th cache block. (7) The write-line command for memory address 0 suspended within the write buffer is now issued to the system bus 40. Since the entry of the region A 0 has 2B×M which is different from memory address 0, the update address removing section 34 does not perform any operation. (8) The write request command for memory address B×M suspended within the write buffer is now issued to the system bus 40. Since the entry of the region A 0 has 2B×M which is different from memory address B×M, the update address removing section 34 does not perform any operation. (Configuration 2-B) Each region should have one entry and a counter for keeping the number of update addresses corresponding to the region. The entry and the counter are used as follows. (1) Counter value zero means that no update address stored in the region exists. (2) When the update address registering section 33 detects update of data corresponding to a region, the update address registering section 33 writes the update address into the entry of the region and increments the counter by one. (3) When the update address removing section 34 detects write-back of data from a dirty block, the update address removing section 34 decrements the counter of the corresponding region by one. (4) When the counter of each region has a non-zero value, the flush executing section 35 issues a command for requesting write-back of data from the dirty block specified by the update address stored in the entry of the region. A region Ai, as is depicted in FIG. 9, has a 4-bit counter as well as a 32-bit entry. The operation of the update address registering section 33 when a data update command is detected in FIG. 10. FIG. 11 shows the operation of the update address removing section 34 when a data write-back command is detected. FIG. 12 shows the operation of the flush executing section 35. Referring to FIG. 13, an example of the operation of the cache flush device and the cache memory is explained. In this example, there is only one processor 10 which sequentially writes data D0 at memory address 0, data D1 at memory address B×M, and data D2 at memory address 2B×M in this order. The initial state of the 0 th cache block is assumed to be invalid and therefore the entry of the region A 0 does not have a valid update address. (1) When the processor 10 is going to write D0 at memory address 0, the 0 th cache block does not hold the data of memory address 0. So a read-line-with-invalidate bus command for memory address 0 is issued on the system bus 40. (2) When data of memory address 0 is supplied as a response of the above bus command, the update address registering section 33 stores memory address 0 as an update address in the entry of the region A 0 and increments the counter to one. The processor 10 writes D0 into the 0 th cache block. (3) When the processor 10 is going to write D1 at memory address B×M, the 0 th cache block holds data D0 in dirty state. A write-line bus command for data D0 is created and suspended in the write buffer. A read-line-with-invalidate bus command for memory address B×M is issued on the system bus 40. (4) The update address registering section 33 overwrites memory address B×M as an update address in the entry of the region A 0 and increments the counter to two. When the data of memory address B×M is supplied, the processor 10 writes data D1 into the 0 th cache block. (5) Before issuing the write-line bus command for memory address 0, the processor 10 is going to write data D2 at memory address 2B×M. Another write-line bus command for data D2 is created and suspended in the write buffer. A read-line-with-invalidate bus command for memory address 2B×M is issued on the system bus 40. As a result, two write-line bus commands are suspended in the write buffer. (6) The update address registering section 33 overwrites memory address 2B×M as an update address in the entry of the region A 0 and increments the counter to three. When the data of memory address 2B×M is supplied, the processor 10 writes data D2 in the 0 th cache block. (7) The write-line command for memory address 0 suspended within the write buffer is now issued to the system bus 40. The update address removing section 34 decrements the counter of the region A 0 to two. (8) The write-line command for memory address B×M suspended within the write buffer is now issued to the system bus 40. The update address removing section 34 decrements the counter of the region A 0 to one. (3. Preferable configuration for a direct-map cache memory without a write buffer and more than one processors) The number of the processors is denoted by P. The cache block size is denoted by B (bytes) and the number of the cache blocks is denoted by M. In this case, either of two examples below may be employed. (Configuration 3-A) The number of the regions is made to be P×M, and each region has one entry. There is a one-to-one correspondence between a cache block of a processor and a region. The update address registering section 33 and the update address removing section 34 are required to select the region according to the processor identifier and the memory address. Since each part of the cache flush device is almost the same as that of the preferable configuration, the detailed explanation is omitted. (Configuration 3-B) The number of the regions is made to be M and each region has P entries. A region Ai is made to correspond to the i-th cache block of each processor 10. When a data update or a data write-back command is detected, a region is selected according to the memory address but not according to the processor identifier. Therefore, the processor identifier is not required to select a region while it is required in configuration 3-A. Thus, this configuration is effective in a case where it is difficult to know the processor identifier because of the system bus specification. However, there arises a problem in that the configuration 3-B cannot be adapted to a processors with a write buffer. For such a case, the configuration 3-A or second to fourth embodiments to be described later should be employed. (4. Preferable configuration for a N-way set-associative cache memory without a write buffer) In this case N cache blocks form a group, and data at address a is stored in a cache block in the ((a/B) mod (M/N))th group. Here, B denotes the cache block size (in bytes) and M denotes the number of the cache blocks. (Configuration 4-A) The number of the regions is made to be M/N, and each region is made to consist of N entries. Data at address a is stored in the ((a/B) mod (M/N)th region. However, this method has a problem in that it can not be applied to a processor with a write buffer. For a processor having both a set-associative cache memory and a write buffer, the second to fourth embodiments should be employed. (Configuration 4-A) In a case where the set-associative cache memory 20, when one of its cache blocks stores a data, asserts some control signal lines to indicate which way of the cache blocks stores the data, the set-associative cache memory can be treated as a direct-map cache block. In this case, configurations 2-A and 2-B are effective for a processor with a write buffer. When the processor 10 requires the cache flush device 30 to perform the cache flush procedure, the flush executing section 35 issues bus commands each of which causes a write-back of data from a dirty block. Now, the bus command which can be used to write back data from a dirty block is explained. In many systems, a Read-Line command can be used. A Read-Line command, in such systems, requests the newest data of the specified address. When a cache memory holds the data in the dirty state, the cache memory makes a reply with the data. Then the main memory controller 50 observes the reply and stores the data into the specified portion of the main memory. In some other systems, when a Read-Line command is issued and a cache memory hold the data in the dirty state, the cache memory replies a Retry command (requiring to issue a Read-Line command again later). Then, the cache memory issues a Write-Line command to the system bus to write-back the data from the dirty block into the main memory. When a Read-Line command is issued later, not the cache memory but the main memory replies. However, there are another type of computer systems where a dirty block remains in the dirty state even when a Read-Line command has been issued for the dirty block. There are two effective ways for such a system. (Configuration 5-A) One way is that both Read-Line-with-Invalidate command and Write-Line command are used. The cache flush device 30, when performing the cache flush, issues a Read-Line-with-Invalidate command for a dirty block and then issues and for making invalid the contents in the dirty block is issued, and then Write-Line command is issued so that data, which is read previously, is written-back into the main memory 51. The foregoing method requires the cache flush device 30 a full functionality of a cache memory 20 for storing the dirty block in order to maintain the data coherency. (Configuration 5-B) The other way is that the processor 10 reads the update addresses stored in the update address memory 32 and executes suitable instructions for writing-back of data according to the read addresses. For this purpose, an update address reading section 37 provides to the processor 10 a function for sequentially transferring all of the update addresses stored in the update address memory 32. The update address reading section 37 provides a new update address each time the update address is read by the processor 10. If plurality of update addresses can be read in parallel by the processor, it leads to speed up the procedure. The processor 10 uses the address read to write-back the contents of the associated dirty block into the main memory. At this time, the processor 10 uses a cache instruction or reads, from the main memory, data at some other address which falls on the associated dirty block so that replacement of data occurs. By repeating this operation until no update address remains, the data of all dirty blocks are written-back into the main memory. Configuration 5-B has an advantage that the hardware is simple since the cache flush device 30 does not have to manage the data coherency. Further, in comparison to the conventional method in which the processor 10 executes all of the processes by a software, the dirty block can efficiently be detected and thus the cache flush process can be performed more quickly. The cache flush operation under configuration 5-B is shown in FIG. 15. At step Ha1, a parameter i for indicating the region is initialized as 0. At step Ha2, it is examined whether an update address is stored in the region Ai. If YES at step Ha2, an update address stored in the region Ai is fetched.at step Ha3 and the data of the associated update address is written back at step Ha4 and then the flow returns to the step Ha2. If NO at step Ha2, the parameter i is incremented by one at step Ha5 and it is examined at step Ha6 whether the parameter i becomes equal to n , the number of the regions. If NO at step Ha6, the flow returns to the step Ha2. If YES at step Ha6, the operation is completed. Other embodiments will now be described. In the description below, portions corresponding to those of the first embodiment are given the same reference numerals and description of the corresponding portions is omitted. Comparing the required time of a cache flush procedure performed by the cache flush device 30 according to this embodiment and that of a conventional cache flush procedure, they do not differ significantly in a case where the dirty block ratio (the ratio of the number of dirty blocks and the number of the whole cache blocks) is high. It is because writing-back data from dirty blocks occupies a dominant portion of the processing time. On the other hand, when the dirty block ratio is low (for example 10%), the former becomes much shorter while the latter is not reduced, because the search of dirty blocks occupies a dominant part. The embodiment has another advantage that at the end of the cache flush procedure, the cache blocks which were dirty at the beginning of the cache flush procedure remain to have the valid data. The embodiment has yet another advantage that the cache flush procedure and the normal data processing by the processors 10 can be done in parallel, which will be described in fifth and sixth embodiments. (Second Embodiment; not covered by the claimed invention) A second alternative embodiment will now be described. FIG. 16 shows the structure of a computer system according to the second alternative embodiment. The structure of the computer, to which the cache flush device 30 is applied, is the same as that according to the first embodiment. The cache flush device 30 comprises the system bus interface 31, update address memory 32 (regions A 0 to A n-1 ), update address registering section 33, flush executing section 35 and an entry reclaiming section 36. The update address memory 32 is composed of n regions (regions A 0 to A n-1 ) for storing addresses of all of the dirty blocks. In this alternative embodiment, the addresses of all the dirty blocks are stored in the update address memory 32. However, the update address memory 32 may also hold addresses the associated cache block of which is not dirty. The reason for this is that the update address removing section 34 of the first embodiment is omitted from the configuration of this embodiment. This is the main difference from the first embodiment. As mentioned above this embodiment is not covered by the claimed invention but it is useful for the understanding of embodiments 3 and 4. The structure of the region Ai will now be described. In order to indicate whether the value stored in each entry of the region Ai is valid, the method described in the first embodiment may be employed. However, it is more preferable to employ the following method. That is, a plurality of entries forming a region is used as a cyclic buffer. A reading pointer (R pointer) and a writing pointer (W pointer) are provided. Then, the update addresses are arranged to be stored in the entries between the R pointer and the W pointer except the entry designated by the W pointer. When the W pointer and the R pointer coincide with each other, it is ambiguous whether all of the entries are empty or all of the entries are filled with update addresses. In order to identify the above cases, a region Ai is equipped with a fullness flag, a one bit flag. This method is advantageous to improve the performance of the update address registering section 33 and that of the flush executing section 35. FIG. 17 is a conceptual view showing the structure of a region according to this embodiment. The R pointer designates the update address which was registered least recently. The W pointer designates the position, at which a new update address must be registered. The fullness flag is ON only when every entry holds a valid update address. The update address registering section 33 is the same as that of the first embodiment. When the update address registering section 33 is going to write an update address to a certain region and detects there is no empty entry belonging to the region, the entry reclaiming section 36 selects an arbitrary entry in the address registering section 33 and issues a bus command for writing-back the contents of the dirty block of the selected entry. Then, the selected entry is used to store the new update address. Note that it is most effective that the entry reclaiming section 36 reclaims an entry in the above-mentioned way. However, the reclaiming operation may be performed somewhat earlier when one or a few empty entries exist. FIG. 18 is an operation diagram of the update address registering section 33 and the entry reclaiming section 36 when a command indicating data update in the cache memory 20 is detected by the update address registering section 33. When the command indicating data update is detected at step I1, corresponding region Ai is identified according to the processor identifier and the update address at step I2. At step I3 the fullness flag of the region Ai is examined. If OFF at step I3, the operation jumps to step I8. If ON at step I3, the entry reclaiming section 36 uses the address in the entry designated by the R pointer of the region Ai to issue a bus command to write-back the data in the dirty block into the main memory at step I4. At step I5 whether or not the R pointer designates the last entry is examined. If No at step I5, the R pointer is incremented by one at step I6. If Yes at step I5, the R pointer is set to designate the first entry at step I7. At step I8 the update address is registered to the entry designated by the W pointer. At step I9 whether or not the W pointer designates the last entry is determined. If No at step I9, the W pointer is incremented by one at step I10. If Yes at step I10, the W pointer is set to designate the first entry at step I11. At step I12 the equality of the W pointer and the R pointer is examined. If YES, the fullness flag is turned ON at step I13, and then the operation ends. If NO, the operation ends without changing the fullness flag. The operation of the flush executing section 35 is shown in FIG. 19. The flush executing section 35, receiving a cache flush request issued from the processor 10 fetches all of the addresses stored in the update address memory 32 (so that the read addresses are removed from the update address memory 32) and issues bus commands each of which writes back the data of a dirty block. In this alternative embodiment, the effective update addresses are stored in only entries of the range designed by the R pointer and the W pointer of each region Ai. Therefore, the update addresses can be efficiently fetched. The operation of the cache flush device 30 according to this embodiment will now be described. (Initialization) The processor 10 initializes the cache flush device and the state of the cache memory 20 in order to match the state of the cache memory 20 and the state of the update address memory 32 of the cache flush device 30 prior to activating the cache flush device 30. The initialization is performed such that all of the cache blocks are invalidated. Although it is not inevitable, it is still recommended in terms of performance that the R pointer and W pointer of each region are set to designate the same entry. (Normal Operation of Cache Flush Device 30) After the processor 10 performs the initialization, each section of the cache flush device 30 perform predetermined operations so that addresses of all the dirty blocks are stored in the update address memory 32. However, when the data of a certain dirty block is written-back into the main memory 51, any of the addresses stored in the regions A 0 to A n-1 is not removed. Therefore, a case is probable to take place where a dirty block turns to a non-dirty block while the associate address remains in the update address memory 32. When the update address registering section 33 detects that data is updated on the cache memory 20, the update address registering section 33 selects one of the regions A 0 to A n-1 according to the update address and the processor identifier 10. If no empty entry exists in the region, that is, the fullness flag is ON, the entry reclaiming section 36 issues, to the system bus 40, a bus command to write-back the data of the dirty block having the address stored in the entry designated by the R pointer. If the dirty block having the address exists, the data is actually written-back into the main memory 51. If no dirty block having the address exists, no operation is performed. Since the foregoing operation assures that no dirty block corresponding to the address exists, the entry designated by the R pointer can be used to hold the update address. When the data of the dirty block is written-back into the main memory 51 during the normal data processing of the processor 10, the cache flush device 30 do not perform any operation. (Cache Flush Operation by Cache Flush Device 30) When the processor 10 requests the cache flush device 30 to start cache flush, the flush executing section 35 fetches all of the addresses stored in the update address memory 32 and issues bus commands each of which writes-back the data of the dirty block. As a result, the state of the cache memory and the state of the cache flush device 30 return to the initial state. In comparison to the first embodiment, this alternative embodiment is able to associate the addresses and the regions more flexibly. That is, in the first embodiment, the regions of the update address memory 32 should resemble the structure of the cache memory 20. However in the second alternative embodiment, this restriction is not necessary and a cache flush device of the second alternative embodiment may be applicable over various cache memory architectures so far as the bus specification does not vary. Examples of associating the addresses and the regions will now be described. (Configuration 6) It is assumed that the cache memory 20 is a direct map and the number of the processors is p. In this case, a region can be provided to the i-th cache block of all the processors 10. Assuming that the number of the cache blocks in one cache memory 20 is M, the number n of the regions is M. Although the first embodiment requires p or more entries for forming one region, the number of entries can be reduced in this embodiment. In this case, p cache blocks correspond to one region, the number of entries may be about p/2 because the probability at which a certain cache block is dirty is usually from 20% to 50%. Moreover, any special mechanism to cope with a write buffer of the processor 10 is not required because of the reason described later. (Configuration 7) In an extreme case, the number of regions may be one. Since the number of the cache blocks is p × M, the number of entries is made to be from p × M/4 to p × M/2. The configuration of the cache memory 20 may be direct map, set associative method, full associative or of any other scheme. In this alternative embodiment, the cache flush device 30 does not issue any bus command when an empty entry exists. If no empty entry exists, a bus command is issued to cause a writing-back of data of a dirty block. When the number of the region is made to be one, the advantage is that the hardware for selecting the region according to the processor identifier and the update address can be omitted. However, it leads to a poor performance because it tends to cause unnecessary write back of data of a dirty block. (Configuration 8) A case where the cache memory 20 is N-way set associative, the number of cache blocks is M and the number of processors is p will now be described. It is assumed that the size of a cache block is B bytes. In this case, N cache blocks form a group, and data at address a is stored in ((a/B) mod (M/N))th cache block group. It is further assumed that the number of regions is p × M and the number of entries of each region is 1. Moreover, update of data at address a performed by a processor having processor identifier k is made to correspond to a (M × k + (a/B mod M))th region. With the foregoing method, while the cache memory 20 acts as N-way set associative, the cache flush device 30 manages the update addresses like a direct map cache memory. When the processor 10 having an identifier 0 is going to update data at address B × M where the cache block has the data of address 0 in a dirty state, the cache flush device 30 issues a bus command to causing a write-back of data of address 0 into the main memory 51. In this alternative embodiment, one region can be made to correspond to a certain cache block of all of the processors 10 as described in Configuration 7 and 8. As a result, the update address registering section 33 does not necessarily require the identifier of the processor 10. Referring to FIG. 20, the operations performed when the processor 10 successively writes data D0, D1 and D2 to addresses 0, B × M and 2B × M will now be described. Note that symbol B indicates the size of the cache block, and M indicates the number of cache blocks of the processor. The number of entries of the region A 0 is made to be 2. (1) Although the processor 10 is going to write data D0 at address 0, the data at address 0 does not exists in the cache block 0. Therefore, the processor 10 issues a bus command for requesting the data from address 0 to address (B - 1) and notifying update of the data to the other processors 10. (2) As a result, the data is brought and stored into the cache block 0 in a dirty state. Among the data, data at address 0 is updated to D0. The address 0 is stored in the region A0 as an update address. (3) Although the processor 10 is going to write data D1 at address B × M, data at the address B × M is not stored in the cache block 0. Therefore, a bus command for writing-back data at address 0 into the main memory 51 is stored in the write buffer. Then, a bus command is issued for requesting data from address B × M to address (B × M + B - 1) and notifying update of the data to the other processors 10. (4) As a result, data from address B × M to address (B × M + B - 1) is brought and stored in the cache block 0 in dirty state. Among stored data, data at address B × M is updated to D1. Address B × M is newly stored in the region A0 as update addresses. (5) Although the processor 10 is going to write data D2 at address 2B × M, data at the address 2B × M is not stored in the cache block 0. Therefore, a bus command for writing-back data at address 0 into the main memory 51 is stored in the write buffer. Then, a bus command is issued for requesting data from address 2B × M to address (2B × M + B - 1) and notifying update of the data to the other processors 10. (6) As a result, data from address 2B × M to address (2B × M + B - 1) is brought and stored in the cache block 0 in dirty state. Among stored data, data at address 2B × M is updated to D1. Address 2B × M is newly going to be stored in the region A0 as update addresses. As the fullness flag is ON, a write-back command of address 0 is scheduled to be issued. (7) The write-back command which has been held in the write buffer since (3) and the write-back command scheduled in (6) are issued. (8) The write-back command of data D1 at address 2B × M which has been held in the write buffer is issued. (9) The sequence of the operations comes to an end where both 2B × M and B × M exists as update addresses in the entries of the region A0. Note that only 2B × M is the valid update address. (Third Embodiment) A third embodiment of the present invention will now be described. FIG. 21 shows the structure of the computer system according to the third embodiment. The cache flush device 30 is applied to the same computer as of the first and second embodiments. The cache flush device 30 comprises a system bus interface 31, update address memory 32 (regions A 0 to A n-1 ), update address registering section 33, update address removing section 34, flush executing section 35 and entry reclaiming section 36. The update address memory 32, the update address registering section 33, the flush executing section 35 and the entry reclaiming section 36 are the same as those according to the second embodiment. The difference from the second embodiment is that the update address removing section is added like the first embodiment. While the update address removing section of the first embodiment, when a write-back bus command is observed, always seeks and clears the entry having the address contained in the bus command, the update address removing section of the third embodiment, when a write-back bus command is observed, tries to seek the entry for a certain time. If it is successful, the entry is cleared. Otherwise the entry remains unchanged. Since there is a possibility that the update address memory 32 holds addresses whose associated dirty blocks do not exist any more, the entry reclaiming section 36 is necessary as in the second embodiment. A typical example in which the update address removing section 34 tries to seek the entry which holds the same address as that of the write-back bus command for a predetermined time will now be described with reference to an operation diagram shown in FIG. 22. As shown in FIG. 22, the update address removing section 34 compares the contents of the entry designated by the R pointer with the write-back address (step K3). If they are the same, the update address removing section 34 advances the R pointer (steps K5 to K6) so as to remove the update address. As a result, the performance can be improved. Instead of seeking the entry for a predetermined time, seeking the entry until a next bus command indicating data update or a bus command for writing-back the contents of the dirty block is detected. This modification improves the performance furthermore because the possibility for the update address removing section 34 to remove the update address from the update address memory 32 is raised. Moreover, when a bus command which shows a cache block is non-dirty is detected, the update address removing section can try to seek and remove the entry. It improves the performance. (Fourth Embodiment) A fourth embodiment of the present invention will now be described. FIG. 23 shows the structure of a computer system according to the fourth embodiment of the present invention. The structure of the computer to which the cache flush device 30 is applied is the same as that according to the first embodiment. The cache flush device 30 comprises the system bus interface 31, update address memory 32 (regions A 0 to A n-1 ), update address registering section 33, update address removing section 34, flush executing section 35 and entry reclaiming section 36. The update address memory 32 has, in addition a dirty block counter for maintaining the number of dirty blocks corresponding to the regions, as shown in FIG. 24. In addition the update address registering section 33 has a function for, by one, increasing the count value of the dirty block counter corresponding to the regions. The entry reclaiming section 36 is the same as that of the second embodiment. FIG. 25 is an operation diagram of the update address registering section 33 and the entry reclaiming section 36 when the update address registering section 33 detects a command indicating data update in the cache memory 20. When the command indicating data update is detected at step L1, the corresponding region Ai is identified according to the processor identifier and the update address at step L2. At step L3, the dirty block counter is incremented by one. At step L4, it is determined whether or not the fullness flag of the region Ai is ON. If NO at step L4, the process is shifted to step L9. If YES at step L4, the entry reclaiming section 36 uses the address in the entry designated by the R pointer of the region Ai to issue a command for requesting writing-back of the data in the dirty block into the main memory at step L5. At step L6, it is determined whether or not the R pointer designates the last entry. If NO at step L6, the R pointer is incremented by one at step L7. If YES at step L6, the R pointer is caused to designate the first entry at step L8. Then, step L9 is performed. At step L9, the update address is registered to the position designated by the W pointer. At step L10, it is determined whether or not the W pointer designates the last entry. If NO at step L10, the W pointer is incremented by one at step L11. If YES at step L10, the W pointer is caused to designate the first entry at step L12. Then, step L13 is performed. At step L13, it is determined whether or not the positions respectively designated by the W pointer and the R pointer are the same. If the same positions are pointed, the fullness flag is turned on at step L14, and then the operation is ended. If the designated positions are not the same, the operation is immediately ended. FIG. 26 shows an operation of the update address removing section 34. When the update address removing section 34 detects a command for writing-back the contents of the dirty block into the main memory 51 (step M1), the update address removing section 34 selects one of n regions (A 0 to A n-1 ) forming the update address memory 32 according to the address (write-back address) at which the write-back is performed and the processor identifier 10 which performs write-back (step M2), and then decrements the dirty block counter by one (step M3). If the count value of the dirty block counter is made to be zero as a result of this decrement, the values of the R pointer and the W pointer are made to be the same and the fullness flag is turned off (step M5) so that all of the update addresses stored in the region are removed. FIG. 27 is an operation diagram showing the process which is performed by the flush executing section 35. The flush executing section 35 follows a command issued from the processor 10 to issue, to the system bus 40, a command for requesting writing-back, into the main memory 51, of the contents of the dirty block having the address stored in each entry of a region having the dirty block counter, the value of which is not zero (step N3). When the count value of the dirty block counter is made to be zero (step N2), the process of the foregoing region is ended. This embodiment has the structure such that, in addition the dirty block counter is provided to correspond to the regions forming the update address memory 32 and the update address registering section 33 and the update address removing section 34 control the dirty block counter to correspond to increase/decrease of the dirty blocks. When all of the dirty blocks corresponding to a certain region are disappeared, the update address removing section 34 makes empty the entries of all of the foregoing regions. As a result, the frequency of turning the entry reclaiming section 36 on can be lowered as compared with the second embodiment. Thus, the performance of the computer having the cache flush device 30 according to this embodiment. Although all of the entries of the corresponding region Ai are made to be empty when the dirty block counter is decremented to zero by the update address removing section 34 according to this embodiment, it might be considered feasible to employ the following second method of use of the dirty block counter. It is assumed that the count value of the dirty block counter of the region Ai is made to be 1 as a result of the decrement operation. If the number (which can be calculated in accordance with the difference between the R pointer and the W pointer) of the update addresses stored in the region Ai is large, it means a fact that no dirty block exists with respect to substantially all update addresses stored in the region Ai. If the entry reclaiming section 36 is applied to all of the entries of the region Ai, the number of issues of commands for requesting writing-back into the main memory 51 to the addresses in each of which no dirty block exists can be decreased. Therefore, improvement of the performance can be performed. The first to fourth embodiments have been described with regard to the cache flush device. A fault tolerant computer employing one of the foregoing embodiments will now be described. (Fifth Embodiment) FIG. 28 shows a fifth embodiment of the present invention. The cache flush device 30 according to one of the first third or fourth embodiments is connected to the system bus 40. Each of the processors 10 has a copy-back type cache memory 20 having a cache coherency function. The computer according to this embodiment performs one of the three steps below so as to be capable of process data with excellent fault tolerant performance. (1) Normal Data Processing Step While causing the cache flush device 30 to acquire the update address, a normal data processing is performed. (2) Checkpoint Acquisition Step This step is periodically performed by temporarily interrupting the normal data processing step. In a case where a plurality of processors 10 are provided, all of the processors 10 are synchronized to perform this step. In this step, the two processes below are performed. (2a) The context (the contents of the program counter, general-purpose register, and the like of the processor 10) of the processor 10, which is processing data, are stored in the main memory 51. (2b) By turning the flush executing section 35 of the cache flush device 30 on, the contents of all of the dirty blocks are written-back into the main memory 51. (3) Rollback & Recovery Step This step is performed if a problem of the computer takes place during the normal data processing step or the checkpoint acquisition step. In this step, the two processes below are performed. (3a) The main memory 51 is restored to the state of the checkpoint which is acquired immediately before the problem. (3b) Information stored in the restored main memory 51 is used to restart the normal data processing (when the operation is restarted, the operation is shifted to the normal data processing step). FIG. 29 shows a state in which the shift among the three steps are denoted. After a predetermined time has elapsed from start of the normal data processing step, each processor 10 starts the checkpoint acquisition step. In this checkpoint acquisition step, a first process is performed such that the progress of the process, that is, the context (the contents of the program counter, state register, the general purpose register and the like) of the processor when the normal data processing step is shifted to the checkpoint acquisition step is written into the main memory 51. However, it may simply be stored in the cache memory 20. A second process is performed in the checkpoint acquisition step such that the contents of the dirty block are written-back into the main memory 51. The second process is required to restart the normal data processing by the rollback & recovery step from a state before a fault even in a case of the fault in which data in the cache memory 20 is destroyed takes place. When the checkpoint acquisition step is ended, the normal data processing step is restarted. At this time, the context of the processor 10 written into the main memory 51 in the checkpoint acquisition step is used. FIG. 29 shows a state where a fault takes place during a third data processing step and the rollback & recovery step is started. In the rollback & recovery step, a first process is performed such that the state of the main memory 51 is restored to the state where the latest checkpoint acquisition step is performed, that is, the state is restored to the state just before the third data processing step is started. In general, write-back of the contents of the dirty block into the main memory 51 takes place any time, the state of the main memory 51 is slightly changed from the state when the normal data processing step is started. Accordingly, the state of the main memory 51 is restored to the state of the latest checkpoint as the first process of the rollback & recovery step. The restoration may be performed such that the contents of the main memory 51 before the write-back are stored in a log memory whenever write-back of the contents of the dirty block into the main memory 51 takes place and the contents are used to restore the state of the main memory 51. When, for example, data D1 is written-back into address a , the memory controller 50 stores the write-back command and reads out the contents (D0) at address a of the main memory 51. Then, D1 is written to address a of the main memory 51. Then, a pair of address a and data D0 is stored. As the first process of the rollback & recovery step, D0 is written into the main memory 51 at the address a so that the state of the main memory 51 at the latest checkpoint is restored. Another method may be employed in which the main memory 51 is duplicated as memory A and memory B. When write-back of the contents of the dirty block into the main memory 51 is performed in the normal data processing step, write-back to only the memory A is performed. The change in the memory A is adapted to the memory B in the checkpoint acquisition step. Thus, the restoration can be performed. A second process of the rollback & recovery step is to restart the normal data processing step at the restored state of the main memory. The foregoing process is the same as the shift from the checkpoint acquisition step to the normal data processing step. In the case shown in FIG. 29, a fourth data processing step is started from the same state as the third data processing step. In the rollback & recovery step, a process must be performed in which the cause of the fault is detected to separate the defective device. If a critical problem takes place, restart must be abandoned and the operation of the computer must be interrupted. Since this process is not the gist of the present invention, it is omitted from the further description. Since the computer of the above type involves deterioration in the performance because of the periodical execution of the checkpoint acquisition step, the time required to perform the checkpoint acquisition step must be shortened. Since the major portion of the checkpoint acquisition step is to write-back the contents of the dirty block into the main memory 51, use of the cache flush device 30 according to the present invention enables the time required to perform the write-back to be shortened. Thus, the time required to complete the checkpoint acquisition step can significantly be shortened. If the flush executing section 35 of the cache flush device 30 is turned on in the latter half portion of the normal data processing step, the time required to complete the checkpoint acquisition step can furthermore be shortened. The reason for this is that the number of the dirty blocks can considerably be reduced when the checkpoint acquisition step is started because the flush executing section 35 of the cache flush device 30 is turned on as compared with the case where the foregoing process is not performed. If the foregoing process is not performed, the probability of the dirty blocks can be lowered from, for example, 30% to about 15%. Since the flush executing section 35 of the cache flush device 30 according to one of the first to fourth embodiments is able to efficiently fetch the update address stored in the update address memory 32, the time required to complete the checkpoint acquisition step can be substantially be halved if the probability of the dirty blocks is 15%. (Sixth Embodiment) A sixth embodiment of the present invention will now be described. FIG. 30 shows the structure of a fault tolerant computer having the cache flush device 30 according to one of the first, third or fourth embodiments. As shown in FIG. 30, the computer according to this embodiment has a structure such that independent first and second computers 100a and 100b are connected to each other by an update monitor section 60 (in the first computer 100a) and a memory update section 70 (in the second computer 100b). The first computer 100a and the second computer 100b must comprise the same type processors 10 and the same type main memories 51. The first computer 100a always performs the normal data processing step and the checkpoint acquisition step. On the other hand, the second computer 100b usually performs a waiting step and continuously performs the normal data processing which is performed by the first computer 100a if a fault takes place in the first computer 100a. The update monitor section 60 monitors the system bus 40 of the first computer 100a to monitor and store commands generated in the first computer 100a and capable of updating the main memory 51. The update monitor section 60 follows a command issued from the first computer 100a to supply the stored commands to the memory update section 70 connected to the second computer 100b. The memory update section 70 supplies the commands received from the update monitor section 60 to the system bus 40 of the second computer 100b so as to make coincide the state of the main memory 51 of the second computer 100b with that of the first computer 100a. The normal data processing step and the checkpoint acquisition step of the first computer 100a will now be described. (1) Normal data processing Step While causing the cache flush device 30 to acquire the update address, the usual data processing is performed. (2) Checkpoint Acquisition Step This step is periodically performed in such a manner that the normal data processing step is temporarily interrupted. If a plurality of the processors 10 are provided, all of the processors 10 must be synchronized with one another. In this step, three processes below are performed. (2a) The context (the contents of the program counter, a general purpose register and the like of the processor 10) of the processor 10, which is performing the data process, are stored in the main memory 51. (2b) By turning the flush executing section 35 of the cache flush device 30 on, the contents of all of the dirty blocks are written-back into the main memory 51. (2c) A command is issued to the update monitor section 60 to supply the stored commands to the memory update section 70. In the waiting step of the second computer 100b, each of the processors 10 does not perform the normal data processing but examined whether or not main memory update commands are periodically supplied from the first computer 100a to the memory update section 70. If the command is not received for a period longer than a predetermined period, it is determined that the first computer 100a is brought to an operation inhibited state. Thus, the normal data processing is performed in the state of the main memory 51 of the second computer 100b at the foregoing moment. FIG. 31 shows a state of the computer according to this embodiment in which the states of the first computer 100a and the second computer 100b are changed as the time elapses. After a predetermined time has elapsed from start of the normal data processing step, each processor 10 of the first computer 100a starts the checkpoint acquisition step. In this checkpoint acquisition step, a first process is performed such that the progress of the process, that is, the context (the contents of the program counter, state register, the general purpose register and the like) of the processor when the normal data processing step is shifted to the checkpoint acquisition step is written into the main memory 51. However, it may simply be stored in the cache memory 20. A second process of the checkpoint acquisition step is to write-back the contents of the dirty block into the main memory 51. The second process is required to supply all of updated contents of the main memory 51 in the first computer 100a to the second computer 100b. A third process of the checkpoint acquisition step is performed such that a command is issued to the update monitor section 60 to supply the stored commands to the memory update section 70. It is preferable that the command be issued immediately before end of the checkpoint acquisition step. The reason for this is that the second computer 100b must always store a correct main memory image. After the checkpoint acquisition step is ended, the normal data processing step is restarted. At this time, the context of the processor 10 written into the main memory 51 in the checkpoint acquisition step is used. FIG. 31 shows a state where a fault is generated during the third data processing step. At this time, the first computer 100a is required to simply interrupt the operation thereof. As an alternative to this, start up may be performed to make provision for a fault of the second computer 100b. The second computer 100b performs the wait step until a fault generates in the first computer 100a. At timing T, it is determined that the memory update section 70 does not receive a command from the update monitor section 60 for a predetermined time and the normal data processing step is performed. In the case shown in FIG. 31, the normal data processing step is, in the second computer 100b, started in the same state as the third data processing step of the first computer 100a. Since the computer of above type involves deterioration in the performance because of the periodical execution of the checkpoint acquisition step, the time required to perform the checkpoint acquisition step must be shortened. Since the major portion of the checkpoint acquisition step is to write-back the contents of the dirty block into the main memory 51, use of the cache flush device 30 enables the time required to perform the write-back to be shortened significantly. If the flush executing section 35 of the cache flush device 30 is turned on in the latter half portion of the normal data processing step, the time required to complete the checkpoint acquisition step can furthermore be shortened similarly to the fifth embodiment. As described above, the cache flush device according to the present invention causes the addresses of all of the dirty blocks on the cache memory to be stored in one of the regions in the cache flush device. If a certain cache block is brought to the dirty state and then suspended from the dirty state, the address is removed from the region. The flush execution portion issues the command for sequentially fetching the addresses of the dirty blocks from each region and writing-back the contents of the dirty block at the address into the main memory so that the contents of all of the dirty blocks are written-back into the main memory. As a result, the process as is required for the conventional software to sequentially determine all of the cache blocks whether or not the cache block is the dirty block can be omitted. Therefore, the cache flush procedure can quickly and efficiently be performed. Even if the processor has the write buffer and each region has only one entry, only the address (the latest update address) of data stored in the cache block in place of the write buffer is stored in the foregoing entry so that an appropriate cache flush procedure is performed. Moreover, a mechanism for issuing a command for writing-back the update address to be adaptable to the state of use of the region is provided so that the number of entries of the region of the update address storage portion is considerably freely be set and the regions and the addresses are made coincide with one another significantly freely. Since the computer system according to the present invention is able to quickly and efficiently perform the cache flush procedure which is the major portion of the checkpoint acquisition step, the performance of the system can be improved.

Claims: A cache flush apparatus for use in a computer having a plurality of processors (10) each provided with a copy-back type cache memory (20) having a bus snoop mechanism, a main memory (51) and a system bus (40) connecting said plurality of processors (10), said cache flush apparatus and said main memory (51), a single cache flush apparatus being provided for the copy-back type cache memories (20) of the plurality of processors (10) and comprising: update address storage means (32) having a plurality of regions each of which has one or more entries each of said entries for storing an address of data held in a dirty block of one of said copy back type cache memories (20), - wherein said regions are configured according to the major aspects of the cache memory configuration; update address registering means (33) for monitoring said system bus (40) to detect an update of data within one of said cache memories (20), selecting a region of said update address storage means (32) according to the memory address MU at which the data has been updated and the identifier of the processor (10) which has updated the data and storing the memory address MU as an update address in an empty of the selected region; update address removing means (34) for monitoring said system bus (40) to detect a write-back of data from a dirty block, selecting a region of said update address storage means (32) according to the memory address MW at which the data has been written back and the identifier of the processor (10) from which the data has been written back and removing the update address which is equal to the memory address MW and is stored in an entry of the selected region; and flush executing means (35), for issuing, to said system bus (40) in response to a request from one of said processors (10), a command for sequentially reading all of update addresses stored in said update address storage means (32) and writing-back into said main memory (51) the data of the dirty block indicated by each of said update addresses read. A cache flush apparatus according to claim 1, wherein each said copy-back type cache memory is a direct map cache memory (20). A cache flush apparatus according to claim 1, or 2, further comprising update address reading means (37) for sequentially reading all of the update addressees stored in said update address storage means (32) in order to make the update addresses co be read by one of said processors (10). A computer system comprising: a cache flush apparatus according to any of claims 1 to 3, a plurality of processors (10) each provided with a copy-back type cache memory (20) having a bus snoop mechanism, a main memory (51) and a system bus (40) connecting said plurality of processors (10), said cash flush apparatus and said main memory (51). A computer system according to claim 4 arranged to periodically extract a checkpoint for restarting an interrupted process; said computer system further comprising: normal data processing means for performing a normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing the context during data process which is performed such that all of said processor (10) are synchronized with one another into said main memory (51) and writing-back, into said main memory (51), of data stored in all of the dirty blocks by said flush executing means (35) of said cache flush apparatus; and rollback & recovery means for restoring said main memory (51) to a previous checkpoint when a fault has taken place and using information stored in said restored main memory (51) to restart the normal data processing.

Inventors: KANO TAKUYA, MASUBUCHI YOSHIO, SAKAI HIROSHI, KANO, TAKUYA, MASUBUCHI, YOSHIO, SAKAI, HIROSHI, Kano, Takuya, c/o Kabushiki Kaisha Toshiba, Masubuchi, Yoshio, c/o Kabushiki Kaisha Toshiba, Sakai, Hiroshi, c/o Kabushiki Kaisha Toshiba
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1997
Main classification: G06F12
IPC codes: G06F12, G06F11