APPARATUS AND METHOD FOR GENERATING A CURRENT WITH A POSITIVE TEMPERATURE COEFFICIENT

Abstract: The invention provides for a bias current generator (10) which includes a first circuit component (MP2) having a first voltage developed across a pair of terminals thereof, the first voltage decreasing as an operating temperature of the first circuit component increases. The bias current generator further includes a second circuit component (Q2) having a second voltage developed across a pair of terminals thereof, the second voltage decreasing as an operating temperature of the second circuit component increases. In addition, the bias current generator (10) includes an impedance element (R2) connected to the first circuit component (MP2) and the second component (Q2), the impedance element (R2) having (i) an impedance which increases as an operating temperature of the impedance element increases, and (ii) a first current flowing therethrough, wherein a decrease in the first voltage causes a corresponding increase in the first current, and a decrease in the second voltage causes a corresponding increase in the first current. Moreover, the bias current generator (10) includes a mirroring circuit (MP3, MP4) for generating a second current which mirrors the first current flowing through the impedance element (R2). A method for generating a bias current that counteracts the effects temperature has upon electron and hole mobility is also disclosed.

Description: APPARATUS AND METHOD FOR GENERATING A CURRENT WITH A POSITIVE TEMPERATURE COEFFICIENT Background of the Invention The present invention relates to apparatus and method for generating a current with a positive temperature coefficient. In particular, but not exclusively, the invention relates to a bias generator for generating a bias current that counteracts the effect that temperature has upon electron and hole mobility. In complementary metal oxide semiconductor (CMOS) integrated circuits both P-channel Metal Oxide Semiconductor Field Effect Transistor (PMOSFET) devices and N-channel Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) devices are incorporated into a common substrate. Transconductance ( ge s ) , as measured in micromhos, is the extent to which drain current (I D ) changes in response to a change in gate-to-source voltage (V ?s ) ; that is, fs g = dI D I dV gs . It is well known that PMOSFET and NMOSFET devices have a transconductance characteristic that has a negative temperature coefficient (i.e. a transconductance that increases with a decrease in temperature and decreases with an increase in temperature) . A negative temperature coefficient transconductance characteristic causes a decrease in the switching speeds of PMOSFET and NMOSFET devices as temperature increases. The decrease in switching speeds of PMOSFET and NMOSFET devices is a direct result of a decrease in the electron and hole mobility associated with an increase in temperature. To offset the effects of a negative temperature coefficient transconductance characteristic, it is known to inject a proportional to absolute temperature bias current into the circuit . In CMOS circuits, bipolar transistors are commonly regarded as parasitic vertical devices because bipolar transistors cause a vertical current to flow through the substrate whereas essentially the rest of the CMOS elements cause a horizontal current to flow across the surface of the substrate. However, when desired in a CMOS circuit bipolar PNP transistors may be implemented in an N well CMOS process, wherein a transistor base is formed from an N well diffusion, a transistor collector is formed from a P-type substrate, and a transistor emitter is formed from P + of a P-channel drain/source diffusion. Likewise, bipolar NPN transistors may be implemented in a P we n CMOS process, wherein a transistor base is formed from an P we n diffusion, a transistor collector is formed from am N-type substrate, and a transistor emitter is formed from N* of an N-channel drain/source diffusion. In both cases, the emitter-base voltage (V EB ) has a large negative temperature coefficient whose value is a function of fabrication. One of the best known ways of obtaining a proportional to absolute bias current is to take the difference in the V EB values of two bipolar devices operating at different current densities. This difference in V EB values is developed across a resistor to obtain the proportional to absolute temperature bias current. However, the bias current in known bias current generators does not adequately compensate for the decrease of electron and hole mobility associated with an increase of temperature. That is, known bias current generators are not able to generate a high enough bias current to compensate for the decrease in electron and hole mobility caused by a negative temperature coefficient transconductance characteristic of CMOS devices, when temperature increases. For the foregoing reasons, there is a need for a bias current generator which sufficiently increases bias current as temperature increases in order to effectively counteract the negative effect that temperature has upon electron and hole mobility of CMOS devices. Summary of the Invention The present invention is directed to a bias generator that satisfies this need for a bias current that counteracts the effect that temperature has upon electron and hole mobility. According to one aspect of the present invention, there is provided a bias current generator comprising a first circuit component arranged to have a first voltage developed across a pair of terminals thereto and which decreases as the operating temperature of the first circuit component increases a second circuit component arranged to have a second voltage developed across a pair of terminals thereof and which decreases as the operating temperature of the second circuit component increases, an impedance connected to the first circuit component and the second component and having an impedance which increases as the operating temperature of the impedance element increases, a first current responsive so that a decrease in the first voltage causes a corresponding increase in the first current, and so that a decrease in the second voltage causes a corresponding increase in the first current . According to another aspect of the present invention there is provided a bias current generator, comprising a first circuit component having a first voltage developed across a pair of terminals thereof, said first voltage decreasing as an operating temperature of said first circuit component increases a second circuit component having a second voltage developed across a pair of terminals thereof, said second voltage decreasing as an operating temperature of said second circuit component increases a third circuit component having a third voltage developed across a pair of terminals thereof, said third voltage decreasing as an operating temperature of said third circuit component increases and an impedance element connected to said first circuit component, said second circuit component and said third circuit component, said impedance element (1) having an impedance which increases as an operating temperature of said impedance element increases, and (2) having a first current flowing therethrough, wherein (1) a decrease in said first voltage causes a corresponding increase in said first current, (2) a decrease in said second voltage causes a corresponding increase in said first current, and (3) a decrease in said third voltage causes a corresponding increase in said first current. According to a further aspect of the present invention there is provided a method of generating a bias current by way of a circuit arrangement having a • first circuit component and a second circuit component and comprising the steps of developing a voltage across an impedance so as to generate a first current by developing a first component voltage across a pair of terminals of the first circuit component and which decreases as an operating temperature of the first circuit component increases, and by developing a second component voltage across a pair of terminals of the second circuit component and which decreases as an operating temperature of said second circuit component increases, and mirroring the first current so as to generate a second current, and in a manner such that the voltage increases at a first rate as an operating temperature of said impedance element increases, the impedance increases at a second rate as an operating temperature of said impedance element increases wherein the first rate is greater than said second rate, and wherein a decrease in the first component voltage causes a corresponding increase in the first current, and a decrease in the second component voltage causes a corresponding increase in the first current. In accordance with one embodiment of the present invention, there is provided a bias current generator which includes a first circuit component having a first voltage developed across a pair of terminals thereof, said first voltage decreasing as an operating temperature of the first circuit component increases. The bias current generator further includes a second circuit component having a second voltage developed across a pair of terminals thereof, said second voltage decreasing as an operating temperature of the second circuit component increases. In addition, the bias current generator includes an impedance element connected to said first circuit component and said second component, said impedance element (1) having an impedance which increases as an operating temperature of said impedance element increases, and (2) having a first current flowing therethrough, wherein a decrease in said first voltage causes a corresponding increase in said first current, and a decrease in said second voltage causes a corresponding increase in said first current. Moreover, the bias current generator includes a mirroring circuit for generating a second current which mirrors the first current flowing through the impedance element. Pursuant to another embodiment of the present invention, there is provided a bias current generator which includes a first circuit component having a first voltage developed across a pair of terminals thereof, said first voltage decreasing as an operating temperature of the first circuit component increases. The bias current generator further includes a second circuit component having a second voltage developed across a pair of terminals thereof, said second voltage decreasing as an operating temperature of the second circuit component increases. In addition, the bias current generator includes a third circuit component having a third voltage developed across a pair of terminals thereof, said third voltage decreasing as an operating temperature of the third circuit component increases. Moreover, the bias current generator includes an impedance element connected to said first circuit component, said second circuit component and said third circuit component, said impedance element (1) having an impedance which increases as an operating temperature of said impedance element increases, and (2) having a first current flowing therethrough, and wherein (1) a decrease in said first voltage causes a corresponding increase in said first current, (2) a decrease in said second voltage causes a corresponding increase in said first current, and (3) a decrease in said third voltage causes a corresponding increase in said first current. In accordance with yet another embodiment of the present invention, there is provided a method for generating a bias current. The method includes the steps of (1) developing a voltage across an impedance element so as to generate a first current; and (2) mirroring the first current so as to generate a second current. In the above method, (1) said voltage increases at a first rate as an operating temperature of said impedance element increases, and (2) said impedance element has an impedance which increases ' at a second rate as an operating temperature of said impedance element increases, and (3) said first rate is greater than said second rate. Further in the above method, said developing step includes the steps of (1) developing a first component voltage across a pair of terminals of a first circuit component, said first voltage decreasing as an operating temperature of the first circuit component increases, and (2) developing a second component voltage across a pair of terminals of a second circuit component, said second voltage decreasing as an operating temperature of the second circuit component increases. Additionally, in the above method, (1) a decrease in said first component voltage causes a corresponding increase in said first current, and (2) a decrease in said second component voltage causes a corresponding increase in said first current . The present invention can therefore advantageously provide a bias current generator that counteracts the effect that temperature has upon electron and hole mobility, and so provide a new and useful bias generator which can be implemented in a standard CMOS process . A bias current generator can thus be provided that counteracts the effect that temperature has on the switching speeds of PMOSFET and NMOSFET devices . Brief Description of the Drawings The invention is described further hereinafter, by way of example only, with reference to the accompanying drawings in which: Fig. 1 is a schematic diagram of a known bias current generator that generates a bias current with a positive temperature coefficient; Fig. 2 is a schematic diagram of a bias current generator according to one embodiment of the present invention; Fig. 3 is a simplified block diagram of the bias current generator shown in Fig. 2 ; Fig. 4 is a graph comparing the effect of temperature upon the bias currents generated by the bias current generators shown in Figs. 1 and 2; and Fig. 5 is a schematic diagram of a bias current generator according to another embodiment of the present invention. Detailed Description of a Preferred Embodiment Referring now to Fig. 1, there is shown a schematic diagram of a known bias current generator 2 that generates a bias current with a positive temperature coefficient. That is, bias current generator 2 generates a bias current ^ OUTI with a small positive temperature coefficient. The bias generator 2 uses two transistors Q x and Q 2 with a resistor R x to generate the bias current I 0 u τι - Tne metal oxide semiconductor (MOS) devices MP A and MP B serve as a current mirror which forces the two currents I 1 and ^ flowing through the transistor Q 1 and device Q respectively to be substantially equal. The transistors MN A and MN B with their respective gate-source voltages form a voltage loop with the transistors Q x and Q 2 and the resistor R x . This voltage loop may be represented by equation (1) : ^(^J+/,Λ,+K β (β l )=^(A/}V β ) + P β tø) d) where V GΞ (MN A ) represents the gate-source voltage of the transistor MN A expressed in Volts (V) , x I represents the current flowing through the transistor Q x expressed in Amperes (A) , R x represents the resistance of the resistor R x expressed in Ohms (Ω) , V E ^C^) represents the emitter-base voltage of the transistor Q x expressed in Volts (V) , V GS (MN B ) represents the gate-source voltage of the transistor MN A expressed in Volts (V) , and V EB (Q 2 ) represents the emitter- base voltage of the transistor Q 2 expressed in Volts (V) . The emitter-base voltage V EB (Q N ) of a transistor Qn may be determined from equation (2) : where V EB (Q N ) represents the emitter-base voltage of the transistor Q N expressed in Volts (V) , k represents Boltzmann's constant of approximately 1.38xl0" 23 Joules per Kelvin (J / K) , T represents the absolute temperature expressed in Kelvin (K) , q represents the charge of an electron which is approximately 1.60xl0 ~19 Coulombs (C) , I N represents the current expressed in Amperes (A) flowing through the emitter of the transistor Q N , I SN represents the reverse saturation current of the emitter-base diode of the transistor Q N expressed in Amperes per square centimeter (A / cm 2 ) , and A EN represents the emitter area of the transistor Q N expressed in square centimetres (cm 2 ) . Substituting the right hand expression of equation (2) into equation (1) yields equation (3) : where I S1 represents the reverse saturation current of the emitter-base diode of the transistor 0^ expressed in Amperes per square centimeter (A / cm 2 ) , A E1 represents the emitter area of the transistor Q x expressed in square centimetres (cm 2 ) , 1 2 represents the current expressed in Amperes (A) flowing through the transistor Q 2 , I S2 represents the reverse saturation current of the emitter-base diode of the transistor Q 2 expressed in Amperes per square centimeter (A / cm 2 ) , and A E2 represents the emitter area of the transistor Q 2 expressed in square centimetres (cm 2 ) . The currents I x and I 2 are substantially equal because the transistors MP A and Mξ are matched devices and their source-gate voltages V sσ (MP A ) and s γ (MjP ) are the same. Therefore, the transistors MP A and MP B form a current mirror and force the current I λ to be substantially equal to the current I 2 . Furthermore, because the transistors Q and Q are matched devices except for the emitter areas A E1 and A E2 respectively, the reverse saturation currents I S1 and I S2 of the transistors Q λ and 2 Q are substantially equal. Furthermore, because the transistors MN A and MN B are matched devices and the currents I 1 and I 2 are substantially equal, the gate-source voltages V GS (MN A ) and GS V B (MN ) are substantially equal (see equation (9) below, substituting V GS (MN A ) for ^ (MP ) ) . Therefore, after noting that the current I α substantially equals the current 2 I , that the reverse saturation current I S1 substantially equals the reverse saturation current I s2 , and that the gate-source voltage V GS (MN A ) substantially equals the gate-source voltage V GS (MN B ) , equation (9) may be simplified to equation (4) : Because the transistor MP C and the transistors MP A are matched devices and share the same source-gate voltage, the drain current I oσn of the transistor MP C mirrors the current I x flowing through the transistor Q and substantially through the transistor MP A . As a result, the collection of like terms of equation (4) and the realization that the bias current I ot)T1 is substantially equal to : I yields equation (5) : where I 0OT1 represents the bias current in Amperes (A) flowing through the transistor MP C . Therefore, at a given temperature T, the emitter area A E1 of the transistor Q x , the emitter area A E2 of the transistor Q 2 , and the resistance of the resistor R x are the circuit design elements which control the bias current I 0t m• As stated above, the bias current I 0UT1 has a slight positive temperature coefficient. As can be seen from equation (5) , if the terms other than the temperature T were substantially constant as temperature increases, the bias current I 0OT1 would have a positive temperature coefficient. However, the resistance of the resistor R 1 is not substantially constant as temperature increases. Diffused resistors like the resistor R x increase over temperature and therefore have a positive temperature coefficient. The positive temperature coefficient of diffused resistors are dependent upon the material used to fabricate the resistor. For example heavier doped diffusions such as P + and N* yield resistors with lower temperature coefficients than resistors made with the typical N WELL or P WELL diffusion process. The rate of change in the resistance of diffused resistors like the resistor R l t however, is slower than the rate of the increase in the temperature T. Therefore, as can be seen from equation (5) , the bias current I 0UT1 increases with an increase in the temperature T because the value of T / R, increases despite the positive temperature coefficient of the resistor Ri The temperature T, however, has an exponential effect upon electron and hole mobility in the standard CMOS process. This effect upon electron and hole mobility may be represented by equation (6) : where T represents the temperature in Kelvin (K) , μ(T) represents the mobility of electrons or holes at the temperature T, T 0 represents room temperature in Kelvin (K) which is about 300 K, μ (T 0 ) represents the mobility of electrons or holes at the room temperature T 0 . Because the bias current I 0UT1 of FIG. 1 increases at a rate of approximately the change in the temperature (ΔT) over the change in the resistance (ΔR X ) of the resistor R x (ΔT / ΔRJ , the bias current I 0 uτ ι does not adequately increase in order to compensate for the exponential decrease of electron and hole mobility as shown in equation (6) . Now referring to Fig. 2, there is shown a schematic diagram of a first embodiment of a bias generator 10 which incorporates the features of the present invention therein. The bias current generator 10 may be fabricated using an N well CMOS process. In the preferred embodiment the transistors MP A , MP B , Mξ , Mp , MP , and MP are P-channel metal oxide semiconductor field effect transistors (PMOSFET) . Likewise, the transistors MN A and MN are N-channel metal oxide semiconductor field effect transistors (NMOSFET) . The transistors Q x and Q are parasitic PNP bipolar junction transistors (PNP BJT) , and the resistors R x and p. are diffused resistors. The transistor MP A is matched with the transistor MP (i.e. the transistors are manufactured such that they have quite similar operating characteristics) . Likewise, the transistor MP 2 is matched with the transistors Mξ and MP , the transistor MN A is matched with the transistor MN , and the transistor C h is matched with the transistor Q, , except that the emitter area A E2 of the transistor Q 2 is smaller than the emitter area A E1 of the transistor X Q . It should be appreciated by those skilled in the art that the above devices are matched only to simplify the design process and that non-matched devices could be used. It should further be appreciated by those skilled in the art that if transistors Q x and Q 2 are not matched devices, or if the current Ij . is not substantially equal to the current I 2 then the emitter area A E2 need not be smaller than the emitter area A E1 . Furthermore, it should be appreciated by those skilled in the art that the use of non-matched devices will result in a bias generator 10 that generates a bias current I OUTI that does not track temperature as well as the bias generator 10 would with matched devices. The source and the substrate of the transistor MP A and the source and the substrate of the transistor MP B are connected to the reference voltage V DD . The gate of the transistor MP A is connected to the gate of the transistor MP B thereby forming a first current mirror. Likewise, the source and the substrate of the transistor MP 2 , the source and the substrate of the transistor MP 3 , and the source and the substrate of the transistor MP 4 are connected to the reference voltage V DD . The gate of the transistor MP is connected at the node N 3 to the gate of the transistor MP 3 , and to the gate of the transistor MP 4 thereby forming a second current mirror. The drain of the transistor MP A is connected to the gate of the transistor MP A and to the drain of the transistor MN A . The drain of the transistor MP B is connected to the drain of the transistor MN B , and the drain of the transistor MN is connected to the gate of the transistor MN B . The gate of the transistor MN B is connected to the gate of the transistor MN A . The substrate of the transistor MN 3 and the substrate of the transistor MN A are connected to the reference voltage V ss . The resistor R λ is connected between the source of the transistor MN A and the emitter of the transistor X Q . The emitter of the transistor Q 2 is connected to the source of the transistor MN B at the node ! N . The base of the transistor Q 2 is connected to the base of the transistor Q x . The base and the collector of the transistor Q 1( and the base and the collector of the transistor Q 2 are connected to the reference voltage V ss which is ground. The gate of the transistor MP 2 is connected at the node N x to the source of the transistor MN B and to the emitter of the transistor Q 2 . The drain of the transistor ! MP is connected to the reference voltage V ss , and the substrate of the transistor MP 1 is connected at the node N 2 to the source of the transistor MP j. . Finally, the resistor R 2 is connected between the node N 2 and the node N 3 . The reference current I REF flows through the resistor R 2 . The bias current I ouτι flowing out of the drain of the transistor MP 3 mirrors the reference current I REF that flows out of the drain of the transistor MP 2 and through the resistor R 2 . Likewise, the bias current I 0UT2 flowing out of the drain of the transistor MP 4 mirrors the reference current I REF that flows out of the drain of the transistor MP and through the resistor R 2 The operation of the first embodiment depicted in FIG. 2 will now be discussed in detail. As can be seen by comparing the bias current generator 2 shown in FIG. 1 to the bias current generator 10 shown in FIG. 2, the transistors MP A , MP B , MM, , MN , X Q , and 2 Q as well as the resistor R λ function in the same manner. As a result the currents I 1 and I 2 of FIG. 2 may be represented by equation 97/50026 16 (5) as set forth above. As a result of the standard CMOS process, the resistor R JL has a positive temperature coefficient typically in the range from a few hundred to a few thousand parts per million per Kelvin (PPM / K) . The positive temperature coefficient for the resistor R x changes at a rate that is slower than the change in temperature. Therefore, as shown in equation (5) , the current I x has a positive temperature coefficient despite the positive temperature coefficient of the resistor R, . Referring now to equation (2) , an increase in the current l λ would result in a small increase in the emitter-base voltage V Ea (Q l ) of the transistor Qj if everything remained constant. However, because the reverse saturation current I S1 increases exponentially with an increase in the temperature T, a smaller emitter-base voltage V EB (Q 1 ) of the transistor Q x can drive the same current 1 X that a larger emitter-base voltage V EB (Q I ) drove at a lower temperature T. The net effect is that even though the currents Ii and X are increasing as temperature increases, the emitter-base voltages V E ^Q J ) and V Ea (Q 2 ) are decreasing as temperature decreases. Therefore, V E3 (Q ι ) an d V B (Q ) have a negative temperature coefficient typically of about -2 millivolts per Kelvin (mV / K) which does not substantially change with process variation or operating conditions. The path between the reference voltages V DD and V ss that goes through the source-gate voltage V S3 (MP 2 ) of the transistor MP 2 , the voltage V^ across the resistor R , the source-gate voltage V SG (MP 1 ) of the transistor Mξ , and the emitter-base voltage V E3 (Q 2 ) of the transistor 2 Q , can be expressed by equation (7) : V oo = v κ (MP 2 ) ÷ 7ζχ + , - sa ( MPι ) + y ε3 ( Qι ) _ v s3 (7) where V R2 represents the voltage across the resistor R 2 as a result of the reference current I REF flowing through the resistor R 2 . Equation (7) solved for the reference current I REF yields equation (8) : * ,R£F _- — v ∞ - v sa(m)- y x "{MP x )- r M (&) - r s (O) The reference voltages V DD and V ss are usually predetermined by design criteria. For example, V ss is typically ground and V DD is typically between 3.3 volts and 5.0 volts but is likely to fall below 3 volts in the future for deep submicron CMOS devices (i.e. devices with a channel length of less than 0.3 microns) . Furthermore, for a given current 1 2 the emitter-base voltage & (Q ) can be determined from equation (2) and at room temperature is typically about 700 millivolts (mV) . The source-gate voltages V SG (MP 1 ) and ΞG V (MP ) are dependent upon their respective drain currents I D1 and ^ 2 which are both substantially equal to the reference current I REF and are also dependent upon other parameters which are usually set by the manufacturing process. Assuming the design criteria requires a predetermined bias current I 00T1 for a given temperature T, the reference current I REF is substantially equal to the bias current I 0UT1 due to the current mirror formed by the transistors MP 2 and MP . Furthermore, the drain current I D1 of the transistor MP X and the drain current I D2 of transistors Mg are substantially equal to the reference current I REF because the gate currents of MOS transistors are usually negligible compared to the drain currents, the source-emitter voltages V SG (MP 1 ) and V SG (MP 2 ) may be determined from equation (9) : where μ p represents the mobility of holes expressed in square centimetres per Volt second (cm 2 / V sec) , e 0 represents the permittivity of free space expressed in Farads per centimeter (F / cm) , e r represents the relative dielectric constant of the semiconductor and is dimensionless, t ox represents the thickness of the gate oxide expressed in centimetres (cm) , V τ represents the threshold voltage of the transistor MP N expressed in Volts (V) , D I represents the drain current of the transistor MP N expressed in Amperes (A) , W represents the width of the channel of the transistor MP N expressed in centimetres (cm) , and L represents the length of the channel of the transistor MP N expressed in centimetres (cm) . An inherent quality of the standard CMOS process is that the threshold voltage V τ of a MOS transistor has a negative temperature coefficient typically of about -2.6 mV. As shown in equation (9) , the source-gate voltage V SG is directly dependent upon the threshold voltage V τ . Therefore, the source-gate voltages V SG (MP 1 ) and V SG (MP 2 ) have a negative temperature coefficient because as temperature increases, the threshold voltage V τ decreases and causes a decrease in the source-gate voltages V SG (MP X ) and V SG (MP 2 ) . Referring now to FIG. 3, there is shown a simplified block diagram of the bias current generator 10 shown in FIG. 2. The elements of FIG. 2 correspond to the blocks of FIG. 3 in the following manner: the source-gate voltage V SG (MP 2 ) of the transistor MP 2 corresponds with the output voltage of the voltage source V S1 ; the gate-source voltage y G (MP ) of the transistor MP X corresponds with the output voltage of the voltage source V S2 ; the emitter-base voltage V B (Q ) of the transistor Q 2 corresponds with the output voltage of the voltage source V S3 ; the resistor R 2 corresponds with the impedance element Z 2 ; the reference voltage V DD corresponds with the reference voltage V REF1 ; and the reference voltage V ss corresponds with the reference voltage V REF2 . Therefore as can be seen from FIG. 3, the voltage sources V S1 , V s2 , and V S3 along with the reference voltages V REF1 and V REF2 generate a voltage V Z2 across the impedance element 2 Z which may be represented by equation (10) : V - V - V - V - V - V RE? (10) The reference voltages V R ^ and V R∑ ^ remain substantially constant with a change in temperature. However, the output voltages of the voltage sources V sα , V s2 , and V S3 decrease wich an increase in temperature. Therefore, as can be seen from equation (10) , the voltage V R2 across the impedance element Z 2 increases with an increase in temperature and causes a reference current I REF to flow through the impedance element Z 2 . The reference currenfø I that flows through the impedance element Z 2 can be determined from the equation (11) : where V Z2 represents the voltage expressed in Volts (V) across the impedance element Z 2 , and jZ represents the impedance expressed in Ohms (Ω) of the impedance element Z 2 . As discussed above, the impedance of impedance element Z 2 increases with an increase in temperature but at a rate slower than the increase in the voltage V Z2 across the impedance element Z 2 . Therefore, as can be seen from equation (11) , the reference current I REF has a positive temperature coefficient because the reference current I REF increases with an increase in temperature. Referring now to FIG. 4, there is shown a graph comparing the effect of temperature upon the bias current Ϊ BIAS generated by the known bias current generator 2 (FIG. 1) , and by the bias current generator 10 (FIG. 2) of the present invention. As can be seen from FIG. 4, the bias current generator 10 of the present invention has a more dramatic increase in bias current I BIAS as temperature increases than the known bias current generator 2. This more dramatic increase in the bias current I BIAS is a direct result of using three voltage sources having a negative temperature coefficient to drive the resistor R 2 . Furthermore, this more dramatic increase in the bias current I BIAS is the reason that the bias current generator 10 counteracts more effectively the effect that increased temperature has upon electron and hole mobility, than the known bias generator 2. Now referring to Fig. 5, there is shown a schematic diagram of a second embodiment of a bias current generator 20 which incorporates the features of the present invention therein. As previously mentioned, the bias current generator 10 (FIG. 2) may be fabricated using an N well CMOS process. The bias current generator 20 (FIG. 5) is a P well CMOS representation of the bias current generator 10 (Fig. 2) . In particular, the bias current generator 20 includes transistors MN A , MN 3 , MN , MN , MN , and « MN which are N- channel metal oxide semiconductor field effect transistors (NMOSFET) . The bias current generator also includes transistors MP A and MP which are P-channel metal oxide semiconductor field effect transistors (PMOSFET) , transistors Q x and 2 Q which are parasitic NPN bipolar junction transistors (NPN BJT) , and the resistor R λ and P which are diffused resistors. The transistor MN A is matched with the transistor MJT (i.e. the transistors are manufactured such that they have quite similar operating characteristics) . Likewise, the transistor MN 2 is matched with the transistor MN and the transistor MN 4 , the transistor #1P is matched with the transistor MP B , and the transistor Q is matched with the transistor Q 2 except that the emitter areja A of the transistor Q 2 is smaller than the emitter area E1 A of the transistor Q x . It should be appreciated by those skilled in the art that the above devices are matched only to simplify the design process and that non-matched devices could be used. It should further be appreciated by those skilled in the art that if the transistors Q λ and Q are not matched devices or if the current 1 1 is not substantially equal to the current I 2 then the emitter area A E2 need not be smaller than the emitter area A E1 . Furthermore, it should be appreciated by those skilled in the art that the use of non- matched devices will result in a bias generator 20 that generates a bias current I oατι that does not track temperature as effectively as the bias generator 20 would with matched devices . The source and the substrate of the transistor MN A and the source and the substrate of the transistor MN B are connected to the reference voltage V ss which is ground. The gate of the transistor MN A is connected to the gate of the transistor MN B thereby forming a first current mirror. Likewise, the source and the substrate of the transistor MN 2 , the source and the substrate of the transistor MN 3 , and the source and the substrate of the transistor MN 4 are connected to the reference voltage V ss . The gate of the transistor MN 2 is connected at the node N 3 to the gate of the transistor MN 3 , and to the gate of the transistor MN 4 thereby forming a second current mirror. The drain of the transistor MN A is connected to the gate of the transistor MN A and to the drain of the transistor MP A . The drain of the transistor MN B is connected to the drain of the transistor MP B , and the drain of the transistor MP is connected to the gate- of the transistor MP B . The gate of the transistor MP B is connected to the gate of the transistor MP A . The substrate of the transistor MP B and the substrate of the transistor MP A are connected to the reference voltage V ss . The resistor R λ is connected between the source of the transistor MP A and the emitter of the transistor Q . The emitter of the transistor Q 2 is connected to the source of the transistor MP B at the node Nl. The base of the transistor Q 2 is connected to the base of the transistor Q x . The base and the collector of the transistor Q lr and the base and the collector of the transistor Q 2 are connected to the reference voltage V DD . The gate of the transistor MN j. is connected at the node N x to the source of the transistor MP B and to the emitter of the transistor Q 2 . The drain of the transistor j MN is connected to the reference voltage V DD , and the substrate of the transistor MN X is connected at the node N 2 to the source of the transistor MN X . Finally, the resistor R 2 is connected between the node N 2 and the node N 3 . The reference current I REF flows through the resistor R 2 . The bias current I 0UT1 flowing into the drain of the transistor MN 3 mirrors the reference current I REF that flows into the drain of the transistor MN 2 and through the resistor R 2 . Likewise, the bias current 3^ 2 flowing into the drain of the transistor MN 4 mirrors the reference current I REF that flows into the drain of the transistor MN 2 and through the resistor R 2 Since the bias current generator 20 (FIG. 5) is simply a P well CMOS representation of the bias current generator 10 (FIG. 2) , a detailed discussion regarding the operation of the bias current generator 20 is not warranted. Referring again to FIG. 3, the elements of the bias current generator 20 correspond to the blocks shown in FIG. 3 in the following manner: the gate-source voltage V GS (MN 2 ) of the transistor MN 2 corresponds with the output voltage of the voltage source V S1 ; the gate-source voltage V GS (M^) ' of the transistor MN corresponds with the output voltage of the voltage source V s2 ; the base-emitter voltage B V ^Q ) corresponds with the output voltage of the voltage source V S3 ; the resistor R corresponds with the impedance element Z 2 ; the reference voltage V DD corresponds with the reference voltage V REF2 ; and the reference voltage V ss corresponds with the reference voltage V REF1 . Therefore, as can be seen from FIG. 3, the voltage sources V S1 , V S2 , and y^ along with the reference voltages V REF1 and }J^ T2 generate a voltage V across the impedance element Z 2 which may be represented by equation (10) hereinabove. The reference voltages V R ^ and V R ^ remain substantially constant with a change in temperature. However, the output voltages of the voltage sources V S1 , V S2 , and V S3 decrease with an increase in temperature. Therefore, as can be seen from equation (10) , the voltage V Z2 across the impedance element Z 2 increases with an increase in temperature and causes a reference current I REF to flow through the impedance element Z 2 . The reference curren£ EF I that flows through the impedance element Z 2 can be determined from the equation (11) hereinabove. Furthermore, the impedance of impedance element Z 2 increases with an increase in temperature but at a rate slower than the increase in the voltage V Z2 across the impedance element Z 2 . Therefore, as can be seen from equation (11) , the reference current I REF has a positive temperature coefficient because the reference current I REF increases with an increase in temperature While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description is to be considered as exemplary and not restrictive in character, it being understood that the invention is not restricted to the details of the foregoing embodiments.

Claims: CLAIMS 1. A bias current generator (10) comprising: a first circuit component (MP2) arranged to have a first voltage developed across a pair of terminals thereof and which decreases as the operating temperature of the first circuit component increases; a second circuit component (Q2) arranged to have a second voltage developed across a pair of terminals thereof and which decreases as the operating temperature of the second circuit component increases; an impedance (R2) connected to the first circuit component (MP2) and the second component (Q2) having an impedance which increases as the operating temperature of the impedance element increases, a first current responsive so that a decrease in the first voltage causes a corresponding increase in the first current, and so that a decrease in the second voltage causes a corresponding increase in the first current. 2. A current generator (10) as claimed in Claim 1, including a mirroring circuit (MP3, MP4) for generating a second current which mirrors the first current flowing through the impedance (R2) . 3. A current generator (10) as claimed in Claim 1 or 2, wherein the first circuit component (MP2) , the second circuit component (Q2) and the impedance (R2) are interposed between a first reference potential (V DD ) and a second reference potential (V ss ) . wherein the impedance (R2) is interposed between the first circuit component (MP2) and the second circuit component (Q2) . 5. A current generator as claimed in Claim 1, 2, 3 or 4 , wherein: the second circuit component includes a bipolar transistor (Q2) having an emitter and a base and the emitter and the base comprise the said pair of terminals of the second circuit component. 6. A current generator as claimed in Claim 1, 2, 3, 4 or 5, wherein: the first circuit component includes a first field effect transistor (MP2) having a first source and a first gate and the first source and the first gate comprise the said pair of terminals of the first circuit component. 7. A current generator as claimed in any one of Claims 1 to 6, further comprising a third circuit component (MPl) arranged to have a third voltage developed across a pair of terminals thereof and which decreases as the operating temperature of the third circuit component increases. 8. A current generator as claimed in Claim 7, when dependent on Claim 6 , wherein said third circuit component includes a second field effect transistor (MPl) having a second source and a second gate and the second source and the second gate comprise the said pair of terminals of the third circuit component. 9. A current generator as claimed in Claim 8 when dependent on Claim 2, wherein: the mirroring circuit includes a third field effect transistor (MP3) having a third gate and a third source and which is arranged to generate the second current and wherein the first gate is coupled to the third gate, and the first source is coupled to the third source. 10. A current generator as claimed in Claim 9, wherein: the mirroring circuit further includes a fourth field effect transistor (MP4) having a fourth gate and a fourth source and which is arranged to generate a third current, and wherein the first gate is coupled to the fourth gate, and the first source is coupled to the fourth source. 11. A current generator as claimed in Claim 7, 8, 9 or 10, wherein the first voltage and the third voltage each decrease at a rate of about 2.6 millivolts per kelvin. 12. A current generator as claimed in any one of the preceding claims, wherein the second voltage decreases at a rate of about 2.0 millivolts per kelvin. 13. A current generator as claimed in any one of the preceding claims, wherein ■ the impedance has a temperature coefficient between about 200 parts per million per kelvin (PPM/K) and about 10000 parts per million per Kelvin (PPM/K) . 14. A current generator as claimed in any one of the preceding claims, wherein the impedance comprises a diffused resistor . 15. A method of generating a bias current by way of a circuit arrangement having a first circuit component and a second circuit component and comprising the steps of: developing a voltage across an impedance so as to generate a first current by developing a first component voltage across a pair of terminals of the first circuit component and which decreases as an operating temperature of the first circuit component increases, and by developing a second component voltage across a pair of terminals of the second circuit component and which decreases as an operating temperature of said second circuit component increases, and mirroring the first current so as to generate a second current, and in a manner such that the voltage increases at a first rate as an operating temperature of said impedance element increases, the impedance increases at a second rate as an operating temperature of said impedance element increases wherein the first rate is greater than said second rate, and wherein a decrease in the first component voltage causes a corresponding increase in the first current, and a decrease in the second component voltage causes a corresponding increase in the first current. 16. A method as claimed in Claim 15, wherein: the developing step further includes the step of developing a third component voltage across a pair of terminals of a third circuit component and which decreases as an operating temperature of the third circuit component increases, and wherein a decrease in said third component voltage causes a corresponding increase in said first current. 17. A method as claimed in Claim 16, wherein: the first circuit component includes a first field effect transistor having a first source and a first gate, the first source and the first gate having the first voltage developed thereacross, the second circuit component includes a bipolar transistor having an emitter and a base, the emitter and the base have the second voltage developed thereacross, the third circuit component includes a second field effect transistor having a second source and a second gate, and the second source and the second gate have the third voltage developed thereacross.

Inventors: GASPARIK FRANK, GASPARIK, FRANK
Applicants: GILL DAVID ALAN, SYMBIOS LOGIC INC, GILL, DAVID, ALAN, SYMBIOS LOGIC INC.
Application year: 1997
Main classification: G05F3
IPC codes: G05F3