Method of forming an Al/Ti layered interconnection

Abstract: In order to provide an Al/Ti layered interconnection which comprises a Ti (titanium) layer and an Al layer composed of Al (aluminum) or an Al alloy both formed over a base in this order and is capable of retarding a reaction between Ti and Al and preventing pinholes from occurring, the present invention is characterized as follows: The Al layer contains Si (silicon) in a portion adjacent to the Ti layer in a concentration capable of retarding an interface reaction between Ti and Al. Further, the concentration of Si in an Al layer portion on the side above the adjacent portion is set to a concentration lower than a concentration for allowing the upper Al layer portion to produce pinholes even at the maximum.

Description: BACKGROUND OF THE INVENTION Field of the Invention: This invention relates to a method of forming an Al/Ti layered interconnection heavily used as an interconnection or the like for a semiconductor device. Description of the Related Art: An Al/Ti stacked or layered interconnection has been known as an interconnection for providing excellent resistance to electromigration (EM). Since Al formed over Ti (normally oriented to a (0002) surface or plane) is firmly oriented onto a (111) plane and an interconnection in which a small amount of Ti has entered an Al layer, is enhanced, the EM resistance has been considered to improve. It is however known that when a structure formed by simply stacking a Ti layer and an Al layer on each other is used, both layers undergo a chemical reaction at an interface between the layers by a heat treatment (corresponding to heat treatment often used during a manufacturing process of a semiconductor device) at a temperature of 400°C or above thereby to increase wiring resistances. This has been disclosed in, for example, a reference I: Appl. Phys. Lett., vol. 23, No. 2, 15, p.99 (1973) and a reference II: J. Appl. Phys., 69(7), p.3907 (1991). Therefore, an Al layer containing Si has been used as the Al layer in the Al/Ti layered interconnection. This is because the reaction between Ti and Al can be retarded owing to the containing of Si in the Al layer. This has been described in, for example, a reference III proposed by inventors of this application, "Extended Abstracts of the 1994 International Conference on Solid State Devices and Materials, Yokohama, 1994, pp.952-954. SUMMARY OF THE INVENTION According to detailed investigations carried out by the inventors of the present application, it became apparent that pinholes would occur in the Al layer according to the concentration of Si when Si was contained in the Al layer of the Al/Ti layered interconnection. This will be described below in detail. A Ti layer having a thickness of 50nm and an Al layer (to be described in detail later) having a thickness of 500nm were continuously formed over a BPSG (Boro-Phospho silicate glass) film of a silicon substrate with the BPSG (Boro-Phospho silicate glass) film formed over the surface thereof, by a sputtering process to prepare an evaluation sample. However, samples of five standards or levels, in which the Al layer is represented in the form of (1): Al-Cu layer (i.e., an Al-Cu alloy layer zero in Si content), (2): Al-0.3%Si-Cu layer, (3): Al-0.5%Si-Cu layer, (4): Al-0.8%Si-Cu layer and (5): Al-2.0%Si-Cu layer, were prepared. Here, Al-0.3%Si and Al-0.5%Si means that Si are respectively contained in the proportions of 0.3 per cent by weight and 0.5 per cent by weight for Al. Incidentally, a film-forming condition at the time of sputtering was set as follows: A film-forming temperature, film-forming pressure and power of the Ti layer were respectively set to 100°C, 3 mTorr (1 Torr = 133 Pa) and 1 KW. Further, a film-forming temperature, film-forming pressure and power of the Al layer were respectively set to 250°C, 2 mTorr and 9 KW. The surfaces of the samples prepared in the above-described manner were observed and photographed by a scanning electron microscope (SEM) in a state prior to the next process immediately after the completion of a deposition process such as sputtering (hereinafter called "as-depo"). Here, SEM photographs each magnified about 12,000 times by the scanning electron microscope were respectively taken. It was further measured whether pinholes would appear in a region corresponding to an area of 525µm 2 in each photograph. Here, the number of the pinholes each larger than about 0.05µm in diameter was measured every samples having the respective standards. The numbers of pinholes for the respective standards in which Si concentrations were set to 0.3, 0.5 and 0.8 per cent by weight, were shown in Fig. 9 by bar graphs as a part of the result of measurement. It can be understood from Fig. 9 that no pinholes are observed in an Al/Ti layered interconnection having an Al layer in which the concentration of Si is set to 0.3 per cent by weight, whereas a number of pinholes are observed in an Al/Ti layered interconnection having an Al layer in which the concentration of Si is set to 0.5 per cent or higher by weight. Fig. 10(A) is a view showing a copy of a surface SEM photograph of an Al/Ti layered interconnection in which the concentration of Si is set to 0.8 per cent by weight, i.e., an Al-0.8wt%Si-Cu/Ti layer is formed. Further, Fig. 10(B) illustrates a copy of a surface SEM photograph of an Al-Cu/Ti layered interconnection in which the concentration of Si is zero, i.e., an Al-Cu layer is formed. It is understood that pinholes P are observed in Fig. 10(A) and no pinholes are observed in Fig. 10(B). Even when the samples given in the form of the respective standards are subjected to heat treatment in an atmosphere of nitrogen at temperatures of about 410°C, 450°C and 500°C for 30 minutes, the situation in which pinholes occur, substantially remains unchanged as upon as-depo. It can be understood from the above description that the pinholes will occur in the Al layer according to the concentration of Si contained in the Al layer in the Al/Ti layered interconnection. The pinholes are considered to cause void, in its turn have some fear for a reduction in resistance to electromigration. With advances in micronization of a semiconductor device, the more the interconnection is micronized, the more the fear is increased. It is considered that in order to avoid this, Si is not allowed to be contained in the Al layer, or even when Si is contained therein, Si may be contained therein by an amount (corresponding to 0.3 per cent by weight even at the maximum judging from the experimental results described with reference to Fig. 9 by way of example) lower than an amount required to allow the Al layer to produce the pinholes. However, this will cause a reduction in wiring resistance due to the reaction between Ti and Al as already described above and as will be described below in detail using Fig. 11. Fig. 11 is a diagram obtained by determining the rate of change in sheet resistance ΔR/R 0 from a sheet resistance R 0 at as-depo, of each of the samples having the five standards used in the experiments for making a decision as to whether or not the pinholes occur, and a sheet resistance of each sample heat-treated at the temperatures of about 410°C, 450°C and 500°C and plotting the rate of change in sheet resistance with respect to each temperature for heat treatment. In Fig. 11, a characteristic indicated by black dots or circles shows that the Al layer in the Al/Ti layered interconnection is the Al-Cu layer. A characteristic indicated by white circles exhibits that the Al layer is the Al-0.3%Si-Cu layer. A characteristic indicated by black square marks shows that the Al layer is the Al-0.5%Si-Cu layer. A characteristics indicated by white square marks exhibits that the Al layer is the Al-0.8%Si-Cu layer. Further, a characteristic indicated by white triangular marks shows that the Al layer is the Al-2.0%Si-Cu layer. Judging from the results shown in Fig. 11, the change in sheet resistance is still large before and after the heat treatment in the case of the Al/Ti interconnection having the Al layer in which the concentration of Si is set to 0.3 per cent by weight. In contrast to this, the change in sheet resistance are approximately the same before and after the heat treatment of the samples in the case of the Al/Ti interconnections having the Al layers in which the Si concentrations are respectively set to 0.8 per cent by weight and 2.0 per cent by weight. It is thus preferable from the experimental results to contain Si in the Al layer in a concentration of at least 0.8 per cent by weight to control an increase in wiring resistance due to the reaction between Ti and Al. However, this cannot prevent the pinholes from occurring. There has been a demand for the appearance of an Al/Ti layered interconnection having a structure capable of avoiding the reaction between Ti and Al and preventing pinholes from occurring in an Al layer. It has also been desired to propose a method capable of easily forming such an Al/Ti layered interconnection. Therefore, it has been found that the following structure is suitable for an Al/Ti layered interconnection comprising an Ti (titanium) layer, and an Al layer composed of Al (aluminum) or an Al alloy both of which are formed over a base or substrate in this order. Namely, the Al layer contains Si (silicon) in a portion adjacent to the Ti layer in a concentration capable of retarding an interface reaction between Ti and Al. Further, the concentration of Si contained in a portion located on the side above the adjacent portion is set to a concentration lower than a concentration for allowing the upper Al layer portion to produce pinholes even at the maximum. Accordingly, an Al/Ti layered interconnection can be obtained which has an Al layer of a structure wherein Si is contained by a needed amount only in a portion required to retard the reaction between Ti and Al and Si is not contained to the utmost in portions other than the portion (inclusive of the case in which no Si is contained). Therefore, the Al/Ti layered interconnection can be realized which is capable of preventing the reaction between Ti and Al and the occurrence of the pinholes. It is considered that the concentration of Si contained in the upper Al layer portion may preferably be 0.3 per cent by weight even at the maximum upon execution of the method of the present invention. This is because if the upper limit of the Si concentration is set in this way, then the pinholes are considered to be capable of being prevented from occurring in the Al layer in terms of the experimental results described using Fig. 9. It is also preferable to make the thickness of the upper Al layer portion thicker than that of the Al layer portion corresponding to the portion adjacent to the Ti layer. This is because if the Al layer portion adjacent to the Ti layer is excessively thick, then the proportion of the same to the Al layer increases to enhance the risk of the occurrence of the pinholes. Therefore, the Al layer portion corresponding to the portion adjacent to the Ti layer is eventually made relatively thin. When the thickness of the upper Al layer portion is thinner than that of the Al layer portion corresponding to the portion adjacent to the Ti layer in such a case, it is considered that (1): since the upper Al layer portion is susceptible to Si contained in the portion adjacent to the Ti layer, a risk, which leads to the generation of the pinholes, is easy to occur and (2): since the total thickness of the Al/Ti layered interconnection becomes thin, wiring resistance increases. In regard to determination about to which extent the concentration of Si in the Al layer portion adjacent to the Ti layer, i.e., the Si concentration capable of retarding the reaction between Ti and Al should be set, the Si concentration may be set to as low as possible in consideration of determination about to what extent the change in wiring resistance should be allowed. The Si concentration is not necessarily limited to this. Since it can be said that a resistance-change control effect is being substantially saturated when the Si concentration exceeds 0.8 per cent by weight, judging from the experimental examples described with reference to Fig. 11 (i.e., since the rate of change in resistance is approximately the same in the case of the standard in which the Si concentration is 0.8 per cent by weight and the standard in which the Si concentration is 2.0 per cent by weight), the Si concentration may be set to a concentration beyond 0.8 per cent by weight and as low as possible. US-A-5 355 020 shows to form on e.g. a Ti/TiN layer a layer of e.g. Al-1% Si and thereon a layer of e.g. pure Al. Accordingly, the invention is a method of forming an Al/Ti layered interconnection as claimed in claim 1. The invention of the present application and specific configurations of the invention will be understood from the following description. BRIEF DESCRIPTION OF THE DRAWINGS While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which: Fig. 1 is a view for describing a first embodiment and a cross-sectional view typically showing a structure of an Al/Ti layered interconnection; Figs. 2(A) and 2(B) are respectively views for describing a process for forming an Al layer in particular and are respectively views for explaining examples in which Al layers different in composition from each other are formed by one film-forming chamber and one target; Fig. 3 is a view showing a copy of a photograph obtained by observing the surface of a sample (Al/Ti layered interconnection) according to the present embodiment with a scanning electron microscope; Fig. 4 is a view for describing the first embodiment and a view for explaining the effect of controlling a sheet resistance of the Al/Ti layered interconnection shown in Fig. 1 to heat treatment; Fig. 5 is a process drawing (No. 1) for describing a second embodiment and is a view showing a method of forming a multilayer interconnection using a W (tungsten) plug; Fig. 6 is a process drawing (No. 2) subsequent to Fig. 5, for describing the second embodiment; Fig. 7 is a process drawing (No. 1) for describing a third embodiment and is a view showing a method of forming a multilayer interconnection using an A1 high-temperature sputtering process or Al high-temperature reflowing process; Fig. 8 is a process drawing (No. 2) subsequent to Fig. 7, for describing the third embodiment; Fig. 9 is a view for describing the relationship between the concentration of Si contained in an Al layer of an Al/Ti layered interconnection and the occurrence of pinholes therein; Fig. 10 is a view showing copies of surface SEM photographs at the time of the occurrence and non-occurrence of pinholes; and Fig. 11 is a view for describing the relationship between Si concentrations of Al layers in Al/Ti layered interconnections and the rate of change in sheet resistance after heat treatment of the Al/Ti layered interconnections. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments each illustrating an Al/Ti stacked or layered interconnection and the present invention of a forming method for an Al/Ti layered interconnection will hereinafter be described with reference to the accompanying drawings. Incidentally, the respective drawings used for their description schematically show the relationship between the dimensions, shapes and placement of elements of structure to the degree to which the present invention can be understood. Elements of structure similar to each other in the respective drawings are identified by the same reference numerals and the description of certain common elements will therefore be omitted. A first embodiment will first be described with reference to Figs. 1 through 4. Fig. 1 is a cross-sectional view typically showing the structure of an Al/Ti stacked or layered interconnection according to the first embodiment. In Fig. 1, reference numeral 11 indicates an arbitrary substrate or base on which the Al/Ti layered interconnection is formed. Reference numerals 13, 15, 15a, 15b and 17 respectively indicate a Ti layer, an Al layer, an Al layer portion adjacent to the Ti layer 13, an Al layer portion located on the side above the Al layer portion 15a, and the Al/Ti layered interconnection according to the present invention. The Al layer portion 15a adjacent to the Ti layer 13 is of a portion containing Si (silicon) in concentration capable of retarding the interface reaction between Ti and Al. The upper Al layer portion 15b is of a portion in which the concentration of Si is set to a concentration lower than a concentration allowing the upper Al layer portion 15b to produce pinholes even at the maximum (the concentration of Si may be zero). The sample, which has been described with reference to Fig. 1, can be formed as follows: Now consider an example in which a silicon substrate 11 having a BPSG (Boro-Phospho silicate glass) film (not shown) formed over the surface thereof is used as the base 11. (1) A Ti layer 13 having a thickness of 50nm, (2) an Al-0.8%Si-Cu layer containing 0.8 per cent Si by weight to Al, containing Cu (copper) and having a thickness of 50nm, (3) a Cu-Al layer containing Cu except for Si and having a thickness of 45nm are continuously formed over the BPSG film of the silicon substrate 1 by the sputtering process and without vacuum break of a film-forming chamber. An on-sputtering condition for forming the Ti layer 13 can be set to a condition under which a film-forming temperature (substrate heating temperature) is defined as suitable temperatures ranging from a room temperature to 300°C, the pressure applied to the film-forming chamber is defined as suitable pressures ranging from 1 mTorr to 6 mTorr and the power is defined as suitable powers ranging from 1 KW to 3 KW. An on-sputtering condition for forming the Al-0.8%Si-Cu layer and the Cu-Al layer can be set to a condition under which the film-forming temperature is defined as suitable temperatures ranging from the room temperature to 600°C, the pressure in the film-forming chamber is defined as suitable pressures ranging from 1 mTorr to 6 mTorr and the power is defined as suitable powers ranging from 8 KW to 12 KW. The following two methods may be mentioned by way of example as a method of continuously forming the Ti layer, Al-0.8%Si-Cu layer and Cu-Al layer under vacuum of the film-forming chamber. One method outside the invention is a method using a so-called multi-chamber type sputtering device having a plurality of film-forming chambers, which is capable of providing the transfer of a sample between the respective film-forming chambers under vacuum without the sample being exposed to the atmosphere. In this case, a target of Ti is placed in a certain chamber of the multi-chamber and a target having a composition of Al-0.8%Si-Cu is provided within another chamber. Further, a target having a composition of Al-Cu is placed in a further chamber. In this condition, the sample is shifted or transferred between these chambers so as to continuously execute respective film forming process steps. The other method in line with the invention is a method of devising a process for forming an Al layer in particular. Namely, the present method needs both a film-forming chamber for the Ti layer and a film-forming chamber for the Al layer but uses only one film-forming chamber as for the Al layer. This method will be described in detail with reference to Figs. 2(A) and 2(B). One film-forming chamber is used as the film-forming chamber for the formation of the Al layer. A target 23 containing no Si or containing Si in a concentration lower than a concentration required to allow the Al layer to generate pinholes even if Si is contained, is disposed within one film-forming chamber 21. In the present embodiment, the target 23 having the composition of Al-Cu, i.e., a target 23 composed of Al-Cu containing no Si or containing 0.3 per cent Si or less by weight for Al even if Si is contained, is placed within the film-forming chamber 21. Incidentally, reference numeral 25 in Fig. 2 indicates a wafer. In a first process for forming the Al-0.8%Si-Cu layer, for example, a mixed gas of Argon (Ar) and monosilane (SiH 4 ) is used as a sputter gas (see Fig. 2(A)). As an alternative to the monosilane, another silane gas, e.g., disilane (Si 2 H 6 ) may be used. When a gas obtained by mixing monosilane having a flow ratio of about one-tenth of Ar into Ar is used as the sputter gas to sputter an Al-Cu target, the Al-0.8%Si-Cu layer can be formed. In a second process for forming the Al-Cu layer, only Ar is used as the sputter gas exclusive of the monosilane (see Fig. 2(B)). In the sample formed in this way, the Al-0.8%Si-Cu layer is considered to substantially constitute the Al layer portion 15a adjacent to the Ti layer described in Fig. 1. Further, the Al-Cu layer is considered to form the upper Al layer portion 15b. An evaluation sample is formed in accordance with the above-described forming procedure, particularly, in a state in which the on-sputtering condition for forming the Ti layer 13 is set to a condition under which the film-forming temperature is defined as 100°C, the pressure applied to the film-forming chamber is defined as 3 mTorr and the power is defined as 1 KW, the on-sputtering condition for forming the Al-0.8%Si-Cu layer and the Cu-Al layer is set to a condition under which the film-forming temperature is defined as 250°C, the pressure in the film-forming chamber is defined as 2 mTorr and the power is defined as 9 KW. Next, the surface of the sample is observed and photographed by a scanning electron microscope (SEM) in an as-depo condition. A copy or trace of the resultant photograph is illustrated in Fig. 3. It is next determined whether or not pinholes appear in a region corresponding to an area of 525µm 2 in the photograph. However, the number of pinholes each larger than about 0.05µm in diameter is measured here. No pinholes were observed in this sample. Further, the rate of change in sheet resistance ΔR/R 0 is determined from a sheet resistance R0 of this sample at the time of as-depo and sheet resistances obtained by subjecting the sample to heat treatment for 30 minutes in an atmosphere of nitrogen at temperatures of about 410°C, 450°C and 500°C. The result of determination was shown in Fig. 4 together with comparative examples. Incidentally, the comparative example 1 shows an example in which the entire Al layer is of an Al-Cu layer, i.e., it shows a standard having an Al-Cu/Ti layered interconnection. The comparative example 2 shows an example in which the entire Al layer is of Al-0.8%Si-Cu, i.e., it shows a level or standard having an Al-0.8%Si-Cu/Ti layered interconnection. Conditions for forming samples employed in these comparative examples conform to those employed in the embodiment. It is understood that the sample employed in the embodiment is lower than one employed in the comparative example 1 in the rate of change in resistance. On the other hand, the sample employed in the comparative example 2 is lower in the rate of change in resistance than one employed in the embodiment but has produced pinholes (see Fig. 10(A)). It is understood from these that in such an Al/Ti layered interconnection, an increase in wiring resistance due to the reaction between Ti and Al can be reduced and the pinholes can be also prevented from occurring. A second embodiment will next be described. The second embodiment shows a case in which an Al/Ti layered interconnection and a forming method therefor are applied to a multilayer interconnection structure for a semiconductor device. In the present embodiment, a description will be made of an example in which the Al/Ti layered interconnection according to the present invention is applied to interconnections subsequent to a second layer interconnection. Further, a description will be made of an example in which throughholes defined in an intralayer insulating film are filled with a high melting-point metal plug such as a W (tungsten) plug and the interconnection according to the present invention is formed thereon. This description will be made with reference to Figs. 5 and 6. Figs. 5 and 6 are process drawings in which the manner of samples in major ones of processes for forming a multilayer interconnection is shown by cross-sectional views. An intermediate insulating film 33 is first formed over a silicon substrate 31 and a throughhole 33a is then defined in the intermediate insulating film 33. A first layer interconnection 35 composed of, for example, W (tungsten) is next formed over this sample. Next, an intralayer insulating film 37 is formed over the sample and a throughhole 37a is defined in the intralayer insulating film 37 (see Fig. 5(A)). A TiN layer 39 and a W layer are first formed over the sample with the throughhole 37a defined therein in this order. The W layer is formed thick to such an extent that it is possible to fill up the throughhole 37a. Further, the sample is etchbacked over its entire surface so that a W plug 41 is formed within the throughhole 37a (see Fig. 5(B)). A Ti layer 43, a first Al layer 45a containing Si (silicon) in a concentration capable of retarding the interface reaction between Ti and Al, and a second Al layer 45b whose Si concentration becomes a concentration lower than a concentration allowing the Al layer to produce pinholes even at the maximum, are all continuously deposited over the sample with the W plug 41 already formed therein, without breaking vacuum by the sputtering process. An on-sputtering condition for forming these layers 43, 45a and 45b can be set to the condition falling within the range described in the first embodiment. As a method of continuously forming these layers 43, 45a and 45b, either one of the two methods described in the first embodiment may be selected. Since the Ti layer has resistivity corresponding to ten times the resistivity of Al at this time, its wiring resistance increases when the thickness of the Ti layer is excessively thick and Ti does not produce a film when the thickness thereof is excessively thin. Therefore, the thickness of the Ti layer is set to about 50nm, for example. Since the thickness of the first Al layer 45a may be preferably determined as thin as possible assuming that it can retard the reaction between Ti and Al, the thickness thereof is set to about 50nm, for example. Further, the concentration of Si contained in the first Al layer 45a is set to, for example, 0.8 per cent by weight for Al. The thickness of the second Al layer 45b is set to thicknesses ranging from 450nm to 700nm in total inclusive of that of the first Al layer 45a. Described specifically, the thickness of the second Al layer 45b is selected so that a desired wiring resistance is obtained in consideration of the relationship between the width of each interconnection and the film thickness. Further, the concentration of Si contained in the second Al layer 45b is set to 0.3 per cent or less by weight for Al (the percent content of Si may be of course zero). Next, these layers 43, 45a and 45b are patterned to a second layer interconnection configuration and sintered to obtain a second layer interconnection 47 (see Fig. 6(A)). Incidentally, the order of the patterning and sintering may be reversed. Further, when it is desired to form third and later layer interconnections, an intralayer insulating film 49 corresponding to a second layer is deposited as shown in Fig. 6(B) and a throughhole 49a is thereafter defined in the intralayer insulating film 49. Afterwards, the processes described with reference to Figs. 5(B) through 6(B) are repeated. The second embodiment has described the case wherein the Al/Ti layered interconnection according to the present invention is applied to the second and later interconnections. This is because since Ti poses poor barrier to Al, an Al spike is produced when the Al/Ti layered interconnection is used in a state of being in direct contact with the silicon substrate 31 upon using the Al/Ti layered interconnection as the first layer interconnection, so that a leak failure may occur. However, if the Al/Ti layered interconnection 47 (see structure shown in Fig. 6(A)) according to the present invention is applied as the first layer interconnection 35 after the implantation of the W plug in the throughhole 33a of the intermediate insulating film 33 in the process described using Fig. 5(A), then the W plug can prevent the Al spike from occurring. Therefore, the Al/Ti layered interconnection according to the present invention can be also applied as the first layer interconnection. A third embodiment will next be described. The aforementioned second embodiment has described the case in which the W plug is used. However, a method called "Al high-temperature sputtering" (for example, a reference: IEEE VLSI Multilevel Interconnection Conference, 1990, p.42) and a method called "Al high-temperature reflowing" (e.g., a reference: IEEE VLSI Multilevel Interconnection Conference, 1991, p.326) are also known as a method of forming a multilayer interconnection structure. The Al/Ti layered interconnection can be applied even to these methods. The third embodiment will describe examples of these methods. This description will be made with reference to Figs. 7 and 8. Figs. 7 and 8 are respectively process drawings in which the manner of samples in major ones of processes for forming the multilayer interconnection is shown by cross-sectional views. In accordance with the procedure described in the second embodiment, an intermediate insulating film 33 is formed above a silicon substrate 11 and a throughhole 33a is defined in the intermediate insulating film 33. Further, a first layer interconnection 35 composed of W (tungsten), an intralayer insulating film 37 and a throughhole 37a are respectively formed over the intermediate insulating film 33. Next, a Ti layer 43 is formed above the sample by the sputtering process (see Fig. 7(A)). An on-sputtering condition for forming the Ti layer 43 can be set to the condition falling within the range described in the first embodiment. Next, a first Al layer 45a containing Si (silicon) in a concentration capable of retarding the interface reaction between Ti and Al, and a second Al layer 45b whose Si concentration becomes a concentration lower than a concentration allowing the Al layer to produce pinholes even at the maximum, are continuously deposited over the sample by the sputtering process without breaking vacuum. As a method of continuously forming these layers 45a and 45b, either one of the two methods described in the first embodiment may be selected. In regard to an on-sputtering condition for forming the first Al layer 45a and the second Al layer 45b, the film-forming temperature can be set to, for example, a temperature range from 450°C to 500°C if Al is allowed to reflow upon film formation (i.e., if the high-temperature sputtering process is executed) . Further, the pressure applied to a film-forming chamber can be set to suitable pressures ranging from 1 mTorr to 6 mTorr and the power can be set to suitable powers ranging from 8 KW to 12 KW. Thus, the inside of the throughhole 37a is filled with the first Al layer 45a and the second Al layer 45b. Further, an Al/Ti layered interconnection 47 is formed over the sample. In order to enhance a coating characteristic on the throughhole 37a, the film-forming temperature at the time of the formation of the first Al layer 45a may preferably be set to a low temperature of 150°C or less. Another method may be used to form the first Al layer 45a and the second Al layer 45b. Namely, a method (high-temperature reflowing process) may be used wherein the first Al layer 45a and the second Al layer 45b are deposited on each other in the neighborhood of room temperature and thereafter placed in an atmosphere of high temperatures ranging from 450°C to 500°C without vacuum break so as to produce reflow, thereby embedding the Al layers 45a and 45b in the throughhole 37a. The thicknesses and Si concentrations of the first Al layer 45a and second Al layer 45b can be set to the thicknesses and Si concentrations described in the second embodiment, for example. Further, when it is desired to form third and later layer interconnections, an intralayer insulating film 49 corresponding to a second layer is deposited as shown in Fig. 8 and a throughhole 49a is thereafter defined in the intralayer insulating film 49. Afterwards, the processes described using Fig. 7(A) through 8 are repeated. According to the methods described in the third embodiment, since the embedding of the throughhole and the formation of the Al/Ti layered interconnection can be simultaneously carried out, throughput can be improved as compared with the second embodiment. The embodiments each illustrative of the Al/Ti layered interconnection and the inventive forming method therefor have been described above. However, the present invention is not necessarily limited to the aforementioned embodiments. In the above description, the Al alloy including Cu has been mentioned as the Al layer. However, an Al layer composed of Al and Si may be substantially used. Alternatively, an Al layer containing one element selected from other elements other than Cu, e.g., Ti, Ni (nickel), Co (cobalt) and Cr (chromium) or a plurality of elements may be used as the Al layer. According to the Al/Ti layered interconnection shown in the above description, an Al layer contains Si (silicon) in a portion adjacent to a Ti layer in a concentration capable of retarding an interface reaction between Ti and Al. Further, the Al layer is formed such that the concentration of Si contained in a portion located on the side above the adjacent portion is set to a concentration lower than a concentration allowing the upper Al layer portion to produce pinholes even at the maximum. Therefore, an Al/Ti layered interconnection is obtained which has the Al layer of a structure wherein Si is contained by a needed amount only in the portion required to retard the reaction between Ti and Al and Si is not contained to the utmost in portions other than the above portion (inclusive of the case where no Si is contained therein). It is thus possible to realize an Al/Ti layered interconnection capable of retarding the reaction between Ti and Al and preventing the pinholes from occurring. According to the Al/Ti layered interconnection forming method of the present invention, an Al/Ti layered interconnection can be easily formed which is capable of retarding the reaction between Ti and Al and preventing pinholes from occurring. Thus, the present invention can be applied to interconnections for a more-micronized semiconductor device and its formation or the like and is defined in the claims.

Claims: A method of forming an Al/Ti layered interconnection, comprising: forming a Ti layer (13, 43) as a first interconnection layer on a substrate (11, 31); and forming an Al layer composed of Al or an Al alloy on the Ti layer (13, 43); wherein said Al layer is formed by a sputtering process under vacuum, characterized in that said step of forming the Al layer comprises a first step of forming an Al interface layer (15a, 45a) on said Ti layer (13, 43) by using as a sputter gas a mixed gas which is composed of an inert gas and a silane gas such that said interface layer (15a, 45a) has a silicon concentration of 0.8% or more by weight, and a second step of forming on said interface layer (15a, 45a) a second interconnection layer (15b, 45b) by using as a sputter gas an inert gas such that said second interconnection layer (15b, 45b) has a silicon concentration of 0.3% or less by weight, said first step and said second step being realized within the same film forming chamber. A method according to claim 1, wherein said first step and said second step are executed such that said second interconnection layer (15b, 45b) is formed with a thickness larger than that of said interface layer (15a, 45a). A method according to claim 1 or 2, wherein the substrate (11, 31) includes a BPSG layer. A method according to any of the preceding claims, wherein the formation of the Ti layer (13, 43) is realized by sputtering.

Inventors: HARADA YUSUKE, NARITA TADASHI, HARADA, YUSUKE, NARITA, TADASHI
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1997
Main classification: H01L23
IPC codes: H01L21, H01L23