Interpolation filter

Abstract: An interpolator for a discrete time signal is provided, which performs the steps of identifying a plurality of interpolation points which interpolation points are symmetrically temporarily displaced about a central reference point of a plurality of discrete time samples of a signal for which interpolated signal samples are to be calculated at the interpolation points, determining a plurality of impulse response coefficients appertaining to the interpolating function at each corresponding sampling time of the said plurality of signal samples, and contemporaneously calculating a plurality of interpolated discrete time signal samples corresponding to the interpolation points in combination with a pre-addition of at least one pair of discrete time signal samples.

Description: The present invention relates to digital signal processors which operate to interpolate discrete time signals. As is well known to those skilled in the art, interpolation is a process wherein a value of a function or signal is estimated at a particular point from values of the function or signal already known. In the context of digital signal processing, interpolation is used to increase a sample rate of a signal represented by discrete time signal samples. The discrete time signal samples representative of the signal are typically displaced in time at regular intervals in accordance with a sampling interval of the signal. The sampling interval, and therefore the sampling rate, are determined by the bandwidth of frequencies from which the signal is comprised as determined by Nyquist Sampling Theory well known to those skilled in the art. Therefore, to increase the sampling rate of the discrete time signal, the signal must be interpolated to provide signal samples at intermediate time displacements between the known signal samples. Known interpolators of discrete time signals embody Finite Impulse Response Filters, wherein known signal samples are fed to a shift register embodied therein and, in accordance with the values of the signal samples present in the shift register, an interpolation process is provided to generate interpolated signal samples at intermediate time displacements. Interpolated signal samples are calculated by convolving the discrete time signal samples held in the shift register with an impulse response representative of the interpolating function. A known technique for providing a reduction in complexity of such interpolating filters or indeed of any Finite Impulse Response (FIR) filter wherein the impulse response of the filter has a linear phase is known as 'pre-addition'. A characteristic of a linear phase impulse response is that coefficients of the impulse response have a symmetrical distribution about a centre or reference point. A pre-addition structure utilises the symmetry of the linear phase impulse response which is characterised in that each impulse response coefficient ai is equal to an impulse response coefficient in an equivalent temporal position about a centre or reference coefficient point. Thus for a linear phase impulse response ai = a -i . The pre-addition structure operates to provide a reduced complexity interpolator by summing pairs of discrete time signal samples held within the shift register of the FIR interpolator, before multiplication by impulse response coefficients wherein the pairs of signal samples correspond to symmetrical pairs of impulse response coefficients of the interpolator, or, in other words, where ai is equal to a -i. FIGURE 1 presents an illustrative example of a Finite Impulse Response interpolating filter, with a pre-addition structure. In Figure 1, a shift register 1' is shown to be comprised of eight stages 1, 2, 3, 4, 5, 6, 7, 8, fed with discrete time signal samples via a conductor 9. Also shown in Figure 1 is a set of lines 10, 11, 12, 13, 14, 15, 16, 17, each of which is representative of a discrete reference corresponding in time to the relative position of each of the stages 1, 2, 3, 4, 5, 6, 7, 8, of the shift register 1'. Each of the lines, 10, 11, 12, 13, 14, 15, 16, 17, is shown with a signal sample represented as xi where i represents the relative position in time of the impulse response of the filter with respect to a central or reference point x 0 . Also shown in Figure 1, is a conceptual line 18, representative of an interpolating function. The interpolating function 18, is shown to be symmetrical about the central or reference position y 0 , which corresponds to a temporal position of a interpolated signal sample to be calculated. As a result of the symmetry of the interpolating function 18, each of the coefficients representative of the impulse response of the interpolating function is symmetrical as aforementioned in that a 1 = a -1 , a 2 = a -2 and so forth such that ai = a -i . Connected to the shift register 1' is a plurality of summing amplifiers 19, 20, 21, 22 which operate to form a pre-addition of discrete time signal samples for corresponding coefficients of the impulse response of the interpolation function 18 which are symmetrical in that a i =a -i At an output of each of the summing amplifiers 19, 20, 21, 22 the pre-addition sum is subsequently scaled by corresponding composite coefficient a i of the interpolating function by a corresponding plurality of multipliers 23, 24, 25, 26. Each output from the multipliers 23, 24, 25, 26, is fed to a final summer 27, which operates to sum the respective outputs from the multipliers to produce the interpolated signal sample y 0 at a conductor 28. The pre-addition structure, as illustrated by the Finite Impulse Response interpolating filter shown in Figure 1, therefore provides a saving in the order of a factor of two in complexity, cost and time for interpolation. This saving is achieved by pre-adding each pair of discrete time signal samples x i associated with a corresponding pair of symmetrical impulse response coefficients a i and multiplying these pre-added samples by one of the pair of corresponding impulse response coefficients. The result of such multiplications for each pair of discrete time signal samples are thereafter summed to form an interpolated signal sample. An interpolating Finite Impulse Response filter, which is provided with a pre-addition structure as hereinbefore described, would have an advantage of a reduced complexity implementation. However, provision of a pre-addition structure is conditioned on the impulse response of the interpolating filter being a linear phase response and thereby possessing a necessary symmetry. Although an interpolation function of an interpolating filter may exhibit a linear phase, an impulse response representative of a sampled version of the interpolation function may not be symmetrical about an interpolation point of the function, corresponding to a temporal position of a interpolated sample, preventing the use of a pre-addition structure. It is an object of the present invention, as defined by the method according to claim 1 and the interpolating filter according to claim 11, to provide a reduced complexity interpolator. According to the present invention, there is provided a method of interpolating a discrete time signal comprising steps of; (i) identifying a plurality of interpolation points which interpolation points are substantially equally temporally displaced about a central reference point ( x 0 ) of a plurality of discrete time samples of ( x -4 to x 3 ) of a signal for which interpolated signal samples ( y 0 , y 1 ) are to be calculated at the said interpolation points; (ii) for each of the interpolation points, determining a plurality of impulse response coefficients ( a -4 to a 4 ) appertaining to an interpolating function at each corresponding sampling time of the said plurality of signal samples ( x -4 to x 3 ), and (iii) contemporaneously calculating the interpolated signal samples ( y 0 , y 1 ) corresponding to the interpolation points in combination with sum and difference operations of at least one pair of impulse response coefficients, and at least one pair of discrete time signal samples, wherein step (iii) of the said method comprises the steps of; (iv) forming first intermediate data α, in accordance with at least one summed pair of discrete time signal samples, in combination with at least one summed pair of corresponding impulse response coefficients; (v) forming second intermediate data β, in accordance with a difference between at least one pair of discrete time signal samples, in combination with a difference between at least one pair of corresponding impulse response coefficients, and (vi) calculating the interpolated signal samples in accordance with a sum of the first intermediate data α, and the second intermediate data β, and a difference between the first intermediate data α, and the second intermediate data β. By selecting a plurality of interpolating points, each of which is displaced in time by an equal amount from a central reference point, the calculation of interpolated signal samples corresponding to the interpolation points may be substantially reduced by utilising a relative symmetry of the impulse response coefficients associated with respective interpolation points. According to the invention there is also provided an interpolating filter for generating a plurality of interpolated signal samples ( y 0 , y 1 ) of a discrete time signal, comprises a shift register, which shift register serves to store samples ( x -4 to x 3 ) of the discrete time signal fed thereto, a plurality of switchable adder/subtractors connected to the said shift register, each of which said adder/subtractors operates in a first mode to add a pair of signal samples communicated from the shift register which pair of signal samples are substantially equally temporally displaced about a central reference point, and in a second mode to subtract the pair of signal samples from each other, and which adder/subtractors are switched between first and second modes in accordance with a control signal, a plurality of scaling means, each of which scaling means operates to scale signals communicated from an output of a respective one of the said adder/subtractors with data communicated from one of a plurality of controllable switches, the data fed from each controllable switch being either a sum of two interpolating coefficients in a first position of the said switch for scaling signals generated by the respective adder/subtractor when operating in the first mode, or a difference between the interpolating coefficients in a second position of the said switch for scaling signals generated by the respective adder/subtractor when operating in the second mode, which position of the switch is controlled in accordance with the said control signal, a summer connected to an output of each of the plurality of scaling means, which summer operates to sum scaled outputs from the said adder/subtractors, and an interpolating controller which operates to generate the control signal and the interpolated signal samples in accordance with the sum and difference operations on signals provided at an output of the summer. One embodiment of the present invention will now be described by way of example only, with reference to the accompanying drawings wherein; Figure 2 is a representation of two versions of an interpolation function with associated coefficients corresponding to two interpolating points for an odd order interpolator. FIGURE 3 is a representation of two versions of an interpolation function with associated coefficients corresponding to two interpolating points, for an even order interpolator, and FIGURE 4 is a schematic block diagram of an even order interpolating filter. A Finite Impulse Response Filter (FIR) which operates to convolve an impulse response of the filter with a discrete time signal may be an even order filter or an odd order filter. An even order filter comprises an impulse response with an even number of impulse response coefficients whereas an odd order filter embodies an impulse response with an odd number of impulse coefficients. An odd order impulse response is characterised by a fact that a discrete time sample will lie at a central point of the impulse response of the filter. An even order impulse response is characterised in that a sample does not lie at a central point of the impulse response of the filter. An illustrative representation of an interpolation function in continuous time form is shown in Figure 2. In Figure 2 two versions of the interpolating function are shown 29a, 29b, which correspond to a calculation of two interpolated signal samples y 0 y 1 . Also shown in Figure 2, are a plurality of discrete time sampling points represented by lines which are labelled with x -i where index i is in the range -3 to 3. In this case an interpolator for interpolating the signal sample is an odd order interpolator. At each of the discrete time sampling points x -3 , x -2 , x -1 , x 0 , x 1 , x 2 , x 3, a corresponding sample of the interpolating functions 29a, 29b is shown by impulse response coefficient ai where i is also in the range -3 to 3. The impulse response coefficients, a i form an impulse response corresponding to a discrete time representation of the interpolating function 29a, 29b which serve to form interpolated samples y 0 , y 1 . As a result of the fact that the interpolated sampling points y 0 y 1 are temporarily displaced with respect to the discrete time sample instant xo by an equal amount, the impulse response coefficient for each of the interpolating points y 1 ,y 0 are substantially the same, in that the coefficient a i where i is -3 to 3 are the same for a calculation of an interpolating sample at the interpolation point y 0 as they are for the interpolating point y 1 . The coefficients for calculation of respective interpolated samples y 0 y 1 are therefore symmetrical. It is this symmetry between calculation of interpolated samples that provides a saving in computation of the interpolated samples at points y 0 y 1 , in accordance with the following method. In the example shown in Figure 2, the interpolation point y 0 corresponds to a temporal position, which is a quarter of the sampling interval earlier than a current input signal sample position corresponding to x o . The interpolator point y 1 corresponds to a temporal position, which is a quarter of the sampling interval later than the current input signal sample corresponding to x o . The coefficients for the interpolation point are shown on the diagram as a i with i ∈ {-3...3}. Thus and, more generally for an odd order interpolator:- where the order of the filter is 2 k +1. Inspection of Figure 2 shows a form of symmetry between the coefficients of the interpolation point for early samples y 0 and that for the interpolation point for late samples y 1 . Thus we can see that and, more generally:- We may express the above as follows:- and Now form (1) wherein and (2) wherein a " i a i - a -i 2 . The interpolated signal samples corresponding to the sampling points y 0 , y 1 are thereafter calculated in accordance with the sum of α and β for y 0 , and a difference between α and β for y 1 as represented by equations (5) and (6). y 0 = α+β y 1 = α - β A representation of two versions of the interpolation function for calculation of two interpolated samples at positions y 0 y 1 for an even order impulse response is shown in Figure 3 where parts or elements also represented in Figure 2 bear identical numerical or alpha numeric designations. In Figure 3, the interpolating function 29a, 29b, are shown to be sampled in accordance with a plurality of discrete time sampling positions x i as for Figure 2, but unlike Figure 2, there are now eight sampling positions and correspondingly the impulse coefficients a i for each of these even number of sampling positions are adjusted in accordance with the temporal position of each of the discrete time sampling points x i where now ; is in the range -4 to +3. In this case we have for a filter of order 2 k ( k =3 in Figure 3). With a symmetry similar to that described earlier, we have We can express the above as:- and Now form where a' i = a i + a -(i+1) 2 where a" i = a i - a -( i +1) 2 Thus, as for the odd interpolator case, we have y 0 = α + β and y 1 = α - β where α and β are generated with only k multiplications each. Consider now a hardware (or software) implementation which uses the final expressions to generate α and β. For α we perform a pre-addition over the samples (for convenience, pre-adding the centre sample to itself) and multiply by the taps a' i , i ∈ {0... k }. Thus we perform k + I multiplications to form α. For β we perform a pre-subtraction over the samples (in this case the subtraction of the centre sample from itself gives zero so this term is ignored) and multiply the taps by a " i , i ∈ {1... k }. Thus we perform k multiplications to form β. In total we perform 2 k + 1 multiplications to generate α and β. Given α and β we can easily derive y 0 and y 1 since y 0 = α + β and y 1 = α - β. as hereinbefore explained. Thus we have generated both y 0 and y 1 by performing only 2 k +1 multiplications whereas in the ordinary implementation, they would require 2 k +1 multiplications each. Thus this approach leads to a halving of the number of multiplications. A corresponding implementation of a FIR interpolating filter for performing the interpolation of an even order impulse response is shown in Figure 4. The above approach for generating interpolated samples may be implemented in a variety of efficient hardware or software embodiments. Figure 4, shows the architecture for an 8th order ( k = 4) interpolator hardware embodiment of an interpolater which operates in accordance with the interpolation method hereinbefore described for an even order interpolater. In Figure 4 a discrete time signal is fed from a conductor 30, to a shift register 58, comprised of eight stages 31, 32, 33, 34, 35, 36, 37, 38. Also shown in Figure 4, are four controllable adder subtractors 39, 40, 41, 42. A first adder/subtractor 39, is connected to a first stage 31, and to the eighth stage 38, of the shift register 58. Adder subtractor 40, is connected to a second stage 32, and to the seventh stage 37, of the shift register 58, whereas the third adder subtractor 41, is connected to the third stage 33, and to the sixth stage 36, of the shift register 58. Finally, the fourth adder subtractor 42, is connected to the fourth stage 34, and to the fifth stage 35, of the shift register 58. An output of each of the four adder subtractors 39, 40, 41, 42, is respectively connected to an input of one of four multipliers 43, 44, 45 and 46. An output of each of the four multipliers 43, 44, 45, 46, is connected to an input of an adder 47. An output of the adder 47, is connected to one positive input of a first arithmetic unit 48. The output form the adder 47, is also connected to a negative input of a second arithmetic unit 49. The output from the adder 47 is also connected to an input of a latch 50. An output of the latch 50, is connected to a second positive input of the first arithmetic unit 48 and a second positive input of the second arithmetic unit 49. A clock input of the latch is connected to a master clock via a conductor 51, which is also connected to a clock input of a divide by two D-type flip-flop 56. A Q output of the D-type flip-flop is connected to a clock input of the shift register 58, and respectively to a control input of each of the adder subtractors 39, 40, 41, 42. The Q output from the D-type flip-flop is also connected to a control input of each of four switches 52, 53, 54, 55. An output from each of the switches 52, 53, 54, 55, is respectively connected to a second input of each of the multipliers 43, 44, 45, 46. In Figure 4, the shift register 58. clock in signals samples, x i , where i ∈{-4...3}. The master clock runs at twice the sample rate. The sample clock which drives the shift register 58, is derived from a version of the master clock, which is divided by two by the divide by 2 flip-flop 56, to produce a sample clock representative of the master clock, but with half the frequency. On the rising edge of the sample clock a new signal sample is shifted into the shift register. The four adder/subtractors 39,40,41,42, are arranged to output x i ± x -( i +1) depending on the state of the sample clock. An adder/subtractor adds its inputs together if configured to add (sample clock high) and subtracts the right hand input from the left hand input if configured to subtract (sample clock low). The rightmost adder/subtractor provides the output for i = 0 and the index increases from right to left. For each position, i, the output is multiplied by either a' i (if the adder/subtractor is adding) or a" i (if the adder/subtractor is subtracting). The choice of a' i or a" i is according to the state of the switches. During the interval between successive cycles of the sample clock, there are two phases of the operation of the master clock. During the first phase the sample clock is high and the circuit is arranged to compute the current value of α. The second phase begins with the next rising edge of the master clock. This clocks the value of α into the latch 57, and sets the sample clock low. In this state the circuit is arranged to compute the value of β. Once the computed value of β becomes valid (towards the end of the master clock cycle), the outputs of the adder and subtractor provide y 0 = α + β and y 1 = α - β respectively. Thus, in this implementation, the two outputs are generated contemporaneously. As will be appreciated by those skilled in the art various modifications may be made to the arrangement of the interpolating filter without departing from the scope of the invention as defined in the appended claims, in particular it may be appropriate to interpolate several values between the regular input samples. There may, nevertheless, remain a symmetry between the coefficients needed to generate half of a subset of these samples and the other half of that subset. The principles hereinbefore described may therefore be extended to this case by generating the same filtering operations to generate each suitable pair of interpolated values. Note, however, that a further saving is possible in this case because the required pre-addition and pre-subtraction operations are common to all required interpolated values. Thus these operations need only be performed once.

Claims: A method of interpolating a discrete time signal comprising steps of; (i) identifying a plurality of interpolation points which interpolation points are substantially equally temporally displaced about a central reference point ( x 0 ) of a plurality of discrete time samples of ( x -4 to x 3 ) of a signal for which interpolated signal samples ( y 0 , y 1 ) are to be calculated at the said interpolation points; (ii) for each of the interpolation points, determining a plurality of impulse response coefficients ( a -4 to a 4 ) appertaining to an interpolating function at each corresponding sampling time of the said plurality of signal samples ( x -4 to x 3 ), and (iii) contemporaneously calculating the interpolated signal samples ( y 0 , y 1 ) corresponding to the interpolation points in combination with sum and difference operations of at least one pair of impulse response coefficients, and at least one pair of discrete time signal samples, wherein step (iii) of the said method comprises the steps of; (iv) forming first intermediate data α, in accordance with at least one summed pair of discrete time signal samples, in combination with at least one summed pair of corresponding impulse response coefficients; (v) forming second intermediate data β, in accordance with a difference between at least one pair of discrete time signal samples, in combination with a difference between at least one pair of corresponding impulse response coefficients, and (vi) calculating the interpolated signal samples in accordance with a sum of the first intermediate data α, and the second intermediate data β, and a difference between the first intermediate data α, and the second intermediate data β. A method of interpolating a discrete time signal as claimed in claim 1, wherein the said plurality of impulse response co-efficients of the interpolation function determined in step (ii) of the said method, are substantially the same for each of the said interpolation points. A method of interpolating a discrete time signal as claimed in claim 1, wherein the interpolation points ( y 0 , y 1 ) are substantially equally temporally displaced about one ( x 0 ) of the plurality of discrete time samples ( x -4 to x 3 ). A method of interpolating a discrete time signal as claimed in claim 1, 2 or 3, wherein each signal sample of the said pair of at least one pair of signal samples in step (iv) of the said method for forming the first intermediate data α, is substantially equally temporally displaced with respect to the central reference point ( x 0 ), and the said at least one pair of impulse response coefficients are representative of samples of the interpolation function at temporal positions appertaining the temporal displacement of the said at least one pair of signal samples with respect to the central reference point ( x 0 ). A method of interpolating a discrete time signal as claimed in any of claims 1 to 4, wherein each signal sample of the said pair of at least one pair of signal samples in step (v) of the said method for forming the second intermediate data β, is substantially equally temporally displaced with respect to the central reference point ( x 0 ), and the said at least one pair of impulse response coefficients are representative of samples of the interpolation function at temporal positions appertaining the temporal displacement of the said at least one pair of signal samples with respect to the central reference point ( x 0 ). A method of interpolating a discrete time signal as claimed in any preceding claim, wherein each of the said pairs of signal samples in step (iv) of the said method for forming the first intermediate data α, are substantially equal to the said pairs of signal samples in step (v) of the said method for forming the second intermediate data β. A method of interpolating a discrete time signal as claimed in any preceding claim, wherein each of the said pairs of impulse response coefficients in step (iv) of the said method for forming the first intermediate data α, are substantially the same as the said pairs of impulse response coefficients in step (v) of the said method for forming the second intermediate data β. A method of interpolating a discrete time signal as claimed in Claim 7, wherein the plurality of discrete time signal samples is an odd number of signal samples represented as 2 k + 1, where k is an integer, and step (iv) of the said method for forming the first intermediate data α, is calculated in accordance with equation (1) as follows; wherein and where a i represents the i-th impulse response coefficient of the interpolation function, and x i represents the i-th signal sample, and step (v) of the said method for forming the second intermediate data β, is calculated in accordance with equation (2) as follows: wherein a " i = a i - a - i 2 . A method of interpolating a discrete time signal as claimed in claim 7, wherein the plurality of discrete time signal samples is an even number of signal samples represented as 2 k , where k is an integer, and step (iv) of the said method for forming the first intermediate data α, is calculated in accordance with equation (3) as follows; for where a ' i = a i + a -( i +1) 2 and where a i represents the i-th impulse response coefficient of the interpolation function, and x i represents the i-th signal sample, and step (v) of the said method for forming the second intermediate data β, is calculated in accordance with equation (4) as follows; where a " i = a i - a -( i +1) 2 . A method of interpolating a discrete time signal as claimed in claims 8 or 9, wherein the plurality of interpolation poins are two interpolation points, designated y 0 and y 1 , and wherein y 0 = α + β and y 1 = α- β An interpolating filter for generating a plurality of interpolated signal samples ( y 0 , y 1 ) of a discrete time signal, comprises a shift register (58), which shift register (58) serves to store samples ( x -4 to x 3 ) of the discrete time signal fed thereto, a plurality of switchable adder/subtractors (39 to 42) connected to the said shift register (58), each of which said adder/subtractors (39 to 42) operates in a first mode to add a pair of signal samples communicated from the shift register which pair of signal samples are substantially equally temporally displaced about a central reference point, and in a second mode to subtract the pair of signal samples from each other, and which adder/subtractors (39 to 42) are switched between first and second modes in accordance with a control signal, a plurality of scaling means (43 to 46), each of which scaling means (43 to 46) operates to scale signals communicated from an output of a respective one of the said adder/subtractors (39 to 42) with data communicated from one of a plurality of controllable switches (52 to 55), the data fed from each controllable switch (52 to 55) being either a sum of two interpolating coefficients in a first position of the said switch for scaling signals generated by the respective adder/subtractor when operating in the first mode, or a difference between the interpolating coefficients in a second position of the said switch for scaling signals generated by the respective adder/subtractor when operating in the second mode, which position of the switch (52 to 55) is controlled in accordance with the said control signal, a summer (47) connected to an output of each of the plurality of scaling means (43 to 46), which summer (47) operates to sum scaled outputs from the said adder/subtractors (29 to 42), and an interpolating controller (56) which operates to generate the control signal and the interpolated signal samples in accordance with the sum and difference operations on signals provided at an output of the summer.

Inventors: HULBERT ANTHONY PETER, HULBERT, ANTHONY PETER
Applicants: ROKE MANOR RESEARCH, ROKE MANOR RESEARCH LIMITED
Application year: 1997
Main classification: H03H17
IPC codes: H03H17