Drive apparatus for self light-emitting display

Abstract: A drive apparatus for a self light-emitting display unit accomplishes pseudo intermediate tone display and pseudo outline compensation while maintaining a high image quality. In executing dithering-based pseudo intermediate tone display and pseudo outline compensation data conversion on pixel data corresponding to the individual pixels of the self light-emitting display unit, dither coefficients to be added to the individual pieces of pixel data are changed field by field in this dithering process. Furthermore, the pseudo outline compensation data conversion performed is associated with each dither coefficient added in the dithering process.

Description: The present invention relates to a drive apparatus for a self light-emitting display. To realize a gradation display on a plasma display panel as a self light-emitting display unit, there is a known method which divides the display period of one frame (field) into N subframes (subfields) to permit light emission only for the time corresponding to the weight on each bit position of N-bit display data (so-called subfield method). When pixel data consists of eight bits, for example, the display period of one frame is divided into eight subframes SF8, SF7, SF6, ..., and SF1 in the order of a heavier weight to a lighter one. At this time, light emissions of 128 pulses, 64 pulses, 32 pulses, 16 pulses, 8 pulses, 4 pulses, 2 pulses and 1 pulse are carried out in the respective subframes SF8 to SF1. The light emissions in those eight subframes provide 256-gradation display. Because of the fixed display order for the subframes SF8-SF1, this gradation display scheme however has such a problem that a moire-like false outline which looks like a gradation-lost image is observed near the area on a flat image where the gradation level crosses the boundary of 2 n gradation levels, such as 128 or 64, which significantly degrades the display quality. A gradation display scheme which solves this problem has been proposed in, for example, Japanese Patent Kokai (laying open) No. Hei 7-271325. This gradation display scheme suppresses a pseudo outline by equally dividing a subframe with a heavy weight into a plurality of subframes, separating them so as to prepare a plurality of light emission patterns which have the equal light emission time (the equal number of light emissions) with different light emission orders of the subframes, and changing the light emission pattern from one to another pixel by pixel (pseudo outline compensation data conversion). This gradation display scheme however results in an increased number of subframes in one frame period. If the number of bits of pixel data is increased to improve the image quality, the number of subframes in one frame period is increased more. The increase in the number of subframes in one frame period increases the addressing period for lighting a plasma display panel for light emission. This relatively shortens the sustain period as the light emission period, reducing the maximum luminescent. In this respect, a dithering process which reduces the number of bits (the number of subframes) of pixel data and effects pseudo intermediate tone display is performed. The dithering process expresses a single intermediate display level with a plurality of adjacent pixels. In the case where 8-bit equivalent gradation display is demonstrated using the upper six bits of pixel data in 8-bit pixel data, for example, four dither coefficients different from one another are respectively assigned to and added to pixel data corresponding to the individual pixels in each set of four pixels adjoining right and left and up and down are added to pixel data. Fig. 1 is a diagram illustrating the correlation between dither coefficients "a" to "d" to be added to pixel data by this dithering process, and the individual pixels. For example, the dither coefficient "a" is added to pixel data corresponding to the pixel at the first row and the first column, the dither coefficient "b" is added to pixel data corresponding to the pixel at the first row and the second column, the dither coefficient "c" is added to pixel data corresponding to the pixel at the second row and the first column, and the dither coefficient "d" is added to pixel data corresponding to the pixel at the second row and the second column. Those dither coefficients "a" to "d" are respectively added to the pixel data of the individual pixels in each set of four pixels adjoining right and left and up and down are added to pixel data, as indicated by the broken lines in Fig. 1. Then, the upper six bits of the dither-coefficients added pixel data are extracted to be used as a drive signal for the display panel. This dithering process generates a combination of four different intermediate display levels with four pixels, thus ensuring four times the 6-bit gradation display levels or 8-bit equivalent intermediate tone display. If the dither pattern consisting of the dither coefficients "a"-"d" is always added to the individual pixels as indicated by the broken lines in Fig. 1, however, noise originating from this dither pattern may appear, thus degrading the image quality. Accordingly, it is an objective of the present invention to provide a drive apparatus for a self light-emitting display unit, which can accomplish pseudo intermediate tone display and pseudo outline compensation while maintaining a high image quality. To achieve this object, a drive apparatus for a self light-emitting display unit for displaying a video signal as sequentially displayed fields, the display unit, according to this invention, comprises an A/D converter for sampling the video signal to convert the video signal to pixel data corresponding to individual pixels of the self light-emitting display unit; a dithering circuit for supplying dithered pixel data, obtained by processing the higher order bits of each of dither-added pixel data obtained by adding a different one of a plurality of different dither coefficients to the pixel data of a corresponding plurality of adjacent pixels on a screen of the self light-emitting display unit; a pseudo outline compensation data converter for converting said dithered pixel data based on a first conversion table and a second conversion table to yield pseudo outline compensation pixel data; and drive means for driving individual pixels of the self light-emitting display unit for light emission based on the pseudo outline compensation pixel data, said pseudo outline compensation data converter selects either said first conversion table or said second conversion table in accordance with a dither coefficient added by said dithering circuit, and converts said dithered pixel data based on said selected conversion table, and wherein a different one of the dithering coefficients is added to the pixel data of a respective pixel for each of the sequentially displayed fields. Fig. 1 is a diagram showing the states of dither coefficients to be added to associated pixels; Fig. 2 is a diagram schematically illustrating the structure of a plasma display equipped with a drive apparatus according to this invention; Fig. 3 is a diagram showing positions of individual pixels on a screen; Figs. 4A through 4H are diagrams illustrating signal waveforms for the internal operation of an image data processor 3 in the first field; Figs. 5A through 5H are diagrams illustrating signal waveforms for the internal operation of the image data processor 3 in the second field; Figs. 6A through 6H are diagrams illustrating signal waveforms for the internal operation of the image data processor 3 in the third field; Figs. 7A through 7H are diagrams illustrating signal waveforms for the internal operation of the image data processor 3 in the fourth field; Fig. 8 is a diagram showing the internal structure of a dithering circuit 31; Fig. 9 is a diagram showing the internal structure of a pseudo outline compensation data converter 32; Fig. 10 is a diagram exemplifying first and second mode conversion tables in the pseudo outline compensation data converter 32; Fig. 11 is a diagram further exemplifying first and second mode conversion tables in the pseudo outline compensation data converter 32; Fig. 12 is a diagram showing a light emission period format in terms of subframes; Figs. 13A through 13D are diagrams exemplifying pseudo outline compensation pixel data generated by the image data processor 3 and illustrating the association of this pixel data with the individual pixels according to this invention; Figs. 14A through 14D are diagrams for explaining the operation at the time flickering occurs; Fig. 15 is a diagram exemplifying the light emission state when flickering occurs; Fig. 16 is a diagram exemplifying the light emission state according to this invention; and Figs. 17A through 17D are diagrams showing another example of pseudo outline compensation pixel data generated by the image data processor 3 and illustrating the association of this pixel data with the individual pixels according to this invention. A preferred embodiment of the present invention will now be described with reference to Figs. 2 through 17D. Fig. 2 is a diagram illustrating the schematic structure of a plasma display equipped with a drive apparatus according to this invention. In Fig. 2, an A/D converter 1 samples an input video signal in accordance with a first clock signal CK1 of a frequency fs, supplied from a control circuit 2, to acquire N-bit pixel data D for each pixel and sequentially sends the pixel data D to an image data processor 3. The image data processor 3 comprises a dithering circuit 31 for executing data processing in accordance with a second clock signal CK2 of a frequency 2· fs, horizontal and vertical sync signals and a select signal, supplied from the control circuit 2, and a pseudo outline compensation data converter 32. Those dithering circuit 31 and pseudo outline compensation data converter 32 carry out processing (which will be discussed later) on the pixel data D to reduce the number of bits of pixel data to thereby accomplish pseudo intermediate tone display. The dithering circuit 31 and the pseudo outline compensation data converter 32 generate pseudo-outline compensated pixel data and supply the data to a frame memory 4. The frame memory 4 sequentially writes the pixel data, sent from the image data processor 3, at every timing of the second clock signal CK2 from the control circuit 2. Further, the frame memory 4 reads the written pixel data at the timing of the second clock signal CK2 and sends it as pixel drive data to a column electrode driver 6. The control circuit 2 generates the aforementioned first clock signal CK1 and second clock signal CK2. The control circuit 2 also generates a select signal which repeats the state of a logic value "1" and the state of a logic value "0" for each period of the first clock signal CK1, and sends this select signal to the pseudo outline compensation data converter 32. Further, the control circuit 2 extracts horizontal and vertical sync signals from the input video signal and supplies those signals to the dithering circuit 31. The control circuit 2 further generates a reset timing signal, a scan timing signal, a sustain timing signal and an erase timing signal according to the horizontal and vertical sync signals, and supplies those timing signals to a row electrode driver 5. In accordance with those various timing signals, the row electrode driver 5 generates a reset pulse for initializing the amount of residual charges, a scan pulse for writing pixel data, a sustain pulse for sustaining the discharge light emission state and an erase pulse for stopping discharge light emission, and applies those pulses to pairs of row electrodes 20 1 to 20 n of a PDP (Plasma Display Panel) 10. At this time, the scan pulse is sequentially applied to the pairs of row electrodes from 20 1 to 20 n . The column electrode driver 6 separates one frame of pixel drive data read from the frame memory 4 for each of bits with the same weight, generates a pixel data pulse having a voltage value corresponding to a logic value "1" or "0" of that bit, and applies the pulse to column electrodes 30 1 to 30 m of the PDP 10. When the scan pulse is applied to the PDP 10 from the row electrode driver 5 while the pixel data pulse from the column electrode driver 6 is applied, a charge corresponding to the applied pixel data pulse is written in the PDP 10. At this time, light emission occurs at the intersection of a column electrode applied with the pixel data pulse corresponding to, for example, logic "1" and a row electrode pair applied with the scan pulse. Each such intersection is equivalent to each of pixels G 11 to G nm on the screen of the PDP 10 as shown in Fig. 3. When the sustain pulse is applied by the row electrode driver 5 thereafter, the light emission state is maintained for the time corresponding to the number of the sustain pulses applied. A viewer would visually sense the luminescence corresponding to the time for sustaining the light emission state. The operation of the image data processor 3 will now be discussed with reference to the signal waveforms for the internal operation illustrated in Figs. 4A-4H through Figs. 7A-7H. Fig. 8 shows the internal structure of the dithering circuit 31 in the image data processor 3. Referring to Fig. 8, N-bit pixel data D for each pixel corresponding to a video signal is sequentially supplied to an adder 320 for each first clock signal CK1. This video signal is what has been produced by skipped scanning. Therefore, pixel data corresponding to an odd row of pixels in the entire pixels of the PDP 10 shown in Fig. 3 are supplied first, and then pixel data corresponding to an even row of pixels are supplied. As shown in Fig. 4B, for example, after pixel data D 11 -D 1m respectively corresponding to the first row of pixels G 11 -G 1m in Fig. 3 are supplied, pixel data D 31 -D 3m respectively corresponding to the next odd row or the third row of pixels G 31 -G 3m are supplied. Likewise, pixel data corresponding to odd rows are sequentially supplied (first field). When pixel data D n1 -D nm respectively corresponding to the last odd row of pixels G n1 -G nm are supplied in the first field, pixel data D 21 -D 2m respectively corresponding to the first even row of pixels G 21 -G 2m are supplied after which pixel data corresponding to other even rows are sequentially supplied (second field), as shown in Fig. 5B. When pixel data D (n-1)1 -D nm respectively corresponding to the last even row are supplied in the second field, pixel data corresponding to odd rows are supplied again (third field) after which pixel data corresponding to even rows are supplied (fourth field). In the first field as shown in Figs. 4C and 4D, a dither coefficients generator 310 repeatedly generates a dither coefficient a, dither coefficient "c", dither coefficient "b" and dither coefficient "d" in circulation for each second clock signal CK2, and supplies those dither coefficients to the adder 320. In the next second field and the subsequent third field, as shown in Figs. 5C and 5D and Figs. 6C and 6D, the dither generator 310 repeatedly generates the dither coefficient "d", dither coefficient "b", dither coefficient "c" and dither coefficient "a" in turn, and supplies those dither coefficients to the adder 320. In the fourth field, as shown in Figs. 7C and 7D, the dither generator 310 repeatedly generates the dither coefficient "a", dither coefficient "c", dither coefficient "b" and dither coefficient "d" in circulation for each second clock signal CK2, and supplies those dither coefficients to the adder 320. The dither coefficients generator 310 repeatedly executes the aforementioned operations in the first field to the fourth field. That is, when completing the operation for generating the dither coefficients in the fourth field, the dither generator 310 returns to the operation for the first field and repeats the aforementioned operations thereafter. The adder 320 adds the aforementioned dither coefficients to the pixel data D sequentially supplied from the A/D converter 1 one by one as shown in Figs. 4E, 5E, 6E and 7E, and sends the resultant dither-added pixel data to an upper-bit extractor 330. In other words, two different dither coefficients are added to a pixel data to newly generate two pieces of dither-added pixel data. The upper-bit extractor 330 extracts upper M bits of data of such dither-added pixel data and supplies the data as dithered pixel data Z to the pseudo outline compensation data converter 32 at the subsequent stage. Fig. 9 shows the internal structure of the pseudo outline compensation data converter 32. In Fig. 9, a first converter 321 converts the dithered pixel data Z consisting of, for example, six bits supplied from the dithering circuit 31 to 8-bit pixel data based on a first mode conversion table as shown in Fig. 10 or 11, and supplies the converted data as pseudo outline compensation pixel data AZ to a selector 322. Meanwhile, a second converter 323 converts the dithered pixel data Z consisting of, for example, six bits supplied from the dithering circuit 31 to 8-bit pixel data based on a second mode conversion table as shown in Fig. 10 or 11, and supplies the converted data as pseudo outline compensation pixel data BZ to the selector 322. The logic value "0" of each bit in the pseudo outline compensation pixel data AZ (BZ) shown in Fig. 10 or 11 designates no light emission while the logic value "1" designates light emission. The light emission period in one frame period accords to the light emission format in Fig. 12. For example, bit 7 of the pseudo outline compensation pixel data AZ corresponds to light emission in the subframe SF4 in Fig. 12, and when its logic value is "1", light emission is carried out for the period of "8". Bit 6 corresponds to light emission in the subframe SF6 1 , and when its logic value is "1", light emission is carried out for the period of "16". Bit 5 corresponds to light emission in the subframe SF2, and when its logic value is "1", light emission is carried out for the period of "2". Bit 4 corresponds to light emission in the subframe SF5 1 , and when its logic value is "1", light emission is carried out for the period of "8". Bit 3 corresponds to light emission in the subframe SF3, and when its logic value is "1", light emission is carried out for the period of "4". Bit 2 corresponds to light emission in the subframe SF1, and when its logic value is "1", light emission is carried out for the period of "1". Bit 1 corresponds to light emission in the subframe SF6 2 , and when its logic value is "1", light emission is carried out for the period of "16". Further, bit 0 corresponds to light emission in the subframe SF5 2 , and when its logic value is "1", light emission is carried out for the period of "8". The sum of the light emission periods in those SF1-SF6 is equivalent to the luminance level. At this time, the subframe SF6 (equivalent to the light emission period of "32") which has a heavy weight is separated into the subframes SF6 1 and SF6 2 each specifying the light emission period of "16" and both arranged apart from each other. Further, the subframe SF5 (equivalent to the light emission period of "16") which also has a heavy weight is separated into the subframes SF5 1 and SF5 2 each specifying the light emission period of "8" and both arranged apart from each other. Two conversion patterns that have different light emission positions in subframes in one frame, whose total light emission periods are the same and whose light emission periods are equal to one another, are prepared in the first and second mode conversion tables to suppress a pseudo outline. With regard to the pseudo outline compensation pixel data AZ equivalent to the luminance level 16 in Figs. 10 and 11, for example, light emission for the period of "8" is carried out at the positions of the subframes SF4 and SF5 1 shown in Fig. 12, while for the pseudo outline compensation pixel data BZ equivalent to the luminance level 16, light emission for the period of "8" is carried out at the positions of the subframes SF5 1 and SF5 2 . Even with the same luminance level, a pseudo outline can be suppressed by shifting the position of light emission in one frame period in the aforementioned manner. Data conversions by the first converter 321 and the second converter 323 are executed in synchronism with the second clock signal CK2. The selector 322 selects one of the pseudo outline compensation pixel data AZ supplied from the first converter 321 and the pseudo outline compensation pixel data BZ supplied from the second converter 323 which accords to the logic value of a select signal, and sends out the selected one. When the logic value of the select signal is "0" in Figs. 4H, 5H, 6H and 7H, the selector 322 selects the pseudo outline compensation pixel data AZ supplied from the first converter 321 and sends it out. When the logic value of the select signal is "1", on the other hand, the selector 322 selects the pseudo outline compensation pixel data BZ supplied from the second converter 323 and sends it out. The image data processor 3, as shown in Figs. 4H, 5H, 6H and 7H, performs two different pixel data processes on a single piece of image-processed pixel data which have undergone the dithering process and pseudo outline compensation, and generate interpolated pixel data corresponding to another field different from the field for the supplied pixel data. In odd fields like the first and third fields, the above-described pixel data processing is executed based on the supplied pixel data corresponding to the odd fields, thereby generating interpolated pixel data corresponding to even fields. In even fields like the second and fourth fields, the above-described pixel data processing is executed based on the supplied pixel data corresponding to the even fields, thereby generating interpolated pixel data corresponding to odd fields. In the first field as shown in Figs. 4A through 4H, for example, two different dithering processes and pseudo outline compensations are performed on the pixel data D 11 at the first row and the first column to generate pseudo outline compensation pixel data AZ(D 11 +a) as image-processed pixel data corresponding to the pixel at the first row and the first column and generate pseudo outline compensation pixel data BZ(D 11 +c) as interpolated pixel data corresponding to the pixel at the second row and the first column. Further, two different dithering processes and pseudo outline compensations are performed on the pixel data D 12 at the first row and the second column to generate pseudo outline compensation pixel data BZ(D 12 +b) as image-processed pixel data corresponding to the pixel at the first row and the second column and generate pseudo outline compensation pixel data AZ(D 12 +d) as interpolated pixel data corresponding to the pixel at the second row and the second column. Those image-processed pixel data and interpolated pixel data are sequentially written in the frame memory 4 in association with each of the first row to the n-th row of the screen of the PDP 10 as shown in Fig. 3. When pixel data of up to the n-th row or one frame of pixel data of one screen is written in the frame memory 4, the written pixel data is sequentially read from the frame memory 4 from the one associated with the first row and is supplied as pixel drive data to the column electrode driver 6. The operation in the first field as shown in Figs. 4A-4H causes light emission on the pixel G 11 at the first row and the first column based on the pseudo outline compensation pixel data AZ(D 11 +a), light emission on the pixel G 12 at the first row and the second column based on the pseudo outline compensation pixel data BZ(D 12 +b), light emission on the pixel G 21 at the second row and the first column based on the pseudo outline compensation pixel data BZ(D 11 +c), and light emission on the pixel G 22 at the second row and the second column based on the pseudo outline compensation pixel data AZ(D 12 +d) as shown in, for example, Fig. 13A. In the second field as shown in Figs. 5A through 5H, based on the pixel data D 21 at the second row and the first column, the image data processor 3 then generates pseudo outline compensation pixel data AZ(D 21 +d) as image-processed pixel data corresponding to this pixel at the second row and the first column, and generates pseudo outline compensation pixel data BZ(D 21 +b) as interpolated pixel data corresponding to the pixel at the first row and the first column. Based on the pixel data D 22 at the second row and the second column, the image data processor 3 generates pseudo outline compensation pixel data BZ(D 22 +c) as image-processed pixel data corresponding to this pixel at the second row and the second column, and generates pseudo outline compensation pixel data AZ(D 22 +a) as interpolated pixel data corresponding to the pixel at the first row and the second column. Those image-processed pixel data and interpolated pixel data are sequentially written in the frame memory 4 in association with each of the first row to the n-th row of the screen of the PDP 10 as shown in Fig. 3. When pixel data of up to the n-th row or one frame of pixel data of one screen is written in the frame memory 4, the written pixel data is sequentially read from the frame memory 4 from the one associated with the first row and is supplied as pixel drive data to the column electrode driver 6. The operation in the second field as shown in Figs. 5A-5H causes light emission on the pixel G 11 at the first row and the first column based on the pseudo outline compensation pixel data BZ(D 21 +b), light emission on the pixel G 12 at the first row and the second column based on the pseudo outline compensation pixel data AZ(D 22 +a), light emission on the pixel G 21 at the second row and the first column based on the pseudo outline compensation pixel data AZ(D 21 +d), and light emission on the pixel G 22 at the second row and the second column based on the pseudo outline compensation pixel data BZ(D 22 +c) as shown in, for example, Fig. 13B. In the third field as shown in Figs. 6A through 6H, based on the pixel data D 11 at the first row and the first column, the image data processor 3 then generates pseudo outline compensation pixel data AZ(D 11 +d) as image-processed pixel data corresponding to this pixel at the first row and the first column, and generates pseudo outline compensation pixel data BZ(D 11 +b) as interpolated pixel data corresponding to the pixel at the second row and the first column. Based on the pixel data D 12 at the first row and the second column, the image data processor 3 generates pseudo outline compensation pixel data BZ(D 12 +c) as image-processed pixel data corresponding to this pixel at the first row and the second column, and generates pseudo outline compensation pixel data AZ(D 12 +a) as interpolated pixel data corresponding to the pixel at the second row and the second column. Those image-processed pixel data and interpolated pixel data are sequentially written in the frame memory 4 in association with each of the first row to the n-th row of the screen of the PDP 10 as shown in Fig. 3. When pixel data of up to the n-th row or one frame of pixel data of one screen is written in the frame memory 4, the written pixel data is sequentially read from the frame memory 4 from the one associated with the first row and is supplied as pixel drive data to the column electrode driver 6. The operation in the third field as shown in Figs. 6A-6H causes light emission on the pixel G 11 at the first row and the first column based on the pseudo outline compensation pixel data AZ(D 11 +d), light emission on the pixel G 12 at the first row and the second column based on the pseudo outline compensation pixel data BZ(D 12 +c), light emission on the pixel G 21 at the second row and the first column based on the pseudo outline compensation pixel data BZ(D 11 +b), and light emission on the pixel G 22 at the second row and the second column based on the pseudo outline compensation pixel data AZ(D 12 +a) as shown in, for example, Fig. 13C. In the fourth field as shown in Figs. 7A through 7H, based on the pixel data D 21 at the second row and the first column, the image data processor 3 then generates pseudo outline compensation pixel data AZ(D 21 +a) as image-processed pixel data corresponding to this pixel at the second row and the first column, and generates pseudo outline compensation pixel data BZ(D 21 +c) as interpolated pixel data corresponding to the pixel at the first row and the first column. Based on the pixel data D 22 at the second row and the second column, the image data processor 3 generates pseudo outline compensation pixel data BZ(D 22 +b) as image-processed pixel data corresponding to this pixel at the second row and the second column, and generates pseudo outline compensation pixel data AZ(D 22 +d) as interpolated pixel data corresponding to the pixel at the first row and the second column. Those image-processed pixel data and interpolated pixel data are sequentially written in the frame memory 4 in association with each of the first row to the n-th row of the screen of the PDP 10 as shown in Fig. 3. When pixel data of up to the n-th row or one frame of pixel data of one screen is written in the frame memory 4, the written pixel data is sequentially read from the frame memory 4 from the one associated with the first row and is supplied as pixel drive data to the column electrode driver 6. The operation in the fourth field as shown in Figs. 7A-7H causes light emission on the pixel G 11 at the first row and the first column based on the pseudo outline compensation pixel data BZ(D 21 +c), light emission on the pixel G 12 at the first row and the second column based on the pseudo outline compensation pixel data AZ(D 22 +d), light emission on the pixel G 21 at the second row and the first column based on the pseudo outline compensation pixel data AZ(D 21 +a), and light emission on the pixel G 22 at the second row and the second column based on the pseudo outline compensation pixel data BZ(D 22 +b) as shown in, for example, Fig. 13D. As discussed above, the drive apparatus for a self light-emitting display unit according to this invention changes the dither coefficients to be added to pixel data corresponding to the individual pixels, field by field, as shown in Figs. 13A-13D. As shown in Figs. 13A-13D, for example, the dither coefficient to be added to the pixel data D 11 corresponding to the pixel G 11 is changed field by field as follows: First field: dither coefficient "a" Second field: dither coefficient "b" Third field: dither coefficient "d" Fourth field: dither coefficient "c" As the dither coefficients to be added are changed field by field in this manner, the noise of the dither pattern is suppressed by the integration effect. Further, the dither coefficients to be added are associated with the converting operation by the pseudo outline compensation data converter 32 in this invention. In Figs. 13A-13D, for example, when the dither coefficient a or the dither coefficient d is added to pixel data D by the dithering circuit 31, the pseudo outline compensation data converter 32 performs conversion based on the first mode conversion table and sends out pseudo outline compensation pixel data AZ. When the dither coefficient b or the dither coefficient c is added to the pixel data D, on the other hand, the pseudo outline compensation data converter 32 performs conversion based on the second mode conversion table and sends out pseudo outline compensation pixel data BZ. Such conversion is executed to prevent the occurrence of flickering which would occur when the dither coefficients to be added are changed field by field. In other words, at the time the dither coefficients to be added are changed field by field as shown in Figs. 13A-13D, light emitting states between fields do not become uniform, causing flickering, unless the dither coefficients to be added are associated with the converting operation by the pseudo outline compensation data converter 32. Suppose that, as shown in Figs. 14A-14D, the value of the dithered pixel data Z obtained by adding the dither coefficient "a" to the pixel data D becomes "16" and the value of the dithered pixel data Z obtained by adding any one of the other dither coefficients "b"-"d" to the pixel data D becomes "15" over the first to fourth fields. In this case, the values of the dithered pixel data Z at the pixel G 11 in the first field, the pixel G 12 in the second field, the pixel G 22 in the third field and the pixel G 21 in the fourth field become "16". The value "16" of the dithered pixel data Z is converted in the first and third fields using the first mode conversion table shown in Fig. 10 and is converted in the second and fourth fields using the second mode conversion table. As a result, the following pseudo outline compensation pixel data are acquired. First field: {10010000} Second field: {00010001} Third field: {10010000} Fourth field: {00010001} Fig. 15 is a diagram showing the light emission state which occurs based on such pseudo outline compensation pixel data. In Fig. 15, the shaded portions indicate the light emission state and blank portions indicate the non-light emission state. As apparent from Fig. 15, the non-light emission state continues between the first field and the second field, and the light emission state continues between the second field and the third field. When the light emission state between fields do not become uniform, flickering may occur. According to this invention, such flickering is prevented by associating the dither coefficients to be added with the converting operation by the pseudo outline compensation data converter 32. When the dither coefficient a is to be added as shown in Figs. 13A-13D, for example, the pseudo outline compensation data converter 32 carries out conversion in any of the first to fourth fields by using the first mode conversion table. In any of the first to fourth fields at this time, therefore, pseudo outline compensation pixel data {10010000} is obtained. Fig. 16 is a diagram exemplifying the light emission state which occurs based on this pseudo outline compensation pixel data. Since the light emission state between fields become uniform as shown in Fig. 16 according to this invention, the aforementioned flickering does not occur. Although the dithering circuit 31 in the above-described embodiment changes the dither coefficients to be added field by field as shown in Figs. 13A-13D, this circuit is not limited to this particular structure. For example, the dithering circuit 31 may be designed to alter the dither coefficients "a"-"d" field by field as shown in Figs. 17A-17D. In the modification illustrated in Figs. 17A-17D, the pseudo outline compensation data converter 32 should perform pseudo outline compensation data conversion in association with the dither coefficients added by the dithering circuit 31 in order to prevent the aforementioned flickering. As apparent from the foregoing description, the drive apparatus according to this invention changes dither coefficients to be added to the individual pieces of pixel data, field by field, at the time of executing dithering-based pseudo intermediate tone display and pseudo outline compensation'data conversion on pixel data corresponding to the individual pixels of a self light-emitting display unit. Further, the pseudo outline compensation data conversion is performed in association with the dither coefficients added in the dithering process. Therefore, this invention can accomplish pseudo intermediate tone display and pseudo outline compensation while preventing noise from being generated by a dither pattern and maintaining a high image quality.

Claims: A self light-emitting display unit for displaying a video signal as sequentially displayed fields, the display unit comprising: an A/D converter for sampling the video signal to convert said video signal to pixel data corresponding to individual pixels of said self light-emitting display unit; a dithering circuit for supplying dithered pixel data obtained by processing the higher order bits of each of dither-added pixel data obtained by adding a different one of a plurality of different dither coefficients to said pixel data of a corresponding plurality of adjacent pixels on a screen of said self light-emitting display unit; a pseudo outline compensation data converter for converting said dithered pixel data based on a first conversion table and a second conversion table to yield pseudo outline compensation pixel data; and drive means for driving individual pixels of said self light-emitting display unit for light emission based on said pseudo outline compensation pixel data, wherein said pseudo outline compensation data converter selects either said first conversion table or said second conversion table in accordance with a dither coefficient added by said dithering circuit, and converts said dithered pixel data based on said selected conversion table, and wherein a different one of the dithering coefficients is added to the pixel data of a respective pixel for each of of the sequentially displayed fields. The drive apparatus according to claim 1, wherein said drive means divides one field into a plurality of subfields having light emission periods corresponding to individual bit positions of pixel drive data, further divides a subfield corresponding to a bit position with a heavy weight into a plurality of subfields, and causes pixels of said self light-emitting display unit to emit light only in those subfields associated with said pixel drive data; and each of said first and second conversion tables converts a bit pattern of said pseudo outline compensation pixel data in such a manner that light emission positions in subfields having an equal light emission period become different from one another. The drive apparatus according to claim 1 or 2, wherein said dithering circuit respectively adds a first dither coefficient, a second dither coefficient, a third dither coefficient and a fourth dither coefficient to four pixel data respectively corresponding to four adjoining pixels on said screen of said self light-emitting display unit, in a first field, and adds said coefficients to different ones of said four adjoining pixels in a subsequent field.

Inventors: SHIGETA TETSUYA, SHIGETA, TETSUYA
Applicants: PIONEER ELECTRONIC CORP, PIONEER ELECTRONIC CORPORATION
Application year: 1997
Main classification: G09G3
IPC codes: G09G3, H04N5