Oscillation circuit, electronic circuit using the same, and semiconductor device, electronic equipment, and timepiece using the same

Abstract: This invention relates to a crystal oscillation circuit that oscillates stably with a low power consumption. This crystal oscillation circuit comprises an inverting amplifier, a crystal oscillator, and a feedback circuit that inverts the phase of an output from this inverting amplifier and feeds it back as an input. The sum of the absolute value of the threshold voltage of a first semiconductor switching element and the absolute value of the threshold voltage of a second semiconductor switching element is set to be greater than or equal to the absolute value of the potential difference between first and second potentials, when said inverting amplifier includes the first and second semiconductor switching elements.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to an oscillation circuit, an electronic circuit using that oscillation circuit, and a semiconductor device, electronic equipment, and timepiece using that oscillation circuit or electronic circuit. Description of the Related Art Oscillation circuits that use crystal oscillators are widely employed in the art in devices such as portable timepieces, portable telephones, and computer terminals. It is necessary to design such portable items of electronic equipment in such a manner that they are economical in their power consumption and have longer battery lives. This crystal oscillation circuit comprises an inverting amplifier and a feedback circuit that is provided with a crystal oscillator. The inverting amplifier comprises a pair of transistors where the gate of each of these transistors is used as an input side and the drain thereof is used as an output side, by way of example. In this case, the drain sides of these two transistors are connected together and the source sides thereof are connected to ground and a power voltage side, respectively. If the power voltage is applied to the inverting amplifier in the crystal oscillation circuit of this configuration, the phase of the output of the inverting amplifier is inverted through 180 degrees and the thus inverted signal is fed back to the gate of each transistor as an input. The transistors configuring the inverting amplifier are turned on and off alternately by the operation of this feedback, the oscillation output of the crystal oscillation circuit gradually increases, and thus the oscillator starts to oscillate stably. However, the absolute value of a voltage V reg applied to the inverting amplifier in this prior-art crystal oscillation circuit is set to be greater than the total of the absolute values of the threshold voltages V TP and V TN of the transistors in this circuit, as follows: |V reg | > |V TP | + |V TN | This is the cause of a short-circuiting current I s that flows from the high potential side to the low potential side within the inverting amplifier, which causes a problem when trying to reduce the power consumption of the entire circuit. US-A-4,459,565 discloses a low current electronic oscillator and tries to avoid this short-circuiting current by adding particular bias circuits designed to bias the transistors of the inverting amplifier in such a way as to avoid that they are both on at the same time. This solution requires additional circuitry, however. US-A-3,887,881 discloses an oscillator circuit employing a low voltage CMOS amplifier designed in such a way that the voltage required to operate the amplifier need only be greater than the threshold voltage of each amplifying transistor instead of greater than the combined threshold voltages of both amplifying transistors. The supply voltage for this low voltage amplifier is reduced compared to the supply voltage of prior art amplifiers by adding particular bias circuits for biasing the two transistors of the amplifier. In a similar way US-A-4,352,073, US-A-4,405,906 and US-A-4,095,195 disclose amplifiers for use in oscillator circuits, where different bias voltages are supplied to the amplifying transistors connected in series between supply voltage terminals in order to reduce power consumption. While all of these circuits may reduce the power consumption, they require additional circuit elements that make these amplifiers more expensive and larger when they are formed as an integrated circuit. SUMMARY OF THE INVENTION An objective of this invention is to reduce the above short-circuiting current that flows through the inverting amplifier and thus provide an oscillation circuit that can oscillate with a low power consumption, an electronic circuit that uses such an oscillation circuit, and a semiconductor device, electronic equipment, and timepiece that use this oscillation circuit or electronic circuit. This object is achieved with an oscillation circuit as claimed in claim 1. Preferred embodiments of the invention are subject-matter of the dependent claims. With the oscillation circuit of claim 1 it is possible to limit the short-circuiting current flowing through the inverting amplifier, making it possible to provide an oscillation circuit that can oscillate with a low power consumption. In the embodiment according to claim 2, when a voltage is applied to the inverting amplifier in the crystal oscillation circuit, excitation of the crystal oscillator starts. The phase of the output of the inverting amplifier is inverted by the feedback circuit and is fed back as an input. The operations of inverting, amplifying, and outputting this feedback input signal by the inverting amplifier are repeated. During this time, the first and second semiconductor switching elements that configure the inverting amplifier are driven to be turned on and off at mutually different timings by this feedback input, to excite the crystal oscillator. As stated above, the sum of the absolute values of the threshold voltages of the first and second semiconductor switching elements are set to be greater than or equal to the absolute value of the power voltage of the inverting amplifier. This prevents the first and second semiconductor switching elements from being driven to turn on simultaneously when the circuit is operating, and, as a result, the short-circuiting current flowing through the inverting amplifier can be greatly reduced, making it possible to reduce the power consumption. In particular, by forming the first and second transistors in such a manner that the threshold voltage conditions are satisfied, there is no further need for means for dealing with this short-circuiting current, making it unnecessary to use special circuit components for counteracting this short-circuiting current. This makes it possible to reduce the power consumption of the crystal oscillation circuit without adversely affecting the degree of integration of the entire circuit. Note that it is necessary to set each of the absolute values of the threshold voltages of these first and second semiconductor switching elements to be less than the absolute value of the power voltage of the inverting amplifier. According to a second aspect of this invention, there is provided an electronic circuit comprising the above oscillation circuit of this invention. Similarly, according to a third aspect of this invention, there is provided a semiconductor device comprising one of the above oscillation circuit and the electronic circuit of this invention. Furthermore, according to a fourth aspect of this invention, there is provided electronic equipment comprising one of the above oscillation circuit and the electronic circuit of this invention. This can reduce the power consumption of an item of portable electronic equipment, such as a portable telephone or computer terminal, and thus makes it possible to reduce the consumption thereof of power from an internal battery or secondary battery. Finally, according to a fifth aspect of this invention, there is provided a timepiece comprising one of the above oscillation circuit and the electronic circuit of this invention. This makes it possible to implement a portable timepiece that has a low power consumption, which enables the design of a timepiece that is itself smaller and uses an even smaller battery. Alternatively, the battery life thereof could be extended even when a battery of the same capacity is used. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a first embodiment of the crystal oscillation circuit in accordance with this invention; Fig. 2 is a timing chart of a prior-art circuit; Fig. 3 is a timing chart of the circuit of Fig. 1; Fig. 4 is a illustrative drawing of the relationship between the threshold voltages, the power source potential, and the ground potential of the prior-art circuit; Fig. 5 is a illustrative drawing of the relationship between the threshold voltages, the power source potential, and the ground potential of the first embodiment; and Fig. 6 is a graph of the V GS -I D characteristic of an enhancement-mode transistor; DESCRIPTION OF PREFERRED EMBODIMENTS Preferred embodiments of this invention will be described below with reference to the accompanying drawings. A crystal oscillation circuit relating to an embodiment of this invention is shown in Fig. 1. The crystal oscillation circuit of this embodiment is one that is used in a quartz wristwatch. This crystal oscillation circuit comprises an inverting amplifier 30 and a feedback circuit. This feedback circuit comprises a crystal oscillator 10, a resistor 14, and phase-compensation capacitors 16 and 18. It inverts the phase of an output V D(t) of the inverting amplifier 30 by 180 degrees and inputs the inverted signal as a gate signal V G(t) to the gate of the inverting amplifier 30 as feedback. The configuration of the inverting amplifier 30 is such that it is connected between a first potential side and a second potential side that is at a lower potential, and it is powered by the potential difference between these two potentials. In this particular case, the first potential is set to the ground potential V DD and the second potential is set to a negative power source potential V reg that is supplied from a power supplying circuit section 60. The inverting amplifier 30 comprises a first circuit 40 and a second circuit 50. The first circuit 40 comprises a p-type field-effect transistor 42 that functions as a first semiconductor switching element. The source of this transistor 42 is connected to ground, the drain thereof is connected to an output terminal 79 side, and the feedback signal V G(t) is applied to the gate thereof. The second circuit 50 comprises an n-type field-effect transistor 52 that functions as a second semiconductor switching element. The source of this transistor 52 is connected to the power source terminal side of the power supplying circuit section 60, the drain thereof is connected to the output terminal 79 side (in this case, it is actually connected to the drain of the transistor 42), and the feedback signal V G(t) is applied to the gate thereof. A transistor that is both a p-type as well as an enhancement-mode field-effect transistor is used as the transistor 42, and a transistor that is both an n-type as well as an enhancement-mode field-effect transistor is used as the transistor 52. The values of the threshold voltage V TP of the transistor 42 and the threshold voltage V TN of the transistor 52 are such that the total absolute value thereof is greater than or equal to the absolute value of the power voltage applied to the inverting amplifier 30 (in this embodiment, the power voltage is V reg , which is the potential difference between the ground potential and the power source potential, because the ground potential V DD is set to zero), as given by the following equation: |V reg | ≤ |V TP | + |V TN | In addition, the absolute values of the threshold voltages of the transistors 42 and 52 are each set to be less than the absolute value of the power voltage, as follows: |V reg | > |V TP | |V reg | > |V TN | This ensures that the short-circuiting current that flows through the inverting amplifier 30 of the crystal oscillation circuit of this embodiment is greatly reduced, making it possible to reduce the power consumption thereof. The reasons for this are discussed below. A timing chart of a prior-art crystal oscillation circuit is shown in Fig. 2 and a timing chart of the crystal oscillation circuit of this embodiment is shown in Fig. 3. In each of these figures, the elapsed time from the application of the power voltage V reg from the power supplying circuit section 60 is plotted along the horizontal axis, with the feedback input V G(t) to the inverting amplifier 30 and the on/off state of the transistors 42 and 52 being plotted along the vertical axis. As previously mentioned, the threshold voltages of the two transistors that configure the inverting amplifier of the prior-art crystal oscillation circuit are set in such a manner that the above Equation (1) is satisfied. The relationships between the threshold voltages of these transistors, the ground potential V DD , and the power source potential V reg in this case are shown graphically in Fig. 4. In other words, if the value of the feedback input V G(t) to the inverting amplifier is set to within the following range with respect to the potentials of the threshold voltages V TP and V TN : V TP > V G(t) > V TN both transistors are turned on and a short-circuiting period is established thereby. Therefore, while these transistors are being turned on and off alternately by the feedback signal V G(t) , a time during which both of the transistors are driven to be on occurs periodically, as shown in Fig. 2, so that a short-circuiting current flows from the high potential (V DD ) to the low potential (V reg ) side, which is an impediment to any reduction in the power consumption. In contrast thereto, the threshold voltages of the transistors 42 and 52 in this embodiment are set in such a manner that the above Equations (2) and (3) are satisfied. The relationships between the threshold voltages, the ground potential V DD , and the power source potential V reg in this case are shown in Fig. 5. That is to say, if the value of the feedback input V G(t) to the inverting amplifier 30 is set to be within the following range with respect to the potentials of the threshold voltages V TP and V TN : V TN > V G(t) > V TP the two transistors 42 and 52 are turned firmly off so that there is no common-on time during which both of the transistors 42 and 52 are on, as there is in the prior art. In other words, as shown in Fig. 3, while the transistors 42 and 52 are being driven on and off alternately by the feedback signal V G(t) , there is no period of time during which both of the transistors 42 and 52 are on, so that the short-circuiting current that causes problems in the prior art is greatly reduced and thus the power consumption of the crystal oscillation circuit can be reduced. In particular, this method of countering the short-circuiting current of the inverting amplifier 30 of this embodiment can be implemented without increasing the number of circuit components. Furthermore, the absolute values of the threshold voltages of the transistors 42 and 52 of this embodiment are each set to be less than the absolute value of the power voltage V reg , as shown by Equations (3). This makes it possible to implement a reduced power consumption while maintaining a stable oscillation of the crystal oscillation circuit. In other words, the absolute value of the amplitude of the feedback signal V G(t) of the inverting amplifier 30 in the crystal oscillation circuit does not exceed the absolute value of the power voltage V reg of the inverting amplifier. This means that the transistors 42 and 52 can be driven to turn on and off alternately in a stable manner by setting the absolute values of the threshold voltages of the transistors 42 and 52 to satisfy Equations (3). Experiments performed by the present inventors have verified that a satisfactory oscillation state can be maintained and the power consumption can be reduced when an oscillation circuit is driven by a power voltage V reg of an absolute value of 0.9 volts, even when the sum of the absolute values of the threshold voltages of the transistors 42 and 52 varies within the following range: 1.4 volts > |V TP | + |V TN | > 0.9 volts In addition, the off-leakage currents of the transistors 42 and 52 in this embodiment are reduced, for reasons that will be described below, making it possible to further reduce the power consumption of the entire circuit. A characteristic graph of the relationship between the drain current I D of an enhancement-mode transistor and the voltage V GS between the gate and source thereof is shown in Fig. 6. It can be seen from this graph that the I D -V GS characteristic curve of an enhancement-mode transistor shifts towards the left and the off-leakage current thereof increases, as shown by the broken lines in the figure, as the threshold voltage is made lower (in this graph, the transistor turns off when V GS is equal to or less than the threshold voltage V TH , but at this region, the current I D is yet to flow through the transistor as the off-leakage current, as shown by the broken lines in the figure). Therefore, if the threshold voltages of the transistors 42 and 52 are set to be low, as in the prior-art oscillation circuit, the off-leakage current at and below the threshold voltage is larger, and the power consumption is increased by that amount. In contrast thereto, since the threshold voltages of the transistors 42 and 52 in this embodiment are set to large values, as shown by Equation (2), the values of the off-leakage currents that flow through the transistors 42 and 52 are greatly reduced, and thus the power consumption of the entire circuit can be reduced. It should be noted that this invention is not limited to the above described embodiment, and it can be modified in various different ways within the range of the invention. For example, the description of the above embodiment is based on a configuration in which each of the first and second circuits 40 and 50 had a single transistor, by way of example, but other configurations could be devised in which other circuit elements could be incorporated into the circuits if necessary, without causing any loss of function of the first and second circuits 40 and 50. In addition, it is preferable that a semiconductor device is fabricated to comprise the crystal oscillation circuit of the above embodiments, or an electronic circuit that comprises such a crystal oscillation circuit, and this semiconductor device could be mounted in portable electronic equipment that has a restricted power source capacity, such as a portable telephone, a portable computer terminal, or any other type of portable equipment.

Claims: An oscillation circuit comprising: an inverting amplifier (30) including a first semiconductor switching element (42) and a second semiconductor switching element (52); characterized in that the sum of the absolute value of the threshold voltage (V TP ) of said first semiconductor switching element (42) and the absolute value of the threshold voltage (V TN ) of said second semiconductor switching element (52) is set to be greater than or equal to the absolute value of the power voltage (Vreg) of said inverting amplifier (30), such that said first and second semiconductor switching elements (42, 52) are prevented from being on simultaneously to limit a short-circuiting current flowing through said inverting amplifier. The oscillation circuit as defined in claim 1, comprising a feedback circuit having a crystal oscillator (10) connected between the output and input sides of said inverting amplifier (30), for causing the phase of the output signal from said inverting amplifier (30) to invert and feeding the thus inverted signal back to said inverting amplifier as an input signal; wherein said inverting amplifier comprises a first circuit including said first semiconductor switching element (42), and a second circuit including said second semiconductor switching element (52); wherein said first semiconductor switching element (42) is connected to the side of a first potential (V DD ) and is driven to be turned on and off by said feedback input signal, to excite said crystal oscillator; wherein said second semiconductor switching element (52) is connected to the side of a second potential (V reg ) that differs from said first potential and is driven to be turned on and off by said feedback input signal at a timing that differs from that of said first semiconductor switching element (42), to excite said crystal oscillator. The oscillation circuit as defined in claims 1 or 2, wherein said first and second semiconductor switching elements (42, 52) are configured by using field-effect transistor elements of differing conductivity types. An electronic circuit comprising the oscillation circuit as defined in any one of claims 1 to 3. A semiconductor device comprising one of the oscillation circuit as defined in any one of claims 1 to 3, and the electronic circuit of claim 4. Electronic equipment comprising one of the oscillation circuit as defined in any one of claims 1 to 3, and the electronic circuit of claim 4. A timepiece comprising one of the oscillation circuit as defined in any one of claims 1 to 3, and the electronic circuit of claim 4.

Inventors: KADOWAKI TADAO, MAKIUCHI YOSHIKI, NAKAMIYA SHINJI, YABE HIROSHI, KADOWAKI, TADAO, MAKIUCHI, YOSHIKI, NAKAMIYA, SHINJI, YABE, HIROSHI
Applicants: SEIKO EPSON CORP, SEIKO EPSON CORPORATION
Application year: 1997
Main classification: G04F5
IPC codes: H03K3, H02H9, G04G19, G04F5