PNP lateral bipolar electronic device and corresponding manufacturing process

Abstract: The invention relates to a process for making a lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other bipolar devices of the NPN type, said device being incorporated to an electrically insulated multilayer structure and comprising: the semiconductor substrate, doped with impurities of the P type; a first buried layer, doped with impurities of the N type to form a base region; a second layer (13), overlying the first and having conductivity of the N type, to form an active area; opposite collector (12) and emitter (14) regions being formed in said active area and separated by a base channel region; characterized in that the width of the base channel is defined essentially by a contact opening (18) formed above an oxide layer (11) protecting the base channel. Advantageously, the opening (18) is formed by shifting an emitter mask.

Description: Field of the Invention This invention relates to a PNP bipolar electronic device. In particular, the invention relates to a lateral PNP bipolar electronic device which is integrated monolithically on a semiconductor substrate together with other bipolar devices of the NPN type; said device being incorporated into an electrically insulated multilayer structure which comprises: the semiconductor substrate, doped with impurities of the P type; a first buried layer, doped with impurities of the N type to provide a base region; a second layer, overlying the first and having conductivity of the N type, to provide an active area; collector and emitter regions being formed in said active area in opposite locations separated by a base channel region. Background Art As is well known, preference is given to NPN transistors for implementing integrated circuitry of the bipolar type on semiconductor substrates, on account of their direct and alternate current amplifications being definitely better than those of PNP transistors. Another disadvantage of PNP bipolar transistors is their close limitations in high frequency applications. Despite all this, the inclusion of both NPN and PNP transistors on a common semiconductor substrate is still a necessity where suitable bias circuits, current mirror circuits and/or load devices for gain stages are to be provided. The formation of PNP transistors on a semiconductor substrate is effected concurrently with that of NPN transistors, without any additional implanting or masking steps. It is for this reason that it has become common practice to form PNP bipolar transistors of the so-called lateral type such that they can be compatible with the process flows adopted to fabricate NPN bipolar devices. In this respect, Figure 1 shows an enlarged cross-sectional view, taken on a vertical plane, of a lateral PNP device 6 formed on a P-doped semiconductor substrate 1. The following are successively deposited onto this substrate 1: a first buried layer 2 doped N+ to form the base region of the transistor, and a second layer 3, doped N, which constitutes the active area of the PNP device to be. Thereafter, a selective diffusion of P-type dopants is effected in the active area 3 to define a central emitter region 4 surrounded by two opposite collector regions 5. This solution has been widely used heretofore, to the point that a text, "Design and Realization of Bipolar Transistors", Peter Ashburn, page 157, gives it as the principal configuration for a lateral PNP device that can ensure of a good current gain. It should be noted that such lateral PNP transistors have an intrinsic current loss of about 3% compared to collector current; these currents can also be explained theoretically by having reference to the diagram in Figure 2 of an equivalent electric circuit of a lateral PNP transistor. It can be seen in this figure that the lateral PNP device, designated Q 1 in the equivalent circuit, is connected to a pair of parasitic PNP transistors Q 2 and Q 3 having their emitter regions connected to the emitter and collector regions, respectively, of the transistor Q 1 . In addition, these parasitic devices Q 2 and Q 3 have their collector regions connected to the semiconductor substrate, and their base regions in common with the base of Q 1 . This equivalent electric diagram shows that the parasitic currents are mainly attributable to the second parasitic device Q 2 draining toward the substrate some of the current being injected by the emitter of Q 1 , thereby lowering the efficiency of lateral emission. Similar considerations apply to the third parasitic device Q 3 , which contributes instead to lowering the collection efficiency of the collector of Q 1 when the latter is biased into its saturation range. To overcome drawbacks of this kind, tied to the parasitic currents, a conventional solution has been that of optimizing the efficiency of collection of the carriers in the collector region, so as to maximize the gain of lateral transistors. For this reason, lateral PNP transistors have been implemented conventionally with their emitter region occupying, in the active area, a central position surrounded by two collector regions. While being in many ways advantageous, this prior solution has a serious drawback in that it leads to increased values of certain characteristic parameters of the lateral PNP device, such as the base-collector and emitter-base capacitances, C bc and C eb , which restrict performance at high frequencies. This drawback is also connected with the considerable spread of the base region in the buried layer brought about by the need to control the lateral PNP device performance in the emitter and collector regions. Especially the width W b of this base region adversely affects the carrying parameter B*, which is tied to W b by the following formula: B * ≈ 1 - W b 2 2 D τ where D is the diffusion value, and τ is the re-combination time of the carriers. It should be noted that the B* factor is inversely proportional to the passage time through the base region, so that as it increases, the frequency performance of the lateral PNP device deteriorates. Unfortunately, this type of lateral PNP device reveals serious limitations when attempts are made to improve its high frequency performance. These limitations come from the practical impossibility of bringing the collector regions closer to the central emitter region. This is both attributable to the photolithographic masks used for transferring the patterns of the active region, and to side diffusion effects during the formation of the emitter and collector regions, as well as to breakdown effects which may occur in the region between the base and the collector. Consequently, the width W b of the base region of the lateral PNP transistors always exhibits values between 2 µm and 4 µm. This invention is directed to reduce substantially the width of the base channel. In fact, a reduction in the base channel width would ensure an improved value of the carrying factor B*. Figure 3 is a vertical cross-section view, to an enlarged scale, of a conventional lateral PNP transistor, highlighting polysilicon contacts 10 above the emitter 4 and collector 5 regions. These contacts 10 are characterized by the presence of so-called "bird's beaks" which jut out sideways from the emitter and collector regions. The possibility of altering the width Wb of the base channel is usually hindered by the bird's beak protrusions. In fact, calling W PPL the distance between the emitter and the collector, L BB the reach of the bird's beak, and D the misalignment between the polysilicon contact layer 10 and the active area, then: W B > W PPL + 2*L BB + 2*D And substituting for the real values of such distances, we get: W B > 1.0 + 2*0.5 + 2*0.4 = 2.8 µm W B > 1.0 + 2*0.5 + 2*0.15 = 2.3 µm. Thus, the heaviest restriction on the reduction of the base channel width appears to be due to the process implementation, rather than to its topography. From Figure 4, showing a schematic detail view of Figure 3, it is evinced that the bird's beak partly overlaps the active area and that the window through which the implantation of BF 2 is effected is reduced accordingly. This results in the creation of a P + _N junction within the polysilicon layer deposited, which keeps the base and collector currents far from the ideal. In the light of the foregoing considerations, the technical problem underlying this invention is to provide a new topography conferring, on a lateral PNP device, such structural and functional features as to make it suitable for high frequency applications as well, thereby overcoming the aforesaid limitations and drawbacks. Summary of the Invention The solution idea behind this invention is to define the width of the base channel by way of the emitter structure. Based on this solution idea, the technical problem is solved by an electronic device as previously indicated and defined in Claim 1. The technical problem is also solved by a process as defined in Claim 4. The features and advantages of the inventive device will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings. Brief Description of the Drawings In the drawings: Figure 1 is an enlarged-scale sectional view taken on a vertical plane of a lateral PNP device integrated on a semiconductor substrate, according to the prior art; Figure 2 shows schematically an equivalent electric circuit of a lateral PNP device integrated on a semiconductor substrate, according to the prior art; Figure 3 is an enlarged-scale sectional detail view, taken on a vertical plane, of a lateral PNP device integrated on a semiconductor substrate, according to the prior art; Figure 4 is an enlarged detail view of Figure 3; Figures 5 to 7 are vertical cross-section and time succession views, respectively showing schematically a portion of the semiconductor substrate whereon a lateral PNP device according to the invention is formed; Figures 8 to 10 are schematic vertical cross-section and time succession views, respectively showing schematically a portion of the semiconductor substrate whereon a lateral NPN device is formed. Detailed Description Referring to Figure 5, a preferred embodiment of a lateral PNP device 15, monolithically integrated on a semiconductor substrate together with other NPN devices, shown in Figures 8-10, will now be described. The device 15 can be operated even at high frequencies. A multilayer structure, electrically isolated from any other integrated devices by the selective growing of isolation oxide regions 11, has been formed on a P-doped semiconductor substrate. This multilayer structure is produced by successive deposition, onto the substrate, of a first buried layer doped for conductivity of the N type to form a base region, and of a second epitaxial layer 13 with conductivity of the N - type representing an active area of the lateral PNP device 15. The fabrication process includes the definition of an emitter region 14 and a collector region 12. For the purpose, a first step of selectively diffusing P-type dopants onto the surface of the active area is carried out. At the end of this operation, the emitter region 14 will locate peripherally of the active area, opposite from the collector region 12. At this point, a polysilicon layer 16 is deposited onto the substrate surface and capped with a protective layer 17 of VAPOX oxide. This layer 17 can be formed by oxidation of the polysilicon 16. By a subsequent dry etching step, an opening 18 is defined through the layers 17 and 16, above the field oxide 11. This etching is carried out with the assistance of an emitter mask, called the EMI mask, being shifted to the appropriate location as shown in Figure 5. The opening 18 is defined in the same manner as an opening 18' during the formation of the NPN transistors included in the same integrated circuit. This step allows the emitter 14 and collector 12 regions to be separated from each other and prevents misalignment of the masks. A layer 19 of nitride is deposited through the opening 18 and caused to adhere on the side walls of the opening. A pair of spacers 21 are formed within the emitter opening 18 over the nitride layer 19. The spacer structure 21 is self-aligned to the spacer structure formed in the NPN transistors, as shown in Figures 6 and 9. The process of this invention further includes a step of forming an N-doped polysilicon layer 22. The layer is formed at the location of the opening 18 and allowed to reach the surface of the oxide 11. A similar N-poly contact is also formed in the window 18' overlying the active areas of the NPN transistors. The polysilicon layer 22 is then contacted by a first metallization layer formed on either the emitter or the collector side. Figure 7 clearly shows the width of the base channel region, comprising a middle portion with a width W E and two opposite regions with a width Δ formed from the portion of the layer 16 that overlaps the region 11. W B > W E + 2*Δ Substituting for the real values of such distances, then: W B > 0.8 + 2*0.4 = 1.6 µm W B > 0.4 + 2*0.2 = 0.8 µm. It will be readily appreciated from the above that the process of this invention is highly beneficial in terms of reduced base channel. The results of actual tests carried out by the Applicant with the lateral PNP device 15 have confirmed the advantages of this solution. The adopted solution allows the size of the lateral PNP device described hereinabove to be reduced, thereby further improving its frequency performance. In conclusion, this lateral PNP device can be operated at high frequencies, with suitable collector current values and good amplifications, to provide a superior figure of merit compared to that typical of conventional lateral PNP devices.

Claims: A lateral PNP bipolar electronic device which is integrated monolithically on a semiconductor substrate together with other bipolar devices of the NPN type; said device being incorporated into an electrically insulated multilayer structure which comprises: the semiconductor substrate, doped with impurities of the P type; a first buried layer, doped with impurities of the N type to form a base region; a second layer (13), overlying the first buried layer and having conductivity of the N type, to form an active area; opposite collector (12) and emitter (14) regions being formed in said active area and separated by a base channel region; an oxide layer (11) being deposited above the base channel between the collector (12) and emitter (14) regions and being covered by a polysilicon layer (16) and a protective layer (17) formed on said polysilicon layer, wherein the width (Wb) of the base channel is defined by the width (We) of an opening (18) formed in said protective layer (17) and in said polysilicon layer (16), said opening (18) defined in the same manner as an emitter opening (18') of said NPN bipolar devices, and by the double width (2Δ) of the portions of said polysilicon layer (16) overlapping said oxide layer (11). A lateral PNP bipolar electronic device according to Claim 1, characterized in that a nitride layer (19) is deposited through said opening (18) and adhered to the side walls of the opening. A lateral PNP bipolar electronic device according to Claim 1, wherein a doped polysilicon layer (22) is formed within said opening (18) above said oxide layer (11). A process for fabricating a lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other bipolar devices of the NPN type, said device being incorporated to an electrically insulated multilayer structure and comprising: a semiconductor substrate, doped with impurities of the P type; a first buried layer, doped with impurities of the N type to form a base region; a second layer (13), overlying the first buried layer and having conductivity of the N type, to form an active area; opposite collector (12) and emitter (14) regions being formed in said active area and separated by a base channel region; an oxide layer (11) being deposited above the base channel between the collector (12) and emitter (14) regions and being covered by a polysilicon layer (16) and a protective layer (17) formed on said polysilicon layer, wherein the width (Wb) of the base channel is defined by the width (We) of an opening (18) formed in said protective layer (17) and in said polysilicon layer (16), said opening (18) defined in the same manner as an emitter opening (18') of said NPN bipolar devices, and by the double width (2Δ) of the portions of said polysilicon layer (16) overlapping said oxide layer (11). A process according to Claim 4, characterized in that a nitride layer (19) is deposited through said opening (18) and adhered to the sidewalls of the opening. A process according to Claim 5, characterized in that oppositely located spacers (21) are formed inside said opening (18) and adhered to said sidewalls and covering said nitride layer (19). A process according to Claim 4, characterized in that a doped polysilicon layer (22) is formed inside said opening (18) above said oxide layer (11). A process according to Claim 4, characterized in that said opening (18) is formed by using an emitter mask for the NPN transistor, shifted to an appropriate location.

Inventors: ALEMANNI CARLO, PINTO ANGELO, ALEMANNI, CARLO, PINTO, ANGELO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1997
Main classification: H01L29
IPC codes: H01L29, H01L27, H01L21