Low consumption linear voltage regulator with high supply line rejection

Abstract: A linear type of voltage regulator, having an input terminal (VBAT) adapted to receive a supply voltage thereon, and an output terminal (VOUT) adapted to deliver a regulated output voltage, comprises a power transistor (M1) and a driving circuit therefor; the driving circuit basically comprises an operational amplifier (OP) having a differential input stage biased by a bias current (Iop) which varies proportionally with the output current (Iload) of the regulator.

Description: This invention relates to a linear type of voltage regulator. Field of the Invention More particularly, the invention relates to a linear type of voltage regulator having its current consumption optimized and controlled, for use with portable battery-powered devices, e.g. cellular telephones. Typical requirements of such regulators are a high PSRR (Power Source Rejection Ratio), very fast response to load transients, low voltage drop and above all a low current consumption, so that the battery charge may last longer. Background Art These regulators are currently implemented with an N-channel MOS power transistor. The adoption of an N-channel transistor is prompted by that, for the same performance level, it allows of optimum utilization of the silicon area, as well as a reduction, of at least one order of magnitude, in the value of the output capacitor. An exemplary application of a voltage regulator according to the prior art is shown in Figure 1. A low-drop type of regulator with N-channel topology, as is that shown in Figure 1, requires that a driving circuit OP be supplied a higher voltage VCP than the power supply voltage VBAT which can be delivered, in the state-of-art, by a charge pump circuit 2. The operation of the device in the circuit of Figure 1 will now be described in detail. The current consumption of the regulator can be calculated by adding together the current I res flowing through the divider R1-R2 and the current I op drawn by the driving circuit OP for the power transistor M1. Since the charge pump circuit 2 used for powering the driving circuit OP is a by-n multiplier of the input voltage VBAT, its current draw on the battery will be n times the current I op that it supplies to the driving circuit OP. When the efficiency E FF of the charge pump circuit is also reckoned with, the overall current draw of the regulator on the battery is given as: I REG = (n/E FF ) * I OP + I res . The compensation employed with a regulator with this topology usually is of the pole-zero type, wherein the internal zero is to cancel out the pole introduced by the load capacitor. The outcome of such compensation is that a dominant pole is created, which greatly slows down the response to load transients and undermines performance in terms of power source rejection. A known solution to this problem consists of increasing the bias current I op of the differential stage in the driving circuit OP, with a consequent increase in the regulator overall consumption. However, this prior solution clashes with the basic requirement for battery-powered devices of having the lowest possible current consumption. Also known from the US Patent No. 5,548,205 to Monticelli is a voltage regulator employing a PNP output transistor of vertical construction, which operates as a linear control element in a feedback controlled circuit which is formed in a substrate. This document described a regulator comprising a differential amplifier which has one input coupled to a voltage reference and another input coupled via feedback from a resistive voltage divider connected between common and the output of the voltage regulator, as well as a parasitic NPN transistor, which is merged physically and thermally with the structure of the PNP output transistor, in order to sense the onset of output transistor saturation and re-route the majority of the excess base current drive to a feedback control node. Moreover, EP 0 892 332 relates to prior art under Art. 54(3) EPC. The underlying technical problem of this invention is to provide a linear type of voltage regulator having its current consumption optimized and controlled, with improved PSRR and faster response to load transients. The technical problem is solved by a circuit as previously indicated, and defined in the characterizing parts of Claims 1 to 7. Summary of the Invention The solvent idea behind this invention is to use a driving circuit OP for the power transistor M1 which has an input differential stage biased by a bias current that varies proportionally with the output current of the regulator. The features and advantages of a circuit according to the invention will be more clearly apparent from the following detailed description of embodiments thereof, as illustrated by way of non-limitative examples in the accompanying drawings. Brief Description of the Drawings Figure 1 shows a linear type of voltage regulating circuit according to the prior art; Figure 2 shows a linear type of voltage regulating circuit according to this invention; Figure 3 shows a first embodiment of a portion of the voltage regulating circuit of Figure 2; Figure 4 shows a second embodiment of a portion of the voltage regulating circuit of Figure 2; and Figures 5, 6 and 7 are plots of some voltage and current signals as obtained by electrical simulation of the circuit of Figure 2. Detailed Description Shown at 1 in Figure 2 is a linear type of voltage regulating circuit according to the invention. The regulating circuit 1 is connected between a battery (BATTERY), itself connected to a terminal VBAT of the circuit, and a load, itself connected to a terminal VOUT and illustrated schematically by an equivalent current generator I load in parallel with a load capacitor C load having an Equivalent Series Resistor ESR. The regulating circuit 1 includes the following circuit portions: a power transistor M1 of the N-channel MOS type having a drain-source main conduction path connected, in series with a sensing resistor (Rsense), between the terminals VBAT and VOUT of the regulating circuit 1; an operational amplifier OP, utilized as a driving circuit for the power transistor M1 and having a differential input stage biased by a given bias current I op , and having a non-inverting input terminal connected to a voltage reference Vref, an inverting input terminal coupled to the output terminal VOUT of the circuit 1 through a resistive divider R1-R2, and an output terminal connected to the gating terminal G of the power transistor M1; a charge pump circuit 2, utilized for supplying a boosted voltage VCP to the operational amplifier OP; a transconductance operational amplifier 3 having first 4 and second 5 inputs which are connected to first and second terminals, respectively, of the sensing resistor R sense . The transconductance operational amplifier 3 comprises a differential input stage 7 controlling an output current generator 8 which supplies the bias current Iop to the differential input stage of the operational amplifier OP. The operation of the circuit shown in Figure 2 will now be described. As the load current I load increases from a minimum value to a maximum value, for example, the voltage drop V sense across the sensing resistor R sense also increases, and the transconductance amplifier 3, having the voltage V sense applied to its inputs 4 and 5, generates a larger bias current I OP . Thus, the bias current of the differential input stage of the amplifier OP, driving the power transistor M1, will be the larger the larger is the load current I LOAD , thereby improving the circuit speed of response. Accordingly, the current consumption of the regulator will only increase when the regulator is to supply large currents, or when abrupt variations, or transients, occur in the load current. On the contrary, when the load current is zero or a very low value, or the current transient is over, the inputs 4 and 5 of the transconductance amplifier 3 are returned to the same potential, thereby restoring the current generator I OP to a very low quiescent current value. The solution proposed in Figure 2 has been implemented with BCD (Bipolar-CMOS-DMOS) technology. Shown in Figure 3 is a circuit diagram of a first embodiment of the transconductance operational amplifier 3 comprising bipolar transistors. The circuit 3 includes a differential input stage consisting of transistors Q1 and Q2, a reference current generator I ref , and an output current mirror Q3, Q4. From the circuit of Figure 3, it can be observed that the collector current of the transistor Q3 is given by: I CQ3 = (I ref /m) * exp((R sense *I load )/(EC*V T )) where, m is the area ratio of transistors Q1 and Q2, and EC is the emission coefficient of transistors Q1 and Q2. Therefore, the bias current I OP will be given by the following implicit equation: I OP * R1 = V T * log((p*I CQ3 )/I OP ) where, p is the area ratio of transistors Q3 and Q4. The transistor Q4 will mirror, with an appropriate gain, the current of Q3 which is, in turn, dependent on the load current I LOAD . Since this dependence is of an exponential type, a resistor R1 has been added to limit the maximum value that the current I OP is allowed to attain. By suitably selecting the two area ratii m and p of the transistor pairs Q1-Q2 and Q3-Q4, it thus becomes possible to set, to low values, the bias current I OP under no load, thereby limiting the current draw on the battery. Then, by selecting suitable dimensions for the resistor R1, the maximum value can be set for the bias current I OP which provides, under full load, the desired PSRR (Power Source Rejection Ratio) and speed of response to transients. On the other hand, where a conventional circuit such as shown in Figure 1 is used, in order to obtain a similar performance in terms of PSRR and response to load transients, a constant bias current of a larger value would be necessary, which entails a much higher overall consumption of the regulator at steady state. Where a limitation is required on the maximum current from the regulator, the layout of the transconductance amplifier of Figure 3 can be modified as illustrated by circuit 3a in Figure 4. Figure 4 shows a second embodiment of the tranconductance operational amplifier 3 of Figure 2, here denoted by the reference 3a. For values of the load current I LOAD below the upper limit, the current flowing through the transistor Q2 is smaller than the current through the transistor Q1; accordingly, the transistor M4 will be off and not affect the regulator operation. When the load current I LOAD exceeds a limiting value I LIM given by: I LIM = (V T *log(m))/R sense , m being the area ratio of transistors Q1 and Q2, the collector current of Q2 increases and turns on the transistor M4 which will drive, from the output terminal 7, the gate terminal of the power transistor M1 (node CL in Figure 2) to deliver less current. Plotted in Figure 5 is the behavior of the bias current versus variations in the load current I LOAD , as gathered by electrical simulation. It can be seen that, in the no-load condition, the bias current I OP is approximately 870 nanoamperes, and rises to 4.18 microamperes under a load current of 100 milliamperes, corresponding to the maximum value specified for the load current. Figure 5 also brings out the operation of the current limitation set at 140 milliamperes. The no-load overall consumption of the regulator is 10 microamperes, and rises to 23 microamperes under a load current of 100 milliamperes. These values were obtained using a reference current I ref of 1 microampere and a divider R1~R2 (Figure 2) dimensioned to provide a current I res of 4 microamperes. Figure 6 shows the PSRR (Power Source Rejection Ratio) obtained with the circuit of Figure 1 (curve 11) compared to that to be obtained by biasing the regulator with a fixed current of 870 nanoamperes (curve 10). Plotted in Figure 7 are patterns, as obtained by electrical simulation, of the output voltage V OUT (graph (a)) versus variations in the load current I LOAD (graph (b)). In graph (a), the run of the signal V OUT obtained when using the proposed circuit (curve 20) is shown superposed on the run of the same signal in a corresponding conventional circuit (curve 21). The smaller voltage drop of curve 20 upon abrupt variations in the load current I LOAD is apparent. It will be appreciated that this operation principle may also be used with regulators having different topologies. In summary, the advantages of this solution are: faster speed of response to transients of the differential stage of a linear regulator; low current consumption under no load or a very small load, and hence low average consumption of the regulator; high power source rejection (PSRR).

Claims: A linear type of voltage regulator, having at least one input terminal (VBAT) adapted to receive a supply voltage thereon, and one output terminal (VOUT) adapted to deliver a regulated output voltage, which voltage regulator comprises: a power transistor (M1) of the N-channel MOS type having a control terminal (G), and having a main conduction path (D-S) connected in a path between the input terminal (VBAT) and the output terminal (VOUT) of the regulator; an operational amplifier (OP) having a differential input stage biased by a bias current (Iop), and having a first input terminal connected to a voltage reference (Vref), a second input terminal coupled to the output terminal (VOUT) of the regulator, and an output terminal coupled to the control terminal (G) of the power transistor (M1); characterized in that it further comprises: a sensing resistor (Rsense) connected in series with the main conduction path (D-S) of the power transistor (M1) for sensing an output current flowing along the path between the input terminal (VBAT) and the output terminal (VOUT) of the regulator; a transconductance operational amplifier (3) having first (4) and second (5) inputs connected to first and second terminals, respectively, of the sensing resistor (Rsense) to measure the difference of potential (Vsense) across said resistor, and an output terminal delivering said bias current (Iop) which is proportional to the difference of potential (Vsense) measured across the sensing resistor (Rsense), the bias current (Iop) of the differential stage varying proportionally with the value of the output current flowing along the path between the input terminal (VBAT) and the output terminal (VOUT) of the regulator. A voltage regulator according to Claim 1, characterized in that the operational amplifier (OP) is supplied a boosted voltage (VCP) relative to the supply voltage (VBAT). A voltage regulator according to Claim 1, characterized in that the first input terminal of the operational amplifier (OP) is a non-inverting (+) input terminal, and the second input terminal is an inverting (-) input terminal coupled to the output terminal (VOUT) of the regulator through a voltage divider (R1-R2). A voltage regulator according to Claim 1, characterized in that the transconductance operational amplifier (3) includes a differential input stage (Q1, Q2) connected to the first (4) and second (5) inputs as well as to a reference current generator (I ref ) and to an output current mirror (Q3, Q4) respectively. A voltage regulator according to Claim 4, characterized in that the transconductance operational amplifier (3) further comprises a resistor (R1) connected in series with said output current mirror (Q3, Q4) in order to limit the maximum value of the output bias current (Iop). A voltage regulator according to Claim 4, characterized in that the area ratii of the differential input stage (Q1, Q2) and output current mirror (Q3, Q4) are chosen in such a way to set, to low values, the output bias current (Iop).

Inventors: CAPICI SALVATORE VINCENZO, MILAZZO PATRIZIA, PULVIRENTI FRANCESCO, CAPICI, SALVATORE VINCENZO, MILAZZO, PATRIZIA, PULVIRENTI, FRANCESCO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1997
Main classification: G05F1
IPC codes: G05F1