CMOS OUTPUT DRIVER WITH P-CHANNEL SUBSTRATE TRACKING FOR COLD SPARE CAPABILITY

Abstract: A CMOS output driver circuit (10) with p-channel substrate tracking provides an output driver to full power supply voltage (VDD). The circuit (10) is especially useful as a redundant circuit where its power supply connection (VDD) is connected to ground (VSS) and the circuit (10) is kept in unbiased storage until it is needed.

Description: CMOS OUTPUT DRIVER WITH P-CHANNEL SUBSTRATE TRACKING FOR COLD SPARE CAPABILITY BACKGROUND OF THE INVENTION The present invention relates to fault tolerant systems and particularly to a CMOS driver circuit for use as a spare or redundant circuit. In high reliability applications, e.g., spacecraft, cold spare is the condition where a spare or redundant parts power supply, V DD , is connected to ground, V ss , and kept in unbiased storage until the part is needed. The power savings from not using power while in the cold spare mode as compared to providing a warm or hot standby circuit is an important benefit of the cold spare circuit. The cold spare circuit output remains connected to an active signal or data bus while in the cold spare mode and must therefore present a high impedance to the active signal. A problem occurs where a typical CMOS output driver having a p-channel transistor drive to a high data state, i.e., V DD or V cc and an n-channel transistor drive to a low data state, i.e., V ss . Figure 1 shows a typical CMOS output driver 1 including input 2, inverter 3, node A, inverter 4, node B, p-channel transistor P10, n-channel transistor N10, power supply connection V DD , ground connection V ss , and output 5. Figure 2 shows p-channel and n-channel MOS transistor schematic pin definitions as shown in the present patent application. The design of output driver 1 prevents using the part as a cold spare if the output node 5 to a package pin remains connected to an active signal or bus. In Figure 1, if V DD is connected to V ss but output node 5 remains connected to an active signal or bus as is the common situation, as an external output driver from another part on the signal or bus pin tries to drive the signal or bus, i.e., output node 5 high, the drain (D) to substrate (B) on junction of P10 will forward bias. Its substrate is connected to V DD , which is connected to V ss , resulting in a current path to V ss . PIO is typically a very wide transistor resulting in a low impedance path to V ss . The external driver will be unable to drive the signal or bus pin to a high state thereby preventing valid operation. One proposed output driver in the past which does not use CMOS is shown in Figure 6. The circuit of Figure 6 only provides an output drive to V DD minus a bipolar junction transistor saturated VCE plus forward bias voltage drop. In addition, the circuit of Figure 6 requires a diode type device and is implemented in BiCMOS technology. Thus, a need exists for a CMOS driver circuit that provides a full CMOS output and can be used in a cold spare mode. SUMMARY OF THE INVENTION The present invention solves these and other problems by providing a CMOS driver circuit, including: a power supply connection connected to a positive voltage when the driver circuit is active and connected to ground when the driver circuit is inactive; a driver circuit input; a first inverter having an input and an output; a second inverter having an input and an output, said first inverter input and said second inverter input coupled to the driver circuit input; a first p-channel transistor having a gate, a source, a drain, and a substrate, the gate coupled to the first inverter output; a first n-channel transistor having a gate, a source, a driver, and a substrate connected to the source, the gate coupled to the second inverter output, with the first p-channel transistor and the first n-channel transistor series connected between the power supply connection and ground; a driver circuit output at the series connection, the driver circuit output connected to an external circuit when the driver circuit is active and when the driver circuit is inactive; means for maintaining the first n-channel transistor in an off condition when the driver circuit is inactive; and means for causing the gate of the first p-channel transistor to track a voltage at the external circuit when the driver circuit is inactive, thereby maintaining the first p- channel transistor in an off condition. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic of a typical CMOS output driver according to the prior art. Figure 2 is a drawing showing p-channel transistor and the n-channel transistor pin definitions. Figure 3 is a schematic drawing of an output driver circuit according to the principles of the present invention. Figure 4 is a schematic of a portion of the circuit of Figure 3. Figure 5 is a schematic drawing of an alternate embodiment of the present invention. Figure 6 is a schematic of an output driver according to the present. DETAILED DESCRIPTION OF THE PRESENT INVENTION A schematic of the preferred embodiment of the present invention is shown in Figure 3 and generally designated 10. Output driver circuit 10 includes p-channel transistors PI, P2, P3, P4, P5, P6, P7 and P8, and n-channel transistors Nl, N2, N3, N4 and N5. Circuit 10 further includes inverter 20, input 22 and output 24. In addition, circuit 10 includes nodes A, B, C, D and E. Power suppply connections shuch as V DD and ground such as V ss are shown by conventional symbols. Output driver circuit 10 has two modes of operation. The first is called normal mode operation where V DD is connected to the power supply such that the part is active and the output driver must drive the signal or bus connected to the output node high or low depending on the input state. The second is called cold spare where V DD is connected to V ss but the output node remains connected to an active signal or bus which is driven high or low by another active part. Under this condition, the output node of the cold spare part must present a high impedance condition for any voltage level on the output node. Normal Mode Operation (V DD is connected to the power supplies of driver circuit 10): The gate of P2 is connected to V DD and therefore an inversion region will not form and the MOS conducting mechanism remains off. The source and substrate of P2 are connected to the output node 24 but since P2 is off and its drain (node C) is at V ss , the substrate/drain pn junction remains reverse biased and output node 24 remains isolated from node C. The gate of N2 is connected to V DD and therefore N2 remains on. This forces node C to V ss which keeps N3 off. Therefore P2, N2 and N3 have no affect on output driver operation in normal mode. These transistors do affect P4 and P7 operation but, as will be explained below, P4 and P7 have no affect on output driver operation therefore the statement remains valid. The gate of P3 and the gate of P6 are at V DD keeping these MOS transistors off. The substrates, P3 drain and P6 source are connected together. P3 and P6 are then equivalent to back to back diodes as shown in figure 4. For any combination of output node 24 and node A voltage there will be a reverse biased pn junction and output node 24 remains isolated from node A. Therefore P3 and P6 have no affect on output driver operation in normal mode. The gate of N5 is connected to V DD and therefore remains on. The gate of P4 is connected to node C, which is held at V ss , and therefore it will turn on if its source and substrate are high. The source of P4 is at V DD and the substrate is connected to the drain. The source/substrate pn junction is forward biased, resulting in the substrate being at V DD minus a diode forward bias voltage drop (Vfd). Vfd is approximately 0.7 volts. With the substrate at V DD minus Vfd, P4 will operate normally and therefore remains on driving node D and the substrate of P4 to V DD . With P4 and N5 both continuously on, P5 and N4 function as an inverter. The substrate of PI is connected to P7 and P8. The gate of P7 is connected to node C which is held at V ss and its source/substrate pn junction is forward biased resulting in the substrate to be at V DD -Vfd resulting in P7 being turned on and driving node E and the substrate of P7 to V DD . The gate of P8 is at V DD and its source and substrate are connected to node E which is also at V DD , therefore, P8 remains off and its drain/substrate pn junction remains reverse biased for any voltage between V ss and V D D on the output node therefore it has no affect on output driver operation in normal mode. With node E at V DD , the substrate of PI is at V DD and it will operate properly. Based on the above operation description, the circuit of Figure 3 in normal mode is equivalent to the circuit of Figure 1. Cold Spare Mode Operation (V DD is connected to V ss of driver circuit 10): When V DD is connected to V ss , all circuitry becomes inactive. Internal nodes which were at V DD are immediately discharged through the p-channel transistor's drain/substrate pn junction to a Vfd voltage level. Over time, pn junction leakage currents will eventually discharge the node from Vfd to V ss but since this could take a long time relative to circuit operating cycle times, it is assumed that all internal nodes are at Vfd unless actively driven to another voltage. In Figure 3, Nl must remain off. To ensure this, the gate, source and substrate of N 1 must remain at V ss . Under these conditions N 1 will remain off and the drain/substrate pn junction will remain reverse biased as the output node is driven between high and low. The source and substrate of Nl are directly connected to V ss . The gate of Nl could be at Vfd which can be higher than the n-channel threshold voltage (Vtn) resulting in a situation where Nl may be weakly turned on resulting in a current path to V ss if the external signal or bus is being driven high. The Vfd voltage can be left over from V DD going from a high to V ss for power down or the voltage can be imposed from capacitive coupling between the drain of Nl (output node 24) and the gate of Nl (node B) which induces node B to exceed V ss when the output node goes high. The p-channel drain to substrate diode, however, would clamp the rise at Vfd. With V DD connected to V ss , N2 remains off. With the source and substrate of P2 connected to the output node, P2 turns on if the output node voltage exceeds the p- channel threshold voltage (Vtp) and node C voltage will then track the output node voltage. With N2 off, there is no current path to V ss . Thus, when the output node voltage goes high, node C also goes high turning N3 on. When N3 is turned on it actively drives the gate of Nl to V ss , thereby ensuring that Nl stays off when the output node goes high. PI also must remain off. To ensure this, its gate voltage must track its drain voltage and the source must remain at V ss . The source of PI is directly connected to VSS (via V DD being connected to V ss ) and its substrate is connected to P7 and P8. P3 and P6 allow the node A voltage to track the output node voltage. The substrate of P3 is connected to the drain but the source/substrate pn junction is forward biased if the output node goes high resulting in the substrate to be at the output voltage (Vout) minus Vfd. With the substrate at Vout-Vfd and its gate at V ss , P3 will turn on as Vout goes high driving the source and substrate of P6 high. The gate of P6 is connected to V ss and therefore it also turns on thereby causing the voltage at node A to increase as Vout increases. With the gate of PI tracking the output voltage, PI stays off when output node 24 goes high. As output node 24 goes high, the drain/substrate pn junction of PI is forward biased, driving node E high but the substrate/source pn junction remains reverse biased thereby preventing PI from being a discharge path to V ss . As the node A voltage increases there must be no current paths to V ss . The gate of N4 could be at Vfd resulting in a weakly on device, however, the gate of N5 is at V ss keeping it off, thereby preventing this path from being a discharge path to V ss for node A. The gate of P5 is at V ss or Vfd and if node A is high its drain/substrate pn junction will forward bias creating a conducting path between its drain and source. Since P5 is on, node D voltage increases with the node A voltage resulting in an increase of the drain and substrate of P4. However, the gate of P4 tracks the output node voltage which means it also tracks the node A voltage thereby keeping P4 off. Its substrate/source pn junction remains reverse biased thereby preventing this path from being a discharge path to V ss for node A. The gate of P7 is connected to node C which also tracks the output node. As node E goes high, P7 remains off and its substrate/source pn junction remains reverse biased thereby preventing this path from being a discharge path to V ss . The gate of P8 is at V ss and its source and substrate are at V DD -Vfd, therefore it turns on as the output node goes high. This then shorts the substrate of PI to the output node, resulting in the node E voltage being equal to output node 24 voltage if node 24 voltage is equal to or greater than Vfd or Vtp. P8 may not be necessary for proper cold spare operation. It depends on whether the substrate of PI can be left floating or not. In some technologies and environment conditions the substrate must be electrically connected to either the source or drain in order to prevent the lateral B JT created by the source/substrate/drain pnp structure from turning on. P8 effectively shorts the base to the emitter, eliminating the possibility of base current since the base/emitter (i.e., substrate/drain) pn junction is not permitted to forward bias. The present invention provides an output drive to V DD instead of V DD minus a BJT saturated VCE plus forward bias diode voltage drop. A high output voltage level (VOH) at V DD offers the advantage of satisfying CMOS level output voltage requirements (VOH=V DD -0.1 V at IOH=-20μA, VOL=V SS +0.1 V at IOL=20μA). Also, A VOH=V DD allows complete turn off of the p-channel transistors in the signal receiving circuit. By turning off the p-channel transistors, crowbar current, i.e., current that flows from V DD to V ss through transistors, can be eliminated, thereby reducing power. This is achieved in the present invention, strictly using only p-channel and n- channel transistors. No bipolar junction transistors (BJT) or diode devices are required and therefore it can be implemented in a pure CMOS technology; a BiCMOS type of technology is not required to implement the present invention. Based on the above description, when the Figure 3 schematic is in cold storage (V DD connected to V ss ), there are no current paths between the cold spare part's V DD /V SS pins and the externally driven signal or bus output node for any voltage. An alternative embodiment for P3 and P6 in Figure 2 for driver circuit 10 is shown in Figure 5. The only difference between Figures 3 and 5 is the substrate connection for P3 and P6. In Figure 5, the substrate of P3 is connected to its source instead of its drain and the substrate of P6 is connected to its drain instead of its source. The operation descriptions for Figure 3 remain valid for Figure 5. The invention is to be limited by the appended claims rather than the foregoing description.

Claims: CLAIMS I claim: 1. A CMOS driver circuit, comprising: a power supply connection, said power supply connection connected to a positive voltage when said driver circuit is active, said power supply connection connected to ground when said driver circuit is inactive; a driver circuit input; a first inverter having an input and an output; a second inverter having an input and an output, said first inverter input and said second inverter input coupled to said driver circuit input; a first p-channel transistor having a gate a source a drain and a substrate, said gate coupled to said first inverter output; a first n-channel transistor having a gate, a source, a drain, and a substrate connected to said source, said gate coupled to said second inverter output, with said first p-channel transistor and said first n-channel transistor series connected between said power suppply connection and ground; a driver circuit output at said series connection, said driver circuit output connected to an external circuit when said driver circuit is active and when said driver circuit is inactive; means for maintaining said first n-channel transistor in an off condition when said driver circuit is inactive; and means for causing said gate of said first p-channel transistor to track a voltage at said external circuit when said driver circuit is inactive, thereby maintaining said first p- channel transistor in an off condition. 2. A method for operating a CMOS driver circuit having a power supply connection, said power supply connection connected to a positive voltage when said driver circuit is active, said power supply connection connected to ground when said driver circuit is inactive; providing a driver circuit input; providing a first inverter having an input and an output; providing a second inverter having an input and an output, said first inverter input and said second inverter input coupled to said driver circuit input; providing a first p-channel transistor having a gate a source a drain and a substrate, said gate coupled to said first inverter output; providing a first n-channel transistor having a gate, a source, a drain, and a substrate connected to said source, said gate coupled to said second inverter output, with said first p-channel transistor and said first n-channel transistor series connected between said power suppply connection and ground; providing a driver circuit output at said series connection, said driver circuit output connected to an external circuit when said driver circuit is active and when said driver circuit is inactive; maintaining said first n-channel transistor in an off condition when said driver circuit is inactive; and causing said gate of said first p-channel transistor to track a voltage at said external circuit when said driver circuit is inactive, thereby maintaining said first p- channel transistor in an off condition.

Inventors: GOLKE KEITH W, GOLKE, KEITH, W.
Applicants: HONEYWELL INC, HONEYWELL INC.
Application year: 1997
Main classification: H03K19
IPC codes: H03K19